WO2020168634A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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Publication number
WO2020168634A1
WO2020168634A1 PCT/CN2019/084915 CN2019084915W WO2020168634A1 WO 2020168634 A1 WO2020168634 A1 WO 2020168634A1 CN 2019084915 W CN2019084915 W CN 2019084915W WO 2020168634 A1 WO2020168634 A1 WO 2020168634A1
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WIPO (PCT)
Prior art keywords
display area
area
display
array substrate
notch
Prior art date
Application number
PCT/CN2019/084915
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English (en)
French (fr)
Inventor
卢延涛
刘广辉
王超
Original Assignee
武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/496,687 priority Critical patent/US11233021B2/en
Publication of WO2020168634A1 publication Critical patent/WO2020168634A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2825—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere in household appliances or professional audio/video equipment
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133305—Flexible substrates, e.g. plastics, organic film
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0651—Function
    • H01L2224/06515—Bonding areas having different functions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate, a display panel and a display device.
  • Chip On Film (COF) technology in the lower frame of the display screen to reduce the width of the lower frame is one of the methods to achieve a high screen-to-body ratio of the display screen.
  • COF Chip On Film
  • the vertical distance between the bonding area of the chip-on-film and the display area of the display is too large, resulting in a narrow bezel and a high screen ratio. Becomes difficult.
  • the purpose of the present application is to provide an array substrate, a display panel, and a display device.
  • the array substrate facilitates the display panel and the display device to achieve a narrow frame and a high screen-to-body ratio.
  • An array substrate the array substrate includes a substrate, the substrate has a display area and a non-display area adjacent to the display area, and the non-display area of the substrate has a first A notch, a binding area is provided on the first edge of the display area of the first notch close to the substrate.
  • the first gap divides an end of the non-display area of the substrate away from the display area into a first non-display area and a second non-display area.
  • the array substrate further includes a test pad and a silver glue coating area, and the test pad and the silver glue coating area are both disposed in the first non-display area and/or the second non-display area. In the non-display area, the test pad and the silver glue coating area are arranged staggered.
  • the length of the binding area in the first direction is less than or equal to the length of the first notch in the first direction, and the first direction and the non-display area point to all directions.
  • the direction of the display area is vertical.
  • the array substrate further includes a plurality of input pads arranged along the first direction and arranged at equal intervals in the binding area and the extension area, and each of the input pads is located on the first side.
  • the ratio of the upward length to the length of each input pad in the second direction ranges from 1/3 to 100, and the second direction is the direction in which the non-display area points to the display area.
  • the first non-display area and the second non-display area have the same length in a first direction, and the first direction is perpendicular to the direction in which the non-display area points to the display area.
  • the array substrate further includes a chip-on-chip film that is bound to the binding area and passes through the first gap to be bent until the substrate faces away from the display area Side.
  • a display panel includes an array substrate, the array substrate includes a substrate, the substrate has a display area and a non-display area adjacent to the display area, and the non-display area of the substrate is far from all One end of the display area has a first notch, and a binding area is provided on the first edge of the display area of the first notch close to the substrate.
  • the first notch divides an end of the non-display area of the substrate away from the display area into a first non-display area and a second non-display area.
  • the array substrate further includes a test pad and a silver glue coating area, and the test pad and the silver glue coating area are both disposed in the first non-display area and/or the second non-display area. In the non-display area, the test pad and the silver glue coating area are arranged staggered.
  • the length of the binding area in the first direction is less than or equal to the length of the first gap in the first direction, and the first direction and the non-display area point to the same direction.
  • the direction of the display area is vertical.
  • the array substrate further includes a plurality of input pads arranged along the first direction and arranged at equal intervals in the binding area, and the length of each input pad in the first direction is equal to The ratio of the length of each of the input pads in the second direction ranges from 1/3 to 100, and the second direction is the direction in which the non-display area points to the display area.
  • the first non-display area and the second non-display area have the same length along a first direction, and the first direction is perpendicular to the direction in which the non-display area points to the display area.
  • the array substrate further includes a chip on film, the chip on film is bound to the bonding area and passes through the first gap to be bent until the substrate faces away from the display area Side.
  • a display device includes the above-mentioned display panel and a backlight module, and the backlight module has a second notch at a position corresponding to the first notch of the display panel.
  • the vertical projection of the display panel on the backlight module is located in the backlight module.
  • the display panel further includes a chip-on-chip film, the chip-on-chip film sequentially passes through the first notch and the second notch to bend until the backlight module faces away from the display panel Side.
  • the bending apex of the chip on film is located in the second notch.
  • the value range of the ratio of the vertical distance from the bending apex of the chip on film to the first edge in the second direction to the length of the first notch in the second direction is 0.8 -1.2
  • the second direction is a direction in which the non-display area points to the display area.
  • the present application provides an array substrate, a display panel, and a display device.
  • a first gap is provided at the end of the non-display area of the array substrate away from the display area, and a binding area is provided at the first edge of the first gap near the display area to reduce the size.
  • the vertical distance between the binding area and the display area reduces the frame of the array substrate, so that the display device and the display panel composed of the array substrate have a narrow frame and a high screen ratio.
  • FIG. 1 is a schematic diagram of a first structure of an array substrate according to an embodiment of the application
  • FIG. 2 is a schematic diagram of a second structure of an array substrate according to an embodiment of the application.
  • FIG. 3 is a schematic diagram of a third structure of an array substrate according to an embodiment of the application.
  • FIG. 4 is a schematic diagram of the first structure in which an input pad is provided in the binding area in FIG. 2;
  • FIG. 5 is a schematic diagram of a second structure in which an input pad is provided in the binding area in FIG. 2;
  • FIG. 6 is a schematic diagram of the first structure of a display panel according to an embodiment of the application.
  • FIG. 7 is a schematic diagram of the first structure of a display device according to an embodiment of the application.
  • FIG. 8 is a cross-sectional view taken along the line A-A of the display device shown in FIG. 7;
  • FIG. 9 is a schematic diagram of the structure of the flip chip film bent from the display panel side to the back of the backlight module in the conventional technology
  • FIG. 10 is a schematic diagram of a second structure of a display device according to an embodiment of the application.
  • 10 substrate 100 display area; 101 non-display area; 101a first gap; 1021 first edge;
  • 101b binding area 101c first non-display area; 101d second non-display area; 101e silver glue coating area;
  • FIG. 1 is a schematic diagram of the first structure of an array substrate according to an embodiment of the application.
  • the array substrate includes a substrate 10 having a display area 100 and a non-display area 101.
  • Scan lines and data lines that intersect vertically are arranged in the display area 100, and thin film transistors are arranged in the areas enclosed by two adjacent scan lines and two adjacent data.
  • the scan lines and the thin film transistor (not shown)
  • the gate is connected to input a scan signal
  • the data line is connected to the source of the thin film transistor to input a data signal.
  • the non-display area 101 of the substrate has a first notch 101 a at one end away from the display area 100.
  • the first edge 1021 of the first notch 101a close to the display area 100 of the substrate 10 is provided with a binding area 101b.
  • the binding area 101b By arranging the binding area 101b at the first edge 1021, the vertical distance between the display area 100 and the binding area 101b is reduced, thereby reducing the frame of the array substrate, and making the non-display area 101 in the second direction (the non-display area 101 points In the direction of the display area 100, the space for arranging circuit devices other than wiring increases.
  • the shape of the first notch 101a is rectangular.
  • the first notch 101a divides the end of the non-display area 101 of the substrate 10 away from the display area 100 into a first non-display area 101c and a second non-display area 101d.
  • the first non-display area 101c and the second non-display area 101d are respectively located on both sides of the first notch 101a.
  • the first non-display area 101c and the second non-display area 101d have the same length in the first direction, so that the wires extending from the end of the display area 100 close to the non-display area 101 to the bonding area 101b can be routed uniformly, and the array substrate
  • the finished display panel has a symmetrical appearance.
  • the array substrate further includes a cell test pad (Cell test pad) 1011, a silver glue coating area (Ag glue pad) 101e.
  • Cell test pad Cell test pad
  • Ag glue pad Ag glue pad
  • a test signal is input to the test pad 1011 to perform a performance test on the display panel.
  • the silver glue coating area 101e is used to coat conductive silver glue, and the conductive silver glue is used to connect the ground wire (not shown) in the non-display area 101 of the array substrate and the color film substrate in the display panel opposite to the array substrate.
  • the array substrate further includes an identification mark 1012 arranged in the first non-display area 101c or the second non-display area 101d, and the identification mark 1012 is used to record related information of the array substrate.
  • the test pad 1011, the silver glue coating area 101e, and the identification mark 1012 are arranged in the same row in the first non-display area 101c and the second non-display area 101d.
  • the array substrate further includes a plurality of wires extending from an end of the display area 100 close to the non-display area 101 to the bonding area 101b.
  • the wiring includes a first wiring 1013 connected to the data line and a second wiring 1014 connected to the peripheral wiring.
  • the multiple second traces 1014 are located on both sides of the multiple first traces 1013.
  • the array substrate further includes a chip on film 1015, which includes a flexible substrate and a control chip (not shown) provided on the flexible substrate.
  • the control chip outputs signals to the second wiring 1014 so that the gate driving circuit (Gate On Array) outputs scan signals to the scan lines, and the control chip outputs signals to the first wiring 1013 to make the data lines input data signals.
  • the chip on film 1015 is bound to the bonding area 101b and passes through the first notch 101a to be bent to the side of the substrate 10 facing away from the display area 100.
  • the first notch 101a provides a accommodating space for the bending section of the chip on film 1015 so as to further narrow the lower frame of the array substrate.
  • FIG. 2 is a schematic diagram of the second structure of the array substrate according to the embodiment of the application.
  • the difference from the first structural schematic diagram is that the test pad 1011 and the silver glue coating area 101e can both be arranged in the first non-display area 101c and/or the second non-display area 101d, the test pad 1011 and the silver glue coating area 101e are arranged in a staggered arrangement, so that the space occupied by the first non-display area 101c and the second non-display area 101d in the first direction is reduced, so that the length of the first notch 101a in the first direction is increased.
  • the direction in which the display area 101 points to the display area 100 is perpendicular.
  • the array substrate also includes an identification mark and a short-circuit ring (not shown).
  • the identification mark 1012 and the short-circuit ring are all arranged in the non-display area 101.
  • the identification mark 1012, the short-circuit ring, the silver glue coating area 101e and the test pad 1011 are in the first Staggered in the direction.
  • the test pad 1011 and the silver paste coating area 101e may also be located in the first non-display area 101c and the second non-display area 101d, respectively.
  • the test pad 1011 includes a plurality of test pads 1011. They are staggered in the first non-display area 101c.
  • the length of the binding area 101b in the first direction is less than or equal to the length of the first gap 101a in the first direction. Specifically, the length of the binding area 101b in the first direction is equal to the length of the first gap 101a in the first direction to maximize the space available in the first direction of the input pad provided in the binding area 101b.
  • the distance between two adjacent traces in the first direction is greater than 1.5 microns.
  • the included angle between the first trace and the first direction is greater than the included angle between the second trace and the first direction.
  • FIG. 3 is a schematic diagram of the third structure of the array substrate according to the embodiment of the application.
  • the difference from the array substrate shown in FIG. 2 is that the first notch 101a is a trapezoid.
  • the first notch 101a is a trapezoid with a narrow upper and a wide bottom, so that the space of the first notch 101a is larger, which is more conducive to the array.
  • the substrate is manufactured into a narrow frame display device.
  • FIG. 4 is a schematic diagram of a first structure in which the binding area 101b in FIG. 2 is provided with an input pad 1016.
  • Each input pad 1016 is strip-shaped and the same, and the ratio of the length d1 of each input pad 1016 in the first direction to the length L1 of each input pad 1016 in the second direction ranges from 1/20-1 /5.
  • the length d1 of each input pad 1016 in the first direction ranges from 5 microns to 100 microns, and the length L1 of each input pad 1016 in the second direction ranges from 100 microns to 500 microns.
  • the area of the input pad 1016 is not less than 500 square microns.
  • the distance between two adjacent input pads 1016 in the first direction is greater than 5 microns.
  • the binding area 101b in FIG. 2 has an increased length in the first direction relative to the binding area 101b in FIG. 1, the distance between two adjacent traces in the first direction in FIG. 2 is relative to that in FIG. The distance between two adjacent traces in the first direction is increased to avoid contact between two adjacent traces while reducing the space occupied by the traces in the second direction, that is, the binding area 101b to the display area 100 The distance is further reduced, and the lower frame of the array substrate is further narrowed.
  • the increase in the length of the binding area 101b in FIG. 2 in the first direction relative to the binding area 101b in FIG. 1 increases the space that each input pad 1016 can use in the first direction. By adding each input pad 1016
  • the length in the first direction increases the area of each input pad, which can increase the contact area between the chip on film 1015 and the input pad 1016 and improve the bonding yield.
  • FIG. 5 is a schematic diagram of a second structure in which the input pad 1016 is provided in the binding area 101b in FIG.
  • the difference from the input pad shown in FIG. 4 is that the shape of each input pad 1016 is flat and wide. Specifically, the ratio of the length d1 of each input pad 1016 in the first direction to the length L2 of each input pad 1016 in the second direction ranges from 1/3-100. Further, the ratio of the length d1 of each input pad 1016 in the first direction to the length L2 of each input pad 1016 in the second direction ranges from 1/3-20.
  • the area of each input pad 1016 is not less than 500 square microns.
  • the length of each input pad 1016 in FIG. 5 increases in the first direction and decreases in the second direction. The reduction in the length of each input pad 1016 in the second direction reduces the space occupied by the binding area 101b in the second direction.
  • the present application also provides a display panel, which may be a liquid crystal display panel or an organic light emitting diode display panel.
  • the display panel includes the above-mentioned array substrate.
  • FIG. 6 is a schematic diagram of the first structure of the display panel according to the embodiment of the present application.
  • the display panel includes an array substrate 11 and a color filter substrate 20.
  • the array substrate 11 and the color filter substrate 20 are connected by a sealant, and a step area is formed between the array substrate 11 and the color filter substrate 20, and the step area is the non-display area 101 of the aforementioned array substrate.
  • One end of the step area away from the color filter substrate 20 has a first notch.
  • the first notch is close to the first edge 1021 of the color filter substrate 20 and is provided with a binding area.
  • the chip-on-chip film 1015 is bound to the binding area on the array substrate 11.
  • the crystal film 1015 passes through the first notch on the array substrate 10 to be bent to the side of the array substrate 11 facing away from the color filter substrate 20.
  • a first notch is provided at one end of the non-display area of the array substrate away from the display area, and the first notch is close to the first edge of the display area of the array substrate to provide a binding area to reduce the vertical distance from the binding area to the display area.
  • FIG. 7 is a schematic diagram of the first structure of the display device according to the embodiment of the present application.
  • the display device includes a display panel 100 and a backlight module 200.
  • the display panel 100 includes the above-mentioned array substrate and a color filter substrate.
  • the step area formed by the array substrate and the color filter substrate is provided with a first notch 101a, the first notch 101a is rectangular, and the first notch 101a is located at an end of the step area away from the color filter substrate.
  • the step area is the non-display area 101 in the aforementioned array substrate.
  • a binding area is provided on the first edge 1021 of the first notch 101a close to the display area of the array substrate.
  • the backlight module 200 provides a light source for the display panel 100 and is located on the back of the light-emitting surface of the display panel 100.
  • the backlight module 200 has a second notch 102a at a position corresponding to the first notch 101a of the display panel 100.
  • the shape of the second notch 102a is the same as that of the first notch 101a, that is, the second notch 102a is rectangular. In other structural diagrams of the display device, the shape of the second notch 102a may also be different from the first notch 101a.
  • the vertical projection of the display panel 100 on the backlight module 200 is located in the backlight module 200 so that the backlight module 200 can protect the display panel 100.
  • the display panel 100 further includes a chip on film 1015, and the chip on film 1015 is bound to the bonding area.
  • FIG. 8 is a cross-sectional view taken along the line A-A of the display device shown in FIG. 7.
  • the chip on film 1015 passes through the first notch 101a and the second notch 102a in sequence to be bent to the side of the backlight module 200 facing away from the display panel 100.
  • FIG. 9 it is a schematic diagram of the structure in which the chip on film is bent from the display panel 100 to the backside of the backlight module 200 in the conventional technology. The bending of the chip on film will increase the distance D of the lower frame of the display device.
  • the chip-on-chip film 1015 occupies space within the first gap 101a and the second gap 102a or partially outside the second gap 102a due to the bending in the second direction, so that the size of the lower frame of the display device of the present application is relatively In the conventional technology, the lower frame of the display device is reduced.
  • the bending vertex B of the chip on film 1015 is located in the second notch 102a to further reduce the overall size of the display device, thereby achieving a narrow frame and high screen-to-body ratio.
  • the bending vertex B of the chip on film 1015 is at The point on the bending section of the chip-on-film in the second direction that has the largest vertical distance from the second edge 2001.
  • the second edge 2001 is the edge of the second notch 102a close to the display area of the display panel 100.
  • the display area of the display panel 100 is The display area of the above-mentioned array substrate.
  • the ratio of the vertical distance D1 from the bending vertex B of the chip-on-chip film 1015 to the first edge 1021 in the second direction to the length D2 of the first notch 101a in the second direction ranges from 0.8 to 1.2.
  • the first edge 1021 is an edge of the first notch 101 a close to the display area of the display panel 100.
  • FIG. 10 is a schematic diagram of the second structure of the display device according to the embodiment of the present application.
  • the difference from the display device shown in FIG. 8 is that the first notch 101a and the second notch 102a are both trapezoidal, and the first notch 101a and the second notch 102a are both trapezoidal, so that the size of the backlight module 200 is larger than the size of the display panel 100
  • the contact area of the chip on film 1015 and the bonding area on the display panel 100 is larger.
  • a first notch is provided at one end of the non-display area of the array substrate away from the display area, and the first notch is close to the first edge of the display area of the array substrate to provide a binding area to reduce the vertical distance from the binding area to the display area.
  • a second notch at the position of the backlight module corresponding to the first notch of the array substrate to reduce the narrow frame of the display device and increase the screen-to-body ratio, so that the flip-chip film bound to the bonding area sequentially passes through the first notch And the second gap to further reduce the frame of the display device and increase the screen-to-body ratio.

Abstract

一种阵列基板、显示面板及显示装置，阵列基板包括基板（10），基板（10）具有显示区（100）及与显示区（100）相邻的非显示区（101），基板（10）的非显示区（101）远离显示区（100）的一端具有第一缺口（101a），第一缺口（101a）靠近基板（10）的显示区（100）的第一边缘（1021）设置有绑定区（101b）。显示装置具有窄边框以及高屏占比。

Description

阵列基板、显示面板及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板、显示面板及显示装置。
 背景技术
随着高屏占比的显示屏越来越受欢迎，高屏占比的显示屏成为研究热点。
目前，在显示屏下边框采用覆晶薄膜（Chip On film，COF）技术以缩小下边框宽度是实现显示屏具有高屏占比的方法之一。然而，将覆晶薄膜绑定于下边框的绑定区时，用于绑定覆晶薄膜的绑定区到显示屏的显示区的垂直距离过大会导致显示屏实现窄边框以及高屏占比变得困难。
因此，有必要提出一种技术方案以解决绑定区到显示屏的显示区的垂直距离过大而导致显示屏难以实现窄边框以及高屏占比的问题。
 技术问题
本申请的目的在于提供一种阵列基板、显示面板以及显示装置，该阵列基板有利于显示面板以及显示装置实现窄边框及高屏占比。
 技术解决方案
一种阵列基板，所述阵列基板包括基板，所述基板具有显示区及与所述显示区相邻的非显示区，所述基板的所述非显示区远离所述显示区的一端具有第一缺口，所述第一缺口靠近所述基板的所述显示区的第一边缘设置有绑定区。
在上述阵列基板中，所述第一缺口将所述基板的所述非显示区远离所述显示区的一端分为第一非显示区和第二非显示区。
在上述阵列基板中，所述阵列基板还包括测试垫及银胶涂布区，所述测试垫和所述银胶涂布区均设置于所述第一非显示区和/或所述第二非显示区，所述测试垫和所述银胶涂布区交错排列。
在上述阵列基板中，所述绑定区在所述第一方向上的长度小于或等于所述第一缺口沿所述第一方向的长度，所述第一方向与所述非显示区指向所述显示区的方向垂直。
在上述阵列基板中，所述阵列基板还包括多个沿所述第一方向排列且等间隔设置于所述绑定区和所述延伸区的输入垫，每个所述输入垫在第一方向上的长度与每个所述输入垫在第二方向上的长度的比值的取值范围为1/3-100，所述第二方向为所述非显示区指向所述显示区的方向。
在上述阵列基板中，所述第一非显示区和所述第二非显示区沿第一方向的长度相同，所述第一方向与所述非显示区指向所述显示区的方向垂直。
在上述阵列基板中，所述阵列基板还包括覆晶薄膜，所述覆晶薄膜绑定于所述绑定区并穿过所述第一缺口以弯折至所述基板背向所述显示区的一侧。
一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括基板，所述基板具有显示区及与所述显示区相邻的非显示区，所述基板的所述非显示区远离所述显示区的一端具有第一缺口，所述第一缺口靠近所述基板的所述显示区的第一边缘设置有绑定区。
在上述显示面板中，所述第一缺口将所述基板的所述非显示区远离所述显示区的一端分为第一非显示区和第二非显示区。
在上述显示面板中，所述阵列基板还包括测试垫以及银胶涂布区，所述测试垫与所述银胶涂布区均设置于所述第一非显示区和/或所述第二非显示区，所述测试垫和所述银胶涂布区交错排列。
在上述显示面板中，所述绑定区在所述第一方向上的长度小于或等于所述第一缺口沿所述第一方向的长度，所述第一方向与所述非显示区指向所述显示区的方向垂直。
在上述显示面板中，所述阵列基板还包括多个沿所述第一方向排列且等间隔设置于所述绑定区的输入垫，每个所述输入垫在第一方向上的长度与每个所述输入垫在第二方向上的长度的比值的取值范围为1/3-100，所述第二方向为所述非显示区指向所述显示区的方向。
在上述显示面板中，所述第一非显示区和所述第二非显示区沿第一方向的长度相同，所述第一方向与所述非显示区指向所述显示区的方向垂直。
在上述显示面板中，所述阵列基板还包括覆晶薄膜，所述覆晶薄膜绑定于所述绑定区并穿过所述第一缺口以弯折至所述基板背向所述显示区的一侧。
一种显示装置，所述显示装置包括上述显示面板及背光模组，所述背光模组对应所述显示面板的所述第一缺口的位置具有第二缺口。
在上述显示装置中，所述显示面板在所述背光模组上的垂直投影位于所述背光模组内。
在上述显示装置中，所述显示面板还包括覆晶薄膜，所述覆晶薄膜依次穿过所述第一缺口和所述第二缺口以弯折至所述背光模组背向所述显示面板的一侧。
在上述显示装置中，所述覆晶薄膜的弯折顶点位于所述第二缺口内。
在上述显示装置中，所述覆晶薄膜的弯折顶点在第二方向上到所述第一边缘的垂直距离与所述第一缺口在第二方向上的长度的比值的取值范围为0.8-1.2，所述第二方向为所述非显示区指向所述显示区的方向。
 有益效果
本申请提供一种阵列基板、显示面板及显示装置，通过在阵列基板的非显示区远离显示区的一端设置第一缺口，并在第一缺口靠近显示区的第一边缘设置绑定区以缩小绑定区与显示区之间的垂直距离从而减小阵列基板的边框，使阵列基板组成的显示装置以及显示面板具有窄边框以及高屏占比。
 附图说明
图1为本申请实施例阵列基板的第一结构示意图；
图2为本申请实施例阵列基板的第二结构示意图；
图3为本申请实施例阵列基板的第三种结构示意图；
图4为图2中绑定区中设置输入垫的第一种结构示意图；
图5为图2中绑定区中设置输入垫的第二种结构示意图；
图6为本申请实施例显示面板的第一种结构示意图；
图7为本申请实施例显示装置的第一种结构示意图；
图8为沿图7所示显示装置切线A-A的剖面图；
图9为传统技术中覆晶薄膜从显示面板侧弯折至背光模组背面的结构示意图；
图10为本申请实施例显示装置的第二种结构示意图。
附图标识如下：
10 基板；100 显示区；  101非显示区； 101a第一缺口； 1021第一边缘；
101b绑定区；101c 第一非显示区； 101d 第二非显示区； 101e 银胶涂布区；
1011 测试垫；1012识别标识；1013 第一走线； 1014 第二走线；
1015覆晶薄膜；1016输入垫；11阵列基板；
20彩膜基板；100显示面板； 200背光模组；102a第二缺口；2001第二边缘。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1，其为本申请实施例阵列基板的第一种结构示意图。阵列基板包括基板10，基板10具有显示区100和非显示区101。
显示区100中设置垂直相交的扫描线和数据线，相邻的两条扫描线和相邻的两条数据围合的区域中均设置有薄膜晶体管，扫描线与薄膜晶体管（未示出）的栅极连接以输入扫描信号，数据线与薄膜晶体管的源极连接以输入数据信号。
基板的非显示区101远离显示区100的一端具有第一缺口101a。第一缺口101a靠近基板10的显示区100的第一边缘1021设置有绑定区101b。通过将绑定区101b设置于第一边缘1021使得显示区100到绑定区101b的垂直距离减小从而减小阵列基板的边框，且使得非显示区101在第二方向（非显示区101指向显示区100的方向）上用于设置走线以外的电路器件的空间增加。
第一缺口101a的形状为矩形。第一缺口101a将基板10的非显示区101远离显示区100的一端分为第一非显示区101c和第二非显示区101d。第一非显示区101c和第二非显示区101d分别位于第一缺口101a的两侧。第一非显示区101c和第二非显示区101d沿第一方向的长度相同，使得从显示区100靠近非显示区101一端延伸至绑定区101b的走线能均匀地布线，且使得阵列基板制成的显示面板具有对称的外观。
阵列基板还包括测试垫（Cell test pad）1011、银胶涂布区（Ag glue pad ）101e。测试垫1011用于阵列基板进一步制备成显示面板后，通过对测试垫1011输入测试信号以对显示面板进行性能测试。银胶涂布区101e用于涂布导电银胶，导电银胶用于连接阵列基板非显示区101中的接地线（未示出）和显示面板中与阵列基板对置的彩膜基板中的导电层以起到防静电（Electro-static discharge，ESD）作用。阵列基板还包括设置于第一非显示区101c或第二非显示区101d中的识别标识1012，识别标识1012用于记录阵列基板的相关信息。测试垫1011、银胶涂布区101e以及识别标识1012同排设置于第一非显示区101c和第二非显示区101d。
阵列基板还包括多条从显示区100靠近非显示区101的一端延伸至绑定区101b的走线。走线包括与数据线连接的第一走线1013以及与外围走线连接的第二走线1014。多条第二走线1014位于多条第一走线1013的两侧。
阵列基板还包括覆晶薄膜1015，覆晶薄膜1015包括柔性衬底以及设置柔性衬底上的控制芯片（未示出）。控制芯片输出信号至第二走线1014以使栅极驱动电路（Gate On Array）输出扫描信号至扫描线，控制芯片输出信号至第一走线1013以使数据线输入数据信号。覆晶薄膜1015绑定于绑定区101b并穿过第一缺口101a以弯折至基板10背向显示区100的一侧。第一缺口101a为覆晶薄膜1015的弯折段提供容纳空间从而使得阵列基板的下边框进一步变窄。
请参阅图2，其为本申请实施例阵列基板的第二种结构示意图。与第一种结构示意图不同之处在于，测试垫1011以及银胶涂布区101e可以均设置于第一非显示区101c和/或第二非显示区101d，测试垫1011与银胶涂布区101e交错排列，以使得第一非显示区101c和第二非显示区101d在第一方向上占用的空间减小，从而使得第一缺口101a在第一方向上的长度增加，第一方向与非显示区101指向显示区100的方向垂直。阵列基板还包括识别标识以及短路环（未示出）等，识别标识1012以及短路环均设置于非显示区101，识别标识1012、短路环、银胶涂布区101e以及测试垫1011在第一方向上交错排列。在阵列基板的其他结构示意图中，测试垫1011以及银胶涂布区101e也可以分别位于第一非显示区101c和第二非显示区101d中，测试垫1011包括多个，多个测试垫1011交错排列在第一非显示区101c中。
绑定区101b在第一方向上的长度小于或等于第一缺口101a在第一方向上的长度。具体地，绑定区101b在第一方向上的长度等于第一缺口101a在第一方向上的长度以使设置于绑定区中101b的输入垫在第一方向上可利用的空间最大。
相邻两条走线在第一方向上的间距大于1.5微米。第一走线与第一方向的夹角大于第二走线与第一方向的夹角。
请参阅图3，其为本申请实施例阵列基板的第三种结构示意图。与图2所示阵列基板不同之处在于，第一缺口101a为梯形，在第二方向上，第一缺口101a为上窄下宽的梯形使得第一缺口101a的空间更大，更有利于阵列基板制造成窄边框的显示装置。
请参阅图4，其为图2中的绑定区101b设置输入垫1016的第一种结构示意图。每个输入垫1016均为条形且相同，每个输入垫1016在第一方向的长度d1与每个输入垫1016在第二方向上的长度L1的比值的取值范围为1/20-1/5。每个输入垫1016在第一方向上的长度d1的取值范围为5微米-100微米，每个输入垫1016在第二方向上的长度L1的取值范围为100微米-500微米，每个输入垫1016的面积不小于500平方微米。相邻两个输入垫1016在第一方向上的间距大于5微米。
由于图2中的绑定区101b相对于图1中的绑定区101b在第一方向上的长度增加，图2中相邻两个走线在第一方向上的间距相对于图1中相邻两个走线在第一方向的间距增加，避免相邻两个走线之间接触的同时，使得走线在第二方向上占用的空间减小，即使得绑定区101b到显示区100的距离进一步地减小，阵列基板的下边框进一步变窄。图2中的绑定区101b相对于图1中的绑定区101b在第一方向上的长度增加使得每个输入垫1016在第一方向可以利用的空间增大，通过增加每个输入垫1016在第一方向上的长度使每个输入垫的面积增大，可以使覆晶薄膜1015与输入垫1016接触的面积变大而提高绑定良率。
请参阅图5，其为图2中绑定区101b中设置输入垫1016的第二种结构示意图。与图4所示输入垫不同之处在于，每个输入垫1016的形状为扁宽形。具体地，每个输入垫1016在第一方向上的长度d1与每个输入垫1016在第二方向上的长度L2的比值的取值范围为1/3-100。进一步地，每个输入垫1016在第一方向上的长度d1与每个输入垫1016在第二方向上的长度L2的比值的取值范围为1/3-20。每个输入垫1016的面积不小于500平方微米。相对于图4中的输入垫1016，图5中的每个输入垫1016在第一方向上的长度增加且在第二方向的长度减小。每个输入垫1016在第二方向上的长度减小使得绑定区101b在第二方向上占用的空间减小。
本申请还提供一种显示面板，显示面板可以为液晶显示面板，也可以为有机发光二极管显示面板。显示面板包括上述阵列基板。
请参阅图6，其为本申请实施例显示面板的第一种结构示意图。显示面板包括阵列基板11和彩膜基板20。阵列基板11和彩膜基板20通过封框胶连接，阵列基板11和彩膜基板20之间形成台阶区，台阶区即上述阵列基板的非显示区101。台阶区远离彩膜基板20的一端具有第一缺口，第一缺口靠近彩膜基板20的第一边缘1021设置有绑定区，覆晶薄膜1015绑定于阵列基板11上的绑定区，覆晶薄膜1015穿过阵列基板10上的第一缺口以弯折至阵列基板11背向彩膜基板20的一侧。
本申请显示面板通过在阵列基板的非显示区远离显示区的一端设置第一缺口，第一缺口靠近阵列基板的显示区的第一边缘设置绑定区以缩小绑定区到显示区的垂直距离从而减小显示面板的下边框，且使得显示面板的台阶区在台阶区指向显示区方向上用于设置走线以外电路器件的空间增加。
请参阅图7，其为本申请实施例显示装置的第一种结构示意图。显示装置包括显示面板100和背光模组200。
显示面板100包括上述阵列基板以及彩膜基板，阵列基板与彩膜基板形成的台阶区设置有第一缺口101a，第一缺口101a为矩形，第一缺口101a位于台阶区远离彩膜基板的一端，台阶区为上述阵列基板中的非显示区101。第一缺口101a靠近阵列基板的显示区的第一边缘1021上设置有绑定区。
背光模组200为显示面板100提供光源，其位于显示面板100发光面的背面。背光模组200对应显示面板100的第一缺口101a的位置具有第二缺口102a。第二缺口102a的形状与第一缺口101a相同，即第二缺口102a为矩形，在显示装置的其他结构示意图中，第二缺口102a的形状也可以与第一缺口101a不同。显示面板100在背光模组200上的垂直投影位于背光模组200内以使背光模组200起到保护显示面板100的作用。
显示面板100上还包括覆晶薄膜1015，覆晶薄膜1015绑定于绑定区。
请参阅图8，其为沿图7所示显示装置切线A-A的剖面图。覆晶薄膜1015依次穿过第一缺口101a和第二缺口102a以弯折至背光模组200背向显示面板100的一侧。如图9所示，其为传统技术中覆晶薄膜从显示面板100弯折至背光模组200的背面的结构示意图，由于覆晶薄膜弯折时会导致显示装置的下边框增加距离D。而在本申请中，覆晶薄膜1015由于弯折在第二方向上占用空间位于第一缺口101a和第二缺口102a内或部分位于第二缺口102a外，使得本申请显示装置的下边框尺寸相对于传统技术中的显示装置下边框减小。
进一步地，覆晶薄膜1015的弯折顶点B位于第二缺口102a内以进一步地减小显示装置的整体尺寸，从而实现窄边框和高屏占比，覆晶薄膜1015的弯折顶点B为在第二方向上覆晶薄膜的弯折段上离第二边缘2001垂直距离最大的点，第二边缘2001为第二缺口102a上靠近显示面板100的显示区的边缘，显示面板100的显示区为上述阵列基板的显示区。
进一步地，覆晶薄膜1015的弯折顶点B在第二方向上到第一边缘1021的垂直距离D1与第一缺口101a在第二方向上的长度D2的比值的取值范围为0.8-1.2，第一边缘1021为第一缺口101a上靠近显示面板100的显示区的边缘。
请参阅图10，其为本申请实施例显示装置的第二种结构示意图。与图8所示显示装置不同之处在于，第一缺口101a和第二缺口102a均为梯形，第一缺口101a和第二缺口102a均为梯形使得背光模组200的尺寸大于显示面板100的尺寸以对显示面板100进行保护时，覆晶薄膜1015与显示面板100上的绑定区接触面积更大。
本申请显示装置通过在阵列基板的非显示区远离显示区的一端设置第一缺口，第一缺口靠近阵列基板的显示区的第一边缘设置绑定区以缩小绑定区到显示区的垂直距离，并在背光模组对应阵列基板的第一缺口的位置设置第二缺口，以降低显示装置的窄边框并提高屏占比，使绑定于绑定区的覆晶薄膜依次穿过第一缺口和第二缺口以进一步地降低显示装置的边框并提高屏占比。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (19)

  1. 一种阵列基板，其中，所述阵列基板包括基板，所述基板具有显示区及与所述显示区相邻的非显示区，所述基板的所述非显示区远离所述显示区的一端具有第一缺口，所述第一缺口靠近所述基板的所述显示区的第一边缘设置有绑定区。
  2. 根据权利要求1所述的阵列基板，其中，所述第一缺口将所述基板的所述非显示区远离所述显示区的一端分为第一非显示区和第二非显示区。
  3. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括测试垫以及银胶涂布区，所述测试垫与所述银胶涂布区均设置于所述第一非显示区和/或所述第二非显示区，所述测试垫和所述银胶涂布区交错排列。
  4. 根据权利要求3所述的阵列基板，其中，所述绑定区在所述第一方向上的长度小于或等于所述第一缺口沿所述第一方向的长度，所述第一方向与所述非显示区指向所述显示区的方向垂直。
  5. 根据权利要求4所述的阵列基板，其中，所述阵列基板还包括多个沿所述第一方向排列且等间隔设置于所述绑定区的输入垫，每个所述输入垫在第一方向上的长度与每个所述输入垫在第二方向上的长度的比值的取值范围为1/3-100，所述第二方向为所述非显示区指向所述显示区的方向。
  6. 根据权利要求2所述的阵列基板，其中，所述第一非显示区和所述第二非显示区沿第一方向的长度相同，所述第一方向与所述非显示区指向所述显示区的方向垂直。
  7. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括覆晶薄膜，所述覆晶薄膜绑定于所述绑定区并穿过所述第一缺口以弯折至所述基板背向所述显示区的一侧。
  8. 一种显示面板，其中，所述显示面板包括阵列基板，所述阵列基板包括基板，所述基板具有显示区及与所述显示区相邻的非显示区，所述基板的所述非显示区远离所述显示区的一端具有第一缺口，所述第一缺口靠近所述基板的所述显示区的第一边缘设置有绑定区。
  9. 根据权利要求8所述的显示面板，其中，所述第一缺口将所述基板的所述非显示区远离所述显示区的一端分为第一非显示区和第二非显示区。
  10. 根据权利要求9所述的显示面板，其中，所述阵列基板还包括测试垫以及银胶涂布区，所述测试垫与所述银胶涂布区均设置于所述第一非显示区和/或所述第二非显示区，所述测试垫和所述银胶涂布区交错排列。
  11. 根据权利要求10所述的显示面板，其中，所述绑定区在所述第一方向上的长度小于或等于所述第一缺口沿所述第一方向的长度，所述第一方向与所述非显示区指向所述显示区的方向垂直。
  12. 根据权利要求11所述的显示面板，其中，所述阵列基板还包括多个沿所述第一方向排列且等间隔设置于所述绑定区的输入垫，每个所述输入垫在第一方向上的长度与每个所述输入垫在第二方向上的长度的比值的取值范围为1/3-100，所述第二方向为所述非显示区指向所述显示区的方向。
  13. 根据权利要求9所述的显示面板，其中， 所述第一非显示区和所述第二非显示区沿第一方向的长度相同，所述第一方向与所述非显示区指向所述显示区的方向垂直。
  14. 根据权利要求8所述的显示面板，其中，所述阵列基板还包括覆晶薄膜，所述覆晶薄膜绑定于所述绑定区并穿过所述第一缺口以弯折至所述基板背向所述显示区的一侧。
  15. 一种显示装置，其中，所述显示装置包括权利要求8所述的显示面板及背光模组，所述背光模组对应所述显示面板的所述第一缺口的位置具有第二缺口。
  16. 根据权利要求15所述的显示装置，其中，所述显示面板在所述背光模组上的垂直投影位于所述背光模组内。
  17. 根据权利要求15所述的显示装置，其中，所述显示面板还包括覆晶薄膜，所述覆晶薄膜依次穿过所述第一缺口和所述第二缺口以弯折至所述背光模组背向所述显示面板的一侧。
  18. 根据权利要求17所述的显示装置，其中，所述覆晶薄膜的弯折顶点位于所述第二缺口内。
  19. 根据权利要求18所述的显示装置，其中，所述覆晶薄膜的弯折顶点在第二方向上到所述第一边缘的垂直距离与所述第一缺口在第二方向上的长度的比值的取值范围为0.8-1.2，所述第二方向为所述非显示区指向所述显示区的方向。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN205231068U (zh) * 2015-12-28 2016-05-11 昆山维信诺科技有限公司 Oled显示面板结构
US20160219706A1 (en) * 2015-01-22 2016-07-28 Samsung Display Co., Ltd. Display device
CN107765919A (zh) * 2017-10-25 2018-03-06 武汉天马微电子有限公司 一种触控显示面板及显示装置
CN108447396A (zh) * 2018-02-26 2018-08-24 上海天马微电子有限公司 显示装置
CN108761627A (zh) * 2018-05-22 2018-11-06 武汉华星光电技术有限公司 异形屏面板
CN108845445A (zh) * 2018-08-24 2018-11-20 武汉华星光电技术有限公司 全面显示屏及采用该全面显示屏的显示装置

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101340667B1 (ko) * 2007-02-13 2013-12-11 엘지디스플레이 주식회사 액정 표시장치의 제조방법
KR102248876B1 (ko) * 2014-12-24 2021-05-07 엘지디스플레이 주식회사 표시장치 어레이 기판 및 표시장치
CN106817451B (zh) * 2017-02-23 2020-02-18 京东方科技集团股份有限公司 一种移动终端触控显示结构及其制造方法、移动终端
CN107123388A (zh) * 2017-06-29 2017-09-01 厦门天马微电子有限公司 一种阵列基板及显示装置
CN113281930B (zh) * 2017-06-30 2022-08-12 厦门天马微电子有限公司 显示屏及显示装置
JP7002908B2 (ja) * 2017-10-13 2022-01-20 株式会社ジャパンディスプレイ 表示装置
CN107643638B (zh) * 2017-10-18 2020-05-15 厦门天马微电子有限公司 阵列基板和显示面板
CN107634072B (zh) * 2017-10-25 2020-04-03 厦门天马微电子有限公司 阵列基板及显示面板
CN108427228B (zh) * 2018-02-24 2021-03-16 武汉天马微电子有限公司 背光模组与显示装置
CN108376518B (zh) * 2018-02-26 2021-07-16 厦门天马微电子有限公司 显示面板和显示装置
CN108416280B (zh) * 2018-02-26 2021-09-17 厦门天马微电子有限公司 显示模组和显示装置
KR102587861B1 (ko) * 2018-03-27 2023-10-12 삼성디스플레이 주식회사 표시 장치 및 이의 제조 방법
CN108281089B (zh) * 2018-03-29 2020-04-24 上海天马微电子有限公司 柔性显示面板和柔性显示装置
US20210028270A1 (en) * 2018-03-30 2021-01-28 Sharp Kabushiki Kaisha Display device
US10546912B2 (en) * 2018-04-19 2020-01-28 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Display panel and display device
US11081059B2 (en) * 2018-05-03 2021-08-03 Kunshan Go-Visionox Opto-Electronics Co., Ltd. Display panels and display devices
US10783825B2 (en) * 2018-05-14 2020-09-22 Kunshan Go-Visionox Opto-Electronics Co., Ltd. Driving substrates and display panels
US10608022B2 (en) * 2018-05-14 2020-03-31 Kunshan Go-Visionox Opto-Electronics Co., Ltd. Array substrates, display devices and methods of manufacturing array substrates
CN108777114B (zh) * 2018-06-26 2021-05-14 上海中航光电子有限公司 显示面板及其制造方法、显示装置和拼接屏
CN109188809B (zh) * 2018-09-30 2021-09-17 武汉天马微电子有限公司 显示面板和显示装置
CN109410761B (zh) * 2018-10-30 2021-04-30 武汉天马微电子有限公司 显示面板和显示装置
CN109410772B (zh) * 2018-10-31 2021-02-09 武汉天马微电子有限公司 显示面板和显示装置
CN109188747B (zh) * 2018-11-27 2021-05-14 厦门天马微电子有限公司 显示面板和显示装置
CN209674154U (zh) * 2019-02-22 2019-11-22 武汉华星光电技术有限公司 阵列基板、显示面板及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160219706A1 (en) * 2015-01-22 2016-07-28 Samsung Display Co., Ltd. Display device
CN205231068U (zh) * 2015-12-28 2016-05-11 昆山维信诺科技有限公司 Oled显示面板结构
CN107765919A (zh) * 2017-10-25 2018-03-06 武汉天马微电子有限公司 一种触控显示面板及显示装置
CN108447396A (zh) * 2018-02-26 2018-08-24 上海天马微电子有限公司 显示装置
CN108761627A (zh) * 2018-05-22 2018-11-06 武汉华星光电技术有限公司 异形屏面板
CN108845445A (zh) * 2018-08-24 2018-11-20 武汉华星光电技术有限公司 全面显示屏及采用该全面显示屏的显示装置

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