WO2020168634A1 - Substrat de réseau, panneau d'affichage et dispositif d'affichage - Google Patents

Substrat de réseau, panneau d'affichage et dispositif d'affichage Download PDF

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Publication number
WO2020168634A1
WO2020168634A1 PCT/CN2019/084915 CN2019084915W WO2020168634A1 WO 2020168634 A1 WO2020168634 A1 WO 2020168634A1 CN 2019084915 W CN2019084915 W CN 2019084915W WO 2020168634 A1 WO2020168634 A1 WO 2020168634A1
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WO
WIPO (PCT)
Prior art keywords
display area
area
display
array substrate
notch
Prior art date
Application number
PCT/CN2019/084915
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English (en)
Chinese (zh)
Inventor
卢延涛
刘广辉
王超
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/496,687 priority Critical patent/US11233021B2/en
Publication of WO2020168634A1 publication Critical patent/WO2020168634A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2825—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere in household appliances or professional audio/video equipment
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133305—Flexible substrates, e.g. plastics, organic film
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0651—Function
    • H01L2224/06515—Bonding areas having different functions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate, a display panel and a display device.
  • Chip On Film (COF) technology in the lower frame of the display screen to reduce the width of the lower frame is one of the methods to achieve a high screen-to-body ratio of the display screen.
  • COF Chip On Film
  • the vertical distance between the bonding area of the chip-on-film and the display area of the display is too large, resulting in a narrow bezel and a high screen ratio. Becomes difficult.
  • the purpose of the present application is to provide an array substrate, a display panel, and a display device.
  • the array substrate facilitates the display panel and the display device to achieve a narrow frame and a high screen-to-body ratio.
  • An array substrate the array substrate includes a substrate, the substrate has a display area and a non-display area adjacent to the display area, and the non-display area of the substrate has a first A notch, a binding area is provided on the first edge of the display area of the first notch close to the substrate.
  • the first gap divides an end of the non-display area of the substrate away from the display area into a first non-display area and a second non-display area.
  • the array substrate further includes a test pad and a silver glue coating area, and the test pad and the silver glue coating area are both disposed in the first non-display area and/or the second non-display area. In the non-display area, the test pad and the silver glue coating area are arranged staggered.
  • the length of the binding area in the first direction is less than or equal to the length of the first notch in the first direction, and the first direction and the non-display area point to all directions.
  • the direction of the display area is vertical.
  • the array substrate further includes a plurality of input pads arranged along the first direction and arranged at equal intervals in the binding area and the extension area, and each of the input pads is located on the first side.
  • the ratio of the upward length to the length of each input pad in the second direction ranges from 1/3 to 100, and the second direction is the direction in which the non-display area points to the display area.
  • the first non-display area and the second non-display area have the same length in a first direction, and the first direction is perpendicular to the direction in which the non-display area points to the display area.
  • the array substrate further includes a chip-on-chip film that is bound to the binding area and passes through the first gap to be bent until the substrate faces away from the display area Side.
  • a display panel includes an array substrate, the array substrate includes a substrate, the substrate has a display area and a non-display area adjacent to the display area, and the non-display area of the substrate is far from all One end of the display area has a first notch, and a binding area is provided on the first edge of the display area of the first notch close to the substrate.
  • the first notch divides an end of the non-display area of the substrate away from the display area into a first non-display area and a second non-display area.
  • the array substrate further includes a test pad and a silver glue coating area, and the test pad and the silver glue coating area are both disposed in the first non-display area and/or the second non-display area. In the non-display area, the test pad and the silver glue coating area are arranged staggered.
  • the length of the binding area in the first direction is less than or equal to the length of the first gap in the first direction, and the first direction and the non-display area point to the same direction.
  • the direction of the display area is vertical.
  • the array substrate further includes a plurality of input pads arranged along the first direction and arranged at equal intervals in the binding area, and the length of each input pad in the first direction is equal to The ratio of the length of each of the input pads in the second direction ranges from 1/3 to 100, and the second direction is the direction in which the non-display area points to the display area.
  • the first non-display area and the second non-display area have the same length along a first direction, and the first direction is perpendicular to the direction in which the non-display area points to the display area.
  • the array substrate further includes a chip on film, the chip on film is bound to the bonding area and passes through the first gap to be bent until the substrate faces away from the display area Side.
  • a display device includes the above-mentioned display panel and a backlight module, and the backlight module has a second notch at a position corresponding to the first notch of the display panel.
  • the vertical projection of the display panel on the backlight module is located in the backlight module.
  • the display panel further includes a chip-on-chip film, the chip-on-chip film sequentially passes through the first notch and the second notch to bend until the backlight module faces away from the display panel Side.
  • the bending apex of the chip on film is located in the second notch.
  • the value range of the ratio of the vertical distance from the bending apex of the chip on film to the first edge in the second direction to the length of the first notch in the second direction is 0.8 -1.2
  • the second direction is a direction in which the non-display area points to the display area.
  • the present application provides an array substrate, a display panel, and a display device.
  • a first gap is provided at the end of the non-display area of the array substrate away from the display area, and a binding area is provided at the first edge of the first gap near the display area to reduce the size.
  • the vertical distance between the binding area and the display area reduces the frame of the array substrate, so that the display device and the display panel composed of the array substrate have a narrow frame and a high screen ratio.
  • FIG. 1 is a schematic diagram of a first structure of an array substrate according to an embodiment of the application
  • FIG. 2 is a schematic diagram of a second structure of an array substrate according to an embodiment of the application.
  • FIG. 3 is a schematic diagram of a third structure of an array substrate according to an embodiment of the application.
  • FIG. 4 is a schematic diagram of the first structure in which an input pad is provided in the binding area in FIG. 2;
  • FIG. 5 is a schematic diagram of a second structure in which an input pad is provided in the binding area in FIG. 2;
  • FIG. 6 is a schematic diagram of the first structure of a display panel according to an embodiment of the application.
  • FIG. 7 is a schematic diagram of the first structure of a display device according to an embodiment of the application.
  • FIG. 8 is a cross-sectional view taken along the line A-A of the display device shown in FIG. 7;
  • FIG. 9 is a schematic diagram of the structure of the flip chip film bent from the display panel side to the back of the backlight module in the conventional technology
  • FIG. 10 is a schematic diagram of a second structure of a display device according to an embodiment of the application.
  • 10 substrate 100 display area; 101 non-display area; 101a first gap; 1021 first edge;
  • 101b binding area 101c first non-display area; 101d second non-display area; 101e silver glue coating area;
  • FIG. 1 is a schematic diagram of the first structure of an array substrate according to an embodiment of the application.
  • the array substrate includes a substrate 10 having a display area 100 and a non-display area 101.
  • Scan lines and data lines that intersect vertically are arranged in the display area 100, and thin film transistors are arranged in the areas enclosed by two adjacent scan lines and two adjacent data.
  • the scan lines and the thin film transistor (not shown)
  • the gate is connected to input a scan signal
  • the data line is connected to the source of the thin film transistor to input a data signal.
  • the non-display area 101 of the substrate has a first notch 101 a at one end away from the display area 100.
  • the first edge 1021 of the first notch 101a close to the display area 100 of the substrate 10 is provided with a binding area 101b.
  • the binding area 101b By arranging the binding area 101b at the first edge 1021, the vertical distance between the display area 100 and the binding area 101b is reduced, thereby reducing the frame of the array substrate, and making the non-display area 101 in the second direction (the non-display area 101 points In the direction of the display area 100, the space for arranging circuit devices other than wiring increases.
  • the shape of the first notch 101a is rectangular.
  • the first notch 101a divides the end of the non-display area 101 of the substrate 10 away from the display area 100 into a first non-display area 101c and a second non-display area 101d.
  • the first non-display area 101c and the second non-display area 101d are respectively located on both sides of the first notch 101a.
  • the first non-display area 101c and the second non-display area 101d have the same length in the first direction, so that the wires extending from the end of the display area 100 close to the non-display area 101 to the bonding area 101b can be routed uniformly, and the array substrate
  • the finished display panel has a symmetrical appearance.
  • the array substrate further includes a cell test pad (Cell test pad) 1011, a silver glue coating area (Ag glue pad) 101e.
  • Cell test pad Cell test pad
  • Ag glue pad Ag glue pad
  • a test signal is input to the test pad 1011 to perform a performance test on the display panel.
  • the silver glue coating area 101e is used to coat conductive silver glue, and the conductive silver glue is used to connect the ground wire (not shown) in the non-display area 101 of the array substrate and the color film substrate in the display panel opposite to the array substrate.
  • the array substrate further includes an identification mark 1012 arranged in the first non-display area 101c or the second non-display area 101d, and the identification mark 1012 is used to record related information of the array substrate.
  • the test pad 1011, the silver glue coating area 101e, and the identification mark 1012 are arranged in the same row in the first non-display area 101c and the second non-display area 101d.
  • the array substrate further includes a plurality of wires extending from an end of the display area 100 close to the non-display area 101 to the bonding area 101b.
  • the wiring includes a first wiring 1013 connected to the data line and a second wiring 1014 connected to the peripheral wiring.
  • the multiple second traces 1014 are located on both sides of the multiple first traces 1013.
  • the array substrate further includes a chip on film 1015, which includes a flexible substrate and a control chip (not shown) provided on the flexible substrate.
  • the control chip outputs signals to the second wiring 1014 so that the gate driving circuit (Gate On Array) outputs scan signals to the scan lines, and the control chip outputs signals to the first wiring 1013 to make the data lines input data signals.
  • the chip on film 1015 is bound to the bonding area 101b and passes through the first notch 101a to be bent to the side of the substrate 10 facing away from the display area 100.
  • the first notch 101a provides a accommodating space for the bending section of the chip on film 1015 so as to further narrow the lower frame of the array substrate.
  • FIG. 2 is a schematic diagram of the second structure of the array substrate according to the embodiment of the application.
  • the difference from the first structural schematic diagram is that the test pad 1011 and the silver glue coating area 101e can both be arranged in the first non-display area 101c and/or the second non-display area 101d, the test pad 1011 and the silver glue coating area 101e are arranged in a staggered arrangement, so that the space occupied by the first non-display area 101c and the second non-display area 101d in the first direction is reduced, so that the length of the first notch 101a in the first direction is increased.
  • the direction in which the display area 101 points to the display area 100 is perpendicular.
  • the array substrate also includes an identification mark and a short-circuit ring (not shown).
  • the identification mark 1012 and the short-circuit ring are all arranged in the non-display area 101.
  • the identification mark 1012, the short-circuit ring, the silver glue coating area 101e and the test pad 1011 are in the first Staggered in the direction.
  • the test pad 1011 and the silver paste coating area 101e may also be located in the first non-display area 101c and the second non-display area 101d, respectively.
  • the test pad 1011 includes a plurality of test pads 1011. They are staggered in the first non-display area 101c.
  • the length of the binding area 101b in the first direction is less than or equal to the length of the first gap 101a in the first direction. Specifically, the length of the binding area 101b in the first direction is equal to the length of the first gap 101a in the first direction to maximize the space available in the first direction of the input pad provided in the binding area 101b.
  • the distance between two adjacent traces in the first direction is greater than 1.5 microns.
  • the included angle between the first trace and the first direction is greater than the included angle between the second trace and the first direction.
  • FIG. 3 is a schematic diagram of the third structure of the array substrate according to the embodiment of the application.
  • the difference from the array substrate shown in FIG. 2 is that the first notch 101a is a trapezoid.
  • the first notch 101a is a trapezoid with a narrow upper and a wide bottom, so that the space of the first notch 101a is larger, which is more conducive to the array.
  • the substrate is manufactured into a narrow frame display device.
  • FIG. 4 is a schematic diagram of a first structure in which the binding area 101b in FIG. 2 is provided with an input pad 1016.
  • Each input pad 1016 is strip-shaped and the same, and the ratio of the length d1 of each input pad 1016 in the first direction to the length L1 of each input pad 1016 in the second direction ranges from 1/20-1 /5.
  • the length d1 of each input pad 1016 in the first direction ranges from 5 microns to 100 microns, and the length L1 of each input pad 1016 in the second direction ranges from 100 microns to 500 microns.
  • the area of the input pad 1016 is not less than 500 square microns.
  • the distance between two adjacent input pads 1016 in the first direction is greater than 5 microns.
  • the binding area 101b in FIG. 2 has an increased length in the first direction relative to the binding area 101b in FIG. 1, the distance between two adjacent traces in the first direction in FIG. 2 is relative to that in FIG. The distance between two adjacent traces in the first direction is increased to avoid contact between two adjacent traces while reducing the space occupied by the traces in the second direction, that is, the binding area 101b to the display area 100 The distance is further reduced, and the lower frame of the array substrate is further narrowed.
  • the increase in the length of the binding area 101b in FIG. 2 in the first direction relative to the binding area 101b in FIG. 1 increases the space that each input pad 1016 can use in the first direction. By adding each input pad 1016
  • the length in the first direction increases the area of each input pad, which can increase the contact area between the chip on film 1015 and the input pad 1016 and improve the bonding yield.
  • FIG. 5 is a schematic diagram of a second structure in which the input pad 1016 is provided in the binding area 101b in FIG.
  • the difference from the input pad shown in FIG. 4 is that the shape of each input pad 1016 is flat and wide. Specifically, the ratio of the length d1 of each input pad 1016 in the first direction to the length L2 of each input pad 1016 in the second direction ranges from 1/3-100. Further, the ratio of the length d1 of each input pad 1016 in the first direction to the length L2 of each input pad 1016 in the second direction ranges from 1/3-20.
  • the area of each input pad 1016 is not less than 500 square microns.
  • the length of each input pad 1016 in FIG. 5 increases in the first direction and decreases in the second direction. The reduction in the length of each input pad 1016 in the second direction reduces the space occupied by the binding area 101b in the second direction.
  • the present application also provides a display panel, which may be a liquid crystal display panel or an organic light emitting diode display panel.
  • the display panel includes the above-mentioned array substrate.
  • FIG. 6 is a schematic diagram of the first structure of the display panel according to the embodiment of the present application.
  • the display panel includes an array substrate 11 and a color filter substrate 20.
  • the array substrate 11 and the color filter substrate 20 are connected by a sealant, and a step area is formed between the array substrate 11 and the color filter substrate 20, and the step area is the non-display area 101 of the aforementioned array substrate.
  • One end of the step area away from the color filter substrate 20 has a first notch.
  • the first notch is close to the first edge 1021 of the color filter substrate 20 and is provided with a binding area.
  • the chip-on-chip film 1015 is bound to the binding area on the array substrate 11.
  • the crystal film 1015 passes through the first notch on the array substrate 10 to be bent to the side of the array substrate 11 facing away from the color filter substrate 20.
  • a first notch is provided at one end of the non-display area of the array substrate away from the display area, and the first notch is close to the first edge of the display area of the array substrate to provide a binding area to reduce the vertical distance from the binding area to the display area.
  • FIG. 7 is a schematic diagram of the first structure of the display device according to the embodiment of the present application.
  • the display device includes a display panel 100 and a backlight module 200.
  • the display panel 100 includes the above-mentioned array substrate and a color filter substrate.
  • the step area formed by the array substrate and the color filter substrate is provided with a first notch 101a, the first notch 101a is rectangular, and the first notch 101a is located at an end of the step area away from the color filter substrate.
  • the step area is the non-display area 101 in the aforementioned array substrate.
  • a binding area is provided on the first edge 1021 of the first notch 101a close to the display area of the array substrate.
  • the backlight module 200 provides a light source for the display panel 100 and is located on the back of the light-emitting surface of the display panel 100.
  • the backlight module 200 has a second notch 102a at a position corresponding to the first notch 101a of the display panel 100.
  • the shape of the second notch 102a is the same as that of the first notch 101a, that is, the second notch 102a is rectangular. In other structural diagrams of the display device, the shape of the second notch 102a may also be different from the first notch 101a.
  • the vertical projection of the display panel 100 on the backlight module 200 is located in the backlight module 200 so that the backlight module 200 can protect the display panel 100.
  • the display panel 100 further includes a chip on film 1015, and the chip on film 1015 is bound to the bonding area.
  • FIG. 8 is a cross-sectional view taken along the line A-A of the display device shown in FIG. 7.
  • the chip on film 1015 passes through the first notch 101a and the second notch 102a in sequence to be bent to the side of the backlight module 200 facing away from the display panel 100.
  • FIG. 9 it is a schematic diagram of the structure in which the chip on film is bent from the display panel 100 to the backside of the backlight module 200 in the conventional technology. The bending of the chip on film will increase the distance D of the lower frame of the display device.
  • the chip-on-chip film 1015 occupies space within the first gap 101a and the second gap 102a or partially outside the second gap 102a due to the bending in the second direction, so that the size of the lower frame of the display device of the present application is relatively In the conventional technology, the lower frame of the display device is reduced.
  • the bending vertex B of the chip on film 1015 is located in the second notch 102a to further reduce the overall size of the display device, thereby achieving a narrow frame and high screen-to-body ratio.
  • the bending vertex B of the chip on film 1015 is at The point on the bending section of the chip-on-film in the second direction that has the largest vertical distance from the second edge 2001.
  • the second edge 2001 is the edge of the second notch 102a close to the display area of the display panel 100.
  • the display area of the display panel 100 is The display area of the above-mentioned array substrate.
  • the ratio of the vertical distance D1 from the bending vertex B of the chip-on-chip film 1015 to the first edge 1021 in the second direction to the length D2 of the first notch 101a in the second direction ranges from 0.8 to 1.2.
  • the first edge 1021 is an edge of the first notch 101 a close to the display area of the display panel 100.
  • FIG. 10 is a schematic diagram of the second structure of the display device according to the embodiment of the present application.
  • the difference from the display device shown in FIG. 8 is that the first notch 101a and the second notch 102a are both trapezoidal, and the first notch 101a and the second notch 102a are both trapezoidal, so that the size of the backlight module 200 is larger than the size of the display panel 100
  • the contact area of the chip on film 1015 and the bonding area on the display panel 100 is larger.
  • a first notch is provided at one end of the non-display area of the array substrate away from the display area, and the first notch is close to the first edge of the display area of the array substrate to provide a binding area to reduce the vertical distance from the binding area to the display area.
  • a second notch at the position of the backlight module corresponding to the first notch of the array substrate to reduce the narrow frame of the display device and increase the screen-to-body ratio, so that the flip-chip film bound to the bonding area sequentially passes through the first notch And the second gap to further reduce the frame of the display device and increase the screen-to-body ratio.

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Abstract

L'invention concerne un substrat de réseau, un écran d'affichage et un dispositif d'affichage. Le substrat de réseau comprend un substrat (10), le substrat (10) étant pourvu d'une zone d'affichage (100) et d'une zone de non affichage (101) adjacente à la zone d'affichage (100); le substrat (10) étant pourvu d'une première encoche (101a) à une extrémité, éloignée de la zone d'affichage (100), de la zone de non affichage (101) correspondante ; et une zone de liaison (101b) disposée au niveau d'un premier bord (1021), à proximité de la zone d'affichage (100) du substrat (10), de la première encoche (101a). Le dispositif d'affichage a un pourtour étroit et un rapport écran-corps élevé.
PCT/CN2019/084915 2019-02-22 2019-04-29 Substrat de réseau, panneau d'affichage et dispositif d'affichage WO2020168634A1 (fr)

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CN201910133852.0A CN109725447B (zh) 2019-02-22 2019-02-22 阵列基板、显示面板及显示装置

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US11233021B2 (en) 2022-01-25
CN109725447A (zh) 2019-05-07
US20200279820A1 (en) 2020-09-03

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