CN202839596U - 半导体元件 - Google Patents

半导体元件 Download PDF

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CN202839596U
CN202839596U CN2012204690271U CN201220469027U CN202839596U CN 202839596 U CN202839596 U CN 202839596U CN 2012204690271 U CN2012204690271 U CN 2012204690271U CN 201220469027 U CN201220469027 U CN 201220469027U CN 202839596 U CN202839596 U CN 202839596U
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semiconductor element
reduced
pin
semiconductor
lead frame
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韩福彬
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Great Team Backend Foundry Dongguan Co Ltd
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Great Team Backend Foundry Dongguan Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

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Abstract

本实用新型涉及半导体电子元器件技术领域，特别涉及一种半导体元件；其结构包括引线框架、半导体芯片和封装外壳，所述半导体芯片装载在所述引线框架，所述半导体芯片封装在所述封装外壳内，所述半导体芯片与所述引线框架的引脚通过导线连接，所述引脚设置为焊盘，且设置于所述封装外壳底面；本实用新型缩小了半导体元件的体积，减少了半导体元件在PCB板上需要的布局空间，布局紧凑，减少了材料的使用量，降低成本，同时，缩短引脚的长度，降低通电状态的电阻，减少功耗。

Description

半导体元件
技术领域
本实用新型涉及半导体电子元器件技术领域，特别涉及一种半导体元件。
背景技术
随着半导体工业的高度发展，电子及半导体元件广泛地应用于日常生活中，如娱乐、教育、交通运输及家电用品等方面。电子产品朝向设计复杂、尺寸小、重量轻及人性化等方面发展。
引线框架一般用于半导体元件的封装，在现有技术中，引线框架上的引脚类型主要分为I型引脚和J型引脚，这两种类型的引脚都有部分设置在封装外壳外，这使得半导体元件的体积较大，导致半导体元件在PCB板上需要更多的布局空间，不利于制作更小尺寸的电子产品。
实用新型内容
本实用新型的目的在于避免上述现有技术中的不足之处而提供一种半导体元件。
本实用新型的目的通过以下技术方案实现：
提供了一种半导体元件，包括引线框架、半导体芯片和封装外壳，所述半导体芯片装载在所述引线框架，所述半导体芯片封装在所述封装外壳内，所述半导体芯片与所述引线框架的引脚通过导线连接，所述引脚设置为焊盘，且设置于所述封装外壳底面。
其中，所述引脚设置为圆形。
其中，所述引脚设置为矩形。
其中，所述引脚设置于所述引线框架的边缘。
本实用新型的有益效果：
一种半导体元件，包括引线框架、半导体芯片和封装外壳，所述半导体芯片装载于所述引线框架，所述半导体芯片封装在所述封装外壳内，所述半导体芯片与所述引线框架的引脚通过导线连接， 所述引脚设置为焊盘，且设置于所述封装外壳底面，所述引脚采用焊盘的设计，且设置于所述封装外壳的底面，缩小了半导体元件的体积，减少了半导体元件在PCB板上需要的布局空间，布局紧凑，减少了材料的使用量，降低成本，同时，缩短引脚的长度，降低通电状态的电阻，减少功耗。
附图说明
利用附图对本实用新型作进一步说明，但附图中的实施例不构成对本实用新型的任何限制，对于本领域的普通技术人员，在不付出创造性劳动的前提下，还可以根据以下附图获得其它的附图。
图1为本实用新型的一种半导体元件的结构示意图。
图2为本实用新型的一种半导体元件的另一视角的结构示意图。
图3为本实用新型的一种半导体元件的内部结构示意图。
附图标记：
1-半导体芯片、2-封装外壳、3-引脚、4-导线。
具体实施方式
结合以下实施例对本实用新型作进一步描述。
本实用新型的一种半导体元件的具体实施方式，如图1、图2和图3所示，包括引线框架、半导体芯片1和封装外壳2，所述半导体芯片1装载于所述引线框架，所述半导体芯片1封装在所述封装外壳2内，所述半导体芯片1与所述引线框架的引脚3通过导线4连接，所述引脚3设置为焊盘结构，且设置于所述封装外壳2的底面。
所述引脚3采用焊盘的设计，焊盘为表面贴装的单元，且设置于所述封装外壳2的底面，即与现有技术相比所述引脚3不露出所述封装外壳2，缩小了半导体元件的体积，减少了半导体元件在PCB板上需要的布局空间，布局紧凑，减少了材料的使用量，降低成本，同时，缩短引脚3的长度，降低通电状态的电阻，减少功耗。
优选地，所述引脚3设置为圆形或矩形。
优选地，所述引脚3设置于所述引线框架的边缘，由于半导体元件应做得尽量小，引脚3与引脚3之间的距离也将很小，通过把引脚3设置于边缘可以尽量地增大引脚3与引脚3间的距离，以便于半导体元件焊接至PCB板时，两相邻的焊锡不会熔融到一起。
最后应当说明的是，以上实施例仅用以说明本实用新型的技术方案，而非对本实用新型保护范围的限制，尽管参照较佳实施例对本实用新型作了详细地说明，本领域的普通技术人员应当理解，可以对本实用新型的技术方案进行修改或者等同替换，而不脱离本实用新型技术方案的实质和范围。

Claims (4)

1.半导体元件，包括引线框架、半导体芯片和封装外壳，所述半导体芯片装载于所述引线框架，所述半导体芯片封装在所述封装外壳内，所述半导体芯片与所述引线框架的引脚通过导线连接，其特征在于：所述引脚设置为焊盘结构，且设置于所述封装外壳的底面。
2.根据权利要求1所述的半导体元件，其特征在于：所述引脚设置为圆形。
3.根据权利要求1所述的半导体元件，其特征在于：所述引脚设置为矩形。
4.根据权利要求1至3任意一项所述的半导体元件，其特征在于：所述引脚设置于所述引线框架的边缘。
CN2012204690271U 2012-09-14 2012-09-14 半导体元件 Expired - Fee Related CN202839596U (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108551722A (zh) * 2018-06-05 2018-09-18 肖国选 单元pcb板
CN109994042A (zh) * 2019-04-11 2019-07-09 武汉华星光电技术有限公司 驱动芯片及显示面板

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108551722A (zh) * 2018-06-05 2018-09-18 肖国选 单元pcb板
CN109994042A (zh) * 2019-04-11 2019-07-09 武汉华星光电技术有限公司 驱动芯片及显示面板
CN109994042B (zh) * 2019-04-11 2024-05-03 武汉华星光电技术有限公司 驱动芯片及显示面板

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Granted publication date: 20130327

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