WO2022033117A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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Publication number
WO2022033117A1
WO2022033117A1 PCT/CN2021/096369 CN2021096369W WO2022033117A1 WO 2022033117 A1 WO2022033117 A1 WO 2022033117A1 CN 2021096369 W CN2021096369 W CN 2021096369W WO 2022033117 A1 WO2022033117 A1 WO 2022033117A1
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WIPO (PCT)
Prior art keywords
area
pad
binding
array substrate
group
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Application number
PCT/CN2021/096369
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English (en)
French (fr)
Inventor
许传志
谢正芳
吴勇
Original Assignee
昆山国显光电有限公司
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Publication date
Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Publication of WO2022033117A1 publication Critical patent/WO2022033117A1/zh
Priority to US17/992,327 priority Critical patent/US20230090854A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/118—Printed elements for providing electric connections to or between printed circuits specially for flexible printed circuits, e.g. using folded portions
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10128—Display

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate, a display panel and a display device.
  • COG chip on glass
  • COF chip on FPC
  • COP chip on plastic
  • the frame is getting smaller and smaller, the cost is also getting higher and higher.
  • the lower frame of the display screen currently on the market mainly adopts the COG (chip on glass) bonding scheme.
  • COG bonding solution since both the driver chip (IC) and the flexible circuit board (FPC) need to be bound on the lower border of the display panel, and the IC and the FPC need to be connected by traces, the lower border needs to be further reduced. more difficult.
  • Embodiments of the present application provide an array substrate, a display panel, and a display device, which aim to reduce the width of a lower frame of the display panel.
  • an embodiment of the present application provides an array substrate, the array substrate has a first area and a second area, the second area is distributed around the first area, and the second area includes a first area adjacent to the first area in a first direction.
  • a binding area the binding area includes: a driving chip binding area and a flexible circuit board binding area, the driving chip binding area is centrally distributed in the binding area, and the flexible circuit board binding area is in a second direction intersecting with the first direction distributed on both sides of the driver chip bonding area; the driver chip bonding area has a first pad, a wiring area and a second pad that are successively distributed in the first direction, the first pad is arranged close to the first area, and the first pad is arranged near the first area.
  • a pad includes a plurality of first solder joints arranged side by side in a second direction, the second pad includes a second solder joint group and an isolation area, the second solder joint group is located on both sides of the isolation interval in the second direction, and the second solder joint group
  • the solder joint group includes a plurality of second solder joints arranged side by side along the second direction; the second solder joints of the second solder joint group are connected to the binding area of the flexible circuit board through wires, and the conductive lines pass through the wiring area.
  • an embodiment of the present application further provides a display panel, including the array substrate described in any of the preceding embodiments.
  • an embodiment of the present application provides a display device, comprising: the display panel according to any of the previous embodiments; a driver chip, the driver chip is bound and connected to a binding area of the driver chip; a flexible circuit board, a flexible circuit board It comprises a main body part and two connecting parts extending along the first direction from one end of the main body part, and the two connecting parts are respectively bound and connected to the two flexible circuit board binding areas.
  • the array substrate has a binding area, the binding area includes a driving chip binding area and a flexible circuit board binding area, and the flexible circuit board binding area is in the second direction It is arranged on both sides of the driver chip binding area, which can reduce the need for the array substrate to be reserved in the first direction for the flexible circuit board binding area and the wiring between the flexible circuit board binding area and the driving chip binding area. Therefore, the width of the binding area in the first direction can be reduced, which is beneficial to realize the narrow frame design of the display panel.
  • an isolation area is set between the second solder joint groups of the second pads of the driving chip bonding area, so that the second solder joint group used for connecting with the flexible circuit board bonding area moves outward in the second direction, It can increase the space of the wiring area between the first pad and the second solder joint group, meet the layout requirements of the wires connecting the binding area of the flexible circuit board and the second solder joint group, and reduce the wiring difficulty caused by insufficient wiring space , problems such as easy interference between signals.
  • FIG. 1 shows a schematic structural diagram of an array substrate provided by an embodiment of the present application, wherein the binding area includes a driving chip binding area and a flexible circuit board binding area;
  • FIG. 2 shows a schematic structural diagram of a bonding area of an array substrate provided by an embodiment of the present application, wherein the driving chip bonding area has a first pad, a wiring area and a second pad that are sequentially distributed in the first direction Y;
  • FIG. 3 is a schematic structural diagram of a bonding area of an array substrate provided by another embodiment of the present application, wherein a plurality of first solder joints of the first pad can be distributed in the second direction X as a middle solder joint group and located in the middle
  • the first welding points of the side welding point group may be distributed in a row in the first direction Y;
  • FIG. 4 shows a schematic structural diagram of a binding area of an array substrate according to another embodiment of the present application, wherein the first solder joints of the side solder joint group may also be distributed in multiple rows in the first direction Y;
  • FIG. 5 shows a schematic structural diagram of a display panel provided by an embodiment of the present application
  • FIG. 6 shows a schematic structural diagram of a display device provided by an embodiment of the present application.
  • FIG. 7 shows a schematic structural diagram of a driver chip of a display device provided by an embodiment of the present application.
  • FIG. 1 shows a schematic structural diagram of an array substrate provided by an embodiment of the present application
  • FIG. 2 is a schematic structural schematic diagram of a binding area of an array substrate provided by an embodiment of the present application.
  • the array substrate provided in this embodiment of the present application has a first area E and a second area F, the second area F is distributed around the first area E, and the second area F includes a first area E adjacent to the first area E in the first direction Y Binding area F1.
  • the binding area F1 includes a driving chip binding area 10 and a flexible circuit board binding area 20 , the driving chip binding area 10 is centrally distributed in the binding area F1 , and both sides of the driving chip binding area 10 in the second direction X are A flexible circuit board binding area 20 is provided, and the second direction X intersects the first direction Y.
  • the driver chip binding area 10 may be an area on the array substrate for binding a driver chip
  • the flexible circuit board binding area 20 may be an area on the array substrate for binding a flexible circuit board.
  • the driving chip bonding area 10 has first pads 11 , wiring areas 12 and second pads 13 distributed in sequence in the first direction Y. As shown in FIG. The first pad 11 is disposed close to the first area E, the first pad 11 includes a plurality of first pads arranged side by side along the second direction X, the second pad 13 includes a second pad group 131 and an isolation area 132, The second solder joint group 131 is located on both sides of the isolation area 132 in the second direction X, and the second solder joint group 131 includes a plurality of second solder joints arranged side by side along the second direction X; The solder joints are connected to the binding area 20 of the flexible circuit board through wires 121 , and the wires 121 pass through the wiring area 12 .
  • the flexible circuit board binding area 20 is arranged on both sides of the driving chip binding area 10 in the second direction X, which can reduce the amount of the flexible circuit board in the first direction Y of the array substrate.
  • the binding area 20 and the space required for the wiring between the flexible circuit board binding area 20 and the driver chip binding area 10 can be reserved, thereby reducing the width of the binding area F1 in the first direction Y.
  • an isolation area 132 is set between the second solder joint groups 131 of the second pads 13, so that the second solder joint group 131 for connecting with the flexible circuit board binding area 20 moves outward in the second direction X, It can increase the space of the wiring area 12 between the first pad 11 and the second pad group 131, meet the layout requirements of the wires 121 connecting the binding area 20 of the flexible circuit board and the second pad group 131, and reduce the wiring Problems such as difficult wiring and easy interference between signals caused by insufficient space.
  • the first direction Y may be the length direction of the array substrate
  • the second direction X may be the width direction of the array substrate
  • the first direction Y may be perpendicular to the second direction X.
  • FIG. 3 shows a schematic structural diagram of a binding area of an array substrate provided by another embodiment of the present application
  • FIG. 4 is a schematic structural diagram of a binding area of an array substrate provided by another embodiment of the present application.
  • a plurality of dummy solder joints arranged side by side along the second direction X may be arranged in the isolation area 132 of the second pad 13 .
  • the driver chip is arranged on the driver chip
  • the pins of the driver chip are bound and connected to the corresponding pads in the binding area 10
  • the corresponding pins on the driver chip can be supported by the virtual solder joints.
  • the plurality of first solder joints of the first pad 11 may be distributed in the second direction X into a middle solder joint group 112 and a middle solder joint group Side solder joint groups 111 on both sides of 112 .
  • the first solder joints of the side solder joint group 111 may be distributed in a row in the first direction Y. As shown in FIG. 3 , optionally, the first solder joints of the side solder joint group 111 may be distributed in a row in the first direction Y. As shown in FIG. 3
  • the first solder joints of the side solder joint group 111 may also be distributed in multiple rows in the first direction Y, which is also within the protection scope of the present application.
  • the minimum distance d1 between the side pad group 111 and the second pad 13 is greater than the minimum distance d1 between the middle pad group 112 and the second pad 13
  • the distance d2 enables the wires 121 to be at least partially laid out to the area between the side pad group 111 and the second pad 13 .
  • the edge of the side solder joint group 111 close to the first area E may be flush with the edge of the middle solder joint group 112 close to the first area E, and the edge of the first pad 11 may not be increased.
  • the space between the side solder joint group 111 and the second pad 13 is maximized.
  • the first solder joints of the intermediate solder joint group 112 may be distributed in one row in the first direction Y, or may be distributed in multiple rows.
  • the first solder joints of the middle solder joint group 112 are distributed in at least two rows in the first direction Y; In the space occupied by the first pads 11 in the first direction Y, the first solder joints of the intermediate solder joint group 112 are distributed in at most three rows in the first direction Y.
  • first solder joints of the middle solder joint group 112 are distributed in at least two rows in the first direction Y, there are gaps between the plurality of first solder joints in each row.
  • the first solder joints in one row and the first solder joints in the other row are staggered.
  • the first solder joints in one row and the first solder joints in the other row can be arranged alternately in the second direction X.
  • the array substrate further includes scan lines and signal lines
  • the plurality of first pads of the first pads 11 include signal line pads for connecting with the signal lines of the array substrate and for connecting with the signal lines of the array substrate.
  • the first solder joints of the middle solder joint group 112 are all signal line solder joints
  • the first solder joints of the side solder joint group 111 are all scan line solder joints, so as to facilitate wiring.
  • At least two alignment marks 14 are further provided in the driver chip binding area 10 , and the alignment marks 14 may be between the first pad 11 and the wiring area 12 .
  • the shape of the alignment mark 14 may be a cross, a trapezoid, a square or any other suitable shape, which is not specifically limited in this application.
  • the alignment marks 14 may be arranged in the wiring area 12 .
  • the middle solder joint group 112 and the side solder joint group 111 may be distributed in a row in the first direction Y.
  • the alignment marks 14 may be disposed above the wiring area 12 and on both sides of the first pads 11 .
  • the alignment mark 14 may also be disposed above the wiring area 12 and between the middle solder joint group 112 and the side solder joint group 111 , which is also within the protection scope of the present application.
  • the alignment mark 14 is located near the corresponding end point of the isolation area 132 in the second direction X, so that the wiring area 12 above the second pad group 131 satisfies Wire 121 routing requirements.
  • the distance l between the orthographic projection of the alignment mark 14 to the isolation area 132 in the first direction Y and the corresponding end point of the isolation area 132 in the second direction X may be 0 mm to 1 mm.
  • the distance l between the orthographic projection of the alignment mark 14 in the first direction Y to the isolation area 132 and the corresponding end point of the isolation area 132 in the second direction X may refer to,
  • the distance from the projection of the center of the alignment mark 14 to the orthographic projection of the isolation section 132 and the corresponding end point of the isolation section 132 in the second direction X is 1.
  • the bonding area 20 of the flexible circuit board may be provided with a third pad 21 , and the third pad 21 includes a plurality of third pads arranged side by side along the second direction X.
  • the third pads The third pads of the pad are connected to the second pads of the second pad 13 in a one-to-one correspondence.
  • the third pads of the third pads 21 may be distributed in one row in the first direction Y, or may be distributed in multiple rows.
  • the minimum distance d3 from the edge of the third pad 21 close to the first region E to the first region E is less than or equal to the distance from the edge of the second pad 13 away from the first region E to the first region E
  • the minimum distance d4 is to reduce the space required to be reserved for the third pad 21 in the first direction Y of the bonding area F1, and reduce the width of the bonding area F1 in the first direction Y.
  • the minimum distance d3 from the edge of the third pad 21 close to the first region E to the first region E is less than or equal to the minimum distance d5 from the edge of the second pad 13 close to the first region E to the first region E, In order to further reduce the width of the binding area F1 in the first direction Y.
  • an embodiment of the present application further provides a display panel including the aforementioned array substrate.
  • the display panel may be an organic light emitting diode (Organic Light Emitting Diode, OLED) display panel, or a liquid crystal (Liquid Crystal Display, LCD) display panel.
  • OLED Organic Light Emitting Diode
  • LCD liquid crystal
  • FIG. 5 shows a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel may include a display area G and a non-display area H, the first area E of the array substrate is set corresponding to the display area G of the display panel, and the second area F is set corresponding to the non-display area H of the display panel.
  • the binding area F1 is set corresponding to the lower border area H1 of the display panel.
  • the first direction Y may be the width direction of the lower border area H1
  • the second direction X may be the length direction of the lower border area H1.
  • the display panel provided according to the embodiments of the present application includes the array substrate provided in the above-mentioned embodiments, and the array substrate sets the flexible circuit board binding area 20 on both sides of the driving chip binding area 10 in the second direction X,
  • the width of the binding area F1 in the first direction Y can be reduced, so that the width of the lower border area H1 of the display panel can be narrowed, which can meet the required narrow border requirements.
  • an embodiment of the present application further provides a display device.
  • FIG. 6 shows a schematic structural diagram of a display device provided by an embodiment of the present application
  • FIG. 7 is a schematic structural schematic diagram of a driver chip of the display device provided by an embodiment of the present application.
  • the display device includes the display panel, the driving chip 30 and the flexible circuit board 40 provided in the above-mentioned embodiments.
  • the driver chip 30 is bound and connected to the driver chip binding area 10 ;
  • the flexible circuit board 40 includes a main body portion 41 and two connecting portions 42 extending from one end of the main body portion 41 along the first direction Y, and the two connecting portions 42 are respectively bound It is fixedly connected to the two flexible circuit board binding areas 20 .
  • the driver chip 30 may include a core base 31 and a first binding pin group 32 and a second binding pin group 33 disposed on the core base 31 .
  • the first binding pin group 32 is located on one side of the second binding pin group 33
  • the first binding pin group 32 may include a plurality of first binding pins arranged side by side along the second direction X
  • the second binding pin group 33 may include a plurality of second binding pins arranged side by side along the second direction X.
  • the first binding pin of the first binding pin group 32 is bound and connected to the first solder point of the first pad 11 in a one-to-one correspondence
  • the second The second binding pins of the binding pin group 33 are bound and connected to the second pads of the second pads 13 in a one-to-one correspondence.
  • the two connection portions 42 of the flexible circuit board 40 may be provided with a plurality of connection pins arranged side by side along the second direction X; when the flexible circuit board binding area 20 of the array substrate is provided with When the third pad 21 and the connecting portion 42 of the flexible circuit board 40 are bound and connected to the flexible circuit board binding area 20 , each connecting pin of the connecting portion 42 corresponds to each third soldering point of the third pad 21 one-to-one. Bind the connection.

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Abstract

本申请涉及一种阵列基板、显示面板及显示装置。阵列基板具有绑定区域，绑定区域包括驱动芯片绑定区和柔性电路板绑定区，驱动芯片绑定区在绑定区域居中分布，柔性电路板绑定区在第二方向上分布于驱动芯片绑定区的两侧，驱动芯片绑定区具有在第一方向上相继分布的第一焊盘、布线区和第二焊盘，第一焊盘靠近第一区域设置，第二焊盘包括第二焊点组和隔离区间，在第二方向上第二焊点组位于隔离区间两侧，第二焊点组的第二焊点通过导线与柔性电路板绑定区连接，导线经过布线区。

Description

阵列基板、显示面板及显示装置
相关申请的交叉引用
本申请要求享有于2020年08月14日提交的名称为“阵列基板、显示面板及显示装置”的中国专利申请第202010820314.1号的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板、显示面板及显示装置。
背景技术
近年来，全面屏成为显示领域的主流设计方案并受到广大消费者的青睐，为提高屏占比，显示屏的下边框越窄越好。
目前，显示屏的下边框贴合方案有COG(chip on glass)、COF(chip on FPC)和COP(chip on plastic)三种，虽然边框越来越小，但成本也越来越高，基于成本的考虑，目前市场上的显示屏的下边框主要采用COG(chip on glass)贴合方案。对于COG贴合方案而言，由于驱动芯片(IC)和柔性电路板(FPC)均需要绑定在显示面板的下边框位置上，且IC与FPC需要通过走线相连，因此要进一步缩小下边框较为困难。
申请内容
本申请实施例提供一种阵列基板、显示面板及显示装置，旨在缩小显示面板下边框的宽度。
一方面，本申请实施例提供了一种阵列基板，阵列基板具有第一区域和第二区域，第二区域环绕第一区域分布，第二区域包括在第一方向上与第一区域相邻的绑定区域，绑定区域包括：驱动芯片绑定区和柔性电路板 绑定区，驱动芯片绑定区在绑定区域居中分布，柔性电路板绑定区在与第一方向相交的第二方向上分布于驱动芯片绑定区的两侧；驱动芯片绑定区具有在第一方向上相继分布的第一焊盘、布线区和第二焊盘，第一焊盘靠近第一区域设置，第一焊盘包括沿第二方向并排设置的多个第一焊点，第二焊盘包括第二焊点组和隔离区间，在第二方向上第二焊点组位于隔离区间两侧，第二焊点组包括沿第二方向并排设置的多个第二焊点；第二焊点组的第二焊点通过导线与柔性电路板绑定区连接，导线路经布线区。
另一方面，本申请实施例还提供了一种显示面板，包括如前任一实施方式所述的阵列基板。
再一方面，本申请实施例提供了一种显示装置，包括：如前任一实施例所述的显示面板；驱动芯片，驱动芯片绑定连接于驱动芯片绑定区；柔性电路板，柔性电路板包括主体部及自主体部的一端沿第一方向延伸出的两个连接部，两个连接部分别绑定连接于两个柔性电路板绑定区。
本申请实施例提供的阵列基板、显示面板及显示装置，阵列基板具有绑定区域，绑定区域包括驱动芯片绑定区和柔性电路板绑定区，柔性电路板绑定区在第二方向上设置于驱动芯片绑定区的两侧，能够减小阵列基板在第一方向上为柔性电路板绑定区以及柔性电路板绑定区与驱动芯片绑定区之间的走线所需预留的空间，进而能够减小绑定区域在第一方向上的宽度，有利于实现显示面板的窄边框设计。而在驱动芯片绑定区的第二焊盘的第二焊点组之间设置隔离区间，使得用于与柔性电路板绑定区连接的第二焊点组在第二方向上向外移动，能够增大第一焊盘与第二焊点组之间的布线区的空间，满足连接柔性电路板绑定区和第二焊点组的导线的布设需求，减少因布线空间不够产生的布线困难、信号之间易干涉等问题。
附图说明
下面将参考附图来描述本申请示例性实施例的特征、优点和技术效果，其中的附图并未按照实际的比例绘制。
图1示出本申请实施例提供的阵列基板的结构示意图，其中绑定区包括驱动芯片绑定区和柔性电路板绑定区；
图2示出本申请实施例提供的阵列基板的绑定区域的结构示意图，其中驱动芯片绑定区具有在第一方向Y上依次分布的第一焊盘、布线区和第二焊盘；
图3示出本申请另一实施例提供的阵列基板的绑定区域的结构示意图，其中第一焊盘的多个第一焊点在第二方向X上可以分布为中间焊点组及位于中间焊点组两侧的侧焊点组，侧焊点组的第一焊点在第一方向Y上可以呈一排分布；
图4示出本申请又一实施例提供的阵列基板的绑定区域的结构示意图，其中侧焊点组的第一焊点在第一方向Y上也可以呈多排分布；
图5示出本申请实施例提供的显示面板的结构示意图；
图6示出本申请实施例提供的显示装置的结构示意图；
图7示出本申请实施例提供的显示装置的驱动芯片的结构示意图。
具体实施方式
下面将详细描述本申请的各个方面的特征和示例性实施例。在下面的详细描述中，提出了许多具体细节，以便提供对本申请的全面理解。但是，对于本领域技术人员来说很明显的是，本申请可以在不需要这些具体细节中的一些细节的情况下实施。下面对实施例的描述仅仅是为了通过示出本申请的示例来提供对本申请的更好的理解。在附图和下面的描述中，至少部分的公知结构和技术没有被示出，以便避免对本申请造成不必要的模糊；并且，为了清晰，可能夸大了部分结构的尺寸。此外，下文中所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。
近年来，显示面板主要朝着高屏占比、窄边框方向发展。目前，显示屏的下边框贴合方案有COG(chip on glass)、COF(chip on FPC)和COP(chip on plastic)三种，以COG贴合方案为例，驱动芯片和柔性电路板均需要绑定在显示面板的下边框区域，由于驱动芯片和柔性电路板沿下边框的宽度方向排布，且在下边框的宽度方向上还需要为连接驱动芯片和柔性电路板的导线预留空间，因此想要进一步缩小下边框较为困难。
为了更好地理解本申请，下面结合图1至图6对本申请实施方式提供 的阵列基板、显示面板及显示装置进行详细描述。
下面参考图1和图2描述根据本申请的阵列基板的实施例。图1示出本申请实施例提供的阵列基板的结构示意图；图2示出本申请实施例提供的阵列基板的绑定区域的结构示意图。
本申请实施例提供的阵列基板，具有第一区域E和第二区域F，第二区域F环绕第一区域E分布，第二区域F包括在第一方向Y上与第一区域E相邻的绑定区域F1。
绑定区域F1包括驱动芯片绑定区10和柔性电路板绑定区20，驱动芯片绑定区10在绑定区域F1居中分布，驱动芯片绑定区10在第二方向X上的两侧均设置有柔性电路板绑定区20，第二方向X与第一方向Y相交。
驱动芯片绑定区10可以是阵列基板上用于绑定驱动芯片的区域，柔性电路板绑定区20可以是阵列基板上用于绑定柔性电路板的区域。
驱动芯片绑定区10具有在第一方向Y上依次分布的第一焊盘11、布线区12和第二焊盘13。第一焊盘11靠近第一区域E设置，第一焊盘11包括沿第二方向X并排设置的多个第一焊点，第二焊盘13包括第二焊点组131和隔离区间132，在第二方向X上第二焊点组131位于隔离区间132两侧，第二焊点组131包括沿第二方向X并排设置的多个第二焊点；第二焊点组131的第二焊点通过导线121与柔性电路板绑定区20连接，导线121经过布线区12。
根据本申请实施例提供的阵列基板，将柔性电路板绑定区20在第二方向X上设置于驱动芯片绑定区10两侧，能够减小阵列基板在第一方向Y上为柔性电路板绑定区20以及柔性电路板绑定区20与驱动芯片绑定区10之间的走线所需预留的空间，进而能够减小绑定区域F1在第一方向Y上的宽度，当本申请实施例提供的阵列基板应用于显示面板时，有利于实现显示面板的窄边框设计。而在第二焊盘13的第二焊点组131之间设置隔离区间132，使得用于与柔性电路板绑定区20连接的第二焊点组131在第二方向X上向外移动，能够增大第一焊盘11与第二焊点组131之间的布线区12的空间，满足连接柔性电路板绑定区20和第二焊点组131的导线121的布设需求，减少因布线空间不够产生的布线困难、信号之间易干涉等问题。
在一些可选的实施例中，第一方向Y可以为阵列基板的长度方向，第二方向X可以为阵列基板的宽度方向，可选地，第一方向Y可以垂直于第二方向X。
下面参考图3和图4描述根据本申请的阵列基板的实施例。图3示出本申请另一实施例提供的阵列基板的绑定区域的结构示意图；图4示出本申请又一实施例提供的阵列基板的绑定区域的结构示意图。
如图3所示，在一些可选的实施例中，在第二焊盘13的隔离区间132可以设置有沿第二方向X并排设置的多个虚拟焊点，在将驱动芯片设置于驱动芯片绑定区10且将驱动芯片的引脚与对应焊盘绑定连接时，可以通过虚拟焊点支撑驱动芯片上对应的引脚。
如图3和图4所示，在一些可选的实施例中，第一焊盘11的多个第一焊点在第二方向X上可以分布为中间焊点组112及位于中间焊点组112两侧的侧焊点组111。
如图3所示，可选地，侧焊点组111的第一焊点在第一方向Y上可以呈一排分布。
如图4所示，侧焊点组111的第一焊点在第一方向Y上也可以呈多排分布，也在本申请的保护范围之内。
在一些可选的实施例中，为满足导线121的布线需求，侧焊点组111与第二焊盘13之间的最小距离d1大于中间焊点组112与第二焊盘13之间的最小距离d2，使得导线121可以至少部分布局至侧焊点组111与第二焊盘13之间的区域。
可选地，在第一方向Y上，侧焊点组111靠近第一区域E的边缘可以与中间焊点组112靠近第一区域E的边缘齐平，可以在不增加第一焊盘11的占用空间的前提下，使侧焊点组111与第二焊盘13之间的空间最大化。
中间焊点组112的第一焊点在第一方向Y上可以呈一排分布，也可以呈多排分布。可选地，为减小第一焊盘11在第二方向X上所占用的空间，中间焊点组112的第一焊点在第一方向Y上至少呈两排分布；同时，为减小第一焊盘11在第一方向Y上所占用的空间，中间焊点组112的第一焊点在第一方向Y上至多呈三排分布。
可选地，中间焊点组112的第一焊点在第一方向Y上呈至少两排分布时，每排中多个第一焊点之间均具有间隙，对于相邻两排第一焊点，一排的第一焊点与另一排的第一焊点错位设置，具体可以为一排的第一焊点与另一排的第一焊点在第二方向X上可以依次交替设置，这种较为紧凑的焊点排布方式，可以使中间焊点组112所在的第一焊盘11空间较小，有利于实现显示面板的窄边框设计。
作为一种可选的实施方式，阵列基板还包括扫描线以及信号线，第一焊盘11的多个第一焊点包括用于与阵列基板的信号线连接的信号线焊点以及用于与阵列基板的扫描线连接的扫描线焊点。可选地，中间焊点组112的第一焊点均为信号线焊点，侧焊点组111的第一焊点均为扫描线焊点，以方便走线。
请继续参考图3和图4，在一些可选的实施例中，为方便驱动芯片的准确绑定，在驱动芯片绑定区10还设置有至少两个对位标记14，对位标记14可以位于第一焊盘11与布线区12之间。
可选地，对位标记14的形状可以为十字型、梯形、方形或其它任何合适的形状，本申请对此不做具体限制。
可选地，侧焊点组111的第一焊点在第一方向Y上可以呈一排分布时，为防止对位标记14干涉导线121的布设，可以将对位标记14设置于布线区12上方并位于中间焊点组112与侧焊点组111之间。
可选地，侧焊点组111的第一焊点在第一方向Y上呈多排分布时，对位标记14可以设置于布线区12上方、第一焊盘11的两侧。当然，也可以将对位标记14设置于布线区12上方、中间焊点组112与侧焊点组111之间，也在本申请的保护范围之内。
在一些可选的实施例中，在第二方向X上，对位标记14位于隔离区间132在第二方向X上的对应端点的附近，为使第二焊点组131上方的布线区12满足导线121的布线需求。
可选地，对位标记14在第一方向Y上投影至隔离区间132的正投影，与隔离区间132在第二方向X上的对应端点之间的间距l可以为0mm至1mm。
在一些可选的实施例中，上述对位标记14在第一方向Y上投影至隔离区间132的正投影与隔离区间132在第二方向X上的对应端点之间的间距l可以是指，对位标记14的中心投影至隔离区间132的正投影与隔离区间132在第二方向X上的对应端点的距离为l。
在一些可选的实施例中，在柔性电路板绑定区20可以设置有第三焊盘21，第三焊盘21包括沿第二方向X并排设置的多个第三焊点，第三焊盘的第三焊点与第二焊盘13的第二焊点一一对应连接。
第三焊盘21的第三焊点在第一方向Y上可以呈一排分布，也可以呈多排分布。
在一些可选的实施例中，第三焊盘21靠近第一区域E的边缘至第一区域E的最小距离d3小于或等于第二焊盘13远离第一区域E的边缘至第一区域E的最小距离d4，以减小绑定区域F1在第一方向Y上为第三焊盘21所需预留的空间，减小绑定区域F1在第一方向Y上的宽度。
可选地，第三焊盘21靠近第一区域E的边缘至第一区域E的最小距离d3小于或等于第二焊盘13靠近第一区域E的边缘至第一区域E的最小距离d5，以进一步减小绑定区域F1在第一方向Y上的宽度。
另外，本申请实施例还提供了一种显示面板，包括如前所述的阵列基板。该显示面板可以是机发光二极管(Organic Light Emitting Diode，OLED)显示面板，也可以是液晶(Liquid Crystal Display，LCD)显示面板。
图5示出本申请实施例提供的显示面板的结构示意图。如图5所示，该显示面板可以包括显示区G以及非显示区H，阵列基板的第一区域E对应显示面板的显示区G设置，第二区域F对应显示面板的非显示区H设置。
在一些可选的实施例中，绑定区域F1对应显示面板的下边框区域H1设置。
在一些可选的实施例中，第一方向Y可以为下边框区域H1的宽度方向，第二方向X可以为下边框区域H1的长度方向。
根据本申请实施例提供的显示面板，因其包括上述各实施例提供的阵列基板，该阵列基板将柔性电路板绑定区20在第二方向X上设置于驱动芯 片绑定区10两侧，能够减小绑定区域F1在第一方向Y上的宽度，进而能够使显示面板下边框区域H1的宽度较窄，能够满足所需的窄边框要求。
另外，本申请实施例还提供了一种显示装置。图6示出本申请实施例提供的显示装置的结构示意图；图7示出本申请实施例提供的显示装置的驱动芯片的结构示意图。
如图6所示，根据本申请的实施例的显示装置包括上述各实施例提供的显示面板以及驱动芯片30和柔性电路板40。驱动芯片30绑定连接于驱动芯片绑定区10；柔性电路板40包括主体部41以及自主体部41的一端沿第一方向Y延伸出的两个连接部42，两个连接部42分别绑定连接于两个柔性电路板绑定区20。
如图7所示，在一些可选的实施例中，驱动芯片30可以包括芯座31以及设置于芯座31的第一绑定引脚组32和第二绑定引脚组33，在第一方向Y上、第一绑定引脚组32位于第二绑定引脚组33一侧，第一绑定引脚组32可以包括沿第二方向X且并排设置的多个第一绑定引脚，第二绑定引脚组33可以包括沿第二方向X且并排设置的多个第二绑定引脚。驱动芯片30绑定连接于驱动芯片绑定区10时，第一绑定引脚组32的第一绑定引脚与第一焊盘11的第一焊点一一对应绑定连接，第二绑定引脚组33的第二绑定引脚与第二焊盘13的第二焊点一一对应绑定连接。
在一些可选的实施例中，柔性电路板40的两个连接部42上可以设置有沿第二方向X并排设置的多个连接引脚；当阵列基板的柔性电路板绑定区20设置有第三焊盘21且柔性电路板40的连接部42绑定连接于柔性电路板绑定区20时，连接部42的各连接引脚与第三焊盘21的各第三焊点一一对应绑定连接。
本领域技术人员应能理解，上述实施例均是示例性而非限制性的。在不同实施例中出现的不同技术特征可以进行组合，以取得有益效果。本领域技术人员在研究附图、说明书及权利要求书的基础上，应能理解并实现所揭示的实施例的其他变化的实施例。权利要求中出现的多个部分的功能可以由一个单独的硬件或软件模块来实现。某些技术特征出现在不同的从属权利要求中并不意味着不能将这些技术特征进行组合以取得有益效果。

Claims (18)

  1. 一种阵列基板，具有第一区域和第二区域，所述第二区域环绕所述第一区域分布，所述第二区域包括在第一方向上与所述第一区域相邻的绑定区域，所述绑定区域包括：
    驱动芯片绑定区和柔性电路板绑定区，所述驱动芯片绑定区在所述绑定区域居中分布，所述柔性电路板绑定区在与所述第一方向相交的第二方向上分布于所述驱动芯片绑定区的两侧，
    其中，所述驱动芯片绑定区具有在所述第一方向上依次分布的第一焊盘、布线区和第二焊盘，所述第一焊盘靠近所述第一区域设置，所述第一焊盘包括沿所述第二方向并排设置的多个第一焊点，所述第二焊盘包括第二焊点组和隔离区间，在所述第二方向上所述第二焊点组位于所述隔离区间两侧，所述第二焊点组包括沿所述第二方向并排设置的多个第二焊点；
    所述第二焊点组的所述第二焊点通过导线与所述柔性电路板绑定区连接，所述导线经过所述布线区。
  2. 根据权利要求1所述的阵列基板，其中，所述隔离区间设置有沿所述第二方向并排设置的多个虚拟焊点。
  3. 根据权利要求1所述的阵列基板，其中，所述第一焊盘的多个所述第一焊点在所述第二方向上分布为中间焊点组及位于所述中间焊点组两侧的侧焊点组。
  4. 根据权利要求3所述的阵列基板，其中，所述阵列基板还包括扫描线以及信号线，所述第一焊盘的多个所述第一焊点包括用于与所述信号线连接的信号线焊点以及用于与所述扫描线连接的扫描线焊点，所述中间焊点组的所述第一焊点均为所述信号线焊点，所述侧焊点组的所述第一焊点均为扫描线焊点。
  5. 根据权利要求3所述的阵列基板，其中，所述侧焊点组的所述第一焊点在所述第一方向上呈一排分布。
  6. 根据权利要求3所述的阵列基板，其中，所述侧焊点组与所述第二焊盘之间的最小距离大于所述中间焊点组与所述第二焊盘之间的最小距离。
  7. 根据权利要求3所述的阵列基板，其中，在所述第一方向上、所述侧焊点组靠近所述第一区域的边缘与所述中间焊点组靠近所述第一区域的边缘齐平。
  8. 根据权利要求3所述的阵列基板，其中，所述中间焊点组的所述第一焊点在所述第一方向上至少呈两排分布，各所述排中多个所述第一焊点之间具有间隙，相邻两排所述第一焊点错位设置。
  9. 根据权利要求3所述的阵列基板，其中，所述驱动芯片绑定区还设置有至少两个对位标记，所述对位标记位于所述第一焊盘与所述布线区之间。
  10. 根据权利要求9所述的阵列基板，其中，所述侧焊点组的所述第一焊点在所述第一方向上呈一排分布，所述对位标记设置于所述布线区上方、及所述中间焊点组与所述侧焊点组之间。
  11. 根据权利要求9所述的阵列基板，其中，所述侧焊点组的所述第一焊点在所述第一方向上呈多排分布，所述对位标记设置于所述布线区上方、所述第一焊盘的两侧，或，所述对位标记设置于所述布线区上方、所述中间焊点组与所述侧焊点组之间。
  12. 根据权利要求9所述的阵列基板，其中，所述对位标记在所述第一方向上投影至所述隔离区间的正投影，与所述隔离区间在所述第二方向上的对应端点之间的间距l为0mm～1mm。
  13. 根据权利要求1至12任意一项所述的阵列基板，其中，所述柔性电路板绑定区设置有第三焊盘，所述第三焊盘包括沿所述第二方向并排设置的多个第三焊点，所述第三焊盘的所述第三焊点与所述第二焊点连接。
  14. 根据权利要求13所述的阵列基板，其中，所述第三焊盘靠近所述第一区域的边缘至所述第一区域的最小距离小于或等于所述第二焊盘远离所述第一区域的边缘至所述第一区域的最小距离。
  15. 根据权利要求14所述的阵列基板，其中，所述第三焊盘靠近所述第一区域的边缘至所述第一区域的最小距离小于或等于所述第二焊盘靠近所述第一区域的边缘至所述第一区域的最小距离。
  16. 一种显示面板，包括权利要求1-15任一项所述的阵列基板。
  17. 一种显示装置，包括：
    如权利要求16所述的显示面板；
    驱动芯片，所述驱动芯片绑定连接于所述驱动芯片绑定区；
    柔性电路板，所述柔性电路板包括主体部及自所述主体部的一端沿所述第一方向延伸出的两个连接部，两个所述连接部分别绑定连接于两个所述柔性电路板绑定区。
  18. 根据权利要求17所述的显示装置，其中，所述驱动芯片包括芯座以及设置于所述芯座的第一绑定引脚组和第二绑定引脚组，在所述第一方向上所述第一绑定引脚组位于所述第二绑定引脚组一侧，所述第一绑定引脚组包括沿所述第二方向且并排设置的多个第一绑定引脚，所述第二绑定引脚组包括沿所述第二方向且并排设置的多个第二绑定引脚，所述第一绑定引脚组的所述第一绑定引脚与所述第一焊盘的所述第一焊点一一对应绑定连接，所述第二绑定引脚组的所述第二绑定引脚与所述第二焊盘的所述第二焊点一一对应绑定连接。
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