WO2022109875A1 - 发光基板及其制备方法、阵列基板 - Google Patents

发光基板及其制备方法、阵列基板 Download PDF

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Publication number
WO2022109875A1
WO2022109875A1 PCT/CN2020/131500 CN2020131500W WO2022109875A1 WO 2022109875 A1 WO2022109875 A1 WO 2022109875A1 CN 2020131500 W CN2020131500 W CN 2020131500W WO 2022109875 A1 WO2022109875 A1 WO 2022109875A1
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WIPO (PCT)
Prior art keywords
pad
lead
substrate
leads
driving
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PCT/CN2020/131500
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English (en)
French (fr)
Inventor
张天宇
何敏
钟腾飞
张新秀
谢晓冬
赵雪
徐文结
桑华煜
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Publication date
Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080002975.1A priority Critical patent/CN114793473B/zh
Priority to PCT/CN2020/131500 priority patent/WO2022109875A1/zh
Priority to US17/438,447 priority patent/US20230207542A1/en
Publication of WO2022109875A1 publication Critical patent/WO2022109875A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a light-emitting substrate, a preparation method thereof, and an array substrate.
  • the thickness of the driving lead can be increased. or width to reduce resistance.
  • the purpose of the present disclosure is to provide a light-emitting substrate, a method for preparing the same, and an array substrate, which can avoid damage to the bonding pads and discard the entire array substrate.
  • an array substrate wherein the array substrate is polygonal and has at least one set of first and second sides disposed opposite to each other, and an array substrate disposed close to the first side. a first binding area and a second binding area disposed near the second side;
  • the array substrate includes a base substrate and a pad layer provided on the main surface of the base substrate, the pad layer includes a plurality of first bonding pads located in the first bonding area, and includes a plurality of second bonding pads located in the second bonding area; any one of the first bonding area and the second bonding area is used for connecting with a driving circuit board to drive the array substrate.
  • the pad layer further includes a plurality of first pad groups; the plurality of first pad groups are centrally symmetrically distributed.
  • any one of the first pad groups includes a pair of first sub-pads and second sub-pads.
  • the pad layer further includes a plurality of second pad groups, any one of the second pad groups is used for connecting with a microchip.
  • any one of the second pad groups includes:
  • a plurality of data sub-pads for connecting with at least part of the first pad groups of the plurality of first pad groups.
  • At least two of the plurality of first bonding pads are respectively used for loading different driving signals; at least two of the plurality of second bonding pads Each is used to load different driving signals;
  • At least one of the plurality of first bonding pads and the plurality of second bonding pads for loading the same kind of driving signal
  • At least one of the second bonding pads is symmetrical with respect to the central axis of the base substrate.
  • the array substrate further includes a metal wiring layer
  • the metal wiring layer includes a plurality of driving leads; the plurality of driving leads are symmetrically distributed in the center.
  • the metal wiring layer further includes a plurality of first fan-out leads for connecting the first bonding area and the plurality of driving leads for connecting the a second bonding area and a plurality of second fan-out leads of the plurality of driving leads; the orthographic projection of the plurality of first fan-out leads on the base substrate and the plurality of first pad groups
  • the orthographic projections on the base substrate have overlapping regions; the orthographic projections of the plurality of second fan-out leads on the base substrate and the plurality of first pad groups on the base substrate There is an overlapping area of the orthographic projections on .
  • the metal wiring layer includes a first metal wiring layer, a planarization layer and a second metal wiring layer sequentially stacked on the base substrate, the first metal wiring layer connected with the second metal wiring layer through a via hole passing through the planarization layer;
  • the first fan-out leads are all located on the first metal wiring layer
  • the second fan-out lead includes a first lead and a second lead; the first lead is located in the first metal wiring layer and is electrically connected to the drive lead and the second bonding pad; the second lead
  • the lead at least includes a first part, a second part and a third part connected in sequence; the first part and the third part are located on the first metal wiring layer, and the second part is located on the second metal wiring layer ;
  • the first part is electrically connected to the driving lead, and the third part is electrically connected to the second bonding pad.
  • the plurality of first bonding pads and the plurality of second bonding pads are symmetrical about the same auxiliary line;
  • the plurality of drive leads include at least one first drive lead group; any one of the first drive lead groups includes a plurality of first drive leads that are symmetrical about the auxiliary line and used for loading the same drive signal;
  • the first leads and the first fan-out leads respectively connected to the plurality of first drive leads in any one of the first drive lead groups are distributed symmetrically in the center.
  • the thickness of the first metal wiring layer is greater than the thickness of the second metal wiring layer; the driving leads are all located on the first metal wiring layer.
  • the difference in thickness of the driving leads at different positions does not exceed 150%.
  • two ends of the driving lead have different thicknesses; wherein, the thickness of the thicker end of the driving lead is thinner than that of the driving lead The thickness of one end is more than 10% larger.
  • the array substrate is rectangular, has a plurality of control areas distributed in an array, and each control area forms N control area columns arranged along the side direction, and forms N control area columns along the long side. 2N control area lines arranged in the direction; wherein, N is a positive integer;
  • any one of the second pad groups also includes a chip power supply sub-pad for connecting with the chip power supply pin of the microchip, and a first power supply sub-pad for connecting with the first power supply pin of the microchip.
  • the array substrate further includes a metal wiring layer, and the metal wiring layer includes a plurality of connecting leads and a plurality of driving leads extending along the longitudinal direction;
  • the driving leads include two second power supply voltage leads for loading the second power supply voltage, one chip power supply lead for loading the chip power supply voltage, and two for loading the chip power supply lead.
  • chip control leads for control signals, a first power supply voltage lead for loading a first power supply voltage, and a driving data lead for loading driving data;
  • the array substrate includes one of the second pad groups and a plurality of pad connection circuits corresponding to each of the data sub-pads in the second pad group.
  • Any one of the pad connection circuits includes at least one of the first pad groups, and each of the first pad groups is connected by the connection leads; the first ends of each of the pad connection circuits are connected through the connecting leads are connected to the corresponding data sub-pads;
  • part of the second end of the pad connection circuit is electrically connected to one of the second power supply voltage leads through the connection lead, and the rest of the pads are connected to the second end of the circuit.
  • the terminal is electrically connected to the other second power supply voltage lead through the connecting lead;
  • the chip power supply sub-pad and the chip power supply lead are electrically connected through the connecting lead, and the first power supply sub-pad is electrically connected to the first power supply voltage lead is electrically connected through the connection lead, and the driving data sub-pad and the drive data lead are electrically connected through the connection lead;
  • each of the chip control leads is arranged in a one-to-one correspondence with each of the control area rows, and each control signal sub-pad in any one of the control area rows is controlled by the corresponding chip control
  • the leads are electrically connected through the connecting leads.
  • each of the control signal sub-pads in the i-th row of the control region row and the i-th chip control lead pass through the connection leads are electrically connected;
  • each of the control signal sub-pads in the i-th row of the control region row is electrically connected to the 2N-i+1-th chip control lead through the connection lead;
  • a light-emitting substrate including the above-mentioned array substrate.
  • the light-emitting substrate further includes a plurality of light-emitting elements bound to the plurality of first pad groups in a one-to-one correspondence; and/or,
  • the light-emitting substrate further includes a plurality of microchips bound to each of the second pad groups in a one-to-one correspondence.
  • the light-emitting substrate includes a plurality of the array substrates spliced with each other.
  • the thicknesses of the two ends of the driving lead are different,
  • the light-emitting substrate has a first side and a second side that are oppositely arranged, and each of the array substrates is arranged side by side along the extending direction of the first side; the thicker portion of the driving lead in each of the array substrates is close to The first side of the light-emitting substrate; and the portions of the driving leads in each array substrate with a smaller thickness are all close to the second side of the light-emitting substrate.
  • a method for preparing a light-emitting substrate comprising:
  • a substrate master is provided, the substrate master includes a substrate area on which a plurality of array substrates are to be formed; any one of the substrate areas has a central axis perpendicular to the plane where the substrate area is located;
  • the driving leads and pad layers of each of the array substrates are formed on each of the substrate regions; the driving leads of any one of the array substrates have a first end close to the edge of the substrate mother board and a first end away from the the second end of the edge of the substrate motherboard; the pad layer of any one of the array substrates includes a plurality of first pad groups, and the plurality of first pad groups are oriented with the central axis of the substrate area is the center of symmetry, and the distribution is center-symmetric;
  • a light-emitting element layer is arranged on any one of the array substrates, and the light-emitting element layer includes a plurality of light-emitting elements bound to each of the first pad groups of the array substrate in a one-to-one correspondence;
  • a plurality of the array substrates are spliced into a light-emitting substrate; wherein, in the same light-emitting substrate, each of the array substrates is arranged along an extension direction perpendicular to the driving leads, and the driving leads of each of the array substrates The first ends of each of the array substrates are close to one edge of the light-emitting substrate, and the second ends of the driving leads of each of the array substrates are close to the other edge of the light-emitting substrate.
  • FIG. 1-1 schematically shows a schematic structural diagram of an array substrate in an embodiment of the present disclosure.
  • 1-2 schematically show a schematic structural diagram of a light-emitting substrate in an embodiment of the present disclosure.
  • FIG. 2 schematically shows a schematic diagram of a partial structure of an array substrate in an embodiment of the present disclosure.
  • FIG. 3 schematically shows a schematic diagram of a pin structure of a microchip in an embodiment of the present disclosure.
  • FIG. 4 schematically shows a schematic partial structure diagram of the first metal wiring layer and the first bonding pad in the area A of FIGS. 1-2 .
  • FIG. 5 schematically shows a schematic diagram of the partial structure of the second metal wiring layer, the light-emitting element, and the microchip in the area A of FIGS. 1-2 .
  • Fig. 6 schematically shows a schematic diagram of the partial structure of the region A in Figs. 1-2.
  • FIG. 7 schematically shows a partial structure diagram of the first metal wiring layer and the first bonding pad in the B region in FIGS. 1-2 .
  • FIG. 8 schematically shows a schematic diagram of the partial structure of the second metal wiring layer, the light-emitting element, and the microchip in the B region in FIGS. 1-2 .
  • FIG. 9 schematically shows a schematic diagram of the partial structure of the B region in FIGS. 1-2 .
  • FIG. 10 schematically shows a schematic diagram of the partial structure in the dotted box in FIG. 9 .
  • FIG. 11 schematically shows the connection relationship of the driving leads, the first fan-out leads and the first bonding pads in the area A of FIGS. 1-2 .
  • FIG. 12 schematically shows the connection relationship of the driving leads, the first fan-out leads and the first bonding pads in the B region in FIGS. 1-2 .
  • FIG. 13 schematically shows a schematic structural diagram of preparing a plurality of array substrates on a substrate mother board in an embodiment of the present disclosure.
  • FIG. 14 schematically shows a schematic structural diagram of splicing a plurality of array substrates to each other in an embodiment of the present disclosure.
  • FIG. 15 schematically shows a schematic diagram of a plurality of array substrates spliced to each other in a bad form.
  • FIG. 16 schematically shows a schematic diagram of a plurality of array substrates spliced to each other in a bad form.
  • FIG. 17 schematically shows a schematic structural diagram of a pad connection circuit.
  • FIG. 18 schematically shows a schematic flowchart of a method for manufacturing a light-emitting substrate.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided in order to give a thorough understanding of the embodiments of the present disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed.
  • well-known solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
  • the present disclosure provides an array substrate.
  • the array substrate 100 is polygonal and has at least one set of first side edges 503 and second side edges 504 disposed opposite to each other, and a first side edge 503 disposed close to the first side edge 503 .
  • the shape referred to here refers to the shape of the orthographic projection of the array substrate on the plane where the main surface of the array substrate is located, for example, it can be a rectangle, a square, a rhombus, a regular polygon, etc.; and the second side can be two relatively short sides of a rectangle, or any two opposite sides of a square, a rhombus or a regular polygon; if it is set close to the first side or the second side, it can be understood as being along the first side
  • the edge or the second side is set, and there is a certain distance from the first side or the second side, for example, the value is between 0-1.5 mm.
  • the array substrate includes a base substrate and a pad layer disposed on the main surface of the base substrate, the pad layer includes a plurality of first bonding pads 230 located in the first bonding area 2301, and includes a plurality of first bonding pads 230 located in the second bonding area A plurality of second bond pads 240 within 2401. Any one of the first binding area 2301 and the second binding area 2401 is used for connecting with the driving circuit board to drive the array substrate 100 .
  • both binding areas can be used for connecting with the driving circuit board to drive the array substrate 100 or based on The light-emitting substrate of the array substrate 100 .
  • the driving circuit board can be reused, and then another bonding pad Set the pad to complete the binding again. That is, in the process of removing the driving circuit board, if the first bonding pad 230 is damaged, the second bonding pad 240 can be replaced to bond the driving circuit board without discarding the array substrate 100 . In this way, the overall process yield of the array substrate 100 can be improved, the utilization rate of the array substrate 100 can be improved, and waste caused by discarding the array substrate 100 due to damage to the bonding pads can be avoided.
  • the array substrate includes a base substrate and a pad layer provided on the main surface of the base substrate.
  • the pad layer includes a plurality of first pad groups 210 ; the plurality of first pad groups 210 are distributed symmetrically around the center. In this way, after being rotated by 180° along the symmetry centers of the plurality of first pad groups 210 , the spatial distribution of the plurality of first pad groups 210 will not change.
  • the array The substrate is bound to the circuit board after being rotated 180° along the symmetry centers of the plurality of first pad groups 210 , so that the position of the circuit board is further maintained unchanged under the condition of maintaining the spatial position distribution of each first pad group 210 unchanged.
  • all the first bonding pads 230 and all the second bonding pads 240 are distributed symmetrically in the center; further, all the first bonding pads 230 and all the The center of symmetry of the second bonding pads 240 coincides with the centers of symmetry of all the first pad groups 210 .
  • the pad area has a central axis.
  • the plurality of first pad groups are centrally symmetrically distributed with respect to the central axis of the pad area.
  • the base substrate has a central axis 101
  • the base substrate has a central axis 101 that can be coincident with the central axis of the pad area, so that the plurality of first pad groups 210 are distributed in a center-symmetrical manner with respect to the central axis 101 of the base substrate.
  • the array substrate 100 provided by the present disclosure includes the first pad group 210 distributed symmetrically in the center, and the array substrate 100 can still keep the position of the first pad group 210 unchanged even after the array substrate 100 is rotated along the central axis 101 of the base substrate by 180° .
  • any one of the array substrates 100 can be rotated 180° as required to ensure that the positions of the first pad groups 210 on the spliced array substrate are maintained. remain unchanged, thereby ensuring that the function of the spliced array substrate is not affected by the rotation of a single base substrate.
  • the array substrate 100 provided by the present disclosure has first pad groups 210 distributed centrally symmetrically with respect to the central axis 101 of the base substrate, and each first pad group 210 can be bound and connected to functional devices to form a functional substrate.
  • each functional device of the functional substrate is center-symmetrical with respect to the central axis of the base substrate.
  • any functional substrate is rotated 180° along the central axis of its base substrate without affecting the positional distribution of each functional device on the spliced functional substrate.
  • the functional device can be a current-driven element, for example, a heating element, a light-emitting element, a sound-emitting element, etc., or a photosensitive element, a thermal element, and the like for outputting current or voltage.
  • the first pad group 210 of the array substrate 100 provided by the present disclosure can be used to bind light-emitting elements, for example, can be used to bind miniature light-emitting diodes (including Micro LEDs, Mini LEDs), etc., so that a light-emitting substrate can be formed. . Further, the light-emitting substrates having one array substrate 100 can be spliced with each other to form a larger-sized light-emitting substrate. It can be understood that the first pad group 210 can also be used to bind other sensors, such as temperature sensors, pressure sensors, infrared sensors and other electronic components. In this case, the first pad group 210 can include multiple sub-solders. plate.
  • all of the first pad group 210 may be used to bind micro light emitting diodes, or all of them may be used to bind components such as sensors, or a part of the first pad group 210 may be used to bind micro light emitting diodes, A part is used to bind sensors, and even part of the first pad group 210 may not be bound to any electronic components.
  • the pad layer of the array substrate 100 provided by the present disclosure may further include a third pad for binding other electronic components.
  • the present disclosure does not limit the position and function of the third pad, which can be based on actually needs to be set up.
  • any one of the first pad groups 210 includes a pair of first sub-pads 211 and second sub-pads 212 .
  • the first sub-pad 211 and the second sub-pad 212 can be used for electrical connection with the two electrodes of the light emitting element 900 .
  • the arrangement direction of the first sub-pads 211 and the second sub-pads 212 may be parallel to the extending direction of one edge of the base substrate, or may be parallel to any edge of the base substrate
  • the extending directions of the sub-pads are not parallel; in any two first pad groups 210, the arrangement directions of the first sub-pads 211 and the second sub-pads 212 may be the same or different; this disclosure does not make any special
  • the definition of is based on being able to realize the symmetry of each first pad group 210 with respect to the central axis 101 of the base substrate.
  • each of the first sub-pads 211 and each of the second sub-pads 212 as a whole is symmetrical about the central axis 101 of the base substrate.
  • the pad layer may further include a plurality of second pad groups 220 ; referring to FIG. 5 , any one of the second pad groups 220 is used to connect with a microchip 800 .
  • the light-emitting element 900 and the microchip 800 can be bound on the array substrate 100 to form a light-emitting substrate, and the microchip 800 is used to control the light emission of each light-emitting element 900 .
  • the microchip 800 is an integrated circuit chip with a side length or a diagonal length or a diameter of about 300um or less than 300um.
  • the second pad group 220 may include sub-pads one-to-one corresponding to each pin of the microchip 800 , the number and type of which may be set according to the type and pin of the microchip 800 .
  • any one of the second pad groups 220 at least includes a plurality of data sub-pads 225 for connecting with each output pin 850 of the microchip 800 in a one-to-one correspondence, and the plurality of data sub-pads 225 are also connected to all the output pins 850 of the microchip 800. At least part of the first pad groups of the plurality of first pad groups are connected.
  • the microchip 800 has a chip power supply pin 810 for loading a chip power supply voltage, a first power supply pin 820 for loading a first power supply voltage, A driving data pin 830 for loading driving data, a control signal pin 840 for loading a chip control signal, and a plurality of output pins 850 .
  • any second pad group 220 includes:
  • the chip power supply sub-pad 221 is used to connect with the chip power supply pin 810 of the microchip 800;
  • the first power supply sub-pad 222 is used to connect with the first power supply pin 820 of the microchip 800;
  • the driving data sub-pad 223 is used for connecting with the driving data pin 830 of the microchip 800;
  • the control signal sub-pad 224 is used for connecting with the control signal pin 840 of the microchip 800;
  • a plurality of data sub-pads 225 for connecting with at least part of the plurality of first pad groups.
  • the array substrate 100 is a center-symmetric polygon, having at least one set of first side edges 503 and second side edges 504 arranged opposite to each other, and a first side edge 503 arranged along the first side edge 503 .
  • the binding area 2301 and the second binding area 2401 disposed along the second side 504 .
  • the pad layer also includes a plurality of first bonding pads 230 within the first bonding region 2301 and a plurality of second bonding pads 240 within the second bonding region 2401 . Any one of the first binding area 2301 and the second binding area 2401 is used for connecting with the driving circuit board to drive the array substrate 100 .
  • the inventors found that if the driving leads are fabricated by electroplating, due to process limitations, the thicknesses of the driving leads in different regions are different, that is, the thickness uniformity of the driving leads on the light-emitting substrate is poor. Further, if each light-emitting substrate has only one binding area, when multiple light-emitting substrates are spliced into a large-sized substrate, and the multiple binding areas are located on the same side of the large-sized substrate, the overall uniformity of the substrate is poor. The situation will increase in multiples, which will greatly increase the difficulty of the overall debugging and testing of the substrate, and affect the improvement of the overall reliability of the substrate.
  • both binding areas can be used for connecting with the driving circuit board to drive the array substrate 100 or based on The light-emitting substrate of the array substrate 100 .
  • the binding area used for the array substrate 100 to be bound with the driving circuit board can be changed, so that the driving circuit board is still on the same side of the spliced array substrate 100 .
  • the driving circuit boards of each array substrate 100 may be located on the same side of the spliced array substrate 100, and the first binding area 2301 of each array substrate 100 is used to bind the driving circuits. plate. If one array substrate 100 needs to be rotated 180° along the central axis of the base substrate, after the rotation, the second binding area 2401 of the array substrate 100 can be connected to the driving circuit board, so that the driving circuit of each array substrate 100 The boards are still on the same side of the spliced array substrate 100 .
  • the planar shape of the array substrate 100 is a centrally symmetric polygon, especially the planar shape of the base substrate can be a polygon that is symmetric about its central axis 101 , for example, the shape of the base substrate can be a rectangle, a rhombus, a regular hexagon, and the like. In this way, it can be ensured that after the array substrate 100 is rotated by 180°, there will be no spatial conflict with other array substrates 100 , thereby ensuring effective splicing.
  • the array substrate 100 has a rectangular shape, and has two oppositely arranged long sides and two oppositely arranged side sides 503 / 504 .
  • At least two of the plurality of first bonding pads 230 are respectively used for loading different driving signals; at least two of the plurality of second bonding pads 240 are respectively used to load different driving signals signal; among the plurality of first bonding pads 230 and the plurality of second bonding pads 240, at least one of the plurality of first bonding pads 230 for loading the same kind of driving signal and the plurality of second bonding pads At least one of the fixed pads 240 is symmetrical about the central axis 101 of the base substrate.
  • the first bonding pad 230 and the second bonding pad 240 can be bonded and connected to the same driving circuit board, and there is no need to set two different drivers for the first bonding pad 230 and the second bonding pad 240
  • the circuit board can realize the multiplexing of driving circuit boards, save design, testing and material costs, and reduce the cost of products using the array substrate 100 .
  • the pin sequences on the corresponding driving circuit boards of the first binding area 2301 and the second binding area 2401 are exactly the same, and only one corresponding driving circuit board needs to be designed to meet the requirements of the first binding Any one of the bonding area 2301 and the second bonding area 2401 drives the requirements of the array substrate 100 .
  • the first bonding pad 210 and the second bonding pad 210 for loading the same type of driving signal The fixed pad 220 is symmetrical with respect to the central axis 101 of the base substrate.
  • FIG. 11 shows the distribution of each first bonding pad 230 in the area A in FIG. 1-2
  • FIG. 12 shows the distribution of the first bonding pads 230 in the area B in FIG. 1-2. Distribution of the respective second bond pads 240 .
  • the first bonding pad 230 includes the last second power supply voltage first pad 235 (2N) for loading the second power supply voltage, the last chip power supply voltage for loading the chip power supply voltage A pad 231 (N), a first pad 234 (2N) for loading the last chip control signal of the chip control signal, a first pad 232 (N) for loading the last first power supply voltage ), the penultimate chip control signal first pad 234 (2N-1) for loading the chip control signal, the last driving data first pad 233 (N) for loading the driving data, and the first pad 233 (N) for loading the last driving data.
  • the penultimate second power supply voltage of the two power supply voltages is the first pad 235 (2N-1).
  • the second bonding pad 240 includes a first second power supply voltage second pad 245(1) for loading the second power supply voltage, a first chip power supply voltage for loading the chip power supply voltage Two bonding pads 241(1), a first chip control signal second bonding pad 244(1) for loading a chip control signal, a first first power supply voltage second bonding pad 242 for loading a first power supply voltage (1), the second pad 244(2) for loading the second chip control signal, the second pad 243(1) for loading the first driving data, and the second pad 243(1) for loading the first driving data
  • the second of the two supply voltages is the second supply voltage of the second pad 245(2).
  • the first pad 235(2N) of the second power supply voltage and the second pad 245(1) of the second power supply voltage are symmetrical with respect to the central axis of the base substrate; the first pad 231(N) of the chip power supply voltage and the chip power supply
  • the voltage second pad 241(1) is symmetrical with respect to the central axis of the base substrate; the chip control signal first pad 234(2N) and the chip control signal second pad 244(1) are symmetrical with respect to the central axis of the base substrate;
  • the first pad 232(N) of the first power supply voltage and the second pad 242(1) of the first power supply voltage are symmetrical with respect to the central axis of the base substrate;
  • the first pad 234(2N-1) of the chip control signal is related to the chip control signal
  • the signal second pad 244(2) is symmetrical about the central axis of the base substrate; the driving data first pad 233(N) and the driving data second pad 243(1) are symmetrical about the central axis of the
  • the driving circuit board for bonding with the first bonding pad 230 and the second bonding pad 240 may have a flexible substrate, which may be a flexible circuit board (FPC) or a chip on film (COF) ).
  • FPC flexible circuit board
  • COF chip on film
  • the array substrate 100 further includes a metal wiring layer; referring to FIG. 1-2 and FIG. 2 (the driving leads 320 are filled in the dotted frame), the metal wiring layer includes a plurality of driving leads 320; Centrosymmetric distribution. 1-1, FIG. 2, FIG. 4, FIG. 9 and FIG. 10, the driving lead 320 is used to connect with the first bonding pad 230 and the second bonding pad 240, and is used to load the first bonding pad The respective driving signals of the pads 230 and/or the second bonding pads 240 are transmitted to respective desired regions of the array substrate 100 .
  • the drive leads 320 take the central axis of the base substrate as the center of symmetry and are distributed symmetrically around the center, which can ensure that the distribution of the drive leads 320 remains unchanged after the array substrate 100 rotates 180° along the central axis of the base substrate, thereby avoiding the change of the drive leads 320 Influence on the light-emitting element 900 bound to the first pad group 210 .
  • each of the driving leads 320 takes the central axis 101 of the base substrate as the center of symmetry, and is distributed centrally symmetrically.
  • the number and type of the driving leads 320 may be determined according to the circuit configuration of the array substrate 100 , which is subject to the ability to drive the light-emitting substrate based on the array substrate 100 .
  • the driving lead 320 includes a second power supply voltage lead 325 for loading the second power supply voltage, a chip power supply lead 321 for loading the chip power supply voltage, and a chip control lead 321 for loading the chip control.
  • the chip control lead 324 for the signal, the first power supply voltage lead 322 for loading the first power supply voltage, and the driving data lead 323 for loading the driving data.
  • the first bonding pad 230 includes a second power supply voltage first pad 235 for loading the second power supply voltage, a chip power supply voltage first pad 231 for loading the chip power supply voltage, and a second power supply voltage first pad 231 for loading the chip power supply voltage.
  • the chip control signal first pad 234 for loading the chip control signal, the first power supply voltage first pad 232 for loading the first power supply voltage, and the driving data first pad 233 for loading the driving data.
  • the second bonding pad 240 includes a second power supply voltage second pad 245 for loading the second power supply voltage, a chip power supply voltage second pad 241 for loading the chip power supply voltage, and a chip power supply voltage for loading the chip.
  • the chip control signal second pad 244 for the control signal, the first power supply voltage second pad 242 for loading the first power supply voltage, and the driving data second pad 243 for loading the driving data.
  • each of the first bonding pads 230 and each of the second bonding pads 240 is a full-surface pad whose width is determined according to the size of the load to be driven.
  • the second power supply voltage may be an anode voltage (V LED ) for driving the light-emitting element to emit light.
  • V LED an anode voltage
  • the second power supply voltage of the first pad 235 and the second power supply voltage may be the first pad 235 and the second power supply voltage.
  • the two pads 245 have larger widths.
  • the first power supply voltage may be the reference voltage of the array substrate, for example, may be the ground line voltage (GND).
  • the width of the second pad 242 for a power supply voltage is not less than the width of the first pad 235 for the second power supply voltage, for example, it may be twice the width of the first pad 235 for the second power supply voltage.
  • the chip power supply voltage, the chip control signal and the driving data are all used to control the operation of the chip to control each light-emitting element, and the load is relatively small, so the first pad 231 of the chip power supply voltage and the second pad of the chip power supply voltage are used to control the operation of the chip to control each light-emitting element. 241.
  • the widths of the first pads 233 for driving data, the second pads 243 for driving data, the first pads 234 for chip control signals, and the second pads 244 for chip control signals may be smaller than the widths of the first pads 235 for the second power supply voltage .
  • each of the first bonding pads and each of the second bonding pads may also be composed of one or more bonding electrodes, and there are gaps between the bonding electrodes.
  • the number of bonding electrodes included in each of the first bonding pads and each of the second bonding pads can be adjusted, thereby determining the width of each of the first bonding pads and each of the second bonding pads.
  • a plurality of bonding electrodes arranged at equal intervals along the first side direction may be provided in the first bonding area; one bonding electrode or a plurality of adjacent bonding electrodes may form a first bonding weld pads, and there is no situation where the bonding electrodes are multiplexed between the first bonding pads.
  • a plurality of bonding electrodes arranged at equal intervals along the second side direction may be provided in the second bonding area; one bonding electrode or a plurality of adjacent bonding electrodes may form a second bonding pad, and each bonding pad There is no situation of multiplexing the bonding electrodes between the second bonding pads.
  • both the first pad of the second power supply voltage and the second pad of the second power supply voltage may include multiple binding electrodes, for example, may include 10-20 binding electrodes.
  • each of the second power supply voltage first pad and the second power supply voltage second pad may include 14 bonding electrodes.
  • Each of the first pads of the first power supply voltage and the second pads of the first power supply voltage may include more binding electrodes than the first pads of the second power supply voltage, for example, may include 20 to 40 binding electrodes.
  • the number of bonding electrodes included in each of the first pad of the first power supply voltage and the second pad of the first power supply voltage is 28.
  • the first pad for chip power supply voltage, the second pad for chip power supply voltage, the first pad for driving data, the second pad for driving data, the first pad for chip control signal, and the second pad for chip control signal may each include 1-
  • the three bound electrodes for example, may each include one bound electrode.
  • the second power supply voltage lead 325 is electrically connected to the second power supply voltage first pad 235 and the second power supply voltage second pad 245;
  • the chip power supply lead 321 is electrically connected to the chip power supply voltage first pad 231.
  • the chip power supply voltage second pad 241 is electrically connected;
  • the chip control lead 324 is electrically connected to the chip control signal first pad 234 and the chip control signal second pad 244;
  • the first power supply voltage lead 322 is electrically connected to the first power supply voltage A pad 232 and the second pad 242 of the first power supply voltage are electrically connected;
  • the driving data lead 323 is electrically connected to the first pad 233 of the driving data and the second pad 243 of the driving data.
  • the metal wiring layer further includes a plurality of first fan-out leads 330 for connecting the first bonding area 2301 and the plurality of driving leads 320 .
  • the second fan-out leads 340 are connected to the second bonding area 2401 and the plurality of driving leads 320 .
  • the orthographic projection of the plurality of first fan-out leads 330 on the base substrate and the orthographic projection of the plurality of first pad groups 210 on the base substrate have an overlapping area; the plurality of second fan-out leads 340 are on the substrate. There is an overlapping area between the orthographic projection on the base substrate and the orthographic projection of the plurality of first pad groups 210 on the base substrate.
  • the first bonding pad 230 and the driving lead 320 for loading the same driving signal are connected through the first fan-out lead 330; the second bonding pad for loading the same driving signal
  • the disk 240 and the driving lead 320 are connected through the second fan-out lead 340 .
  • the second power supply voltage lead 325 (2N) for loading the second power supply voltage and the second power supply voltage first pad 235 (2N) are connected through the first fan-out lead 330 for loading
  • the chip power lead 321(N) of the chip power supply voltage is connected to the first pad 231(N) of the chip power supply voltage through the first fan-out lead 330, and the chip control lead 324(2N) for loading the chip control signal is connected with the chip control signal
  • the first pad 234(2N) is connected through the first fan-out lead 330, and the first power supply voltage lead 322(N) for loading the first power supply voltage and the first pad 232(N) of the first power supply voltage pass through the first
  • the fan-out lead 330 is connected, and the chip control lead 324 (2N-1) for loading the chip control signal is connected with the first pad 234 (2N-1) of the chip control signal through the first fan-out lead 330 for loading the driving data.
  • the driving data lead 323(N) of the 100 is connected to the driving data
  • the second power supply voltage lead 325(1) for loading the second power supply voltage and the second power supply voltage second pad 245(1) are connected through the second fan-out lead 340 for
  • the chip power lead 321(1) for loading the chip power supply voltage is connected to the second pad 241(1) of the chip power supply voltage through the second fan-out lead 340, and the chip control lead 324(1) for loading the chip control signal is connected to the chip control
  • the signal second pad 244(1) is connected through the second fan-out lead 340, and the first power supply voltage lead 322(1) for loading the first power supply voltage and the first power supply voltage second pad 242(1) pass through the first power supply voltage lead 322(1).
  • the two fan-out leads 340 are connected, and the chip control lead 324(2) for loading the chip control signal is connected with the second pad 244(2) of the chip control signal through the second fan-out lead 340, and is used for loading the driving data of the driving data
  • the lead 323( 1 ) is connected to the driving data second pad 233( 1 ) through the second fan-out lead 340 .
  • the metal wiring layer includes a first metal wiring layer, a planarization layer and a second metal wiring layer sequentially stacked on the base substrate, and between the first metal wiring layer and the second metal wiring layer Connect via vias through the planarization layer.
  • the first fan-out leads 330 are all located at the first metal wiring layer.
  • the second fan-out lead 340 includes a first lead 341 and a second lead 342 ; the first lead 341 is located at the first metal wiring layer and is electrically connected to the driving lead 320 and the second bonding pad 240
  • the second lead 342 includes at least a first part 3421, a second part 3422 and a third part 3423 connected in sequence; the first part 3421 and the third part 3423 are located at the first metal wiring layer, and the second part 3422 is located at the second metal wiring layer ;
  • the first portion 3421 is electrically connected to the drive lead 320, and the third portion 3423 is electrically connected to the second bonding pad 240.
  • the second lead 342 can avoid the first lead 341 by bridging the first metal wiring layer and the second metal wiring layer.
  • the first fan-out lead 330 has a first straight line segment connected to the driving lead 320 , a second straight line segment connected to the first bonding pad 230 , and the first straight line segment and the second straight line.
  • the first oblique line segment of the segment wherein, the width of the first straight line segment may be the same as the width of the connected driving lead 320; the width of the second straight line segment may be the same as the width of the connected first bonding pad 230; Extending from the end connected with the first straight line segment to the end connected with the second straight line segment, the width of the first oblique line segment uniformly transitions from the width equal to the width of the driving lead 320 to the width equal to the connected first bonding pad 230 . width.
  • the extending direction of the first straight line segment and the second straight line segment is parallel to the extending direction of the driving lead 320, and the extending direction of the first oblique line segment is at an acute angle with the extending direction of the driving lead 320; the first straight segment, the second straight segment and the The width of the first oblique line segment is the dimension in the plane where the array substrate is located and perpendicular to the extending direction of the driving lead 320 . Further, the width of the driving lead 320 is greater than the width of the first bonding pad 230 to which it is connected, so that the width of the first oblique line segment gradually decreases in the direction toward the first side 503 .
  • the second fan-out lead 340 has a third straight line segment connected to the driving lead 320 , a fourth straight line segment connected to the second bonding pad 240 , a third straight line segment connected to and The second oblique line segment of the fourth straight line segment; wherein the width of the third straight line segment may be the same as the width of the connected driving lead 320 ; the width of the fourth straight line segment may be the same as the width of the connected second bonding pad 240 same.
  • the extending directions of the third straight line segment and the fourth straight line segment are parallel to the extending direction of the driving lead 320 .
  • the extending direction of the second oblique line segment forms an acute angle with the extending direction of the driving lead 320; as it extends from the end connected with the third straight line segment to the end connected with the fourth straight line segment, the second oblique line segment
  • the width of the transitions uniformly from being equal to the width of the driving lead 320 to being equal to the width of the connected second bonding pad 240 .
  • the second oblique line segment may include a bottom oblique line segment and a top oblique line segment, wherein the bottom oblique line segment is located on the first metal wiring layer and connects the third straight line segment, and is along two adjacent other second fan-outs
  • the space and size defined by the leads 340 extend to the side close to the second side 504; the top oblique line segment is located in the second metal wiring layer and is connected to the bottom oblique line segment through vias, which may be parallel and/or perpendicular to
  • the extending direction of the driving lead wire extends in a zigzag manner or linearly so as to be connected with the fourth straight line segment through a via hole.
  • the third straight line segment and the bottom oblique line segment form the first part 3421 of the second lead 342
  • the top oblique line segment forms the second part 3422 of the second lead
  • the fourth straight segment forms the third part 3423 of the second lead.
  • the widths of the third straight line segment, the fourth straight line segment, the second oblique line segment of the first lead, and the bottom oblique line segment of the second lead are the dimensions in the plane of the array substrate and perpendicular to the extending direction of the driving lead.
  • the width of the driving lead is greater than the width of the second bonding pad to which it is connected, so that at least part of the second oblique line segment of the first lead and the bottom oblique line segment of the second lead are in the direction toward the second side.
  • the width gradually decreases.
  • the plurality of first bonding pads 230 and the plurality of second bonding pads 240 are symmetrical about the same auxiliary line;
  • the plurality of driving leads 320 include at least one first driving lead group; any one first driving lead group It includes a plurality of first drive leads that are symmetrical about the auxiliary line and used to load the same drive signal; a first lead 341 and a first fan-out lead respectively connected to the plurality of first drive leads in any one of the first drive lead groups 330 is distributed symmetrically in the center; at least one of the plurality of first bonding pads 230 and at least one of the plurality of second bonding pads 240 for loading the same kind of driving signal pass through the first fan-out leads 330 respectively.
  • the second fan-out lead 340 is connected to a plurality of first drive leads in any one of the first drive lead groups. In this way, the design of the array substrate and the preparation of the mask can be facilitated. Especially in the layout design stage of the base substrate, after the layout design of the first fan-out leads is completed, the design layout of each first fan-out lead can be rotated 180° along the central axis of the base substrate to obtain the second fan-out. The design sketch of the lead 340 ; then, fine-tuning is performed on the basis of the design sketch of the second fan-out lead 340 to ensure the connection relationship between the second bonding pad 240 and the driving lead 320 .
  • the fan-out lead sketch serves as the audit layout for the first lead 341 . If a fan-out lead sketch on the design sketch of the second fan-out lead 340 cannot electrically connect the second bonding pad 240 for loading the same kind of drive signal with the drive lead 320, it will be connected by means of bridging.
  • the adjusted and adjusted sketch of the fan-out lead is used as the design layout of the second lead 342 , so that the second bonding pad 240 and the drive lead 320 loaded with the same driving signal can be electrically connected through the second lead 342 .
  • auxiliary line is located in the plane of the base substrate, is perpendicular to the first side 503 and the second side 504 and passes through the central axis 101 of the base substrate.
  • the driving lead 320 includes a plurality of second power supply voltage leads 325 for loading the second power supply voltage, and each second power supply voltage lead 325 is symmetrically arranged with respect to the auxiliary line to form a first power supply voltage lead 325 .
  • a drive lead set Referring to FIG. 4 and FIG. 7 , each of the first leads 341 and each of the first fan-out leads 330 respectively connected to the respective second power supply voltage leads 325 are distributed symmetrically in the center.
  • the driving wires 320 include chip control wires 324 for loading chip control signals, and each chip control wire 324 is symmetrically arranged about the auxiliary line to form a first driving wire group.
  • each first lead 341 and each first fan-out lead 330 respectively connected to each chip control lead 324 are distributed symmetrically in the center.
  • the thickness of the first metal wiring layer is greater than the thickness of the second metal wiring layer; the driving leads 320 are all located on the first metal wiring layer.
  • the body material of the first metal wiring layer includes copper, and the first metal wiring layer may be formed by an electroplating process.
  • the metal wiring layer may further include connection leads 310 for realizing the first pad group 210 (in FIG. 5 , FIG. 6.
  • the connection lead 310 may be located on the second metal wiring layer.
  • the pad layer and the metal wiring layer may be disposed on the same layer, for example, the pad layer and the metal wiring layer may be prepared from the same one or more metal layers.
  • a first pad group 210 obscured by the light emitting element 900 in FIGS. 5 and 8
  • a second pad group 220 blind in FIGS. 5 and 8
  • Each sub-pad in the chip 800 may be disposed on the same layer as the second metal wiring layer, that is, the first pad group 210 and the second pad group 220 may also be regarded as an extension or part of the second metal wiring layer.
  • FIGS. 5 a first pad group 210 (obscured by the light emitting element 900 in FIGS. 5 and 8 ) and a second pad group 220 (blind in FIGS. 5 and 8 )
  • Each sub-pad in the chip 800 may be disposed on the same layer as the second metal wiring layer, that is, the first pad group 210 and the second pad group 220 may also be regarded as an extension or part of the second metal wiring layer.
  • the first bonding pads 230 and the second bonding pads 240 may be disposed on the same layer as the first metal wiring layer, that is, the first bonding pads 230 and the second bonding pads 240 Bond pads 240 may be considered an extension or part of the second metal wiring layer.
  • the metal wiring layer and the pad layer of the array substrate 100 may be formed by the following methods shown in steps S110 to S130.
  • Step S110 referring to FIG. 4 and FIG. 7, forming a first metal wiring layer, a first bonding pad 230 and a second bonding pad 240 on one side of the base substrate; wherein, along the plane perpendicular to the base substrate direction, the first metal wiring layer, the first bonding pad 230 and the second bonding pad 240 at least include a copper seed layer and a copper growth layer stacked in sequence, and the copper growth layer can be prepared by electroplating copper.
  • the step S110 may be implemented in a variety of different methods, as long as the first metal wiring layer, the first bonding pad 230 and the second bonding pad 240 can be prepared.
  • an unpatterned copper seed layer covering the base substrate may be formed first, then copper is deposited by electroplating copper to form an unpatterned copper growth layer, and finally The patterned copper seed layer and the unpatterned copper growth layer are patterned to obtain a first metal wiring layer, a first bond pad 230 and a second bond pad 240 .
  • a patterned copper seed layer may be formed first, then a pattern defining layer covering the base substrate and exposing the copper seed layer may be formed, and then a copper electroplating method is used to form a pattern on the pattern.
  • a patterned copper growth layer is formed on the doped copper seed layer to obtain a first metal wiring layer, a first bonding pad 230 and a second bonding pad 240; the pattern defining layer is removed.
  • an unpatterned copper seed layer covering the base substrate may be formed first, and then a pattern-defining layer is formed on the side of the copper seed layer away from the base substrate, and the pattern-defining layer only needs to be exposed.
  • a patterned copper growth layer is formed on the unpatterned copper seed layer by a method of electroplating copper, and the unpatterned copper seed layer is patterned after removing the pattern defining layer to obtain the first A metal wiring layer, the first bonding pad 230 and the second bonding pad 240 .
  • the first metal wiring layer, the first bonding pad 230 and the second bonding pad 240 may further include materials located between the copper seed layer and the base substrate.
  • the material of the first adhesion metal layer can be molybdenum, molybdenum-copper alloy, molybdenum-niobium alloy, molybdenum-copper-niobium alloy or other metals or metal alloys to improve the first metal wiring layer, the first The bonding strength of the bonding pad 230 and the second bonding pad 240 with the base substrate.
  • the first metal wiring layer, the first bonding pad 230 and the second bonding pad 240 may further include a copper growth layer located far from the base substrate.
  • the first protective metal layer on one side, the material of the first protective metal layer can be metal oxides such as nickel, copper-nickel alloy or indium tin oxide, so as to avoid the first metal wiring layer, the first bonding pad 230 and the second The surface of the bond pad 240 is oxidized.
  • the thickness of the first metal wiring layer may be 1.5-20 microns, and in some embodiments, may be 2-10 microns.
  • Step S120 forming a planarization layer, the planarization layer is located on the side of the first metal wiring layer, the first bonding pad 230 and the second bonding pad 240 away from the base substrate, and has an exposed part of the first metal wiring layer , at least part of the first bonding pad 230 and at least part of the via hole of the second bonding pad 240 .
  • the via hole is used for the electrical connection between the second metal wiring layer and the first metal wiring layer, and for the electrical connection between the driving circuit board and the first bonding pad 230 and the second bonding pad 240 .
  • planarization layer is opened at positions corresponding to the first bonding pads 230 and the second bonding pads 240 to expose part or all of the surfaces of the first bonding pads 230 and the second bonding pads 240 , to be bound and connected with the golden finger structure of the drive circuit board.
  • the material of the planarization layer may be an organic material, especially a photosensitive organic material, for example, a phenolic resin or a curable acrylic resin.
  • a passivation layer may also be formed, and the passivation layer is located on the side of the first metal wiring layer, the first bonding pad 230 and the second bonding pad 240 away from the base substrate, And the via hole on the planarization layer also penetrates the passivation layer.
  • the material of the passivation layer may be silicon nitride to prevent the first metal wiring layer, the first bonding pad 230 and the second bonding pad 240 from being oxidized.
  • Step S130 a metal layer is formed on the side of the planarization layer away from the base substrate, and then the metal layer is patterned to form a second metal wiring layer, a first pad group 210 and a second pad group 220 .
  • the second metal wiring layer, the first pad group 210 and the second pad group 220 may include a second adhesion metal layer and a copper metal layer.
  • the material of the second adhesion metal layer may be molybdenum, molybdenum-copper alloy, molybdenum-niobium alloy, molybdenum-copper-niobium alloy or other metals or metal alloys.
  • the second metal wiring layer, the first pad group 210 and the second pad group 220 may further include a second protective metal layer, and the material of the second protective metal layer may be It is a metal oxide such as nickel, copper-nickel alloy or indium zinc oxide, so as to avoid oxidation on the surfaces of the first metal wiring layer, the first bonding pad 230 and the second bonding pad 240, and improve the connection between the light-emitting element 900, Bonding strength of the microchip 800 .
  • the preparation method of the array substrate may further include step S140 , forming an organic protective layer on the side of the second metal wiring layer away from the base substrate, and the organic protective layer exposes at least part of the surface and the surface of each of the first bonding pads 230 . At least part of the surface of each of the second bonding pads 240 is also exposed at least part of the surface of each of the first pad groups 210 and at least part of the surface of the second pad group 220 .
  • the organic protective layer may be formed by screen printing green oil.
  • the preparation method of the array substrate may further include step S150, forming a protective metal layer on the surface of each first pad group 210 and each second pad group 220, and the material of the protective metal layer may be nickel, copper-nickel alloy Or metal oxides such as indium zinc oxide.
  • the difference in thickness of the driving leads 320 at different positions does not exceed 150%.
  • the thickness of the thickest position of the driving wire 320 may not exceed 2.5 times the thickness of the thinnest position of the driving wire 320 to avoid reliability problems caused by excessive thickness difference of the driving wire 320 at different positions.
  • the difference in thickness of the driving wire 320 at different positions does not exceed 100%, that is, the thickness of the thickest position of the driving wire 320 may not exceed twice the thickness of the thinnest position of the driving wire 320 .
  • the difference in thickness of the driving leads 320 at different positions is formed during the process of preparing the driving leads 320 by the electroplating process, rather than deliberately designed. If the copper electroplating process is used in the preparation process of the array substrate 100 , the thickness of the copper growth layer at different positions will be different. The difference will have a certain impact on the debugging and reliability of the array substrate 100 , and when the difference is too large, it may lead to difficulty in debugging or a reliability defect.
  • the thicknesses of the two ends of the driving leads 320 are different; Further, the thickness of the thicker end of the driving lead 320 is more than 50% greater than the thickness of the thinner end of the driving lead 320.
  • the thickness of the thicker end of the driving lead 320 may be 7.5 micrometers or more, for example, 10 micrometers.
  • the thickness of the thinner end of the driving lead 320 may be about 5 microns.
  • the thicker end of the driving lead 320 of the array substrate 100 may be defined as the first end 501 of the array substrate 100
  • the thinner end of the driving lead 320 of the array substrate 100 may be defined as the second end 502 of the array substrate 100 .
  • the array substrate 100 can be rotated by 180°, referring to FIG. 14 , so that the first end 501 of each array substrate 100 is located in the spliced array On the same side of the substrate 100 , the thickness distribution of the driving leads 320 on the spliced array substrate 100 can be made regular, which facilitates debugging and improves reliability.
  • the utilization rate of the substrate motherboard 600 when four array substrates 100 are spliced into a large-sized substrate is lower than that of two array substrates.
  • the utilization rate of the substrate motherboard 600 can be increased from 55% to more than 80%.
  • one substrate motherboard 600 may include six substrate regions to be prepared to form the array substrate 100 , and the substrate regions correspond to the substrate substrates of the array substrate 100 .
  • the six array substrates 100 are arranged in two rows and three columns.
  • any row includes three array substrates 100 arranged along the side direction 505 of the array substrate 100
  • any column includes two array substrates arranged along the long side direction 506 of the array substrate 100 .
  • Substrate 100 .
  • the array substrate 100 includes a first end 501 close to the edge of the base substrate 600 and a second end 502 close to the middle of the base base 600 . Since the film forming process and the patterning process are performed on the same substrate mother board 600 , and the mask used in the patterning process is inconvenient to rotate, the pattern of the film layers prepared in each area of the array substrate 100 is exactly the same.
  • the film pattern of the first end 501 of the array substrate 100 (1, 1), the film pattern of the first end 501 of the array substrate 100 (1, 2), the first end of the array substrate 100 (1, 3) The film layer pattern of 501, the film layer pattern of the second end 502 of the array substrate 100 (2, 1), the film layer pattern of the second end 502 of the array substrate 100 (2, 2), the array substrate 100 (2, 3)
  • the film pattern of the second end 502 of the array substrate 100(1,1) is the same; the film pattern of the second end 502 of the array substrate 100(1,1), the film pattern of the second end 502 of the array substrate 100(1,2), the array substrate 100
  • the film layer pattern of the second end 502 of (1,3), the film layer pattern of the first end 501 of the array substrate 100 (2,1), the film layer pattern of the first end 501 of the array substrate 100 (2,2) , the film pattern of the first end 501 of the array substrate 100 ( 2 , 3 ) is the same.
  • the copper growth layer at the first end 501 of each array substrate 100 is likely to be thick and the copper growth layer at the second end 502 is thin.
  • the distance between the first end 501 of the array substrate 100 and the edge of the substrate motherboard 600 is very small, for example, it can be as small as 11.5 mm. , which results in a large thickness difference of the driving lead 320 along its extending direction.
  • the array substrates 100 of the present disclosure can be rotated by 180° during splicing, so that the first ends 501 of each array substrate 100 can be located on the same side of the array substrates 100 to be spliced.
  • the array substrate 100 ( 2 , 1 ) and the array substrate 100 ( 2 , 2 ) can be rotated by 180° and then spliced with the array substrate 100 ( 1 , 1 ) and the array substrate 100 ( 1 , 2 ), and further The first ends 501 of two adjacent array substrates are adjacent, and the second ends 502 of two adjacent array substrates are adjacent.
  • the thickness of the driving leads of the spliced substrates is basically uniform; in the direction of the long side of the array substrate, the thickness of the driving leads of the spliced substrates is basically regular thickening or thin. This can make commissioning of spliced substrates easier and easier to locate and eliminate reliability issues.
  • the array substrate 100 is rectangular, has a plurality of control areas 400 distributed in an array, and each control area 400 forms N control area columns 410 arranged along the side direction 505 , and forms 2N control area rows 420 arranged along the longitudinal direction 506; wherein, N is a positive integer.
  • the array substrate 100 further includes a metal wiring layer, and the metal wiring layer includes a plurality of connecting leads 310 and a plurality of driving leads 320 extending along the longitudinal direction.
  • the driving lead 320 includes two second power supply voltage leads 325 for loading the second power supply voltage, and one chip power supply for loading the chip power supply voltage Leads 321, two chip control leads 324 for loading chip control signals, one first power supply voltage lead 322 for loading a first power supply voltage, and one driving data lead 323 for loading driving data.
  • the array substrate 100 includes a second pad group 220 and a plurality of pad connection circuits 401 corresponding to each data sub-pad 225 in the second pad group 220 one-to-one .
  • any one pad connection circuit 401 includes at least one first pad group 210 , and each of the first pad groups 210 is connected by connecting leads 310 ; the first end of each pad connecting circuit 401 is connected to the The corresponding data sub-pads 225 are connected, and the second end of the pad connection circuit 401 is electrically connected to the second power supply voltage lead 325 through the connection lead 310 .
  • the first pad group 210 on any one of the pad connection circuits 401 can be bound to the light-emitting element 900 to form the light-emitting circuit 402 .
  • the second end of part of the pad connection circuit 401 is electrically connected to a second power supply voltage lead 325 through the connection lead 310 , and the remaining pads are connected to the second end of the circuit 401 . It is electrically connected to another second power supply voltage lead 325 through the connection lead 310 .
  • the chip power supply sub-pad 221 and the chip power supply lead 321 are electrically connected through the connecting lead 310
  • the first power supply sub-pad 222 and the first power supply voltage lead 322 are electrically connected through the connecting lead 310
  • the driving data sub-pad 223 and the driving data lead 323 are electrically connected Electrically connected by connecting leads 310 .
  • each chip control lead 324 is arranged in a one-to-one correspondence with each control area row 420 , and each control signal sub-pad 224 in any one control area row 420 is associated with the corresponding chip control lead 324 is electrically connected by connecting leads 310 .
  • two adjacent second power supply voltage leads 325 may be close to the first bonding pad 230 or the second bonding pad 240 locations are connected to each other.
  • two first fan-out leads 330 connected to two adjacent second power supply voltage leads 325 may be connected to each other to form a fan-out lead, and two adjacent second power supply voltage leads 325 are connected to each other to form one fan-out lead.
  • the second fan-out leads 340 may be connected to each other to form a fan-out lead.
  • two second power supply voltage first pads 235 connected to two adjacent second power supply voltage leads 325 may be connected to each other to form one second power supply voltage first pad 235, which is connected to the adjacent two second power supply voltage first pads 235.
  • Two second power supply voltage second pads 245 connected to the second power supply voltage leads 325 may be connected to each other to form one second power supply voltage second pad 245 .
  • control area column 410(N) and the control area column 410(N-1) are two adjacent control area columns 410 .
  • the second power supply voltage lead 325 (2N-1) and the two first fan-out leads 330 connected to the second power supply voltage lead 325 (2N-2) are connected to each other and merged into a wider first fan-out lead 330 .
  • the second power supply voltage first pad 235 (2N-1) and the second power supply voltage first pad 235 (2N-1) connected to the second power supply voltage lead 325 (2N-1) and the second power supply voltage lead 325 (2N-2) 235 (2N-2) are connected to each other and merged into a second power supply voltage first pad 235 with a larger width.
  • control area column 410( 1 ) and the control area column 410( 2 ) are two adjacent control area columns 410 .
  • the two second fan-out leads 340 connected to the second power supply voltage lead 325( 2 ) and the second power supply voltage lead 325 ( 3 ) are connected to each other to form a second fan-out lead 340 with a larger width.
  • the second supply voltage second pad 245(2) and the second supply voltage second pad 245(3) to which the second supply voltage lead 325(2) and the second supply voltage lead 325(3) are connected are connected to each other And merged into a second power supply voltage second pad 245 with a larger width.
  • the first metal wiring layer may be provided with a hollow area between two adjacent second power supply voltage leads 325, so as to avoid that the metal area of the first metal wiring layer accounts for too much and affects subsequent processes such as exposure.
  • the first metal wiring layer is hollowed out between the second supply voltage lead 325(2) and the second supply voltage lead 325(3).
  • each control signal sub-pad in the i-th control region row is electrically connected to the i-th chip control lead through connecting leads; or, in the array substrate, in the i-th control region row
  • Each of the control signal sub-pads is electrically connected to the 2N-i+1th chip control lead through connecting leads; wherein, 1 ⁇ i ⁇ 2N, and i is a positive integer.
  • the control area columns and the respective driving leads are arranged in sequence along the lateral direction; the control area rows are sequentially arranged along the longitudinal direction.
  • the first bonding pad 230 and the second bonding pad 240 of the array substrate 100 can be applied to the same driving circuit board and the same driving sequence, which reduces the development cost of the driving circuit board.
  • a second power supply voltage lead 325 , a driving data lead 323 , a chip control lead 324 , a first power supply voltage lead 322 , and a chip control lead 324 extend along the side direction 505 of the array substrate 100 , and the widths of the driving data lead 323 and the chip power lead 321 are substantially the same.
  • the first fan-out lead 330 is located at the first metal wiring layer, and the driving lead 320 for loading the same driving signal and the first bonding pad 230 are connected through the first fan-out lead 330 .
  • the second fan-out lead 340 includes a first lead 341 and a second lead 342 ; the first lead 341 is located at the first metal wiring layer and is used to load the first power supply voltage The second bonding pad 240 and the first power supply voltage lead 322 are electrically connected through the first lead 341 , and the second binding pad 240 for loading the chip control signal and the chip control lead 324 are electrically connected through the first lead 341 .
  • the second bonding pad 240 loaded with the second power supply voltage and the second power supply voltage lead 325 are electrically connected through the first lead 341;
  • the second lead 342 at least includes a first part 3421, a second part 3422 and a third part connected in sequence 3423;
  • the first part 3421 and the third part 3423 are located on the first metal wiring layer, and the second part 3422 is located on the second metal wiring layer;
  • the second bonding pad 240 and the chip power lead 321 for loading the chip power supply voltage pass through the first
  • the two leads 342 are electrically connected;
  • the second bonding pad 240 for loading driving data and the chip power lead 321 are electrically connected through the driving data lead 323 .
  • the second lead 342 may include a driving data fan-out lead connecting the second pad 243 of the driving data and the driving data lead 323, and a second pad 241 and the second pad 241 connecting the chip power supply voltage.
  • Two supply voltage pins 325 are chip supply voltage fanout pins.
  • the first part 3611 and the third part 3613 of the driving data fan-out lead are respectively located on the first metal wiring layer, and the second part 3612 is located on the second metal wiring layer.
  • the first part 3511 and the third part 3513 of the chip power supply voltage fan-out lead are respectively located on the first metal wiring layer, and the second part 3512 is located on the second metal wiring layer.
  • the second portion 3612 of the driving data fan-out lead and the second portion 3512 of the chip power supply voltage fan-out lead extend along the side direction 505 of the array substrate 100 .
  • FIG. 5 the light-emitting element 900 is bound on the first pad group 210
  • FIG. 8 the light-emitting element 900 is bound on the first pad group 210
  • the array substrate 100 includes four pad connection circuits 401 ; correspondingly, the second pad group 220 (on which the microchip 800 is bound) includes four data sub-pads 225 .
  • any pad connection circuit 401 includes four first pad groups 210 , and the first sub-pads 211 of the first first pad group 210 ( 1 ) are connected to the second power supply through the connection leads 310
  • the voltage lead 325 is connected, and the second sub-pad 212 of the first first pad group 210(1) is connected to the first sub-pad 211 of the second first pad group 210(2) through the connecting lead 310
  • the lead 310 is connected, and the second sub-pad 212 of the second first pad group 210 ( 2 ) is connected to the first sub-pad 211 of the third first pad group 210 ( 3 ) through the connecting lead 310 310 is connected, and the second sub-pad 212 of the third first pad group 210 ( 3 ) is connected to the first sub-pad 211 of the fourth first pad group 210 ( 4 ) through the connection wire 310
  • the second sub-pads 212 of the fourth first pad group 210 ( 4 ) are connected to the corresponding data sub-pads 225 through the connection wires 310
  • a microchip 800 and four light-emitting circuits 402 are arranged in a control area 400 , and any one of the light-emitting circuits 402 includes a connection through a pad Circuits 401 are connected in series with four light-emitting elements 900; the microchip 800 can control the four light-emitting circuits 402 to emit light independently.
  • N 12. In this way, a suitable array substrate 100 can be prepared, so that the array substrate 100 can be applied to a 75-inch liquid crystal display device.
  • Embodiments of the present disclosure further provide a light-emitting substrate, where the light-emitting substrate includes any one of the light-emitting substrates described in the foregoing embodiments of the array substrate 100 .
  • the light-emitting substrate can be a lighting lamp, a Micro LED display panel, a light panel of a liquid crystal display device, or the like. Since the light-emitting substrate has any of the array substrates 100 described in the above-mentioned embodiments of the array substrate 100 , it has the same beneficial effects, and details are not described herein again.
  • the light-emitting substrate further includes a plurality of light-emitting elements 900 bound to each of the first pad groups 210 in one-to-one correspondence.
  • the light emitting substrate further includes a plurality of microchips 800 bound to each of the second pad groups 220 in a one-to-one correspondence.
  • the microchip 800 is used to drive the light-emitting elements 900 of the light-emitting substrate to emit light.
  • the light-emitting substrate includes a plurality of array substrates 100 spliced with each other. In this way, a larger size spliced light-emitting substrate can be obtained by splicing.
  • the light-emitting substrate has a first side 710 and a second side 720 arranged opposite to each other.
  • the extending directions of the first sides 710 are arranged side by side; the parts of the array substrates 100 with the larger thicknesses of the driving leads 320 are close to the first side 710 of the light-emitting substrate; the parts of the array substrates 100 with the smaller thicknesses of the driving leads 320 are Both are close to the second side 720 of the light-emitting substrate.
  • the thicknesses of the respective driving leads 320 can be uniformly changed, thereby improving the adjustability and reliability of the light-emitting substrates.
  • the present disclosure also provides a method for preparing a light-emitting substrate.
  • the method for preparing a light-emitting substrate includes:
  • a substrate mother board 600 is provided.
  • the substrate mother board 600 includes a plurality of substrate regions on which the array substrate 100 is to be formed; any one of the substrate regions has a central axis 101 perpendicular to the plane where the substrate region is located. ;
  • Step S220 the driving leads and pad layers of each array substrate 100 are formed on each base substrate; the driving leads of any array substrate 100 have a first end 501 close to the edge of the substrate motherboard 600 and a first end 501 away from the substrate motherboard 600 The second end 502 of the edge; the pad layer of any one of the array substrates 100 includes a plurality of first pad groups 210, and the plurality of first pad groups 210 take the central axis of the substrate area as the center of symmetry, and are distributed in a center-symmetric manner ;
  • Step S230 cutting the substrate motherboard 600 to obtain each array substrate 100;
  • Step S240 a light-emitting element layer is provided on any one of the array substrates 100 , and the light-emitting element layer includes a plurality of light-emitting elements 900 bound in a one-to-one correspondence with each of the first pad groups 210 of the array substrate 100 ;
  • Step S250 referring to FIG. 14 , splicing a plurality of array substrates 100 into a light-emitting substrate; wherein, in the same light-emitting substrate, each array substrate 100 is arranged along the extending direction perpendicular to the driving lead 320 , and the driving lead 320 of each array substrate 100 The first ends of each of the array substrates 100 are close to one edge of the light-emitting substrate, and the second ends of the driving leads 320 of each array substrate 100 are close to the other edge of the light-emitting substrate.
  • the utilization rate of the substrate mother board 600 can be improved, and the defects of complicated debugging and reduced reliability caused by uneven thickness of the driving lead 320 can be overcome.
  • the mother substrate 600 may be a glass substrate. It can be understood that, for each array substrate, only one of the first binding area and the second binding area is used for connecting with the driving circuit board to drive the array substrate, and not connected with the driving circuit board. To connect the other, the bonding area can be covered with an insulating layer or the connection between the bonding pads and the driving leads in the bonding area can be cut off by laser, so as to prevent the introduction of static charges from affecting the yield and use of the array substrate life.

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Abstract

本公开涉及一种发光基板及其制备方法、阵列基板，涉及显示技术领域。该阵列基板呈多边形且具有至少一组相对设置的第一侧边和第二侧边，以及具有靠近所述第一侧边设置的第一绑定区和靠近所述第二侧边设置的第二绑定区；所述阵列基板包括衬底基板和设于所述衬底基板主表面的焊盘层，所述焊盘层包括位于所述第一绑定区内的多个第一绑定焊盘，以及包括位于所述第二绑定区内的多个第二绑定焊盘；所述第一绑定区和所述第二绑定区中的任意一个，用于与驱动电路板连接以驱动所述阵列基板。该阵列基板能够避免绑定焊盘损伤而废弃阵列基板。

Description

发光基板及其制备方法、阵列基板 技术领域
本公开涉及显示技术领域，尤其涉及一种发光基板及其制备方法、阵列基板。
背景技术
在Micro LED(微发光二极管)发光基板、Mini LED(迷你发光二极管)发光基板的制备过程中，为了满足发光二极管对较大电流的需求和降低驱动引线上的压降，可以增加驱动引线的厚度或宽度来降低电阻。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种发光基板及其制备方法、阵列基板，避免绑定焊盘损伤而废弃整个阵列基板。
根据本公开的一个方面，提供一种阵列基板，其中，所述阵列基板呈多边形且具有至少一组相对设置的第一侧边和第二侧边，以及具有靠近所述第一侧边设置的第一绑定区和靠近所述第二侧边设置的第二绑定区；
所述阵列基板包括衬底基板和设于所述衬底基板主表面的焊盘层，所述焊盘层包括位于所述第一绑定区内的多个第一绑定焊盘，以及包括位于所述第二绑定区内的多个第二绑定焊盘；所述第一绑定区和所述第二绑定区中的任意一个，用于与驱动电路板连接以驱动所述阵列基板。
在本公开的一种示例性实施例中，所述焊盘层还包括多个第一焊盘组；所述多个第一焊盘组呈中心对称分布。
在本公开的一种示例性实施例中，任意一个所述第一焊盘组包括成对设置第一子焊盘和第二子焊盘。
在本公开的一种示例性实施例中，所述焊盘层还包括多个第二焊盘组，任意一个所述第二焊盘组用于与一微芯片连接。
在本公开的一种示例性实施例中，任意一个所述第二焊盘组包括：
多个数据子焊盘，用于与所述多个第一焊盘组的至少部分第一焊盘组连接。
在本公开的一种示例性实施例中，所述多个第一绑定焊盘中的至少两个分别用于加载不同的驱动信号；所述多个第二绑定焊盘中的至少两个分别用于加载不同的驱动信号；
所述多个第一绑定焊盘和所述多个第二绑定焊盘中，用于加载同种驱动信号 的所述多个第一绑定焊盘中的至少一个和所述多个第二绑定焊盘中的至少一个，关于所述衬底基板的中心轴对称。
在本公开的一种示例性实施例中，所述阵列基板还包括金属布线层；
所述金属布线层包括多个驱动引线；所述多个驱动引线呈中心对称分布。
在本公开的一种示例性实施例中，所述金属布线层还包括用于连接所述第一绑定区和所述多个驱动引线的多个第一扇出引线、用于连接所述第二绑定区和所述多个驱动引线的多个第二扇出引线；所述多个第一扇出引线在所述衬底基板上的正投影和所述多个第一焊盘组在所述衬底基板上的正投影存在交叠区域；所述多个第二扇出引线在所述衬底基板上的正投影和所述多个第一焊盘组在所述衬底基板上的正投影存在交叠区域。
在本公开的一种示例性实施例中，所述金属布线层包括依次层叠于所述衬底基板的第一金属布线层、平坦化层和第二金属布线层，所述第一金属布线层和所述第二金属布线层之间通过贯穿所述平坦化层的过孔连接；
所述第一扇出引线均位于所述第一金属布线层；
所述第二扇出引线包括第一引线和第二引线；所述第一引线位于所述第一金属布线层，且与所述驱动引线和第二绑定焊盘电连接；所述第二引线至少包括依次连接的第一部分、第二部分和第三部分；所述第一部分和所述第三部分位于所述第一金属布线层，且所述第二部分位于所述第二金属布线层；所述第一部分与所述驱动引线电连接，所述第三部分与所述第二绑定焊盘电连接。
在本公开的一种示例性实施例中，所述多个第一绑定焊盘和所述多个第二绑定焊盘均关于同一辅助线对称；
所述多个驱动引线包括至少一个第一驱动引线组；任意一个所述第一驱动引线组包括关于所述辅助线对称、用于加载相同驱动信号的多个第一驱动引线；
分别与任意一个所述第一驱动引线组中的所述多个第一驱动引线相连接的所述第一引线和所述第一扇出引线呈中心对称分布。
在本公开的一种示例性实施例中，所述第一金属布线层的厚度大于所述第二金属布线层的厚度；所述驱动引线均位于所述第一金属布线层。
在本公开的一种示例性实施例中，沿所述阵列基板的长边方向，所述驱动引线在不同位置处的厚度差异不超过150％。
在本公开的一种示例性实施例中，沿所述阵列基板的长边方向，所述驱动引线两端的厚度不同；其中，所述驱动引线较厚一端的厚度，比所述驱动引线较薄一端的厚度大10％以上。
在本公开的一种示例性实施例中，所述阵列基板呈矩形，具有阵列分布的多个控制区域，且各个控制区域形成沿侧边方向排列的N个控制区域列，以及形成沿 长边方向排列的2N个控制区域行；其中，N为正整数；
任意一个所述第二焊盘组还包括用于与所述微芯片的芯片电源引脚连接的芯片电源子焊盘、用于与所述微芯片的第一电源引脚连接的第一电源子焊盘、用于与所述微芯片的驱动数据引脚连接的驱动数据子焊盘、用于与所述微芯片的控制信号引脚连接的控制信号子焊盘；
所述阵列基板还包括金属布线层，所述金属布线层包括多个连接引线和多个沿所述长边方向延伸的驱动引线；
在任意一个所述控制区域列内，所述驱动引线包括两根用于加载第二电源电压的第二电源电压引线、一根用于加载芯片电源电压的芯片电源引线、两根用于加载芯片控制信号的芯片控制引线、一根用于加载第一电源电压的第一电源电压引线和一根用于加载驱动数据的驱动数据引线；
在任意一个所述控制区域内，所述阵列基板包括一个所述第二焊盘组和与所述第二焊盘组中的各个所述数据子焊盘一一对应的多个焊盘连接电路；任意一个所述焊盘连接电路包括至少一个所述第一焊盘组，且各个所述第一焊盘组通过所述连接引线连接；各个所述焊盘连接电路的第一端通过所述连接引线与对应的所述数据子焊盘连接；
其中，在任意一个所述控制区域内，部分所述焊盘连接电路的第二端与一根所述第二电源电压引线通过所述连接引线电连接，其余所述焊盘连接电路的第二端与另一根所述第二电源电压引线通过所述连接引线电连接；所述芯片电源子焊盘与所述芯片电源引线通过所述连接引线电连接，所述第一电源子焊盘与所述第一电源电压引线通过所述连接引线电连接，所述驱动数据子焊盘与所述驱动数据引线通过所述连接引线电连接；
在所述阵列基板中，各个所述芯片控制引线与各个所述控制区域行一一对应设置，且任意一个所述控制区域行中的各个的控制信号子焊盘均与对应的所述芯片控制引线通过所述连接引线电连接。
在本公开的一种示例性实施例中，在所述阵列基板中，第i行所述控制区域行中的各个所述控制信号子焊盘均与第i根所述芯片控制引线通过所述连接引线电连接；或者，
在所述阵列基板中，第i行所述控制区域行中的各个所述控制信号子焊盘均与第2N-i+1根所述芯片控制引线通过所述连接引线电连接；
其中，1≤i≤2N，且i为正整数。
根据本公开的一个方面，提供一种发光基板，包括上述的阵列基板。
在本公开的一种示例性实施例中，所述发光基板还包括与所述多个第一焊盘组一一对应绑定的多个发光元件；和/或，
所述发光基板还包括与各个所述第二焊盘组一一对应绑定的多个微芯片。
在本公开的一种示例性实施例中，所述发光基板包括多个相互拼接的所述阵列基板。
在本公开的一种示例性实施例中，沿所述阵列基板的长边方向，驱动引线两端的厚度不同，
所述发光基板具有相对设置的第一边和第二边，各个所述阵列基板沿所述第一边的延伸方向并排排列；各个阵列基板中所述驱动引线的厚度较大的部分，均靠近所述发光基板的第一边；各个阵列基板中所述驱动引线的厚度较小的部分，均靠近所述发光基板的第二边。
根据本公开的一个方面，提供一种发光基板的制备方法，包括：
提供一衬底母板，所述衬底母板包括待形成多个阵列基板的衬底区域；任意一个所述衬底区域具有垂直于所述衬底区域所在平面的中心轴；
在各个所述衬底区域上形成各个所述阵列基板的驱动引线和焊盘层；任意一个所述阵列基板的所述驱动引线具有靠近所述衬底母板边缘的第一端和远离所述衬底母板边缘的第二端；任意一个所述阵列基板的所述焊盘层包括多个第一焊盘组，且多个所述第一焊盘组以所述衬底区域的中心轴为对称中心，呈中心对称分布；
切割所述衬底母板，以获得各个所述阵列基板；
在任意一个所述阵列基板上设置发光元件层，所述发光元件层包括与所述阵列基板的各个所述第一焊盘组一一对应地绑定的多个发光元件；
将多个所述阵列基板拼接成发光基板；其中，在同一所述发光基板中，各个所述阵列基板沿垂直于所述驱动引线的延伸方向排列，且各个所述阵列基板的所述驱动引线的第一端均靠近所述发光基板的一边缘，各个所述阵列基板的所述驱动引线的第二端均靠近所述发光基板的另一边缘。
本公开的其他特性和优点将通过下面的详细描述变得显然，或部分地通过本公开的实践而习得。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1-1示意性示出本公开一种实施方式中的阵列基板的结构示意图。
图1-2示意性示出本公开一种实施方式中的发光基板的结构示意图。
图2示意性示出本公开一种实施方式中的阵列基板的局部结构示意图。
图3示意性示出本公开一种实施方式中的微芯片的引脚结构示意图。
图4示意性示出图1-2中A区域的第一金属布线层和第一绑定焊盘的局部结构示意图。
图5示意性示出图1-2中A区域的第二金属布线层和发光元件、微芯片的局部结构示意图。
图6示意性示出图1-2中A区域的局部结构示意图。
图7示意性示出图1-2中B区域的第一金属布线层和第一绑定焊盘的局部结构示意图。
图8示意性示出图1-2中B区域的第二金属布线层和发光元件、微芯片的局部结构示意图。
图9示意性示出图1-2中B区域的局部结构示意图。
图10示意性示出图9中虚线框中的局部结构示意图。
图11示意性示出图1-2中A区域的驱动引线、第一扇出引线和第一绑定焊盘的连接关系。
图12示意性示出图1-2中B区域的驱动引线、第一扇出引线和第一绑定焊盘的连接关系。
图13示意性示出本公开一种实施方式中在一衬底母板上制备多个阵列基板的结构示意图。
图14示意性示出本公开一种实施方式中将多个阵列基板相互拼接的结构示意图。
图15示意性示出一种多个阵列基板以不良的形式相互拼接的示意图。
图16示意性示出一种多个阵列基板以不良的形式相互拼接的示意图。
图17示意性示出一种焊盘连接电路的结构示意图。
图18示意性示出一种发光基板的制备方法的流程示意图。
图中主要元件附图标记说明如下：
100、阵列基板；101、阵列基板的中心轴；210、第一焊盘组；211、第一子焊盘；212、第二子焊盘；220、第二焊盘组；221、芯片电源子焊盘；222、第一电源子焊盘；223、驱动数据子焊盘；224、控制信号子焊盘；225、数据子焊盘；2301、第一绑定区；230、第一绑定焊盘；231、芯片电源电压第一焊盘；232、第一电源电压第一焊盘；233、驱动数据第一焊盘；234、芯片控制信号第一焊盘；235、第二电源电压第一焊盘；2401、第二绑定区；240、第二绑定焊盘；241、芯 片电源电压第二焊盘；242、第一电源电压第二焊盘；243、驱动数据第二焊盘；244、芯片控制信号第二焊盘；245、第二电源电压第二焊盘；310、连接引线；320、驱动引线；321、芯片电源引线；322、第一电源电压引线；323、驱动数据引线；324、芯片控制引线；325、第二电源电压引线；330、第一扇出引线；340、第二扇出引线；341、第一引线；342、第二引线；3421、第二引线的第一部分；3422、第二引线的第二部分；3423、第二引线的第三部分；3511、芯片电源电压扇出引线的第一部分；3512、芯片电源电压扇出引线的第二部分；3513、芯片电源电压扇出引线的第三部分；3611、驱动数据扇出引线的第一部分；3612、驱动数据扇出引线的第二部分；3613、驱动数据扇出引线的第三部分；400、控制区域；410、控制区域列；420、控制区域行；401、焊盘连接电路；402、发光电路；501、阵列基板的第一端；502、阵列基板的第二端；503、阵列基板的第一侧边；504、阵列基板的第二侧边；505、阵列基板的侧边方向；506、阵列基板的长边方向；600、衬底母板；710、发光基板的第一边；720、发光基板的第二边；800、微芯片；810、芯片电源引脚；820、第一电源引脚；830、驱动数据引脚；840、控制信号引脚；850、输出引脚；900、发光元件。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
用语“一个”、“一”、“该”和“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/ 组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
本公开提供一种阵列基板，参见图1-1，阵列基板100呈多边形且具有至少一组相对设置的第一侧边503和第二侧边504，以及具有靠近第一侧边503设置的第一绑定区2301和靠近第二侧边504设置的第二绑定区2401。可以理解的是，这里所指的是形状指的是在阵列基板主表面所在平面上，阵列基板的正投影的形状，例如，可以为矩形，正方形，菱形，正多边形等；而第一侧边和第二侧边可以为矩形的两个相对短边，或者是正方形、菱形或正多边形的任意的两个相对边；靠近第一侧边或第二侧边设置，可以理解为沿第一侧边或第二侧边设置，且与第一侧边或第二侧边存在一定距离，例如在0-1.5毫米之间取值。
阵列基板包括衬底基板和设于衬底基板主表面的焊盘层，焊盘层包括位于第一绑定区2301内的多个第一绑定焊盘230，以及包括位于第二绑定区2401内的多个第二绑定焊盘240。第一绑定区2301和第二绑定区2401中的任意一个，用于与驱动电路板连接以驱动阵列基板100。
本公开提供的阵列基板100，通过设置第一绑定区2301和第二绑定区2401两个绑定区，两个绑定区均可以用于与驱动电路板连接以驱动阵列基板100或者基于该阵列基板100的发光基板。在将驱动电路板与阵列基板100的第一绑定焊盘230或者第二绑定焊盘240之一绑定时，如果出现绑定不良，则可以重复利用驱动电路板，然后在另一绑定焊盘重新完成绑定。即，在去除驱动电路板的过程中，若第一绑定焊盘230出现损伤的情形，就可以换成第二绑定焊盘240来绑定驱动电路板，而无需废弃该阵列基板100。如此，可以提高阵列基板100整体工序的良率并提高阵列基板100的利用率，避免因绑定焊盘损伤而废弃阵列基板100所造成的浪费。
下面，结合附图对本公开的阵列基板100的结构、原理和方法做进一步的解释和说明。
阵列基板包括衬底基板和设于衬底基板的主表面的焊盘层。参见图1-1，焊盘层包括多个第一焊盘组210；多个第一焊盘组210呈中心对称分布。如此，沿多个第一焊盘组210的对称中心旋转180°后，多个第一焊盘组210在空间上的位置分布不会发生改变。因此，若需要更换绑定电路板的绑定焊盘时，例如将与电路板绑定的绑定焊盘由第一绑定焊盘230改变为第二绑定焊盘240时，可以将阵列基板沿多个第一焊盘组210的对称中心旋转180°后与电路板绑定，进而在维持各个第一焊盘组210的空间位置分布不变的情况下进一步维持电路板的位置不变。
进一步地，参见图1-1，所有的第一绑定焊盘230和所有的第二绑定焊盘240，呈中心对称分布；更进一步地，所有的第一绑定焊盘230和所有的第二绑定焊盘 240的对称中心，与所有第一焊盘组210的对称中心重合。
可以理解的是，对多个第一焊盘组中的最靠外侧的多个第一子焊盘和/或第二子焊盘的连线，以形成焊盘区，焊盘区具有中心轴，所述多个第一焊盘组以所述焊盘区的中心轴呈中心对称分布。
可选地，衬底基板具有中心轴101，衬底基板具有中心轴101可与焊盘区的中心轴重合，从而多个第一焊盘组210关于衬底基板的中心轴101呈中心对称分布。如此，本公开提供的阵列基板100，包括中心对称分布的第一焊盘组210，阵列基板100沿衬底基板的中心轴101旋转180°后依然可以保持第一焊盘组210的位置不变。如此，将需要将多个阵列基板100拼接成一个大的拼接阵列基板时，则可以根据需要将任意一个阵列基板100旋转180°而保证拼接阵列基板上的各个第一焊盘组210的位置保持不变，进而保证拼接阵列基板的功能不受单一衬底基板的旋转的影响。
可选地，参见图1-1，本公开提供的阵列基板100具有关于衬底基板的中心轴101中心对称分布的第一焊盘组210，各个第一焊盘组210可以绑定连接功能器件以形成一功能基板。如此，该功能基板的各个功能器件关于衬底基板的中心轴中心对称。将多个功能基板拼接成一个大的拼接功能基板时，将任意一个功能基板沿其衬底基板的中心轴旋转180°，不会影拼接功能基板上的各个功能器件的位置分布。该功能器件可以为电流驱动的元件，例如可以为发热元件、发光元件、发声元件等，也可以为用于输出电流或者电压的光敏元件、热敏元件等。
示例性地，本公开提供的阵列基板100的第一焊盘组210可以用于绑定发光元件，例如可以用于绑定微型发光二极管(包括Micro LED、Mini LED)等，如此可以形成发光基板。进一步地，具有一块阵列基板100的发光基板可以相互拼接，形成更大尺寸的发光基板。可以理解的是，第一焊盘组210还可以用来绑定其他传感器，例如温度传感器，压力传感器，红外传感器等等电子元件，在此情况下，第一焊盘组210可以包括多个子焊盘。在一些实施例中，第一焊盘组210可以全部用来绑定微型发光二极管，或者全部用来绑定传感器等元件，或者第一焊盘组210中的一部分用来绑定微型发光二极管，一部分用来绑定传感器，甚至，可以有部分第一焊盘组210不绑定任何电子元器件。
在一些实施例中，本公开提供的阵列基板100的焊盘层还可以包括用于绑定其他电子元件的第三焊盘，本公开对第三焊盘的位置和作用不做限定，可以根据实际需要进行设置。
可选地，参见图1-1、图5和图17，任意一个第一焊盘组210包括成对设置第一子焊盘211和第二子焊盘212。如此，第一子焊盘211和第二子焊盘212可以用于与发光元件900的两极电连接。在任意一个第一焊盘组210中，第一子焊盘 211和第二子焊盘212的排列方向可以与衬底基板的一个边缘的延伸方向平行，也可与衬底基板的任意一个边缘的延伸方向均不平行；在任意两个第一焊盘组210中，第一子焊盘211和第二子焊盘212的排列方向可以相同，也可以不相同；本公开对此不做特殊的限定，以能够实现各个第一焊盘组210关于衬底基板的中心轴101对称为准。优选地，各个第一子焊盘211和各个第二子焊盘212在整体上，关于衬底基板的中心轴101对称。
可选地，参见图1-1，焊盘层还可以包括多个第二焊盘组220；参见图5，任意一个第二焊盘组220用于与一微芯片800连接。如此，该阵列基板100上可以绑定发光元件900和微芯片800以形成发光基板，该微芯片800用于控制各个发光元件900的发光。可以理解的是，微芯片800为边长尺寸或对角线长度或者直径在300um左右以及小于300um的集成电路芯片。
第二焊盘组220可以包括与微芯片800的各个引脚一一对应的子焊盘，其数量和类型可以根据微芯片800的类型和引脚进行设置。可选地，任意一个第二焊盘组220至少包括用于与微芯片800的各个输出引脚850一一对应连接的多个数据子焊盘225，且多个数据子焊盘225还与所述多个第一焊盘组的至少部分第一焊盘组连接。
示例性地，在本公开的一种实施方式中，参见图3，微芯片800具有用于加载芯片电源电压的芯片电源引脚810、用于加载第一电源电压的第一电源引脚820、用于加载驱动数据的驱动数据引脚830、用于加载芯片控制信号的控制信号引脚840和多个输出引脚850。
相应地，参见图2，任意一个第二焊盘组220包括：
芯片电源子焊盘221，用于与微芯片800的芯片电源引脚810连接；
第一电源子焊盘222，用于与微芯片800的第一电源引脚820连接；
驱动数据子焊盘223，用于与微芯片800的驱动数据引脚830连接；
控制信号子焊盘224，用于与微芯片800的控制信号引脚840连接；
多个数据子焊盘225，用于与所述多个第一焊盘组的至少部分连接。
可选地，参见图1-1，阵列基板100呈中心对称的多边形，具有至少一组相对设置的第一侧边503和第二侧边504，以及具有沿第一侧边503设置的第一绑定区2301和沿第二侧边504设置的第二绑定区2401。焊盘层还包括位于第一绑定区2301内的多个第一绑定焊盘230，以及包括位于第二绑定区2401内的多个第二绑定焊盘240。第一绑定区2301和第二绑定区2401中的任意一个，用于与驱动电路板连接以驱动阵列基板100。
发明人发现，如使用电镀方式制作驱动引线，由于工艺限制，驱动引线在不同区域的厚度不同，即发光基板上的驱动引线的厚度均一性较差。进一步地，如 果每个发光基板上仅具有一个绑定区，多个发光基板拼接成大尺寸基板时，且多个绑定区均位于大尺寸基板的同一侧时，基板整体的均一性较差的情况会呈倍数增加，会大大提高基板整体的调试测试难度，并影响基板整体信赖性的提高。
本公开提供的阵列基板100，通过设置第一绑定区2301和第二绑定区2401两个绑定区，两个绑定区均可以用于与驱动电路板连接以驱动阵列基板100或者基于该阵列基板100的发光基板。如此，在将多个阵列基板100进行拼接时，如果将其中一个阵列基板100旋转180°，则可以改变该阵列基板100用于与驱动电路板绑定的绑定区，以使得驱动电路板依然位于拼接的阵列基板100的同一侧。示例性地，在拼接多个阵列基板100后，各个阵列基板100的驱动电路板可以位于拼接的阵列基板100的同一侧，且各个阵列基板100的第一绑定区2301用于绑定驱动电路板。如果需要将一个阵列基板100沿衬底基板的中心轴旋转180°，则在旋转后，可以将该阵列基板100的第二绑定区2401与驱动电路板连接，使得各个阵列基板100的驱动电路板依然位于拼接的阵列基板100的同一侧。
阵列基板100的平面形状为呈中心对称的多边形，尤其是衬底基板的平面形状为可以为关于其中心轴101对称的多边形，例如衬底基板的形状可以为矩形、菱形、正六边形等。如此，可以保证阵列基板100旋转180°后不会与其他阵列基板100产生空间上的冲突，进而确保有效地拼接。
在一些实施例中，阵列基板100呈矩形，其具有相对设置的两个长边和相对设置的两个侧边503/504。
在一些实施例中，多个第一绑定焊盘230中的至少两个分别用于加载不同的驱动信号；多个第二绑定焊盘240中的至少两个分别用于加载不同的驱动信号；多个第一绑定焊盘230和多个第二绑定焊盘240中，用于加载同种驱动信号的多个第一绑定焊盘230中的至少一个和多个第二绑定焊盘240中的至少一个，关于衬底基板的中心轴101对称。
如此，第一绑定焊盘230和第二绑定焊盘240可以与同一驱动电路板绑定连接，无需针对第一绑定焊盘230和第二绑定焊盘240设置两种不同的驱动电路板，可以实现驱动电路板的复用，节省设计、测试和物料费用，降低应用该阵列基板100的产品的成本。换言之，第一绑定区2301和第二绑定区2401的对应的驱动电路板上的引脚(Pin)序列完全一致，只需要设计一种对应的驱动电路板就可以满足在第一绑定区2301和第二绑定区2401的任意一个绑定区驱动阵列基板100的需求。
在本公开的一种实施方式中，多个第一绑定焊盘210和多个第二绑定焊盘220中，用于加载同种驱动信号的第一绑定焊盘210和第二绑定焊盘220，关于衬底基板的中心轴101对称。
示例性地，参见11、图12和图13，图11示出了图1-2中A区域的各个第一绑定焊盘230的分布，图12示出了图1-2中B区域的各个第二绑定焊盘240的分布。其中，在A区域，第一绑定焊盘230包括用于加载第二电源电压的最后一个第二电源电压第一焊盘235(2N)、用于加载芯片电源电压的最后一个芯片电源电压第一焊盘231(N)、用于加载芯片控制信号的最后一个芯片控制信号第一焊盘234(2N)、用于加载第一电源电压的最后一个第一电源电压第一焊盘232(N)、用于加载芯片控制信号的倒数第二个芯片控制信号第一焊盘234(2N-1)、用于加载驱动数据的最后一个驱动数据第一焊盘233(N)、用于加载第二电源电压的倒数第二个第二电源电压第一焊盘235(2N-1)。在B区域，第二绑定焊盘240包括用于加载第二电源电压的第一个第二电源电压第二焊盘245(1)、用于加载芯片电源电压的第一个芯片电源电压第二焊盘241(1)、用于加载芯片控制信号的第一个芯片控制信号第二焊盘244(1)、用于加载第一电源电压的第一个第一电源电压第二焊盘242(1)、用于加载芯片控制信号的第二个芯片控制信号第二焊盘244(2)、用于加载驱动数据的第一个驱动数据第二焊盘243(1)、用于加载第二电源电压的第二个第二电源电压第二焊盘245(2)。其中，第二电源电压第一焊盘235(2N)与第二电源电压第二焊盘245(1)关于衬底基板的中心轴对称；芯片电源电压第一焊盘231(N)与芯片电源电压第二焊盘241(1)关于衬底基板的中心轴对称；芯片控制信号第一焊盘234(2N)与芯片控制信号第二焊盘244(1)关于衬底基板的中心轴对称；第一电源电压第一焊盘232(N)与第一电源电压第二焊盘242(1)关于衬底基板的中心轴对称；芯片控制信号第一焊盘234(2N-1)与芯片控制信号第二焊盘244(2)关于衬底基板的中心轴对称；驱动数据第一焊盘233(N)与驱动数据第二焊盘243(1)关于衬底基板的中心轴对称；第二电源电压第一焊盘235(2N-1)与第二电源电压第二焊盘245(2)关于衬底基板的中心轴对称。
在一些实施例中，用于与第一绑定焊盘230和第二绑定焊盘240绑定的驱动电路板可以具有柔性基底，具体可以为柔性电路板(FPC)或者覆晶薄膜(COF)。
可选地，阵列基板100还包括金属布线层；参见图1-2和图2(虚线框内且被填充的为驱动引线320)，金属布线层包括多个驱动引线320；各个驱动引线320呈中心对称分布。参见图1-1、图2、图4、图9和图10，驱动引线320用于与第一绑定焊盘230和第二绑定焊盘240连接，用于将加载于第一绑定焊盘230和或第二绑定焊盘240的各个驱动信号传输至阵列基板100的各个所需区域。驱动引线320以衬底基板的中心轴为对称中心，呈中心对称分布，可以保证阵列基板100沿衬底基板的中心轴旋转180°后驱动引线320的分布不变，进而避免驱动引线320的改变对绑定于第一焊盘组210上的发光元件900的影响。
在本公开的一种实施方式中，各个驱动引线320以衬底基板的中心轴101为 对称中心，呈中心对称分布。
驱动引线320的数量和类型可以根据阵列基板100的电路设置进行确定，以能够驱动基于阵列基板100的发光基板为准。在本公开的一种实施方式中，参见图2，驱动引线320包括用于加载第二电源电压的第二电源电压引线325、用于加载芯片电源电压的芯片电源引线321、用于加载芯片控制信号的芯片控制引线324、用于加载第一电源电压的第一电源电压引线322和用于加载驱动数据的驱动数据引线323。
相应的，参见图4，第一绑定焊盘230包括用于加载第二电源电压的第二电源电压第一焊盘235、用于加载芯片电源电压的芯片电源电压第一焊盘231、用于加载芯片控制信号的芯片控制信号第一焊盘234、用于加载第一电源电压的第一电源电压第一焊盘232和用于加载驱动数据的驱动数据第一焊盘233。参见图7，第二绑定焊盘240包括用于加载第二电源电压的第二电源电压第二焊盘245、用于加载芯片电源电压的芯片电源电压第二焊盘241、用于加载芯片控制信号的芯片控制信号第二焊盘244、用于加载第一电源电压的第一电源电压第二焊盘242和用于加载驱动数据的驱动数据第二焊盘243。
在图4和图7中，各个第一绑定焊盘230和各个第二绑定焊盘240为一个整面的焊盘，根据所需驱动的负载的大小而确定其宽度。示例性地，第二电源电压可以为用于驱动发光元件发光的阳极电压(V LED)，为了保证其具有足够的驱动能力，可以使得第二电源电压第一焊盘235和第二电源电压第二焊盘245具有较大的宽度。再示例性地，第一电源电压可以为阵列基板的参考电压，例如可以为地线电压(GND)，为了保证该第一电源电压的稳定，可以使得第一电源电压第一焊盘232和第一电源电压第二焊盘242的宽度不小于第二电源电压第一焊盘235的宽度，例如可以为第二电源电压第一焊盘235的宽度的两倍。再示例性地，芯片电源电压、芯片控制信号和驱动数据均用于控制芯片的工作以控制各个发光元件，其负载比较小，因此芯片电源电压第一焊盘231、芯片电源电压第二焊盘241、驱动数据第一焊盘233、驱动数据第二焊盘243、芯片控制信号第一焊盘234和芯片控制信号第二焊盘244的宽度可以小于第二电源电压第一焊盘235的宽度。
可以理解的是，各个第一绑定焊盘和各个第二绑定焊盘也可以为由一个或者多个绑定电极组成，且各个绑定电极之间具有间隙。可以调整各个第一绑定焊盘和各个第二绑定焊盘所包含的绑定电极的数量，进而确定各个第一绑定焊盘和各个第二绑定焊盘的宽度。举例而言，在第一绑定区可以设置有沿第一侧边方向等间距排列的多个绑定电极；一个绑定电极或者相邻的多个绑定电极可以形成一个第一绑定焊盘，且各个第一绑定焊盘之间不存在复用绑定电极的情况。在第二绑定区可以设置有沿第二侧边方向等间距排列的多个绑定电极；一个绑定电极或者 相邻的多个绑定电极可以形成一个第二绑定焊盘，且各个第二绑定焊盘之间不存在复用绑定电极的情况。其中，第二电源电压第一焊盘和第二电源电压第二焊盘均可以包括多个绑定电极，例如可以包括10～20个绑定电极。示例性地，第二电源电压第一焊盘和第二电源电压第二焊盘均可以包括14个绑定电极。第一电源电压第一焊盘和第一电源电压第二焊盘各自所包括的绑定电极的数量可以多于第二电源电压第一焊盘，例如可以包括20～40个绑定电极。示例性地，第一电源电压第一焊盘和第一电源电压第二焊盘各自包括的绑定电极的数量为28个。芯片电源电压第一焊盘、芯片电源电压第二焊盘、驱动数据第一焊盘、驱动数据第二焊盘、芯片控制信号第一焊盘和芯片控制信号第二焊盘可以各自包括1～3个绑定电极，例如可以各自包括一个绑定电极。
其中，参见图4和图7，第二电源电压引线325与第二电源电压第一焊盘235、第二电源电压第二焊盘245电连接；芯片电源引线321与芯片电源电压第一焊盘231、芯片电源电压第二焊盘241电连接；芯片控制引线324与芯片控制信号第一焊盘234、芯片控制信号第二焊盘244电连接；第一电源电压引线322与第一电源电压第一焊盘232、第一电源电压第二焊盘242电连接；驱动数据引线323与驱动数据第一焊盘233、驱动数据第二焊盘243电连接。
可选地，参见图1-1、图2、图4和图9，金属布线层还包括用于连接第一绑定区2301和多个驱动引线320的多个第一扇出引线330、用于连接第二绑定区2401和多个驱动引线320的多个第二扇出引线340。多个第一扇出引线330在衬底基板上的正投影和多个第一焊盘组210在衬底基板上的正投影存在交叠区域；多个第二扇出引线340在所述衬底基板上的正投影和多个第一焊盘组210在衬底基板上的正投影存在交叠区域。
在本公开的一种实施方式中，用于加载同一驱动信号的第一绑定焊盘230和驱动引线320，通过第一扇出引线330连接；用于加载同一驱动信号的第二绑定焊盘240和驱动引线320，通过第二扇出引线340连接。
示例性地，参见图11，用于加载第二电源电压的第二电源电压引线325(2N)和第二电源电压第一焊盘235(2N)通过第一扇出引线330连接，用于加载芯片电源电压的芯片电源引线321(N)与芯片电源电压第一焊盘231(N)通过第一扇出引线330连接，用于加载芯片控制信号的芯片控制引线324(2N)与芯片控制信号第一焊盘234(2N)通过第一扇出引线330连接，用于加载第一电源电压的第一电源电压引线322(N)与第一电源电压第一焊盘232(N)通过第一扇出引线330连接，用于加载芯片控制信号的芯片控制引线324(2N-1)与芯片控制信号第一焊盘234(2N-1)通过第一扇出引线330连接，用于加载驱动数据的驱动数据引线323(N)与驱动数据第一焊盘233(N)通过第一扇出引线330连接。
再示例性地，参见图12，用于加载第二电源电压的第二电源电压引线325(1)和第二电源电压第二焊盘245(1)通过第二扇出引线340连接，用于加载芯片电源电压的芯片电源引线321(1)与芯片电源电压第二焊盘241(1)通过第二扇出引线340连接，用于加载芯片控制信号的芯片控制引线324(1)与芯片控制信号第二焊盘244(1)通过第二扇出引线340连接，用于加载第一电源电压的第一电源电压引线322(1)与第一电源电压第二焊盘242(1)通过第二扇出引线340连接，用于加载芯片控制信号的芯片控制引线324(2)与芯片控制信号第二焊盘244(2)通过第二扇出引线340连接，用于加载驱动数据的驱动数据引线323(1)与驱动数据第二焊盘233(1)通过第二扇出引线340连接。
在本公开的一种实施方式中，金属布线层包括依次层叠于衬底基板的第一金属布线层、平坦化层和第二金属布线层，第一金属布线层和第二金属布线层之间通过贯穿平坦化层的过孔连接。参见图4，第一扇出引线330均位于第一金属布线层。参见图9和图10，第二扇出引线340包括第一引线341和第二引线342；第一引线341位于第一金属布线层，且与驱动引线320和第二绑定焊盘240电连接；第二引线342至少包括依次连接的第一部分3421、第二部分3422和第三部分3423；第一部分3421和第三部分3423位于第一金属布线层，且第二部分3422位于第二金属布线层；第一部分3421与驱动引线320电连接，第三部分3423与第二绑定焊盘240电连接。如此，第二引线342可以通过跨接于第一金属布线层和第二金属布线层的方式避让第一引线341。
可选地，参见图4，第一扇出引线330具有与驱动引线320连接的第一直线段、与第一绑定焊盘230连接的第二直线段、连接第一直线段和第二直线段的第一斜线段；其中，第一直线段的宽度可以与所连接的驱动引线320的宽度相同；第二直线段的宽度可以与所连接的第一绑定焊盘230的宽度相同；随着从与第一直线段连接的一端延伸至与第二直线段连接的一端，第一斜线段的宽度从等于驱动引线320的宽度均匀地过渡至等于所连接的第一绑定焊盘230的宽度。其中，第一直线段和第二直线段的延伸方向平行于驱动引线320的延伸方向，第一斜线段的延伸方向与驱动引线320的延伸方向呈锐角；第一直线段、第二直线段和第一斜线段的宽度为其在阵列基板所在平面内且垂直于驱动引线320的延伸方向上的尺寸。进一步地，驱动引线320的宽度大于其所连接的第一绑定焊盘230的宽度，使得第一斜线段在朝向第一侧边503的方向上宽度逐渐减小。
可选地，参见图7和图9，第二扇出引线340具有与驱动引线320连接的第三直线段、与第二绑定焊盘240连接的第四直线段、连接第三直线段和第四直线段的第二斜线段；其中，第三直线段的宽度可以与所连接的驱动引线320的宽度相同；第四直线段的宽度可以与所连接的第二绑定焊盘240的宽度相同。第三直线 段和第四直线段的延伸方向平行于驱动引线320的延伸方向。在第一引线341中，第二斜线段的延伸方向与驱动引线320的延伸方向呈锐角；随着从与第三直线段连接的一端延伸至与第四直线段连接的一端，第二斜线段的宽度从等于驱动引线320的宽度均匀地过渡至等于所连接的第二绑定焊盘240的宽度。在第二引线342中，第二斜线段可以包括底斜线段和顶斜线段，其中，底斜线段位于第一金属布线层且连接第三直线段，且沿相邻两个其他第二扇出引线340所限定的空间和尺寸向靠近第二侧边504的一侧延伸；顶斜线段位于第二金属布线层且通过过孔与底斜线段连接，其可以沿着平行于和/或垂直于驱动引线的延伸方向曲折延伸或者直线延伸，以与第四直线段通过过孔连接。如此，第三直线段和底斜线段组成了第二引线342的第一部分3421，顶斜线段组成了第二引线的第二部分3422，第四直线段组成了第二引线的第三部分3423。其中，第三直线段、第四直线段、第一引线的第二斜线段、第二引线的底斜线段的宽度为其在阵列基板所在平面内且垂直于驱动引线的延伸方向上的尺寸。进一步地，驱动引线的宽度大于其所连接的第二绑定焊盘的宽度，使得第一引线的第二斜线段、第二引线的底斜线段的至少部分在朝向第二侧边的方向上宽度逐渐减小。
进一步地，多个第一绑定焊盘230和多个第二绑定焊盘240均关于同一辅助线对称；多个驱动引线320包括至少一个第一驱动引线组；任意一个第一驱动引线组包括关于辅助线对称、用于加载相同驱动信号的多个第一驱动引线；分别与任意一个第一驱动引线组中的多个第一驱动引线相连接的第一引线341和第一扇出引线330呈中心对称分布；用于加载同种驱动信号的多个第一绑定焊盘230中的至少一个和多个第二绑定焊盘240中的至少一个，分别通过第一扇出引线330和第二扇出引线340与任意一个第一驱动引线组中的多个第一驱动引线连接。如此，可以方便阵列基板的设计和掩膜板的制备。尤其是在衬底基板的版图设计阶段，可以在完成第一扇出引线的版图设计后，将各个第一扇出引线的设计版图沿衬底基板的中心轴旋转180°而获得第二扇出引线340的设计草图；然后，在第二扇出引线340的设计草图的基础上进行微调，以保证第二绑定焊盘240与驱动引线320之间的连接关系。示例性地，如果第二扇出引线340的设计草图上的一个扇出引线草图，能够将用于加载同种驱动信号的第二绑定焊盘240和驱动引线320电连接，则该扇出引线草图作为第一引线341的审计版图。如果第二扇出引线340的设计草图上的一个扇出引线草图不能将用于加载同种驱动信号的第二绑定焊盘240和驱动引线320电连接，则通过跨接的方式对其进行调整，调整后的扇出引线草图作为第二引线342的设计版图，使得加载同种驱动信号的第二绑定焊盘240和驱动引线320能够通过第二引线342电连接。
进一步地，辅助线位于衬底基板所在平面内，垂直于第一侧边503、第二侧边 504且通过衬底基板的中心轴101。
示例性地，参见图1-2和图2，驱动引线320包括用于加载第二电源电压的多个第二电源电压引线325，各个第二电源电压引线325关于辅助线对称设置以形成一个第一驱动引线组。参见图4和图7，分别与各个第二电源电压引线325连接的各个第一引线341和各个第一扇出引线330呈中心对称分布。
再示例性地，参见图1-2和图2，驱动引线320包括用于加载芯片控制信号的芯片控制引线324，各个芯片控制引线324关于辅助线对称设置以形成一个第一驱动引线组。参见图4和图7，分别与各个芯片控制引线324连接的各个第一引线341和各个第一扇出引线330呈中心对称分布。
可选地，第一金属布线层的厚度大于第二金属布线层的厚度；驱动引线320均位于第一金属布线层。第一金属布线层的主体材料包括铜，可以采用电镀工艺形成第一金属布线层。
可选地，如图2、图5、图6、图8、图9和图17所示，金属布线层还可以包括连接引线310，用于实现第一焊盘组210(在图5、图6、图8和图9中被发光元件900遮挡)之间的连接、第一焊盘组210与驱动引线320之间的连接和/或者第二焊盘组220(在图5、图6、图8和图9中被微芯片800遮挡)与驱动引线320之间的连接。进一步地，连接引线310可以位于第二金属布线层。
可选地，焊盘层可以与金属布线层同层设置，例如焊盘层和金属布线层可以由相同的一层或者多层金属层制备而来。在一些实施方式中，参见图5和图8，第一焊盘组210(在图5和图8中被发光元件900遮挡)和第二焊盘组220(在图5和图8中被微芯片800遮挡)中各个子焊盘可以与第二金属布线层同层设置，即第一焊盘组210和第二焊盘组220也可以视为第二金属布线层的延伸或者一部分。在一些实施方式中，参见图4和图7，第一绑定焊盘230和第二绑定焊盘240可以与第一金属布线层同层设置，即第一绑定焊盘230和第二绑定焊盘240可以视为第二金属布线层的延伸或者一部分。
示例性地，可以采用如下步骤S110～步骤S130所示的方法形成阵列基板100的金属布线层和焊盘层。
步骤S110，参见图4和图7，在衬底基板的一侧形成第一金属布线层、第一绑定焊盘230和第二绑定焊盘240；其中，沿垂直于衬底基板所在平面方向，第一金属布线层、第一绑定焊盘230和第二绑定焊盘240至少包括依次层叠设置的铜种子层和铜生长层，铜生长层可以采用电镀铜的方法进行制备。
可以采用多种不同的方法实现步骤S110，以能够制备第一金属布线层、第一绑定焊盘230和第二绑定焊盘240为准。示例性地，在本公开的一种实施方式中，可以先形成覆盖衬底基板的未图案化的铜种子层，然后采用电镀铜的方法沉积铜 以形成未图案化的铜生长层，最后对图案化的铜种子层和未图案化的铜生长层进行图案化，以获得第一金属布线层、第一绑定焊盘230和第二绑定焊盘240。示例性地，在本公开的另一种实施方式中，可以先形成图案化的铜种子层，然后形成一覆盖衬底基板且暴露铜种子层的图案限定层，再采用电镀铜的方法在图案化的铜种子层上形成图案化的铜生长层，获得第一金属布线层、第一绑定焊盘230和第二绑定焊盘240；去除图案限定层。在本公开的另一种实施方式中，可以先形成覆盖衬底基板的未图案化的铜种子层，然后在铜种子层远离衬底基板的一侧形成图案限定层，图案限定层仅暴露需要形成铜生长层的位置；然后，通过电镀铜的方法在未图案化的铜种子层上形成图案化的铜生长层，去除图案限定层后对未图案化的铜种子层进行图案化，获得第一金属布线层、第一绑定焊盘230和第二绑定焊盘240。
可选地，沿垂直于衬底基板所在平面方向，第一金属布线层、第一绑定焊盘230和第二绑定焊盘240在材料上还可以包括位于铜种子层与衬底基板之间的第一粘附金属层，第一粘附金属层的材料可以为钼、钼铜合金、钼铌合金、钼铜铌合金或者其他金属或者金属合金，以提高第一金属布线层、第一绑定焊盘230和第二绑定焊盘240与衬底基板的结合强度。
可选地，沿垂直于衬底基板所在平面方向，第一金属布线层、第一绑定焊盘230和第二绑定焊盘240在材料上还可以包括位于铜生长层远离衬底基板的一侧的第一保护金属层，第一保护金属层的材料可以为镍、铜镍合金或者氧化铟锡等金属氧化物，以避免第一金属布线层、第一绑定焊盘230和第二绑定焊盘240的表面发生氧化。
可选地，沿垂直于衬底基板所在平面方向，第一金属布线层的厚度可以为1.5～20微米，在一些实施例中，可以为2～10微米。
步骤S120，形成平坦化层，平坦化层位于第一金属布线层、第一绑定焊盘230和第二绑定焊盘240远离衬底基板的一侧，且具有暴露部分第一金属布线层、至少部分第一绑定焊盘230和至少部分第二绑定焊盘240的过孔。该过孔用于第二金属布线层与第一金属布线层之间的电连接，以及用于驱动电路板与第一绑定焊盘230和第二绑定焊盘240的电连接。更进一步地，平坦化层在对应第一绑定焊盘230和第二绑定焊盘240位置处开口，以露出第一绑定焊盘230和第二绑定焊盘240的部分或者全部表面，待与驱动电路板的金手指结构绑定连接。
平坦化层的材料可以为有机材料，尤其是可以为光敏有机材料，例如可以为酚醛树脂或固化型亚克力树脂。
进一步地，在形成平坦化层之前，还可以形成钝化层，钝化层位于第一金属布线层、第一绑定焊盘230和第二绑定焊盘240远离衬底基板的一侧，且平坦化 层上的过孔还贯穿该钝化层。钝化层的材料可以为氮化硅，以避免第一金属布线层、第一绑定焊盘230和第二绑定焊盘240被氧化。
步骤S130，在平坦化层远离衬底基板的一侧形成一金属层，然后对该金属层进行图案化操作以形成第二金属布线层、第一焊盘组210和第二焊盘组220。
可选地，沿垂直于衬底基板所在平面方向，第二金属布线层、第一焊盘组210和第二焊盘组220可以包括第二粘附金属层和铜金属层。其中，第二粘附金属层的材料可以为钼、钼铜合金、钼铌合金、钼铜铌合金或者其他金属或者金属合金。
可选地，沿垂直于衬底基板所在平面方向，第二金属布线层、第一焊盘组210和第二焊盘组220还可以包括第二保护金属层，第二保护金属层的材料可以为镍、铜镍合金或者氧化铟锌等金属氧化物，以避免第一金属布线层、第一绑定焊盘230和第二绑定焊盘240的表面发生氧化，并提高与发光元件900、微芯片800的结合强度。
可选地，阵列基板的制备方法还可以包括步骤S140，在第二金属布线层远离衬底基板的一侧形成有机保护层，有机保护层暴露各个第一绑定焊盘230的至少部分表面和各个第二绑定焊盘240的至少部分表面，还暴露各个第一焊盘组210的至少部分表面和第二焊盘组220的至少部分表面。示例性地，可以通过丝网印刷绿油来形成有机保护层。
可选地，阵列基板的制备方法还可以包括步骤S150，在各个第一焊盘组210和各个第二焊盘组220的表面形成保护金属层，保护金属层的材料可以为镍、铜镍合金或者氧化铟锌等金属氧化物。
可选地，沿阵列基板100的长边方向506，驱动引线320在不同位置处的厚度差异不超过150％。换言之，驱动引线320最厚的位置的厚度，可以不超过驱动引线320最薄的位置的厚度的2.5倍，避免驱动引线320在不同位置处的厚度差异过大而导致的信赖性问题。进一步地，驱动引线320在不同位置处的厚度差异不超过100％，即驱动引线320最厚的位置的厚度，可以不超过驱动引线320最薄的位置的厚度的2倍。
可以理解的是，驱动引线320在不同位置处的厚度差异，是由于采用电镀工艺制备驱动引线320的过程中形成的，而非刻意设计的。阵列基板100在制备过程中如果采用电镀铜工艺，则不同位置处的铜生长层的厚度会有差异。该差异会对阵列基板100的调试、信赖性等产生一定的影响，且当该差异太大时，可能导致调试困难或者信赖性缺陷。
进一步地，沿阵列基板100的长边方向506，驱动引线320两端的厚度不同；其中，驱动引线320较厚一端的厚度，比驱动引线320较薄一端的厚度大10％以上。更进一步地，驱动引线320较厚一端的厚度，比驱动引线320较薄一端的厚 度大50％以上，示例性地，驱动引线320较厚一端的厚度可以为7.5微米以上，例如可以为10微米，驱动引线320较薄一端的厚度可以为5微米左右。
参见图13，可以将阵列基板100的驱动引线320较厚的一端定义为阵列基板100的第一端501，阵列基板100的驱动引线320较薄的一端定义为阵列基板100的第二端502。在将多个阵列基板100拼接成一个拼接阵列基板100时，参见图15和图16，如果部分阵列基板100的第一端501和其余阵列基板100的第二端502位于拼接阵列基板100的同一侧，则将会导致拼接阵列基板100上的驱动引线320厚度分布无规律，不利于进行调试和提高信赖性。而在本公开中，由于阵列基板100上的第一焊盘组210中心对称设置，因此可以对阵列基板100进行180°旋转，参见图14，使得各个阵列基板100的第一端501位于拼接阵列基板100的同一侧，则可以使得拼接阵列基板100上的驱动引线320的厚度分布有规律，便于进行调试和提高信赖性。
示例性地，在利用高世代产线制备大尺寸显示产品时，采用四个阵列基板100拼接成一个大尺寸的基板(四拼方案)时对衬底母板600的利用率，相比于两个阵列基板100拼接成一个大尺寸的基板时对衬底母板600的利用率，可以从55％提升至80％以上。参见图13，为了实现四拼方案，一个衬底母板600上可以包括6个待制备形成阵列基板100的衬底区域，衬底区域即对应着阵列基板100的衬底基板。该6个阵列基板100呈两行三列排列，任意一行包括沿阵列基板100的侧边方向505排列的三个阵列基板100，任意一列包括沿阵列基板100的长边方向506排列的两个阵列基板100。其中，沿长边方向506，阵列基板100包括靠近衬底母板600边缘的第一端501和靠近衬底母板600中间的第二端502。由于在同一衬底母板600上进行成膜工艺和构图工艺，而构图工艺使用的掩膜板旋转的不便性，因此在各个阵列基板100区域制备的膜层图案完全相同。换言之，阵列基板100(1,1)的第一端501的膜层图案、阵列基板100(1,2)的第一端501的膜层图案、阵列基板100(1,3)的第一端501的膜层图案、阵列基板100(2,1)的第二端502的膜层图案、阵列基板100(2,2)的第二端502的膜层图案、阵列基板100(2,3)的第二端502的膜层图案相同；阵列基板100(1,1)的第二端502的膜层图案、阵列基板100(1,2)的第二端502的膜层图案、阵列基板100(1,3)的第二端502的膜层图案、阵列基板100(2,1)的第一端501的膜层图案、阵列基板100(2,2)的第一端501的膜层图案、阵列基板100(2,3)的第一端501的膜层图案相同。在采用电镀工艺制备第一金属布线层时，容易出现各个阵列基板100的第一端501的铜生长层厚而第二端502的铜生长层薄。尤其是，为了实现在G6衬底母板600上制备出6个阵列基板100，阵列基板100的第一端501与衬底母板600的边缘之间的间距非常小，例如可以小至11.5mm，这会导致驱动引线320沿其延伸方向具有较大的厚度差异。当切割 获得各个阵列基板100后，在拼接过程中，如果阵列基板100不能够沿衬底基板的中心轴进行180°旋转，则拼接的基板会出现厚度不均一的情形。示例性地，如果不能够旋转，则需要采用图15、图16或者其他类似的方式进行拼接，这使得一个阵列基板100的第一端501与另一个阵列基板的第二端502相邻，使得拼接的基板出现厚度不均一的情形。
参见图14，本公开的阵列基板100在拼接时可以进行180°旋转，因此可以使得各个阵列基板100的第一端501位于拼接阵列基板100的同一侧。示例性地，可以使得阵列基板100(2,1)、阵列基板100(2,2)均旋转180°后与阵列基板100(1,1)、阵列基板100(1,2)进行拼接，进而使得相邻两个阵列基板的第一端501相邻，且相邻两个阵列基板的第二端502相邻。如此，在垂直于阵列基板的长边方向上，拼接的基板的驱动引线的厚度基本均一；在沿阵列基板的长边方向上，拼接的基板的的驱动引线的厚度基本有规律的增厚或者减薄。这可以使得拼接的基板的调试更简便，且更容易定位和消除影响信赖性的问题。
在一些实施方式中，参见图1-1，阵列基板100呈矩形，具有阵列分布的多个控制区域400，且各个控制区域400形成沿侧边方向505排列的N个控制区域列410，以及形成沿长边方向506排列的2N个控制区域行420；其中，N为正整数。
参见图2，阵列基板100还包括金属布线层，金属布线层包括多个连接引线310和多个沿长边方向延伸的驱动引线320。
参见图1-1和图2，在任意一个控制区域列410内，驱动引线320包括两根用于加载第二电源电压的第二电源电压引线325、一根用于加载芯片电源电压的芯片电源引线321、两根用于加载芯片控制信号的芯片控制引线324、一根用于加载第一电源电压的第一电源电压引线322和一根用于加载驱动数据的驱动数据引线323。
参见图2，在任意一个控制区域400内，阵列基板100包括一个第二焊盘组220和与第二焊盘组220中的各个数据子焊盘225一一对应的多个焊盘连接电路401。参见图17，任意一个焊盘连接电路401包括至少一个第一焊盘组210，且各个第一焊盘组210通过连接引线310连接；各个焊盘连接电路401的第一端通过连接引线310与对应的数据子焊盘225连接，焊盘连接电路401的第二端与第二电源电压引线325通过连接引线310电连接。参见图5和图8，任意一个焊盘连接电路401上的第一焊盘组210可以绑定发光元件900，以形成发光电路402。
其中，参见图2，在任意一个控制区域400内，部分焊盘连接电路401的第二端与一根第二电源电压引线325通过连接引线310电连接，其余焊盘连接电路401的第二端与另一根第二电源电压引线325通过连接引线310电连接。芯片电源子焊盘221与芯片电源引线321通过连接引线310电连接，第一电源子焊盘222与 第一电源电压引线322通过连接引线310电连接，驱动数据子焊盘223与驱动数据引线323通过连接引线310电连接。
参见图2，在阵列基板100中，各个芯片控制引线324与各个控制区域行420一一对应设置，且任意一个控制区域行420中的各个的控制信号子焊盘224均与对应的芯片控制引线324通过连接引线310电连接。
可选地，参见图4和图7，相邻两个控制区域列410中，相邻的两个第二电源电压引线325可以在靠近第一绑定焊盘230或者第二绑定焊盘240的位置相互连接。进一步地，与相邻的两个第二电源电压引线325连接的两个第一扇出引线330可以相互连接成一条扇出引线，与相邻的两个第二电源电压引线325连接的两个第二扇出引线340可以相互连接成一条扇出引线。再进一步地，与相邻的两个第二电源电压引线325连接的两个第二电源电压第一焊盘235可以相互连接而成一个第二电源电压第一焊盘235，与相邻的两个第二电源电压引线325连接的两个第二电源电压第二焊盘245可以相互连接而成一个第二电源电压第二焊盘245。
示例性地，参见图11，控制区域列410(N)和控制区域列410(N-1)为相邻的两个控制区域列410。第二电源电压引线325(2N-1)和第二电源电压引线325(2N-2)所连接的两个第一扇出引线330相互连接而合并成一个宽度更大的第一扇出引线330。与第二电源电压引线325(2N-1)和第二电源电压引线325(2N-2)所连接的第二电源电压第一焊盘235(2N-1)和第二电源电压第一焊盘235(2N-2)相互连接而合并为一个宽度更大的第二电源电压第一焊盘235。
示例性地，参见图12，控制区域列410(1)和控制区域列410(2)为相邻的两个控制区域列410。第二电源电压引线325(2)和第二电源电压引线325(3)所连接的两个第二扇出引线340相互连接而合并成一个宽度更大的第二扇出引线340。与第二电源电压引线325(2)和第二电源电压引线325(3)所连接的第二电源电压第二焊盘245(2)和第二电源电压第二焊盘245(3)相互连接而合并为一个宽度更大的第二电源电压第二焊盘245。
可选地，第一金属布线层在相邻的两个第二电源电压引线325之间可以设置有镂空区域，以避免第一金属布线层的金属面积占比太大而影响后续的曝光等工序。示例性地，参见图12，第一金属布线层在第二电源电压引线325(2)和第二电源电压引线325(3)之间镂空。
进一步地，在阵列基板中，第i行控制区域行中的各个控制信号子焊盘均与第i根芯片控制引线通过连接引线电连接；或者，在阵列基板中，第i行控制区域行中的各个控制信号子焊盘均与第2N-i+1根芯片控制引线通过连接引线电连接；其中，1≤i≤2N，且i为正整数。其中，控制区域列、各个驱动引线沿侧边方向依次排列；控制区域行沿长边方向依次排列。
如此，可以保证阵列基板100的第一绑定焊盘230和第二绑定焊盘240可以适用同一驱动电路板和同一驱动时序，降低了驱动电路板的开发成本。
进一步地，参见图2，在控制区域400，一根第二电源电压引线325、一根驱动数据引线323、一根芯片控制引线324、一根第一电源电压引线322、一根芯片控制引线324、一根芯片电源引线321和一根第二电源电压引线325沿阵列基板100的侧边方向505延伸，驱动数据引线323和芯片电源引线321的宽度基本大致相同。
进一步地，参见图4，第一扇出引线330位于第一金属布线层，且用于加载同一驱动信号的驱动引线320和第一绑定焊盘230通过第一扇出引线330连接。参见图7、图8、图9和图10，第二扇出引线340包括第一引线341和第二引线342；第一引线341位于第一金属布线层，且用于加载第一电源电压的第二绑定焊盘240和第一电源电压引线322通过第一引线341电连接，用于加载芯片控制信号的第二绑定焊盘240和芯片控制引线324通过第一引线341电连接，用于加载第二电源电压的第二绑定焊盘240和第二电源电压引线325通过第一引线341电连接；第二引线342至少包括依次连接的第一部分3421、第二部分3422和第三部分3423；第一部分3421和第三部分3423位于第一金属布线层，且第二部分3422位于第二金属布线层；用于加载芯片电源电压的第二绑定焊盘240和芯片电源引线321通过第二引线342电连接；用于加载驱动数据的第二绑定焊盘240和芯片电源引线321通过驱动数据引线323电连接。
示例性地，参见图7和图10，第二引线342可以包括连接驱动数据第二焊盘243和驱动数据引线323的驱动数据扇出引线，以及包括连接芯片电源电压第二焊盘241和第二电源电压引线325的芯片电源电压扇出引线。其中，驱动数据扇出引线的第一部分3611和第三部分3613分别位于第一金属布线层，且第二部分3612位于第二金属布线层。其中，芯片电源电压扇出引线的第一部分3511和第三部分3513分别位于第一金属布线层，且第二部分3512位于第二金属布线层。进一步地，驱动数据扇出引线的第二部分3612和芯片电源电压扇出引线的第二部3512分沿阵列基板100的侧边方向505延伸。
示例性地，参见图2、图5(第一焊盘组210上绑定了发光元件900)和图8(第一焊盘组210上绑定了发光元件900)，在一个控制区域400，阵列基板100包括四个焊盘连接电路401；相应的，第二焊盘组220(第二焊盘组220上绑定了微芯片800)包括四个数据子焊盘225。其中，参见图17，任意一个焊盘连接电路401包括四个第一焊盘组210，第一个第一焊盘组210(1)的第一子焊盘211通过连接引线310与第二电源电压引线325连接，第一个第一焊盘组210(1)的第二子焊盘212通过连接引线310与第二个第一焊盘组210(2)的第一子焊盘211通过连接 引线310连接，第二个第一焊盘组210(2)的第二子焊盘212通过连接引线310与第三个第一焊盘组210(3)的第一子焊盘211通过连接引线310连接，第三个第一焊盘组210(3)的第二子焊盘212通过连接引线310与第四个第一焊盘组210(4)的第一子焊盘211通过连接引线310连接，第四个第一焊盘组210(4)的第二子焊盘212通过连接引线310与对应的数据子焊盘225连接。
如此，参见图5和图8，在基于该阵列基板100的发光基板中，在一个控制区域400内设置有一个微芯片800和四个发光电路402，任意一个发光电路402包括通过一个焊盘连接电路401串联的四个发光元件900；该微芯片800可以控制该四个发光电路402独立的发光。
在本公开的一种实施方式中，N＝12。如此，可以制备出合适的阵列基板100，以使得该阵列基板100能够适用于75寸液晶显示装置。
本公开实施方式还提供一种发光基板，该发光基板包括上述阵列基板100实施方式所描述的任意一种发光基板。该发光基板可以为照明灯、Micro LED显示面板、液晶显示装置的灯板等。由于该发光基板具有上述阵列基板100实施方式所描述的任意一种阵列基板100，因此具有相同的有益效果，本公开在此不再赘述。
可选地，该发光基板还包括与各个第一焊盘组210一一对应地绑定的多个发光元件900。
在一些实施例中，发光基板还包括与各个第二焊盘组220一一对应绑定的多个微芯片800。微芯片800用于驱动发光基板的各个发光元件900的发光。
在一些实施例中，发光基板包括多个相互拼接的阵列基板100。如此，可以通过拼接的方式获得更大尺寸的拼接发光基板。
在一些实施例中，沿阵列基板100的长边方向506，驱动引线320两端的厚度不同时，参见图12，发光基板具有相对设置的第一边710和第二边720，各个阵列基板100沿第一边710的延伸方向并排排列；各个阵列基板100中驱动引线320的厚度较大的部分，均靠近发光基板的第一边710；各个阵列基板100中驱动引线320的厚度较小的部分，均靠近发光基板的第二边720。
如此，可以使得在拼接发光基板中，各个驱动引线320的厚度变化一致，提高发光基板的可调式性和信赖性。
本公开还提供一种发光基板的制备方法，参见图18，发光基板的制备方法包括：
步骤S210，参见图13，提供一衬底母板600，衬底母板600包括多个待形成阵列基板100的衬底区域；任意一个衬底区域具有垂直于衬底区域所在平面的中心轴101；
步骤S220，在各个衬底基板上形成各个阵列基板100的驱动引线和焊盘层； 任意一个阵列基板100的驱动引线具有靠近衬底母板600边缘的第一端501和远离衬底母板600边缘的第二端502；任意一个阵列基板100的焊盘层包括多个第一焊盘组210，且多个第一焊盘组210以衬底区域的中心轴为对称中心，呈中心对称分布；
步骤S230，切割衬底母板600，以获得各个阵列基板100；
步骤S240，在任意一个阵列基板100上设置发光元件层，发光元件层包括与阵列基板100的各个第一焊盘组210一一对应地绑定的多个发光元件900；
步骤S250，参见图14，将多个阵列基板100拼接成发光基板；其中，在同一发光基板中，各个阵列基板100沿垂直于驱动引线320的延伸方向排列，且各个阵列基板100的驱动引线320的第一端均靠近发光基板的一边缘，各个阵列基板100的驱动引线320的第二端均靠近发光基板的另一边缘。
根据本公开的发光基板的制备方法，不仅可以提高对衬底母板600的利用率，而且可以克服驱动引线320的厚度不均一导致的调试复杂、信赖性降低的缺陷。其中，衬底母板600可以为玻璃基板。可以理解的是，对于每个阵列基板而言，第一绑定区和所述第二绑定区中只有一个用于与驱动电路板连接以驱动所述阵列基板，而未与与驱动电路板连接另一个，可以通过在该绑定区上覆盖绝缘层或者利用激光切断该绑定区中绑定焊盘与驱动引线之间的连接关系，以防止引入静电荷影响阵列基板的良率和使用寿命。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板呈多边形且具有至少一组相对设置的第一侧边和第二侧边，以及具有靠近所述第一侧边设置的第一绑定区和靠近所述第二侧边设置的第二绑定区；
    所述阵列基板包括衬底基板和设于所述衬底基板主表面的焊盘层，所述焊盘层包括位于所述第一绑定区内的多个第一绑定焊盘，以及包括位于所述第二绑定区内的多个第二绑定焊盘；所述第一绑定区和所述第二绑定区中的任意一个，用于与驱动电路板连接以驱动所述阵列基板。
  2. 根据权利要求1所述的阵列基板，其中，所述焊盘层还包括多个第一焊盘组；所述多个第一焊盘组呈中心对称分布。
  3. 根据权利要求2所述的阵列基板，其中，任意一个所述第一焊盘组包括成对设置的第一子焊盘和第二子焊盘。
  4. 根据权利要求2所述的阵列基板，其中，所述焊盘层还包括多个第二焊盘组，任意一个所述第二焊盘组用于与一微芯片连接。
  5. 根据权利要求4所述的阵列基板，其中，任意一个所述第二焊盘组包括：
    多个数据子焊盘，用于与所述多个第一焊盘组的至少部分第一焊盘组连接。
  6. 根据权利要求1-5任一项所述的阵列基板，其中，所述多个第一绑定焊盘中的至少两个分别用于加载不同的驱动信号；所述多个第二绑定焊盘中的至少两个分别用于加载不同的驱动信号；
    所述多个第一绑定焊盘和所述多个第二绑定焊盘中，用于加载同种驱动信号的所述多个第一绑定焊盘中的至少一个和所述多个第二绑定焊盘中的至少一个，关于所述衬底基板的中心轴对称。
  7. 根据权利要求6所述的阵列基板，其中，所述阵列基板还包括金属布线层；
    所述金属布线层包括多个驱动引线；所述多个驱动引线呈中心对称分布。
  8. 根据权利要求7所述的阵列基板，其中，所述金属布线层还包括用于连接所述第一绑定区和所述多个驱动引线的多个第一扇出引线、用于连接所述第二绑定区和所述多个驱动引线的多个第二扇出引线；所述多个第一扇出引线在所述衬底基板上的正投影和所述多个第一焊盘组在所述衬底基板上的正投影存在交叠区域；所述多个第二扇出引线在所述衬底基板上的正投影和所述多个第一焊盘组在所述衬底基板上的正投影存在交叠区域。
  9. 根据权利要求8所述的阵列基板，其中，所述金属布线层包括依次层叠于所述衬底基板的第一金属布线层、平坦化层和第二金属布线层，所述第一金属布线层和所述第二金属布线层之间通过贯穿所述平坦化层的过孔连接；
    所述第一扇出引线均位于所述第一金属布线层；
    所述第二扇出引线包括第一引线和第二引线；所述第一引线位于所述第一金属布线层，且与所述驱动引线和第二绑定焊盘电连接；所述第二引线至少包括依次连接的第一部分、第二部分和第三部分；所述第一部分和所述第三部分位于所述第一金属布线层，且所述第二部分位于所述第二金属布线层；所述第一部分与所述驱动引线电连接，所述第三部分与所述第二绑定焊盘电连接。
  10. 根据权利要求9所述的阵列基板，其中，所述多个第一绑定焊盘和所述多个第二绑定焊盘均关于同一辅助线对称；
    所述多个驱动引线包括至少一个第一驱动引线组；任意一个所述第一驱动引线组包括关于所述辅助线对称、用于加载相同驱动信号的多个第一驱动引线；
    分别与任意一个所述第一驱动引线组中的所述多个第一驱动引线相连接的所述第一引线和所述第一扇出引线呈中心对称分布。
  11. 根据权利要求9所述的阵列基板，其中，所述第一金属布线层的厚度大于所述第二金属布线层的厚度；所述驱动引线均位于所述第一金属布线层。
  12. 根据权利要求7所述的阵列基板，其中，沿所述阵列基板的长边方向，所述驱动引线在不同位置处的厚度差异不超过150％。
  13. 根据权利要求12所述的阵列基板，其中，沿所述阵列基板的长边方向，所述驱动引线两端的厚度不同；其中，所述驱动引线较厚一端的厚度，比所述驱动引线较薄一端的厚度大10％以上。
  14. 根据权利要求4所述的阵列基板，其中，所述阵列基板呈矩形，具有阵列分布的多个控制区域，且各个控制区域形成沿侧边方向排列的N个控制区域列，以及形成沿长边方向排列的2N个控制区域行；其中，N为正整数；
    任意一个所述第二焊盘组还包括用于与所述微芯片的芯片电源引脚连接的芯片电源子焊盘、用于与所述微芯片的第一电源引脚连接的第一电源子焊盘、用于与所述微芯片的驱动数据引脚连接的驱动数据子焊盘、用于与所述微芯片的控制信号引脚连接的控制信号子焊盘；
    所述阵列基板还包括金属布线层，所述金属布线层包括多个连接引线和多个沿所述长边方向延伸的驱动引线；
    在任意一个所述控制区域列内，所述驱动引线包括两根用于加载第二电源电压的第二电源电压引线、一根用于加载芯片电源电压的芯片电源引线、两根用于加载芯片控制信号的芯片控制引线、一根用于加载第一电源电压的第一电源电压引线和一根用于加载驱动数据的驱动数据引线；
    在任意一个所述控制区域内，所述阵列基板包括一个所述第二焊盘组和与所述第二焊盘组中的各个所述数据子焊盘一一对应的多个焊盘连接电路；任意一个 所述焊盘连接电路包括至少一个所述第一焊盘组，且各个所述第一焊盘组通过所述连接引线连接；各个所述焊盘连接电路的第一端通过所述连接引线与对应的所述数据子焊盘连接；
    其中，在任意一个所述控制区域内，部分所述焊盘连接电路的第二端与一根所述第二电源电压引线通过所述连接引线电连接，其余所述焊盘连接电路的第二端与另一根所述第二电源电压引线通过所述连接引线电连接；所述芯片电源子焊盘与所述芯片电源引线通过所述连接引线电连接，所述第一电源子焊盘与所述第一电源电压引线通过所述连接引线电连接，所述驱动数据子焊盘与所述驱动数据引线通过所述连接引线电连接；
    在所述阵列基板中，各个所述芯片控制引线与各个所述控制区域行一一对应设置，且任意一个所述控制区域行中的各个的控制信号子焊盘均与对应的所述芯片控制引线通过所述连接引线电连接。
  15. 根据权利要求14所述的阵列基板，其中，在所述阵列基板中，第i行所述控制区域行中的各个所述控制信号子焊盘均与第i根所述芯片控制引线通过所述连接引线电连接；或者，
    在所述阵列基板中，第i行所述控制区域行中的各个所述控制信号子焊盘均与第2N-i+1根所述芯片控制引线通过所述连接引线电连接；
    其中，1≤i≤2N，且i为正整数。
  16. 一种发光基板，包括权利要求1～15任意一项所述的阵列基板。
  17. 根据权利要求16所述的发光基板，其中，所述发光基板还包括与所述多个第一焊盘组一一对应绑定的多个发光元件；和/或，所述发光基板还包括与各个所述第二焊盘组一一对应绑定的多个微芯片。
  18. 根据权利要求16或者17所述的发光基板，其中，所述发光基板包括多个相互拼接的所述阵列基板。
  19. 根据权利要求18所述的发光基板，其中，沿所述阵列基板的长边方向，驱动引线两端的厚度不同，
    所述发光基板具有相对设置的第一边和第二边，各个所述阵列基板沿所述第一边的延伸方向并排排列；各个阵列基板中所述驱动引线的厚度较大的部分，均靠近所述发光基板的第一边；各个阵列基板中所述驱动引线的厚度较小的部分，均靠近所述发光基板的第二边。
  20. 一种发光基板的制备方法，包括：
    提供一衬底母板，所述衬底母板包括多个待形成阵列基板的衬底区域；任意一个所述衬底区域具有垂直于所述衬底区域所在平面的中心轴；
    在各个所述衬底区域上形成各个所述阵列基板的驱动引线和焊盘层；任意一 个所述阵列基板的所述驱动引线具有靠近所述衬底母板边缘的第一端和远离所述衬底母板边缘的第二端；任意一个所述阵列基板的所述焊盘层包括多个第一焊盘组，且多个所述第一焊盘组以所述衬底基板的中心轴为对称中心，呈中心对称分布；
    切割所述衬底母板，以获得各个所述阵列基板；
    在任意一个所述阵列基板上设置发光元件层，所述发光元件层包括与所述阵列基板的各个所述第一焊盘组一一对应地绑定的多个发光元件；
    将多个所述阵列基板拼接成发光基板；其中，在同一所述发光基板中，各个所述阵列基板沿垂直于所述驱动引线的延伸方向排列，且各个所述阵列基板的所述驱动引线的第一端均靠近所述发光基板的一边缘，各个所述阵列基板的所述驱动引线的第二端均靠近所述发光基板的另一边缘。
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