WO2024065412A1 - 覆晶薄膜及显示装置 - Google Patents

覆晶薄膜及显示装置 Download PDF

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Publication number
WO2024065412A1
WO2024065412A1 PCT/CN2022/122676 CN2022122676W WO2024065412A1 WO 2024065412 A1 WO2024065412 A1 WO 2024065412A1 CN 2022122676 W CN2022122676 W CN 2022122676W WO 2024065412 A1 WO2024065412 A1 WO 2024065412A1
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WIPO (PCT)
Prior art keywords
area
pattern
binding
pad
pads
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PCT/CN2022/122676
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English (en)
French (fr)
Inventor
董水浪
曲燕
卢鑫泓
李国腾
李柳青
周靖上
李宝曼
Original Assignee
京东方科技集团股份有限公司
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Priority to PCT/CN2022/122676 priority Critical patent/WO2024065412A1/zh
Publication of WO2024065412A1 publication Critical patent/WO2024065412A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a chip-on-film and a display device.
  • COF Chip On Film packaging technology came into being.
  • COF is composed of a driver chip (source driver chip IC or gate driver chip IC) bonded and installed on a flexible wiring substrate that forms a wiring pattern.
  • the wiring pattern of COF is usually composed of inner leads connected to the electrodes of the driver chip and outer leads connected to the external circuit.
  • an embodiment of the present disclosure provides a flip chip film, comprising:
  • a base substrate comprising a plurality of binding regions and a peripheral region disposed around each of the binding regions;
  • a plurality of pads are located on the substrate, and each of the binding areas is provided with a plurality of pads;
  • the accompanying plating pattern is provided in the same layer and with the same material as the plurality of pads, and the accompanying plating pattern is located in the peripheral area on at least one side of the binding area.
  • the pads are arranged into multiple rows along the extension direction of the pads, the peripheral area includes a first peripheral area on the side where the first row of pads is located, and the second peripheral area on the side where the last row of pads is located, and the accompanying plating pattern includes a first accompanying plating pattern located in the first peripheral area and/or the second peripheral area.
  • the first accompanying plating pattern corresponds one-to-one with each of the pads in the first row and/or each of the pads in the last row, and the first accompanying plating pattern is integrally arranged with the corresponding pads.
  • one of the plurality of binding regions includes a first sub-binding region and a second sub-binding region arranged side by side in the extension direction of the pad;
  • the peripheral region further includes a third peripheral region located between the first sub-binding region and the second sub-binding region, and the accompanying plating pattern includes a plurality of second accompanying plating patterns located in the third peripheral region.
  • the above-mentioned flip chip film provided in the embodiments of the present disclosure further includes a plurality of support patterns, and the plurality of support patterns are located in the third peripheral region.
  • the third peripheral region includes a first edge region adjacent to the first sub-binding region, and a second edge region adjacent to the second sub-binding region;
  • the flip chip film further includes at least two groups of common routing lines, each group of the common routing lines includes a first common routing line and a second common routing line, wherein the first common routing line is led out from the second sub-binding area and extends in the first edge area, and the second common routing line is led out from the second sub-binding area and extends in the second edge area;
  • each pattern is evenly distributed in the area between each group of the common routing lines and in the area between the first common routing line and the second common routing line in each group of the common routing lines.
  • the plurality of support patterns are integrally provided with a portion of the second accompanying plating pattern.
  • the support pattern in the above-mentioned flip chip film provided in the embodiments of the present disclosure, is symmetrically arranged about the central axis of the combined pattern extending in the intersecting direction of the extension direction of the pad.
  • the second accompanying plating pattern separated from the supporting pattern is an independent pattern, and each of the combined patterns is evenly distributed in the area between each group of the common routing lines and in the area between the first common routing line and the second common routing line in each group of the common routing lines.
  • the length of the combined pattern and the length of the independent pattern are respectively more than 50% of the distance between the first common routing line and the second common routing line.
  • the second accompanying plating pattern separated from the supporting pattern is an independent pattern
  • each of the combined patterns forms at least one row
  • each of the independent patterns forms at least two rows
  • at least one row of the combined patterns and at least two rows of the independent patterns are arranged in the extension direction of the pad, and the row where the combined pattern is located is farther away from the first edge area and the second edge area than the row where the independent pattern is located.
  • the shape and width of the combined pattern, and the shape and width of the independent pattern are substantially the same as the shape and width of the pad, respectively.
  • the second accompanying plating pattern spaced apart from the supporting pattern is an independent pattern, each of the combined patterns forms at least one row, and the independent pattern is a strip-shaped accompanying plating pattern between the area where the combined pattern is located and the first sub-binding area, and between the area where the combined pattern is located and the second sub-binding area;
  • a length of the strip-shaped accompanying plating pattern is greater than or equal to a distance between a start and end position of a row of the pads.
  • the length of the first accompanying plating pattern in the extension direction of the pad is greater than or equal to 300 ⁇ m and less than or equal to 1000 ⁇ m.
  • the peripheral area includes a fourth peripheral area and a fifth peripheral area, the fourth peripheral area and the fifth peripheral area extend in the extending direction of the pad, and in the intersecting direction of the extending direction of the pad, the fourth peripheral area and the fifth peripheral area are located on both sides of the binding area;
  • the chip-on-film further includes alignment marks located in the fourth peripheral area and the fifth peripheral area, and the alignment marks are provided in the same layer and the same material as the plurality of pads;
  • the accompanying plating pattern includes a third accompanying plating pattern located in the fourth peripheral area and/or the fifth peripheral area, and the third accompanying plating pattern is arranged around the alignment mark on both sides of the intersection of the alignment mark and the extension direction of the pad, and at least one side of the side of the alignment mark away from the binding area, and there is a preset distance between the third accompanying plating pattern and the alignment mark.
  • the third accompanying plating pattern is a block pattern.
  • the third accompanying plating pattern includes a plurality of strip patterns sequentially arranged in the extension direction of the pad.
  • the length of the third accompanying plating pattern in the intersection direction with the pad extension direction is greater than or equal to 1 mm and less than or equal to 5 mm.
  • the distance from the end surface of the third plating pattern away from the binding area to the binding area is substantially the same as the length of the first plating pattern.
  • the above-mentioned flip chip film provided in the embodiments of the present disclosure further includes a first protective pattern located on the side of the layer where the multiple pads are located away from the base substrate, and the orthographic projection of the first protective pattern on the base substrate overlaps with the orthographic projections of the first co-plating pattern and the third co-plating pattern arranged side by side in the cross direction of the pad extension direction on the base substrate, and in the pad extension direction, there is a preset distance between the orthographic projection of the first protective pattern on the base substrate and the binding area.
  • the plurality of binding regions include a first binding region for binding a display substrate, and a second binding region for binding a circuit board.
  • two adjacent rows of the pads are partially staggered along a direction intersecting with an extending direction of the pads.
  • the above-mentioned flip chip film provided in the embodiments of the present disclosure further includes a second protection pattern integrally arranged with the first protection pattern, and the orthographic projection of the second protection pattern on the base substrate overlaps with the orthographic projection of the third accompanying plating pattern on the base substrate, and in the cross direction of the pad extension direction, there is a preset distance between the orthographic projection of the second protection pattern on the base substrate and the binding area.
  • the plurality of binding regions include a third binding region for binding the driving chip.
  • the third binding area includes the first sub-binding area and the second sub-binding area, and in the first sub-binding area and the second sub-binding area, two adjacent rows of pads are partially staggered along a direction intersecting with an extension direction of the pads;
  • the second sub-binding area includes a first signal output area and a second signal output area arranged side by side, and a signal input area located between the first signal output area and the second signal output area;
  • the first sub-binding area includes a third signal output area and a fourth signal output area.
  • the third signal output area and the first signal output area are arranged side by side in the extending direction of the pad.
  • the fourth signal output area and the second signal output area are arranged side by side in the extending direction of the pad.
  • an embodiment of the present disclosure provides a display device, including a display substrate, a circuit board, a driver chip and a chip-on-chip film, wherein the chip-on-chip film is the above-mentioned chip-on-chip film provided in the embodiment of the present disclosure, and the chip-on-chip film includes binding areas corresponding one by one to the display substrate, the driver chip and the circuit board.
  • FIG1 is a schematic diagram showing a thicker pad at the edge of a binding area provided by an embodiment of the present disclosure
  • FIG2 is a schematic diagram of an area where a thicker pad is located in a binding area for binding a display substrate or a flexible circuit board provided by an embodiment of the present disclosure
  • FIG3 is a schematic diagram of an area where a relatively thick pad is located in a binding area for binding a driver chip provided by an embodiment of the present disclosure
  • FIG4 is a schematic structural diagram of a chip-on-chip film provided in an embodiment of the present disclosure.
  • FIG5 is a schematic diagram of another structure of a chip-on-chip film provided in an embodiment of the present disclosure.
  • FIG6 is a schematic diagram of an enlarged structure of the M1 region in FIG5 ;
  • FIG7 is a schematic diagram of an enlarged structure of the M2 region in FIG5;
  • FIG8 is a schematic diagram of an enlarged structure of the M3 region in FIG5 ;
  • FIG9 is another enlarged structural schematic diagram of the M2 region in FIG5 ;
  • FIG10 is another enlarged structural schematic diagram of the M2 region in FIG5 ;
  • FIG11 is another enlarged structural schematic diagram of the M1 region in FIG5 ;
  • FIG12 is another enlarged structural schematic diagram of the M2 region in FIG5 ;
  • FIG13 is another enlarged structural schematic diagram of the M1 region in FIG5 ;
  • FIG14 is another enlarged structural schematic diagram of the M2 region in FIG5 ;
  • FIG15 is another enlarged structural schematic diagram of the M3 region in FIG5 ;
  • FIG16 is another enlarged structural schematic diagram of the M2 region in FIG5 ;
  • FIG17 is another enlarged structural schematic diagram of the M2 region in FIG5 ;
  • FIG18 is another enlarged structural schematic diagram of the M1 region in FIG5 ;
  • FIG19 is another enlarged structural schematic diagram of the M2 region in FIG5 ;
  • FIG20 is a schematic diagram of a structure of a flip chip film during the manufacturing process provided by an embodiment of the present disclosure
  • FIG21 is a schematic diagram of a local structure of a layer where leads are provided in an embodiment of the present disclosure
  • Fig. 22 is a cross-sectional view along the I-I' direction in Fig. 21;
  • FIG23 is a schematic diagram of the structure of the layer where the leads are provided in an embodiment of the present disclosure.
  • FIG24 is a schematic diagram of the enlarged structure of the M4 region in FIG23;
  • FIG25 is another structural schematic diagram of a flip chip film during the manufacturing process provided by an embodiment of the present disclosure.
  • FIG26 is another structural schematic diagram of a chip-on-chip film during the manufacturing process provided by an embodiment of the present disclosure.
  • FIG27 is another structural schematic diagram of a chip-on-chip film during the manufacturing process provided by an embodiment of the present disclosure.
  • FIG28 is another structural schematic diagram of a chip-on-chip film during the manufacturing process provided by an embodiment of the present disclosure.
  • FIG29 is another structural schematic diagram of a chip-on-chip film during the manufacturing process provided by an embodiment of the present disclosure.
  • FIG30 is another structural schematic diagram of a chip-on-chip film during the manufacturing process provided by an embodiment of the present disclosure.
  • FIG31 is a schematic diagram of a structure of a display device provided in an embodiment of the present disclosure.
  • FIG32 is a schematic diagram of the structure after the display substrate or the flexible circuit board is bound to the chip-on-film according to an embodiment of the present disclosure
  • FIG33 is a schematic diagram of a structure after a driver chip and a flip chip film are bound together according to an embodiment of the present disclosure
  • FIG34 is another schematic diagram of a structure after a driver chip and a flip chip film are bound together according to an embodiment of the present disclosure
  • FIG35 is a schematic diagram of another structure of a display device provided in an embodiment of the present disclosure.
  • FIG. 36 is another schematic diagram of the structure of the display device provided in the embodiment of the present disclosure.
  • the inventors fabricated leads and pads (Pad) on a flexible substrate (PI) in layers, wherein the leads include a laminated structure consisting of a stacked titanium metal layer/aluminum metal layer/titanium metal layer, and the pads include a single-layer copper structure.
  • the leads include a laminated structure consisting of a stacked titanium metal layer/aluminum metal layer/titanium metal layer, and the pads include a single-layer copper structure.
  • the small area of the pad will lead to an uneven proportion of local copper, resulting in the concentration of power lines around the pad (P) and an increase in current density during the electroplating process, as shown in FIG1 ,
  • the pad (P) near the edge is thicker, resulting in a large difference in pad thickness, which can easily lead to poor binding.
  • the pad P in the edge area A is more than 2 ⁇ m thick, which can easily lead to poor binding.
  • the pads in the edge area B and the middle area C are too thick, which can also easily lead to poor binding.
  • the embodiment of the present disclosure provides a flip chip film, as shown in FIG. 4 to FIG. 8 , comprising:
  • a base substrate 101 includes a plurality of binding areas (e.g., a first binding area BA 1 for binding a display substrate, a second binding area BA 2 for binding a flexible circuit board, and a third binding area BA 3 for binding a driver chip), and a peripheral area (e.g., a first peripheral area SA 1 , a second peripheral area SA 2 , a third peripheral area SA 3 , a fourth peripheral area SA 4 , and a fifth peripheral area SA 5 ) arranged around each binding area (e.g., the first binding area BA 1 , the second binding area BA 2 , and the third binding area BA 3 ); the base substrate 101 may be a flexible substrate made of a material such as polyimide;
  • a plurality of pads 102 are located on the substrate 101.
  • Each binding area eg, the first binding area BA 1 , the second binding area BA 2 , and the third binding area BA 3 ) is provided with a plurality of pads 102.
  • the material of the pads 102 may be copper, etc.;
  • the accompanying plating pattern 103 is provided in the same layer and with the same material as the plurality of pads 102, and is located in a peripheral area (e.g., first peripheral area SA1 , second peripheral area SA2 , third peripheral area SA3 , fourth peripheral area SA4 , fifth peripheral area SA5 ) on at least one side of the binding area (e.g., first binding area BA1 , second binding area BA2 , third binding area BA3 ).
  • a peripheral area e.g., first peripheral area SA1 , second peripheral area SA2 , third peripheral area SA3 , fourth peripheral area SA4 , fifth peripheral area SA5 .
  • a companion plating pattern 103 of the same layer and the same material as the pad 102 can be simultaneously formed in the peripheral area (e.g., the first peripheral area SA1 , the second peripheral area SA2 , the third peripheral area SA3 , the fourth peripheral area SA4 , and the fifth peripheral area SA5 ).
  • the peripheral area (for example, the first peripheral area SA 1 , the second peripheral area SA 2 , the third peripheral area SA 3 , the fourth peripheral area SA 4 , and the fifth peripheral area SA 5 ) where the accompanying plating pattern 103 is located is located outside the binding area (for example, the first binding area BA 1 , the second binding area BA 2 , and the third binding area BA 3 ) where the pad 102 is located, the phenomenon of more concentrated electric lines and higher current density will occur in the peripheral area (for example, the first peripheral area SA 1 , the second peripheral area SA 2 , the third peripheral area SA 3 , the fourth peripheral area SA 4 , and the fifth peripheral area SA 5 ) during the electroplating process, thereby ensuring that the electric lines and current density in the binding area (for example, the first binding area BA 1 , the second binding area BA 2 , and the third binding area BA 3 ) are normal, and then a pad 102 with uniform thickness can be formed in the binding area (for example, the first binding area BA 1 , the second binding area BA 2
  • the present disclosure may enable the thickness uniformity difference of the pads 102 in the bonding areas (eg, the first bonding area BA 1 , the second bonding area BA 2 , and the third bonding area BA 3 ) to be less than 1 ⁇ m.
  • each pad 102 in each binding area (for example, the first binding area BA1 , the second binding area BA2 , and the third binding area BA3 ), is arranged into multiple rows along its extension direction Y, and the peripheral area includes a first peripheral area SA1 on the side where the first row of pads 102 are located, and a second peripheral area SA2 on the side where the last row of pads 102 are located, and the accompanying plating pattern 103 includes a first accompanying plating pattern 31 located in the first peripheral area SA1 and/or the second peripheral area SA2 .
  • the edge area is the area where the electric force lines are concentrated and the current density is high during the electroplating process, which makes the thickness of the first row of pads 102 and the end of the last row of pads 102 away from the binding area (e.g., the first binding area BA 1 , the second binding area BA 2 , and the third binding area BA 3 ) tend to be thicker.
  • the first accompanying plating pattern 31 in the first peripheral area SA 1 on the side where the first row of pads 102 are located and/or the second peripheral area SA 2 on the side where the last row of pads 102 are located it is equivalent to transferring the area where the electric force lines are concentrated and the current density is relatively high to the first peripheral area SA 1 and/or the second peripheral area SA 2 , so as to meet the normal electric force lines and current density in the edge area where the first row of pads 102 and the last row of pads 102 are located, and then the first row of pads 102 and the last row of pads 102 with uniform thickness can be formed.
  • the first accompanying plating pattern 31 may correspond to each pad 102 in the first row and/or each pad 102 in the last row, and the first accompanying plating pattern 31 is integrally provided with the corresponding pad 102.
  • each pad 102 in the first row and/or each pad 102 in the last row may be extended toward the first peripheral area SA 1 and/or the second peripheral area SA 2 , and the portion of the pad 102 extending to the first peripheral area SA 1 and/or the second peripheral area SA 2 may be used as the first accompanying plating pattern 31.
  • the length of the first accompanying plating pattern 31 in the extension direction Y of the pad 102 can be greater than or equal to 300 ⁇ m and less than or equal to 1000 ⁇ m.
  • the length of the first accompanying plating pattern 31 in the extension direction Y of the pad 102 is 300 ⁇ m, 400 ⁇ m, 500 ⁇ m, 600 ⁇ m, 700 ⁇ m, 800 ⁇ m, 900 ⁇ m, 1000 ⁇ m, etc.
  • one of the plurality of binding areas (e.g., the first binding area BA1 , the second binding area BA2 , and the third binding area BA3 ) (e.g., the third binding area BA3 ) includes a first sub-binding area BA31 and a second sub-binding area BA32 arranged side by side in the extension direction Y of the pad 102, and a row of pads 102 farthest from the second sub-binding area BA32 in the first sub-binding area BA31 is the first row of pads 102 in the binding area (e.g., the third binding area BA3 ), and a row of pads 102 farthest from the first sub-binding area BA31 in the second sub-binding area BA32 is the last row of pads 102 in the binding area (e.g., the third binding area BA3 ).
  • the peripheral area may also include a third peripheral area SA3 located between the first sub-binding area BA31 and the second sub-binding area BA32 .
  • the accompanying plating pattern 103 may include a plurality of second accompanying plating patterns 32 located in the third peripheral area SA 3.
  • the sum of the orthographic projection areas of all the second accompanying plating patterns 32 on the base substrate 101 accounts for less than 50% of the area of the third peripheral area SA 3 , and optionally about 40%, such as 45%, 40%, 35%, 30%, etc.
  • a plurality of support patterns ST may also be included. These support patterns ST are used to support the driver chip IC and balance the binding pressure, and may not load any electrical signal.
  • the plurality of support patterns ST are located in the third peripheral area SA 3 , and the ratio of the sum of the orthogonal projection areas of the plurality of support patterns ST on the base substrate 101 to the sum of the orthogonal projection areas of the gaps between the support patterns ST on the base substrate 101 is less than or equal to 1/9, which is equivalent to the sum of the orthogonal projection areas of all the support patterns ST on the base substrate 101 accounting for less than 10% of the area of the third peripheral area SA 3 , such as 10%, 9%, 8%, etc.
  • a second accompanying plating pattern 32 is provided at the gap between the supporting patterns ST.
  • the area of all the second accompanying plating patterns 32 of the present disclosure and all the supporting patterns ST in the third peripheral area SA 3 accounts for less than 50%, such as 30% to 50%.
  • the third peripheral area SA 3 includes a first edge area SA 31 adjacent to the first sub-binding area BA 31 , and a second edge area SA 32 adjacent to the second sub-binding area BA 32 ;
  • the flip chip film also includes at least two groups of common routing lines, each group of common routing lines includes a first common routing line CL 1 and a second common routing line CL 2 , wherein each first common routing line CL 1 of each group of common routing lines is led out from the second sub-binding area BA 32 and then extends in the first edge area SA 31 , and each second common routing line CL 2 of each group of common routing lines is led out from the second sub-binding area BA 32 and then extends in the second edge area SA 32 ; in order to ensure the thickness uniformity of the pads 102 on both sides of the third peripheral area SA 3 , in the pattern set composed of multiple support patterns ST and multiple second accompanying plating patterns 32, each pattern is evenly
  • the width of the support pattern ST is approximately the same as the width of the second accompanying plating pattern 32 (that is, the same or within the error range caused by factors such as manufacturing process and measurement).
  • the support pattern ST in the above-mentioned flip chip film provided in the embodiments of the present disclosure, as shown in Figures 7 to 10, in the combined pattern formed by the integrally arranged support pattern ST and the second accompanying plating pattern 32, the support pattern ST is symmetrically arranged about the central axis of the combined pattern extending in the intersecting direction X of the extension direction Y of the pad 102, that is, in the extension direction Y of the pad 102, both sides of the support pattern ST may have the second accompanying plating pattern 32 integrally arranged with the support pattern ST. Such an arrangement is conducive to the support pattern ST to more evenly support the driver chip IC.
  • the second accompanying plating pattern 32 separated from the support pattern ST is an independent pattern, and each combination pattern (composed of the support pattern ST and the second accompanying plating pattern 32 provided as one) is evenly distributed in the area between each group of common lines, and in the area between the first common line CL 1 and the second common line CL 2 in each group of common lines.
  • an independent pattern is provided between any two adjacent combination patterns.
  • the independent patterns can be distributed at approximately equal intervals between any two adjacent combination patterns.
  • the area of the independent pattern between any two adjacent combination patterns accounts for 30% to 50%, for example, 30%, 40%, 50%, etc.
  • uniform distribution in the present disclosure can be understood as “distribution at approximately equal intervals”, that is, the intervals between adjacent patterns are the same or within the error range caused by factors such as manufacturing and measurement.
  • the flip chip film in order to ensure the area ratio of multiple support patterns ST and multiple second accompanying plating patterns 32 in the third peripheral area SA 3 , it can be set in the extension direction Y of the pad 102, and the length of the combined pattern (composed of the support pattern ST and the second accompanying plating pattern 32 set as one) and the length of the independent pattern (the second accompanying plating pattern 32 separated from the support pattern ST) are respectively more than 50% of the distance between the first common wiring CL 1 and the second common wiring CL 1 , for example, 50%, 60%, 70%, 80%, 90%, etc.
  • each combined pattern (composed of the integrally arranged support pattern ST and the second accompanying plating pattern 32) forms at least one row
  • each independent pattern (the second accompanying plating pattern 32 separated from the support pattern ST) forms at least two rows
  • at least one row of combined patterns and at least two rows of independent patterns are arranged in the extension direction Y of the pad 102, and the row where the combined pattern is located is farther away from the first edge area SA 31 and the second edge area SA 32 than the row where the independent pattern is located
  • the combined pattern composed of the support pattern ST and the second accompanying plating pattern 32 can be evenly arranged in the middle area located in the third peripheral area SA 3 , so as to evenly support the driver chip IC through the support pattern ST.
  • a part of the first common wiring CL 1 and a part of the second common wiring CL 2 can also be used to support the driver chip IC.
  • the shape and width (i.e., the dimension in the cross direction X of the extension direction Y of the pad 102) of the combined pattern (composed of the integrally arranged support pattern ST and the second accompanying plating pattern 32) and the shape and width of the independent pattern (the second accompanying plating pattern 32 separated from the support pattern ST) can be roughly the same as the shape and width of the pad 102 (i.e., the shape is the same or similar, the width is the same or within the error range caused by factors such as manufacturing and measurement).
  • the height (also referred to as thickness) and length (i.e., the dimension in the extension direction Y of the pad 102) of the combined pattern and the height and length of the independent pattern can also be roughly the same as the height and length of the pad 102 (i.e., the same or within the error range caused by factors such as manufacturing and measurement).
  • a chip bump (IC Bump) is set on the side of the support pattern ST away from the substrate.
  • each combined pattern (composed of an integrally arranged support pattern ST and a second accompanying plating pattern 32) forms at least one row
  • each independent pattern (a second accompanying plating pattern 32 separated from the support pattern ST) is a strip accompanying plating pattern located between the area where the combined pattern is located and the first sub-binding area BA 31 , and between the area where the combined pattern is located and the second sub-binding area BA 32.
  • the length of the strip accompanying plating pattern 322 is greater than or equal to the distance between the starting and ending positions of a row of pads 102; in some embodiments, in the intersecting direction X of the extension direction Y of the pad 102, the length of the strip accompanying plating pattern may be greater than the length of the driver chip IC.
  • the peripheral area may include a fourth peripheral area SA 4 and a fifth peripheral area SA 5 , the fourth peripheral area SA 4 and the fifth peripheral area SA 5 respectively extend in the extension direction Y of the pad 102, and in the cross direction X of the extension direction Y of the pad 102, the fourth peripheral area SA 4 and the fifth peripheral area SA 5 are separated on both sides of the binding area (for example, the first binding area BA 1 , the second binding area BA 2 , and the third binding area BA 3 ); the flip chip film may also include an alignment mark 104 located in the fourth peripheral area SA 4 and the fifth peripheral area SA 5 , and the alignment mark 104 is set in the same layer and the same material as the multiple pads 102; the accompanying plating pattern 103 includes a fourth peripheral area SA 4 and/or the fifth peripheral area SA 5.
  • the third accompanying plating pattern 33 is arranged around the alignment mark 104 on at least one side of the two sides where the alignment mark 104 and the extension direction Y of the solder pad 102 are intersected, and the side of the alignment mark 104 away from the binding area, and there is a preset distance l (for example, 0.3 mm) between the third accompanying plating pattern 33 and the alignment mark 104.
  • the electric force lines are concentrated and the current density is large during the electroplating process, resulting in poor thickness uniformity of the pad 102 in the edge area.
  • the third accompanying plating pattern 33 in the fourth peripheral area SA 4 and/or the fifth peripheral area SA 5 it is equivalent to transferring the area with concentrated electric force lines and high current density to the fourth peripheral area SA 4 and/or the fifth peripheral area SA 5 , so that the electric force lines and current density in the edge area of the binding area (e.g., the first binding area BA 1 , the second binding area BA 2 , the third binding area BA 3 ) adjacent to the fourth peripheral area SA 4 and/or the fifth peripheral area SA 5 are normal, and thus the pad 102 with uniform thickness can be formed.
  • the binding area e.g., the first binding area BA 1 , the second binding area BA 2 , the third binding area BA 3
  • a preset distance (e.g., 0.3 mm) is provided between the third accompanying plating pattern 33 and the alignment mark 104, which can ensure that the third accompanying plating pattern 33 and the alignment mark 104 are relatively independent, which is convenient for identifying the alignment mark 104 in the subsequent binding process and improving the binding yield.
  • the third accompanying plating pattern 33 does not load any electrical signal.
  • the third accompanying plating pattern 33 may include a plurality of strip patterns sequentially arranged in the extension direction Y of the pad 102; or, as shown in FIG11 and FIG12, the third accompanying plating pattern 33 may be a block pattern.
  • the third accompanying plating pattern 33 may be arranged in the fourth peripheral area SA4 and the fifth peripheral area SA5 within a range of 1mm to 5mm from the binding area (e.g., the first binding area BA1 , the second binding area BA2 , the third binding area BA3 ), that is, on both sides of the cross direction X between the alignment mark 104 and the extension direction Y of the pad 102, the length l1 of the third accompanying plating pattern 33 in the cross direction X is greater than or equal to 1mm and less than or equal to 5mm, for example, 1mm, 2mm, 3mm, 4mm, 5mm, etc.
  • the length of the third accompanying plating pattern 33 in the cross direction X is approximately equal to (l 1 -l 2 -l), where l 2 is the length of the alignment mark 104 in the cross direction X, and l is the preset distance between the alignment mark 104 and the third accompanying plating pattern 33 in the cross direction X.
  • the distance from the end surface of the third accompanying plating pattern 33 away from the binding area (e.g., the first binding area BA1 , the second binding area BA2 , the third binding area BA3 ) to the binding area (e.g., the first binding area BA1 , the second binding area BA2 , the third binding area BA3 ) is approximately the same as the length of the first accompanying plating pattern 31, that is, the two are the same or within the error range caused by factors such as manufacturing and measurement.
  • the flip chip film in the above-mentioned flip chip film provided in the embodiments of the present disclosure, as shown in Figures 13 to 19, it can also include a first protection pattern 105 located on the side of the layer where the multiple pads 103 are located away from the base substrate 101, and the orthographic projection of the first protection pattern 105 on the base substrate 101 overlaps with the orthographic projections of the first accompanying plating pattern 31 and the third accompanying plating pattern 33 arranged side by side in the cross direction X of the extension direction Y of the pad 102 on the base substrate 101, and in the extension direction Y of the pad 102, the orthographic projection of the first protection pattern 105 on the base substrate 101 has a preset distance (for example, a preset distance of 100 ⁇ m) between the binding area (for example, the first binding area BA 1 , the second binding area BA 2 , the third binding area BA 3 ).
  • a preset distance for example, a preset distance of 100 ⁇ m
  • the first protection pattern 105 can improve the flatness of the positions of the first accompanying plating pattern 31 and the third accompanying plating pattern 33 covered by it; and considering the manufacturing accuracy of the first protection pattern 105 and the need for overflow space in the subsequent bonding process of the display substrate and the flip chip film through anisotropic conductive adhesive (ACF), the present disclosure sets a preset distance between the first protection pattern 105 and the bonding area (e.g., the first bonding area BA 1 , the second bonding area BA 2 , and the third bonding area BA 3 ), so that the first protection pattern 105 only covers the partial area of the first accompanying plating pattern 31 away from the bonding area (e.g., the first bonding area BA 1 , the second bonding area BA 2 , and the third bonding area BA 3 ) and the partial third accompanying plating pattern 33 arranged side by side with the partial area.
  • ACF anisotropic conductive adhesive
  • the first protection pattern 105 can be set in the same layer and the same material as the solder mask layer in the related art.
  • the material of the first protection pattern 105 is green oil (SR) with a thickness of 5 ⁇ m to 20 ⁇ m, such as 5 ⁇ m, 10 ⁇ m, 15 ⁇ m, 20 ⁇ m, etc.
  • the flip chip film in the above-mentioned flip chip film provided in the embodiments of the present disclosure, as shown in Figures 14, 16, 17 and 19, it can also include a second protection pattern 106 integrally provided with the first protection pattern 105, and the orthographic projection of the second protection pattern 106 on the base substrate 101 overlaps with the orthographic projection of the third accompanying plating pattern 33 on the base substrate 101, and in the intersection direction X of the extension direction Y of the pad 102, there is a preset distance (for example, 100 ⁇ m ⁇ 200 ⁇ m) between the orthographic projection of the second protection pattern 106 on the base substrate 101 and the binding area (for example, the third binding area BA3 ).
  • a preset distance for example, 100 ⁇ m ⁇ 200 ⁇ m
  • the second protection pattern 106 can improve the flatness of the position where the third accompanying plating pattern 33 covered by it is located; and considering the manufacturing accuracy of the second protection pattern 106, in order to prevent the second protection pattern 106 from covering the pad 102, the present disclosure provides a preset distance between the second protection pattern 105 and the binding area (for example, the third binding area BA 3 ), so that the second protection pattern 105 only covers a partial area of the third accompanying plating pattern 33 away from the binding area (for example, the third binding area BA 3 ).
  • the plurality of binding areas may include a first binding area BA 1 for binding the display substrate, and a second binding area BA 2 for binding the flexible circuit board. Since the size of the binding pressure head used in the binding process of the display substrate and the flexible circuit board in the cross direction X of the extension direction Y of the pad 102 is larger than the size of the binding area (e.g., the first binding area BA 1 and the second binding area BA 2 ), the pressure head will press the binding area (e.g., the first binding area BA 1 and the second binding area BA 2 ), and the fourth peripheral area SA 4 and the fifth peripheral area SA 5 at the same time.
  • the film layer height in the fourth peripheral area SA 4 and the fifth peripheral area SA 5 will be greater than the film layer height in the binding area (e.g., the first binding area BA 1 and the second binding area BA 2 ), so that the binding area (e.g., the first binding area BA 1 and the second binding area BA 2 ) cannot be uniformly stressed. Based on this, only the first protection pattern 105 may be disposed around the first bonding area BA 1 and the second bonding area BA 2 .
  • the multiple binding areas may further include a third binding area BA 3 for binding a driver chip IC. Since the size of the driver chip IC is approximately equal to the sum of the size of the third binding area BA 3 and the size of the third peripheral area SA 3 , the film layer height of the peripheral area around the third binding area BA 3 (for example, the first peripheral area SA 1 , the second peripheral area SA 2 , the fourth peripheral area SA 4 , and the fifth peripheral area SA 5 ) has no effect on the binding of the driver chip IC. Therefore, the first protection pattern 105 and the second protection pattern 106 can be simultaneously set around the third binding area BA 3 .
  • each row of pads 102 is arranged at equal intervals in the extension direction Y of the pads 102, and two adjacent rows of pads 102 are partially staggered along the cross direction X of the extension direction Y of the pads 102.
  • the present disclosure partially staggers any two adjacent rows of pads 102 in the cross direction X, which helps to ensure that there is a larger space for arranging the leads 107 electrically connected to the pads 102 in different rows.
  • the third binding area BA3 includes a first sub-binding area BA31 and a second sub-binding area BA32 , and in the first sub-binding area BA31 and the second sub-binding area BA32 , each row of pads 102 is arranged at equal intervals in the extension direction Y of the pads 102, and two adjacent rows of pads 102 are partially staggered along the intersection direction X with the extension direction Y of the pads 102; in the intersection direction X with the extension direction Y of the pads 102, the second sub-binding area BA32 includes a first signal output area O1 and a second signal output area O2 arranged side by side, and a signal input binding area I located between the first signal output area O1 and the second signal output area O2 ; the first sub-binding area BA31 includes a third signal output area O3 and a fourth signal output area O4 , the third
  • the rows of pads 102 in the first signal output area O 1 and the rows of pads 102 in the third signal output area O 3 are arranged symmetrically about the central axis of the driver chip IC along the cross direction X of the extension direction Y of the pad 102
  • the rows of pads 102 in the second signal output area O 2 and the rows of pads 102 in the fourth signal output area O 4 are arranged symmetrically about the central axis of the driver chip IC along the cross direction X of the extension direction Y of the pad 102.
  • the pads 102 of the first signal output area O 1 , the second signal output area O 2 , the third signal output area O 3 , and the fourth signal output area O 4 are respectively connected to the data pins (Source pin) of the display substrate through the leads 107 arranged on both sides of the driver chip IC to maximize the number of data pins; the pads 102 of the signal input binding area I are connected to the flexible circuit board through the leads 107 to receive the driving signal provided by the flexible circuit board.
  • the present disclosure also provides a method for manufacturing the above-mentioned chip-on-film, which may include the following steps:
  • a base substrate 101 is coated or laminated on the glass substrate G, and a barrier layer 108 is deposited on the base substrate 101;
  • the base substrate 101 may be a flexible substrate made of a material such as polyimide, and the thickness of the base substrate 101 may be greater than or equal to 10 ⁇ m and less than or equal to 40 ⁇ m, for example, the thickness of the base substrate 101 is 10 ⁇ m, 20 ⁇ m, 30 ⁇ m, 40 ⁇ m, etc.
  • the material of the barrier layer 108 may be silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), etc.
  • the barrier layer 108 may be a single-layer structure or a stacked-layer structure, and the thickness of the barrier layer 108 may be greater than or equal to 100 nm and less than or equal to 500 nm, for example, the thickness of the barrier layer 108 may be 100 nm, 200 nm, 300
  • a metal film layer is deposited on the barrier layer 108.
  • the material of the metal film layer can be molybdenum (Mo), aluminum (Al), titanium (Ti) and other materials suitable for dry etching.
  • the metal film layer can be a single-layer metal or a laminated metal.
  • the metal film layer is a triple-layer composed of a titanium metal layer/an aluminum metal layer/a titanium metal layer.
  • the thickness of the metal film layer composed of the titanium metal layer/an aluminum metal layer/a titanium metal layer is greater than or equal to 500 nm and less than or equal to 1000 nm.
  • the thickness of the metal film layer is 500 nm, 600 nm, 700 nm, etc. , 800nm, 900nm, 1000nm, etc.; then the metal film layer is patterned to form a lead 107.
  • the metal film layer is etched by a dry etching process to form the lead 107.
  • the lead 107 includes a routing portion 71 and a widened portion 72 for connecting the subsequent pad 102; limited by the accuracy of the binding equipment, the spacing of the widened portion 72 needs to be greater than 20 ⁇ m.
  • the spacing of the routing portion 71 in the densest wiring area between the widened portions 72 is less than 4 ⁇ m; in order to maximize the number of data pins (source pins), data lines are wired and connected above and below the third binding area BA 3 for binding the driver chip IC, and the lead 702 in the middle area of the lower end of the third binding area BA 3 is an input signal line (input line) for connecting the flexible circuit board.
  • an insulating layer 109 is formed on the layer where the lead 107 is located.
  • the material of the insulating layer 109 may be silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), etc.
  • the insulating layer 109 may be a single-layer structure or a stacked-layer structure. The thickness of the insulating layer 109 is greater than or equal to 100 nm and less than or equal to 500 nm.
  • the thickness of the insulating layer 109 is 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, etc., and a transfer hole V is provided in the insulating layer 109 at the position of the widened portion 72.
  • each widened portion 72 is electrically connected to a corresponding pad 102 manufactured subsequently through at least one transfer hole V.
  • a pad 102 is formed by electroplating on the insulating layer 109.
  • the pad 102 is made of copper.
  • the thickness of the pad 102 needs to be greater than or equal to 5 ⁇ m and less than or equal to 8 ⁇ m.
  • the thickness of the pad 102 is 5 ⁇ m, 6 ⁇ m, 7 ⁇ m, 8 ⁇ m, etc.
  • a plating pattern 103 and an alignment mark 104 are also formed.
  • the description of the plating pattern 103 and the alignment mark 104 please refer to the above text and will not be repeated here.
  • an anti-oxidation layer 110 is formed on the pad 102.
  • the material of the anti-oxidation layer 110 may be tin (Sn) metal or the like.
  • the anti-oxidation layer 110 may be formed by a chemical plating process.
  • the thickness of the anti-oxidation layer 110 is greater than or equal to 0.5 ⁇ m and less than or equal to 2 ⁇ m, for example, 0.5 ⁇ m, 1 ⁇ m, 1.5 ⁇ m, 2 ⁇ m, etc.; in addition, the surface of the pad 102 may be covered with indium tin oxide (ITO) to prevent the pad 102 from being oxidized.
  • ITO indium tin oxide
  • a solder resist layer 111 is brushed on the non-binding area above the anti-oxidation layer 110.
  • the material of the solder resist layer 111 can be green oil, and the thickness of the solder resist layer 111 can be greater than or equal to 5 ⁇ m and less than or equal to 20 ⁇ m.
  • the thickness of the solder resist layer 111 is 5 ⁇ m, 10 ⁇ m, 15 ⁇ m, 20 ⁇ m, etc.; it should be noted that while forming the solder resist layer 111, a first protection pattern 105 and a second protection pattern 106 that partially cover the accompanying plating pattern 103 can also be formed near the binding area (for example, the first binding area BA1 , the second binding area BA2 , and the third binding area BA3), and the description of the accompanying plating pattern 103 and the alignment mark 104 can be found above and will not be repeated here.
  • the large-sized chip-on-film is subjected to laser lift-off (LLO) to remove the glass substrate G, and the chip-on-film is cut to obtain multiple target-sized chips.
  • LLO laser lift-off
  • the flip chip film of the target size is bonded to the driver chip IC at the third bonding area BA 3 for bonding the driver chip IC, and is packaged by dispensing to obtain the flip chip film with the driver chip IC.
  • the patterning process involved in forming each layer structure may include not only part or all of the process such as deposition, photoresist coating, mask template masking, exposure, development, etching, photoresist stripping, etc., but also other process, which is subject to the pattern of the required composition formed in the actual manufacturing process and is not limited here.
  • a post-baking process may also be included after development and before etching.
  • the deposition process can be chemical vapor deposition, plasma enhanced chemical vapor deposition or physical vapor deposition, which is not limited here;
  • the mask plate used in the mask process can be a half tone mask (Half Tone Mask), a single slit diffraction mask (Single Slit Mask) or a gray tone mask (Gray Tone Mask), which is not limited here;
  • the etching can be dry etching or wet etching, which is not limited here.
  • an embodiment of the present disclosure provides a display device, as shown in FIG. 31 , which may include a chip-on-chip film 001, a display substrate 002, a driver chip IC and a circuit board (e.g., a flexible circuit board FPC), wherein the chip-on-chip film 001 is the above-mentioned chip-on-chip film 001 provided in an embodiment of the present disclosure, and the chip-on-chip film 001 includes binding areas corresponding one to one with the display substrate 001, the driver chip IC, and the circuit board (e.g., a flexible circuit board FPC).
  • a display device as shown in FIG. 31 , which may include a chip-on-chip film 001, a display substrate 002, a driver chip IC and a circuit board (e.g., a flexible circuit board FPC), wherein the chip-on-chip film 001 is the above-mentioned chip-on-chip film 001 provided in an embodiment of the present disclosure, and the chip-on-chip
  • the display substrate 002 is electrically connected to a first binding area BA 1 of the chip-on-chip film 001
  • the flexible circuit board FPC is electrically connected to a second binding area BA 2 of the chip-on-chip film 001
  • the driver chip IC is electrically connected to a third binding area BA 3 of the chip-on-chip film 001.
  • the pins 102' of the display substrate 002 or the flexible circuit board FPC are electrically connected one-to-one with the pads 102 of the corresponding binding area in the flip chip film 001.
  • the bumps BP of the driver chip IC are electrically connected one-to-one with the pads 102 of the first sub-binding area BA31 and the second sub-binding area BA32 , and in the third peripheral area SA3 between the first sub-binding area BA31 and the second sub-binding area BA32 , support patterns ST fixedly connected to the bumps BP of the driver chip IC are evenly arranged, and optionally, the bumps BP corresponding to the support patterns ST do not provide electrical signals, but only play a role in balancing the binding pressure.
  • a first common line CL 1 and a second common line CL 2 may be provided.
  • the first common line CL 1 and the second common line CL 2 may be connected to a power signal (Pwr), a ground signal (Gnd), etc. provided by a flexible circuit board FPC.
  • a bump BP in the driver chip IC that balances the binding pressure may also be fixedly connected to the common line CL.
  • the display device provided by the embodiments of the present disclosure may be a liquid crystal display device.
  • the liquid crystal display device includes a backlight module BLU and a liquid crystal display panel PNL located on the light-emitting side of the backlight module BLU.
  • the liquid crystal display panel may be a twisted nematic (TN) type liquid crystal display panel, an advanced dimension switch (ADS) type liquid crystal display panel, a high aperture ratio-advanced dimension switch (HADS) type liquid crystal display panel, an in-plane switch (IPS) type liquid crystal display panel, etc.
  • TN twisted nematic
  • ADS advanced dimension switch
  • HADS high aperture ratio-advanced dimension switch
  • IPS in-plane switch
  • the liquid crystal display panel PNL includes a first substrate 201 and a second substrate 202 disposed opposite to each other, a first liquid crystal layer 203 located between the first substrate 201 and the second substrate 202, a first sealant 204 surrounding the first liquid crystal layer 203 is provided between the first substrate 201 and the second substrate 202, a driving circuit 205 and a pixel electrode (not shown in the figure) may be provided on the side of the first substrate 201 facing the first liquid crystal layer 203, and a color filter 206 may be provided on the side of the second substrate 202 facing the first liquid crystal layer 203, and the color filter 206 includes a black matrix 61 and color resistance 62.
  • the common electrode (Com) of the liquid crystal display panel PNL can be arranged on the side of the layer where the driving circuit 205 is located away from the first substrate 201, or be arranged on the side of the color film 206 away from the second substrate 202.
  • the liquid crystal display panel PNL can also include a first polarizer (pol, not shown in the figure) located on the side of the first substrate 201 away from the first liquid crystal layer 203, and a second polarizer (pol, not shown in the figure) located on the side of the second substrate 202 away from the first liquid crystal layer 203, etc., wherein the transmittance axis of the first polarizer is perpendicular to the transmittance axis of the second polarizer.
  • the backlight module BLU can be a direct-type backlight module or an edge-type backlight module.
  • the edge-type backlight module may include a light bar, a reflective sheet stacked, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate.
  • the direct-type backlight module may include a matrix light source, a reflective sheet stacked on the light-emitting side of the matrix light source, a diffuser, and a brightness enhancement film, etc.
  • the reflective sheet includes an opening arranged directly opposite to the position of each lamp bead in the matrix light source.
  • the lamp beads in the light bar and the lamp beads in the matrix light source may be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.).
  • Submillimeter or even micron-scale micro-LEDs are self-luminous devices like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because the light emission of inorganic light-emitting diodes is based on metal semiconductors with more stable properties and lower resistance, compared with organic light-emitting diodes that emit light based on organic matter, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life. And when micro-LEDs are used as backlight sources, more precise dynamic backlight effects can be achieved. While effectively improving the brightness and contrast of the screen, it can also solve the glare caused by traditional dynamic backlighting between the bright and dark areas of the screen, optimizing the visual experience.
  • OLEDs organic light-emitting diodes
  • the display device provided by the embodiment of the present disclosure may be a 3D display device.
  • the display device may further include a liquid crystal grating LCG located between the backlight module BLU and the liquid crystal display panel PNL, and the liquid crystal grating LCG may be fixed to the liquid crystal display panel PNL through an adhesive layer 004.
  • the liquid crystal grating LCG may be controlled to form light-transmitting areas and light-shielding areas arranged alternately, so that the viewer's left eye sees the left eye image displayed by the display panel PNL through the light-transmitting area of the liquid crystal grating LCG, and the right eye sees the right eye image displayed by the display panel PNL through the light-transmitting area.
  • the liquid crystal grating LCG By arranging the liquid crystal grating LCG on the light-incident side of the liquid crystal display panel PNL, when the liquid crystal display panel PNL includes a touch electrode, the liquid crystal grating LCG will not shield the touch electrode in the liquid crystal display panel PNL, thereby avoiding the problem of touch failure, thereby improving the touch sensitivity and accuracy of the liquid crystal display panel PNL.
  • the liquid crystal grating LCG may include a third substrate 301 and a fourth substrate 302 disposed opposite to each other, a second liquid crystal layer 303 located between the third substrate 301 and the fourth substrate 302, a first strip electrode 304 located on a side of the third substrate 301 facing the second liquid crystal layer 303, a second strip electrode 305 located on a side of the layer where the first strip electrode 304 is located facing the second liquid crystal layer 303, a planar electrode 306 located on a side of the fourth substrate 302 facing the second liquid crystal layer 303, a first transistor T 1 electrically connected to the first strip electrode 304, a second transistor T 2 electrically connected to the second strip electrode 305, and a second encapsulation layer 307 surrounding the second liquid crystal layer 303 between the third substrate 301 and the fourth substrate 302.
  • the second liquid crystal layer 303 can be controlled to form a light-transmitting area and a light-shielding area, so as to cooperate with the liquid crystal display panel PNL that outputs left-eye images and right-eye images to achieve 3D display.
  • the display device provided by the embodiment of the present disclosure may be a 3D display device.
  • the 3D display device may further include a light splitting component SE located on the light-emitting side of the liquid crystal display panel PNL.
  • the light splitting component SE includes a plurality of light splitting structures 501 arranged parallel to each other and side by side.
  • the light splitting structure 501 may be a composite lens formed by a high-refractive resin layer 501a and a low-refractive resin layer 501b.
  • the high-refractive resin layer 501a is composed of a plurality of cylindrical lenses
  • the low-refractive resin layer 501b fills the gap between the cylindrical lenses and the thickness of the low-refractive resin layer is greater than the arch height of the cylindrical lens.
  • the cylindrical lens may be an angular or non-angular structure.
  • the composite lens may be a substrate 502 made of a transparent material.
  • the material of the substrate 502 may be polyethylene terephthalate (PET).
  • PET polyethylene terephthalate
  • a spacer glass 006 may be provided between the liquid crystal display panel PNL and the light splitting component SE, and the spacer glass 006 and the light splitting component SE may be bonded and fixed by optical glue 007.
  • the image plane of the liquid crystal display panel PNL is set on the focal plane of the cylindrical lens, and the pixels under each cylindrical lens are divided into several sub-pixels.
  • the pixels at different positions on the liquid crystal display panel PNL are refracted and split by the cylindrical lens, and the light path changes to form different viewpoints in space.
  • the left eye receives the left viewpoint image
  • the right eye also receives the right viewpoint image, thereby realizing 3D display.
  • liquid crystal display panel in the above-mentioned display device provided by the embodiment of the present disclosure can also be replaced by an electroluminescent display panel (Organic Light Emitting Diodes, OLED) or a quantum dot display panel (Quantum Dot Light Emitting Diodes, QLED), which is not limited here.
  • OLED Organic Light Emitting Diodes
  • QLED Quantum Dot Light Emitting Diodes
  • the OLED display panel or QLED display panel includes a light-emitting device and a pixel driving circuit electrically connected to the light-emitting device; wherein the light-emitting device may include a cathode and an anode disposed opposite to each other, and a light-emitting functional layer between the cathode and the anode; the pixel driving circuit may include a thin film transistor, a storage capacitor, etc., which can be implemented in various different types, such as a 2TIC type (i.e., including two thin film transistors and a storage capacitor), and can further include more transistors and/or capacitors on the basis of the 2T1C type to have functions such as compensation, reset, light emission control, detection, etc.
  • the thin film transistor directly electrically connected to the light-emitting element can be a driving transistor (Td) or a light emission control transistor (EM), etc.
  • the light-emitting functional layer includes, but is not limited to, a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting material layer, a hole blocking layer, an electron transport layer, an electron injection layer, etc.
  • the light-emitting material layer may be a red light material layer, a green light material layer, a blue light material layer, a yellow light material layer, a white light material layer, etc.
  • the light-emitting material layer may include a small molecule organic material or a polymer molecule, and may be a fluorescent light-emitting material, a phosphorescent light-emitting material, etc.
  • the light-emitting material layer may include silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, zinc selenide quantum dots, cadmium telluride quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, indium arsenide quantum dots, etc.
  • the material of the anode may include at least one transparent conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc.
  • the anode may include a metal with high reflectivity as a reflective layer, such as silver (Ag).
  • the material of the cathode may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag), etc.
  • the thin film transistor includes a gate, a source, a drain, and an active layer, wherein a material of the active layer may include amorphous silicon, polycrystalline silicon, or an oxide semiconductor (eg, indium gallium zinc oxide).
  • the materials of the gate, source and drain may include metal materials or alloy materials, such as a metal single layer or multilayer structure formed by molybdenum, aluminum and titanium, for example, the multilayer structure is a multi-metal layer stack (such as a three-layer metal stack of titanium, aluminum and titanium (Ti/Al/Ti).
  • the thin film transistor may be a bottom gate transistor, a top gate transistor, a double gate transistor, etc.
  • the thin film transistor may be a P-type transistor or an N-type transistor, wherein the P-type transistor is turned on when the voltage difference V gs between its gate and its source and its threshold voltage V th satisfy the relationship V gs ⁇ V th , and is turned off when the voltage difference V gs between its gate and its source and its threshold voltage V th satisfy the relationship V gs ⁇ V th ; the N-type transistor is turned on when the voltage difference V gs between its gate and its source and its threshold voltage V th satisfy the relationship V gs >V th , and is turned off when the voltage difference V gs between its gate and its source and its threshold voltage V th satisfy the relationship V gs ⁇ V th .
  • the OLED/QLED display panel may further include an encapsulation layer on the light-emitting side of the light-emitting element.
  • the encapsulation layer seals the light-emitting element, thereby reducing or preventing the degradation of the light-emitting element caused by moisture and/or oxygen included in the environment.
  • the encapsulation layer may be a single-layer structure or a composite layer structure, which includes a structure in which an inorganic layer and an organic layer are stacked.
  • the encapsulation layer may include a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer arranged in sequence.
  • the material of the encapsulation layer may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resins.
  • Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water, oxygen, and the like;
  • the material of the organic encapsulation layer may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as a polymer resin, etc., to flatten the surface of the display substrate, and can relieve the stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer, and may also include a desiccant and other water-absorbing materials to absorb water, oxygen, and other substances that invade the interior.
  • the OLED/QLED display panel may further include a touch structure located above the encapsulation layer, which may be a self-capacitive touch structure or a mutual capacitance touch structure.
  • the self-capacitive touch structure includes a plurality of self-capacitive electrodes arranged in an array (on the same layer), each of which is electrically connected to a touch processing circuit (touch driver chip) via a touch lead.
  • Position detection is achieved by detecting changes in the capacitance of the self-capacitive electrode due to, for example, the proximity of a finger during touch control.
  • the mutual capacitance touch structure includes a plurality of first touch signal lines extending in a first direction and a plurality of second touch signal lines extending in a second direction, and the first touch signal line and the second touch signal line are both electrically connected to the touch processing circuit (touch driver chip) via touch leads.
  • the first direction and the second direction intersect with each other and form an opening, thereby forming a touch capacitor at the intersection of the first touch signal line and the second touch signal line, and position detection is achieved by detecting changes in the touch capacitor due to, for example, the proximity of a finger during touch control.
  • the material forming the touch structure may be indium tin oxide, a metal grid, or the like.
  • the OLED/QLED display panel may further include a circular polarizer or a color film located above the layer where the touch structure is located, and the color film includes a grid-shaped black matrix and a color resistor arranged in the mesh.
  • a protective cover is also provided on the circular polarizer or the color film.
  • the protective cover may be an ultra-thin glass (UTG) cover. Since the ultra-thin glass cover not only maintains the characteristics of glass but also has good flexibility, it can fully meet the needs of folding products. Specifically, ultra-thin glass (UTG) refers to a glass layer with a thickness of tens of microns or less, which can be bent and deformed and can be folded.
  • ultra-thin glass can effectively avoid screen damage and provide better optical clarity; at the same time, ultra-thin glass is not prone to creases and has good reliability; and it will not be naturally decomposed like plastic, and has a long life, thereby providing more stable and reliable protection for the display screen.
  • the above-mentioned display device provided in the embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, etc.
  • the above-mentioned display device provided in the embodiment of the present disclosure includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip.
  • control chip is a central processing unit, a digital signal processor, a system chip (SoC), etc.
  • the control chip may also include a memory, and may also include a power module, etc., and realize power supply and signal input and output functions through additionally provided wires, signal lines, etc.
  • the control chip may also include hardware circuits and computer executable codes, etc.
  • the hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc.
  • VLSI very large scale integration
  • the above structure does not constitute a limitation on the above display device provided in the embodiment of the present disclosure.
  • the above display device provided in the embodiment of the present disclosure may include more or fewer of the above components, or a combination of certain components, or different component arrangements.

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Abstract

提供了一种覆晶薄膜（001）及显示装置，包括衬底基板（101），衬底基板（101）包括多个绑定区（ BA1， BA2， BA3）、以及在每个绑定区（ BA1， BA2， BA3）周围设置的周边区（ SA1， SA2， SA3， SA4， SA5）；多个焊盘（102），位于衬底基板（101）之上，每个绑定区（ BA1， BA2， BA3）设置多个焊盘（102）；陪镀图案（103），与多个焊盘（102）同层、同材料设置，陪镀图案（103）位于绑定区（BA1， BA2， BA3）至少一侧的周边区（ SA1， SA2， SA3， SA4， SA5）。

Description

覆晶薄膜及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种覆晶薄膜及显示装置。
背景技术
大尺寸电子产品如液晶显示器、液晶电视、等离子电视，中小尺寸电子产品如手机、数码相机等都是以轻薄短小为发展趋势的，这就要求必须有高密度、小体积，能自由安装的新一代封装技术来满足以上需求。覆晶薄膜(Chip On Film，COF)封装技术应运而生。COF是将驱动芯片(源极驱动芯片IC或门驱动芯片IC)接合并安装在形成了布线图形的柔性布线基板上构成的。COF的布线图形通常由与驱动芯片的电极连接的内引线、以及与外部电路连接的外引线构成。
发明内容
本公开实施例提供的覆晶薄膜及显示装置，具体方案如下：
一方面，本公开实施例提供了一种覆晶薄膜，包括：
衬底基板，所述衬底基板包括多个绑定区、以及在每个所述绑定区周围设置的周边区；
多个焊盘，位于所述衬底基板之上，每个所述绑定区设置有多个所述焊盘；
陪镀图案，与所述多个焊盘同层、同材料设置，所述陪镀图案位于所述绑定区至少一侧的所述周边区。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，在每个所述绑定区内，各所述焊盘沿所述焊盘的延伸方向排列成多排，所述周边区包括首排焊盘所在侧的第一周边区，以及末排焊盘所在侧的所述第二周边区，所述陪镀图案包括位于所述第一周边区和/或所述第二周边区的第一陪镀图案。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述第一陪镀图案与首排的各所述焊盘和/或末排的各所述焊盘一一对应，且所述第一陪镀图案与对应的所述焊盘一体设置。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述多个绑定区中的一个所述绑定区包括在所述焊盘的延伸方向上并排设置的第一子绑定区和第二子绑定区；
所述周边区还包括位于所述第一子绑定区与所述第二子绑定区之间的第三周边区，所述陪镀图案包括位于所述第三周边区的多个第二陪镀图案。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，还包括多个支撑图案，所述多个支撑图案位于所述第三周边区。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述第三周边区包括邻接所述第一子绑定区的第一边缘区、以及邻接所述第二子绑定区的第二边缘区；
所述覆晶薄膜还包括至少两组公共走线，每组所述公共走线包括第一公共走线和第二公共走线，其中，所述第一公共走线自所述第二子绑定区引出后在所述第一边缘区延伸，所述第二公共走线自所述第二子绑定区引出后在所述第二边缘区延伸；
在所述多个支撑图案和所述多个第二陪镀图案构成的图案集合中，各图案在各组所述公共走线之间的区域、以及每组所述公共走线中所述第一公共走线与所述第二公共走线之间的区域内均匀分布。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述多个支撑图案与部分所述第二陪镀图案一体设置。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，在一体设置的所述支撑图案与所述第二陪镀图案构成组合图案中，所述支撑图案关于所述组合图案在所述焊盘延伸方向的交叉方向上延伸的中心轴对称设置。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，相对于所述支撑图案隔开设置的所述第二陪镀图案为独立图案，各所述组合图案在各组 所述公共走线之间的区域、以及每组所述公共走线中所述第一公共走线与所述第二公共走线之间的区域内均匀分布。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，在所述焊盘延伸方向上，所述组合图案的长度、以及所述独立图案的长度分别是所述第一公共走线与所述第二公共走线之间距离的50％以上。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，相对于所述支撑图案隔开设置的所述第二陪镀图案为独立图案，各所述组合图案形成至少一排，各所述独立图案形成至少两排，至少一排所述组合图案与至少两排所述独立图案在所述焊盘延伸方向上排列，且所述组合图案所在排相对于所述独立图案所在排更远离所述第一边缘区和所述第二边缘区。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述组合图案的形状、宽度，以及所述独立图案的形状、宽度分别与所述焊盘的形状、宽度大致相同。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，相对于所述支撑图案隔开设置的所述第二陪镀图案为独立图案，各所述组合图案形成至少一排，所述独立图案为所述组合图案所在区与所述第一子绑定区之间、以及位于所述组合图案所在区与所述第二子绑定区之间的条状陪镀图案；
在所述焊盘延伸方向的交叉方向上，所述条状陪镀图案的长度大于等于一排所述焊盘的起止位置之间的距离。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述第一陪镀图案在所述焊盘延伸方向上的长度大于等于300μm且小于等于1000μm。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述周边区包括第四周边区和第五周边区，所述第四周边区和所述第五周边区在所述焊盘延伸方向上延伸，且在所述焊盘延伸方向的交叉方向上，所述第四周边区和所述第五周边区分居于所述绑定区的两侧；
所述覆晶薄膜还包括位于所述第四周边区和所述第五周边区的对位标识，所述对位标识与所述多个焊盘同层、同材料设置；
所述陪镀图案包括位于所述第四周边区和/或所述第五周边区的第三陪镀图案，所述第三陪镀图案在所述对位标识与所述焊盘延伸方向交叉设置的两侧、以及所述对位标识远离所述绑定区的一侧中的至少一边绕设于所述对位标识，且所述第三陪镀图案与所述对位标识之间具有预设距离。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述第三陪镀图案为块状图案。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述第三陪镀图案包括在所述焊盘的延伸方向上依次设置的多个条状图案。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，在所述对位标识与所述焊盘延伸方向的交叉方向上的两侧，所述第三陪镀图案在与所述焊盘延伸方向的交叉方向上的长度大于等于1mm且小于等于5mm。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，在所述焊盘延伸方向上，所述第三陪镀图案远离所述绑定区的端面到所述绑定区的距离与所述第一陪镀图案的长度大致相同。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，还包括位于所述多个焊盘所在层远离所述衬底基板一侧的第一保护图案，所述第一保护图案在所述衬底基板上的正投影与在所述焊盘延伸方向的交叉方向上并排设置的所述第一陪镀图案和所述第三陪镀图案在所述衬底基板上的正投影相互交叠，且在所述焊盘延伸方向上，所述第一保护图案在所述衬底基板上的正投影与所述绑定区之间具有预设距离。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述多个绑定区包括用于绑定显示基板的第一绑定区，以及用于绑定电路板的第二绑定区。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，在所述第一绑定区和所述第二绑定区内，相邻两排所述焊盘沿与所述焊盘延伸方向交叉的方向局部错开设置。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，还包括与所 述第一保护图案一体设置的第二保护图案，所述第二保护图案在所述衬底基板上的正投影与所述第三陪镀图案在所述衬底基板上的正投影相互交叠，且在所述焊盘延伸方向的交叉方向上，所述第二保护图案在所述衬底基板上的正投影与所述绑定区之间具有预设距离。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述多个绑定区包括用于绑定驱动芯片的第三绑定区。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述第三绑定区包括所述第一子绑定区和所述第二子绑定区，且在所述第一子绑定区和所述第二子绑定区，相邻两排所述焊盘沿与所述焊盘延伸方向的交叉方向局部错开设置；
在所述焊盘延伸方向的交叉方向上，所述第二子绑定区包括并排设置的第一信号输出区和第二信号输出区，以及位于所述第一信号输出区与所述第二信号输出区之间的信号输入区；
所述第一子绑定区包括第三信号输出区和第四信号输出区，所述第三信号输出区与所述第一信号输出区在所述焊盘延伸方向上并排设置，所述第四信号输出区与所述第二信号输出区在所述焊盘延伸方向上并排设置。
另一方面，本公开实施例提供了一种显示装置，包括显示基板、电路板、驱动芯片和覆晶薄膜，其中，所述覆晶薄膜为本公开实施例提供的上述覆晶薄膜，所述覆晶薄膜包括与所述显示基板、所述驱动芯片、所述电路板一一对应的绑定区。
附图说明
图1为本公开实施例提供的绑定区的边缘处焊盘偏厚的原理图；
图2为本公开实施例提供的用于绑定显示基板或柔性电路板的绑定区中偏厚焊盘所在区域的示意图；
图3为本公开实施例提供的用于绑定驱动芯片的绑定区中偏厚焊盘所在区域的示意图；
图4为本公开实施例提供的覆晶薄膜的一种结构示意图；
图5为本公开实施例提供的覆晶薄膜的又一种结构示意图；
图6为图5中M 1区域的一种放大结构示意图；
图7为图5中M 2区域的一种放大结构示意图；
图8为图5中M 3区域的一种放大结构示意图；
图9为图5中M 2区域的又一种放大结构示意图；
图10为图5中M 2区域的又一种放大结构示意图；
图11为图5中M 1区域的又一种放大结构示意图；
图12为图5中M 2区域的又一种放大结构示意图；
图13为图5中M 1区域的又一种放大结构示意图；
图14为图5中M 2区域的又一种放大结构示意图；
图15为图5中M 3区域的又一种放大结构示意图；
图16为图5中M 2区域的又一种放大结构示意图；
图17为图5中M 2区域的又一种放大结构示意图；
图18为图5中M 1区域的又一种放大结构示意图；
图19为图5中M 2区域的又一种放大结构示意图；
图20为本公开实施例提供的覆晶薄膜在制作过程中的一种结构示意图；
图21为本公开实施例提供的引线所在层的局部结构示意图；
图22为沿图21中I-I’方向的截面图；
图23为本公开实施例提供的引线所在层的结构示意图；
图24为图23中M 4区域的放大结构示意图；
图25为本公开实施例提供的覆晶薄膜在制作过程中的又一种结构示意图；
图26为本公开实施例提供的覆晶薄膜在制作过程中的又一种结构示意图；
图27为本公开实施例提供的覆晶薄膜在制作过程中的又一种结构示意图；
图28为本公开实施例提供的覆晶薄膜在制作过程中的又一种结构示意图；
图29为本公开实施例提供的覆晶薄膜在制作过程中的又一种结构示意图；
图30为本公开实施例提供的覆晶薄膜在制作过程中的又一种结构示意图；
图31为本公开实施例提供的显示装置的一种结构示意图；
图32为本公开实施例提供的显示基板或柔性电路板与覆晶薄膜绑定后的结构示意图；
图33为本公开实施例提供的驱动芯片与覆晶薄膜绑定后的一种结构示意图；
图34为本公开实施例提供的驱动芯片与覆晶薄膜绑定后的又一种结构示意图；
图35为本公开实施例提供的显示装置的又一种结构示意图；
图36为本公开实施例提供的显示装置的又一种结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。为了保持本公开实施例的以下说明清楚且简明，本公开省略了已知功能和已知部件的详细说明。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
随着三维(3D)显示技术的不断发展，3D显示产品的市场需求快速增加，其中分辨率持续提高(16K、32K等)来支撑3D显示的信息量是3D产品的 主要发展趋势；为支撑多视点(View)、X-Zone等技术，3D显示产品所需的数据通道(channel)数量大大提升，因此需要更高分辨率的COF封装工艺，以满足巨量的数据传输。目前市场上COF产品均为卷对卷(roll to roll)工艺，工艺精度低，且金属采用铜(Cu)制程，走线间距(Pitch)大，无法应对数据引脚(source pin)数量在5000以上的3D产品需求。
基于此，发明人在柔性基板(PI)上分层制作了引线和焊盘(Pad)，其中引线包括由层叠设置的钛金属层/铝金属层/钛金属层构成的叠层结构，焊盘包括单层铜结构。通过多排焊盘设计，实现了匹配数据引脚(source pin)数量在10000以上的COF制作方案。在该方案中，由于焊盘的铜层厚度要求在5μm以上，焊盘间距小于30μm，致使只能采用半加成法电镀工艺制作焊盘。但是焊盘的面积小，会导致局部铜占比不均，造成在电镀过程中，如图1所示，焊盘(P)四周电力线集中、电流密度增加，靠近边缘的焊盘(P)偏厚，出现焊盘厚度差异较大的问题，易导致绑定不良。具体而言：如图2所示，在用于绑定显示基板(panel)的绑定区(OLB Bonding)、以及用于绑定柔性电路板(FPC)的绑定区(FPC Bonding)，边缘区域A的焊盘P偏厚2μm以上，易导致绑定不良；另外，如图3所示，在用于绑定驱动芯片(IC)的绑定区(ILB Bonding)，其边缘区域B、以及中间区域C的焊盘偏厚，也易导致绑定不良。
为了解决相关技术中存在的上述技术问题，本公开实施例提供了一种覆晶薄膜，如图4至图8所示，包括：
衬底基板101，该衬底基板101包括多个绑定区(例如用于绑定显示基板的第一绑定区BA 1、用于绑定柔性电路板的第二绑定区BA 2、以及用于绑定驱动芯片的第三绑定区BA 3)、以及在每个绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)周围设置的周边区(例如第一周边区SA 1、第二周边区SA 2、第三周边区SA 3、第四周边区SA 4、第五周边区SA 5)；衬底基板101可以为聚酰亚胺等材质的柔性衬底；
多个焊盘102，位于衬底基板101之上，每个绑定区(例如第一绑定区 BA 1、第二绑定区BA 2、第三绑定区BA 3)分别设置有多个焊盘102；焊盘102的材料可以为铜等；
陪镀图案103，与多个焊盘102同层、同材料设置，陪镀图案103位于绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)至少一侧的周边区(例如第一周边区SA 1、第二周边区SA 2、第三周边区SA 3、第四周边区SA 4、第五周边区SA 5)。
在本公开实施例提供的上述覆晶薄膜中，在绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)电镀形成焊盘102的过程中，可在周边区(例如第一周边区SA 1、第二周边区SA 2、第三周边区SA 3、第四周边区SA 4、第五周边区SA 5)同步形成与焊盘102同层、同材料的陪镀图案103。由于陪镀图案103所在的周边区(例如第一周边区SA 1、第二周边区SA 2、第三周边区SA 3、第四周边区SA 4、第五周边区SA 5)位于焊盘102所在绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)外围，所以电镀过程中电力线较集中、电流密度较大的现象会发生在周边区(例如第一周边区SA 1、第二周边区SA 2、第三周边区SA 3、第四周边区SA 4、第五周边区SA 5)，从而可保证绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)的电力线及电流密度正常，进而可在绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)形成厚度均匀的焊盘102，利于提高绑定良率。可选地，本公开可使得绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)的焊盘102厚度均一性差异小于1μm。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图6至图8所示，在每个绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)内，各焊盘102沿其延伸方向Y排列成多排，周边区包括首排焊盘102所在侧的第一周边区SA 1，以及末排焊盘102所在侧的第二周边区SA 2，陪镀图案103包括位于第一周边区SA 1和/或第二周边区SA 2的第一陪镀图案31。由于首排焊盘102、末排焊盘102位于绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)的边缘区域，该边缘区域是在电镀过程中电力 线集中、电流密度大的区域，致使首排焊盘102、以及末排焊盘102远离绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)的一端的厚度容易偏厚。通过在首排焊盘102所在侧的第一周边区SA 1和/或末排焊盘102所在侧的第二周边区SA 2设置第一陪镀图案31，相当于将电力线集中、电流密度较大的区域转移至第一周边区SA 1和/或第二周边区SA 2，从而满足首排焊盘102、末排焊盘102所在边缘区域的电力线和电流密度正常，进而可形成厚度均一的首排焊盘102和末排焊盘102。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图6至图8所示，第一陪镀图案31可以与首排的各焊盘102和/或末排的各焊盘102一一对应，且第一陪镀图案31与对应的焊盘102一体设置。换言之，可通过将首排的各焊盘102和/或末排的各焊盘102朝向第一周边区SA 1和/或第二周边区SA 2延伸，并将焊盘102延伸至第一周边区SA 1和/或第二周边区SA 2的部分作为第一陪镀图案31。考虑到相关电镀过程中，电力线集中、电流密度大的区域宽度在200μm左右，因此，为了使得焊盘102完全避开电力线集中、电流密度大的区域，在本公开中可以使得第一陪镀图案31在焊盘102延伸方向Y上的长度大于等于300μm且小于等于1000μm，例如第一陪镀图案31在焊盘102延伸方向Y上的长度为300μm、400μm、500μm、600μm、700μm、800μm、900μm、1000μm等。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图7和图8所示，多个绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)中的一个绑定区(例如第三绑定区BA 3)包括在焊盘102的延伸方向Y上并排设置的第一子绑定区BA 31和第二子绑定区BA 32，第一子绑定区BA 31中距离第二子绑定区BA 32最远的一排焊盘102即为该绑定区(例如第三绑定区BA 3)内的首排焊盘102，第二子绑定区BA 32中距离第一子绑定区BA 31最远的一排焊盘102即为该绑定区(例如第三绑定区BA 3)内的末排焊盘102。周边区还可以包括位于第一子绑定区BA 31与第二子绑定区BA 32之间的第三周边区SA 3。由于在第一子绑定区BA 31与第二子绑定区BA 32内，邻近第三周边区SA 3的焊 盘102易出现厚度不均一的现象，因此，为了保证第三周边区SA 3两侧焊盘102的厚度均一性，如图7和图8所示，可以设置陪镀图案103包括位于第三周边区SA 3的多个第二陪镀图案32。可选地，全部第二陪镀图案32在衬底基板101上的正投影面积之和在第三周边区SA 3的面积占比在50％一下，可选的在40％左右，例如45％、40％、35％、30％等。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图7至图10所示，还可以包括多个支撑图案ST，这些支撑图案ST用于支撑驱动芯片IC、平衡绑定压力，可不加载任何电信号，可选地，多个支撑图案ST位于第三周边区SA 3，多个支撑图案ST在衬底基板101上的正投影面积之和与各支撑图案ST之间的间隙在衬底基板101上的正投影面积之和的比值小于等于1/9，相当于全部支撑图案ST在衬底基板101上的正投影面积之和在第三周边区SA 3的面积占比在10％以下，例如10％、9％、8％等。可选地，在各支撑图案ST之间的间隙处设置有第二陪镀图案32。在一些实施例中，本公开的全部第二陪镀图案32与全部支撑图案ST在第三周边区SA 3的面积占比在50％以下，例如30％～50％。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图7至图10所示，第三周边区SA 3包括邻接第一子绑定区BA 31的第一边缘区SA 31、以及邻接第二子绑定区BA 32的第二边缘区SA 32；覆晶薄膜还包括至少两组公共走线，每组公共走线包括第一公共走线CL 1和第二公共走线CL 2，其中，每组公共走线的各第一公共走线CL 1自第二子绑定区BA 32引出后在第一边缘区SA 31延伸，每组公共走线的各第二公共走线CL 2自第二子绑定区BA 32引出后在第二边缘区SA 32延伸；为了保证第三周边区SA 3两侧焊盘102的厚度均一性，在多个支撑图案ST和多个第二陪镀图案32构成的图案集合中，各图案在各组公共走线之间的区域、以及每组公共走线中第一公共走线CL 1与第二公共走线CL 2之间的区域内均匀分布。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图7至图10所示，为便于均匀排布支撑图案ST与第二陪镀图案32构成的图案集合，可 以使得多个支撑图案ST与部分第二陪镀图案32一体设置，可选地，在焊盘102延伸方向Y的交叉方向X上，支撑图案ST的宽度与第二陪镀图案32的宽度大致相同(即相同或在因制作工艺、测量等因素造成的误差范围内)。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图7至图10所示，在一体设置的支撑图案ST与第二陪镀图案32构成组合图案中，支撑图案ST关于组合图案在焊盘102延伸方向Y的交叉方向X上延伸的中心轴对称设置，即在焊盘102延伸方向Y上，在支撑图案ST的两侧可以均具有与该支撑图案ST一体设置的第二陪镀图案32，这样设置有利于支撑图案ST更均衡地支撑驱动芯片IC。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图7和图8所示，相对于支撑图案ST隔开设置的第二陪镀图案32为独立图案，各组合图案(由一体设置的支撑图案ST与第二陪镀图案32构成)在各组公共走线之间的区域、以及每组公共走线中第一公共走线CL 1与第二公共走线CL 2之间的区域内均匀分布，可选地，在任意相邻两个组合图案之间设置有独立图案。独立图案可在任意相邻两个组合图案之间大致等间距分布，在一些实施例中，独立图案在任意相邻两个组合图案之间区域的面积占比为30％～50％，例如30％、40％、50％等。
需要说明的是，本公开中的“均匀分布”可理解为“大致等间距分布”，即相邻图案的间距相同或在因制作、测量等因素造成的误差范围内。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，为了保证多个支撑图案ST与多个第二陪镀图案32在第三周边区SA 3内的面积占比，可以设置在焊盘102延伸方向Y上，组合图案(由一体设置的支撑图案ST与第二陪镀图案32构成)的长度、以及独立图案(相对于支撑图案ST隔开设置的第二陪镀图案32)的长度分别是第一公共走线CL 1与第二公共走线CL 1之间距离的50％以上，例如50％、60％、70％、80％、90％等。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图9所示，各组合图案(由一体设置的支撑图案ST与第二陪镀图案32构成)形成至少 一排，各独立图案(与支撑图案ST隔开设置的第二陪镀图案32)形成至少两排，至少一排组合图案与至少两排独立图案在焊盘102延伸方向Y上排列，且组合图案所在排相对于独立图案所在排更远离第一边缘区SA 31和第二边缘区SA 32，例如支撑图案ST与第二陪镀图案32构成的组合图案可以均匀设置在位于第三周边区SA 3的中间区域，以通过支撑图案ST均衡支撑驱动芯片IC。可选地，第一公共走线CL 1的局部、以及第二公共走线CL 2的局部也可用于支撑驱动芯片IC。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图9所示，为提高刻蚀均一性，可以设置组合图案(由一体设置的支撑图案ST与第二陪镀图案32构成)的形状、宽度(即在焊盘102的延伸方向Y的交叉方向X上的尺寸)，以及独立图案(与支撑图案ST隔开设置的第二陪镀图案32)的形状、宽度可与焊盘102的形状、宽度大致相同(即形状相同或相似，宽度相同或在因制作、测量等因素造成的误差范围内)。可选地，组合图案的高度(也可称为厚度)、长度(即在焊盘102的延伸方向Y上的尺寸)，以及独立图案的高度、长度也可以与焊盘102的高度、长度分别大致相同(即相同或在因制作、测量等因素造成的误差范围内)。可选的，在支撑图案ST远离设置衬底基板的一侧设置芯片凸点(IC Bump)。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图10所示，各组合图案(由一体设置的支撑图案ST与第二陪镀图案32构成)形成至少一排，各独立图案(与支撑图案ST隔开设置的第二陪镀图案32)为位于组合图案所在区与第一子绑定区BA 31之间、以及组合图案所在区与第二子绑定区BA 32之间的条状陪镀图案，可选地，在焊盘102延伸方向Y的交叉方向X上，条状陪镀图案322的长度大于等于一排焊盘102的起止位置之间的距离；在一些实施例中，在焊盘102延伸方向Y的交叉方向X上，条状陪镀图案的长度可以大于驱动芯片IC的长度。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图6、图7、图9和图10所示，周边区可以包括第四周边区SA 4和第五周边区SA 5，第四 周边区SA 4和第五周边区SA 5分别在焊盘102延伸方向Y上延伸，且在焊盘102的延伸方向Y的交叉方向X上，第四周边区SA 4和第五周边区SA 5分居于绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)的两侧；覆晶薄膜还可以包括位于第四周边区SA 4和第五周边区SA 5的对位标识104，对位标识104与多个焊盘102同层、同材料设置；陪镀图案103包括位于第四周边区SA 4和/或第五周边区SA 5的第三陪镀图案33，第三陪镀图案33在对位标识104与焊盘102延伸方向Y交叉设置的两侧、以及对位标识104远离绑定区的一侧中的至少一边绕设于对位标识104，且第三陪镀图案33与对位标识104之间具有预设距离l(例如0.3mm)。
相关技术中，由于在绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)邻接第四周边区SA 4和/或第五周边区SA 5的边缘区域内，电镀过程中电力线集中、电流密度大，致使该边缘区域内的焊盘102厚度均一性差。通过在第四周边区SA 4和/或第五周边区SA 5设置第三陪镀图案33，相当于将电力线集中、电流密度较大的区域转移至第四周边区SA 4和/或第五周边区SA 5，从而使得在绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)邻接第四周边区SA 4和/或第五周边区SA 5的边缘区域的电力线和电流密度正常，进而可形成厚度均一的焊盘102。另外，第三陪镀图案33与对位标识104之间设有预设距离(例如0.3mm)，可以保证第三陪镀图案33与对位标识104相对独立，便于后续在绑定过程中识别对位标识104，提高绑定良率。可选地，第三陪镀图案33不加载任何电信号。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图6、图7、图9和图10所示，第三陪镀图案33可以包括在焊盘102的延伸方向Y上依次设置的多个条状图案；或者，如图11和图12所示，第三陪镀图案33可以为块状图案。可选地，为使得绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)内的焊盘102完全避开电力线集中、电流密度大的区域，可在第四周边区SA 4、第五周边区SA 5距离绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)1mm～5mm的范围内设置第三陪镀图案33， 即在对位标识104与焊盘102延伸方向Y的交叉方向X上的两侧，第三陪镀图案33在该交叉方向X上的长度l 1大于等于1mm且小于等于5mm，例如为1mm、2mm、3mm、4mm、5mm等。相应地，在对位标识104远离绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)的一侧，第三陪镀图案33在该交叉方向X上的长度近似等于(l 1-l 2-l)，其中，l 2为对位标识104在交叉方向X上的长度，l为在交叉方向X上对位标识104与第三陪镀图案33之间的预设距离。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图6、图7图9至图12所示，在焊盘102的延伸方向Y上，第三陪镀图案33远离绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)的端面到绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)的距离与第一陪镀图案31的长度大致相同，即二者相同或在因制作、测量等因素造成的误差范围内。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图13至图19所示，还可以包括位于多个焊盘103所在层远离衬底基板101一侧的第一保护图案105，第一保护图案105在衬底基板101上的正投影与在焊盘102的延伸方向Y的交叉方向X上并排设置的第一陪镀图案31和第三陪镀图案33在衬底基板101上的正投影相互交叠，且在焊盘102的延伸方向Y上，第一保护图案105在衬底基板101上的正投影与绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)之间具有预设距离(例如具有100μm的预设距离)。第一保护图案105可提高被其覆盖的第一陪镀图案31和第三陪镀图案33所在位置的平坦度；并且考虑到第一保护图案105的制作精度，以及后续显示基板与覆晶薄膜通过各向异性导电胶(ACF)进行绑定的过程中需要溢胶空间，本公开中设置了第一保护图案105与绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)之间具有预设距离，使得第一保护图案105仅覆盖第一陪镀图案31远离绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)的部分区域、以及与该部分区域并排设置的 部分第三陪镀图案33。在一些实施例中，第一保护图案105可以与相关技术中的阻焊层同层、同材料设置，可选地，第一保护图案105的材料为绿油(SR)，厚度为5μm～20μm，例如5μm、10μm、15μm、20μm等。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图14、图16、图17和图19所示，还可以包括与第一保护图案105一体设置的第二保护图案106，第二保护图案106在衬底基板101上的正投影与第三陪镀图案33在衬底基板101上的正投影相互交叠，且在焊盘102延伸方向Y的交叉方向X上，第二保护图案106在衬底基板101上的正投影与绑定区(例如第三绑定区BA 3)之间具有预设距离(例如100μm～200μm)。第二保护图案106可提高被其覆盖的第三陪镀图案33所在位置的平坦度；并且考虑到第二保护图案106的制作精度，为防止第二保护图案106覆盖焊盘102，本公开中设置了第二保护图案105与绑定区(例如第三绑定区BA 3)之间具有预设距离，使得第二保护图案105仅覆盖第三陪镀图案33远离绑定区(例如第三绑定区BA 3)的部分区域。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，多个绑定区可以包括用于绑定显示基板的第一绑定区BA 1，以及用于绑定柔性电路板的第二绑定区BA 2。由于在显示基板、以及柔性电路板绑定过程中使用的绑定压头在焊盘102延伸方向Y的交叉方向X上的尺寸大于绑定区(例如第一绑定区BA 1、第二绑定区BA 2)的尺寸，使得压头会同时压附绑定区(例如第一绑定区BA 1、第二绑定区BA 2)、以及第四周边区SA 4和第五周边区SA 5，若在第四周边区SA 4和第五周边区SA 5设置覆盖第三陪镀图案33的第二保护图案106，则会造成在第四周边区SA 4和第五周边区SA 5的膜层高度大于绑定区(例如第一绑定区BA 1、第二绑定区BA 2)的膜层高度，致使绑定区(例如第一绑定区BA 1、第二绑定区BA 2)不能均匀受力。基于此，在第一绑定区BA 1、以及第二绑定区BA 2周围仅可以设置第一保护图案105。
在一些实施例中，多个绑定区还可以包括用于绑定驱动芯片IC的第三绑定区BA 3，由于驱动芯片IC的尺寸近似等于第三绑定区BA 3尺寸与第三周边 区SA 3的尺寸之和，因此，第三绑定区BA 3周围的周边区(例如第一周边区SA 1、第二周边区SA 2、第四周边区SA 4、第五周边区SA 5)的膜层高度对驱动芯片IC的绑定无影响，故可在第三绑定区BA 3周围同时设置第一保护图案105和第二保护图案106。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图13和图18所示，在第一绑定区BA 1和第二绑定区BA 2内，各排焊盘102在焊盘102的延伸方向Y上等间距设置，且相邻两排焊盘102沿与焊盘102延伸方向Y的交叉方向X上局部错开设置。相较于各排焊盘102平齐设置的方案，本公开通过在交叉方向X上将任意相邻两行焊盘102局部错开设置，利于保证有较大的空间设置与异行焊盘102电连接的引线107。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图14至图17、以及图19所示，第三绑定区BA 3包括第一子绑定区BA 31和第二子绑定区BA 32，且在第一子绑定区BA 31和第二子绑定区BA 32，各排焊盘102在焊盘102的延伸方向Y上等间距设置，且相邻两排焊盘102沿与焊盘102延伸方向Y的交叉方向X上局部错开设置；在焊盘102延伸方向Y的交叉方向X上，第二子绑定区BA 32包括并排设置的第一信号输出区O 1和第二信号输出区O 2，以及位于第一信号输出区O 1和第二信号输出区O 2之间的信号输入绑定区I；第一子绑定区BA 31包括第三信号输出区O 3和第四信号输出区O 4，第三信号输出区O 3与第一信号输出区O 1在焊盘102延伸方向Y上并排设置，第四信号输出区O 4与第二信号输出区O 2在焊盘102延伸方向Y上并排设置。可选地，第一信号输出区O 1的各排焊盘102与第三信号输出区O 3的各排焊盘102关于驱动芯片IC沿焊盘102延伸方向Y的交叉方向X的中心轴对称设置，第二信号输出区O 2的各排焊盘102与第四信号输出区O 4的各排焊盘102关于驱动芯片IC沿焊盘102延伸方向Y的交叉方向X的中心轴对称设置。可选地，在本公开中，第一信号输出区O 1、第二信号输出区O 2、第三信号输出区O 3、第四信号输出区O 4的各焊盘102分别通过在驱动芯片IC两侧布设的引线107连接至显示基板的数据引脚(Source pin)，以实现数据引脚数量的 最大化；信号输入绑定区I的焊盘102通过引线107连接至柔性电路板，以接收柔性电路板提供的驱动信号。
相应地，本公开实施例还提供了上述覆晶薄膜的制作方法，可以包括以下步骤：
第一步，如图20所示，所示玻璃基板G上涂覆或贴合衬底基板101，并在衬底基板101上沉积阻挡层108；其中，衬底基板101可以为聚酰亚胺等材质的柔性衬底，衬底基板101的厚度可以大于等于10μm且小于等于40μm，例如，衬底基板101的厚度为10μm、20μm、30μm、40μm等；阻挡层108的材料可以为氧化硅(SiO 2)、氮化硅(SiN)、氮氧化硅(SiON)等，阻挡层108可以为单层结构，也可以为叠层结构，阻挡层108的厚度大于等于100nm且小于等于500nm，例如阻挡层108的厚度为100nm、200nm、300nm、400nm、500nm等。
第二步，如图21至图24所示，在阻挡层108上沉积金属膜层，金属膜层的材料可以采用钼(Mo)、铝(Al)、钛(Ti)等适于干刻的材料，金属膜层可以为单层金属或叠层金属，示例性地，金属膜层为钛金属层/铝金属层/钛金属层构成的三叠层，可选地，钛金属层/铝金属层/钛金属层构成的金属膜层的厚度为大于等于500nm且小于等于1000nm，例如金属膜层的厚度为500nm、600nm、700nm、800nm、900nm、1000nm等；之后对金属膜层进行图案化形成引线107，为实现更小的引线间距(pitch)，采用干法刻蚀工艺刻蚀金属膜层以形成引线107，引线107包括走线部71、以及用于连接后续焊盘102的加宽部72；受绑定设备精度限制，加宽部72的间距需大于20μm，如果采用单层布线，则加宽部72之间布线最密区域的走线部71的间距小于4μm；为实现数据引脚(source pin)的数量最大化，在用于绑定驱动芯片IC的第三绑定区BA 3上下均布线连接数据线，第三绑定区BA 3下端中间区域的引线702为用于连接柔性电路板的输入信号线(input line)。
第三步，如图25所示，在引线107所在层之上形成绝缘层109，绝缘层109的材料可以为氧化硅(SiO 2)、氮化硅(SiN)、氮氧化硅(SiON)等，绝 缘层109可以为单层结构，也可以为叠层结构，绝缘层109的厚度大于等于100nm且小于等于500nm，例如绝缘层109的厚度为100nm、200nm、300nm、400nm、500nm等，且在加宽部72的位置处的绝缘层109设置转接孔V，可选地，每个加宽部72至少通过一个转接孔V与后续制作的一个焊盘102对应电连接。
第四步，如图26所示，在绝缘层109上电镀形成焊盘102，焊盘102的材质为铜，为保证在绑定过程中的溢胶空间充足，焊盘102的厚度需大于等于5μm且小于等于8μm，例如焊盘102的厚度为5μm、6μm、7μm、8μm等。需要说明的是，在形成焊盘102的同时还形成了陪镀图案103和对位标识104，关于陪镀图案103和对位标识104的描述内容参见上文，在此不做赘述。
第五步，如图27所示，在焊盘102上形成防氧化层110，防氧化层110的材质可以为锡(Sn)金属等，在一些实施例中，可采用化学镀工艺形成防氧化层110，防氧化层110的厚度大于等于0.5μm且小于等于2μm，例如0.5μm、1μm、1.5μm、2μm等；此外，也可以在焊盘102表面覆盖氧化铟锡(ITO)来防止焊盘102被氧化。
第六步，如图28所示，在防氧化层110之上的非绑定区刷上阻焊层111，阻焊层111的材料可以为绿油，阻焊层111的厚度可以大于等于5μm且小于等于20μm，可选地，阻焊层111的厚度为5μm、10μm、15μm、20μm等；需要说明的是，在形成阻焊层111的同时，还可以在绑定区(例如第一绑定区BA 1、第二绑定区BA 2、第三绑定区BA 3)附近形成部分覆盖陪镀图案103的第一保护图案105和第二保护图案106，并且关于陪镀图案103和对位标识104的描述内容可以参见上文，在此不做赘述。
第七步，如图29所示，对上述大尺寸的覆晶薄膜进行激光剥离(LLO)去除玻璃基板G，并切割获得多个目标尺寸的覆晶薄膜。
第八步，如图30所示，对上述目标尺寸的覆晶薄膜在用于绑定驱动芯片IC的第三绑定区BA 3键合驱动芯片IC，并用点胶封装，得到具有驱动芯片IC的覆晶薄膜。
需要说明的是，在本公开实施例提供的上述制作方法中，形成各层结构涉及到的构图工艺，不仅可以包括沉积、光刻胶涂覆、掩模板掩模、曝光、显影、刻蚀、光刻胶剥离等部分或全部的工艺过程，还可以包括其他工艺过程，具体以实际制作过程中形成所需构图的图形为准，在此不做限定。例如，在显影之后和刻蚀之前还可以包括后烘工艺。
其中，沉积工艺可以为化学气相沉积法、等离子体增强化学气相沉积法或物理气相沉积法，在此不做限定；掩膜工艺中所用的掩膜板可以为半色调掩膜板(Half Tone Mask)、单缝衍射掩模板(Single Slit Mask)或灰色调掩模板(Gray Tone Mask)，在此不做限定；刻蚀可以为干法刻蚀或者湿法刻蚀，在此不做限定。
基于同一发明构思，本公开实施例提供了一种显示装置，如图31所示，可以包括覆晶薄膜001、显示基板002、驱动芯片IC和电路板(例如柔性电路板FPC)，其中，覆晶薄膜001为本公开实施例提供的上述覆晶薄膜001，覆晶薄膜001包括与显示基板001、驱动芯片IC、电路板(例如柔性电路板FPC)一一对应的绑定区，可选地，显示基板002与覆晶薄膜001的第一绑定区BA 1电连接，柔性电路板FPC与覆晶薄膜001的第二绑定区BA 2电连接，驱动芯片IC与覆晶薄膜001的第三绑定区BA 3电连接。
在一些实施例中，如图32所示，显示基板002或柔性电路板FPC的引脚102’与覆晶薄膜001中对应绑定区的焊盘102一一对应电连接。可选地，如图33和图34所示，驱动芯片IC的凸块BP与第一子绑定区BA 31、以及第二子绑定区BA 32的焊盘102一一对应电连接，且在第一子绑定区BA 31与第二子绑定区BA 32之间的第三周边区SA 3内，均匀设置有与驱动芯片IC的凸块BP固定连接的支撑图案ST，可选地，支撑图案ST对应的凸块BP不提供电信号，仅起到平衡绑定压力的作用。并且，由图33和图34所示，还可以设置有第一公共走线CL 1和第二公共走线CL 2，该第一公共走线CL 1和第二公共走线CL 2可接入柔性电路板FPC提供的电源信号(Pwr)、接地信号(Gnd)等，可选地，驱动芯片IC中起平衡绑定压力作用的凸块BP也可以与公共走线CL 固定连接。
在一些实施例中，本公开实施例提供的显示装置具体可以为液晶显示装置，如图35所示，液晶显示装置包括背光模组BLU、以及位于背光模组BLU出光侧的液晶显示面板PNL。其中，液晶显示面板可以为扭转向列(Twisted Nematic,TN)型液晶显示面板、高级超维场开关(Adwanced Dimension Switch,ADS)型液晶显示面板、高开口率-高级超维场开关(High-Adwanced Dimension Switch,HADS)型液晶显示面板、平面内开关(In-Plane Switch,IPS)型液晶显示面板等。
在一些实施例中，液晶显示面板PNL包括相对而置的第一衬底201和第二基板202，位于第一基板201和对向基板第二基板202之间的第一液晶层203，在第一基板201和第二基板202之间具有包围第一液晶层203的第一密封胶204，在第一基板201面向第一液晶层203的一侧可设置有驱动电路205、像素电极(图中未示出)，在第二基板202面向第一液晶层203的一侧可设置有彩膜206，彩膜206包括黑矩阵61和色阻62，可选地，液晶显示面板PNL的公共电极(Com)可设置驱动电路205所在层远离第一基板201的一侧，或者设置于彩膜206远离第二基板202的一侧，液晶显示面板PNL还可以包括位于第一基板201远离第一液晶层203一侧的第一偏光片(pol，图中未示出)、以及位于第二基板202远离第一液晶层203一侧的第二偏光片(pol，图中未示出)等，其中，第一偏光片的透光轴与第二片偏光片的透光轴相互垂直。
在一些实施例中，背光模组BLU可以为直下式背光模组，也可以为侧入式背光模组。可选地，侧入式背光模组可以包括灯条、层叠设置的反射片、导光板、扩散片、棱镜组等，灯条位于导光板厚度方向的一侧。直下式背光模组可以包括矩阵光源、在矩阵光源出光侧层叠设置的反射片、扩散板和增亮膜等，反射片包括与矩阵光源中各灯珠的位置正对设置的开孔。灯条中的灯珠、矩阵光源中的灯珠可以为发光二极管(LED)，例如微型发光二极管(Mini LED、Micro LED等)。
亚毫米量级甚至微米量级的微型发光二极管和有机发光二极管(OLED)一样属于自发光器件。其与有机发光二极管一样，有着高亮度、超低延迟、超大可视角度等一系列优势。并且由于无机发光二极管发光是基于性质更加稳定、电阻更低的金属半导体实现发光，因此它相比基于有机物实现发光的有机发光二极管来说，有着功耗更低、更耐高温和低温、使用寿命更长的优势。且在微型发光二极管作为背光源时，能够实现更精密的动态背光效果，在有效提高屏幕亮度和对比度的同时，还能解决传统动态背光在屏幕亮暗区之间造成的眩光现象，优化视觉体验。
在一些实施例中，本公开实施例提供的显示装置可以为3D显示装置，此时，如图35所示，显示装置还可以包括位于背光模组BLU与液晶显示面板PNL之间的液晶光栅LCG，该液晶光栅LCG可通过粘结层004与液晶显示面板PNL固定在一起。可选地，根据观看者眼睛所在的当前位置，可控制液晶光栅LCG形成交替排列的透光区和遮光区，使观看者的左眼通过液晶光栅LCG的透光区看到显示面板PNL显示的左眼图像，右眼通过透光区看到显示面板PNL显示的右眼图像。通过将液晶光栅LCG设置于液晶显示面板PNL的入光侧，当液晶显示面板PNL包括触控电极时，液晶光栅LCG不会对液晶显示面板PNL中的触控电极产生屏蔽，避免出现触控失效的问题，从而可以提高液晶显示面板PNL的触控灵敏度及准确度。
在一些实施例中，如图35所示，液晶光栅LCG可以包括相对而置的第三基板301和第四基板302，位于第三基板301和第四基板302之间的第二液晶层303，位于第三基板301朝向第二液晶层303一侧的第一条状电极304，位于第一条状电极304所在层朝向第二液晶层303一侧的第二条状电极305，位于第四基板302朝向第二液晶层303一侧的面状电极306，与第一条状电极304电连接的第一晶体管T 1，第二条状电极305电连接的第二晶体管T 2，以及第三基板301和第四基板302之间包围第二液晶层303的第二封装层307。在具体实施时，通过对第一条状电极304、第二条状电极305、面状电极306加电，可控制第二液晶层303能够形成透光区和遮光区，以与输出左眼图像 和右眼图像的液晶显示面板PNL相配合，实现3D显示。
在一些实施例中，本公开实施例提供的显示装置可以为3D显示装置，如图36所示，该3D显示装置还可以包括位于液晶显示面板PNL出光侧的分光组件SE，可选地，分光组件SE包括彼此平行且并排设置的多个分光结构501，分光结构501可以为高折树脂层501a和低折树脂层501b形成的复合透镜，具体地，高折树脂层501a由多个柱透镜构成，低折树脂层501b填充各柱透镜的间隙且低折树脂层的厚度大于柱透镜的拱高。柱透镜可以是有棱、无棱结构。可选地，上述复合透镜可以透明材质的材料为基底502，示例性地，基底502的材料可以为聚对苯二甲酸乙二醇酯(PET)。在一些实施例中，可在液晶显示面板PNL与分光组件SE之间设置隔垫玻璃006，并将隔垫玻璃006与分光组件SE通过光学胶007进行贴合固定。
在具体实施时，通过设置液晶显示面板PNL的像平面位于柱透镜的焦平面上，每个柱透镜下面的像素被分成几个子像素，液晶显示面板PNL上不同位置的像素经过柱透镜的折射分光，光线路径发生变化从而在空间中形成不同的视点，当左眼接收到左视点图像的同时，右眼也接收右视点图像，实现3D显示。
在一些实施例中，本公开实施例提供的上述显示装置中的液晶显示面板还可以替换为电致发光显示面板(Organic Light Emitting Diodes，OLED)，或量子点显示面板(Quantum Dot Light Emitting Diodes，QLED)，在此不做限定。OLED显示面板或QLED显示面板包括发光器件、以及与发光器件电连接的像素驱动电路；其中，发光器件可以包括相对而置的阴极和阳极，以及在阴极和阳极之间的发光功能层；像素驱动电路可以包括薄膜晶体管、存储电容等，可以实现为各种不同类型，例如为2TIC型(即包括两个薄膜晶体管和一个存储电容)，还可以在2T1C型的基础上进一步包括更多的晶体管和/或电容以具有补偿、复位、发光控制、检测等功能，本公开的实施例对于像素驱动电路不作限制。例如，在一些实施例中，与发光元件直接电连接的薄膜晶体管可以为驱动晶体管(Td)或发光控制晶体管(EM)等。
在一些实施例中，发光功能层包括但不限于空穴注入层、空穴传输层、电子阻挡层、发光材料层、空穴阻挡层、电子传输层、电子注入层等。发光材料层可以为红光材料层、绿光材料层、蓝光材料层、黄光材料层、白光材料层等。对于OLED显示装置，发光材料层可以包括小分子有机材料或聚合物分子，可以为荧光发光材料、磷光发光材料等。对于QLED显示装置，发光材料层可以包括硅量子点、锗量子点、硫化镉量子点、硒化镉量子点、硒化锌量子点、碲化镉量子点、硫化铅量子点、硒化铅量子点、磷化铟量子点、砷化铟量子点等。
在一些实施例中，阳极的材料可以包括至少一种透明导电氧化物材料，包括氧化锢锡(ITO)、氧化锢锌(IZO)、氧化锌(ZnO)等；此外，阳极可以包括具有高反射率的金属作为反射层，诸如银(Ag)。阴极的材料可以包括锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料。
在一些实施例中，薄膜晶体管包括栅极、源极、漏极和有源层，其中，有源层的材料可以包括非晶硅、多晶硅或氧化物半导体(例如，氧化锢稼锌)。栅极、源极及漏极的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Ti/Al/Ti)。可选地，薄膜晶体管可以为底栅型晶体管、顶栅型晶体管、双栅型晶体管等。在一些实施例中，薄膜晶体管可以为P型晶体管或N型晶体管，其中，P型晶体管在其栅极与其源极之间的电压差V gs与其阈值电压V th满足关系式V gs<V th时导通，在其栅极与其源极之间的电压差V gs与其阈值电压V th满足关系式V gs≥V th时截止；N型晶体管在其栅极与其源极之间的电压差V gs与其阈值电压V th满足关系式V gs＞V th时导通，在其栅极与其源极之间的电压差V gs与其阈值电压V th满足关系式V gs≤V th时截止。
在一些实施例中，OLED/QLED显示面板还可以包括在发光元件出光侧的封装层。封装层将发光元件密封，从而可以减少或防止由环境中包括的湿气和/或氧引起的发光元件的劣化。封装层可以为单层结构，也可以为复合层结构，该复合层结构包括无机层和有机层堆叠的结构，例如，封装层可以包括 依次设置的第一无机封装层、第一有机封装层、第二无机封装层。该封装层的材料可以包括氮化硅、氧化硅、氮氧化硅、高分子树脂等绝缘材料。氮化硅、氧化硅、氮氧化硅等无机材料的致密性高，可以防止水、氧等的侵入；有机封装层的材料可以为含有干燥剂的高分子材料或可阻档水汽的高分子材料等，例如高分子树脂等以对显示基板的表面进行平坦化处理，并且可以缓解第一无机封装层和第二无机封装层的应力，还可以包括干燥剂等吸水性材料以吸收侵入内部的水、氧等物质。
在一些实施例中，OLED/QLED显示面板还可以包括位于封装层之上的触控结构，该触控结构可以为自电容型触控结构或互电容型触控结构。自电容型触控结构包括多个阵列排布(在同一层)的自电容电极，每个自电容电极通过触控引线与触控处理电路(触控驱动芯片)电连接。通过检测在触控时由于例如手指靠近而导致自电容电极的电容变化而实现位置检测。互电容型触控结构包括多条沿第一方向延伸的第一触控信号线和多条沿第二方向延伸的第二触控信号线，第一触控信号线和第二触控信号线均通过触控引线与触控处理电路(触控驱动芯片)电连接。第一方向和第二方向彼此交叉并且形成开口，由此在第一触控信号线和第二触控信号线交又位置处形成触控电容，通过检测在触控时由于例如手指靠近而导致该触控电容的变化而实现位置检测。形成触控结构的材料可以为氧化铟锡、金属网格等。
在一些实施例中，OLED/QLED显示面板还可以包括位于触控结构所在层之上的圆偏光片或彩膜，彩膜包括网格状的黑矩阵，以及设置在网孔内的色阻。可选地，在圆偏光片或彩膜之上还设置有保护盖板，在一些实施例中，保护盖板可以为超薄玻璃(UTG)盖板，由于超薄玻璃盖板既保持了玻璃的特性，同时兼具良好的柔韧性，因此，可以完全满足折叠产品的需求。具体地，超薄玻璃(UTG)是指厚度量级为几十微米及其以下的玻璃层，其可弯曲变形，可进行折叠。相对于聚合物塑料膜，超薄玻璃可以有效避免屏幕损伤，同时能提供更好的光学清晰度；同时，超薄玻璃不易出现折痕，可靠性好；而且不会像塑料一样被自然分解，寿命长，从而可以对显示屏提供更加 稳定可靠的保护。
在一些实施例中，本公开实施例提供的上述显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。可选地，本公开实施例提供的上述显示装置包括但不限于：射频单元、网络模块、音频输出&输入单元、传感器、显示单元、用户输入单元、接口单元以及控制芯片等部件。可选地，控制芯片为中央处理器、数字信号处理器、系统芯片(SoC)等。例如，控制芯片还可以包括存储器，还可以包括电源模块等，且通过另外设置的导线、信号线等实现供电以及信号输入输出功能。例如，控制芯片还可以包括硬件电路以及计算机可执行代码等。硬件电路可以包括常规的超大规模集成(VLSI)电路或者门阵列以及诸如逻辑芯片、晶体管之类的现有半导体或者其它分立的元件；硬件电路还可以包括现场可编程门阵列、可编程阵列逻辑、可编程逻辑设备等。另外，本领域技术人员可以理解的是，上述结构并不构成对本公开实施例提供的上述显示装置的限定，换言之，在本公开实施例提供的上述显示装置中可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (26)

  1. 一种覆晶薄膜，其中，包括：
    衬底基板，所述衬底基板包括多个绑定区、以及在每个所述绑定区周围设置的周边区；
    多个焊盘，位于所述衬底基板之上，每个所述绑定区设置有多个所述焊盘；
    陪镀图案，与所述多个焊盘同层、同材料设置，所述陪镀图案位于所述绑定区至少一侧的所述周边区。
  2. 如权利要求1所述的覆晶薄膜，其中，在每个所述绑定区内，各所述焊盘沿所述焊盘的延伸方向排列成多排，所述周边区包括首排焊盘所在侧的第一周边区，以及末排焊盘所在侧的所述第二周边区，所述陪镀图案包括位于所述第一周边区和/或所述第二周边区的第一陪镀图案。
  3. 如权利要求2所述的覆晶薄膜，其中，所述第一陪镀图案与首排的各所述焊盘和/或末排的各所述焊盘一一对应，且所述第一陪镀图案与对应的所述焊盘一体设置。
  4. 如权利要求2或3所述的覆晶薄膜，其中，所述多个绑定区中的一个所述绑定区包括在所述焊盘的延伸方向上并排设置的第一子绑定区和第二子绑定区；
    所述周边区还包括位于所述第一子绑定区与所述第二子绑定区之间的第三周边区，所述陪镀图案包括位于所述第三周边区的多个第二陪镀图案。
  5. 如权利要求4所述的覆晶薄膜，其中，还包括多个支撑图案，所述多个支撑图案位于所述第三周边区。
  6. 如权利要求5所述的覆晶薄膜，其中，所述第三周边区包括邻接所述第一子绑定区的第一边缘区、以及邻接所述第二子绑定区的第二边缘区；
    所述覆晶薄膜还包括至少两组公共走线，每组所述公共走线包括第一公共走线和第二公共走线，其中，所述第一公共走线自所述第二子绑定区引出 后在所述第一边缘区延伸，所述第二公共走线自所述第二子绑定区引出后在所述第二边缘区延伸；
    在所述多个支撑图案和所述多个第二陪镀图案构成的图案集合中，各图案在各组所述公共走线之间的区域、以及每组所述公共走线中所述第一公共走线与所述第二公共走线之间的区域内均匀分布。
  7. 如权利要求6所述的覆晶薄膜，其中，所述多个支撑图案与部分所述第二陪镀图案一体设置。
  8. 如权利要求7所述的覆晶薄膜，其中，在一体设置的所述支撑图案与所述第二陪镀图案构成的组合图案中，所述支撑图案关于所述组合图案在所述焊盘延伸方向的交叉方向上延伸的中心轴对称设置。
  9. 如权利要求7或8所述的覆晶薄膜，其中，相对于所述支撑图案隔开设置的所述第二陪镀图案为独立图案，各所述组合图案在各组所述公共走线之间的区域、以及每组所述公共走线中所述第一公共走线与所述第二公共走线之间的区域内均匀分布。
  10. 如权利要求9所述的覆晶薄膜，其中，在所述焊盘延伸方向上，所述组合图案的长度、以及所述独立图案的长度分别是所述第一公共走线与所述第二公共走线之间距离的50％以上。
  11. 如权利要求7或8所述的覆晶薄膜，其中，相对于所述支撑图案隔开设置的所述第二陪镀图案为独立图案，各所述组合图案形成至少一排，各所述独立图案形成至少两排，至少一排所述组合图案与至少两排所述独立图案在所述焊盘延伸方向上排列，且所述组合图案所在排相对于所述独立图案所在排更远离所述第一边缘区和所述第二边缘区。
  12. 如权利要求9或11所述的覆晶薄膜，其中，所述组合图案的形状、宽度，以及所述独立图案的形状、宽度分别与所述焊盘的形状、宽度大致相同。
  13. 如权利要求7或8所述的覆晶薄膜，其中，相对于所述支撑图案隔开设置的所述第二陪镀图案为独立图案，各所述组合图案形成至少一排，所 述独立图案为位于所述组合图案所在区与所述第一子绑定区之间、以及位于所述组合图案所在区与所述第二子绑定区之间的条状陪镀图案；
    在所述焊盘延伸方向的交叉方向上，所述条状陪镀图案的长度大于等于一排所述焊盘的起止位置之间的距离。
  14. 如权利要求2～13任一项所述的覆晶薄膜，其中，所述第一陪镀图案在所述焊盘延伸方向上的长度大于等于300μm且小于等于1000μm。
  15. 如权利要求1～14任一项所述的覆晶薄膜，其中，所述周边区包括第四周边区和第五周边区，所述第四周边区和所述第五周边区在所述焊盘延伸方向上延伸，且在所述焊盘延伸方向的交叉方向上，所述第四周边区和所述第五周边区分居于所述绑定区的两侧；
    所述覆晶薄膜还包括位于所述第四周边区和所述第五周边区的对位标识，所述对位标识与所述多个焊盘同层、同材料设置；
    所述陪镀图案包括位于所述第四周边区和/或所述第五周边区的第三陪镀图案，所述第三陪镀图案在所述对位标识与所述焊盘延伸方向交叉设置的两侧、以及所述对位标识远离所述绑定区的一侧中的至少一边绕设于所述对位标识，且所述第三陪镀图案与所述对位标识之间具有预设距离。
  16. 如权利要求15所述的覆晶薄膜，其中，所述第三陪镀图案为块状图案。
  17. 如权利要求15所述的覆晶薄膜，其中，所述第三陪镀图案包括在所述焊盘的延伸方向上依次设置的多个条状图案。
  18. 如权利要求15～17任一项所述的覆晶薄膜，其中，在所述对位标识与所述焊盘延伸方向的交叉方向上的两侧，所述第三陪镀图案在与所述焊盘延伸方向的交叉方向上的长度大于等于1mm且小于等于5mm。
  19. 如权利要求15～18任一项所述的覆晶薄膜，其中，在所述焊盘延伸方向上，所述第三陪镀图案远离所述绑定区的端面到所述绑定区的距离与所述第一陪镀图案的长度大致相同。
  20. 如权利要求15～19任一项所述的覆晶薄膜，其中，还包括位于所述 多个焊盘所在层远离所述衬底基板一侧的第一保护图案，所述第一保护图案在所述衬底基板上的正投影与在所述焊盘延伸方向的交叉方向上并排设置的所述第一陪镀图案和所述第三陪镀图案在所述衬底基板上的正投影相互交叠，且在所述焊盘延伸方向上，所述第一保护图案在所述衬底基板上的正投影与所述绑定区之间具有预设距离。
  21. 如权利要求20所述的覆晶薄膜，其中，所述多个绑定区包括用于绑定显示基板的第一绑定区，以及用于绑定电路板的第二绑定区。
  22. 如权利要求21所述的覆晶薄膜，其中，在所述第一绑定区和所述第二绑定区内，相邻两排所述焊盘沿与所述焊盘延伸方向交叉的方向局部错开设置。
  23. 如权利要求20所述的覆晶薄膜，其中，还包括与所述第一保护图案一体设置的第二保护图案，所述第二保护图案在所述衬底基板上的正投影与所述第三陪镀图案在所述衬底基板上的正投影相互交叠，且在所述焊盘延伸方向的交叉方向上，所述第二保护图案在所述衬底基板上的正投影与所述绑定区之间具有预设距离。
  24. 如权利要求23所述的覆晶薄膜，其中，所述多个绑定区包括用于绑定驱动芯片的第三绑定区。
  25. 如权利要求24所述的覆晶薄膜，其中，所述第三绑定区包括所述第一子绑定区和所述第二子绑定区，且在所述第一子绑定区和所述第二子绑定区，相邻两排所述焊盘沿与所述焊盘延伸方向的交叉方向局部错开设置；
    在所述焊盘延伸方向的交叉方向上，所述第二子绑定区包括并排设置的第一信号输出区和第二信号输出区，以及位于所述第一信号输出区与所述第二信号输出区之间的信号输入区；
    所述第一子绑定区包括第三信号输出区和第四信号输出区，所述第三信号输出区与所述第一信号输出区在所述焊盘延伸方向上并排设置，所述第四信号输出区与所述第二信号输出区在所述焊盘延伸方向上并排设置。
  26. 一种显示装置，其中，包括显示基板、电路板、驱动芯片和覆晶薄 膜，其中，所述覆晶薄膜为如权利要求1～25任一项所述的覆晶薄膜，所述覆晶薄膜包括与所述显示基板、所述驱动芯片、所述电路板一一对应的绑定区。
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