WO2023077281A1 - 发光基板和显示装置 - Google Patents

发光基板和显示装置 Download PDF

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Publication number
WO2023077281A1
WO2023077281A1 PCT/CN2021/128266 CN2021128266W WO2023077281A1 WO 2023077281 A1 WO2023077281 A1 WO 2023077281A1 CN 2021128266 W CN2021128266 W CN 2021128266W WO 2023077281 A1 WO2023077281 A1 WO 2023077281A1
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WIPO (PCT)
Prior art keywords
line
chip
power supply
reference power
light
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PCT/CN2021/128266
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English (en)
French (fr)
Inventor
雷杰
许邹明
田�健
刘纯建
吴信涛
王杰
张建英
金枝
Original Assignee
京东方科技集团股份有限公司
合肥京东方瑞晟科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方瑞晟科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/128266 priority Critical patent/WO2023077281A1/zh
Priority to EP21962801.3A priority patent/EP4345864A1/en
Priority to CN202180003216.1A priority patent/CN116391221A/zh
Priority to TW111141342A priority patent/TW202320047A/zh
Publication of WO2023077281A1 publication Critical patent/WO2023077281A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • the present disclosure relates to the field of display technology, in particular, to a light-emitting substrate and a display device.
  • the LED (Light Emitting Diode) light-emitting substrate can be driven in an active driving mode; wherein, an LED and a chip for driving the LED are arranged in the light-emitting area.
  • An external circuit (such as a circuit board) provides power and signals to the LED and the chip through the driving wiring provided on the light-emitting substrate. When the driving wiring is disturbed to generate noise, the luminous quality of the LED light-emitting substrate will be greatly affected.
  • the purpose of the present disclosure is to overcome the shortcomings of the above-mentioned prior art, provide a light-emitting substrate and a display device, and reduce at least part of the noise on the driving wiring.
  • a light-emitting substrate including a plurality of signal channels arranged in sequence along the row direction; each of the signal channels includes a plurality of control regions arranged in the column direction; each of the control regions including at least one light zone controlled by the same chip;
  • the light-emitting substrate is provided with a first driving wiring, a second driving wiring and a plurality of reference power supply lines; the first driving wiring and the second driving wiring are used for Provide different driving signals to the chip; the reference power supply line is used to provide a reference power supply voltage to the chip; wherein, the reference power supply lines in the same signal channel are electrically connected, and the first At least one reference power supply line is arranged between a driving line and the second driving line.
  • the first driving wiring is a clock signal line that provides a clock signal to the chip
  • the second driving wiring is a driving data line for providing a driving data signal to the chip or an address configuration line for providing an address configuration signal to the chip.
  • the second driving wiring is a driving data line.
  • the light-emitting substrate in the signal channel, further includes a lamp area power line for loading the lamp area power supply voltage to the lamp area, and a lamp area power supply line for loading the chip power supply to the chip. Voltage chip power lines, address configuration lines for loading address configuration signals to the chip;
  • the lamp area power line, the reference power line, the chip power line, the address configuration line, the clock signal line, the reference power line, the driving data line, the The reference power line and the lamp area power line are arranged in sequence.
  • the reference power supply line is also provided between the address configuration line and the clock signal line.
  • the light-emitting substrate has a chip pad group for bonding connection with the chip, and is provided with a reference power connection line;
  • the reference power supply connection line is connected to each of the reference power supply lines through via holes, and is electrically connected to the chip pad group.
  • the plurality of reference power lines include two main reference power lines located on both sides of the signal channel and two main reference power lines located between the main reference power lines.
  • Auxiliary reference power line the width of the main reference power line is greater than the width of the auxiliary reference power line;
  • the main reference power line overlaps with the lamp area, and does not overlap with at least part of the chips.
  • the plurality of reference power lines include a main reference power line and at least one auxiliary reference power line;
  • the line has the largest width and is not adjacent to the driving data line and the clock signal line.
  • the chip is located between the main reference power line and the auxiliary reference power line.
  • the light-emitting substrate in the signal channel, further includes a lamp area power line for loading the lamp area power supply voltage to the lamp area, and a lamp area power supply line for loading the chip power supply to the chip. Voltage chip power line;
  • the main reference power line is adjacent to the lamp area power line, and its width is larger than that of the chip power line;
  • the width of the auxiliary reference power line is smaller than that of the chip power line.
  • the light-emitting substrate further includes a lamp area power line for applying the lamp area power supply voltage to the lamp area, and a chip power line for applying the chip power supply voltage to the chip;
  • a first capacitor is disposed between at least part of the lamp zone power lines and the reference power line; and/or a second capacitor is disposed between at least part of the chip power lines and the reference power line.
  • one lamp area power line in one of the signal channels is connected to one of the other signal channels.
  • the lamp area power lines are arranged adjacent to each other; the two adjacently arranged lamp area power lines are connected to each other to form a combined light area power line; the combined light area power line is one of the two signal channels.
  • the lamp area provides the power supply voltage of the lamp area;
  • first capacitors are arranged between any one of the merged light zone power lines and the reference power line.
  • 2 to 4 second capacitors are arranged between any one of the chip power lines and the reference power line.
  • the light-emitting substrate is provided with a temperature sensor, and a temperature sensor power line for applying a temperature sensor power supply voltage to the temperature sensor;
  • a third capacitor is arranged between any one of the temperature sensor power lines and the reference power line.
  • the light-emitting substrate includes a base substrate, a driving metal layer, a first insulating layer, a wiring metal layer, a second insulating layer, and a device layer that are sequentially stacked;
  • the driving metal layer is provided with the first driving wiring, the second driving wiring and the reference power supply line;
  • the lamp area includes a plurality of light emitting elements electrically connected; the light emitting element and the chip are arranged on the device layer;
  • the wiring metal layer is provided with a light-emitting element pad group for binding the light-emitting element, a chip pad group for bonding the chip, and a pad group for connecting the light-emitting element pad and the chip pad. Connecting traces for group electrical connections.
  • the wiring metal layer is provided with a reference power supply resistance drop structure corresponding to at least part of the reference power supply line; the reference power supply resistance drop structure and the corresponding reference power supply line pass through hole connection.
  • the orthographic projection of the reference power supply resistance reducing structure on the base substrate is located within the range of the corresponding reference power supply line's orthographic projection on the base substrate.
  • At least part of the via holes between the reference power supply resistance reducing structure and the corresponding reference power supply line are distributed around the edge of the reference power supply resistance reducing structure.
  • the multiple reference power lines have one or two main reference power lines with the largest width; line connection.
  • the driving metal layer is provided with a lamp area power line for loading the lamp area power supply voltage to the lamp area; the wiring metal layer is provided with a lamp area power line corresponding to the lamp area power line.
  • the resistance-reducing structure of the power supply of the lamp area; the power line of the lamp area is connected to the corresponding resistance-reducing structure of the power supply of the lamp area through a via hole.
  • At least part of the via holes between the resistance reducing structure for the lamp area power supply and the corresponding power line for the lamp area are distributed around the edge of the resistance reducing structure for the lamp area power supply.
  • the orthographic projection of the resistance-reducing structure of the lamp area power supply on the base substrate coincides with the orthographic projection of the corresponding lamp area power line on the base substrate.
  • the driving metal layer is provided with a chip power supply line for loading the chip power supply voltage to the chip;
  • the wiring metal layer is provided with a chip power drop resistance corresponding to the chip power supply line Structure; the resistance-reducing structure of the chip power supply is connected to the corresponding chip power supply line through a via hole.
  • At least some via holes between the chip power supply resistance reducing structure and the corresponding chip power supply lines are arranged in a straight line along the column direction.
  • a display device comprising the above-mentioned light-emitting substrate.
  • FIG. 1 is a schematic diagram of pins of a chip in an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of the principle of the connection between the chip pad group and the driving wires in an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of the principle of the connection between the chip pad group and the driving wires in an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a partial structure of a driving metal layer in the first implementation manner of the present disclosure.
  • FIG. 5 is a schematic diagram of a partial structure of a wiring metal layer in the first implementation manner of the present disclosure.
  • FIG. 6 is a schematic diagram of a partial structure of a driving metal layer and a wiring metal layer in the first implementation manner of the present disclosure.
  • FIG. 7 is a schematic diagram of a partial structure of a driving metal layer, a wiring metal layer, and a via hole disposed on a first insulating layer in the first implementation manner of the present disclosure.
  • FIG. 8 is a partially enlarged view of FIG. 7 around the chip area.
  • FIG. 9 is a schematic diagram of a partial structure of a driving metal layer in a second implementation manner of the present disclosure.
  • FIG. 10 is a partial enlarged view of FIG. 9 around the chip area.
  • FIG. 11 is a schematic diagram of a partial structure of a wiring metal layer in a second implementation manner of the present disclosure.
  • FIG. 12 is a partial enlarged view of FIG. 11 around the chip area.
  • FIG. 13 is a schematic diagram of the partial structure around the chip area of the driving metal layer, the wiring metal layer and the via holes provided on the first insulating layer in the second implementation manner of the present disclosure.
  • FIG. 14 is a schematic diagram of the partial structure around the chip area of the driving metal layer, the wiring metal layer and the via holes provided on the first insulating layer in the third implementation manner of the present disclosure.
  • FIG. 15 is a schematic diagram of a local structure around the chip area of the driving metal layer, the wiring metal layer and the via holes disposed on the first insulating layer in the fourth implementation manner of the present disclosure.
  • FIG. 16 is a schematic diagram of a via hole and a resistance-reducing structure on the first insulating layer in an embodiment of the present disclosure.
  • FIG. 17 is a schematic diagram of a via hole and a resistance-reducing structure on the first insulating layer in an embodiment of the present disclosure.
  • FIG. 18 is a schematic diagram of a via hole and a resistance-reducing structure on the first insulating layer in an embodiment of the present disclosure.
  • FIG. 19 is a schematic diagram of a via hole and a resistance-reducing structure on the first insulating layer in an embodiment of the present disclosure.
  • FIG. 20 is a schematic diagram of a via hole and a resistance-reducing structure on the first insulating layer in an embodiment of the present disclosure.
  • Fig. 21 is a schematic diagram of the film layer structure of the light-emitting substrate in an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • the width of a trace refers to the dimension of the trace in the row direction.
  • the relative positional relationship between two structures refers to the positional relationship between the orthographic projections of the two structures on the substrate.
  • positional relationship of two structures relative to the substrate refers to the positional relationship of the two structures in the direction perpendicular to the substrate, that is, the layer relationship between the film layers where the two structures are located.
  • the two structures are in different film layers, and the orthographic projections of the two structures on the substrate are at least partially overlapped.
  • complete overlap between two structures it is meant that the orthographic projection of one of the structures on the substrate is completely within the orthographic projection of the other structure on the substrate.
  • non-overlap between two structures it is meant that the orthographic projection of one of the structures on the substrate substrate is outside the orthographic projection of the other structure on the substrate substrate.
  • the present disclosure provides a light emitting substrate and a display device having the light emitting substrate.
  • the light-emitting substrate includes a base substrate BP, a driving metal layer Cu1 , a first insulating layer OC1 , a wiring metal layer Cu2 , a second insulating layer OC2 and a device layer, which are sequentially stacked.
  • the driving metal layer Cu1 is formed with driving wires, which are used for electrical connection with external circuits (such as circuit boards), and provide signals and power to electronic components located on the device layer.
  • the wiring metal layer Cu2 is connected to the driving metal layer Cu1 through a via hole, and it is provided with a pad for binding electronic components and a connecting wire connected to the pad, and at least part of the connecting wire is electrically connected to the driving wire to provide information to each electronic component.
  • Components are loaded with signals and power (in this disclosure, a driving trace for loading a power supply voltage may be defined as a power trace).
  • the first insulating layer OC1 is used to isolate the driving metal layer Cu1 and the wiring metal layer Cu2 , and is provided with a via hole for electrically connecting the driving metal layer Cu1 and the wiring metal layer Cu2 .
  • the second insulating layer OC2 is used to protect the wiring metal layer Cu2, and is provided with a via hole exposing the pad, so that the electronic component can be bonded and connected to the pad through the via hole.
  • the driving metal layer Cu1 and/or the wiring metal layer Cu2 may also be provided with a bonding pad for bonding connection with an external circuit.
  • the bonding pads may be disposed on the edge of the light emitting substrate.
  • the light-emitting substrate is provided with a fan-out area at one end close to the bonding pad. In the fan-out area, there are fan-out lines electrically connected to each driving line. The fan-out lines can be bent to connect to the corresponding bonding pads. pad.
  • the fan-out lines can be arranged on the driving metal layer Cu1 or on the wiring metal layer Cu2; some fan-out lines can also be arranged across the driving metal layer Cu1 and the wiring metal layer Cu2. In one embodiment of the present disclosure, the fan-out area may span 2 to 4 lamp region rows, for example, span three lamp region rows.
  • the extending direction of the driving wires in the non-fan-out region can be defined as the column direction H2, and the direction perpendicular to the column direction H2 and parallel to the plane of the light-emitting substrate is defined as the row direction H1.
  • the fan-out region and the bonding pad are located at one end of the light-emitting substrate in the column direction H2. Further, at the end of the light-emitting substrate away from the fan-out area, at least part of the driving wires (ie, power wires) loaded with the same power supply may be electrically connected to each other.
  • the same power supply lines can be electrically connected through the conductive structure located in the driving metal layer Cu1, or electrically connected through the conductive structure located in the wiring metal layer Cu2, or can be connected at the same time.
  • the conductive structure of the driving metal layer Cu1 and the wiring metal layer Cu2 is used for electrical connection, which is not specifically limited in the present disclosure.
  • the power supply wiring may include a reference power line GNDA for loading the reference power supply voltage GND, and a lamp area power line VLEDA for loading the lamp area power supply voltage VLED.
  • the reference power lines GNDA are electrically connected through the conductive traces located on the driving metal layer Cu1 and/or the wiring metal layer Cu2, and the power lines VLEDA of each lamp area are electrically connected through the conductive traces located on the driving metal layer Cu1 and the wiring metal layer Cu2. /or the conductive traces of the wiring metal layer Cu2 are electrically connected.
  • both ends of the light-emitting substrate in the column direction H2 may be provided with bonding pads and fan-out regions adjacent to the bonding pads.
  • the external circuit for driving the light-emitting substrate can be electrically connected to the bonding pad at any end to drive the light-emitting substrate.
  • each film layer of the light-emitting substrate of the present disclosure is exemplarily introduced and described as follows.
  • the base substrate BP may be a base substrate BP of inorganic material, or may be a base substrate BP of organic material.
  • the material of the base substrate BP can be glass materials such as soda-lime glass, quartz glass, sapphire glass, that is, the base substrate BP can be a glass substrate .
  • the material of the base substrate BP can be polymethyl methacrylate (Polymethyl methacrylate, PMMA), polyvinyl alcohol (Polyvinyl alcohol, PVA), polyvinyl phenol (Polyvinyl phenol, PVP), polyethersulfone (Polyether sulfone, PES), polyimide, polyamide, polyacetal, polycarbonate (Polycarbonate, PC), polyethylene terephthalate (Polyethylene terephthalate, PET), Polyethylene naphthalate (PEN) or a combination thereof, that is, the base substrate BP may be an organic flexible substrate.
  • the base substrate BP may also be made of other materials and structures, such as a multi-layer composite base substrate BP, subject to being able to effectively support the light-emitting substrate.
  • the thickness of the driving metal layer Cu1 may be greater than the thickness of the wiring metal layer Cu2, so as to reduce the impedance of each driving wire, reduce the power consumption of the light-emitting substrate and reduce the difficulty of debugging the light-emitting substrate, and improve the uniformity of light emission of the light-emitting substrate. sex.
  • copper electroplating, electroless copper plating, lamination of multiple thin metal layers, or other feasible methods can be used to make the driving metal layer Cu1 have a thickness required to meet the electrical properties of the light-emitting substrate.
  • any thin metal layer can be prepared by magnetron sputtering.
  • the Cu2 layer of the wiring metal layer can be prepared by magnetron sputtering.
  • the thickness of the driving metal layer Cu1 may be between 1-20 microns, for example, between 2-5 microns. In one embodiment of the present disclosure, the thickness of the wiring metal layer Cu2 is between 0.3-0.8 microns, for example, between 0.3-0.5 microns. Of course, in other embodiments of the present disclosure, the thicknesses of the driving metal layer Cu1 and the wiring metal layer Cu2 may be similar, as long as the electrical performance requirements of the light-emitting substrate for the driving wiring can be met.
  • the driving metal layer Cu1 may include one or more stacked metal layers.
  • the driving metal layer Cu1 includes at least one copper metal layer, so as to improve the conductivity of the driving metal layer Cu1 and reduce the square resistance of the driving metal layer Cu1 .
  • the driving metal layer Cu1 may also include other metal layers, for example, an alloy layer (such as molybdenum-niobium alloy layer).
  • the driving metal layer Cu1 can be formed on the base substrate BP through a photolithography process, including sputtering (Sputter), cleaning (Cleaning), coating (Coating), baking, exposure (Photo), development, hard baking, etching (Etch), stripping and other steps.
  • a photolithography process including sputtering (Sputter), cleaning (Cleaning), coating (Coating), baking, exposure ( Photo), development, hard baking, etching (Etch), stripping and other steps.
  • a first passivation layer may also be provided on the upper surface of the driving metal layer Cu1 (the surface away from the base substrate BP).
  • the first passivation layer is used to protect the driving metal layer Cu1 and prevent the driving metal layer Cu1 from Oxidized during the process.
  • the material of the first passivation layer may be silicon nitride, silicon oxide, silicon oxynitride and other inorganic insulating materials, especially silicon nitride.
  • the first insulating layer OC1 is disposed on a side of the driving metal layer Cu1 away from the base substrate BP.
  • the material of the first insulating layer OC1 can be an organic material such as photosensitive resin; the first insulating layer OC1 can be formed through processes of coating, exposure, and development, so that the first insulating layer OC1 covers the driving metal layer Cu1 and A via hole exposing part of the driving metal layer Cu1 is formed.
  • the first insulating layer OC1 is formed on the side of the first passivation layer away from the base substrate BP.
  • a via hole exposing the driving metal layer Cu1 may be opened on the first passivation layer by using the first insulating layer OC1 as a mask.
  • the wiring metal layer Cu2 may include one or more stacked metal layers.
  • the wiring metal layer Cu2 includes at least one copper metal layer, so as to improve the electrical conductivity of the wiring metal layer Cu2 and reduce the square resistance of the wiring metal layer Cu2.
  • the wiring metal layer Cu2 may also include other metal layers, for example, an alloy layer (such as a molybdenum-niobium alloy) located on the copper metal layer (the side away from the base substrate BP) or below (the side close to the base substrate BP). layer).
  • an alloy layer such as a molybdenum-niobium alloy
  • the wiring metal layer Cu2 can be formed on the base substrate BP through a photolithography process, including sputtering (Sputter), cleaning (Cleaning), coating (Coating), baking, exposure (Photo), development, hard baking, etching (Etch), stripping and other steps.
  • a photolithography process including sputtering (Sputter), cleaning (Cleaning), coating (Coating), baking, exposure ( Photo), development, hard baking, etching (Etch), stripping and other steps.
  • a second passivation layer may also be provided on the upper surface of the wiring metal layer Cu2 (the surface away from the base substrate BP), and the second passivation layer is used to protect the wiring metal layer Cu2 and prevent the wiring metal layer Cu2 from It is oxidized during the preparation of the luminescent substrate.
  • the material of the second passivation layer may be inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, especially silicon nitride.
  • the second insulating layer OC2 is disposed on a side of the wiring metal layer Cu2 away from the base substrate BP.
  • the material of the second insulating layer OC2 may be an organic material such as a photosensitive resin.
  • the second insulating layer OC2 may be formed through processes of coating, exposure, and development, so that the second insulating layer OC2 covers the wiring metal layer Cu2 and forms a via hole exposing part of the wiring metal layer Cu2.
  • the second insulating layer OC2 is formed on the side of the second passivation layer away from the base substrate BP.
  • a via hole exposing the pad can be opened on the second passivation layer by using the second insulating layer OC2 as a mask.
  • the materials, film structure and formation method of the driving metal layer Cu1 and the wiring metal layer Cu2 can also be other feasible ways, so as to be able to form a light-emitting substrate that meets the electrical requirements.
  • the driving metal layer Cu1 and the wiring metal layer Cu2 shall prevail.
  • the materials and forming methods of the first insulating layer OC1 and the second insulating layer OC2 may also be in other feasible ways.
  • the device layer may include various electronic components bonded to the wiring metal layer Cu2, and these electronic components may include light emitting elements and chip ICs for driving the light emitting elements.
  • the bonding pads on the wiring metal layer Cu2 include a light-emitting element pad group LEDPAD for bonding with a light-emitting element and a chip pad group ICPAD for bonding with a chip IC.
  • the electronic component may further include a temperature sensor, and the wiring metal layer Cu2 may also include a temperature sensor pad group for bonding with the temperature sensor.
  • the electronic component may further include a capacitor, and the wiring metal layer Cu2 may also be provided with a capacitor pad group for bonding connection with the capacitor.
  • the light-emitting element can be an active light-emitting electronic component such as LED (light-emitting diode), Mini LED (submillimeter light-emitting diode, Mini Light Emitting Diode), Micro LED (micro light-emitting diode, Micro Light Emitting Diode), etc.
  • LED light-emitting diode
  • Mini LED submillimeter light-emitting diode
  • Mini Light Emitting Diode Mini Light Emitting Diode
  • Micro LED micro light-emitting diode, Micro Light Emitting Diode
  • the light emitting element is a Mini LED.
  • the cross-sectional size of the Mini LED (parameters such as length, width or diagonal or diameter) is between about 100 ⁇ m and about 300 ⁇ m.
  • the light emitting element is a Micro LED.
  • the cross-sectional size of the Mini LED (parameters such as length, width or diagonal or diameter) is below 100 ⁇ m.
  • the device layer may also include more types of electronic components, and the wiring metal layer Cu2 may be provided with corresponding pads according to the types and positions of the electronic components.
  • the light-emitting substrate of the present disclosure may include a plurality of signal channels CH arranged in sequence along the row direction H1 (FIG. 2 shows a partial schematic diagram of a signal channel CH); each signal channel CH Including a plurality of control areas BB arranged in the column direction H2; each control area BB includes at least one lamp area controlled by the same chip IC (the chip pad group ICPAD for binding the chip IC is shown in Figure 2) AA.
  • each control area BB includes a plurality of lamp areas AA controlled by the same chip IC, for example, four lamp areas AA.
  • each lamp area AA includes one or more electrically connected light emitting elements.
  • each lamp area AA includes a plurality of electrically connected light emitting elements, for example, four light emitting elements connected in series in sequence. It can be understood that, in a lamp area AA, the number of light-emitting elements can be other than four, such as two, six, nine, etc., and the light-emitting elements in the lamp area AA can be connected in parallel or in series , the present disclosure makes no special limitation on this, as long as each light emitting element in the lamp area AA can work synchronously.
  • Fig. 1 shows a schematic diagram of a chip IC driving four lamp areas AA simultaneously in an embodiment of the present disclosure.
  • the chip IC includes four output pins (namely the first output pin OUT1D, the second output pin OUT2D, the third output pin OUT3D, the fourth output pin OUT4D), the clock signal pin CLKD, the reference There are ten pins including power supply pin GNDD, driving data pin DataD, chip power supply pin VCCD, address relay pin DOSD, and address configuration pin DISD.
  • the first output pin OUT1D, the second output pin OUT2D, the third output pin OUT3D, and the fourth output pin OUT4D are respectively electrically connected to the second end of a lamp area AA, and the first end of the lamp area AA is used for To load the power supply voltage VLED of the lamp area.
  • the reference power pin GNDD is used to load the reference power voltage GND to the chip IC
  • the clock signal pin CLKD is used to load the clock signal CLK to the chip IC
  • the driving data pin DataD is used to load the driving data signal Data to the chip IC
  • the pin VCCD is used to load the chip power supply voltage VCC to the chip IC
  • the address configuration pin DISD is used to load the address configuration signal DIS to the chip IC
  • the chip IC outputs the address relay signal DOS through the address relay pin DOSD.
  • FIG. 1 shows an arrangement of pins of a chip IC in an embodiment of the present disclosure.
  • each pin of the chip IC is arranged in two columns, and each column includes 5 pins. Wherein, each column has two output pins.
  • the first row of pins includes a clock signal pin CLKD, a first output pin OUT1D, an address configuration pin DISD, a third output pin OUT3D, and a chip power pin VCCD arranged in sequence.
  • the second column of pins includes a driving data pin DataD, a second output pin OUT2D, an address relay pin DOSD, a fourth output pin OUT4D, and a reference power pin GNDD arranged in sequence.
  • each pin of the chip IC can also be arranged in other ways, such as adjusting the arrangement order of each pin in each column of pins or making each pin in two columns Redistribute in the middle, or make each pin arrange into three columns or four columns, etc., so that the chip IC includes the above ten pins shall prevail.
  • each chip IC is set in one-to-one correspondence with each control area BB, and each control area BB includes four lamp areas AA, and the four lamp areas AA are driven by the corresponding chip IC of the control area BB.
  • the chip IC can be located in the corresponding control area BB, or can be located outside the corresponding control area BB, as long as the four lamp areas AA in the control area BB can be driven.
  • the chip IC of the present disclosure When the chip IC of the present disclosure is working, it can work in address configuration mode, drive configuration mode and device drive mode.
  • the external circuit In the address configuration mode, the external circuit can load the address configuration signal DIS to the address configuration pad DISP of the chip IC, and the chip IC can configure its own address according to the received address configuration signal DIS, and automatically generate the address relay signal DOS and DOSP output via address relay pad.
  • the address relay signal DOS output by the chip IC can be used as the next-level address configuration signal DIS to enable the next-level chip IC to perform address configuration. In this way, each chip IC in a signal channel CH can sequentially complete address configuration and determine its own address information.
  • the address relay signal DOS output by the last-level chip IC can be fed back to the external circuit.
  • the external circuit sends the driving data signal Data and the clock signal CLK to each chip IC in the same signal channel CH. Specifically, the external circuit loads the clock signal CLK to the clock signal pad CLKP of the chip IC, and loads the driving data signal Data to the driving data pad DataP of the chip IC.
  • the clock signal CLK is used to control the sampling of the driving data signal Data by the chip IC, for example, the driving data pad DataP is sampled at a rising edge or a falling edge of the clock signal CLK.
  • the driving data signal Data includes driving data information of each chip IC, and each driving data information corresponds to an address information (for example, the driving data information has an address information label).
  • Each chip IC can further receive the driving data information required by itself according to its own address information.
  • the chip IC can control the opening or closing of each output pin according to the received driving data information, and then realize the control of each lamp area.
  • FIG. 2 and FIG. 3 show schematic diagrams of a light-emitting substrate in a signal channel CH in some embodiments of the present disclosure.
  • a chip pad group ICPAD for bonding connection with a chip IC is shown.
  • the order of the driving wires is only a schematic illustration, and does not mean that the driving wires of the light-emitting substrate of the present disclosure are arranged in the order shown in FIG. 2 and FIG. 3 .
  • driving wires are provided in the driving metal layer Cu1, and these driving wires include a reference power line GNDA for loading a reference power supply voltage GND, a lamp area power line VLEDA for loading a lamp area power supply voltage VLED, and a power line for The chip power supply line VCCA for loading the chip power supply voltage VCC, the address configuration line DSA for loading the address configuration signal DIS, the driving data line DataA for loading the driving data signal Data, and the clock signal line CLKA for loading the clock signal CLK, etc.
  • the chip pad group ICPAD for bond connection with the chip IC is disposed on the wiring metal layer Cu2.
  • the chip pad group ICPAD includes the reference power pad GNDP for bonding connection with the reference power pin GNDD, the chip power pad VCCP for bonding connection with the chip power pin VCCD, and the chip power pad VCCP for bonding with the drive data pin DataD
  • the relay pin DOSD is bonded to the address relay pad DOSP, and each of the four output pads is bonded to the four output pins.
  • the four output pads include a first output pad OUT1P for bonding connection with the first output pin OUT1D, a second output pad OUT2P for bonding connection with the second output pin OUT2D, and a second output pad OUT2P for bonding connection with the second output pin OUT2D.
  • the arrangement of the pads of the chip pad group ICPAD can match the arrangement of the pins of the chip IC, so that each pin of the chip IC can be bound to each pad in one-to-one correspondence.
  • ten pads are arranged in two columns.
  • the first row of pads includes clock signal pads CLKP, first output pads OUT1P, address configuration pads DISP, third output pads OUT3P, chip power pads VCCP, and the second row of pads includes sequentially arranged
  • the data pad DataP, the second output pad OUT2P, the address relay pad DOSP, the fourth output pad OUT4P, and the reference power pad GNDP are driven.
  • the chip power pad VCCP and the driving data pad DataP are respectively arranged in two columns of pads of the chip pad group ICPAD, so that the chip power pad A column of pads of the VCCP is a first column of pads, and a column of pads provided with a driving data pad DataP is a second column of pads.
  • each row of pads may extend along the column direction H2.
  • the chip power supply pad VCCP is located on one side of the driving data pad DataP.
  • one specific direction of the row direction H1 can be defined as a preset direction H11, so that the driving data pad DataP is located on the side of the preset direction H11 of the chip power pad VCCP.
  • the wiring metal layer Cu2 is also provided with a light-emitting element pad group LEDPAD for binding light-emitting elements.
  • the light emitting element pad group LEDPAD may include a first light emitting element pad LEDPAD1 for connecting to the anode of the light emitting element and a second light emitting element pad LEDPAD2 for connecting to the cathode of the light emitting element.
  • Connection wires may also be provided in the wiring metal layer Cu2, and the connection wires may be connected to the light emitting element pad group LEDPAD and the chip pad group ICPAD.
  • connection wiring may include a lamp area connecting line LEDL electrically connected to the light emitting element pad group LEDPAD, and the light emitting element pad group LEDPAD in the same lamp area AA is electrically connected through the lamp area connecting line LEDL, so that the same lamp area AA The light-emitting elements in the electrical connection.
  • the second pad LEDPAD2 of a light-emitting element in the lamp area AA can be used as the second end of the lamp area AA, and connect the output pads (the first output pad OUT1P, the second output pad OUT2P, Any one of the third output pad OUT3P and the fourth output pad OUT4P) is connected, and the first pad LEDPAD1 of a light-emitting element in the lamp area AA can be used as the first end of the lamp area AA through the lamp area connection line LEDL and The power cord of the lamp area is connected to VLEDA.
  • the connection wiring also includes a reference power connection line GNDL, a chip power connection line VCCL, a drive data connection line DataL, an address configuration connection line DISL, an address relay connection line DOSL, a clock signal connection line CLKL, and the like.
  • the reference power pad GNDP is electrically connected to the reference power line GNDA through the reference power connection line GNDL
  • the chip power pad VCCP is electrically connected to the chip power line VCCA through the chip power connection line VCCL
  • the driving data pad DataP is connected through the driving data connection line.
  • DataL is electrically connected to the drive data line DataA
  • the address configuration pad DISP is connected to the address configuration line DSA through the address configuration connection line DISL
  • the address relay pad DOSP is connected to the address configuration line DSA through the address relay connection line DOSL
  • the clock signal is connected to the address configuration line DSA.
  • the disk CLKP is connected to the clock signal line CLKA through the clock signal connection line CLKL.
  • a chip pad group ICPAD is electrically connected to two address configuration lines DSA, wherein the address configuration line DSA electrically connected to the address configuration pad DISP can be defined as the front address configuration line DSA of the chip pad group ICPAD,
  • the address configuration line DSA electrically connected to the address relay pad DOSP can be defined as the post-address configuration line DSA of the chip pad group ICPAD. It can be understood that, in two cascaded chip ICs, the rear address configuration line DSA of the chip pad group ICPAD corresponding to the upper-level chip IC, and the rear address configuration line DSA of the chip pad group ICPAD corresponding to the lower-level chip IC
  • the configuration line DSA is the same address configuration line DSA.
  • each signal channel CH of the light-emitting substrate there are multiple channels for loading different driving signals (non-power supply signals) to the chip.
  • the driving wires are, for example, provided with a first driving wire and a second driving wire for loading different driving signals.
  • Multiple reference power lines GNDA are also provided in each signal channel CH. Wherein, the reference power lines GNDA in the same signal channel CH are electrically connected to each other, and at least one reference power line GNDA is arranged between the first driving line and the second driving line. In this way, the first driving trace and the second driving trace can be shielded through the reference power supply line GNDA to avoid mutual interference between different driving signals loaded on different driving traces, thereby reducing at least part of the driving trace. Noise on the line.
  • the first driving wiring is a clock signal line CLKA; the second driving wiring is driving a data line DataA or an address configuration line DSA.
  • the first driving wiring is a clock signal line CLKA; the second driving wiring is a driving data line DataA.
  • the light-emitting substrate of the present disclosure can reduce or eliminate the impact of the driving data signal Data loaded on the driving data line DataA on the clock signal line by setting the reference power line GNDA as a shielding line between the driving data line DataA and the clock signal line CLKA.
  • the interference of the clock signal CLK loaded on CLKA overcomes the defect that the clock signal CLK is easy to be interfered as a high-frequency signal, thereby making the working state of the chip IC more stable.
  • each signal channel CH the reference power lines GNDA are electrically connected to each other, so that the currents between the reference power lines GNDA can flow through each other, and the current fluctuation on a single reference power line GNDA can be stabilized.
  • the reference power supply voltage GND is made more stable, and the noise of the reference power supply voltage GND is reduced.
  • this can reduce the overall impedance of the reference power supply line GNDA in the signal channel CH, and further improve the signal stability of the reference power supply voltage GND in the signal channel CH.
  • each reference power line GNDA is electrically connected to the reference power pad GNDP through a reference power connection line GNDL.
  • At least part of the chip pad group ICPAD corresponding to the chip IC is disposed in the control area BB corresponding to the chip IC.
  • a reference power connection line GNDL is provided in the control area BB, and the reference power connection line GNDL is electrically connected to the reference power pad GNDP and each reference power line GNDA. In this way, the reference power supply voltage GND in the signal channel CH can be gridded, further improving the stability of the light-emitting substrate.
  • the sizes of the multiple reference power lines GNDA are not completely the same.
  • the reference power line GNDA with a larger width can be recorded as the main reference power line GNDA, and the reference power line GNDA with a smaller width, which is mainly used to shield the driving lines such as the clock signal line CLKA and the driving data line DataA, can be recorded as the auxiliary power line.
  • the width of the main reference power line GNDA is greater than the width of the chip power line VCCA, and the width of the chip power line VCCA is greater than the width of each auxiliary reference power line GNDA.
  • the main reference power line GNDA may be arranged adjacent to the lamp area power line VLEDA.
  • the main reference power line GNDA is set adjacent to one of the light area power lines VLEDA;
  • the zone power line VLEDA may or may not be adjacent to the auxiliary reference power line GNDA.
  • the main reference power line GNDA may overlap with the light area AA, and not overlap with at least part of the chip IC.
  • the driving wiring in a signal channel CH, along the preset direction H11, includes the lamp area power line VLEDA, the reference power line GNDA, the chip power line VCCA, the address Configuration line DSA, clock signal line CLKA, reference power line GNDA, driving data line DataA, reference power line GNDA, and lamp area power line VLEDA.
  • each driving wire extends along the column direction H2 as a whole.
  • the two reference power lines GNDA on both sides of the signal channel CH are the main reference power line GNDA, and the main reference power line GNDA is mainly used to load the reference power voltage GND to the chip IC.
  • the reference power line GNDA between the two main reference power lines GNDA is the auxiliary reference power line GNDA, and the auxiliary reference power line GNDA is set adjacent to the clock signal line CLKA to shield the signals on other driving traces from the clock signal line CLKA. crosstalk.
  • the width of the main reference power line GNDA is greater than the width of the auxiliary reference power line GNDA.
  • the chip pad group ICPAD is disposed between two main reference power lines GNDA such that the chip pad group ICPAD is close to the center of the signal channel in the row direction.
  • an auxiliary reference power line GNDA can also be additionally set, so that the clock signal line CLKA is sandwiched between two auxiliary Between the reference power lines GNDA, it is less susceptible to crosstalk from other signals.
  • the light-emitting substrate has a chip area ICA for arranging a chip pad group ICPAD, and the chip pad group ICPAD is arranged in the chip area ICA.
  • the address configuration pad DISP is arranged closer to the chip power line VCCA.
  • the chip pad group ICPAD is located between the chip power line VCCA and the address configuration line DSA.
  • the driving metal layer Cu1 is provided with an address configuration switching structure DSC on the side of the chip pad group ICPAD close to the chip power line VCCA, and the address configuration switching structure DSC is electrically connected to the front address configuration line DSA of the chip pad group ICPAD.
  • the address relay pad DOSP of the chip pad group ICPAD can be electrically connected to the rear address configuration line DSA of the chip pad group ICPAD through the address relay connection line DOSL, and the address configuration pad of the chip pad group ICPAD
  • the DISP can be electrically connected to the DAC through the address configuration connection line DISL, and then electrically connected to the front address configuration line DSA of the chip pad group ICPAD.
  • the chip power line VCCA is provided with a chip power line avoidance gap VCCAG.
  • the DSC part of the address configuration transfer structure is set in the avoidance gap VCCAG of the chip power line. In this way, the chip power line VCCA can avoid the address configuration switching structure DSC through the chip power line avoidance gap VCCAG, thereby saving space and increasing the width of the driving trace.
  • the part of the chip power line VCCA provided with the chip power line avoidance gap VCCAG is the avoidance section of the chip power line VCCA, and the chip power line VCCA is not provided with the part of the chip power line avoidance gap VCCAG. It is the wiring segment of the chip power line VCCA. Due to the setting of the chip power line avoidance gap VCCAG, the width of the avoidance section of the chip power line VCCA is smaller than the width of the wiring section of the chip power line VCCA. Further, the avoidance section and the wiring section of the chip power line VCCA are the same edge as the edge far away from the chip pad group ICPAD. In other words, the chip power line VCCA can avoid the address configuration transition structure DSC by setting the chip power line avoidance gap VCCAG, without bending the address configuration transition structure DSC, thereby avoiding the bending of each driving line. Influence.
  • part of the reference power line GNDA is provided with a reference power line avoidance gap GNDAG to avoid the light-emitting element pad group LEDPAD, for example, the main reference power line GNDA is provided with a reference power line Avoid the notch GNDAG.
  • the main reference power line GNDA is provided with a reference power line Avoid the notch GNDAG.
  • part of the connection lines LEDL of the lamp area are arranged in the avoidance gap GNDAG of the reference power line, which can reduce the risk of short circuit between the reference power line GNDA and the connection line LEDL of the light area, and improve the quality of the light-emitting substrate. Rate.
  • part of the lamp area connection line LEDL needs to overlap the reference power line GNDA, so that the lamp area connection line LEDL passes through the wiring area of the reference power line GNDA to pass through the lamp area power line VLEDA hole electrical connection.
  • both sides of the main reference power line GNDA are retracted to form a wiring space as a part of the reference power line avoidance gap GNDAG, and the wiring space extends along the column direction H2; at least partly along the column direction
  • the lamp area connection line LEDL extended by H2 is arranged in this wiring space.
  • the main reference power line GNDA may include a control section in the control area BB and a connection section between the control areas BB.
  • the reference power line avoidance gap GNDAG is set at the control section of the main reference power line GNDA, which is not only provided with a concave portion, but also smaller in width than the connecting section of the main reference power line GNDA.
  • the recessed part and the constricted part provided by the control section of the main reference power line GNDA compared with the connection section of the main reference power line GNDA can be used as a reference power line avoidance gap GNDAG.
  • the lamp area connection line LEDL is arranged between the connection sections of the main reference power line GNDA.
  • the main reference power line GNDA may not be provided with reference power line avoidance gaps, and part of the light emitting element pad group LEDPAD and part of the lamp area connection line LEDL may overlap with the reference power line GNDA. In this way, the impact on the impedance caused by setting the reference power line GNDA to avoid the gap GNDAG is avoided.
  • the wiring metal layer Cu2 is provided with a reference power connection line GNDL, and the reference power connection line GNDL is connected to each reference power line GNDA through via holes HH.
  • the reference power connection line GNDL can be set on the side of the chip pad group ICPAD close to the reference power pad GNDP, and the two ends of the row direction H1 are respectively electrically connected to the main reference power line GNDA, and the middle part is connected to the auxiliary reference power line through the via hole H.
  • the power line GNDA is electrically connected, and is electrically connected to the reference power pad GNDP.
  • the reference power connection line GNDL not only electrically connects the main reference power line GNDA and the auxiliary reference power line GNDA, improves the stability of the signal on the reference power line GNDA, but also effectively provides the reference power voltage GND to the chip IC.
  • the relative position between the chip pad group ICPAD and the driving wiring can also be in other ways.
  • the driving wiring includes lamp area power lines VLEDA (not shown in FIG. 14 ) arranged in sequence along the preset direction H11. , main reference power line GNDA, chip power line VCCA, address configuration line DSA, auxiliary reference power line GNDA, clock signal line CLKA, auxiliary reference power line GNDA, driving data line DataA, address configuration line DSA, main reference power line GNDA and Lamp area power line VLEDA (not shown in Figure 14).
  • the first row of pins of the chip pad group ICPAD is set between the middle address configuration line DSA and the clock signal line CLKA, for example overlapping with the auxiliary reference power line GNDA between the two driving lines;
  • the second column of pins of the group ICPAD overlaps the clock signal line CLKA.
  • the two address configuration lines DSA on both sides can be bridge-connected through the address configuration switching structure DSC (not shown in FIG. 14 ) on the wiring metal layer Cu2, so that the two address configuration lines The address configuration lines DSA are electrically connected as a whole.
  • the chip power line VCCA may not have a chip power line avoidance gap VCCAG to avoid the chip pad group ICPAD or other driving lines, thereby ensuring a small voltage drop on the chip power line VCCA.
  • the width of the chip power supply line VCCA is smaller than the width of the main reference power supply line GNDA and greater than the width of the auxiliary reference power supply line GNDA.
  • the address configuration line DSA, the driving data line DataA, the clock signal line CLKA and other driving lines have the same width and are smaller than the width of the auxiliary reference power line GNDA.
  • the reference power connection line GNDL may be electrically connected to each main reference power line GNDA, each auxiliary reference power line GNDA and the reference power pad GNDP.
  • the driving wiring includes lamp area power lines VLEDA (not shown in FIG. 15 ), main reference power line GNDA, chip power line VCCA, address configuration line DSA, clock signal line CLKA, auxiliary reference power line GNDA, driving data line DataA, address configuration transfer structure DSC, main reference power line GNDA, lamp area power supply Line VLEDA (not shown in Figure 15).
  • the width of the auxiliary reference power line GNDA is not smaller than the width of the chip pad group ICPAD. In this way, the chip pad group ICPAD can be disposed on the auxiliary reference power line GNDA or in the avoidance space formed by disconnecting the auxiliary reference power line GNDA.
  • the auxiliary reference power line GNDA is disconnected at the chip pad group ICPAD to form an avoidance space as the chip area ICA where the chip pad group ICPAD is arranged, and the chip pad group ICPAD is arranged in the chip area Inside the ICA.
  • the auxiliary reference power line GNDA is divided into multiple sections by the avoidance space. Further, one end of the auxiliary reference power line GNDA close to the chip pad group ICPAD is electrically connected to the reference power connection line GNDL.
  • the reference power connection line GNDL includes a first reference power connection line GNDL1 and a second reference power connection line GNDL2; the first reference power connection line GNDL1 and the second reference power connection line GNDL2 are respectively connected to two The ends of the auxiliary reference power line GNDA are connected, and both are connected to the two main reference power lines GNDA.
  • the chip power line VCCA is provided with a chip power line avoidance gap VCCAG;
  • the main reference power line GNDA has a reference power line extension GNDE extending toward the chip pad group ICPAD side, and part of the reference power line extension GNDE can Set in the chip power line avoidance gap VCCAG.
  • the reference power connection line GNDL can be connected to the reference power line extension GNDE through the via hole HH, and the lamp area connection line LEDL can be avoided.
  • part or all of the chip power line avoidance gap VCCAG can be disconnected so that the chip power line VCCA can be divided into multiple sections; two adjacent sections of the chip power line VCCA can be connected by a chip power switch arranged on the wiring metal layer Cu2.
  • the ground structure is electrically connected to VCCBC.
  • the chip power connection line VCCL is connected to the chip power transfer structure VCCBC.
  • the chip power transfer structure VCCBC includes two parallel wires to avoid defective grounding structures.
  • the front address configuration line DSA corresponding to the chip pad group ICPAD is electrically connected to the address configuration pad DISP through the address configuration connection line DISL.
  • the rear address configuration line DSA corresponding to the chip pad group ICPAD is electrically connected to the address configuration transfer structure DSC through a transfer wire located at the wiring metal layer Cu2, and the address configuration transfer structure DSC is connected to the address relay through the address relay connection line DOSL.
  • Disc DOSP electrical connection is electrical connection.
  • the address configuration lines DSA, CKLA, the driving data line DataA, and the address configuration switching structure DSC have the same width and are smaller than the auxiliary reference power line GNDA.
  • the width of the chip power line VCCA is greater than that of the auxiliary reference power line GNDA and smaller than that of the main reference power line GNDA (not all of the main reference power line GNDA is shown in FIG. 15 ).
  • the wiring metal layer Cu2 is also provided with a plurality of resistance-reducing structures (for example, the lamp area power supply resistance-reduction structure VLEDB in FIG. 6 and FIG. 7 , the reference power supply resistance-reduction structure GNDB, the chip power supply resistance-reduction structure VCCB, etc.) , any one of the resistance-reducing structures is set correspondingly to one of the driving traces.
  • the resistance reducing structure is connected to the corresponding driving wiring through the via hole HH. It can be understood that any driving trace may correspond to one or more resistance-reducing structures; multiple resistance-reducing structures may correspond to the same driving trace.
  • the driving trace connected to the resistance-reducing structure through the via hole is equivalent to being connected in parallel with a conductive path, so that the impedance of the driving trace is reduced.
  • this can reduce the impedance of the driving lines, and ensure that the signal and power supply have a smaller voltage drop on the light-emitting substrate; on the other hand, the thickness or width of the driving lines can be reduced.
  • the driving metal layer Cu1 with a small thickness can be formed by magnetron sputtering; since the resistance-reducing structure of the wiring metal layer Cu2 can reduce the impedance of the driving wiring, the driving metal layer The reduction in the thickness of Cu1 will not have an obvious negative impact on the reduction of the electrical performance of the light-emitting substrate, and can simplify the preparation process of the driving metal layer Cu1 and reduce the cost and thickness of the light-emitting substrate.
  • the orthographic projection of the resistance-dropping structure on the base substrate BP is located within the orthographic projection of the corresponding driving wiring.
  • connection between the resistance reducing structure and the corresponding driving wiring may be through a via hole, especially through a plurality of via holes HH.
  • FIGS. 16 to 20 taking the reference power supply resistance drop structure GNDB corresponding to the main reference power supply line GNDA as an example, the arrangement of the via hole HH between the resistance drop structure and the corresponding driving trace is exemplified. It can be understood that the examples of the distribution of the via holes HH in FIGS. 16 to 20 are only examples of some implementations of the present disclosure.
  • the vias HH on the resistance-dropping structure may be arranged in a ring around the edge of the resistance-dropping structure.
  • the width of the resistance reducing structures is too small to be circular, they can also be arranged along the column direction H2.
  • This arrangement of the via holes HH can make the connection between the resistance-reducing structure and the corresponding driving trace distributed and multi-point, thereby improving the diversity and flexibility of the current between the resistance-reducing structure and the driving trace.
  • the via hole HH between the resistance reducing structure and the corresponding driving wiring is also arranged in other feasible manners.
  • the vias HH can be arranged in multiple via-hole rows, for example, arranged as two holes located at both ends of the column direction H2 of the resistance-reducing structure.
  • Each via row includes a plurality of vias H extending along the row direction H1.
  • FIG. 18 using the reference power supply resistance reduction structure GNDB to illustrate the resistance reduction structure
  • each via hole in the via hole row can be merged into a via hole HH, so that the via hole HH is along the row.
  • FIG. 19 using the reference power supply resistance reducing structure GNDB to illustrate the resistance reducing structure, various via holes around the edge of the resistance reducing structure can be merged in sequence to form an entire annular via hole HH.
  • FIG. 19 using the reference power supply resistance reducing structure GNDB to illustrate the resistance reducing structure
  • the part of the first insulating layer OC1 surrounded by the ring via hole is also removed, so that the via hole HH forms an entire cavity structure, the edge of the cavity structure is set along the edge of the resistance-reducing structure; in this way, the large area of the resistance-reducing structure located on the wiring metal layer Cu2 is directly overlapped with the driving wiring located on the driving metal layer Cu1, for example, the overlapping area reaches a reduction More than 30% of the resistance structure area.
  • the size of the via hole HH may be between 100-300 microns.
  • the size of the via hole between the resistance-dropping structure and the corresponding driving trace is 200 microns.
  • the distance between the via holes HH may be between 800-1200 microns.
  • the spacing between the via holes may be 1000 micrometers between the resistance-dropping structure and the corresponding driving wiring.
  • the distance between the via hole HH and the edge of the resistance-reducing structure is not less than 10 microns.
  • the shape of the via hole HH may be a square or a circle.
  • the shape of the via hole HH may also be other feasible shapes, such as rectangle, hexagon and so on.
  • the resistance-reducing structure includes a reference power-resistance-reducing structure GNDB corresponding to the main reference power line GNDA;
  • the projection is in the corresponding main reference power line GNDA.
  • the reference power supply resistance reducing structure GNDB is connected to the corresponding reference power supply line GNDA through a via hole.
  • at least part of the vias between the reference power line GNDA and the reference power drop structure GNDB can be arranged around the edge of the reference power drop structure GNDB, so as to effectively reduce the impedance of the reference power line GNDA.
  • the vias located between the reference power supply line GNDA and the reference power supply drop-resistance structure GNDB may be arranged in two via hole rows, and each via hole row includes array of vias.
  • the two via hole rows may be respectively arranged at both ends of the reference power supply resistance reducing structure GNDB in the column direction H2.
  • each via hole in a row of via holes may be connected in sequence to form an elongated hole extending along the row direction H1 as a whole.
  • the reference power line GNDA may include a control section in the control area BB and a connection section between the control areas BB.
  • the reference power drop resistance structure GNDB may include a reference power drop resistance structure GNDB connection section overlapping with a connection section of the reference power line GNDA and a reference power line overlapped with a control section of the reference power line GNDA.
  • the GNDB control section of the power supply resistance drop structure Referring to FIG. 6 and FIG. 7 , a connection line LEDL for the lamp area is provided between the reference power supply resistance drop structure GNDB connection section and the reference power supply resistance drop structure GNDB control section.
  • the reference power supply resistance reducing structure GNDB control section is provided with an avoidance gap exposing the control section of the reference power supply line GNDA, and the reference power connection line GNDL passes through the via hole and the reference power supply line GNDA in the avoidance gap. electrical connection.
  • the auxiliary reference power supply line GNDA may not be provided with a corresponding reference power supply resistance drop structure GNDB.
  • the resistance reducing structure may include a lamp region power supply resistance reducing structure VLEDB corresponding to the lamp region power supply line VLEDA; the lamp region power supply resistance reducing structure VLEDB is formed on the substrate
  • the orthographic projection on BP is located in the corresponding lamp area power line VLEDA, and is electrically connected to the lamp area power line VLEDA through a plurality of via holes HH.
  • at least part of the via hole HH located between the lamp area power line VLEDA and the lamp area power supply resistance reducing structure VLEDB can be arranged around the edge of the lamp area power supply resistance reducing structure VLEDB, so as to efficiently reduce the power supply line VLEDA of the lamp area.
  • one or more edges of the light area power supply resistance reducing structure VLEDB may also be provided between the lamp area power supply line VLEDA and the lamp area power supply resistance reducing structure VLEDB.
  • the via holes HH so that these via holes and some via holes located at the edge form a via hole row, increasing the density of via holes and reducing the impedance of the power line VLEDA of the lamp area.
  • the vias located between the lamp area power supply line VLEDA and the lamp area power supply resistance reducing structure VLEDB can be arranged in two via hole rows, and each via hole row includes A plurality of via holes arranged in the direction H1.
  • the two via hole rows can be respectively arranged at both ends of the lamp area power supply resistance reducing structure VLEDB in the column direction H2.
  • each via hole in a row of via holes may be connected in sequence to form an elongated hole extending along the row direction H1 as a whole.
  • the lamp area power supply resistance reducing structure VLEDB in the non-fan-out area, can completely overlap with the lamp area power supply line VLEDA, so that the lamp area power supply resistance reducing structure VLEDB has the largest layout area and can maximize Minimize the impedance of the power line VLEDA of the lamp area.
  • the resistance reducing structure may include a chip power supply resistance reducing structure VCCB; the orthographic projection of the chip power supply resistance reducing structure VCCB on the base substrate BP is located in the chip power supply line VCCA, and It is electrically connected to the chip power line VCCA through a plurality of via holes.
  • the chip power supply resistance reducing structure VCCB may overlap with the avoidance section of the chip power supply line VCCA, but not overlap with the non-avoidance section of the chip power supply line VCCA.
  • the chip power supply resistance reducing structure VCCB is connected to the chip power supply line VCCA through a plurality of via holes arranged in sequence along the column direction H2 .
  • the device layer may also be provided with a capacitor, and the two pins of the capacitor are respectively electrically connected to the reference power line GNDA and other power supply lines (other power supply lines other than the reference power line GNDA), so as to The signal of the power trace is stabilized, the noise on the power trace is filtered and the coupling between the power trace and the reference power line GNDA is decoupled, and the voltage fluctuation on the power trace is prevented from degrading the quality of the light-emitting substrate.
  • the capacitor can be arranged outside the lamp area AA, so as to reduce the influence on the uniformity of light output from the light-emitting substrate and reduce the difficulty of wiring.
  • the capacitors may be evenly distributed on the light-emitting substrate, so as to eliminate possible fluctuations of the voltage signal more efficiently and uniformly, and make the influence on the uniformity of light output from the light-emitting substrate more uniform.
  • capacitors may be provided only on part of the power supply lines, so as to avoid placing capacitors on each power supply line and resulting in too large a density of capacitors, thereby avoiding too large a density of capacitors and affecting the uniformity of light output from the light-emitting substrate.
  • a first capacitor Cst1 may be provided between at least part of the lamp area power line VLEDA and the reference power line GNDA, so that the noise on the lamp area power line VLEDA is filtered out. , thereby improving the stability of the lamp area power supply voltage VLED on the lamp area power line VLEDA.
  • the wiring metal layer Cu2 may be provided with a first capacitor pad group, and the first capacitor pad group includes capacitors connected to the lamp area power line VLEDA through via holes and the first pad for the main capacitor.
  • the reference power line GNDA is connected to the second pad of the first capacitor through the via hole.
  • the two pins of the capacitor are electrically connected to the first pad of the first capacitor and the second pad of the first capacitor respectively.
  • capacitors may be connected to the power lines VLEDA of some lamp areas and no capacitors may be connected to the power lines VLEDA of the remaining lamp areas, so as to avoid too many capacitors affecting the light uniformity of the light-emitting substrate.
  • two adjacent lamp area power lines VLEDA of two adjacent signal channels CH are electrically connected to each other to form a combined lamp area power line VLEDA, for example, merged into a wider wiring or interconnected through a conductive structure. connected to form a hollow structure.
  • a first capacitor is connected between any merged light area power line VLEDA and the reference power line GNDA. Further, 3-5 first capacitors are connected to the power line VLEDA of each merged lamp area.
  • the number of columns of the lamp area AA on the light-emitting substrate is 80 columns, and the number of rows of the lamp area AA is 45 rows (one chip IC can drive Two lamp areas AA).
  • the first capacitor Cst1 is disposed on the power line VLEDA of the lamp area driving the even or odd columns.
  • Each first capacitor Cst1 is arranged in four rows, and each first capacitor Cst1 row is adjacent to the 11th row (starting from the end close to the bonding pad), the 13th row, the 33rd row and the 39th row of lamp areas AA.
  • a second capacitor Cst2 may be provided between at least part of the chip power line VCCA and the main reference power line GNDA, so that the noise on the chip power line VCCA is filtered, Further, the stability of the chip power supply voltage VCC on the chip power line VCCA is improved.
  • the wiring metal layer Cu2 may be provided with a second capacitor pad group, and the second capacitor pad group includes the first pad of the second capacitor connected to the chip power line VCCA through a via hole and the main reference power line.
  • GNDA is connected to the second pad of the second capacitor through a via.
  • the two pins of the capacitor are electrically connected to the first pad of the second capacitor and the second pad of the second capacitor respectively.
  • the second capacitor Cst2 may be connected to some chip power lines VCCA and the second capacitor Cst2 may not be connected to the rest of the chip power lines VCCA, so as to avoid too many second capacitors Cst2 affecting the light uniformity of the light-emitting substrate. .
  • the second capacitor Cst2 is connected to the power line VCCA of each chip. Further, the number of second capacitors Cst2 connected to each chip power line VCCA is 2-4.
  • the number of columns of the lamp area AA on the light-emitting substrate is 80 columns, and the number of rows of the lamp area AA is 45 rows (one chip IC can drive Two lamp areas AA).
  • Each chip power line VCCA is connected to three second capacitors Cst2.
  • Each second capacitor Cst2 is arranged in three rows, and the second capacitor Cst2 row is adjacent to the third row (starting from the end close to the bonding pad), the 23rd row, and the 43rd row of light areas AA.
  • the electronic component may further include a temperature sensor for measuring temperature and a third capacitor for filtering a power line of the temperature sensor.
  • the driving wiring includes a temperature sensor power supply line for applying a temperature sensor power supply voltage to the temperature sensor.
  • One pin of the third capacitor is electrically connected to the temperature sensor power line, and the other pin is electrically connected to the main reference power line GNDA.
  • each temperature sensor power line is connected with a third capacitor.
  • 2-4 third capacitors are connected to each temperature sensor power line.
  • the wiring metal layer Cu2 is provided with a third capacitor pad group, a first temperature sensor wire, a temperature sensor second wire, and a temperature sensor pad group for binding the temperature sensor.
  • the first trace of the temperature sensor is electrically connected to the power line of the temperature sensor, and is electrically connected to the pad group of the temperature sensor, so as to load the power supply voltage of the temperature sensor to the temperature sensor.
  • the second wire of the temperature sensor is electrically connected to the reference power line GNDA, and is electrically connected to the temperature sensor pad group, so as to load the reference power voltage GND to the temperature sensor.
  • the third capacitor pad group includes the first pad of the third capacitor and the second pad of the third capacitor; the first pad of the third capacitor is set on the first wiring of the temperature sensor, and the second pad of the third capacitor is set on the temperature sensor Second trace.
  • the two pins of the third capacitor are electrically connected to the first pad of the third capacitor and the second pad of the third capacitor respectively.
  • the number of columns of the lamp area AA on the light-emitting substrate is 80 columns, and the number of rows of the lamp area AA is 45 rows (one chip IC can drive Two lamp areas AA).
  • the light-emitting substrate is provided with at least 5 columns of temperature sensor power lines, and the 5 columns of temperature sensor power lines are respectively adjacent to the 8th, 24th, 40th, 56th and 72nd column of lamp areas.
  • Each column of temperature sensor power lines includes three temperature sensor power lines, and each temperature sensor power line is connected to a third capacitor. The respective third capacitors are arranged in three rows and five columns.
  • each third capacitor row is adjacent to the 6th row (starting from the end close to the bonding pad), the 22nd row, and the 38th row with the light area AA.
  • each third capacitor adjoins the 8th, 24th, 40th, 56th and 72nd column lamp areas.
  • the main reference power lines GNDA can be merged with each other to form a main reference power line GNDA with a larger width. In this way, only one main reference power line GNDA can be provided in one signal channel CH on the light-emitting substrate.
  • the main reference power line GNDA is disposed on a side of the chip power line VCCA away from the driving data line DataA.
  • the chip pad group ICPAD is located on one side of the main reference power line GNDA without overlapping with the main reference power line GNDA, which makes the chip pad group ICPAD deviate from the signal channel CH in the row direction. center. In one embodiment of the present disclosure, the chip pad group ICPAD is located between the main reference power line GNDA and the auxiliary reference power line GNDA.
  • the driving wires in a signal channel CH may include lamp area power line VLEDA, main reference power line GNDA, chip power line VCCA, Address configuration line DSA, clock signal line CLKA, auxiliary reference power line GNDA, driving data line DataA, auxiliary reference power line GNDA and lamp area power line VLEDA.
  • an auxiliary reference power line GNDA is provided between the clock signal line CLKA and the driving data line DataA, thereby preventing the signal on the driving data line DataA from causing crosstalk to the clock signal line CLKA.
  • the lamp area power supply voltage V lamp area connecting line LEDL, light-emitting element pad group LEDPAD, etc. set by the wiring metal layer Cu2 can be connected with the lamp area power line VLEDA, the reference power line GNDA etc. overlap.
  • the wiring metal layer Cu2 is provided with a lamp area power supply resistance reducing structure VLEDB overlapping with the lamp area power supply line VLEDA, and the lamp area power supply resistance reducing structure VLEDB is connected to the lamp area power line VLEDA through a plurality of via holes A plurality of via holes are at least partially arranged around the edge of the lamp area power supply resistance drop structure VLEDB.
  • the wiring metal layer Cu2 is provided with a reference power supply resistance reducing structure GNDB that partially overlaps with the main reference power supply line GNDA, and a lamp area power supply voltage V lamp area connecting line LEDL, Light-emitting element pad group LEDPAD, etc.
  • the reference power supply resistance reducing structure GNDB is connected to the reference power supply line GNDA through a plurality of via holes, and the plurality of via holes are at least partially arranged around the edge of the reference power supply resistance reducing structure GNDB.
  • the chip pad group ICPAD is disposed between the chip power line VCCA and the main reference power line GNDA.
  • the driving metal layer Cu1 is provided with an output transfer wire OUTC between the main reference power line GNDA and the chip pad group ICPAD, and the lamp area power supply voltage V lamp area connection line LEDL connected to the third output pad OUT3P passes through the output transfer wire OUTC jumper.
  • the clock signal connection line CLKL overlaps with the chip power line VCCA, the address configuration line DSA, and the clock signal line CLKA, and is electrically connected to the clock signal pad CLKP, and the clock signal line CLKA.
  • the driving data connection line DataL overlaps with the chip power line VCCA, the address configuration line DSA, the clock signal line CLKA, the auxiliary reference power line GNDA and the driving data line DataA, and is connected to the driving data pad DataP and the driving data line DataA.
  • the address configuration connection line DISL overlaps with the output transfer line OUTC, the main reference power line GNDA, the chip power line VCCA and the front address configuration line DSA, and is connected to the address configuration pad DISP and the front address configuration line DSA.
  • the address relay connection line DOSL overlaps with the chip power line VCCA and the rear address configuration line DSA, and is connected with the chip power pad VCCP and the rear address configuration line DSA.
  • the reference power connection line GNDL includes a first reference power connection line GNDL1 and a second reference power connection line GNDL2.
  • the main reference power supply voltage GND has a reference power line extension GNDE extending to the side close to the reference power pad GNDP, the first reference power connection line GNDL1 and the reference power line extension GNDE, the reference power pad GNDP and the chip power line VCCA
  • the auxiliary reference power line GNDA is connected to the auxiliary reference power line GNDA
  • the second reference power connection line GNDL2 is connected to the two auxiliary reference power lines GNDA.
  • the chip power line VCCA is provided with a chip power line avoidance gap VCCAG avoiding the chip pad group ICPAD on a side close to the main reference power line GNDA.
  • the chip pad group ICPAD is disposed in the chip power line avoidance gap VCCAG.
  • the chip power line VCCA has an avoidance section where the chip power line avoidance gap VCCAG is set and a non-avoidance section where the chip power line avoidance gap VCCAG is not set, wherein the width of the avoidance section of the chip power line VCCA is smaller than that of the non-avoidance section of the chip power line VCCA width.
  • the wiring metal layer Cu2 is further provided with a chip power supply resistance reducing structure VCCB, and the chip power supply resistance reducing structure VCCB is connected to the non-avoiding section of the chip power line VCCA through a via hole.
  • the wiring arrangement in a local area can be fine-tuned according to the actual wiring requirements. For example, when a wiring located in the driving metal layer Cu1 is blocked by other wirings in the driving metal layer Cu1, the wiring can be The bridging is performed through the wiring metal layer Cu2. Correspondingly, when a wire in the wiring metal layer Cu2 is blocked by other wires in the wiring metal layer Cu2, the wire can be bridged through the driving metal layer Cu1. In some embodiments, in the fan-out region of the PNL, the fan-out line is arranged on the driving metal layer Cu1; when the fan-out line is blocked by other driving lines, the fan-out line can be partially bridged through the wiring metal layer Cu2 .
  • some chip ICs need to use long connecting lines to connect to the driving lines and the lamp area, and these connecting lines may need to be bent to avoid other connecting lines.
  • the driving metal layer Cu1 can also be bridged to avoid other wirings.
  • the light-emitting substrate can directly display images as a display panel, and can also be used as a backlight for a transmissive liquid crystal display device or as a front light source for a reflective liquid crystal display device.
  • the display device may be a mobile phone screen, a computer monitor, a television, an electronic billboard or other display devices, which are not specifically limited in the present disclosure.

Abstract

提供一种发光基板和显示装置，属于显示技术领域。发光基板包括沿行方向(H1)依次排列的多个信号通道(CH)；每个信号通道(CH)包括沿列方向(H2)排列的多个控制区(BB)；每个控制区(BB)包括由同一芯片(IC)控制的至少一个灯区(AA)；每个信号通道(CH)中，发光基板设置有第一驱动走线、第二驱动走线和多个参考电源线(GNDA)；第一驱动走线、第二驱动走线分别用于向芯片(IC)提供不同的驱动信号；参考电源线(GNDA)用于向芯片(IC)提供参考电源电压(GND)；其中，同一信号通道(CH)中的各个参考电源线(GNDA)之间电连接，且第一驱动走线和第二驱动走线之间设置有至少一根参考电源线(GNDA)。该发光基板能够减小至少部分驱动走线上的噪音。

Description

发光基板和显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种发光基板和显示装置。
背景技术
LED(发光二极管)发光基板可以采用主动驱动模式进行驱动；其中，在发光区域设置有LED和用于驱动LED的芯片。外部电路(例如电路板)通过设置于发光基板上的驱动走线向LED和芯片提供电源和信号。驱动走线被干扰而产生噪音时，LED发光基板的发光质量将受到较大程度的影响。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于克服上述现有技术的不足，提供一种发光基板和显示装置，降低至少部分驱动走线上的噪音。
根据本公开的第一个方面，提供一种发光基板，包括沿行方向依次排列的多个信号通道；每个所述信号通道包括沿列方向排列的多个控制区；每个所述控制区包括由同一芯片控制的至少一个灯区；
每个所述信号通道中，所述发光基板设置有第一驱动走线、第二驱动走线和多个参考电源线；所述第一驱动走线、所述第二驱动走线分别用于向所述芯片提供不同的驱动信号；所述参考电源线用于向所述芯片提供参考电源电压；其中，同一所述信号通道中的各个所述参考电源线之间电连接，且所述第一驱动走线和所述第二驱动走线之间设置有至少一根所述参考电源线。
在本公开的一种实施方式中，所述第一驱动走线为向所述芯片提供时钟信号的时钟信号线；
所述第二驱动走线为用于向所述芯片提供驱动数据信号的驱动数据线或者用于向所述芯片提供地址配置信号的地址配置线。
在本公开的一种实施方式中，所述第二驱动走线为驱动数据线。
在本公开的一种实施方式中，在所述信号通道中，所述发光基板还包括用于向所述灯区加载灯区电源电压的灯区电源线、用于向所述芯片加载芯片电源电压的芯片电源线、用于向所述芯片加载地址配置信号的地址配置线；
沿所述行方向，所述灯区电源线、所述参考电源线、所述芯片电源线、所述地址配置线、所述时钟信号线、所述参考电源线、所述驱动数据线、所述参考电源线和所述灯区电源线依次设置。
在本公开的一种实施方式中，在所述地址配置线和所述时钟信号线之间也设置有所述参考电源线。
在本公开的一种实施方式中，所述发光基板具有用于与所述芯片绑定连接的芯片焊盘组，以及设置有参考电源连接线；
其中，所述参考电源连接线与各个所述参考电源线通过过孔连接，且与所述芯片焊盘组电连接。
在本公开的一种实施方式中，在所述信号通道中，所述多个参考电源线包括位于所述信号通道两侧的两个主参考电源线和位于所述主参考电源线之间的辅助参考电源线；所述主参考电源线的宽度大于所述辅助参考电源线的宽度；
所述主参考电源线与所述灯区交叠，且与至少部分所述芯片不交叠。
在本公开的一种实施方式中，在所述信号通道中，所述多个参考电源线包括一个主参考电源线和至少一个辅助参考电源线；所述主参考电源线在各个所述参考电源线中宽度最大，且与所述驱动数据线、所述时钟信号线不相邻。
在本公开的一种实施方式中，所述芯片位于所述主参考电源线和所述辅助参考电源线之间。
在本公开的一种实施方式中，在所述信号通道中，所述发光基板还包括用于向所述灯区加载灯区电源电压的灯区电源线、用于向所述芯片加载芯片电源电压的芯片电源线；
所述主参考电源线与所述灯区电源线相邻，且宽度大于所述芯片电源线；
所述辅助参考电源线的宽度小于所述芯片电源线。
在本公开的一种实施方式中，所述发光基板还包括用于向所述灯区加载灯区电源电压的灯区电源线、用于向所述芯片加载芯片电源电压的芯片电源线；在至少部分所述灯区电源线与所述参考电源线之间，设置有第一电容器；和/或者，在至少部分所述芯片电源线与所述参考电源线之间，设置有第二电容器。
在本公开的一种实施方式中，在沿所述行方向相邻的两个所述信号通道中，其中一个所述信号通道中的一个灯区电源线与另一个所述信号通道中的一个所述灯区电源线相邻设置；该相邻设置的两个所述灯区电源线相互连接为合并的灯区电源线；所述合并的灯区电源线为两个所述信号通道中的灯区提供所述灯区电源电压；
任意一个所述合并的灯区电源线与所述参考电源线之间，设置有3～5个所述第一电容器。
在本公开的一种实施方式中，任意一个所述芯片电源线与所述参考电源线之间，设置有2～4个所述第二电容器。
在本公开的一种实施方式中，所述发光基板设置有温度传感器，以及用于向所述温度传感器加载温度传感器电源电压的温度传感器电源线；
任意一个所述温度传感器电源线与所述参考电源线之间，设置有第三电容器。
在本公开的一种实施方式中，所述发光基板包括依次层叠设置的衬底基板、驱动金属层、第一绝缘层、布线金属层、第二绝缘层和器件层；
所述驱动金属层设置有所述第一驱动走线、所述第二驱动走线和所述参考电源线；
所述灯区包括电连接的多个发光元件；所述发光元件和所述芯片设置于所述器件层；
所述布线金属层设置有用于绑定所述发光元件的发光元件焊盘组、用于绑定所述芯片的芯片焊盘组、用于与所述发光元件焊盘组和所述芯片焊盘组电连接的连接走线。
在本公开的一种实施方式中，所述布线金属层设置有与至少部分所述参考电源线对应的参考电源降阻结构；所述参考电源降阻结构与对应的所述参考电源线通过过孔连接。
在本公开的一种实施方式中，所述参考电源降阻结构在所述衬底基板上的正投影，位于对应的所述参考电源线在所述衬底基板的正投影的范围内。
在本公开的一种实施方式中，所述参考电源降阻结构与对应的所述参考电源线之间的至少部分过孔，环绕所述参考电源降阻结构的边缘分布。
在本公开的一种实施方式中，在所述信号通道中，多个所述参考电源线具有宽度最大的一个或者两个主参考电源线；所述参考电源降阻结构与所述主参考电源线连接。
在本公开的一种实施方式中，所述驱动金属层设置有用于向所述灯区加载灯区电源电压的灯区电源线；所述布线金属层设置有与所述灯区电源线对应的灯区电源降阻结构；所述灯区电源线与对应的所述灯区电源降阻结构之间通过过孔连接。
在本公开的一种实施方式中，所述灯区电源降阻结构与对应的所述灯区电源线之间的至少部分过孔，环绕所述灯区电源降阻结构的边缘分布。
在本公开的一种实施方式中，所述灯区电源降阻结构在所述衬底基板上的正投影，与对应的所述灯区电源线在所述衬底基板上的正投影重合。
在本公开的一种实施方式中，所述驱动金属层设置有用于向所述芯片加载芯片电源电压的芯片电源线；所述布线金属层设置有与所述芯片电源线对应的芯片电源降阻结构；所述芯片电源降阻结构与对应的所述芯片电源线之间通过过孔连接。
在本公开的一种实施方式中，所述芯片电源降阻结构与对应的所述芯片电源线之间的至少部分过孔，沿列方向直线排列。
根据本公开的第二个方面，提供一种显示装置，包括上述的发光基板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开的一种实施方式中，芯片的引脚示意图。
图2为本公开的一种实施方式中，芯片焊盘组与驱动走线之间连接的原理示意图。
图3为本公开的一种实施方式中，芯片焊盘组与驱动走线之间连接的原理示意图。
图4为本公开的第一种实施方式中，驱动金属层的局部结构示意图。
图5为本公开的第一种实施方式中，布线金属层的局部结构示意图。
图6为本公开的第一种实施方式中，驱动金属层和布线金属层的局部结构示意图。
图7为本公开的第一种实施方式中，驱动金属层、布线金属层和设置于第一绝缘层上的过孔的局部结构示意图。
图8为图7在芯片区周围的局部放大图。
图9为本公开的第二种实施方式中，驱动金属层的局部结构示意图。
图10为图9在芯片区周围的局部放大图。
图11为本公开的第二种实施方式中，布线金属层的局部结构示意图。
图12为图11在芯片区周围的局部放大图。
图13为本公开的第二种实施方式中，驱动金属层、布线金属层和设置于第一绝缘层上的过孔的在芯片区周围的局部结构示意图。
图14为本公开的第三种实施方式中，驱动金属层、布线金属层和设置于第一绝缘层上的过孔的在芯片区周围的局部结构示意图。
图15为本公开的第四种实施方式中，驱动金属层、布线金属层和设置于第一绝缘层上的过孔的在芯片区周围的局部结构示意图。
图16为本公开的一种实施方式中，第一绝缘层上的过孔与降阻结构的示意图。
图17为本公开的一种实施方式中，第一绝缘层上的过孔与降阻结构的示意图。
图18为本公开的一种实施方式中，第一绝缘层上的过孔与降阻结构的示意图。
图19为本公开的一种实施方式中，第一绝缘层上的过孔与降阻结构的示意图。
图20为本公开的一种实施方式中，第一绝缘层上的过孔与降阻结构的示意图。
图21为本公开的一种实施方式中，发光基板的膜层结构示意图。
附图标记说明：
AA、灯区；BB、控制区；CH、信号通道；BP、衬底基板；Cu1、驱动金属层；Cu2、布线金属层；OC1、第一绝缘层；OC2、第二绝缘层；VLED、灯区电源电压；GND、参考电源电压；VCC、芯片电源电压；DIS、地址配置信号；DOS、地址中继信号；Data、驱动数据信号；CLK、时钟信号；GNDD、参考电源引脚；VCCD、芯片电源引脚；DISD、地址配置引脚；DOSD、地址中继引脚；DataD、驱动数据引脚；CLKD、时钟信号引脚；ICA、芯片区；VLEDA、灯区电源线；GNDA、参考电源线；VCCA、芯片电源线；DSA、地址配置线；DataA、驱动数据线；CLKA、时钟信号线；VLEDB、灯区电源降阻结构；GNDB、参考电源降阻结构；VCCB、芯片电源降阻结构；GNDL、参考电源连接线；VCCL、芯片电源连接线；DISL、地址配置连接线；DOSL、地址中继连接线；DataL、驱动数据连接线；CLKL、时钟信号连接线；LEDL、灯区连接线；DSC、地址配置转接结构；GNDE、参考电源线延伸部；VCCAG、芯片电源线避让缺口；GNDAG、参考电源线避让缺口；LEDPAD、发光元件焊盘组；LEDPAD1、发光元件第一焊盘；LEDPAD2、发光元件第二焊盘；ICPAD、芯片焊盘组；Cst1、第一电容器；Cst2、第二电容器；GNDP、参考电源焊盘；VCCP、芯片电源焊盘；DISP、地址配置焊盘；DOSP、地址中继焊盘；DataP、驱动数据焊盘；CLKP、时钟信号焊盘；HH、过孔；H1、行方向；H11、预设方向；H2、列方向。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
在本公开中，除非特别说明，否则走线的宽度指的是，该走线在行方向上的尺寸。
在本公开中，除非特别说明，当描述两个结构之间的相对位置关系时，指的是两个结构在衬底基板上的正投影之间的位置关系。当说明两个结构相对于衬底基板的位置关系时，指的是两个结构在垂直于衬底基板方向上的位置关系，即两个结构所处的膜层之间的层得关系。
当描述两个结构之间交叠时，指的是两个结构处于不同的膜层，且两个结构在衬底基板上的正投影至少部分重合。当描述两个结构之间完全交叠时，指的是其中一个结构在衬底基板上的正投影，完全在另一个结构在衬底基板上的正投影内。当描述两个结构之间不交叠时，指的是其中一个结构在衬底基板上的正投影，在另一个结构在衬底基板上的正投影之外。
本公开提供一种发光基板以及具有该发光基板的显示装置。参见图21，该发光基板包括依次层叠设置的衬底基板BP、驱动金属层Cu1、第一绝缘层OC1、布线金属层Cu2、第二绝缘层OC2和器件层。其中，驱动金属层Cu1形成有驱动走线，驱动走线用于与外部电路(例如电路板)电连接，并向位于器件层的电子元件提供信号和电源。布线金属层Cu2通过过孔与驱动金属层Cu1连接，其设置有用于绑定电子元件的焊盘和与焊盘连接的连接走线，至少部分连接走线与驱动走线电连接以向各个电子元件加载信号和电源(在本公开中，可以将用于加载电源电压的驱动走线定义为电源走线)。其中，第一绝缘层OC1用于隔离驱动金属层Cu1和布线金属层Cu2，其设置有使得驱动金属层Cu1和布线金属层Cu2电连接的过孔。第二绝缘层OC2用于对布线金属层Cu2进行保护，其设置有暴露焊盘的过孔，以使得电子元件可以通过过孔与焊盘绑定连接。
在本公开中，驱动金属层Cu1和/或布线金属层Cu2上还可以设置有用于与外部电路绑定连接的绑定焊盘。绑定焊盘可以设置于发光基板的边缘。发光基板在靠近绑定焊盘的一端设置有扇出区，扇出区内设置有与各个驱动走线一一对应电连接的扇出走线，扇出走线可以弯折以连接至对应的绑定焊盘上。其中，扇出走线可以设置于驱动金属层Cu1，也可以设置于布线金属层Cu2；部分扇出走线还可以在驱动金属层Cu1和布线金属层Cu2之间跨接设置。在本公开的一种实施方式中，扇出区可以跨越2～4个灯区行，例如跨越三个灯区行。
在本公开中，可以将驱动走线在非扇出区部分的延伸方向定义为列方向H2，将垂直于列方向H2且平行于发光基板所在平面的方向定义为行方向H1。在本公开的一些实施方式中，扇出区和绑定焊盘位于发光基板的列方向H2的其中一端。进一步地，在发光基板远离扇出区的一端，至少部分加载相同电源的驱动走线(即电源走线)可以相互电连接。可以理解的是，在发光基板的端部，相同的电源走线之间既可以通过位于驱动金属层Cu1的导电结构电连接，也可以通过位于布线金属层Cu2的导电结构电连接，还可以同时利用驱动金属层Cu1和布线金属层Cu2的导电结构进行电连接，本公开对此不做特殊的限定。
举例而言，在本公开的一种实施方式中，电源走线可以包括用于加载 参考电源电压GND的参考电源线GNDA、用于加载灯区电源电压VLED的灯区电源线VLEDA。在远离扇出区的一端，各个参考电源线GNDA之间通过位于驱动金属层Cu1和/或布线金属层Cu2的导电走线电连接，各个灯区电源线VLEDA之间通过位于驱动金属层Cu1和/或布线金属层Cu2的导电走线电连接。
当然的，在本公开的其他实施方式中，发光基板的列方向H2的两端可以均设置有绑定焊盘和与绑定焊盘毗邻的扇出区。用于驱动发光基板的外部电路，可以与任意一端的绑定焊盘电连接，以驱动该发光基板。
如下，从各个膜层的材料的角度，对本公开的发光基板的各个膜层进行示例性地的介绍和说明。
在本公开中，衬底基板BP可以为无机材料的衬底基板BP，也可以为有机材料的衬底基板BP。举例而言，在本公开的一种实施方式中，衬底基板BP的材料可以为钠钙玻璃(soda-lime glass)、石英玻璃、蓝宝石玻璃等玻璃材料，即衬底基板BP可以为玻璃基板。在本公开的另一种实施方式中，衬底基板BP的材料可以为聚甲基丙烯酸甲酯(Polymethyl methacrylate，PMMA)、聚乙烯醇(Polyvinyl alcohol，PVA)、聚乙烯基苯酚(Polyvinyl phenol，PVP)、聚醚砜(Polyether sulfone，PES)、聚酰亚胺、聚酰胺、聚缩醛、聚碳酸酯(Poly carbonate，PC)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，PET)、聚萘二甲酸乙二酯(Polyethylene naphthalate，PEN)或其组合，即衬底基板BP可以为有机柔性基板。当然地，在本公开的其他实施方式中，衬底基板BP还可以为其他材料和结构，例如为多层复合的衬底基板BP，以能够有效的支撑发光基板为准。
在一些实施方式中，驱动金属层Cu1的厚度可以大于布线金属层Cu2的厚度，以降低各个驱动走线的阻抗，降低发光基板的功耗并降低发光基板的调试难度，提高发光基板的发光均一性。可选地，可以采用电镀铜、化学镀铜、多层薄金属层层叠或者其他可行的方法进行制备，以使得驱动金属层Cu1具有满足发光基板的电学性能所需的厚度为准。其中，任意薄层金属层可以采用磁控溅射的方法进行制备。布线金属层Cu2层可以采用磁控溅射的方法进行制备。在本公开的一种实施方式中，驱动金属层Cu1的厚度可以在1～20微米之间，例如在2～5微米之间。在本公开的一种实 施方式中，布线金属层Cu2的厚度在0.3～0.8微米之间，例如在0.3～0.5微米之间。当然地，在本公开的其他实施方式中，驱动金属层Cu1和布线金属层Cu2的厚度可以相差不大，以能够满足发光基板对驱动走线的电学性能要求为准。
可选地，驱动金属层Cu1可以包括一层或者多层层叠的金属层。在本公开的一种实施方式中，驱动金属层Cu1中至少包括一层铜金属层，以提高驱动金属层Cu1的导电性能，降低驱动金属层Cu1的方阻。进一步地，驱动金属层Cu1中还可以包括其他金属层，例如包括位于铜金属层上(远离衬底基板BP一侧)或者下(靠近衬底基板BP一侧)的合金层(例如钼铌合金层)。
在本公开的一种实施方式中，可以在衬底基板BP上通过光刻工艺形成驱动金属层Cu1，包括溅射(Sputter)、清洁(Cleaning)、涂覆(Coating)、烘烤、曝光(Photo)、显影、硬烤、刻蚀(Etch)、剥离等步骤。
在一些实施方式中，在驱动金属层Cu1上表面(远离衬底基板BP的表面)还可以设置有第一钝化层，第一钝化层用于保护驱动金属层Cu1，避免驱动金属层Cu1在工艺过程中被氧化。第一钝化层的材料可以为氮化硅、氧化硅、氮氧化硅等无机绝缘材料，尤其是可以为氮化硅。
第一绝缘层OC1设置于驱动金属层Cu1远离衬底基板BP的一侧。在一些实施方式中，第一绝缘层OC1的材料可以为光敏树脂等有机材料；可以通过涂覆、曝光、显影的工艺形成第一绝缘层OC1，使得第一绝缘层OC1覆盖驱动金属层Cu1且形成有暴露部分驱动金属层Cu1的过孔。当发光基板设置有第一钝化层时，第一绝缘层OC1形成于第一钝化层远离衬底基板BP的一侧。在第一绝缘层OC1形成过孔后，可以以第一绝缘层OC1为掩膜，在第一钝化层上开设暴露驱动金属层Cu1的过孔。
在本公开中，布线金属层Cu2可以包括一层或者多层层叠的金属层。在本公开的一种实施方式中，布线金属层Cu2中至少包括一层铜金属层，以提高布线金属层Cu2的导电性能，降低布线金属层Cu2的方阻。进一步地，布线金属层Cu2中还可以包括其他金属层，例如包括位于铜金属层上(远离衬底基板BP一侧)或者下(靠近衬底基板BP一侧)的合金层(例如钼铌合金层)。
在本公开的一种实施方式中，可以在衬底基板BP上通过光刻工艺形成布线金属层Cu2，包括溅射(Sputter)、清洁(Cleaning)、涂覆(Coating)、烘烤、曝光(Photo)、显影、硬烤、刻蚀(Etch)、剥离等步骤。
在一些实施方式中，在布线金属层Cu2上表面(远离衬底基板BP的表面)还可以设置有第二钝化层，第二钝化层用于保护布线金属层Cu2，避免布线金属层Cu2在发光基板的制备过程中被氧化。第二钝化层的材料可以为氮化硅、氧化硅、氮氧化硅等无机绝缘材料，尤其是可以为氮化硅。
第二绝缘层OC2设置于布线金属层Cu2远离衬底基板BP的一侧。在一些实施方式中，第二绝缘层OC2的材料可以为光敏树脂等有机材料。可以通过涂覆、曝光、显影的工艺形成第二绝缘层OC2，使得第二绝缘层OC2覆盖布线金属层Cu2且形成有暴露部分布线金属层Cu2的过孔。当发光基板设置有第二钝化层时，第二绝缘层OC2形成于第二钝化层远离衬底基板BP的一侧。在第二绝缘层OC2形成过孔后，可以以第二绝缘层OC2为掩膜，在第二钝化层上开设暴露焊盘的过孔。
可以理解的是，在本公开的其他实施方式中，驱动金属层Cu1、布线金属层Cu2的材料、膜层结构和形成方法，还可以为其他可行方式，以能够形成满足发光基板电性需求的驱动金属层Cu1、布线金属层Cu2为准。相应的，第一绝缘层OC1、第二绝缘层OC2的材料和形成方法，也可以为其他可行方式。
在本公开中，器件层可以包括与布线金属层Cu2绑定连接的各个电子元件，这些电子元件可以包括发光元件和驱动发光元件的芯片IC。对应的，在布线金属层Cu2上的焊盘包括用于与发光元件绑定的发光元件焊盘组LEDPAD和用于与芯片IC绑定的芯片焊盘组ICPAD。在一些实施方式中，电子元件还可以包括温度传感器，则布线金属层Cu2还可以包括用于与温度传感器绑定的温度传感器焊盘组。在一些实施方式中，电子元件还可以包括电容器，则布线金属层Cu2则还可以设置有用于与电容器绑定连接的电容器焊盘组。在一些实施方式中，发光元件可以为LED(发光二极管)、Mini LED(次毫米发光二极管，Mini Light Emitting Diode)、Micro LED(微型发光二极管，Micro Light Emitting Diode)等主动发光的电子元件，在本公开的附图中均以LED表示和示意。
在本公开的一种实施方式中，发光元件为Mini LED。其中，Mini LED的截面尺寸(长、宽或者对角线或者直径等参数)在大约100μm到大约300μm之间。
在本公开的另一种实施方式中，发光元件为Micro LED。其中，Mini LED的截面尺寸(长、宽或者对角线或者直径等参数)在100μm以下。
可以理解的是，在本公开的其他实施方式中，器件层还可以包括更多种类的电子元件，布线金属层Cu2可以根据电子元件的种类和位置，设置与之对应的焊盘。
从俯视的角度看，参见图2，本公开的发光基板可以包括沿行方向H1依次排列的多个信号通道CH(图2示出了一个信号通道CH的局部原理示意图)；每个信号通道CH包括沿列方向H2排列的多个控制区BB；每个控制区BB包括由同一芯片IC(图2中示出了用于绑定该芯片IC的芯片焊盘组ICPAD)控制的至少一个灯区AA。在本公开的一种实施方式中，每个控制区BB包括由同一芯片IC控制的多个灯区AA，例如四个灯区AA。其中，每个灯区AA包括一个或者多个电连接的发光元件。在本公开的一种实施方式中，每个灯区AA包括多个电连接的发光元件，例如包括依次串联的四个发光元件。可以理解的是，在一个灯区AA中，发光元件的数量可以为四个以外的其他数量，例如为两个、六个、九个等等，灯区AA中的发光元件可以并联或则串联，本公开对此不做特殊限制，以灯区AA中的各个发光元件能够同步工作为准。
图1示出了本公开一种实施方式中的芯片IC同时驱动四个灯区AA的原理示意图。参见图1，芯片IC包括四个输出引脚(即第一输出引脚OUT1D、第二输出引脚OUT2D、第三输出引脚OUT3D、第四输出引脚OUT4D)、时钟信号引脚CLKD、参考电源引脚GNDD、驱动数据引脚DataD、芯片电源引脚VCCD、地址中继引脚DOSD、地址配置引脚DISD等十个引脚。其中，第一输出引脚OUT1D、第二输出引脚OUT2D、第三输出引脚OUT3D、第四输出引脚OUT4D分别与一个灯区AA的第二端电连接，灯区AA的第一端用于加载灯区电源电压VLED。参考电源引脚GNDD用于向芯片IC加载参考电源电压GND，时钟信号引脚CLKD用于向芯片IC加载时钟信号CLK，驱动数据引脚DataD用于向芯片IC加载 驱动数据信号Data，芯片电源引脚VCCD用于向芯片IC加载芯片电源电压VCC，地址配置引脚DISD用于向芯片IC加载地址配置信号DIS，芯片IC通过地址中继引脚DOSD输出地址中继信号DOS。
图1示出了本公开一种实施方式中，芯片IC的各个引脚的排列方式。参加图1，芯片IC的各个引脚排列为两列，每列包括5个引脚。其中，每列具有两个输出引脚。在本公开的一种实施方式中，第一列引脚包括依次排列的时钟信号引脚CLKD、第一输出引脚OUT1D、地址配置引脚DISD、第三输出引脚OUT3D、芯片电源引脚VCCD，第二列引脚包括依次排列的驱动数据引脚DataD、第二输出引脚OUT2D、地址中继引脚DOSD、第四输出引脚OUT4D、参考电源引脚GNDD。可以理解的是，在本公开的其他实施方式中，芯片IC的各个引脚还可以采用其他的方式进行排列，例如调整每一列引脚中各个引脚的排列顺序或者使得各个引脚在两列中重新分布，亦或可以使得各个引脚排列成三列或者四列等，以使得芯片IC包括上述的十个引脚为准。
参见图2，同一信号通道CH中，各个芯片IC(图2中示出了用于绑定芯片IC的芯片焊盘组ICPAD)可以依次级联。在相邻级联的两个芯片IC中，上一级芯片IC的地址中继引脚DOSD可以与下一级芯片IC的地址配置引脚DISD电连接，使得上一级芯片IC的地址中继信号DOS作为下一级芯片IC的地址配置信号DIS。其中，各个芯片IC与各个控制区BB一一对应设置，每个控制区BB包括四个灯区AA，且该四个灯区AA由该控制区BB所对应的芯片IC驱动。芯片IC可以位于对应的控制区BB中，可以位于对应的控制区BB以外，以能够实现对控制区BB中的四个灯区AA的驱动为准。
本公开的芯片IC在工作时，可以此次在地址配置模式、驱动配置模式和器件驱动模式下工作。在地址配置模式下，外部电路可以向芯片IC的地址配置焊盘DISP加载地址配置信号DIS，芯片IC可以根据所接收的地址配置信号DIS来配置自身的地址，并自动生成地址中继信号DOS并通过地址中继焊盘DOSP输出。芯片IC所输出的地址中继信号DOS，可以作为下一级的地址配置信号DIS，使得下一级芯片IC进行地址配置。如此，一个信号通道CH中的各个芯片IC可以依次完成地址配置，确定 自身的地址信息。最后一级芯片IC所输出的地址中继信号DOS可以反馈至外部电路。在驱动配置模式下，外部电路向同一信号通道CH中的各个芯片IC发送驱动数据信号Data和时钟信号CLK。具体的，外部电路向芯片IC的时钟信号焊盘CLKP加载时钟信号CLK，向芯片IC的驱动数据焊盘DataP加载驱动数据信号Data。其中，时钟信号CLK用于控制芯片IC对驱动数据信号Data的采样，例如使得驱动数据焊盘DataP在时钟信号CLK的上升沿或者下降沿进行采样。驱动数据信号Data中包含各个芯片IC的驱动数据信息，每个驱动数据信息均与一个地址信息相对应(例如驱动数据信息具有地址信息标签)。各个芯片IC可以根据自身的地址信息，进而接收自身所需的驱动数据信息。在器件驱动模式下，芯片IC可以根据所接收的驱动数据信息，进而控制各个输出引脚的开启或者关闭，进而实现对各个灯区的控制。
图2和图3示出了本公开的一些实施方式中，发光基板在一个信号通道CH中的原理示意图。在图2和图3中，示出了用于与芯片IC绑定连接的芯片焊盘组ICPAD。在图2和图3中，各个驱动走线的顺序仅仅为原理性示意，并不表示本公开的发光基板的各个驱动走线按照图2和图3所示的顺序进行排列。
参见图2，驱动金属层Cu1中设置有驱动走线，这些驱动走线包括用于加载参考电源电压GND的参考电源线GNDA、用于加载灯区电源电压VLED的灯区电源线VLEDA、用于加载芯片电源电压VCC的芯片电源线VCCA、用于加载地址配置信号DIS的地址配置线DSA、用于加载驱动数据信号Data的驱动数据线DataA和用于加载时钟信号CLK的时钟信号线CLKA等。
用于与芯片IC绑定连接的芯片焊盘组ICPAD设置于布线金属层Cu2。芯片焊盘组ICPAD包括用于与参考电源引脚GNDD绑定连接的参考电源焊盘GNDP、用于与芯片电源引脚VCCD绑定连接的芯片电源焊盘VCCP、用于与驱动数据引脚DataD绑定连接的驱动数据焊盘DataP、用于与时钟信号引脚CLKD绑定连接的时钟信号焊盘CLKP、用于与地址配置引脚DISD绑定连接的地址配置焊盘DISP、用于与地址中继引脚DOSD绑定连接的地址中继焊盘DOSP、各分别与四个输出引脚绑定连接的四个输出焊 盘。四个输出焊盘包括用于与第一输出引脚OUT1D绑定连接的第一输出焊盘OUT1P、用于与第二输出引脚OUT2D绑定连接的第二输出焊盘OUT2P、用于与第三输出引脚OUT3D绑定连接的第三输出焊盘OUT3P、用于与第四输出引脚OUT4D绑定连接的第四输出焊盘OUT4P等十个焊盘。
芯片焊盘组ICPAD的各个焊盘的排布方式可以根芯片IC的引脚的排布方式相匹配，使得芯片IC的各个引脚能够一一对应的绑定至各个焊盘上。在本公开的一种实施方式中，参见图2，在一个芯片焊盘组ICPAD中，十个焊盘排列成两列。第一列焊盘包括依次排列的时钟信号焊盘CLKP、第一输出焊盘OUT1P、地址配置焊盘DISP、第三输出焊盘OUT3P、芯片电源焊盘VCCP，第二列焊盘包括依次排列的驱动数据焊盘DataP、第二输出焊盘OUT2P、地址中继焊盘DOSP、第四输出焊盘OUT4P、参考电源焊盘GNDP。
在本公开的一种实施方式中，参见图2和图3，芯片电源焊盘VCCP和驱动数据焊盘DataP分别设置于芯片焊盘组ICPAD的两列焊盘中，以设置有芯片电源焊盘VCCP的一列焊盘为第一列焊盘，以设置有驱动数据焊盘DataP的一列焊盘为第二列焊盘。其中，芯片焊盘组ICPAD在设置时，各列焊盘可以沿列方向H2延伸。这样，沿行方向H1，芯片电源焊盘VCCP位于驱动数据焊盘DataP的一侧。在本公开中，可以将行方向H1的其中一个特定方向定义为预设方向H11，以使得驱动数据焊盘DataP位于芯片电源焊盘VCCP的预设方向H11一侧。
参加图7和图8，布线金属层Cu2中还设置有用于绑定发光元件的发光元件焊盘组LEDPAD。其中，发光元件焊盘组LEDPAD可以包括用于与发光元件阳极连接的发光元件第一焊盘LEDPAD1和与发光元件阴极连接的发光元件第二焊盘LEDPAD2。
布线金属层Cu2中还可以设置有连接走线，连接走线可以与发光元件焊盘组LEDPAD和芯片焊盘组ICPAD连接。
连接走线可以包括与发光元件焊盘组LEDPAD电连接的灯区连接线LEDL，同一灯区AA中的发光元件焊盘组LEDPAD之间通过灯区连接线LEDL电连接，以使得同一灯区AA中的发光元件电连接。其中，灯区AA 中的一个发光元件第二焊盘LEDPAD2可以作为灯区AA的第二端而通过灯区连接线LEDL与输出焊盘(第一输出焊盘OUT1P、第二输出焊盘OUT2P、第三输出焊盘OUT3P、第四输出焊盘OUT4P中的任意一个)连接，灯区AA中的一个发光元件第一焊盘LEDPAD1可以作为灯区AA的第一端而通过灯区连接线LEDL与灯区电源线VLEDA连接。
连接走线还包括参考电源连接线GNDL、芯片电源连接线VCCL、驱动数据连接线DataL、地址配置连接线DISL、地址中继连接线DOSL、时钟信号连接线CLKL等。其中，参考电源焊盘GNDP通过参考电源连接线GNDL与参考电源线GNDA电连接，芯片电源焊盘VCCP通过芯片电源连接线VCCL与芯片电源线VCCA电连接，驱动数据焊盘DataP通过驱动数据连接线DataL与驱动数据线DataA电连接，地址配置焊盘DISP通过地址配置连接线DISL与地址配置线DSA连接，地址中继焊盘DOSP通过地址中继连接线DOSL与地址配置线DSA连接，时钟信号焊盘CLKP通过时钟信号连接线CLKL与时钟信号线CLKA连接。
参见图2，一个芯片焊盘组ICPAD与两个地址配置线DSA电连接，其中与地址配置焊盘DISP电连接的地址配置线DSA可以定义为该芯片焊盘组ICPAD的前地址配置线DSA，与地址中继焊盘DOSP电连接的地址配置线DSA可以定义为该芯片焊盘组ICPAD的后地址配置线DSA。可以理解的是，在级联的两个芯片IC中，上一级芯片IC对应的芯片焊盘组ICPAD的后地址配置线DSA，与下一级芯片IC对应的芯片焊盘组ICPAD的后地址配置线DSA为同一地址配置线DSA。
参见图4、图9、图14和图15，在本公开的一些实施方式中，发光基板的每个信号通道CH中，设置有多条用于向芯片加载不同驱动信号(非电源信号)的驱动走线，例如设置有用于加载不同驱动信号的第一驱动走线和第二驱动走线。每个信号通道CH中还设置有多个参考电源线GNDA。其中，同一信号通道CH中的各个参考电源线GNDA之间电连接，且第一驱动走线和第二驱动走线之间设置有至少一根参考电源线GNDA。这样，第一驱动走线和第二驱动走线之间可以通过参考电源线GNDA进行屏蔽，避免不同的驱动走线上所加载的不同的驱动信号之间的相互干扰，进而降低至少部分驱动走线上的噪音。
在一些示例中，第一驱动走线为时钟信号线CLKA；第二驱动走线为驱动数据线DataA或者地址配置线DSA。
举例而言，在本公开的一种实施方式中，第一驱动走线为时钟信号线CLKA；第二驱动走线为驱动数据线DataA。这样，本公开的发光基板通过在驱动数据线DataA和时钟信号线CLKA之间设置参考电源线GNDA作为屏蔽走线，可以减小或者消除驱动数据线DataA上加载的驱动数据信号Data对时钟信号线CLKA上加载的时钟信号CLK的干扰，克服了时钟信号CLK作为高频信号易被干扰的缺陷，进而使得芯片IC工作状态更稳定。不仅如此，在每个信号通道CH中，各个参考电源线GNDA之间相互电连接，这样可以使得各个参考电源线GNDA之间的电流可以相互流通，可以平抑单个参考电源线GNDA上的电流波动进而使得参考电源电压GND更稳定，降低参考电源电压GND噪音。另一方面，这可以使得信号通道CH内的参考电源线GNDA的整体阻抗降低，进一步提高信号通道CH内的参考电源电压GND的信号稳定性。
在本公开的一种实施方式中，同一信号通道CH中，各个参考电源线GNDA和参考电源焊盘GNDP之间通过参考电源连接线GNDL电连接。
在本公开的一种实施方式中，参见图7和图8，至少部分芯片IC对应的芯片焊盘组ICPAD设置于该芯片IC对应的控制区BB中。在该控制区BB中设置有参考电源连接线GNDL，该参考电源连接线GNDL与参考电源焊盘GNDP、各个参考电源线GNDA电连接。这样，可以使得信号通道CH中的参考电源电压GND呈网格化，进一步提高发光基板的稳定性。
在本公开的一些实施方式中，在一个信号通道CH中，多个参考电源线GNDA的尺寸并不完全相同。可以将具有较大宽度的参考电源线GNDA记为主参考电源线GNDA，将具有较小宽度、主要用于屏蔽时钟信号线CLKA、驱动数据线DataA等驱动走线的参考电源线GNDA记为辅助参考电源线GNDA。在本公开的一种实施方式中，主参考电源线GNDA的宽度大于芯片电源线VCCA的宽度，芯片电源线VCCA的宽度大于各个辅助参考电源线GNDA的宽度。在本公开的一种实施方式中，主参考电源线GNDA可以与灯区电源线VLEDA相邻设置。当然的，当信号通道CH中设置两根灯区电源线VLEDA，且设置一根主参考电源线GNDA时，主 参考电源线GNDA与其中一根灯区电源线VLEDA相邻设置；另一根灯区电源线VLEDA可以与辅助参考电源线GNDA相邻，也可以不与参考电源线GNDA相邻。
在本公开的一种实施方式中，主参考电源线GNDA可以与灯区AA交叠，且与至少部分芯片IC不交叠。
在本公开的一些实施方式中，参见图4，在一个信号通道CH中，沿预设方向H11，驱动走线包括依次设置的灯区电源线VLEDA、参考电源线GNDA、芯片电源线VCCA、地址配置线DSA、时钟信号线CLKA、参考电源线GNDA、驱动数据线DataA、参考电源线GNDA、灯区电源线VLEDA。其中，各个驱动走线在整体上沿列方向H2延伸。在该实施方式中，信号通道CH中两侧的两个参考电源线GNDA为主参考电源线GNDA，主参考电源线GNDA主要用于向芯片IC加载参考电源电压GND。两个主参考电源线GNDA之间的参考电源线GNDA为辅助参考电源线GNDA，辅助参考电源线GNDA与时钟信号线CLKA相邻设置，以屏蔽其他驱动走线上的信号对时钟信号线CLKA的串扰。参见图4，主参考电源线GNDA的宽度大于辅助参考电源线GNDA的宽度。在本公开的一种实施方式中，芯片焊盘组ICPAD设置于两个主参考电源线GNDA之间，以使得芯片焊盘组ICPAD在行方向上靠近信号通道的中心。
在本公开的另一种实施方式中，参见图14，在地址配置线DSA和时钟信号线CLKA之间，也可以额外设置辅助参考电源线GNDA，这样，时钟信号线CLKA夹设于两个辅助参考电源线GNDA之间，更不容易受到其他信号的串扰。
在本公开的一些实施方式中，参见图2、图4～图8，发光基板具有用于布设芯片焊盘组ICPAD的芯片区ICA，芯片焊盘组ICPAD布设于芯片区ICA内。在一个芯片焊盘组ICPAD中，相较于地址中继焊盘DOSP，地址配置焊盘DISP靠近芯片电源线VCCA设置。其中，芯片焊盘组ICPAD位于芯片电源线VCCA和地址配置线DSA之间。驱动金属层Cu1在芯片焊盘组ICPAD靠近芯片电源线VCCA的一侧设置有地址配置转接结构DSC，地址配置转接结构DSC与该芯片焊盘组ICPAD的前地址配置线DSA电连接。这样，该芯片焊盘组ICPAD的地址中继焊盘DOSP可以通 过地址中继连接线DOSL与该芯片焊盘组ICPAD的后地址配置线DSA电连接，该芯片焊盘组ICPAD的地址配置焊盘DISP可以通过地址配置连接线DISL与DAC电连接，进而与该芯片焊盘组ICPAD的前地址配置线DSA电连接。在本公开的一些实施方式中，参见图4，芯片电源线VCCA设置有芯片电源线避让缺口VCCAG。地址配置转接结构DSC部分设置于芯片电源线避让缺口VCCAG。如此，芯片电源线VCCA可以通过芯片电源线避让缺口VCCAG避让地址配置转接结构DSC，进而节省空间以增大驱动走线的宽度。
在本公开的一种实施方式中，参见图4，芯片电源线VCCA设置芯片电源线避让缺口VCCAG的部分为芯片电源线VCCA的避让段，芯片电源线VCCA不设置芯片电源线避让缺口VCCAG的部分为芯片电源线VCCA的布线段。由于芯片电源线避让缺口VCCAG的设置，芯片电源线VCCA的避让段的宽度小于芯片电源线VCCA的布线段的宽度。进一步地芯片电源线VCCA的避让段和布线段，远离芯片焊盘组ICPAD的边缘为同一边缘。换言之，芯片电源线VCCA可以通过设置芯片电源线避让缺口VCCAG的方式避让地址配置转接结构DSC，而无需通过弯折的方式避让地址配置转接结构DSC，进而避免弯折对各个驱动走线的影响。
在本公开的一些实施方式中，参见图5和图6，部分参考电源线GNDA设置有参考电源线避让缺口GNDAG，以避让发光元件焊盘组LEDPAD，例如主参考电源线GNDA设置有参考电源线避让缺口GNDAG。这样，可以避免发光元件焊盘组LEDPAD与参考电源线GNDA交叠，进而消除发光元件焊盘组LEDPAD与参考电源线GNDA之间短路的风险，提供发光基板的良率。
在本公开的一种实施方式中，部分灯区连接线LEDL布设于参考电源线避让缺口GNDAG，这样可以减小参考电源线GNDA与灯区连接线LEDL之间短路的风险，提高发光基板的良率。当然的，参见图4～图6，部分灯区连接线LEDL需要与参考电源线GNDA交叠，以使得灯区连接线LEDL穿过参考电源线GNDA的布线区域以与灯区电源线VLEDA通过过孔电连接。示例性地的，在灯区AA中，主参考电源线GNDA的两侧均内缩以形成作为参考电源线避让缺口GNDAG一部分的布线空间，该 布线空间沿列方向H2延伸；至少部分沿列方向H2延伸的灯区连接线LEDL布设于该布线空间内。
示例性地，参见图4～图6，主参考电源线GNDA可以包括在控制区BB中的控制段和位于控制区BB之间的连接段。其中，参考电源线避让缺口GNDAG设置于主参考电源线GNDA的控制段，其不仅设置有凹陷部分，而且在宽度上也小于主参考电源线GNDA的连接段。主参考电源线GNDA的控制段相较于主参考电源线GNDA的连接段所设置的凹陷部分和收缩部分，可以作为参考电源线避让缺口GNDAG。其中，沿列方向H2，灯区连接线LEDL在主参考电源线GNDA的连接段之间设置。
当然的，在本公开的其他实施方式中，主参考电源线GNDA也可以不设置参考电源线避让缺口，部分发光元件焊盘组LEDPAD、部分灯区连接线LEDL可以与参考电源线GNDA交叠。这样，避免参考电源线GNDA设置参考电源线避让缺口GNDAG而对阻抗的影响。
在本公开的一些实施方式中，参见图7～图8，布线金属层Cu2设置有参考电源连接线GNDL，参考电源连接线GNDL与各个参考电源线GNDA通过过孔HH连接。换言之，参考电源连接线GNDL可以设置于芯片焊盘组ICPAD靠近参考电源焊盘GNDP的一侧，且行方向H1的两端分别与主参考电源线GNDA电连接，中间部分通过过孔H与辅助参考电源线GNDA电连接，且与参考电源焊盘GNDP电连接。这样，参考电源连接线GNDL不仅使得主参考电源线GNDA和辅助参考电源线GNDA电连接，提高了参考电源线GNDA上信号的稳定性，而且可以有效的向芯片IC提供参考电源电压GND。
当然的，在本公开的其他实施方式中，芯片焊盘组ICPAD与驱动走线之间的相对位置还可以为其他方式。
举例而言，在本公开的另外一些实施方式中，参见图14，在一个信号通道CH中，驱动走线包括沿预设方向H11依次排列的灯区电源线VLEDA(图14中未示出)、主参考电源线GNDA、芯片电源线VCCA、地址配置线DSA、辅助参考电源线GNDA、时钟信号线CLKA、辅助参考电源线GNDA、驱动数据线DataA、地址配置线DSA、主参考电源线GNDA和灯区电源线VLEDA(图14中未示出)。其中，芯片焊盘组ICPAD的第一 列引脚设于中地址配置线DSA与时钟信号线CLKA之间，例如与这两个驱动走线之间的辅助参考电源线GNDA交叠；芯片焊盘组ICPAD的第二列引脚与时钟信号线CLKA交叠。在该实施方式中，位于两侧的两个地址配置线DSA可以通过位于布线金属层Cu2的地址配置转接结构DSC(图14中未示出)进行跨接连接，进而使得位于两侧的两个地址配置线DSA电连接为一个整体。
在一种示例中，参见图14，芯片电源线VCCA可以不设置芯片电源线避让缺口VCCAG以避让芯片焊盘组ICPAD或者其他驱动走线，进而保证芯片电源线VCCA上的压降较小。
在一种示例中，参见图14，芯片电源线VCCA的宽度小于主参考电源线GNDA的宽度，大于辅助参考电源线GNDA的宽度。地址配置线DSA、驱动数据线DataA、时钟信号线CLKA等驱动走线的宽度相同，且小于辅助参考电源线GNDA的宽度。
在一种示例中，参见图14，参考电源连接线GNDL可以与各个主参考电源线GNDA、各个辅助参考电源线GNDA和参考电源焊盘GNDP电连接。
再示例性地，在本公开的另外一些实施方式中，参见图15，在一个信号通道CH中，驱动走线包括沿预设方向H11依次排列的灯区电源线VLEDA(图15中未示出)、主参考电源线GNDA、芯片电源线VCCA、地址配置线DSA、时钟信号线CLKA、辅助参考电源线GNDA、驱动数据线DataA、地址配置转接结构DSC、主参考电源线GNDA、灯区电源线VLEDA(图15中未示出)。其中，辅助参考电源线GNDA的宽度不小于芯片焊盘组ICPAD的宽度。这样，芯片焊盘组ICPAD可以设置在辅助参考电源线GNDA上或者在辅助参考电源线GNDA断开所形成的避让空间内。
在一种示例中，参见图15，辅助参考电源线GNDA在芯片焊盘组ICPAD处断开以形成避让空间作为布设芯片焊盘组ICPAD的芯片区ICA，芯片焊盘组ICPAD设置于该芯片区ICA内。这样，地址配置线DSA、时钟信号线CLKA、驱动数据线DataA、地址配置转接结构DSC走线可以无需弯折以避让芯片焊盘组ICPAD。辅助参考电源线GNDA被避让空间分 割为多段。进一步地，辅助参考电源线GNDA靠近芯片焊盘组ICPAD的一端均与参考电源连接线GNDL电连接。这样，参考电源连接线GNDL包括第一参考电源连接线GNDL1和第二参考电源连接线GNDL2；第一参考电源连接线GNDL1和第二参考电源连接线GNDL2分别与靠近芯片焊盘组ICPAD的两个辅助参考电源线GNDA的端部连接，且均与两个主参考电源线GNDA连接。
在一种示例中，芯片电源线VCCA设置有芯片电源线避让缺口VCCAG；主参考电源线GNDA具有向芯片焊盘组ICPAD一侧延伸的参考电源线延伸部GNDE，部分参考电源线延伸部GNDE可以设置于芯片电源线避让缺口VCCAG中。这样，参考电源连接线GNDL可以与参考电源线延伸部GNDE通过过孔HH连接，且可以避让灯区连接线LEDL。
在一种示例中，部分或者全部芯片电源线避让缺口VCCAG可以断开以使得芯片电源线VCCA分为多段；相邻两段芯片电源线VCCA之间可以通过设置于布线金属层Cu2的芯片电源转接结构VCCBC电连接。
在一种示例中，芯片电源连接线VCCL与芯片电源转接结构VCCBC连接。
在一种示例中，芯片电源转接结构VCCBC包括并排的两个走线，以避免出现缺陷接地结构。
在一种示例中，芯片焊盘组ICPAD对应的前地址配置线DSA通过地址配置连接线DISL与地址配置焊盘DISP电连接。芯片焊盘组ICPAD对应的后地址配置线DSA通过一位于布线金属层Cu2的转接线与地址配置转接结构DSC电连接，地址配置转接结构DSC通过地址中继连接线DOSL与地址中继焊盘DOSP电连接。
在一种示例中，地址配置线DSA、CKLA、驱动数据线DataA、地址配置转接结构DSC宽度相同且小于辅助参考电源线GNDA。芯片电源线VCCA的宽度大于辅助参考电源线GNDA，且小于主参考电源线GNDA(图15中未示出主参考电源线GNDA的全部)。
在一种示例中，芯片电源线VCCA与主参考电源线GNDA之间设置有用于布设灯区连接线LEDL的间隙，以减小灯区连接线LEDL与主参考电源线GNDA的交叠，降低短路不良的风险。
在一些实施方式中，布线金属层Cu2还设置有多个降阻结构(例如图6和图7中的灯区电源降阻结构VLEDB、参考电源降阻结构GNDB、芯片电源降阻结构VCCB等)，任意一个降阻结构与其中一条驱动走线对应设置。其中，降阻结构通过过孔HH连接至对应的驱动走线上。可以理解的是，任意一个驱动走线，可以对应于一个或者多个降阻结构；多个降阻结构可以对应于同一驱动走线。这样，与降阻结构通过过孔连接的驱动走线相当于被并联了导电通路，使得该驱动走线的阻抗降低。这一方面可以减小驱动走线的阻抗，保证信号和电源在发光基板上具有较小的压降；另一方面，可以使得驱动走线的厚度减小或者宽度降低。
在本公开的一种实施方式中，可以通过磁控溅射的方法形成厚度较小的驱动金属层Cu1；由于布线金属层Cu2的降阻结构能够降低驱动走线的阻抗，因此对驱动金属层Cu1的厚度降低不会对发光基板的电学性能减低产生明显的负面影响，而且可以简化驱动金属层Cu1的制备工艺，降低发光基板的成本和厚度。在本公开的一种实施方式中，降阻结构在衬底基板BP上的正投影，位于对应的驱动走线的正投影内。
可选地，在降阻结构和对应的驱动走线之间，可以通过过孔连接，尤其是可以通过多个过孔HH连接。图16～图20中，以与主参考电源线GNDA对应的参考电源降阻结构GNDB为例，例举了降阻结构与对应的驱动走线之间的过孔HH的设置方式。可以理解的是，图16～图20中对过孔HH的分布方式的例举，仅仅为本公开的部分实施方式的示例。
在本公开的一种实施方式中，参见图16，降阻结构(图16中以参考电源降阻结构GNDB作为示例)上的过孔HH可以环绕降阻结构的边缘呈环形排列。当然的，当降阻结构宽度较小而无法呈环形时，也可以沿列方向H2排列。过孔HH的这种排列方式，一方面可以使得降阻结构与对应的驱动走线之间呈现分散且多点的连接，进而提高降阻结构和驱动走线之间电流的多样性和灵活性，使得降阻结构与对应的驱动走线之间具有较低的接触阻抗，减小了过孔接触阻抗带来的升温问题，进而提高发光基板的信赖性。在另一方面，在降阻结构和对应的驱动走线之间具有较小的接触面积，能够保证降阻结构和驱动走线之间的第一绝缘层OC1面积不会过分减小，进而避免第一绝缘层OC1面积减小而导致的容值增大。
当然的，在本公开的其他示例中，降阻结构与对应的驱动走线之间的过孔HH还按照其他的可行方式进行设置。在一种示例中，参见图17(用参考电源降阻结构GNDB来示例降阻结构)，过孔HH可以排列成多个过孔行，例如排列成位于降阻结构列方向H2的两端的两个过孔行；每个过孔行包括沿行方向H1延伸的多个过孔H。在另一种示例中，参见图18(用参考电源降阻结构GNDB来示例降阻结构)，过孔行中的各个过孔可以相互合并为一个过孔HH，使得该过孔HH呈沿行方向H1延伸的长条形。在另一种示例中，参见图19(用参考电源降阻结构GNDB来示例降阻结构)，环绕降阻结构边缘的各个过孔可以依次合并，进而形成一整个环形过孔HH。在另一种示例中，参见图20(用参考电源降阻结构GNDB来示例降阻结构)，环形过孔所环绕的第一绝缘层OC1部分也被去除，使得过孔HH呈一整个腔体结构，该腔体结构的边缘沿降阻结构的边缘设置；这样，位于布线金属层Cu2的降阻结构大面积的直接搭接与位于驱动金属层Cu1的驱动走线，例如搭接面积达到降阻结构面积的30％以上。
在本公开的一种实施方式中，在降阻结构和对应的驱动走线之间，过孔HH的尺寸可以在100～300微米之间。示例性地，在降阻结构和对应的驱动走线之间，过孔的尺寸为200微米。
在本公开的一种实施方式中，在降阻结构和对应的驱动走线之间，过孔HH的间距可以在800～1200微米之间。示例性地，在降阻结构和对应的驱动走线之间，过孔的间距可以为1000微米。
在本公开的一种实施方式中，在降阻结构和对应的驱动走线之间，过孔HH与降阻结构的边缘之间的距离，不小于10微米。
在本公开的一种实施方式中，在降阻结构和对应的驱动走线之间，过孔HH的形状可以为正方形或者圆形。当然的，过孔HH的形状也可以为其他可行的形状，例如矩形、六边形等。
在本公开的一种实施方式中，参见图4～图8，降阻结构包括与主参考电源线GNDA对应的参考电源降阻结构GNDB；参考电源降阻结构GNDB在衬底基板BP上的正投影位于对应的主参考电源线GNDA中。其中，参考电源降阻结构GNDB通过过孔与对应的参考电源线GNDA连接。在该实施方式中，位于参考电源线GNDA与参考电源降阻结构GNDB之间的 至少部分过孔可以环绕参考电源降阻结构GNDB的边缘设置，以高效的降低参考电源线GNDA的阻抗。当然的，在本公开的另一种实施方式中，位于参考电源线GNDA与参考电源降阻结构GNDB之间的过孔可以排列成两个过孔行，每个过孔行包括沿行方向H1排列的多个过孔。其中，两个过孔行可以分别设置于参考电源降阻结构GNDB在列方向H2上的两端。在本公开的另一种实施方式中，过孔行中的各个过孔可以依次连接而整体上呈沿行方向H1延伸的长条孔。
在本公开的一种实施方式中，参考电源线GNDA可以包括在控制区BB中的控制段和位于控制区BB之间的连接段。
在本公开的一种实施方式中，参考电源降阻结构GNDB可以包括与参考电源线GNDA的连接段交叠的参考电源降阻结构GNDB连接段和与参考电源线GNDA的控制段交叠的参考电源降阻结构GNDB控制段。参见图6和图7，参考电源降阻结构GNDB连接段和参考电源降阻结构GNDB控制段之间设置有灯区连接线LEDL。
在本公开的一种实施方式中，参考电源降阻结构GNDB控制段设置有暴露参考电源线GNDA的控制段的避让缺口，参考电源连接线GNDL在该避让缺口内通过过孔与参考电源线GNDA电连接。
在本公开的一种实施方式中，辅助参考电源线GNDA上可以不设置与之对应的参考电源降阻结构GNDB。
在本公开的一些实施方式中，参见图4～图8，降阻结构可以包括与灯区电源线VLEDA对应的灯区电源降阻结构VLEDB；所述灯区电源降阻结构VLEDB在衬底基板BP上的正投影位于对应的灯区电源线VLEDA内，且通过多个过孔HH与灯区电源线VLEDA电连接。在该实施方式中，位于灯区电源线VLEDA与灯区电源降阻结构VLEDB之间的至少部分过孔HH可以环绕灯区电源降阻结构VLEDB的边缘设置，以高效的降低灯区电源线VLEDA的阻抗。在本公开的一种实施方式中，在每个控制区BB，灯区电源线VLEDA与灯区电源降阻结构VLEDB之间还可以设置有一个或者多个不位于灯区电源降阻结构VLEDB边缘的过孔HH，以使得这些过孔与位于边缘的部分过孔形成过孔行，提高过孔密度进而降低灯区电源线VLEDA的阻抗。
当然的，在本公开的另一种实施方式中，位于灯区电源线VLEDA与灯区电源降阻结构VLEDB之间的过孔可以排列成两个过孔行，每个过孔行包括沿行方向H1排列的多个过孔。其中，两个过孔行可以分别设置于灯区电源降阻结构VLEDB在列方向H2上的两端。在本公开的另一种实施方式中，过孔行中的各个过孔可以依次连接而整体上呈沿行方向H1延伸的长条孔。
在本公开的一种实施方式中，在非扇出区，灯区电源降阻结构VLEDB可以与灯区电源线VLEDA完全重合，以使得灯区电源降阻结构VLEDB具有最大的布设面积，能够最大程度的减小灯区电源线VLEDA的阻抗。
在一些实施方式中，参见图4～图8，降阻结构可以包括芯片电源降阻结构VCCB；所述芯片电源降阻结构VCCB在衬底基板BP上的正投影位于芯片电源线VCCA内，且通过多个过孔与芯片电源线VCCA电连接。在本公开的一种实施方式中，芯片电源降阻结构VCCB可以与芯片电源线VCCA的避让段交叠，而与芯片电源线VCCA的非避让段不交叠。如此，相邻芯片电源降阻结构VCCB之间形成有避让空间，以利于时钟信号连接线CLKL、灯区连接线LEDL、地址配置连接线DISL、芯片电源连接线VCCL、参考电源连接线GNDL等位于布线金属层Cu2的连接走线的布设。
在本公开的一种实施方式中，参见图7，芯片电源降阻结构VCCB与芯片电源线VCCA之间通过沿列方向H2依次排列的多个过孔连接。
在本公开的一些实施方式中，器件层还可以设置有电容器，电容器的两个引脚分别与参考电源线GNDA和其他电源走线(参考电源线GNDA以外的其他电源走线)电连接，以使得电源走线的信号稳定，滤除电源走线上的噪音并解除电源走线与参考电源线GNDA之间的耦合，避免电源走线上的电压波动而导致降低发光基板的品质。
可选地，电容器可以设置于灯区AA以外，以减小对发光基板出光均一性的影响，并降低布线难度。
可选地，电容器在发光基板上可以较为均匀的分布，以利于更高效、更均匀的消除电压信号可能的波动，并使得对发光基板出光均一性的影响更均匀。
可选地，可以仅在部分电源走线上设置电容器，以避免在各个电源线 上设置电容器而导致电容器密度太大，进而避免电容器密度太大而影响发光基板出光的均一性。
在本公开的一种实施方式中，参见图3，在至少部分灯区电源线VLEDA与参考电源线GNDA之间，可以设置第一电容器Cst1，以使得灯区电源线VLEDA上的噪音被滤除，进而提高灯区电源线VLEDA上的灯区电源电压VLED的稳定性。
在一种示例中，布线金属层Cu2可以设置有第一电容器焊盘组，第一电容器焊盘组包括与灯区电源线VLEDA通过过孔连接的电容器第一电容器第一焊盘和用于主参考电源线GNDA通过过孔连接的第一电容器第二焊盘。电容器的两个引脚，分别与第一电容器第一焊盘、第一电容器第二焊盘电连接。
在一种示例中，部分灯区电源线VLEDA上可以连接电容器且其余灯区电源线VLEDA上可以不连接电容器，以避免电容器数量太多而影响发光基板的出光均一性。
在一种示例中，相邻两个信号通道CH的相邻两个灯区电源线VLEDA相互电连接以形成合并的灯区电源线VLEDA，例如合并为一条较宽的走线或者通过导电结构相互连接以形成镂空结构。任意一个合并的灯区电源线VLEDA与参考电源线GNDA之间，均连接有第一电容器。进一步地，每个合并的灯区电源线VLEDA上连接有3～5个第一电容器。
举例而言，在本公开的一种实施方式中，发光基板上灯区AA的列数为80列，灯区AA的行数为45行(远离绑定焊盘的一端，一个芯片IC可以驱动两个灯区AA)。第一电容器Cst1设置在驱动第偶数列或者第奇数列的灯区电源线VLEDA上。各个第一电容器Cst1排列成四行，各个第一电容器Cst1行与第11行(从靠近绑定焊盘的一端开始)、第13行、第33行和第39行灯区AA毗邻。
在本公开的一种实施方式中，参见图3，在至少部分芯片电源线VCCA与主参考电源线GNDA之间，可以设置第二电容器Cst2，以使得芯片电源线VCCA上的噪音被滤除，进而提高芯片电源线VCCA上的芯片电源电压VCC的稳定性。
在一种示例中，布线金属层Cu2可以设置有第二电容器焊盘组，第二 电容器焊盘组包括与芯片电源线VCCA通过过孔连接的第二电容器第一焊盘和与主参考电源线GNDA通过过孔连接的第二电容器第二焊盘。电容器的两个引脚，分别与第二电容器第一焊盘、第二电容器第二焊盘电连接。
在一种示例中，部分芯片电源线VCCA上可以连接第二电容器Cst2且其余芯片电源线VCCA上可以不连接第二电容器Cst2，以避免第二电容器Cst2数量太多而影响发光基板的出光均一性。
在一种示例中，每个芯片电源线VCCA上连接有第二电容器Cst2。进一步地，每个芯片电源线VCCA上，所连接的第二电容器Cst2的数量为2～4个。
举例而言，在本公开的一种实施方式中，发光基板上灯区AA的列数为80列，灯区AA的行数为45行(远离绑定焊盘的一端，一个芯片IC可以驱动两个灯区AA)。各个芯片电源线VCCA均连接有三个第二电容器Cst2。各个第二电容器Cst2排列成三行，且第二电容器Cst2行与第3行(从靠近绑定焊盘的一端开始)、第23行、第43行灯区AA毗邻。
在本公开的一种实施方式中，电子元件还可以包括用于测量温度的温度传感器和对温度传感器的电源线进行滤波的第三电容器。在驱动金属层Cu1，驱动走线包括用于向温度传感器加载温度传感器电源电压的温度传感器电源线。第三电容器的一个引脚与温度传感器电源线电连接，另一个引脚与主参考电源线GNDA电连接。
在一种示例中，每个温度传感器电源线均连接有第三电容器。
在一种示例中，每个温度传感器电源线上连接有2～4个第三电容器。
在一种示例中，布线金属层Cu2设置有第三电容器焊盘组、温度传感器第一走线、温度传感器第二走线和用于绑定温度传感器的温度传感器焊盘组。其中，温度传感器第一走线与温度传感器电源线电连接，且与温度传感器焊盘组电连接，以向温度传感器加载温度传感器电源电压。温度传感器第二走线与参考电源线GNDA电连接，且与温度传感器焊盘组电连接，以向温度传感器加载参考电源电压GND。第三电容器焊盘组包括第三电容器第一焊盘和第三电容器第二焊盘；第三电容器第一焊盘设置于温度传感器第一走线，第三电容器第二焊盘设置于温度传感器第二走线。第 三电容器的两个引脚，分别与第三电容器第一焊盘、第三电容器第二焊盘电连接。
举例而言，在本公开的一种实施方式中，发光基板上灯区AA的列数为80列，灯区AA的行数为45行(远离绑定焊盘的一端，一个芯片IC可以驱动两个灯区AA)。其中，发光基板至少设置有5列温度传感器电源线，5列温度传感器电源线分别与第8列、24列、40列、56列和72列灯区毗邻。每列温度传感器电源线包括三个温度传感器电源线，每个温度传感器电源线均连接有第三电容器。各个第三电容器排列成三行五列。沿列方向H2，各个第三电容器行与第6行(从靠近绑定焊盘的一端开始)、第22行、第38行灯区AA毗邻。沿行方向H1，各个第三电容器与第8列、24列、40列、56列和72列灯区毗邻。
在本公开的一些实施方式中，参见图9，主参考电源线GNDA可以相互合并以形成一个更大宽度的主参考电源线GNDA。这样，发光基板在一个信号通道CH中可以仅仅设置一个主参考电源线GNDA。在本公开的一种实施方式中，主参考电源线GNDA设置于芯片电源线VCCA远离驱动数据线DataA的一侧。在本公开的一种实施方式中，芯片焊盘组ICPAD位于主参考电源线GNDA的一侧而不与主参考电源线GNDA交叠，这使得芯片焊盘组ICPAD在行方向上偏离信号通道CH的中心。在本公开的一种实施方式中，芯片焊盘组ICPAD位于主参考电源线GNDA与辅助参考电源线GNDA之间。
在一种示例中，参见图9和图10，沿预设方向H11，一个信号通道CH中的驱动走线可以包括依次设置的灯区电源线VLEDA、主参考电源线GNDA、芯片电源线VCCA、地址配置线DSA、时钟信号线CLKA、辅助参考电源线GNDA、驱动数据线DataA、辅助参考电源线GNDA和灯区电源线VLEDA。在该示例中，时钟信号线CLKA与驱动数据线DataA之间设置有辅助参考电源线GNDA，进而避免驱动数据线DataA上的信号对时钟信号线CLKA进行串扰。
在一种示例中，参见图11～图13，布线金属层Cu2所设置的灯区电源电压V灯区连接线LEDL、发光元件焊盘组LEDPAD等，可以与灯区电源线VLEDA、参考电源线GNDA等交叠。
在一种示例中，布线金属层Cu2设置有与灯区电源线VLEDA交叠的灯区电源降阻结构VLEDB，灯区电源降阻结构VLEDB与灯区电源线VLEDA之间通过多个过孔连接，多个过孔至少部分沿灯区电源降阻结构VLEDB的边缘环绕设置。
在一种示例中，布线金属层Cu2设置有与主参考电源线GNDA部分交叠的参考电源降阻结构GNDB，参考电源降阻结构GNDB之间设置有灯区电源电压V灯区连接线LEDL、发光元件焊盘组LEDPAD等。其中，参考电源降阻结构GNDB与参考电源线GNDA之间通过多个过孔连接，多个过孔至少部分环绕参考电源降阻结构GNDB的边缘设置。
在一种示例中，芯片焊盘组ICPAD设置于芯片电源线VCCA和主参考电源线GNDA之间。其中，驱动金属层Cu1在主参考电源线GNDA和芯片焊盘组ICPAD之间设置有输出转接线OUTC，与第三输出焊盘OUT3P连接的灯区电源电压V灯区连接线LEDL通过输出转接线OUTC跨接。
在一种示例中，参见图13，时钟信号连接线CLKL与芯片电源线VCCA、地址配置线DSA、时钟信号线CLKA交叠，并与时钟信号焊盘CLKP、时钟信号线CLKA电连接。
驱动数据连接线DataL与芯片电源线VCCA、地址配置线DSA、时钟信号线CLKA、辅助参考电源线GNDA和驱动数据线DataA交叠，并与驱动数据焊盘DataP、驱动数据线DataA连接。
地址配置连接线DISL与输出转接线OUTC、主参考电源线GNDA、芯片电源线VCCA和前地址配置线DSA交叠，并与地址配置焊盘DISP、前地址配置线DSA连接。
地址中继连接线DOSL与芯片电源线VCCA、后地址配置线DSA交叠，并与芯片电源焊盘VCCP、后地址配置线DSA连接。
参考电源连接线GNDL包括第一参考电源连接线GNDL1和第二参考电源连接线GNDL2。主参考电源电压GND具有向靠近参考电源焊盘GNDP一侧延伸的参考电源线延伸部GNDE，第一参考电源连接线GNDL1与参考电源线延伸部GNDE、参考电源焊盘GNDP和靠近芯片电源线VCCA的辅助参考电源线GNDA连接，第二参考电源连接线GNDL2与两个辅助参考电源线GNDA连接。
在一种示例中，芯片电源线VCCA在靠近主参考电源线GNDA的一侧设置有避让芯片焊盘组ICPAD的芯片电源线避让缺口VCCAG。芯片焊盘组ICPAD设置于芯片电源线避让缺口VCCAG中。芯片电源线VCCA具有设置芯片电源线避让缺口VCCAG的避让段和未设置芯片电源线避让缺口VCCAG的非避让段，其中，芯片电源线VCCA的避让段的宽度小于芯片电源线VCCA的非避让段的宽度。
在一种示例中，布线金属层Cu2还设置有芯片电源降阻结构VCCB，芯片电源降阻结构VCCB与芯片电源线VCCA的非避让段通过过孔连接。
本公开的发光基板中，局部区域的走线排布可以根据实际走线需求进行微调，例如当位于驱动金属层Cu1的一个走线被驱动金属层Cu1的其他走线阻挡时，该走线可以通过布线金属层Cu2进行跨接。相应的，当位于布线金属层Cu2的一个走线被布线金属层Cu2的其他走线阻挡时，该走线可以通过驱动金属层Cu1进行跨接。在一些实施方式中，在PNL的扇出区，扇出走线设置于驱动金属层Cu1；当扇出走线被其他驱动走线阻挡时，该扇出走线可以局部的通过布线金属层Cu2进行跨接。在另外一些实施方式中，在扇出区，部分芯片IC需要通过较长的连接走线才能够与驱动走线和灯区连接，这些连接走线可能需要进行弯折以避让其他连接走线，也可以通过驱动金属层Cu1进行跨接以避让其他走线。
在本公开提供的显示装置中，发光基板可以直接显示画面而作为显示面板，也可以作为透射式液晶显示装置的背光源或者作为反射式液晶显示装置的前光源。该显示装置可以为手机屏幕、电脑显示器、电视机、电子广告牌或者其他用于显示的装置，本公开不做特殊的限定。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (25)

  1. 一种发光基板，包括沿行方向依次排列的多个信号通道；每个所述信号通道包括沿列方向排列的多个控制区；每个所述控制区包括由同一芯片控制的至少一个灯区；
    每个所述信号通道中，所述发光基板设置有第一驱动走线、第二驱动走线和多个参考电源线；所述第一驱动走线、所述第二驱动走线分别用于向所述芯片提供不同的驱动信号；所述参考电源线用于向所述芯片提供参考电源电压；其中，同一所述信号通道中的各个所述参考电源线之间电连接，且所述第一驱动走线和所述第二驱动走线之间设置有至少一根所述参考电源线。
  2. 根据权利要求1所述的发光基板，其中，所述第一驱动走线为向所述芯片提供时钟信号的时钟信号线；
    所述第二驱动走线为用于向所述芯片提供驱动数据信号的驱动数据线或者用于向所述芯片提供地址配置信号的地址配置线。
  3. 根据权利要求1所述的发光基板，其中，所述第二驱动走线为驱动数据线。
  4. 根据权利要求3所述的发光基板，其中，在所述信号通道中，所述发光基板还包括用于向所述灯区加载灯区电源电压的灯区电源线、用于向所述芯片加载芯片电源电压的芯片电源线、用于向所述芯片加载地址配置信号的地址配置线；
    沿所述行方向，所述灯区电源线、所述参考电源线、所述芯片电源线、所述地址配置线、所述时钟信号线、所述参考电源线、所述驱动数据线、所述参考电源线和所述灯区电源线依次设置。
  5. 根据权利要求4所述的发光基板，其中，在所述地址配置线和所述时钟信号线之间也设置有所述参考电源线。
  6. 根据权利要求3所述的发光基板，其中，所述发光基板具有用于与所述芯片绑定连接的芯片焊盘组，以及设置有参考电源连接线；
    其中，所述参考电源连接线与各个所述参考电源线通过过孔连接，且与所述芯片焊盘组电连接。
  7. 根据权利要求3所述的发光基板，其中，在所述信号通道中，所 述多个参考电源线包括位于所述信号通道两侧的两个主参考电源线和位于所述主参考电源线之间的辅助参考电源线；所述主参考电源线的宽度大于所述辅助参考电源线的宽度；
    所述主参考电源线与所述灯区交叠，且与至少部分所述芯片不交叠。
  8. 根据权利要求3所述的发光基板，其中，在所述信号通道中，所述多个参考电源线包括一个主参考电源线和至少一个辅助参考电源线；所述主参考电源线在各个所述参考电源线中宽度最大，且与所述驱动数据线、所述时钟信号线不相邻。
  9. 根据权利要求8所述的发光基板，其中，所述芯片位于所述主参考电源线和所述辅助参考电源线之间。
  10. 根据权利要求7或8所述的发光基板，其中，在所述信号通道中，所述发光基板还包括用于向所述灯区加载灯区电源电压的灯区电源线、用于向所述芯片加载芯片电源电压的芯片电源线；
    所述主参考电源线与所述灯区电源线相邻，且宽度大于所述芯片电源线；
    所述辅助参考电源线的宽度小于所述芯片电源线。
  11. 根据权利要求1～9任意一项所述的发光基板，其中，所述发光基板还包括用于向所述灯区加载灯区电源电压的灯区电源线、用于向所述芯片加载芯片电源电压的芯片电源线；在至少部分所述灯区电源线与所述参考电源线之间，设置有第一电容器；和/或者，在至少部分所述芯片电源线与所述参考电源线之间，设置有第二电容器。
  12. 根据权利要求11所述的发光基板，其中，在沿所述行方向相邻的两个所述信号通道中，其中一个所述信号通道中的一个灯区电源线与另一个所述信号通道中的一个所述灯区电源线相邻设置；该相邻设置的两个所述灯区电源线相互连接为合并的灯区电源线；所述合并的灯区电源线为两个所述信号通道中的灯区提供所述灯区电源电压；
    任意一个所述合并的灯区电源线与所述参考电源线之间，设置有3～5个所述第一电容器。
  13. 根据权利要求11所述的发光基板，其中，任意一个所述芯片电源线与所述参考电源线之间，设置有2～4个所述第二电容器。
  14. 根据权利要求1～9任意一项所述的发光基板，其中，所述发光基板设置有温度传感器，以及用于向所述温度传感器加载温度传感器电源电压的温度传感器电源线；
    任意一个所述温度传感器电源线与所述参考电源线之间，设置有第三电容器。
  15. 根据权利要求1～9任意一项所述的发光基板，其中，所述发光基板包括依次层叠设置的衬底基板、驱动金属层、第一绝缘层、布线金属层、第二绝缘层和器件层；
    所述驱动金属层设置有所述第一驱动走线、所述第二驱动走线和所述参考电源线；
    所述灯区包括电连接的多个发光元件；所述发光元件和所述芯片设置于所述器件层；
    所述布线金属层设置有用于绑定所述发光元件的发光元件焊盘组、用于绑定所述芯片的芯片焊盘组、用于与所述发光元件焊盘组和所述芯片焊盘组电连接的连接走线。
  16. 根据权利要求15所述的发光基板，其中，所述布线金属层设置有与至少部分所述参考电源线对应的参考电源降阻结构；所述参考电源降阻结构与对应的所述参考电源线通过过孔连接。
  17. 根据权利要求16所述的发光基板，其中，所述参考电源降阻结构在所述衬底基板上的正投影，位于对应的所述参考电源线在所述衬底基板的正投影的范围内。
  18. 根据权利要求16所述的发光基板，其中，所述参考电源降阻结构与对应的所述参考电源线之间的至少部分过孔，环绕所述参考电源降阻结构的边缘分布。
  19. 根据权利要求16所述的发光基板，其中，在所述信号通道中，多个所述参考电源线具有宽度最大的一个或者两个主参考电源线；所述参考电源降阻结构与所述主参考电源线连接。
  20. 根据权利要求15所述的发光基板，其中，所述驱动金属层设置有用于向所述灯区加载灯区电源电压的灯区电源线；所述布线金属层设置有与所述灯区电源线对应的灯区电源降阻结构；所述灯区电源线与对应的 所述灯区电源降阻结构之间通过过孔连接。
  21. 根据权利要求20所述的发光基板，其中，所述灯区电源降阻结构与对应的所述灯区电源线之间的至少部分过孔，环绕所述灯区电源降阻结构的边缘分布。
  22. 根据权利要求20所述的发光基板，其中，所述灯区电源降阻结构在所述衬底基板上的正投影，与对应的所述灯区电源线在所述衬底基板上的正投影重合。
  23. 根据权利要求15所述的发光基板，其中，所述驱动金属层设置有用于向所述芯片加载芯片电源电压的芯片电源线；所述布线金属层设置有与所述芯片电源线对应的芯片电源降阻结构；所述芯片电源降阻结构与对应的所述芯片电源线之间通过过孔连接。
  24. 根据权利要求23所述的发光基板，其中，所述芯片电源降阻结构与对应的所述芯片电源线之间的至少部分过孔，沿列方向直线排列。
  25. 一种显示装置，包括权利要求1～24任意一项所述的发光基板。
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CN103327667A (zh) * 2012-03-21 2013-09-25 马丁专业公司 带有两条屏蔽接地线的柔性led像素串
CN108630144A (zh) * 2018-06-19 2018-10-09 武汉天马微电子有限公司 显示面板和显示装置
CN109389907A (zh) * 2018-12-11 2019-02-26 厦门天马微电子有限公司 显示面板及显示装置
CN113130463A (zh) * 2021-04-16 2021-07-16 京东方科技集团股份有限公司 一种发光基板及其制备方法、显示装置

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CN103327667A (zh) * 2012-03-21 2013-09-25 马丁专业公司 带有两条屏蔽接地线的柔性led像素串
CN108630144A (zh) * 2018-06-19 2018-10-09 武汉天马微电子有限公司 显示面板和显示装置
CN109389907A (zh) * 2018-12-11 2019-02-26 厦门天马微电子有限公司 显示面板及显示装置
CN113130463A (zh) * 2021-04-16 2021-07-16 京东方科技集团股份有限公司 一种发光基板及其制备方法、显示装置

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