WO2022226976A1 - 一种显示基板和显示装置 - Google Patents

一种显示基板和显示装置 Download PDF

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Publication number
WO2022226976A1
WO2022226976A1 PCT/CN2021/091389 CN2021091389W WO2022226976A1 WO 2022226976 A1 WO2022226976 A1 WO 2022226976A1 CN 2021091389 W CN2021091389 W CN 2021091389W WO 2022226976 A1 WO2022226976 A1 WO 2022226976A1
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WIPO (PCT)
Prior art keywords
conductive
hollow portion
lead
orthographic projection
hollow
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PCT/CN2021/091389
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English (en)
French (fr)
Inventor
王杰
许邹明
吴信涛
田�健
刘纯建
雷杰
曾琴
张建英
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/769,032 priority Critical patent/US20240105894A1/en
Priority to CN202180000997.9A priority patent/CN115552618A/zh
Priority to DE112021004601.2T priority patent/DE112021004601T5/de
Priority to PCT/CN2021/091389 priority patent/WO2022226976A1/zh
Publication of WO2022226976A1 publication Critical patent/WO2022226976A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • Mini-Light-Emitting Diode is a new type of LED display technology derived from small-pitch LEDs, also known as sub-millimeter light-emitting diodes. Due to its good display effect, thin and light experience, high contrast ratio, long life and other advantages, it has an obvious trend of use in the high-end display field.
  • the mainstream driving method for Mini-LED is a quasi-active driving (AM, Active Matrix) type driving with the lamp group IC chip of the lamp group as the control source.
  • AM Active Matrix
  • This driving method can realize fine partition control, but this kind of driving
  • the backplane wiring of this method is complicated, and the winding length is greatly increased.
  • materials with lower resistivity such as Cu
  • the laying width should be increased as much as possible in the design. , which leads to the problem that the adhesion of the metal layer on the OC material of the insulating layer decreases during production, resulting in a large number of poor detachment of the product.
  • the purpose of the present disclosure is to provide a display substrate and a display device.
  • a display substrate comprising:
  • a first conductive layer located on one side of the base substrate, comprising a first conductive portion extending along a first direction;
  • a second conductive layer located on the side of the first conductive layer away from the base substrate;
  • an insulating layer located between the first conductive layer and the second conductive layer;
  • At least one of the first conductive portions includes a first hollow portion, the first hollow portion includes a plurality of slot structures arranged along a second direction, the slot structures extend along the first direction, and the first direction There is an included angle with the second direction.
  • the first conductive layer includes a plurality of first conductive parts with different sizes in the second direction, and the size of the first hollow part in the second direction is positively related to the size of the corresponding first conductive portion in the second direction, and the number of slot structures in the first hollow portion is positively related to the size of the corresponding first conductive portion in the second direction .
  • the ratio of the size of the first hollow portion in the second direction to the size of the corresponding first conductive portion in the second direction is 20 %-40%, wherein the dimension of the first hollow portion in the second direction is the sum of the dimensions of all the groove structures in the first hollow portion in the second direction.
  • a ratio of a size of the groove structure in the first hollow portion in the first direction to a size of the first conductive portion in the first direction 0.3%-0.5%.
  • the groove structures in the first hollow portion are arranged at equal intervals along the second direction.
  • the size of the first hollow portion in the first direction is positively correlated with the size of the corresponding first conductive portion in the first direction, and the first hollow portion
  • the number of parts is inversely related to the size of the corresponding first conductive part in the first direction.
  • the first hollow portions are arranged at equal intervals along the first direction.
  • the first conductive layer includes a plurality of first conductive parts having different sizes in the second direction;
  • the distance between two adjacent slot structures in the second direction is positively correlated with the size of the corresponding first conductive portion in the second direction.
  • the ratio of the distance between the two adjacent groove structures in the second direction and the size of the corresponding first conductive portion in the second direction is 8% -10%.
  • the second conductive layer includes a second conductive portion
  • the at least one first conductive portion further includes a second hollow portion, and the orthographic projection of at least part of the second conductive portion on the base substrate is located at the position of the second hollow portion on the base substrate. within the area enclosed by the orthographic projection.
  • an orthographic edge of a portion of the second conductive portion corresponding to the second hollowed-out portion and an orthographic edge of the second hollowed-out portion on the base substrate The orthographic edges have gaps.
  • the second conductive portion includes at least one of a pad, a first lead, a second lead, and a functional unit.
  • the second conductive part includes a plurality of groups of pads, and each group of the pads includes a plurality of sub-pads;
  • At least part of the orthographic projections of the sub-pads on the base substrate are located in the area enclosed by the orthographic projections of the second hollow portions, and the orthographic projections of the sub-pads are in a one-to-one correspondence. Each has a gap with the corresponding orthographic projection edge of the second hollow portion.
  • the distance between two adjacent first hollows is equal to the distance between two adjacent groups of pads.
  • the first conductive part includes at least two first hollow parts arranged in sequence along a first direction, and the at least two first hollow parts in the first direction
  • the ratio of the spacing to the spacing of the adjacent two groups of pads is between 0.8 and 2.
  • the second conductive portion includes a first lead extending along the first direction
  • At least part of the orthographic projection of the first lead on the base substrate overlaps with the area enclosed by the orthographic projection of the second hollow portion on the base substrate, and at least one side of the first lead There is a gap between the orthographic projection edge of the second hollow portion and the orthographic projection edge of the second hollow portion.
  • the second conductive portion includes a second lead extending along the second direction
  • At least part of the orthographic projection of the second lead on the base substrate overlaps with the area enclosed by the orthographic projection of the second hollow portion on the base substrate, and at least one side of the second lead There is a gap between the orthographic projection edge of the second hollow portion and the orthographic projection edge of the second hollow portion.
  • the second conductive portion includes several functional units
  • the orthographic projections of each of the functional units on the base substrate are located in the area enclosed by the orthographic projections of the second hollow portions, and the orthographic outer peripheries of the functional units are all corresponding to the corresponding orthographic projections.
  • the orthographic projection edge of the second hollow portion has a gap.
  • the second conductive portion includes a plurality of groups of pads and first leads corresponding to the plurality of groups of pads in a one-to-one correspondence, and the arrayed extension directions of the plurality of groups of pads, The extension direction of the first lead and the extension direction of the first hollow portion are both the first direction;
  • the orthographic projection of the one-to-one corresponding first leads on the base substrate is located in the orthographic projection area of the first hollow portion on the base substrate.
  • an orthographic projection of the plurality of groups of pads on the base substrate is located in an orthographic projection area of the first hollow portion on the base substrate.
  • the functional unit includes a test conductive portion electrically connected to the pad, the first lead or the second lead, and the test conductive portion is used to detect the pad, the first lead or the second lead. Electrical properties of the first lead or the second lead.
  • a buffer layer located between the base substrate and the first conductive layer
  • the insulating layer is filled into the first hollow portion, and the insulating layer is in contact with the buffer layer through the first hollow portion.
  • a display device including the above-mentioned display substrate.
  • FIG. 1 is a schematic cross-sectional structure diagram of a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure.
  • FIG. 4 is an enlarged view of the M region in FIG. 2 according to an embodiment of the present disclosure
  • FIG. 5 is a schematic cross-sectional view along the A-A direction in FIG. 4 according to an embodiment of the present disclosure
  • FIG. 6 is an enlarged view of the N region in FIG. 2 according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic cross-sectional view along the A-A direction in FIG. 6 according to an embodiment of the present disclosure
  • FIG. 8 is an enlarged view of another N region in FIG. 2 according to an embodiment of the present disclosure.
  • FIG. 9 is an enlarged view of another N region in FIG. 2 according to an embodiment of the present disclosure.
  • FIG. 10 is an enlarged view of another N region in FIG. 2 according to an embodiment of the present disclosure.
  • FIG. 11 is an enlarged view of yet another N region in FIG. 2 according to an embodiment of the present disclosure.
  • FIG. 12 is an enlarged view of region F in FIG. 2 provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic cross-sectional view along the direction A-A in FIG. 12 according to an embodiment of the present disclosure
  • FIG. 14 is an enlarged view of the G region in FIG. 2 according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic cross-sectional view of the direction A-A in FIG. 14 according to an embodiment of the present disclosure
  • FIG. 16 is a schematic structural diagram of a pad according to an embodiment of the present disclosure.
  • FIG. 17 is a cross-sectional view taken along the direction A-A in FIG. 16 , provided for an embodiment of the present disclosure
  • FIG. 18 is a schematic structural diagram of another pad according to an embodiment of the present disclosure.
  • FIG. 19 is a cross-sectional view along the A-A direction in FIG. 18 provided for an embodiment of the present disclosure
  • FIG. 20 is a schematic structural diagram of another pad according to an embodiment of the present disclosure.
  • FIG. 21 is a schematic structural diagram of another pad according to an embodiment of the present disclosure.
  • FIG. 22 is a schematic structural diagram of a first lead according to an embodiment of the present disclosure.
  • FIG. 23 is a schematic structural diagram of a second lead according to an embodiment of the present disclosure.
  • FIG. 24 is a schematic structural diagram of a test conductive portion according to an embodiment of the present disclosure.
  • FIG. 25 is a schematic structural diagram of a pad group and a first lead according to an embodiment of the present disclosure.
  • FIG. 26 is a cross-sectional view taken along the direction A-A in FIG. 27, provided for an embodiment of the present disclosure
  • FIG. 27 is a schematic structural diagram of still another pad group and a first lead according to an embodiment of the present disclosure.
  • FIG. 28 is a cross-sectional view taken along the direction A-A in FIG. 29, provided for an embodiment of the present disclosure
  • FIG. 29 is a schematic structural diagram of still another pad group and a first lead according to an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • a certain structure When a certain structure is "on” other structures, it may mean that a certain structure is integrally formed on other structures, or that a certain structure is “directly” arranged on other structures, or that a certain structure is “indirectly” arranged on another structure through another structure. other structures.
  • a display substrate provided by an embodiment of the present disclosure includes a base substrate 10 , a first conductive layer 2 , a second conductive layer 3 , a first insulating layer 4 , a second insulating layer 5 , a third The insulating layer 6 and the fourth insulating layer 7, as can be seen from FIG. 1, the first conductive layer 2 is provided on one side of the base substrate 10, and includes a first conductive portion 20 extending along the first direction, at least one first conductive portion 20.
  • the conductive portion 20 includes a first hollow portion 201 .
  • the first hollow portion 201 may include a plurality of slot structures arranged along a second direction. The slot structures extend along the first direction, and an angle exists between the first direction and the second direction.
  • the second conductive layer 3 is disposed on the side of the first conductive layer 2 away from the base substrate 10 , and includes a second conductive portion 30 .
  • a first insulating layer 4 and a second insulating layer 5 are arranged between the first conductive layer 2 and the second conductive layer 3, a third insulating layer 6 and a fourth insulating layer 7 are arranged above the second conductive layer 3, and the base substrate
  • a buffer layer 8 may be provided between 10 and the first conductive layer 2 .
  • the first insulating layer 4 and the third insulating layer 6 may be inorganic insulating materials, such as at least one of silicon oxide, silicon nitride, and silicon oxynitride; the second insulating layer 5 and the third insulating layer
  • the four insulating layers 7 may be organic insulating materials, such as organic resins. It can be understood that the specific material selection of the first insulating layer 4 , the second insulating layer 5 , the third insulating layer 6 and the fourth insulating layer 7 is not limited to this.
  • the depth of the groove structure perpendicular to the plane where the base substrate 10 is located is substantially equal to the thickness of the first conductive layer 2 or the first conductive portion 20 perpendicular to the plane where the base substrate 10 is located.
  • the hollow slit of the first conductive part 20 is substantially equal to the thickness of the first conductive layer 2 or the first conductive portion 20 perpendicular to the plane where the base substrate 10 is located.
  • the first direction is the direction perpendicular to the paper surface
  • the second direction is the horizontal direction parallel to the paper surface, that is, the angle between the first direction and the second direction is 90°, that is, the first direction and the second direction are 90°.
  • the two directions are vertical.
  • the angle between the first direction and the second direction is not limited to 90°, and is not specifically limited in the embodiment of the present disclosure.
  • the first conductive layer includes a first conductive portion extending along the first direction
  • at least one first conductive portion includes a first hollow portion
  • the first hollow portion includes a plurality of grooves arranged along the second direction structure
  • the groove structure extends along the first direction, so that the occupied area of the first conductive part and the base substrate and the first conductive part and the insulating layer can be reduced by the groove structure, and the first conductive part and the base substrate and the first conductive part can be enhanced.
  • the adhesion between a conductive part and the insulating layer can further reduce the defect rate of the product.
  • the first conductive layer 2 is usually used for arranging various signal lines, that is, the first conductive portion 20 can be various signal lines, such as a common voltage line GND, a driving voltage line VLED, a source power line PWR, a source address line DI, and the like.
  • the thickness of the first conductive layer 2 is about 1.5-7 ⁇ m, and the material thereof may include copper.
  • a stacked material such as MoNb/Cu/MoNb may be formed by sputtering.
  • the side material is MoNb, and the thickness is about It is mainly used to improve the adhesion between the film layer and the substrate.
  • the intermediate layer material of the stack is Cu, which is the preferred material for the electrical signal transmission channel.
  • the material on the side away from the substrate is MoNb, with a thickness of about It can be used to protect the intermediate layer and prevent the surface of the intermediate layer with low resistivity from being exposed and oxidized.
  • the first conductive layer can also be formed by electroplating. Specifically, MoNiTi can be used to form a seed layer to improve the nucleation density of metal grains in the subsequent electroplating process, and then copper with low resistivity can be produced by electroplating.
  • the anti-oxidation layer is made, and the material can be MoNiTi.
  • the second conductive layer 3 is usually used for setting pads and connecting leads.
  • the film thickness of the second conductive layer is about about.
  • the second conductive layer 3 in the embodiment of the present disclosure may include a second conductive part 30 , and the second conductive part 30 may be a pad 301 for binding various electrical components, for example, for mounting light Pads 3011 for components, and/or pads 3012 for mounting functional components such as driver chips or sensors; the second conductive portion 30 includes a lead with a connection function, that is, the second conductive portion 30 may also include wires along the first direction.
  • the extended first lead 302 and the second lead 303 extended in the second direction are divided.
  • the pad 301 is the part of the second conductive part 30 to be electrically connected to electronic components (such as light-emitting devices, driving circuits, sensors, etc.), and the surface of the side away from the substrate needs to be partially exposed before it is not connected to the electronic components. .
  • the surface on the side away from the base substrate is covered with an insulating material layer to ensure the reliability and stability of the electrical path.
  • an anti-oxidation material layer can be provided only on the exposed surface area of the pad 301, that is, the solder pad 301 is exposed to the air.
  • the surface of the pad area will have one more layer structure than the area where the first lead 302 and the second lead 303 are located; or the second conductive part 30 is integrally arranged as a laminated structure of at least two layers, which is far from the film of the base substrate 10
  • the layer material is an anti-oxidation metal or alloy material, specifically, it can be composed of a stacked structure such as MoNb/Cu/CuNi.
  • the underlying material in the stack, MoNb is mainly used to improve adhesion.
  • the intermediate layer Cu in the stack is due to The low resistivity is mainly used to transmit electrical signals, and the top layer of CuNi in the stack can not only prevent oxidation of the intermediate layer, but also ensure the firmness of the connection with the electronic components.
  • the first conductive layer 2 may include a plurality of first conductive parts 20 having different sizes in the second direction, the size of the first hollow part 201 in the second direction and the corresponding first conductive parts
  • the size of the portion 20 in the second direction is positively correlated, and the number of groove structures in the first conductive portion 20 is positively correlated with the size of the corresponding first conductive portion 20 in the second direction.
  • the first conductive layer 2 includes first conductive parts with different width sizes in the second direction, such as 20-1 and 20-2, and the size of the first conductive part 20-1 in the second direction is larger than The size of the first conductive portion 20-2 in the second direction, as can be seen from FIG. 1, the size of the first hollow portion 201 corresponding to the first conductive portion 20-1 in the second direction is larger than the size of the first conductive portion 20-1 in the second direction. The size of the first hollow portion 201 corresponding to the portion 20-2 in the second direction, and the number of groove structures in the first hollow portion 201 corresponding to the first conductive portion 20-1 is larger than that of the first conductive portion 20-2. The corresponding number of groove structures in the first hollow portion 201 .
  • the dimension of the first hollow portion 201 in the second direction is the sum of the dimensions of all the groove structures in the first hollow portion 201 in the second direction.
  • the ratio of the size of the first hollow portion 201 in the second direction to the size of the corresponding first conductive portion 20 in the second direction may be set between 20% and 40% according to actual needs. .
  • the dimension of the first hollow portion 201 in the second direction is the sum of the dimensions of all the groove structures in the first hollow portion in the second direction.
  • the size of the groove structure in the first hollow portion 201 in the first direction is positively related to the size of the corresponding first conductive portion 20 in the first direction.
  • the first hollow portion 201 can be
  • the ratio of the size of the groove structure in the first direction to the size of the first conductive portion 20 in the first direction is set between 0.3% and 0.5%.
  • the size of the first hollow part is set to be positively correlated with the size of the first conductive part, and the first hollow part of different sizes can be set according to the first conductive part of different sizes, so that the first conductive part and the substrate can be better strengthened.
  • the adhesion of the substrate and the adhesion between the first conductive part and the insulating layer are better enhanced.
  • the arrangement of the groove structures in the first hollow portion 201 in the second direction may be equidistant arrangement.
  • the first hollow portions 201 may be arranged at equal intervals along the first direction.
  • the groove structures in the first hollow part are arranged at equal intervals, and/or the plurality of first hollow parts in the first conductive part are arranged at equal intervals, which can make the adhesion of each position of the first conductive part uniform and improve the product yield. .
  • the size of the first hollow portion 201 in the first direction is positively related to the size of the corresponding first conductive portion 20 in the first direction, and the number of the first hollow portion 201 is directly related to the corresponding first hollow portion 201.
  • the size of a conductive portion 20 in the first direction is negatively correlated.
  • the number of the first hollow parts can be set so that the corresponding first conductive parts are The size in the first direction is negatively correlated.
  • the size of the first hollow portion in the first direction is set to be positively correlated with the size of the first conductive portion in the first direction, and the number of the first hollow portion is set to be related to the size of the first conductive portion in the first direction.
  • the size is negatively correlated, which can better enhance the adhesion between the first conductive portion and the base substrate, and better enhance the adhesion between the first conductive portion and the insulating layer.
  • the first conductive layer includes a plurality of first conductive parts with different sizes in the second direction.
  • the size of the first conductive parts 20 - 1 in the second direction is larger than that of the first conductive parts 20-2 Size in the second direction, the larger the size of the first conductive part in the second direction, the larger the spacing between the groove structures in the first hollow part can be set, and the adjacent two first hollow parts can be set.
  • the spacing in the first direction can also be set to be larger.
  • the spacing of the first hollow parts 201 in the first direction may be equal to the spacing of the adjacent two groups of pads in the first direction. In another embodiment, the first hollow parts 201 The ratio of the spacing in the first direction to the spacing of the adjacent two groups of pads in the first direction may be in the range of 0.8-2.
  • a group of pads in the embodiment of the present disclosure refers to a plurality of pads located in one light-emitting unit EU, and may specifically include pads for soldering light-emitting devices and pads for soldering driver chips; the adjacent two groups of pads are in The spacing in the first direction refers to the distance between two pads located at the same relative position in the two light-emitting units EU arranged adjacently in the first direction, respectively.
  • a light-emitting unit 3011 includes four light-emitting devices L connected in series.
  • the light-emitting device electrically connected to the driving voltage line VLED is used as the starting point of the series connection of the four light-emitting devices, and the light-emitting device electrically connected to the driving chip is used as the light-emitting device.
  • the end point of the series connection of 4 light-emitting devices. 4 light-emitting devices are driven by one driver chip.
  • the number of light-emitting devices L in each light-emitting unit EU is not limited, and may be any number such as 5, 6, 7, 8, etc., but not limited to 4 ;
  • the connection relationship of the light-emitting devices L in each light-emitting unit EU is not limited to series connection, but may also be connected in parallel or in a combination of series and parallel.
  • the light-emitting device L may be Mini LED, MicroLED, OLED, QLED or any other type of light-emitting device.
  • D1 is the spacing of the first hollow parts on the first conductive part 20-1 in the first direction
  • D3 is the distance of the first hollow parts on the first conductive part 20-2 in the first direction
  • the distance, D2 is the distance between the adjacent two groups of pads in the first direction.
  • the distance between the first hollow parts in the first direction is the distance in the first direction between two groove structures with the same relative positions in the two first hollow parts.
  • the distance between the two groups of pads in the first direction is the distance between the sides of the two groups of solder pads on which the driver chip is soldered and facing the same direction in the first direction.
  • the second conductive portion 30 Due to the limitation of substrate size, process, etc., when the second conductive portion 30 is fabricated, it is often unavoidable to overlap with the first conductive portion 20.
  • the overlapping area of the two is a region with weak performance, which is prone to short circuit or open circuit, resulting in failure. or affect reliability.
  • the orthographic projection of the pad on the base substrate overlaps with the orthographic projection of the signal line on the base substrate, when the electronic components are bonded and connected to the pad, for example, when the LED chip is soldered by reflow soldering technology, due to The instantaneous temperature of the reflow soldering process is as high as 260 to 265 °C, and an insulating layer is provided between the pad and the signal line, and this temperature range easily exceeds the temperature resistance value of the insulating layer, resulting in damage to the insulating layer, so that the pad and the signal are damaged. The line is shorted.
  • particles such as dust and foreign matter are inevitably generated in the thin film process.
  • the particles exist in the overlapping area of the lead and the signal line, it is easy to cause the lead and the signal line to conduct erratically, affecting the reliability of the product.
  • the pin-pin test method to test the current or voltage of the upper-layer leads, it is easy to penetrate the insulating layer and tie the signal lines below, resulting in inaccurate testing or reduced accuracy.
  • the first conductive part 20 is usually set thicker and wider, so that the first conductive part 20 can have a lower resistance, so as to provide a relatively low resistance.
  • the second conductive portion 30 is usually set narrower and shorter, and exists as a structure such as a lead wire and a pad. Therefore, there is a certain potential difference between the two. Since the insulating layer between the two conductive parts is in a semi-solid and semi-liquid state before curing in the glass-based film manufacturing process, the water vapor introduced during the process may remain in the insulating layer.
  • the line width ratio of the first conductive part 20 and the second conductive part 30 is about 20 to 30; for large size products, the line widths of the first conductive part 20 and the second conductive part 30
  • the width ratio can be as high as 100 times or even more, so the second conductive portion 30 and the first conductive portion 20 must overlap.
  • the first hollow portion 201 can be provided at the overlapping position of the first conductive portion 20 and the second conductive portion 30, because the first hollow portion 201 includes a groove
  • the existence of the slot structure can reduce the overlapping area of the first conductive part 20 and the second conductive part 30 , thereby reducing the probability of a short circuit between the first conductive part 20 and the second conductive part 30 .
  • the first hollow portion 201 may include a first groove structure 2010 (2010-1 and 2010-2) and a second groove structure 2011.
  • the first groove structure 2010 (2010-1 and 2010-2) ) on the base substrate 10 and the orthographic projection of the second conductive portion 30 (second lead 303 ) on the base substrate 10 at least partially overlap, and the orthographic projection of the second groove structure 2011 on the base substrate 10 is the same as
  • the orthographic projections of the second conductive portions 30 on the base substrate 10 do not overlap each other.
  • the first groove structure 2010 is disposed in the first conductive part 20 and at least partially overlaps with the second conductive part 30 , so the first groove structure 2010 can reduce the overlapping area of the first conductive part and the buffer layer, and reduce the first
  • the overlapping area of the conductive part and the insulating layer can enhance the adhesion between the first conductive part and the buffer layer, and while enhancing the adhesion between the first conductive part and the insulating layer, it can also reduce the first conductive part 20 and the second conductive part.
  • the probability of occurrence of a short circuit between the parts 30 can be reduced, so that the product defect rate can be reduced.
  • the orthographic projection of the first groove structure 2010 on the base substrate 10 may partially fall within the orthographic projection range of the second conductive portion 30 on the base substrate 10 , and may also entirely fall within the range of the orthographic projection of the second conductive portion 30 on the base substrate 10 . within the orthographic projection range. As shown in FIG. 2 , the first groove structure 2010-1 partially falls within the orthographic projection range of the second lead 303 on the base substrate, and the first groove structure 2010-2 all falls into the first lead 302 on the base substrate within the orthographic projection range.
  • the size of the first slot structure in the first direction may be larger than that of the second lead in the first direction size, but it needs to ensure that the first slot structure will not interrupt the signal transmission of the first conductive part;
  • the size of the second groove structure in the first direction can be between 300 ⁇ m-500 ⁇ m, and the second groove structure in the second direction The size is between 100 ⁇ m-300 ⁇ m.
  • FIG. 4 it is an enlarged view of the M area in FIG. 2 .
  • the orthographic portion of the first groove structure 2010 on the base substrate 10 falls within the range of the orthographic projection of the second lead 303 on the base substrate 10 , and the first groove structure 2010 in the first direction
  • the size is larger than the size of the second lead 303 in the first direction.
  • FIG. 5 it is a schematic cross-sectional view along the A-A direction in FIG. 4 .
  • FIG. 6 it is an enlarged view of the N region in FIG. 2 .
  • the orthographic portion of the first groove structure 2010 on the base substrate falls within the range of the orthographic projection of the first lead 302 on the base substrate 10 , and the size of the first groove structure 2010 in the second direction is smaller than The dimension of the first lead 302 in the second direction.
  • the dotted line part in FIG. 6 is the part of the first groove structure 2010 that is blocked by the second lead 302 .
  • FIG. 7 it is a schematic cross-sectional view along the A-A direction in FIG. 6 .
  • FIG. 8 it is an enlarged view of the N region in FIG. 2 .
  • the orthographic portion of the first groove structure 2010 on the base substrate falls within the range of the orthographic projection of the first lead 302 on the base substrate 10 , and the size of the first groove structure in the second direction is larger than that of the first lead 302 in the second direction.
  • the dimension of a lead 302 in the second direction is larger.
  • the dotted line part in FIG. 8 is the part of the first groove structure 2010 that is blocked by the second lead 302 .
  • FIG. 9 it is an enlarged view of the N region in FIG. 2 .
  • the orthographic portion of the first groove structure 2010 on the base substrate falls within the range of the orthographic projection of the first lead 302 on the base substrate 10 , and the size of the first groove structure 2010 in the second direction is larger than The dimension of the first lead 302 in the second direction.
  • dotted line portion in FIG. 9 is the portion of the first groove structure 2010 that is blocked by the second lead 302 .
  • FIG. 10 it is an enlarged view of the N region in FIG. 2 .
  • the orthographic projection of the first groove structure 2010 on the base substrate all falls within the range of the orthographic projection of the first lead 302 on the base substrate 10 , and the size of the first groove structure 2010 in the second direction is smaller than The dimension of the first lead 302 in the second direction.
  • FIG. 11 an enlarged view of the N region in FIG. 2 .
  • the orthographic projection of the first groove structure 2010 on the base substrate all falls within the range of the orthographic projection of the second lead 303 on the base substrate 10 , and the size of the first groove structure 2010 in the first direction is smaller than The size of the second lead 303 in the second direction.
  • the first conductive layer 2 may include a plurality of first conductive parts 20 with different sizes in the second direction. If the first conductive parts 20 and the second conductive parts 30 do not overlap each other, the first conductive parts 20
  • the distance between the two adjacent slot structures in the hollow portion 201 in the second direction is positively related to the size of the corresponding first conductive portion in the second direction. Specifically, the distance between the two adjacent slot structures in the second direction is The ratio of the spacing to the size of the corresponding first conductive portion 20 in the second direction may be between 8% and 10%, for example, 100 ⁇ m to 200 ⁇ m.
  • the first conductive layer 2 includes two first conductive parts with different sizes in the second direction, 20-1 and 20-2, wherein the size of 20-1 in the second direction Greater than the dimension of 20-2 in the second direction, the spacing between the groove structures 2011-1 in the first hollow portion 201-1 in 20-1 is greater than that in the first hollow portion 201-2 in 20-2 Spacing between slot structures 2011-2.
  • FIG. 13 it is a schematic cross-sectional view along the A-A direction in FIG. 12 .
  • the first conductive layer 2 includes a plurality of first conductive parts 20 with different sizes in the second direction, and the first conductive parts 20 and the second conductive parts 30 partially overlap, the first hollow in the first conductive part 20
  • the spacing of the groove structures in the second direction is positively related to the size of the corresponding first conductive part 20 in the second direction. Specifically, the spacing of two adjacent groove structures in the second direction is the corresponding The ratio of the size of the first conductive portion 20 in the second direction can be between 0-8%.
  • the size of the substrate is 1850mm*1500mm
  • the spacing of the groove structure in the second direction can be between 5mm and 10mm. .
  • the first conductive portion 20 may also include a second hollow portion 202 .
  • the second hollow portion 202 includes a third groove structure 2021 .
  • the groove structure 2021 extends along the second direction, and at least part of the orthographic projection of the second conductive portion 30 on the base substrate is located in an area enclosed by the orthographic projection of the second hollow portion 202 on the base substrate. That is to say, in the thickness direction of the display substrate, the second conductive portion 30 and the first conductive portion 20 do not overlap at least in part, so the non-overlapping place can avoid the occurrence of static electricity, process technology, testing and other reasons between the two. Short circuit, thereby improving product performance stability. Of course, in a completely ideal situation, if all the second conductive parts 30 and the first conductive parts 20 do not overlap, short circuits can be completely avoided.
  • overlap when describing "overlap" between two structures, it is meant that the orthographic projection of one of the structures on the base substrate at least partially overlaps the orthographic projection of the other structure on the base substrate.
  • the second hollow portion 202 may include one third groove structure, or may include a plurality of third groove structures, wherein, if the second hollow portion 202 includes a third groove structure 2021, because the third groove The structure 2021 extends along the second direction, so the second hollow portion 202 also extends along the second direction; if the second hollow portion 202 includes a plurality of third groove structures 2021, the plurality of third groove structures 2021 can be along the first direction
  • the arrangement, that is, the second hollow portion 202 extends along the first direction, and the plurality of third groove structures 2021 can also be arranged along the second direction, that is, the second hollow portion 202 extends along the second direction.
  • FIG. 14 it is an enlarged view of the G area in FIG. 2 .
  • the first conductive portion 20 includes a second hollow portion 202.
  • the second hollow portion 202 includes three third groove structures 2021 extending along the second direction and arranged along the second direction.
  • the orthographic projections of the third groove structures 2021 are all falls within the orthographic projection of the second lead 303 .
  • FIG. 15 it is a schematic cross-sectional view along the direction A-A in FIG. 14 .
  • the second hollow portion 202 can enhance the adhesion between the first conductive layer and the film layer, and on the other hand, it can also reduce the probability of a short circuit between the first conductive portion 20 and the second conductive portion 30 .
  • At least part of the orthographic projection of the second conductive portion 30 on the base substrate 10 is located in an area enclosed by the orthographic projection of the second hollow portion 202 on the base substrate 10 .
  • the second hollowed-out portion 202 is to hollow out the part of the overlapping area of the first conductive portion 20 and the second conductive portion 30 , so as to prevent the first conductive portion 20 and the second conductive portion 30 from being affected by static electricity, process technology, and testing in the overlapping area. Short circuit occurs due to other reasons, so as to avoid affecting the stability of product performance.
  • a certain gap may be set between the orthographic projection edge of the portion of the second conductive portion 30 corresponding to the second hollow portion 202 and the orthographic projection edge of the second hollow portion 202 on the base substrate 10 , so that the second conductive portion 30 A certain distance is reserved from the edge of the first conductive portion 20 to further reduce the possibility of a short circuit between the two.
  • the second conductive part 30 may include at least one of a pad 301 , a first lead 302 , a second lead 303 , and a functional unit (test conductive part 304 ).
  • the second conductive portion 30 includes multiple groups of pads 301 , each group of pads includes a plurality of sub-pads, and at least some of the sub-pads have their orthographic projections on the base substrate 10 located one-to-one in each In the area enclosed by the orthographic projection of the second hollow portion 202 , and the orthographic projection periphery of each sub-pad has a gap with the orthographic projection of the corresponding second hollow portion.
  • the pad 301 may be a conductive pattern used to complete electrical bonding with electronic components, and the electronic components include light-emitting diodes, sensors, driving chips, and the like.
  • the pad 301 includes two sub-pads, one is the sub-pad P and the other is the sub-pad N.
  • the first conductive portion 20 is the common voltage line GND, and the pads of the light emitting diodes overlap with the common voltage line GND in the thickness direction of the display substrate.
  • the orthographic projection of the sub-pad P on the base substrate 10 is located in the area enclosed by the orthographic projection of one of the third groove structures 2021 in the second hollow portion 202 , and the sub-pad P and the orthographic projection edge of the third slot structure 2021 has a gap.
  • the orthographic projection of the sub-pad N on the base substrate 10 is located in the area enclosed by the orthographic projection of another third groove structure 2021 in the second hollow portion 202 , and the orthographic projection of the sub-pad N There is a gap between the projected peripheral edge and the orthographic projected edge of the third groove structure 2021 .
  • the two groove structures are separated by the first conductive portion 20 that is not hollowed out, so that each groove structure corresponds to a respective sub-pad.
  • FIG. 17 it is a cross-sectional view taken along the line A-A in FIG. 16 .
  • the first conductive portion 20 is hollowed out in the area facing the sub-pad P and the sub-pad N, so that the sub-pad P, the sub-pad N and the lower first conductive portion 20 no longer overlap, thereby avoiding soldering.
  • a short circuit occurs between the disk and the first conductive portion 20 due to welding, die bonding and other reasons.
  • the third groove structures 2021 corresponding to the sub-pads of the same group of pads may be connected to each other.
  • the two third groove structures 2021 are connected to each other to form a groove structure, that is to say, the orthographic projections of the sub-pad P and the sub-pad N are located in the area enclosed by the orthographic projection of the same large groove structure Inside.
  • This structure can not only avoid the short circuit between the sub-pad P, the sub-pad N and the first conductive part 20 , but also reduces the process difficulty of hollowing out the first conductive part 20 .
  • FIG. 19 it is a cross-sectional view taken along the line A-A in FIG. 18 .
  • the shapes of the sub-pads and the third groove structure 2021 may be the same, and both are substantially rectangular.
  • the pad includes four sub-pads, namely the first input pad Di, the second input pad Pwr, the output pad Out and the common voltage pad Gnd.
  • the above-mentioned first input pad Di is configured to receive a first input signal, such as an address signal, for gating a driver chip of a corresponding address.
  • the first input signal may be an 8-bit address signal from the source address line DI, and the address to be transmitted may be obtained by parsing the address signal.
  • the second input pad Pwr is configured to receive a second input signal, eg, a power line carrier communication signal from the source power line PWR.
  • the second input signal not only provides power for the driver chip, but also transmits communication data to the driver chip.
  • the communication data can be used to control the luminous duration of the corresponding light-emitting unit, thereby controlling its visual luminous brightness.
  • the output pad Out is configured to output a driving signal.
  • the driving signal may be a driving voltage from the driving voltage line VLED for driving the light-emitting element to emit light.
  • the common voltage pad Gnd is configured to receive a common voltage signal, eg, a ground signal from the common voltage line GND.
  • the first conductive portion 20 is the common voltage line GND, and the pads of the driving chip overlap with the common voltage line GND in the thickness direction of the display substrate.
  • the first conductive portion 20 includes four second hollow portions 202 ; in the thickness direction of the substrate, the orthographic projection of the first input pad Di on the base substrate 10 is located in the area surrounded by the orthographic projection of the first second hollow portion 202 . area, and there is a gap between the orthographic peripheral edge of the first input pad Di and the orthographic edge of the second hollow portion 202 .
  • the orthographic projection of the second input pad Pwr on the base substrate 10 is located in the area enclosed by the orthographic projection of the second second hollow portion 202 , and the orthographic outer peripheral edge of the second input pad Pwr and the second hollow
  • the orthographic edge of portion 202 has a gap.
  • the orthographic projection of the output pad Out on the base substrate 10 is located in the area surrounded by the orthographic projection of the third second hollow portion 202 , and the orthographic outer peripheral edge of the output pad Out is in line with the orthographic projection of the second hollow portion 202 .
  • the projected edges have gaps.
  • the orthographic projection of the common voltage pad Gnd on the base substrate 10 is located in the area enclosed by the orthographic projection of the fourth second hollow portion 202 .
  • the orthographic edges have gaps.
  • the four second hollow parts 202 are separated by the first conductive parts 20 that are not hollowed out, so that each second hollow part 202 corresponds to a respective sub-pad.
  • the area where the first conductive portion 20 is facing the four sub-pads is hollowed out, so that the four sub-pads and the first conductive portion 20 below no longer overlap, thereby avoiding the short circuit between the pad and the first conductive portion 20 . question.
  • the second hollow portions 202 corresponding to the sub-pads of the same group of pads can be communicated with each other, thereby reducing the difficulty of hollowing out.
  • four second hollow parts 202 are connected to each other to form one second hollow part 202 , that is, the first input pad Di, the second input pad Pwr, and the output pad Out
  • the orthographic projection of the common voltage pad Gnd is located in the area enclosed by the orthographic projection of the same large second hollow portion 202 .
  • This structure can not only avoid short circuit between each sub-pad and the first conductive part 20 below, but also reduce the precision requirement for the hollowing process of the first conductive part 20 .
  • the electronic components have been bound and connected to the corresponding pads 3011 or 3012 in FIG. 2 , for example, the light emitting device L is connected to the pad 3011 correspondingly, and the driver chip IC is connected to the pad 3012 correspondingly.
  • the shape of the sub-pad is substantially a pentagon, and the shape of the second hollow portion 202 is substantially a rectangle.
  • each pad may also have other numbers of sub-pads, such as 1, 3, etc. sub-pads.
  • a corresponding number of second hollowed-out portions may be included, so that each sub-pad corresponds to a second hollowed-out portion to avoid overlapping at the sub-pads. It is not repeated here.
  • the second conductive part 30 includes a first lead 302 , and the first lead 302 extends along the first direction in the figure.
  • the first lead 302 is a lead in the first direction extending from the LED light-emitting diode.
  • the first lead 302 may also be a lead in the first direction extending from the driving die pad.
  • the first conductive portion 20 is also the common voltage line GND, and the first lead extending in the first direction overlaps the portion of the common voltage line GND extending in the first direction in the thickness direction of the substrate.
  • the first conductive portion 20 includes a second hollow portion 202 , and the second hollow portion 202 includes four third groove structures 2021 , and the third groove structures 2021 extend along the second direction and are arranged along the first direction.
  • the orthographic projection of at least one segment of the first leads 302 on the base substrate 10 is located in the area enclosed by the orthographic projection of the second hollow portion 202 , that is, the corresponding first lead 302 below at least one segment of the first leads 302 is located.
  • the conductive portion 20 is hollowed out, so that the first lead 302 and the lower first conductive portion 20 are no longer overlapped in this area, thereby avoiding static electricity, testing, and manufacturing between the first lead 302 and the first conductive portion 20. cause of short circuit.
  • the region of the first conductive portion 20 directly below the first lead 302 may be hollowed out entirely, or only a section may be hollowed out. That is to say, the second hollow portion 202 may be provided below all the first leads 302 , or may be provided only below a partial area of the first leads 302 . 22, in other embodiments, at least two third groove structures 2021 can also be connected to each other, as long as the connected groove structures are arranged along the first direction, along the first direction. It is sufficient to extend in the second direction, thereby reducing the difficulty of hollowing out.
  • the light emitting diode or the driver chip has been bound at the position of the pad 301 , so the light emitting diode or the driver chip covers the pad 301 , and what is actually seen in the figure is the light emitting diode or the driver chip.
  • the second conductive portion 30 may further include a second lead 303 extending along the second direction.
  • the second lead 303 may be a second-direction lead extending from the driving chip pad, or may be a second-direction lead extending from an LED light-emitting diode.
  • the first conductive portion 20 is also the common voltage line GND, and the second lead 303 extending in the second direction overlaps the portion of the common voltage line GND extending in the first direction in the thickness direction of the substrate.
  • the first conductive portion 20 includes a second hollow portion 202 , and the second hollow portion 202 is located at the portion extending in the first direction of the first conductive portion 20 ; the orthographic projection of at least a section of the second lead 303 on the base substrate 10 is located in the second hollow portion. within the area enclosed by the orthographic projection of the portion 202 . That is to say, the corresponding first conductive portion 20 under at least a section of the second lead 303 is hollowed out, so that the second lead 303 and the lower first conductive portion 20 no longer overlap in this area, thereby avoiding The second lead 303 and the first conductive portion 20 are short-circuited due to static electricity, testing and manufacturing.
  • the bottom of the second lead 303 may be hollowed out entirely, or only a section may be hollowed out. That is to say, the second hollow portion 202 may be provided below all the second leads 303 , or may be provided only below a partial area of the second leads 303 .
  • the second hollow portion 202 under the second lead 303 includes only one third groove structure 2021 .
  • a plurality of third groove structures may also be included.
  • FIG. 24 when the second hollow portion is When 202 includes a plurality of third groove structures, at least two third groove structures may also communicate with each other, thereby reducing the difficulty of hollowing out.
  • the first conductive portion 20 under the second lead 303 is hollowed out, thereby avoiding a short circuit between the second lead 303 and the first conductive portion 20 due to static electricity and process reasons.
  • the second hollow portion 202 corresponding to the second lead 303 may be located at the upper edge or the lower edge of the first conductive portion 20 , or may be located in the middle of the first conductive portion 20 . Therefore, there is a gap between the orthographic projection edge of at least one of the upper and lower sides of the second lead 303 and the orthographic projection edge of the second hollow portion 202 .
  • the second hollow portion 202 shown in FIG. 23 is a closed opening area, the orthographic projection of a section of the second lead 303 overlaps with the orthographic projection of the second hollow portion 202, and the orthographic projection of at least one of the upper and lower sides There is a gap between the edge and the orthographic edge of the second hollow portion 202 .
  • the second hollow portion 202 also extends along the second direction.
  • the second hollow portion 202 For the second hollow portion 202 in a first conductive portion 20, the second hollow portion 202 The length in the second direction should be smaller than the width of the first conductive portion 20 , otherwise the first conductive portion 20 will be cut off. Therefore, when the second lead 303 passes through the entire first conductive portion 20 in the second direction, only a part of the second lead 303 should be hollowed out below.
  • the longer the length of the second hollow portion 202 in the second direction the greater the influence on the IR Drop of the first conductive portion 20 extending in the first direction, resulting in a decrease in signal strength.
  • the longer the length of the second hollow portion 202 in the second direction the less the overlapping area of the second lead 303 and the first conductive portion 20, and the less likely to generate static electricity.
  • the second lead 303 can also span a plurality of first conductive parts 20 extending in the first direction at the same time, and then, one or more groove structures can be provided in each of the first conductive parts 20 .
  • the corresponding second hollow portion 202 may include a plurality of first conductive portions 203 .
  • the three-slot structure corresponds to a plurality of parts on the second lead 303 respectively.
  • the second direction in which the second lead 303 extends may not be perpendicular to the first direction. Regardless of the direction, it should be ensured that the second hollow portion 202 corresponding to the second lead 303 will not cut off the first conductive portion 20, and the influence on the IR Drop should be minimized.
  • the shape of the first lead 302 or the second lead 303 is generally a strip shape
  • the shape of the third groove structure in the second hollow portion 202 is also generally a strip shape.
  • the present disclosure does not limit the specific shape of the third groove structure in the second hollow portion 202, which may or may not be consistent with the shape of the lead.
  • the second conductive portion 30 may further include several functional units for implementing specific functions.
  • the functional unit may include a pad, a first lead, a second lead, and a test conductive part. The following description will be given by taking the functional unit as the test conductive part as an example.
  • the test conductive part 304 is electrically connected to the pad 301 , the first lead 302 or the second lead 303 for testing the electrical properties of the pad 301 or the first lead 302 and the second lead 303 .
  • FIG. 25 shows the test conductive portion 304 and the second hollow portion 202 corresponding to the three sub-pads in the driving chip pad.
  • the test conductive parts 304 are respectively disposed near the first input pad Di, the second input pad Pwr, and the output pad Out, and one end is connected to the sub-pad for testing the voltage and/or current of the sub-pad, and the other is connected to the sub-pad.
  • One end can also be connected to the first lead or the second lead.
  • the film layer above the test conductive portion 304 is opened, so that the test conductive portion 304 is exposed to the outside, so that the needle stick test can be performed there.
  • one second hollow portion 202 may include three third groove structures 2021 , and the orthographic projections of the three test conductive portions 304 on the base substrate correspond to the orthographic projections of the third groove structures 2021 in a one-to-one correspondence.
  • the orthographic projection of the test conductive portion 304 has a gap with the orthographic projection edge of the corresponding third slot structure 2021 . That is to say, the corresponding first conductive portion 20 below the test conductive portion 304 is hollowed out, so that the test conductive portion 304 and the lower first conductive portion 20 no longer overlap in this area, thereby avoiding the need for a needle stick test.
  • test conductive portion 304 may be punctured and contacted with the first conductive portion 20 to cause a short circuit or inaccurate test. Since the common voltage pad Gnd is connected to the common voltage line GND through a via hole, the current or voltage of the common voltage pad Gnd can be directly tested on the common voltage line GND.
  • FIG. 26 it is a cross-sectional view taken along the line A-A in FIG. 25 .
  • test conductive parts 304 in this embodiment is only an example, and the specific number can be set as required. For example, only one test conductive part 304 can be set for a certain sub-pad. Special restrictions.
  • the three groove structures 2021 may communicate with each other, as shown in FIG. 27 , thereby reducing the difficulty of hollowing out.
  • FIG. 28 it is a cross-sectional view taken along the line A-A in FIG. 27 .
  • the second conductive portion includes multiple groups of pads and first leads corresponding to the multiple groups of pads one-to-one, the extending directions of the multiple groups of pads are arranged, the extending directions of the first leads and the first hollow portion
  • the extension directions are the first direction
  • the one-to-one orthographic projection of the first lead on the base substrate is located in the orthographic projection area of the first hollow part on the base substrate
  • multiple groups of pads are located on the substrate
  • the orthographic projection on the substrate is located in the orthographic projection area of the first hollow portion on the base substrate.
  • the orthographic projections of the first lead 302 and the plurality of groups of pads 301 on the base substrate are all within the orthographic projection area of the first hollow portion 201 on the base substrate.
  • the first conductive parts 20 corresponding to at least one section of the first leads 302 are hollowed out, and/or the first conductive sections 20 corresponding to at least one section of the plurality of groups of pads are hollowed out, so that the first leads 302 are hollowed out.
  • 302 and the pad and the first conductive part 20 below do not overlap in this area, so as to avoid short circuit between the first lead 302 and the pad and the first conductive part 20 due to static electricity, testing and process reasons.
  • the display substrate of the present disclosure may only include any one of the above-mentioned second conductive portions 10 and corresponding hollow portions, or may include at least any two types of second conductive portions 10 and their corresponding hollow portions.
  • the substrate may include pads and first leads arranged in the first direction, and also include a first hollow portion and a second hollow portion; it may also include a pad and a test conductive portion, and also include a first hollow portion and a second hollow portion. It can also include the pad, the first lead, the second lead and the test conductive part 304 at the same time, and also include the first hollow part and the second hollow part, etc., which will not be listed one by one here.
  • Embodiments of the present invention further provide a display device including the display substrate in the above-mentioned embodiments. Since the display device includes the above-mentioned display substrate, it has the same beneficial effects, and details are not described herein again in the present invention.
  • the present invention does not specifically limit the application of display devices, which can be TVs, notebook computers, tablet computers, wearable display devices, mobile phones, in-vehicle displays, navigation, e-books, digital photo frames, advertising light boxes, etc. products or parts.
  • display devices can be TVs, notebook computers, tablet computers, wearable display devices, mobile phones, in-vehicle displays, navigation, e-books, digital photo frames, advertising light boxes, etc. products or parts.

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Abstract

本公开提供一种显示基板和显示装置。显示基板包括衬底基板、第一导电层、第二导电层和绝缘层，第一导电层位于衬底基板的一侧，包括沿第一方向延伸的第一导电部，第二导电层位于第一导电层背离衬底基板的一侧，绝缘层位于第一导电层和第二导电层之间，至少一个第一导电部包括第一镂空部，第一镂空部包括多个沿第二方向排布的槽结构，该槽结构沿第一方向延伸，第一方向与第二方向之间存在夹角。本公开在第一导电部设置第一镂空部，可以通过第一镂空部中的多个沿第二方向排布，沿第一方向延伸的槽结构增强第一导电部与层膜之间的附着力，从而提高产品良率，提高产品性能稳定性。

Description

一种显示基板和显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示基板和显示装置。
背景技术
微发光二极管(Mini-Light-Emitting Diode，Mini-LED)是在小间距LED基础上衍生出来的一种新型LED显示技术，也被称为亚毫米发光二极管。由于其具有较好的显示效果以及轻薄体验，同时具有较高的对比度、寿命长等优势，因此在高端显示领域使用趋势明显。
目前，针对Mini-LED的主流驱动方式是以灯组的灯组IC芯片为控制源的类有源驱动(AM，Active Matrix)式驱动，该驱动方式可以实现精细化分区调控，但是此种驱动方式的背板布线涉及复杂，绕线长度大大增加，为了实现更低的压降IR Drop，在制作工艺上采用了较低电阻率的材料(如Cu)，同时在设计时尽量增加其敷设宽度，这就导致了在制作中金属层在绝缘层OC材料上附着力下降的问题，导致产品产生大量脱离不良。
发明内容
本公开的目的在于提供一种显示基板和显示装置。
根据本公开的第一个方面，提供一种显示基板，其中，包括：
衬底基板；
第一导电层，位于所述衬底基板的一侧，包括沿第一方向延伸的第一导电部；
第二导电层，位于所述第一导电层背离所述衬底基板的一侧；
绝缘层，位于所述第一导电层和第二导电层之间；
其中，至少一个所述第一导电部包括第一镂空部，所述第一镂空部包括多个沿第二方向排布的槽结构，所述槽结构沿第一方向延伸，所述第一方向 与所述第二方向之间存在夹角。
在本公开的一种示例性实施方式中，所述第一导电层包括多个在所述第二方向上具有不同尺寸的第一导电部，第一镂空部在所述第二方向上的尺寸和与其对应的所述第一导电部在所述第二方向上的尺寸正相关，第一镂空部中槽结构的数量和与其对应的第一导电部在所述第二方向上的尺寸正相关。
在本公开的一种示例性实施方式中，其中，所述第一镂空部在所述第二方向上的尺寸和与其对应的第一导电部在所述第二方向上的尺寸的比值为20％-40％，其中，所述第一镂空部在所述第二方向上的尺寸为所述第一镂空部中所有槽结构在所述第二方向上的尺寸之和。
在本公开的一种示例性实施方式中，其中，所述第一镂空部中槽结构在所述第一方向上的尺寸与所述第一导电部在所述第一方向上的尺寸的比值为0.3％-0.5％。
在本公开的一种示例性实施方式中，其中，所述第一镂空部中槽结构沿所述第二方向等间距排布。
在本公开的一种示例性实施方式中，其中，第一镂空部在所述第一方向上的尺寸和与其对应的第一导电部在所述第一方向上的尺寸正相关，第一镂空部的数量和与其对应的第一导电部在所述第一方向上的尺寸负相关。
在本公开的一种示例性实施方式中，其中，第一镂空部沿所述第一方向等间距排布。
在本公开的一种示例性实施方式中，所述第一导电层包括多个在所述第二方向上具有不同尺寸的第一导电部；
相邻两个槽结构在所述第二方向的间距和与其对应的第一导电部在所述第二方向上的尺寸正相关。
在本公开的一种示例性实施方式中，其中，所述相邻两个槽结构在所述第二方向的间距和与其对应的第一导电部在第二方向上的尺寸的比值为8％-10％。
在本公开的一种示例性实施方式中，其中，所述第二导电层包括第二导 电部；
所述至少一个所述第一导电部还包括第二镂空部，至少部分所述第二导电部在所述衬底基板上的正投影位于所述第二镂空部在所述衬底基板上的正投影围成的区域内。
在本公开的一种示例性实施方式中，其中，所述第二导电部中与所述第二镂空部对应的部分的正投影边缘与所述第二镂空部在所述衬底基板上的正投影边缘具有间隙。
在本公开的一种示例性实施方式中，其中，所述第二导电部包括焊盘、第一引线、第二引线、功能单元中的至少一者。
在本公开的一种示例性实施方式中，其中，所述第二导电部包括多组焊盘，每组所述焊盘包括多个子焊盘；
至少部分所述子焊盘在所述衬底基板上的正投影分别一一对应的位于各所述第二镂空部的正投影围成的区域内，且各所述子焊盘的正投影外周均与对应的所述第二镂空部的正投影边缘具有间隙。
在本公开的一种示例性实施方式中，在所述第一方向上，相邻两个第一镂空部的间距等于相邻两组焊盘的间距。
在本公开的一种示例性实施方式中，所述第一导电部包括至少两个沿第一方向依次排布的第一镂空部，至少两个第一镂空部在所述第一方向上的间距与相邻两组焊盘的间距的比值在0.8-2之间取值。
在本公开的一种示例性实施方式中，所述第二导电部包括沿所述第一方向延伸的第一引线；
至少部分所述第一引线在所述衬底基板上的正投影与所述第二镂空部在所述衬底基板上的正投影围成的区域重叠，且，所述第一引线至少一侧的正投影边缘与所述第二镂空部的正投影边缘具有间隙。
在本公开的一种示例性实施方式中，所述第二导电部包括沿所述第二方向延伸的第二引线；
至少部分所述第二引线在所述衬底基板上的正投影与所述第二镂空部在 所述衬底基板上的正投影围成的区域重叠，且，所述第二引线至少一侧的正投影边缘与所述第二镂空部的正投影边缘具有间隙。
在本公开的一种示例性实施方式中，所述第二导电部包括若干功能单元；
各所述功能单元在所述衬底基板上的正投影一一对应的位于各所述第二镂空部的正投影围成的区域内，且所述功能单元的正投影外周均与对应的所述第二镂空部的正投影边缘具有间隙。
在本公开的一种示例性实施方式中，所述第二导电部包括多组焊盘和与所述多组焊盘一一对应的第一引线，所述多组焊盘排列的延伸方向、所述第一引线的延伸方向和所述第一镂空部的延伸方向均为所述第一方向；
所述一一对应的第一引线在所述衬底基板上的正投影位于所述第一镂空部在所述衬底基板上的正投影区域内。
在本公开的一种示例性实施方式中，所述多组焊盘在所述衬底基板上的正投影位于所述第一镂空部在所述衬底基板上的正投影区域内。
在本公开的一种示例性实施方式中，所述功能单元包括与所述焊盘、第一引线或第二引线电连接的测试导电部，所述测试导电部用于检测所述焊盘、第一引线或第二引线的电学性能。
在本公开的一种示例性实施方式中，还包括：
缓冲层，位于所述衬底基板和所述第一导电层之间；
其中，所述绝缘层填充至所述第一镂空部，所述绝缘层且通过所述第一镂空部与所述缓冲层接触。
根据本公开另一个方面，提供一种显示装置，包括以上所述的显示基板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本发 明的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种显示基板的截面结构示意图；
图2为本公开实施例提供的一种显示基板的结构示意图；
图3为本公开实施例提供的又一种显示基板的结构示意图；
图4为本公开实施例提供的图2中M区域的放大图；
图5为本公开实施例提供的图4中A-A向的截面示意图；
图6为本公开实施例提供的图2中N区域的放大图；
图7为本公开实施例提供的图6中A-A向的截面示意图；
图8为本公开实施例提供的图2中又一种N区域的放大图；
图9为本公开实施例提供的图2中又一种N区域的放大图；
图10为本公开实施例提供的图2中又一种N区域的放大图；
图11为本公开实施例提供的图2中又一种N区域的放大图；
图12为本公开实施例提供的图2中F区域的放大图；
图13为本公开实施例提供的图12中A-A向的截面示意图；
图14为本公开实施例提供的图2中G区的放大图；
图15为本公开实施例提供的图14中A-A向的截面示意图；
图16为本公开实施例提供的一种焊盘的结构示意图；
图17为本公开实施例提供的为图16中A-A向的截面图；
图18为本公开实施例提供的又一种焊盘的结构示意图；
图19为本公开实施例提供的为图18中A-A向的截面图；
图20为本公开实施例提供的又一种焊盘的结构示意图；
图21为本公开实施例提供的又一种焊盘的结构示意图；
图22为本公开实施例提供的一种第一引线的结构示意图；
图23为本公开实施例提供的一种第二引线的结构示意图；
图24为本公开实施例提供的一种测试导电部的结构示意图；
图25为本公开实施例提供的一种焊盘组和第一引线的结构示意图；
图26为本公开实施例提供的为图27中A-A向的截面图；
图27为本公开实施例提供的又一种焊盘组和第一引线的结构示意图；
图28为本公开实施例提供的为图29中A-A向的截面图；
图29为本公开实施例提供的又一种焊盘组和第一引线的结构示意图。
图中：10、衬底基板；2、第一导电层；20、第一导电部；201、第一镂空部；2010、第一槽结构；2011、第二槽结构；202、第二镂空部；2021、第三槽结构；3、第二导电层；30、第二导电部；301、3011、3012、焊盘；302、第一引线；303、第二引线；304、测试导电部；4、第一绝缘层；5、第二绝缘层；6、第三绝缘层；7、第四绝缘层；8、缓冲层；EU、发光单元；L、发光器件。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的 充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料等。在其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本公开的主要技术创意。
当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
如图1所示，为本公开实施例提供的一种显示基板，包括衬底基板10、第一导电层2、第二导电层3和第一绝缘层4、第二绝缘层5、第三绝缘层6和第四绝缘层7，从图1中可以看出，第一导电层2设于衬底基板10的一侧，包括沿第一方向延伸的第一导电部20，至少一个第一导电部20包括第一镂空部201，第一镂空部201可以包括多个沿第二方向排布的槽结构，槽结构沿第一方向延伸，第一方向与第二方向之间存在夹角。第二导电层3设于第一导电层2背离衬底基板10的一侧，包括第二导电部30。第一导电层2和第二导电层3之间设有第一绝缘层4和第二绝缘层5，第二导电层3上方设有第三绝缘层6和第四绝缘层7，衬底基板10和第一导电层2之间可以设有缓冲层8。其中，在一些实施例中，第一绝缘层4和第三绝缘层6可以是无机绝缘材料，例如为氧化硅、氮化硅、氮氧化硅中的至少一种；第二绝缘层5和第四绝缘层7可以是有机绝缘材料，例如为有机树脂。可以理解的是，第一绝缘层4、第二绝缘层5、第三绝缘层6和第四绝缘层7具体的材料选择不限于此。可以理解的是，槽结构在垂直于衬底基板10所在的平面的深度基本等于第一导电层2或第一导电部20在垂直于衬底基板10所在的平面的厚度，即槽结构为贯穿第一导电部20的镂空狭缝。
图1中，第一方向为垂直于纸面的方向，第二方向为平行于纸面的水平方向，即第一方向和第二方向之间的夹角为90°，即第一方向和第二方向垂直。当然上述只是举例说明，第一方向和第二方向之间的夹角不仅限于90°，本公开实施例不做具体限定。
本公开实施例中，由于第一导电层包括沿第一方向延伸的第一导电部，至少一个第一导电部包括第一镂空部，第一镂空部包括多个沿第二方向排布的槽结构，且槽结构沿第一方向延伸，从而可以通过槽结构减小第一导电部与衬底基板以及第一导电部与绝缘层的占比面积，增强第一导电部与衬底基板以及第一导电部与绝缘层之间的附着力，进而可以降低产品的不良率。
第一导电层2通常用于布置各种信号线，即第一导电部20可以为各种信号线，例如公共电压线GND、驱动电压线VLED、源电源线PWR、源地址线DI等。可选的，第一导电层2的厚度约为1.5～7μm，其材料可以包括铜，例如可以通过溅射的方式形成例如MoNb/Cu/MoNb的叠层材料，叠层中靠近衬底的一侧材料为MoNb，厚度大约在
Figure PCTCN2021091389-appb-000001
左右，主要用于提高膜层与衬底的粘附力，叠层的中间层材料为Cu，为电信号传递通道的优选材料，远离衬底一侧的材料为MoNb，厚度大约在
Figure PCTCN2021091389-appb-000002
左右，可以用于保护中间层，防止电阻率低的中间层表面暴露发生氧化。第一导电层还可以通过电镀的方式形成，具体地，可以先利用MoNiTi形成种子层，以提高后续电镀工艺中金属晶粒的成核密度，之后再通过电镀制作电阻率低的铜，之后再制作防氧化层，材料可以为MoNiTi。
第二导电层3通常用于设置焊盘以及连接引线，可选的，第二导电层的膜层厚度大约在
Figure PCTCN2021091389-appb-000003
左右。
如图1所示，本公开实施例中的第二导电层3可以包括第二导电部30，第二导电部30可以为用于绑定各种电气元件的焊盘301，例如用于安装发光元件的焊盘3011，和/或，用于安装功能元件例如驱动芯片或者传感器的焊盘3012；第二导电部30包括具有连接作用的引线，即第二导电部30也可以包括沿第一方向延伸的第一引线302和沿第二方向延伸的第二引线303分。焊 盘301为第二导电部30中待与电子元件(如发光器件、驱动电路、传感器等元件)电学连接的部分，其远离衬底基板一侧的表面在未与电子元件连接之前需要部分暴露。其远离衬底基板一侧的表面会被绝缘材料层覆盖，以保证电气通路的可靠性和稳定性。为了防止从基板制程到将电子元件设置在基板上的制程过程中，焊盘301暴露在空气中可能会产生氧化的问题，可以只在焊盘301暴露的表面区域设置防氧化材料层，即焊盘区域的表面会比第一引线302和第二引线303所在区域多出一层结构；或者将第二导电部30整体设置为至少两层结构的叠层结构，其远离衬底基板10的膜层材料为防氧化的金属或者合金材料，具体地可以由例如MoNb/Cu/CuNi的叠层结构构成，叠层中的底层材料MoNb主要用于提高粘附力，叠层中的中间层Cu由于电阻率低主要用于传递电信号，叠层中的顶层CuNi既可以防止中间层氧化，又可以保证与电子元件连接的牢固性。
在一种实施例中，第一导电层2可以包括多个在第二方向上具有不同尺寸的第一导电部20，第一镂空部201在第二方向上的尺寸和与其对应的第一导电部20在第二方向上的尺寸正相关，第一导电部20中槽结构的数量和与其对应的第一导电部20在第二方向上的尺寸正相关。
如图2所示，第一导电层2包括在第二方向上具有不同宽度尺寸的第一导电部，例如20-1和20-2，第一导电部20-1在第二方向的尺寸大于第一导电部20-2在第二方向上的尺寸，从图1中可以看出，与第一导电部20-1对应的第一镂空部201在第二方向上的尺寸大于与第一导电部20-2对应的第一镂空部201在第二方向上的尺寸，且与第一导电部20-1对应的第一镂空部201中的槽结构的数量大于与第一导电部20-2对应的第一镂空部201中的槽结构的数量。
需要说明的是，第一镂空部201在第二方向上的尺寸为第一镂空部201中所有槽结构在第二方向上的尺寸的和。
在具体设计中，根据实际需要可以将第一镂空部201在第二方向上的尺寸和与其对应的第一导电部20在第二方向上的尺寸的比值可以设置在 20％-40％之间。
本公开实施例中第一镂空部201在第二方向上的尺寸为第一镂空部中所有槽结构在第二方向上的尺寸之和。
需要说明的是，本公开实施例的图中的尺寸只是示意，并不代表实际的尺寸。
第一镂空部201中的槽结构在第一方向上的尺寸和与其对应的第一导电部20在第一方向上的尺寸正相关，具体的，根据实际需要，可以将第一镂空部201中槽结构在第一方向上的尺寸与第一导电部20在第一方向上的尺寸的比值设置在0.3％-0.5％之间。
将第一镂空部的尺寸设置成与第一导电部的尺寸正相关，可以根据不同尺寸的第一导电部设置不同尺寸的第一镂空部，从而可以更好的增强第一导电部与衬底基板的附着力，以及更好的增强第一导电部与绝缘层的附着力。
在一种实施例中，第一镂空部201中槽结构在第二方向上的排布方式可以为等间距排布。
在一种实施例中，第一导电部中包括多个第一镂空部的情况下，第一镂空部201可以沿第一方向等间距排布。
第一镂空部中的槽结构等间距排布，和/或第一导电部中的多个第一镂空部等间距排布，可以使第一导电部各位置的附着力均匀，提高产品良率。
在一种实施例中，第一镂空部201在第一方向上的尺寸和与其对应的第一导电部20在第一方向上的尺寸正相关，第一镂空部201的数量和与其对应的第一导电部20在第一方向上的尺寸负相关。
由于第一导电部在第一方向上的尺寸越小，则第一导电部与膜层之间的附着力越小，所以可以将第一镂空部的数量设置成与其对应的第一导电部在第一方向上的尺寸负相关。
将第一镂空部在第一方向上的尺寸设置成与第一导电部在第一方向上的尺寸正相关，以及将第一镂空部的数量设置成与第一导电部在第一方向上的尺寸负相关，可以更好的增强第一导电部与衬底基板的附着力，以及更好的 增强第一导电部与绝缘层的附着力。
如图2所示，第一导电层包括多个在第二方向上具有不同尺寸的第一导电部，图2中，第一导电部20-1在第二方向上的尺寸大于第一导电部20-2在第二方向上的尺寸，第一导电部在第二方向上的尺寸越大，第一镂空部中槽结构之间的间距可以设置的越大，相邻两个第一镂空部在第一方向上的间距也可以设置的越大。
在一种实施例中，第一镂空部201在第一方向上的间距可以与相邻的两组焊盘在第一方向上的间距相等，在另一种实施例中，第一镂空部201在第一方向上的间距可以与相邻的两组焊盘在第一方向上的间距的比值在0.8-2之间取值。
本公开实施例中的一组焊盘指的是位于一个发光单元EU中的多个焊盘，具体可以包括焊接发光器件的焊盘和焊接驱动芯片的焊盘；相邻的两组焊盘在第一方向上的间距指的是在第一方向上相邻设置的两个发光单元EU中，分别位于该两个发光单元中相对位置相同的两个焊盘之间的距离。
如图3所示，一个发光单元3011包括4个串联的发光器件L，以与驱动电压线VLED电连接的发光器件作为这4个发光器件串联的起点，与驱动芯片电连接的发光器件作为这4个发光器件串联的终点。4个发光器件由一个驱动芯片驱动。
需要说明的是，本公开的实施例中，每个发光单元EU中的发光器件L的数量不受限制，可以为5个、6个、7个、8个等任意数量，而不限于4个；每个发光单元EU中的发光器件L的连接关系也不限于串联，还可以为并联，或者串并联结合的方式连接。此外，发光器件L可以是Mini LED、MicroLED、OLED、QLED或其他任意类型的发光器件。
如图3所示，D1为第一导电部20-1上的第一镂空部在第一方向上的间距，D3为第一导电部20-2上的第一镂空部在第一方向上的间距，D2为相邻两组焊盘在第一方向上的间距。
需要说明的是，第一镂空部在第一方向上的间距为两个第一镂空部中相 对位置相同的两个槽结构在第一方向上的距离。两组焊盘在第一方向上的间距为两组焊盘中焊接驱动芯片的焊盘在第一方向上朝向同一方向的侧边之间的距离。
由于基板尺寸、工艺等限制，在制作第二导电部30时，往往不可避免的会与第一导电部20形成重叠，二者的重叠区为性能薄弱区域，容易发生短路或断路，导致发生不良或影响信赖性。
例如，若焊盘在衬底基板上的正投影与信号线在衬底基板上的正投影重叠，则在将电子元件与焊盘绑定连接时，例如采用回流焊技术焊接LED芯片时，由于回流焊工艺的瞬时温度高达260～265℃，而焊盘和信号线之间设置有绝缘层，而该温度区间易超出绝缘层的耐温值，导致绝缘层出现破损，从而使焊盘与信号线短路。
再例如，在薄膜制程中不可避免的会产生灰尘、异物等颗粒，当颗粒存在于引线与信号线的重叠区时，容易导致引线与信号线不稳定性地导通，影响产品的信赖性。再者，在采用扎针测试法对上层引线进行电流或电压测试时，容易穿透绝缘层扎到下方的信号线，导致测试不准或精度降低。
第一导电部20和第二导电部30发生短路的一种原因在于，第一导电部20通常设置的较厚较宽，从而第一导电部20能够具有较低的电阻，从而在以提供较大的电压/电流时能够降低IR压降以及RC延迟的问题和较低的电阻；而第二导电部30通常设置的较窄较短，作为引线、焊盘等结构存在。因此二者之间存在一定的电势差。由于玻璃基薄膜制程中，两个导电部之间的绝缘层在固化前为半固半液状态，该过程中引入的水汽可能会留在绝缘层内。在第一导电部20和第二导电部30之间传输的电压信号存在压差时，由于水在电势差的存在下会产生电化学反应，在绝缘层中形成OH -，OH -则会引发第一导电部20和第二导电部30短路。
可见，为了确保产品质量和性能，应当尽量避免第一导电部20和第二导电部30之间短路。
在一些实施例中，对于小尺寸产品，第一导电部20和第二导电部30的 线宽比值约为20到30；对于大尺寸产品，第一导电部20和第二导电部30的线宽比值可高达100倍甚至更多，因此第二导电部30与第一导电部20必然存在重叠。
为了降低第一导电部20和第二导电部30之间短路的概率，可以在第一导电部20和第二导电部30重叠的位置设置第一镂空部201，由于第一镂空部201包括槽结构，槽结构的存在可以减少第一导电部20和第二导电部30重叠的面积，从而可以降低第一导电部20和第二导电部30之间短路出现的概率。
具体的，如图2所示，第一镂空部201可以包括第一槽结构2010(2010-1和2010-2)和第二槽结构2011，第一槽结构2010(2010-1和2010-2)在衬底基板10上的正投影与第二导电部30(第二引线303)在衬底基板10上的正投影至少部分重叠，第二槽结构2011在衬底基板10上的正投影与第二导电部30在衬底基板10上的正投影互不重叠。
第一槽结构2010设置在第一导电部20中，且与第二导电部30至少部分重叠，因此第一槽结构2010能够减小第一导电部与缓冲层的重叠面积，以及减小第一导电部和绝缘层的重叠面积，从而增强第一导电部与缓冲层的附着力，以及增强第一导电部和绝缘层的附着力的同时，还可以减小第一导电部20和第二导电部30之间的短路发生的概率，从而可以降低产品不良率。
第一槽结构2010在衬底基板10上的正投影可以部分落入第二导电部30在衬底基板10上的正投影范围内，还可以全部落入第二导电部30在衬底基板10上的正投影范围内。如图2所示，第一槽结构2010-1部分落入第二引线303在衬底基板上的正投影范围内，第一槽结构2010-2全部落入第一引线302在衬底基板上的正投影范围内。
本公开实施例中，如果第二导电部和第一导电部重叠，且第二导电部为第二引线，则第一槽结构在第一方向上的尺寸可以大于第二引线在第一方向上的尺寸，但是需要保证第一槽结构不会中断第一导电部的信号传输；
如果第二导电部和第一导电部不重叠，当基板尺寸为1850mm*1500mm时，第二槽结构在第一方向上的尺寸可以在300μm-500μm之间，第二槽结 构在第二方向上尺寸为100μm-300μm之间。
下面通过举例进行详细说明。
如图4所示，为图2中M区域的放大图。
图4中，第一槽结构2010在衬底基板10上的正投影部分落入第二引线303在衬底基板10上的正投影的范围内，且第一槽结构2010在第一方向上的尺寸大于第二引线303在第一方向上的尺寸。
参考图5，为图4中A-A向的截面示意图。
如图6所示，为图2中N区域的放大图。
图6中，第一槽结构2010在衬底基板上的正投影部分落入第一引线302在衬底基板10上的正投影的范围内，第一槽结构2010在第二方向上的尺寸小于第一引线302在第二方向上的尺寸。
需要说明的是，图6中虚线部分为第一槽结构2010被第二引线302遮挡住的部分。
参考图7，为图6中A-A向的截面示意图。
如图8所示，为图2中N区域的放大图。
图8中，第一槽结构2010在衬底基板上的正投影部分落入第一引线302在衬底基板10上的正投影的范围内，第一槽结构在第二方向上的尺寸大于第一引线302在第二方向上的尺寸。
需要说明的是，图8中虚线部分为第一槽结构2010被第二引线302遮挡住的部分。
如图9所示，为图2中N区域的放大图。
图9中，第一槽结构2010在衬底基板上的正投影部分落入第一引线302在衬底基板10上的正投影的范围内，第一槽结构2010在第二方向上的尺寸大于第一引线302在第二方向上的尺寸。
需要说明的是，图9中虚线部分为第一槽结构2010被第二引线302遮挡住的部分。
如图10所示，为图2中N区域的放大图。
图10中，第一槽结构2010在衬底基板上的正投影全部落入第一引线302在衬底基板10上的正投影的范围内，第一槽结构2010在第二方向上的尺寸小于第一引线302在第二方向上的尺寸。
如图11所示，图2中N区域的放大图。
图11中，第一槽结构2010在衬底基板上的正投影全部落入第二引线303在衬底基板10上的正投影的范围内，第一槽结构2010在第一方向上的尺寸小于第二引线303在第二方向上的尺寸。
在一种实施例中，第一导电层2可以包括多个在第二方向上具有不同尺寸的第一导电部20，如果第一导电部20和第二导电部30互不重叠，则第一镂空部201中相邻两个槽结构在第二方向上的间距和与其对应的第一导电部在第二方向上的尺寸正相关，具体的，相邻两个槽结构在第二方向上的间距和与其对应的第一导电部20在第二方向上的尺寸的比值可以在8％-10％之间取值，比如100μm-200μm。
如图12所示，为图2中F区域的放大图。从图12中可以看出，第一导电层2包括两个在第二方向上具有不同尺寸的第一导电部，20-1和20-2，其中，20-1在第二方向上的尺寸大于20-2在第二方向上的尺寸，20-1中的第一镂空部201-1中的槽结构2011-1之间的间距大于20-2中的第一镂空部201-2中的槽结构2011-2之间的间距。
参考图13，为图12中A-A向的截面示意图。
由于图12中，第一镂空部201-1与第二导电部30无交叠，第一镂空部201-2与第二导电部30无交叠，因此图13中未显示第二导电部30。
如果第一导电层2包括多个在第二方向上具有不同尺寸的第一导电部20，且第一导电部20和第二导电部30部分重叠，则第一导电部20中的第一镂空部中的槽结构在第二方向上的间距和与其对应的第一导电部20在第二方向上的尺寸正相关，具体的，相邻两个槽结构在第二方向上的间距和与其对应的第一导电部20在第二方向上的尺寸的比值可以在0-8％之间取值，比如基板尺寸为1850mm*1500mm，槽结构在第二方向上的间距可以在5mm～10mm 之间。
本公开实施例中，第一导电部20除了可以包括第一镂空部201以外，还可以包括第二镂空部202，如图14所示，第二镂空部202包括第三槽结构2021，第三槽结构2021沿第二方向延伸，至少部分第二导电部30在衬底基板上的正投影位于第二镂空部202在衬底基板上的正投影围成的区域内。也就是说，在显示基板厚度方向上，第二导电部30和第一导电部20至少部分不重叠，那么，不重叠的地方就可以避免二者之间因静电、制程工艺、测试等原因发生短路，从而提高产品性能稳定性。当然，在完全理想的情况下，使所有第二导电部30和第一导电部20都不重叠，则可以完全避免短路。
在本公开中，描述两个结构之间“重叠”时，指的是其中一个结构在衬底基板上的正投影，与另一个结构在衬底基板上的正投影至少部分重叠。
在一种实施例中，第二镂空部202可以包括一个第三槽结构，也可以包括多个第三槽结构，其中，如果第二镂空部202包括一个第三槽结构2021，由于第三槽结构2021沿第二方向延伸，所以该第二镂空部202也沿第二方向延伸；如果第二镂空部202包括多个第三槽结构2021，则多个第三槽结构2021可以沿第一方向排布，即第二镂空部202沿第一方向延伸，多个第三槽结构2021还可以沿第二方向排布，即第二镂空部202沿第二方向延伸。
如图14所示，为图2中G区的放大图。
第一导电部20包括第二镂空部202，第二镂空部202中包括三个沿第二方向延伸，且沿第二方向排布的第三槽结构2021，第三槽结构2021的正投影全部落入第二引线303的正投影内。
需要说明的是，由于第三槽结构2021被第二引线303覆盖，所以图12中槽结构用虚线表示。
参考图15，为图14中A-A向的截面示意图。
第二镂空部202一方面可以增强第一导电层与膜层间的附着力，另一方面还可以减小第一导电部20与第二导电部30之间出现短路现象的概率。
在具体实施中，至少部分第二导电部30在衬底基板10上的正投影位于 第二镂空部202在衬底基板10上的正投影围成的区域内。
第二镂空部202，即将第一导电部20和第二导电部30重叠的部分区域挖空，由此可以避免第一导电部20与第二导电部30在重叠区域因静电、制程工艺、测试等原因发生短路，从而可以避免影响产品性能的稳定性。
进一步的，第二导电部30中与第二镂空部202对应的部分的正投影边缘与第二镂空部202在衬底基板10上的正投影边缘可以设置一定的间隙，使得第二导电部30与第一导电部20的边缘保留一定距离，进一步降低二者之间发生短路的可能性。
本公开实施例中，第二导电部30可以包括焊盘301、第一引线302、第二引线303、功能单元(测试导电部304)中的至少一者。
在一种实施例中，第二导电部30包括多组焊盘301，每组焊盘包括多个子焊盘，至少部分子焊盘在衬底基板10上的正投影分别一一对应的位于各个第二镂空部202的正投影围成的区域内，且各个子焊盘的正投影外周均与对应的第二镂空部的正投影具有间隙。
本实施方式中，焊盘301可以是用于与电子元件完成电气绑定的导电图案，电子元件包括发光二极管、传感器、驱动芯片等。
参考图16，以用于安装发光二极管的焊盘为例，该焊盘301包括两个子焊盘，一个为子焊盘P，另一个为子焊盘N。
本实施例中，第一导电部20为公共电压线GND，发光二极管的焊盘在显示基板厚度方向上与公共电压线GND发生重叠。在基板厚度方向上，子焊盘P的正投影在衬底基板10上的正投影位于第二镂空部202中的一个第三槽结构2021的正投影围成的区域内，且子焊盘P的正投影外周边缘与该第三槽结构2021的正投影边缘具有间隙。同样的，子焊盘N的正投影在衬底基板10上的正投影位于第二镂空部202中的另一个第三槽结构2021的正投影围成的区域内，且子焊盘N的正投影外周边缘与该第三槽结构2021的正投影边缘具有间隙。
本实施例中，两个槽结构之间被未挖空的第一导电部20分隔，以使每个 槽结构对应各自的子焊盘。
参考图17，为图16中A-A向的截面图。
将第一导电部20正对子焊盘P和子焊盘N的区域进行了挖空，使得子焊盘P、子焊盘N与下方的第一导电部20不再形成重叠，从而避免了焊盘与第一导电部20因焊接、固晶等原因发生短路的问题。
进一步地，同一组焊盘的各子焊盘对应的各第三槽结构2021可以相互连通。参考图18。在本实施例中，两个第三槽结构2021相互连通，形成一个槽结构，也就是说，子焊盘P和子焊盘N的正投影位于同一个大的槽结构的正投影围成的区域内。该结构既可以避免子焊盘P、子焊盘N与第一导电部20短路，又降低了对第一导电部20进行挖空处理的工艺难度。
参考图19，为图18中A-A向的截面图。
本实施例中，子焊盘和第三槽结构2021的形状可以一致，大致均为矩形。
参考图20，以用于安装驱动芯片的焊盘为例，该焊盘包括四个子焊盘，分别为第一输入焊盘Di、第二输入焊盘Pwr、输出焊盘Out以及公共电压焊盘Gnd。上述第一输入焊盘Di被配置为接收第一输入信号，该第一输入信号例如为地址信号，以用于选通相应地址的驱动芯片。例如，第一输入信号可以为来自于源地址线DI的8bit的地址信号，通过解析该地址信号可以获知待传输的地址。第二输入焊盘Pwr被配置为接收第二输入信号，第二输入信号例如为来自于源电源线PWR的电力线载波通信信号。第二输入信号不仅为驱动芯片提供电能，还向驱动芯片传输通信数据，该通信数据可用于控制相应的发光单元的发光时长，进而控制其视觉上的发光亮度。输出焊盘Out被配置为输出驱动信号。例如，驱动信号可以为来自于驱动电压线VLED的驱动电压，用于驱动发光元件发光。公共电压焊盘Gnd被配置为接收公共电压信号，例如来自于公共电压线GND的接地信号。
本实施例中，第一导电部20为公共电压线GND，驱动芯片的焊盘在显示基板厚度方向上与公共电压线GND发生重叠。第一导电部20包括4个第二镂空部202；在基板厚度方向上，第一输入焊盘Di在衬底基板10上的正投 影位于第一个第二镂空部202的正投影围成的区域内，且第一输入焊盘Di的正投影外周边缘与该第二镂空部202的正投影边缘具有间隙。第二输入焊盘Pwr在衬底基板10上的正投影位于第二个第二镂空部202的正投影围成的区域内，且第二输入焊盘Pwr的正投影外周边缘与该第二镂空部202的正投影边缘具有间隙。输出焊盘Out在衬底基板10上的正投影位于第三个第二镂空部202的正投影围成的区域内，且输出焊盘Out的正投影外周边缘与该第二镂空部202的正投影边缘具有间隙。公共电压焊盘Gnd在衬底基板10上的正投影位于第四个第二镂空部202的正投影围成的区域内，公共电压焊盘Gnd的正投影外周边缘与该第二镂空部202的正投影边缘具有间隙。本实施例中，四个第二镂空部202之间被未挖空的第一导电部20分隔，以使每个第二镂空部202对应各自的子焊盘。
将第一导电部20正对四个子焊盘的区域进行了挖空，使得四个子焊盘与下方的第一导电部20不再形成重叠，从而避免了焊盘与第一导电部20短路的问题。
进一步地，同一组焊盘的各子焊盘对应的各第二镂空部202可以相互连通，从而降低挖空难度。参考图21，在本实施例中，四个第二镂空部202相互连通，形成一个第二镂空部202，也就是说，第一输入焊盘Di、第二输入焊盘Pwr、输出焊盘Out以及公共电压焊盘Gnd的正投影位于同一个大的第二镂空部202的正投影围成的区域内。该结构既可以避免各子焊盘与下方第一导电部20短路，又降低了对第一导电部20挖空处理的精度要求。
图22中，电子元件已经与图2中对应的焊盘3011或3012完成绑定连接，例如发光器件L与焊盘3011对应连接，驱动芯片IC与焊盘3012对应连接。
本实施例中，子焊盘的形状大致为五边形，第二镂空部202的形状大致为矩形。
在其他实施例中，每个焊盘还可以具有其他数量的子焊盘，例如具有1个、3个等数量的子焊盘。相应的，可以包括相应数量的第二镂空部，以使每个子焊盘下方都对应一个第二镂空部，避免在子焊盘处形成重叠。此处不再 一一赘述。
在一种实施例中，参考图22，第二导电部30包括第一引线302，第一引线302沿图中第一方向延伸。以图中所示为例，第一引线302为由LED发光二极管延伸出的第一方向引线。在其他实施例中，第一引线302还可以为由驱动芯片焊盘延伸出的第一方向引线。
继续参考图22，本实施例中，第一导电部20也为公共电压线GND，第一方向延伸的第一引线在基板厚度方向上与公共电压线GND第一方向延伸的部分发生重叠。
第一导电部20包括第二镂空部202，第二镂空部202包括4个第三槽结构2021，该第三槽结构2021沿第二方向延伸，沿第一方向排布。第一引线302中的至少一段在衬底基板10上的正投影位于第二镂空部202的正投影围成的区域内，也就是说，将第一引线302中的至少一段下方对应的第一导电部20进行挖空处理，使得第一引线302与下方的第一导电部20在该区域不再形成重叠，从而避免了第一引线302与第一导电部20之间因静电、测试、制程的原因短路。
第一导电部20中位于第一引线302正下方的区域可以全部挖空，也可以只有一段挖空。也就是说，第二镂空部202可以设置在全部第一引线302的下方，也可以仅设置在第一引线302的部分区域的下方。图22中第一引线302下方对应的第二镂空部202，在其他实施方式中，至少两个第三槽结构2021也可以相互连通，只要保证相互连通的槽结构是沿第一方向排列，沿第二方向延伸即可，从而降低挖空难度。
需要说明的是，图22中在焊盘301的位置处已经绑定了发光二极管或驱动芯片，因此发光二极管或驱动芯片覆盖了焊盘301，图中实际看到的是发光二极管或驱动芯片。
在一种实施例中，参考图23，第二导电部30还可以包括第二引线303，第二引线303沿第二方向延伸。第二引线303可以为由驱动芯片焊盘延伸出的第二方向引线，也可以为由LED发光二极管延伸出的第二方向引线。
本实施例中，第一导电部20也为公共电压线GND，第二方向延伸的第二引线303在基板厚度方向上与公共电压线GND第一方向延伸的部分发生重叠。
第一导电部20包括第二镂空部202，第二镂空部202位于第一导电部20第一方向延伸的部分；第二引线303中至少一段在衬底基板10上的正投影位于第二镂空部202的正投影围成的区域内。也就是说，将第二引线303中的至少一段下方对应的第一导电部20进行挖空处理，使得第二引线303与下方的第一导电部20在该区域不再形成重叠，从而避免了第二引线303与第一导电部20之间因静电、测试、制程的原因短路。
第二引线303下方可以全部挖空，也可以只有一段挖空。也就是说，第二镂空部202可以设置在全部第二引线303的下方，也可以仅设置在第二引线303的部分区域的下方。
图23中第二引线303下方的第二镂空部202仅包括一个第三槽结构2021，在其他实施方式中，也可以包含多个第三槽结构，如图24所示，当第二镂空部202包括多个第三槽结构时，至少两个第三槽结构也可以相互连通，从而降低挖空难度。
在本实施例中，将该第二引线303下方的第一导电部20进行挖空，由此可以避免第二引线303与第一导电部20之间因静电、制程的原因短路。
本公开中，在第一方向上，第二引线303对应的第二镂空部202可以位于第一导电部20的上边缘或下边缘，也可以位于第一导电部20的中间。因此，第二引线303上下两侧中至少一侧的正投影边缘与第二镂空部202的正投影边缘具有间隙。图23中所示的第二镂空部202为一封闭的开口区，第二引线303中的一段的正投影与第二镂空部202的正投影重叠，且上下两侧中至少一侧的正投影边缘与第二镂空部202的正投影边缘具有间隙。
需要注意的是，由于第二引线303沿第二方向延伸，第二镂空部202也沿第二方向延伸，对于一个第一导电部20内的第二镂空部202而言，第二镂空部202第二方向长度应当小于第一导电部20的宽度，否则会截断第一导电 部20。因此，当第二引线303在第二方向上穿过整个第一导电部20时，应当只对第二引线303中的一部分下方进行挖空。可以理解的是，第二镂空部202在第二方向上的长度越长，对第一方向延伸的第一导电部20的IR Drop影响越大，导致信号强度降低。但第二镂空部202在第二方向上的长度越长，第二引线303与第一导电部20重叠区越少，越不容易产生静电。
实际产品中，需综合考虑两方面原因设置第二镂空部202的第二方向长度。此外，第二引线303也可以同时横跨多个第一方向延伸的第一导电部20，那么，每个第一导电部20内都可以设置一个或多个槽结构。一条第二引线303不横跨第一导电部20时，即第二引线303的正投影仅位于一个第一导电部20的正投影内时，其对应的第二镂空部202可以包括多个第三槽结构，分别对应第二引线303上的多个部分。
在其他实施例中，第二引线303延伸的第二方向也可以不垂直于第一方向。无论方向如何，都应保证第二引线303对应的第二镂空部202不会截断第一导电部20，且尽量降低对IR Drop的影响。
本实施例中，由于第一引线302或第二引线303的形状一般大致为条形，因此第二镂空部202中的第三槽结构的形状大致也为条形。本公开不限定第二镂空部202中的第三槽结构的具体形状，其可以与引线形状一致，也可以不一致。
在一种实施例中，第二导电部30还可以包括若干功能单元，用于实现特定功能。功能单元可以包括焊盘、第一引线、第二引线、测试导电部，下面以功能单元为测试导电部为例进行说明。
测试导电部304，测试导电部304与焊盘301、第一引线302或第二引线303电连接，用于检测焊盘301或第一引线302、第二引线303的电学性能。
例如可采用扎针测试方法测试焊盘的电流或电压特性，具体而言，图25中示出了驱动芯片焊盘中的三种子焊盘对应的测试导电部304及第二镂空部202，三个测试导电部304分别对应设置在第一输入焊盘Di、第二输入焊盘Pwr、输出焊盘Out附近，一端与子焊盘连接，用于测试子焊盘的电压和/或电 流，其另一端还可以与第一引线或第二引线连接。测试导电部304上方膜层开口，使测试导电部304裸露在外，以便在此处进行扎针测试。
如图25所示，一个第二镂空部202可以包括三个第三槽结构2021，三个测试导电部304在衬底基板上的正投影一一对应的位于各第三槽结构2021的正投影内，测试导电部304的正投影与对应的第三槽结构2021的正投影边缘具有间隙。也就是说，将测试导电部304下方对应的第一导电部20进行挖空处理，使得测试导电部304与下方的第一导电部20在该区域不再形成重叠，从而避免了在进行扎针测试时可能会扎破测试导电部304而与第一导电部20接触造成短路或测试不准。由于公共电压焊盘Gnd与公共电压线GND通过过孔相连，因此公共电压焊盘Gnd的电流或电压可以直接在公共电压线GND上测试。
参考图26，为图25中A-A向的截面图。
本实施例中测试导电部304的数量仅为示例，具体数量可根据需要进行设置，例如，也可以仅针对某一子焊盘设置一个测试导电部304，本申请不对测试导电部304的数量进行特殊限定。本实施例中，三个槽结构2021可以相互连通，如图27所示，从而降低挖空难度。
参考图28，为图27中A-A向的截面图。
在一种实施例中，第二导电部包括多组焊盘和与多组焊盘一一对应的第一引线，多组焊盘排列的延伸方向、第一引线的延伸方向和第一镂空部的延伸方向均为第一方向，一一对应的第一引线在衬底基板上的正投影位于第一镂空部在衬底基板上的正投影区域内，和/或多组焊盘在衬底基板上的正投影位于第一镂空部在衬底基板上的正投影区域内。
如图29所示，第一引线302和多组焊盘301在衬底基板上的正投影均在第一镂空部201在衬底基板上的正投影区域内。
将第一引线302中的至少一段下方对应的第一导电部20进行挖空处理，和/或将多组焊盘的至少一段下方对应的第一导电部20进行挖空处理，使得第一引线302和焊盘与下方的第一导电部20在该区域不再形成重叠，从而避免 了第一引线302和焊盘与第一导电部20之间因静电、测试、制程的原因短路。
以上对各种第二导电部10的类型及其对应第一导电部的镂空部进行了详细说明。本公开的显示基板可以只包括上述任意一种第二导电部10及其对应的镂空部，也可以包括至少任意两种第二导电部10及其对应的镂空部。例如，基板上可以包括焊盘及第一方向设置的第一引线，还包括第一镂空部和第二镂空部；也可以包括焊盘及测试导电部，还包括第一镂空部和第二镂空部；也可以同时包括焊盘、第一引线、第二引线及测试导电部304，还包括第一镂空部和第二镂空部，等，此处不再一一列举。
本发明实施方式还提供一种显示装置，该显示装置包括上述实施方式中的显示基板。由于该显示装置包括上述显示基板，因此具有相同的有益效果，本发明在此不再赘述。
本发明对于显示装置的适用不做具体限制，其可以是电视机、笔记本电脑、平板电脑、可穿戴显示设备、手机、车载显示、导航、电子书、数码相框、广告灯箱等任何具有柔性显示功能的产品或部件。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (23)

  1. 一种显示基板，其中，包括：
    衬底基板；
    第一导电层，位于所述衬底基板的一侧，包括沿第一方向延伸的第一导电部；
    第二导电层，位于所述第一导电层背离所述衬底基板的一侧；
    绝缘层，位于所述第一导电层和第二导电层之间；
    其中，至少一个所述第一导电部包括第一镂空部，所述第一镂空部包括多个沿第二方向排布的槽结构，所述槽结构沿第一方向延伸，所述第一方向与所述第二方向之间存在夹角。
  2. 如权利要求1所述的显示基板，其中，所述第一导电层包括多个在所述第二方向上具有不同尺寸的第一导电部，第一镂空部在所述第二方向上的尺寸和与其对应的所述第一导电部在所述第二方向上的尺寸正相关，第一镂空部中槽结构的数量和与其对应的第一导电部在所述第二方向上的尺寸正相关。
  3. 如权利要求2所述的显示基板，其中，所述第一镂空部在所述第二方向上的尺寸和与其对应的第一导电部在所述第二方向上的尺寸的比值为20％-40％，其中，所述第一镂空部在所述第二方向上的尺寸为所述第一镂空部中所有槽结构在所述第二方向上的尺寸之和。
  4. 如权利要求2所述的显示基板，其中，所述第一镂空部中槽结构在所述第一方向上的尺寸与所述第一导电部在所述第一方向上的尺寸的比值为0.3％-0.5％。
  5. 如权利要求2所述的显示基板，其中，所述第一镂空部中槽结构沿所述第二方向等间距排布。
  6. 如权利要求2所述的显示基板，其中，第一镂空部在所述第一方向上的尺寸和与其对应的第一导电部在所述第一方向上的尺寸正相关，第一镂空 部的数量和与其对应的第一导电部在所述第一方向上的尺寸负相关。
  7. 如权利要求6所述的显示基板，其中，第一镂空部沿所述第一方向等间距排布。
  8. 如权利要求1所述的显示基板，其中，所述第一导电层包括多个在所述第二方向上具有不同尺寸的第一导电部；
    相邻两个槽结构在所述第二方向的间距和与其对应的第一导电部在所述第二方向上的尺寸正相关。
  9. 如权利要求8所述的显示基板，其中，所述相邻两个槽结构在所述第二方向的间距和与其对应的第一导电部在第二方向上的尺寸的比值为8％-10％。
  10. 如权利要求2-9任一所述的显示基板，其中，所述第二导电层包括第二导电部；
    所述至少一个所述第一导电部还包括第二镂空部，至少部分所述第二导电部在所述衬底基板上的正投影位于所述第二镂空部在所述衬底基板上的正投影围成的区域内。
  11. 如权利要求10所述的显示基板，其中，所述第二导电部中与所述第二镂空部对应的部分的正投影边缘与所述第二镂空部在所述衬底基板上的正投影边缘具有间隙。
  12. 如权利要求10所述的显示基板，其中，所述第二导电部包括焊盘、第一引线、第二引线、功能单元中的至少一者。
  13. 如权利要求12所述的显示基板，其中，所述第二导电部包括多组焊盘，每组所述焊盘包括多个子焊盘；
    至少部分所述子焊盘在所述衬底基板上的正投影分别一一对应的位于各所述第二镂空部的正投影围成的区域内，且各所述子焊盘的正投影外周均与对应的所述第二镂空部的正投影边缘具有间隙。
  14. 如权利要求13所述的显示基板，其中，在所述第一方向上，相邻两个第一镂空部的间距等于相邻两组焊盘的间距。
  15. 如权利要求13所述的显示基板，其中，所述第一导电部包括至少两个沿第一方向依次排布的第一镂空部，至少两个第一镂空部在所述第一方向上的间距与相邻两组焊盘的间距的比值在0.8-2之间取值。
  16. 如权利要求12所述的显示基板，其中，所述第二导电部包括沿所述第一方向延伸的第一引线；
    至少部分所述第一引线在所述衬底基板上的正投影与所述第二镂空部在所述衬底基板上的正投影围成的区域重叠，且，所述第一引线至少一侧的正投影边缘与所述第二镂空部的正投影边缘具有间隙。
  17. 如权利要求12所述的显示基板，其中，所述第二导电部包括沿所述第二方向延伸的第二引线；
    至少部分所述第二引线在所述衬底基板上的正投影与所述第二镂空部在所述衬底基板上的正投影围成的区域重叠，且，所述第二引线至少一侧的正投影边缘与所述第二镂空部的正投影边缘具有间隙。
  18. 如权利要求12所述的显示基板，其中，所述第二导电部包括若干功能单元；
    各所述功能单元在所述衬底基板上的正投影一一对应的位于各所述第二镂空部的正投影围成的区域内，且所述功能单元的正投影外周均与对应的所述第二镂空部的正投影边缘具有间隙。
  19. 如权利要求12所述的显示基板，其中，所述第二导电部包括多组焊盘和与所述多组焊盘一一对应的第一引线，所述多组焊盘排列的延伸方向、所述第一引线的延伸方向和所述第二镂空部的延伸方向均为所述第一方向；
    所述一一对应的第一引线在所述衬底基板上的正投影位于所述第二镂空部在所述衬底基板上的正投影区域内。
  20. 如权利要求13所述的显示基板，其中，所述多组焊盘在所述衬底基板上的正投影位于所述第二镂空部在所述衬底基板上的正投影区域内。
  21. 如权利要求12所述的显示基板，其中，所述功能单元包括与所述焊盘、第一引线或第二引线电连接的测试导电部，所述测试导电部用于检测所 述焊盘、第一引线或第二引线的电学性能。
  22. 如权利要求1-9、11-21任一所述的显示基板，其中，还包括：
    缓冲层，位于所述衬底基板和所述第一导电层之间；
    其中，所述绝缘层填充至所述第一镂空部，所述绝缘层且通过所述第一镂空部与所述缓冲层接触。
  23. 一种显示装置，其中，包括如权利要求1-22任一所述的显示基板。
PCT/CN2021/091389 2021-04-30 2021-04-30 一种显示基板和显示装置 WO2022226976A1 (zh)

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DE112021004601.2T DE112021004601T5 (de) 2021-04-30 2021-04-30 Anzeigesubstrat und anzeigevorrichtung
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050077524A1 (en) * 2003-10-14 2005-04-14 Ahn Byung Chul Liquid crystal display panel and fabricating method thereof
US20060113538A1 (en) * 2004-12-01 2006-06-01 Lg Philips Lcd Co., Ltd. Thin film transistor substrate and fabricating method thereof
CN107203060A (zh) * 2017-06-05 2017-09-26 昆山龙腾光电有限公司 彩膜基板和液晶显示面板
CN111146238A (zh) * 2018-10-17 2020-05-12 昆山工研院新型平板显示技术中心有限公司 阵列基板及其制作方法、显示面板、电子设备

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050077524A1 (en) * 2003-10-14 2005-04-14 Ahn Byung Chul Liquid crystal display panel and fabricating method thereof
US20060113538A1 (en) * 2004-12-01 2006-06-01 Lg Philips Lcd Co., Ltd. Thin film transistor substrate and fabricating method thereof
CN107203060A (zh) * 2017-06-05 2017-09-26 昆山龙腾光电有限公司 彩膜基板和液晶显示面板
CN111146238A (zh) * 2018-10-17 2020-05-12 昆山工研院新型平板显示技术中心有限公司 阵列基板及其制作方法、显示面板、电子设备

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