WO2023142021A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2023142021A1
WO2023142021A1 PCT/CN2022/074923 CN2022074923W WO2023142021A1 WO 2023142021 A1 WO2023142021 A1 WO 2023142021A1 CN 2022074923 W CN2022074923 W CN 2022074923W WO 2023142021 A1 WO2023142021 A1 WO 2023142021A1
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WO
WIPO (PCT)
Prior art keywords
display panel
base substrate
display
insulating
electrostatic protection
Prior art date
Application number
PCT/CN2022/074923
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English (en)
French (fr)
Other versions
WO2023142021A9 (zh
Inventor
刘超
赵仲兰
翟明
孙海威
时凌云
谷其兵
王莉莉
贾明明
冯莎
王静
Original Assignee
京东方科技集团股份有限公司
京东方晶芯科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 京东方晶芯科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000101.1A priority Critical patent/CN117083658A/zh
Priority to PCT/CN2022/074923 priority patent/WO2023142021A1/zh
Priority to US18/016,478 priority patent/US20240258325A1/en
Publication of WO2023142021A1 publication Critical patent/WO2023142021A1/zh
Publication of WO2023142021A9 publication Critical patent/WO2023142021A9/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields

Definitions

  • the present disclosure relates to the field of display technology, in particular to a display panel and a display device.
  • Electrostatic breakdown is a phenomenon that due to the large amount of static electricity accumulated in the display panel manufacturing process, when the charge transfer process encounters thinner traces or places where wires cross, the instantaneous current is too large, thus causing damage to electronic devices. During the manufacturing process or testing process of the display panel, once the phenomenon of electrostatic breakdown occurs, the yield rate of the display panel will be affected.
  • Embodiments of the present disclosure provide a display panel and a display device.
  • the present disclosure provides a display panel, including:
  • a base substrate having a first surface and a second surface oppositely arranged, and a side surface connecting the first surface and the second surface; the first surface includes a display area and an epitaxial area;
  • each of the first binding electrodes is electrically connected to a display signal line located on the first surface and extending from the display region to the epitaxial region ;
  • a plurality of driving signal lines disposed on the second surface of the base substrate, wherein at least one of the plurality of driving signal lines is a ground line;
  • a plurality of side traces each of the side traces electrically connects one of the driving signal lines to one of the first bonding electrodes via the side;
  • the electrostatic protection layer is electrically connected to the ground wire, and the orthographic projection of the electrostatic protection layer on the side is at least partially overlapped with the orthographic projection of the side wiring on the side.
  • the electrostatic protection layer includes at least:
  • the connected first static protection part and the second static protection part, the first static protection part is located on the second surface of the base substrate, and the orthographic projection on the second surface covers the side
  • the orthographic projection of the part of the wiring on the second surface on the second surface; the first electrostatic protection part is connected to the ground wire; the orthographic projection of the second electrostatic protection part on the side covers An orthographic projection of the side wiring on the side.
  • the display panel also includes:
  • a first insulating layer is located on a side of the plurality of driving signal lines away from the base substrate, and each of the side wirings is connected through a first via hole on the first insulating layer one drive signal line;
  • the first static protection portion is located on a side of the first insulating layer away from the base substrate, and is connected to the ground wire through a second via hole on the first insulating layer.
  • the orthographic projection of the boundary of the first ESD protection part away from the second ESD protection part on the base substrate and the orthographic projection of the second via hole on the base substrate The shortest distance between them is between 15 and 25 ⁇ m.
  • the display panel also includes:
  • the second insulating layer is arranged on the side of the electrostatic protection layer close to the side wiring;
  • the second insulating layer includes: a first insulating part and a second insulating part, the first insulating part is located between the first electrostatic protection part and the side wiring, and the second insulating part is located Between the second electrostatic protection part and the side wiring, the orthographic projection of the first insulating part on the base substrate is the same as the orthographic projection of the second via hole on the base substrate. overlap.
  • the first insulating part has a first side extending away from the second insulating part along a first direction, and the first direction is the same as that directed from the display region to the epitaxial region. direction crossing;
  • the portion of the side wiring on the second surface has a first end close to the first side, and the orthographic projection of the first side on the base substrate is the same as the first end.
  • the interval between the orthographic projections of the parts on the base substrate is between 15-25 ⁇ m.
  • the second insulating layer further includes:
  • the third insulating part is located on the side where the side traces are located on the second surface away from the second surface, and the third insulating part is connected to the second insulating part ;
  • the third insulating portion has a second side extending away from the side of the base substrate and extending along a first direction, the first direction intersects a direction from the display area to the epitaxial area; the The part of the side wiring on the first surface has a second end close to the second side, and the distance between the second side and the second end is between 15 ⁇ m and 25 ⁇ m.
  • the electrostatic protection layer also includes:
  • a third static protection part is located on the first surface of the base substrate and in the epitaxial region, the third static protection part is connected to the second static protection part.
  • the first ESD protection part, the second ESD protection part and the third ESD protection part are connected as an integral structure, and the positive side of the third ESD protection part on the first surface The projection penetrates the first surface along the first direction, and the orthographic projection of the first electrostatic protection part on the second surface penetrates the second surface along the first direction, wherein the first direction and The direction from the display area to the epitaxial area intersects.
  • the display panel also includes:
  • a third insulating layer is located on a side of the second electrostatic protection portion away from the side of the base substrate.
  • the third insulating layer covers all of the second ESD protection part and at least part of the first ESD protection part.
  • the display area includes a plurality of sub-pixels, each sub-pixel is provided with a light-emitting element, and each of the light-emitting elements is connected to the display signal line.
  • the display panel also includes:
  • a driving structure is connected to the plurality of driving signal lines, and is used to provide driving signals for the plurality of driving signal lines.
  • the display panel also includes:
  • a first insulating layer is located on a side of the plurality of driving signal lines away from the base substrate, and the side wiring passes through the first via hole on the first insulating layer and the corresponding Drive signal line connection;
  • the driving structure is connected to the driving signal line through the third via hole on the first insulating layer.
  • the present disclosure provides a display device, including:
  • the display panel of the first aspect is the display panel of the first aspect
  • an outer frame at least a part of the outer frame is located on a side of the base substrate away from the display signal line;
  • Adhesive glue the adhesive glue is located on the side of the base substrate away from the display signal line, and is connected between the display panel and the outer frame.
  • the outer frame is a metal frame
  • the bonding glue is conductive glue, and is connected between the metal frame and the electrostatic protection layer.
  • Figure 1 is a schematic diagram of the sideline technique provided in an example
  • FIG. 2 is a plan view of a display structure layer and a first binding electrode on a display panel provided in an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 4 is a plan view of a driving signal line provided by an embodiment of the present disclosure.
  • FIG. 5 is a plan view of vias and driving signal lines on the first insulating layer provided in an embodiment of the present disclosure
  • FIG. 6 is a plan view of a first electrostatic protection portion and a driving signal line provided by an embodiment of the present disclosure
  • FIG. 7 is a plan view of a third electrostatic protection part provided by an embodiment of the present disclosure.
  • FIG. 8 is a plan view of a first insulating part and side traces provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • FIG. 12 is a rear view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic front view of a display structure layer provided by an embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of a display structure layer provided by an embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of the principle of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 16 is a plan view of an encapsulation layer provided by an embodiment of the present disclosure.
  • FIG. 17 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • Fig. 18 is a plan view of an outer frame provided by an embodiment of the present disclosure.
  • FIG. 19 is a schematic structural diagram of another display device provided by an embodiment of the present disclosure.
  • micro light-emitting diode (Micro LED or Mini LED) display technology is developing rapidly. Due to its outstanding advantages: small size, low power consumption, high color saturation, fast response, long life, etc., it has attracted a large number of scientific and technological workers. investment in research. However, due to the immaturity of mass transfer technology, the development of micro light-emitting diode displays in high resolution and large size has been hindered.
  • the capability of the existing mass transfer technology corresponds to TV and giant screen display, and the seamless splicing display technology can make up for the shortcomings of the current mass transfer technology to achieve large-screen display. To achieve truly seamless splicing in micro-LED splicing displays requires the use of side wiring (Side wiring) technology.
  • FIG. 1 is a schematic diagram of the side line technology provided in an example.
  • at least one display signal line extends from the front display area AA to the epitaxial area NA, and is connected to the first bonding electrode 2 in the epitaxial area NA.
  • the first binding electrode 2 is connected to the side wiring 4
  • the side wiring 4 is wound to the back of the base substrate 1 through the side of the base substrate 1, and is connected to the driving signal line 3 on the back, and the driving signal line is connected to the driving signal line 3.
  • the protective layer 4A is used to space adjacent display panels so as not to affect the display effect of the spliced display screen. Due to the need to meet the seamless splicing requirements of the spliced display screen, the insulating protection layer 4A is generally set relatively thin (for example, in the range of 2-10 ⁇ m), so that during the preparation or testing of the display panel, when the display panel When static electricity is generated at the edge, the insulating protective layer 4A cannot achieve a good electrostatic protection effect.
  • the embodiments of the present disclosure provide a display panel, which satisfies the requirement of the display panel for a narrow frame while effectively implementing electrostatic protection.
  • Fig. 2 is a plan view of the display structure layer and the first binding electrode on the display panel provided in the embodiment of the present disclosure
  • Fig. 3 is a schematic structural diagram of a display panel provided in the embodiment of the present disclosure, as shown in Figs. 2 and 3
  • An embodiment of the present disclosure provides a display panel, including: a base substrate 1 , a plurality of first binding electrodes 2 , a display structure layer 10 , a plurality of side traces 4 and an electrostatic protection layer 5 .
  • the base substrate 1 has a first surface 1a and a second surface 1b oppositely arranged, and a side surface 1c connecting the first surface and the second surface, the first surface includes a display area AA and an epitaxial area NA, and the epitaxial area NA is located on the display At least one side of the area AA, the display area AA includes a plurality of sub-pixels.
  • the display structure layer 10 includes a plurality of display signal lines 16 and a plurality of light-emitting elements, each sub-pixel is provided with a light-emitting element, and the light-emitting elements are micro light-emitting diodes such as Micro LED or Mini LED.
  • a plurality of display signal lines 16 are used to provide driving signals for a plurality of light emitting elements, and at least part of the display signal lines 16 extend from the display area to the epitaxial area NA.
  • a plurality of first binding electrodes 2 are located in the epitaxial area NA, and each first binding electrode 2 is electrically connected to a display signal line 16 extending from the display area AA to the epitaxial area NA.
  • the first binding electrode 2 may be rectangular, and its length may be between 0.08-0.2 mm, and its width may be between 0.06-0.1 mm.
  • Fig. 4 is a plan view of the driving signal lines provided by the embodiment of the present disclosure.
  • a plurality of driving signal lines 3 are arranged on the second surface 1b, and at least one of the plurality of driving signal lines 3 is a ground line.
  • Each side trace 4 electrically connects a driving signal line 3 to a first bonding electrode 2 via the side.
  • one end of the driving signal line 3 away from the side wiring can be connected to the driving structure 9 (for example, a driving circuit board), thereby receiving the driving signal provided by the driving structure 9, and the side wiring 4 transmits the driving signal on the driving signal line 3 To the display signal line 16, and then provided to the light emitting element.
  • the driving structure 9 for example, a driving circuit board
  • the electrostatic protection layer 5 is electrically connected to the ground wire 3a, and the orthographic projection of the electrostatic protection layer 5 on the side 1c covers the orthographic projection of the side wiring 4 on the side 1c.
  • the embodiment of the present disclosure does not limit the material of the electrostatic protection layer.
  • the electrostatic protection layer 5 may be an anti-corrosion metal material, such as Ti.
  • the side traces 4 on the display panel can be made by a sputtering process.
  • a chamfer N is formed at the edge of the intersection of the first surface 1 a and the side 1 c of the base substrate 1 , and a chamfer is also formed at the edge of the intersection of the second surface 1 b and the side 1 c.
  • the formation of the above-mentioned chamfering structure is beneficial to prepare the side traces 4 on the display panel through a sputtering process, avoiding the breakage of the side traces 4 at the edge position, and avoiding the cracking at the above-mentioned edge when depositing other film layers on the substrate substrate. The location is broken.
  • the width of the above-mentioned chamfer N may be d0, for example, d0 is 1/30 ⁇ 1/5 of the thickness of the base substrate, and its size is not specifically limited.
  • the above-mentioned chamfer N may be a chamfered surface, or may be an outwardly protruding arc surface structure.
  • the edge position can also be made into a chamfered structure as shown in FIG. 3 , which is not limited in the present disclosure.
  • At least one of the plurality of driving signal lines 3 being a ground line 3a specifically refers to: part of the plurality of driving signal lines 3 is a ground line 3a, and the other part is a non-ground line 3b.
  • the electrical protection layer 5 and the non-ground wire 3 b are separated by an insulating layer, so as to prevent different driving signal lines 3 from short-circuiting through the electrostatic protection layer 5 .
  • the material of the driving signal line in the embodiment of the present disclosure is a metal material, which can be a single layer of metal, or a stack of multiple layers of metal, such as Ti/AL/Ti, or Mo/Cu/Mo or Ti/Cu/Ti or Mo/Cu/ITO, etc., which are not limited in the embodiments of the present disclosure.
  • a plurality of driving signal lines 3 may be formed by depositing a metal layer on the second surface 1 b of the base substrate 1 and performing a patterning process on the metal layer.
  • an electrostatic protection layer 5 is provided, and the orthographic projection of the electrostatic protection layer 5 on the side 1c covers the orthographic projection of the side wiring 4 on the side 1c, because the electrostatic protection layer 5 is also connected to the ground wire 3a connection, therefore, during the electrostatic test process, the static electricity generated on the side of the display panel can be exported through the electrostatic protection layer, which improves the electrostatic protection capability of the display panel.
  • the electrostatic protection layer 5 can play the role of anti-static, there is no need to provide structures such as an overly thick insulating layer or conductive glue on the side of the display panel, which is conducive to realizing a narrow frame of the display panel.
  • the thickness of the static protection layer 5 can be set between 0.06-0.5 ⁇ m, so as to reduce the influence of the static protection layer 5 on the frame width of the display panel while achieving a good antistatic effect.
  • the electrostatic protection layer 5 at least includes: a connected first electrostatic protection portion 51 and a second electrostatic protection portion 52, and the first electrostatic protection portion 51 is located on the second surface 1b of the base substrate. , and the orthographic projection on the second surface 1b covers the orthographic projection of the part of the side wiring 4 located on the second surface 1b on the second surface 1b; the first electrostatic protection part 51 is connected to the ground wire 3a.
  • the second ESD protection portion 52 is opposite to the side surface 1c of the base substrate 1 , and the orthographic projection of the second ESD protection portion 52 on the side surface 1c at least partially overlaps the orthographic projection of the side wiring 4 on the side surface 1c.
  • the orthographic projection of the second electrostatic protection part 52 on the side 1c may cover the orthographic projection of the side wiring 4 on the side 1c; in another example, the second electrostatic protection part 52 is on the side An orthographic projection on 1c can cover the entire side 1c.
  • the display panel further includes: a first insulating layer 6 , and a plurality of via holes are arranged on the first insulating layer 6 .
  • FIG. 5 shows the first insulating layer provided in an embodiment of the present disclosure. 3 and 5, the first insulating layer 6 is located on the side of the plurality of driving signal lines 3 away from the base substrate 1, and the first insulating layer 6 can cover the second A partial area of the surface 1b may also cover the entire area of the second surface 1b.
  • a plurality of first via holes 61 are disposed on the first insulating layer 6 , and each side trace 4 is connected to a driving signal line 3 through the first via holes 61 on the first insulating layer 6 .
  • the first electrostatic protection part 51 is located on the side of the first insulating layer 6 away from the base substrate 1 , and is connected to the ground wire 3 a through the second via hole 62 on the first insulating layer 6 .
  • the embodiment of the present disclosure is described by taking the side traces directly connected to the driving signal line 3 through the first via hole 61 as an example.
  • a transfer electrode a part of the transfer electrode Located in the first via hole 61 , the side wiring 4 is connected to the driving signal line 3 through the via electrode.
  • the first insulating layer 6 is further provided with a third via hole 63 at a position corresponding to each driving signal line, and the third via hole 63 is used to connect the driving structure to each driving signal line.
  • the driving structure will be described below, so I won't go into details here.
  • the material of the above-mentioned first insulating layer may be any one of silicon nitride material, silicon oxide material and silicon oxynitride, and each via hole may be formed by a photolithographic patterning process.
  • the ESD protection layer 5 may further include: a third ESD protection part 53, the third ESD protection part 53 is connected to the second ESD protection part 52, and the third ESD protection part 53 is positioned on the lining
  • the first surface 1a of the base substrate 1 is located in the epitaxial area NA, that is, the third static protection portion 53 does not extend to the display area AA, so the arrangement of the third static protection portion 53 will not affect the display function of the display panel.
  • the first ESD protection part 51 , the second ESD protection part 52 and the third ESD protection part 53 are connected as an integral structure.
  • FIG. 6 is a plan view of a first electrostatic protection portion and a driving signal line provided by an embodiment of the present disclosure
  • FIG. 7 is a plan view of a third electrostatic protection portion provided by an embodiment of the present disclosure.
  • the orthographic projection of the third electrostatic protection part 53 on the first surface 1a penetrates the first surface 1a along the first direction; as shown in Figure 7, the projection of the first electrostatic protection part 51 on the second surface 1b The orthographic projection penetrates the second surface 1b along the first direction.
  • the first direction crosses the direction from the display area AA to the epitaxial area NA, for example, the first direction is perpendicular to the direction from the display area AA to the epitaxial area NA.
  • the static electricity protection layer 5 can lead out the static electricity, so as to prevent the static electricity from causing damage to the devices and/or circuits inside the display panel, and improve the static electricity protection capability of the display panel. .
  • the orthographic projection of the first electrostatic protection portion 51 on the base substrate 1 completely covers the orthographic projection of the second via hole 62 on the base substrate 1.
  • the first The shortest distance d1 between the orthographic projection of the boundary of the electrostatic protection portion 51 away from the second electrostatic protection portion 52 on the base substrate 1 and the orthographic projection of the second via hole 62 on the base substrate 1 is between 15 ⁇ m and 25 ⁇ m, In order to ensure the reliability of the connection between the first electrostatic protection portion 51 and the second via hole 62 .
  • d1 may be 15 ⁇ m or 18 ⁇ m or 20 ⁇ m or 22 ⁇ m or 25 ⁇ m.
  • the display panel further includes: a second insulating layer 7 , and the second insulating layer 7 is disposed on a side of the electrostatic protection layer 5 close to the side traces 4 .
  • the second insulating layer 7 includes: a first insulating part 71 and a second insulating part 72, the first insulating part 71 is located between the first electrostatic protection part 51 and the side wiring 4, and the second insulating part 72 is located between the second Between the electrostatic protection part 52 and the side wiring 4, the orthographic projection of the first insulating part 71 on the base substrate 1 does not overlap with the orthographic projection of the second via hole 62 on the base substrate 1, that is, the first insulating part The boundary of 71 does not extend to the second via hole 62 , which will not affect the connection between the second via hole 62 and the first ESD protection portion 51 .
  • FIG. 8 is a plan view of the first insulating part and the side traces provided by an embodiment of the present disclosure.
  • the first insulating part 71 has a The first side 71a extends in a first direction, and the first direction crosses the direction from the display area AA to the epitaxial area NA.
  • the part of the side wiring 4 located on the second surface 1b has a first end 4a close to the first side, and the orthographic projection of the first side 71a on the base substrate 1 is the same as that of the first end 4a on the base substrate 1
  • the distance d2 between the orthographic projections on the above is between 15 ⁇ m and 25 ⁇ m, so as to ensure that the first insulating part 71 completely covers the part of the side wiring 4 on the second surface 1b, and does not affect the passage of the first electrostatic protection part 51 through the second surface 1b.
  • the two via holes 62 are connected to the ground wire 3a.
  • d2 may be 15 ⁇ m or 18 ⁇ m or 20 ⁇ m or 22 ⁇ m or 25 ⁇ m.
  • the second insulating layer 7 further includes a third insulating portion 73, which is connected to the second insulating portion 72, and the third insulating portion 73 is disposed on the side wiring 4 located on the first side of the base substrate 1.
  • the part of one side 1a is away from the side of the base substrate 1, and the orthographic projection of the third insulating portion 73 on the base substrate 1 covers the part of the side wiring 4 located on the first side 1a of the base substrate 1 on the base substrate 1. Orthographic projection on .
  • the third insulating portion 73 has a second side extending away from the second insulating portion 72 and along the first direction, and the part of the side wiring 4 on the first surface 1 a has a second end close to the second side
  • the distance d3 between the orthographic projection of the second side on the base substrate 1 and the orthographic projection of the second end on the base substrate 1 is between 15 ⁇ m and 25 ⁇ m.
  • the second insulating part 72 , the first insulating part 71 and the third insulating part 73 can be of an integral structure, which can completely cover the side wiring 4 .
  • Fig. 9 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure. As shown in Fig. 9, in some embodiments, the display panel further includes: a third insulating layer 8, at least a part of the third insulating layer 8 is located on the first The second electrostatic protection portion 52 is away from the side of the side surface 1 c of the base substrate 1 .
  • the orthographic projection of the third insulating layer 8 on the base substrate side 1c covers the orthographic projection of the second electrostatic protection portion 52 on the side 1c, so that the third insulating layer 8 can at least play a role for the second electrostatic protection portion 52 Moreover, when a plurality of display panels are spliced to form a large-size display screen, the third insulating layer 8 can prevent the static electricity generated on the display panel from affecting the adjacent display panels.
  • the third insulating layer 8 may specifically include a fourth insulating portion 81 , a fifth insulating portion 82 and a sixth insulating portion 83 .
  • the fourth insulating portion 81 is located on the side of the first electrostatic protection portion 51 away from the base substrate
  • the fifth insulating portion 82 is located on the side of the second electrostatic protection portion 52 away from the side of the base substrate 1
  • the sixth insulating portion 83 is located on the side of the second electrostatic protection portion 52.
  • the three electrostatic protection parts 53 are away from the side of the base substrate 1 .
  • the orthographic projection of the fourth insulating portion 81 on the second surface 1b covers the orthographic projection of the first electrostatic protection portion 51 on the second surface 1b
  • the orthographic projection of the fifth insulating portion 82 on the side surface 1c covers the orthographic projection of the first electrostatic protection portion 51 on the second surface 1b
  • the orthographic projection of the second electrostatic protection portion 52 on the side surface 1c, the orthographic projection of the sixth insulating portion 83 on the base substrate 1 covers the orthographic projection of the third insulating portion 73 on the base substrate 1 and the third electrostatic protection portion 53 Orthographic projection on substrate substrate 1 .
  • FIG. 10 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • the fourth insulating portion 81 in the third insulating layer 8 is located on the second surface of the first electrostatic protection portion 51 away from the base substrate.
  • a portion of the first electrostatic protection portion 51 away from the edge of the display panel is exposed by the fourth insulating portion 81, wherein the width d4 of the portion of the first electrostatic protection portion 51 exposed by the fourth insulating portion 81 in the second direction can be Between 0.5 mm and 1.5 mm, for example, 0.5 mm or 1 mm or 1.5 mm.
  • Other structures of the display panel are the same as those in FIG. 9 above, and will not be repeated here.
  • the second direction is the direction from the display area AA to the epitaxial area NA.
  • the materials of the second insulating layer 7 and the third insulating layer 8 in the embodiment of the present disclosure may be inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, or epoxy resin materials. Not limited.
  • Fig. 11 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • the display panel further includes a driving structure 9, which is connected to a plurality of driving signal lines 3 for providing a plurality of driving signals Line 3 provides the drive signal.
  • the structures on the display panel in FIG. 11 except for the driving structure 9 may be the same as those in FIG. 9 above.
  • the third via hole 63 (see FIG. 5 and FIG. 11 ) is also provided on the first insulating layer 6, and the driving structure 9 is connected to the driving signal line 3 through the third via hole 63 of the first insulating layer 6.
  • the first via hole 61 is located near the edge of the display panel
  • the third via hole 63 is located near the middle of the display panel
  • the second via hole 62 is located between the third via hole 63 and the second via hole 62 .
  • the driving structure 9 is connected to each driving signal line 3 through the third via hole 63 .
  • Fig. 12 is a rear view of the display panel provided by the embodiment of the present disclosure.
  • the drive structure 9 may specifically include:
  • the flexible circuit board 92 is connected to the driving signal line 3 through the third via hole 63 , and the driving circuit board 92 provides the driving signal for the driving signal line 3 through the flexible circuit board 92 .
  • the conductive glue 93 when connecting the flexible circuit board 92 to the driving signal line 3, can be coated at the position of the third via hole 63, and then the flexible circuit board 92 is pressed against the base substrate 1, so that The binding electrode on the flexible circuit board 92 is connected to the driving signal line 3 through the conductive glue 93 in the third via hole 63.
  • the conductive glue 93 remaining in the third via hole 63 can also play a role in connecting the flexible circuit board 92. the fixation effect.
  • Fig. 13 is a schematic front view of the display structure layer provided by the embodiment of the present disclosure
  • Fig. 14 is a schematic view of the structure of the display structure layer provided by the embodiment of the present disclosure.
  • the display structure layer includes The light emitting element 11 further includes a pixel circuit connected to the light emitting element 11 .
  • the light emitting element 11 may be a micro light emitting diode, and its light emitting color may be blue, red or green.
  • a plurality of light emitting elements 11 can form a plurality of repeating units, and each repeating unit includes a red light emitting element R, a green light emitting element G and a blue light emitting element B.
  • Fig. 15 is a schematic diagram of the principle of a pixel circuit provided by an embodiment of the present disclosure.
  • the pixel circuit may specifically include: a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a switching transistor T4, a first light emission control Transistor T5, second light emission control transistor T6, second reset transistor T7, and first storage capacitor C1; wherein, the first pole of the first transistor T1 is connected to the initial voltage signal terminal Vint, and the second pole of the first reset transistor T1 is connected to the first A second terminal of the storage capacitor C1, a first pole of the threshold compensation transistor T2 and a control pole of the driving transistor T3, the control pole of the first reset transistor T1 is connected to the reset signal terminal Reset; the second pole of the threshold compensation transistor T2 is connected to the driving transistor The second pole of T3 and the first pole of the second light emission control transistor T6, the control pole of the threshold compensation transistor T2 is connected to the gate line Gate; the first pole of the driving transistor T3 is connected
  • Fig. 14 only shows some devices, such as: switching transistor T4, driving transistor T3, etc.
  • the transistor T4 and the driving transistor T3 are top-gate thin film transistors as an example for description.
  • the display structure layer 10 includes: a buffer layer 141 located on the base substrate 1; an active layer of the switching transistor T4 and an active layer of the driving transistor T3 located on the buffer layer 141 and arranged on the same layer; The active layer of the driving transistor T3 and the gate insulating layer 142 on the layer where the active layer is located, the gate insulating layer 142 can cover the display area AA and the epitaxial area NA; The gate of the switching transistor T4 and the gate of the driving transistor T3 arranged in layers; the fourth insulating layer 143 on the layer where the gate of the switching transistor T4 and the gate of the driving transistor T3 are located, the fourth insulating layer 143 can cover The display area AA and the epitaxial area NA; the source and drain of the switch transistor T4 located on the fourth insulating layer 143 and arranged in the same layer, the source and drain of the drive transistor T3, and connected to the source of the switch transistor T4 The data line; the source and drain of the switching transistor T4, the source and the drain of the driving transistor
  • Fig. 16 is a plan view of the encapsulation layer provided by the embodiment of the present disclosure.
  • the display panel may also be provided with an encapsulation layer 13, and the above encapsulation layer 13 is disposed on a plurality of light-emitting elements 11 away from the base substrate 1 side.
  • the encapsulation layer 13 may include: a plurality of light-transmitting parts, and a light-shielding part that separates the plurality of light-transmitting parts from each other. Light.
  • the material of the light-shielding portion may be a black insulating material, such as inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, or an epoxy resin material.
  • the light-transmitting part can be a hollow structure, or a film layer made of a transparent material.
  • the light-emitting element 11 adopts a micro light-emitting diode
  • its light-emitting direction is not collimated, but is emitted toward the surroundings, so that a part of the light will be directed to the base substrate 1, and the setting of the light-shielding part can prevent the light-emitting element 11 from
  • the metal structure of the base substrate 1 reflects light; in addition, the setting of the light-shielding portion can also prevent crosstalk of light between adjacent light-emitting elements 11 .
  • FIG. 17 is a schematic structural view of a display device provided by an embodiment of the present disclosure
  • FIG. 18 is a plan view of an outer frame provided by an embodiment of the present disclosure.
  • the display device provided by an embodiment of the present disclosure includes The above-mentioned display panel and the outer frame 14 , at least a part of the outer frame 14 is located on the side of the base substrate 1 away from the display signal line 16 .
  • the display device further includes an adhesive 15 , which is located on the side of the base substrate 1 away from the display signal line 16 and connected between the display panel and the outer frame 14 .
  • the outer frame 14 is fixedly connected to the cabinet of the splicing display device, so as to fix the display panel.
  • the structure of the display panel included in the display device in FIG. 17 is as shown in FIG. 9, wherein the fourth insulating portion 81 completely covers the first electrostatic protection portion 51, and the adhesive glue is only used to fix the outer surface. Box 14.
  • FIG. 19 is a schematic structural view of another display device provided by an embodiment of the present disclosure.
  • the bonding glue can be conductive glue
  • the outer frame can be an outer frame of metal material (for example, adopting a better and lighter aluminum frame with heat dissipation), so that the first electrostatic protection part 51 can pass through the conductive glue 15.
  • the outer frame 14 of metal material is connected, so that the static electricity on the first static protection part 51 can be led out through the metal frame, and then the static electricity can be released more fully to avoid affecting the display effect of the display panel.
  • the above-mentioned display device may be any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc.

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Abstract

一种显示面板和显示装置，显示面板包括：衬底基板（1），具有相对设置的第一面（1a）和第二面（1b），以及连接第一面（1a）和第二面（1b）的侧面（1c）；第一面（1a）包括显示区（AA）和外延区（NA）；多个第一绑定电极（2），位于外延区（NA），每个第一绑定电极（2）与位于第一面（1a）、且由显示区（AA）延伸至外延区（NA）的一条显示信号线（16）电连接；多条驱动信号线（3），设置在衬底基板（1）的第二面（1b）上，其中多条驱动信号线（3）中的至少一条为地线（3a）；多条侧面走线（4），每条侧面走线（4）经由侧面（1c）将一条驱动信号线（3）与一个第一绑定电极（2）电连接；静电防护层（5），与地线（3a）电连接，且静电防护层（5）在侧面（1c）的正投影与侧面走线（4）在侧面上（1c）的正投影至少部分重叠。

Description

显示面板和显示装置 技术领域
本公开涉及显示技术领域，具体涉及一种显示面板和显示装置。
背景技术
静电击穿是显示面板制程中由于静电大量累积，在电荷转移过程中遇到较细的走线或者导线交叉的地方，瞬间电流过大，从而对电子器件造成破坏的现象。在显示面板的制备过程或者测试过程中，一旦发生静电击穿现象会影响显示面板的良品率。
发明内容
本公开实施例提供一种显示面板和显示装置。
第一方面，本公开提供一种显示面板，包括：
衬底基板，具有相对设置的第一面和第二面，以及连接所述第一面和所述第二面的侧面；所述第一面包括显示区和外延区；
多个第一绑定电极，位于所述外延区，每个所述第一绑定电极与位于所述第一面、且由所述显示区延伸至所述外延区的一条显示信号线电连接；
多条驱动信号线，设置在所述衬底基板的第二面上，其中所述多条驱动信号线中的至少一条为地线；
多条侧面走线，每条所述侧面走线经由所述侧面将一条所述驱动信号线与一个所述第一绑定电极电连接；
静电防护层，与所述地线电连接，且所述静电防护层在所述侧面的正投影与所述侧面走线在所述侧面上的正投影至少部分重叠。
在一些实施例中，静电防护层至少包括：
相连的第一静电防护部和第二静电防护部，所述第一静电防护部位 于所述衬底基板的第二面上，且在所述第二面上的正投影，覆盖所述侧边走线位于所述第二面上的部分在所述第二面的正投影；所述第一静电防护部与所述地线连接；所述第二静电防护部在所述侧面的正投影覆盖所述侧面走线在所述侧面上的正投影。
在一些实施例中，显示面板还包括：
第一绝缘层，所述第一绝缘层位于所述多条驱动信号线远离所述衬底基板的一侧，每条所述侧面走线通过所述第一绝缘层上的第一过孔连接一条所述驱动信号线；
所述第一静电防护部位于所述第一绝缘层远离所述衬底基板的一侧，并通过所述第一绝缘层上的第二过孔与所述地线连接。
在一些实施例中，所述第一静电防护部远离所述第二静电防护部的边界在所述衬底基板上的正投影与所述第二过孔在所述衬底基板上的正投影之间的最近距离在15～25μm之间。
在一些实施例中，显示面板还包括：
第二绝缘层，设置在所述静电防护层靠近所述侧面走线的一侧；
其中，所述第二绝缘层包括：第一绝缘部和第二绝缘部，所述第一绝缘部位于所述第一静电防护部与所述侧面走线之间，所述第二绝缘部位于所述第二静电防护部与所述侧面走线之间，所述第一绝缘部在所述衬底基板上的正投影与所述第二过孔在所述衬底基板上的正投影无交叠。
在一些实施例中，所述第一绝缘部具有远离所述第二绝缘部、且沿第一方向延伸的第一侧边，所述第一方向与由所述显示区指向所述外延区的方向交叉；
所述侧面走线位于所述第二面上的部分具有靠近所述第一侧边的第一端部，所述第一侧边在所述衬底基板上的正投影与所述第一端部在所述衬底基板上的正投影之间的间隔在15～25μm之间。
在一些实施例中，所述第二绝缘层还包括：
第三绝缘部，所述第三绝缘部位于所述侧面走线位于所述第二面上的部分远离所述第二面一侧，且所述第三绝缘部与所述第二绝缘部连接；
所述第三绝缘部具有远离所述衬底基板的侧面、且沿第一方向延伸的第二侧边，所述第一方向与由所述显示区指向所述外延区的方向交叉；所述侧面走线位于所述第一面上的部分具有靠近所述第二侧边的第二端部，所述第二侧边与所述第二端部之间的间隔在15～25μm之间。
在一些实施例中，静电防护层还包括：
第三静电防护部，所述第三静电防护部位于所述衬底基板的第一面、且位于所述外延区内，所述第三静电防护部与所述第二静电防护部连接。
在一些实施例中，所述第一静电防护部、所述第二静电防护部和所述第三静电防护部连接为一体结构，所述第三静电防护部在所述第一面上的正投影沿第一方向贯穿所述第一面，所述第一静电防护部在所述第二面上的正投影沿所述第一方向贯穿所述第二面，其中，所述第一方向与由所述显示区指向所述外延区的方向交叉。
在一些实施例中，显示面板还包括：
第三绝缘层，所述第三绝缘层的至少一部分位于所述第二静电防护部远离所述衬底基板的侧面的一侧。
在一些实施例中，所述第三绝缘层覆盖所述第二静电防护部的全部和所述第一静电防护部的至少部分。
在一些实施例中，所述显示区包括多个子像素，每个子像素中设置有发光件，每个所述发光件与所述显示信号线连接。
在一些实施例中，显示面板还包括：
驱动结构，所述驱动结构与所述多条驱动信号线连接，用于为所述多条驱动信号线提供驱动信号。
在一些实施例中，显示面板还包括：
第一绝缘层，所述第一绝缘层位于所述多条驱动信号线远离所述衬 底基板的一侧，所述侧面走线通过所述第一绝缘层上的第一过孔与相应的驱动信号线连接；
其中，所述驱动结构通过所述第一绝缘层上的第三过孔与所述驱动信号线连接。
第二方面，本公开提供一种显示装置，包括：
第一方面所述的显示面板；
外框，所述外框的至少一部分位于所述衬底基板远离所述显示信号线的一侧；
粘结胶，所述粘结胶位于所述衬底基板远离所述显示信号线的一侧，并连接在所述显示面板与所述外框之间。
在一些实施例中，所述外框为金属框；
所述粘结胶为导电胶，且连接在所述金属框与所述静电防护层之间。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1为一个示例中提供的侧面线技术的示意图；
图2为本公开实施例中提供的显示面板上的显示结构层和第一绑定电极的平面图；
图3为本公开实施例提供的一种显示面板的结构示意图；
图4为本公开实施例提供的驱动信号线的平面图；
图5为本公开实施例中提供的第一绝缘层上的过孔与驱动信号线的平面图；
图6为本公开实施例提供的第一静电防护部和驱动信号线的平面图；
图7为本公开实施例提供的第三静电防护部的平面图；
图8为本公开实施例提供的第一绝缘部和侧面走线的平面图；
图9为本公开实施例提供的另一显示面板的结构示意图；
图10为本公开实施例提供的另一显示面板的结构示意图；
图11为本公开实施例提供的另一显示面板的结构示意图；
图12为本公开实施例提供的显示面板的后视图；
图13为本公开实施例提供的显示结构层的正面示意图；
图14为本公开实施例提供的显示结构层的结构示意图；
图15为本公开实施例提供的像素电路的原理示意图；
图16为本公开实施例提供的封装层的平面图；
图17为本公开实施例提供的一种显示装置的结构示意图；
图18为本公开实施例提供的外框的平面图；
图19为本公开实施例提供的另一显示装置的结构示意图。
具体实施方式
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，本公开实施例使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含” 等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
目前，微型发光二极管(Micro LED或Mini LED)显示技术正在日新月异地发展，由于其突出的优点：体积微型、低耗电、高色彩饱和度、反应速度快、寿命长等吸引了广大科技工作者的投入研究。但由于巨量转移技术还没有发展成熟，使得微型发光二极管显示器在高分辨率、大尺寸上的发展受到了阻碍。针对现有巨量转移技术的能力对应的是电视及巨幕显示，通过无缝拼接显示技术可以弥补当下巨量转移技术的不足实现大屏显示。在微型发光二极管拼接显示屏中要实现真正无缝拼接需要使用侧面线(Side wiring)技术。图1为一个示例中提供的侧面线技术的示意图，如图1所示，至少一条显示信号线由正面的显示区AA延伸至外延区NA，并与外延区NA中的第一绑定电极2连接，第一绑定电极2与侧面走线4连接，侧面走线4经由衬底基板1的侧面绕至衬底基板1背面，并与背面的驱动信号线3连接，驱动信号线与3驱动芯片进行绑定(IC bonding)等连接。
如图1所示，在通过无缝拼接显示技术形成大尺寸拼接显示屏时，为了防止显示面板的侧面走线对其相邻的显示面板造成干扰，需要在侧面走线4的外层设置绝缘保护层4A，以对相邻的显示面板进行间隔，避免影响拼接显示屏的显示效果。由于需要满足拼接显示屏的无缝拼接要求，因此绝缘保护层4A一般设置得较薄(例如在2-10μm的范围内)，这样，在显示面板的制备过程或者测试过程中，当显示面板的边缘位置产生静电时，绝缘保护层4A不能达到良好的静电防护效果。此时，需 要在静电防护层4A远离衬底基板1侧面的一侧通过导电胶或点银胶连接金属导电层，以释放静电。但由于导电胶或点银胶的厚度尺寸较大，将其设置在显示面板的侧面位置会影响到显示面板边框的宽度，不利于显示面板的窄边框设计，进而会影响拼接屏的显示效果。
为了解决上述技术问题，本公开实施例提供一种显示面板，在有效实现静电防护的同时，满足显示面板对窄边框的要求。
图2为本公开实施例中提供的显示面板上的显示结构层和第一绑定电极的平面图，图3为本公开实施例提供的一种显示面板的结构示意图，如图2、3所示，本公开实施例提供一种显示面板，包括：衬底基板1、多个第一绑定电极2、显示结构层10、多条侧面走线4以及静电防护层5。其中，衬底基板1具有相对设置的第一面1a和第二面1b，以及连接第一面和第二面的侧面1c，第一面包括显示区AA和外延区NA，外延区NA位于显示区AA的至少一侧，显示区AA包括多个子像素。显示结构层10包括多条显示信号线16和多个发光件，每个子像素中均设置有发光件，发光件例如为Micro LED或Mini LED等微型发光二极管。多条显示信号线16用于为多个发光件提供驱动信号，且至少部分显示信号线16从显示区延伸至外延区NA。
多个第一绑定电极2位于外延区NA，每个第一绑定电极2与由显示区AA延伸至外延区NA的一条显示信号线16电连接。在一个示例中，第一绑定电极2可以为矩形，其长度可以在0.08～0.2mm之间，宽度在0.06～0.1mm之间。
图4为本公开实施例提供的驱动信号线的平面图，如图4所示，多条驱动信号线3设置于第二面1b上，多条驱动信号线3中的至少一条为地线。每条侧面走线4经由侧面将一条驱动信号线3与一个第一绑定电极2电连接。其中，驱动信号线3远离侧面走线的一端可以与驱动结构9(例如，驱动电路板)连接，从而接收驱动结构9提供的驱动信号，侧 面走线4将驱动信号线3上的驱动信号传输至显示信号线16，进而提供给发光件。
静电防护层5与地线3a电连接，且静电防护层5在侧面1c的正投影覆盖侧面走线4在侧面1c上的正投影。本公开实施例对静电防护层的材料不作限定，例如静电防护层5可以为防腐蚀的金属材料，例如Ti。其中，显示面板上的侧面走线4可以通过溅射工艺制成。
需要说明的是，图3中衬底基板1的第一面1a与侧面1c交叉处的边缘位置形成有倒角N、第二面1b与侧面1c的交叉处的边缘位置也形成有倒角。上述倒角结构的形成，有利于在显示面板上通过溅射工艺制备侧面走线4，避免侧面走线4在边缘位置出现断裂，以及在衬底基板上沉积其他膜层时，避免在上述边缘位置出现断裂的情况。上述倒角N的宽度可以为d0，例如d0为衬底基板厚度的1/30～1/5，其尺寸具体不做限定。可选地，上述倒角N可以为斜切面，也可以是向外凸出的弧面结构。
本公开实施例中提供的其他显示面板的结构示意图中，虽然衬底基板是以边缘位置为直角结构为例进行示意的，但其边缘位置同样可以制作成如图3中所示的倒角结构，本公开对此不作限定。
可选地，多条驱动信号线3中至少一条为地线3a具体指：多条驱动信号线3中的部分为地线3a，另一部分为非地线3b。如图4所示，电防护层5与非地线3b之间通过绝缘层间隔开，以防止不同的驱动信号线3通过静电防护层5发生短路。本公开实施例中驱动信号线的材料为金属材料，其可以为单层金属，也可以为多层金属的叠加，例如Ti/AL/Ti，或Mo/Cu/Mo或Ti/Cu/Ti或Mo/Cu/ITO等，本公开实施例对此不作限定。其中，可以通过在衬底基板1的第二面1b上沉积金属层，并对金属层进行构图工艺的方式形成多条驱动信号线3。
在本公开实施例提供的显示面板中设置了静电防护层5，且静电防 护层5在侧面1c的正投影覆盖侧面走线4在侧面1c上的正投影，由于静电防护层5还与地线3a连接，因此，在静电测试过程中，显示面板侧面处产生的静电可以通过静电防护层导出，提升了显示面板的静电防护能力。另一方面，由于静电防护层5可以起到防静电的作用，因此，无需在显示面板侧面设置过厚的绝缘层或导电胶等结构，从而有利于显示面板实现窄边框。
在一些实施例中，静电防护层5的厚度可以设置在0.06～0.5μm之间，从而在达到良好的防静电效果的同时，减小静电防护层5对显示面板边框宽度的影响。
如图3所示，在一些实施例中，静电防护层5至少包括：相连的第一静电防护部51和第二静电防护部52，第一静电防护部51位于衬底基板的第二面1b上，且在第二面1b上的正投影覆盖侧边走线4位于第二面1b上的部分在第二面1b的正投影；第一静电防护部51与地线3a连接。第二静电防护部52与衬底基板1的侧面1c相对，且第二静电防护部52在侧面1c上的正投影与侧面走线4在侧面1c上的正投影至少部分重叠。可选地，在一个示例中，第二静电防护部52在侧面1c上的正投影可以覆盖侧面走线4在侧面1c上的正投影；在另一个示例中，第二静电防护部52在侧面1c上的正投影可以覆盖整个侧面1c。
如图3所示，在一些实施例中，显示面板还包括：第一绝缘层6，第一绝缘层6上设置有多个过孔，图5为本公开实施例中提供的第一绝缘层上的过孔与驱动信号线的平面图，如图3和图5所示，第一绝缘层6位于多条驱动信号线3远离衬底基板1的一侧，第一绝缘层6可以覆盖第二面1b的部分区域，也可以覆盖第二面1b的整个区域。第一绝缘层6上设置有多个第一过孔61，每条侧面走线4通过第一绝缘层6上的第一过孔61连接一条驱动信号线3。第一静电防护部51位于第一绝缘层6远离衬底基板1的一侧，并通过第一绝缘层6上的第二过孔62与地 线3a连接。
需要说明的是，本公开实施例是以侧面走线直接通过第一过孔61连接驱动信号线3为例进行说明的，在其他实施例中，还可以设置转接电极，转接电极的一部分位于第一过孔61中，通过转接电极将侧面走线4与驱动信号线3连接。
另外，第一绝缘层6对应于每条驱动信号线的位置还设置有第三过孔63，第三过孔63用于使驱动结构与每条驱动信号线连接。下文将对驱动结构进行说明，这里先不赘述。
其中，上述第一绝缘层的材料可以是氮化硅材料、氧化硅材料和氮氧化硅中的任一种，各过孔可以通过光刻构图工艺制成。
在一些实施例中，如图3所示，静电防护层5还可以包括：第三静电防护部53，第三静电防护部53与第二静电防护部52连接，第三静电防护部53位于衬底基板1的第一面1a、且位于外延区NA内，即第三静电防护部53不会延伸至显示区AA，因此第三静电防护部53的设置不会影响显示面板的显示功能。
在一些实施例中，第一静电防护部51、第二静电防护部52和第三静电防护部53连接为一体结构。图6为本公开实施例提供的第一静电防护部和驱动信号线的平面图，图7为本公开实施例提供的第三静电防护部的平面图。如图6所示，第三静电防护部53在第一面1a上的正投影沿第一方向贯穿第一面1a；如图7所示，第一静电防护部51在第二面1b上的正投影沿第一方向贯穿第二面1b。其中，第一方向与由显示区AA指向外延区NA的方向交叉，例如，第一方向与由显示区AA指向外延区NA的方向垂直。这种情况下，无论在哪个位置的侧面走线4上产生静电，静电防护层5均可以将静电导出，避免静电对显示面板内部的器件和/或电路造成损坏，提高显示面板的静电防护能力。
在一些实施例中，如图6所示，第一静电防护部51在衬底基板1 上的正投影完全覆盖第二过孔62在衬底基板1上的正投影，可选地，第一静电防护部51远离第二静电防护部52的边界在衬底基板1上的正投影与第二过孔62在衬底基板1上的正投影之间的最近距离d1在15μm～25μm之间，以保证第一静电防护部51与第二过孔62的连接可靠性。例如，d1可以为15μm或18μm或20μm或22μm或25μm。
在一些实施例中，如图3所示，显示面板还包括：第二绝缘层7，第二绝缘层7设置在静电防护层5靠近侧面走线4的一侧。
具体地，第二绝缘层7包括：第一绝缘部71和第二绝缘部72，第一绝缘部71位于第一静电防护部51与侧面走线4之间，第二绝缘部72位于第二静电防护部52与侧面走线4之间，第一绝缘部71在衬底基板1上的正投影与第二过孔62在衬底基板1上的正投影无交叠，即第一绝缘部71的边界未延伸至第二过孔62，其对第二过孔62与第一静电防护部51之间的连接不会造成影响。
图8为本公开实施例提供的第一绝缘部和侧面走线的平面图，在一些实施例中，如图3和图8所示，第一绝缘部71具有远离第二绝缘部72、且沿第一方向延伸的第一侧边71a，第一方向与由显示区AA指向外延区NA的方向交叉。侧面走线4位于第二面1b上的部分具有靠近第一侧边的第一端部4a，第一侧边71a在衬底基板1上的正投影与第一端部4a在衬底基板1上的正投影之间的间隔d2在15μm～25μm之间，以保证第一绝缘部71完全包覆侧面走线4位于第二面1b上的部分，且不影响第一静电防护部51通过第二过孔62与地线3a连接。例如，d2可以为15μm或18μm或20μm或22μm或25μm。
在一些实施例中，如图3所示，第二绝缘层7还包括第三绝缘部73，其连接第二绝缘部72，第三绝缘部73设置于侧面走线4位于衬底基板1第一面1a的部分远离衬底基板1的一侧，且第三绝缘部73在衬底基板1上的正投影覆盖侧面走线4位于衬底基板1第一面1a的部分在衬底基 板1上的正投影。
其中，第三绝缘部73具有远离第二绝缘部72、且沿第一方向延伸的第二侧边，侧面走线4位于第一面1a上的部分具有靠近第二侧边的第二端部，第二侧边在衬底基板1上的正投影与第二端部在衬底基板1上的正投影之间的间隔d3在15μm～25μm之间。
其中，第二绝缘部72、第一绝缘部71和第三绝缘部73可以为一体结构，其可以将侧面走线4完全包覆。
图9为本公开实施例提供的另一显示面板的结构示意图，如图9所示，在一些实施例中，显示面板还包括：第三绝缘层8，第三绝缘层8的至少一部分位于第二静电防护部52远离衬底基板1的侧面1c的一侧。
其中，第三绝缘层8在衬底基板侧面1c上的正投影覆盖第二静电防护部52在侧面1c上的正投影，这样，第三绝缘层8至少可以对第二静电防护部52起到保护作用，并且，在多个显示面板进行拼接以形成大尺寸显示屏时，第三绝缘层8可以避免显示面板上产生的静电影响到与其相邻的显示面板。
在一个示例中，如图9所示，第三绝缘层8具体可以包括第四绝缘部81、第五绝缘部82和第六绝缘部83。第四绝缘部81位于第一静电防护部51远离衬底基板的一侧，第五绝缘部82位于第二静电防护部52远离衬底基板1的侧面的一侧，第六绝缘部83位于第三静电防护部53远离衬底基板1的一侧。在一个示例中，第四绝缘部81在第二面1b上的正投影覆盖第一静电防护部51在第二面1b上的正投影，第五绝缘部82在侧面1c上的正投影覆盖第二静电防护部52在侧面1c上的正投影，第六绝缘部83在衬底基板1上的正投影覆盖第三绝缘部73在衬底基板1上的正投影、以及第三静电防护部53在衬底基板1上的正投影。
图10为本公开实施例提供的另一显示面板的结构示意图，如图10所示，第三绝缘层8中的第四绝缘部81位于第一静电防护部51远离衬 底基板的第二面一侧，且第一静电防护部51在第二面1b上的正投影超出第四绝缘部81在第二面1b上的正投影。例如，第一静电防护部51远离显示面板边缘的一部分被第四绝缘部81暴露出，其中，第一静电防护部51被第四绝缘部81暴露出的部分在第二方向上的宽度d4可以在0.5mm～1.5mm之间，例如为0.5mm或1mm或1.5mm。显示面板的其他结构与上述图9中相同，在此不再赘述。第二方向为由显示区AA指向外延区NA的方向。
另外，本公开实施例中的第二绝缘层7和第三绝缘层8的材料可以是氮化硅、氧化硅、氮氧化硅等无机材料，也可以是环氧树脂类材料，本公开对此不作限定。
图11为本公开实施例提供的另一显示面板的结构示意图，在一些实施例中，显示面板还包括驱动结构9，驱动结构9与多条驱动信号线3连接，用于为多条驱动信号线3提供驱动信号。此处，图11中显示面板上除驱动结构9之外的结构可以与上述图9中相同。
如上所述，第一绝缘层6上还设置有第三过孔63(参见图5和图11所示)，驱动结构9通过第一绝缘层6的第三过孔63与驱动信号线3连接。其中，第一过孔61位于靠近显示面板边缘的位置，第三过孔63位于靠近显示面板中部的位置，第二过孔62位于第三过孔63与第二过孔62之间。驱动结构9通过第三过孔63与每条驱动信号线3连接。
图12为本公开实施例提供的显示面板的后视图，如图11和图12所示，驱动结构9具体可以包括：驱动电路板91和柔性线路板92，其中，驱动电路板91与柔性线路板92连接，柔性线路板92通过第三过孔63与驱动信号线3连接，驱动电路板92通过柔性线路板92为驱动信号线3提供驱动信号。
在一些实施例中，将柔性线路板92与驱动信号线3连接时，可以在第三过孔63的位置涂覆导电胶93，之后，将柔性线路板92与衬底基板 1压合，从而使柔性线路板92上的绑定电极通过第三过孔63内的导电胶93与驱动信号线3连接，另外，残留在第三过孔63的导电胶93还可以起到对柔性线路板92的固定作用。
图13为本公开实施例提供的显示结构层的正面示意图，图14为本公开实施例提供的显示结构层的结构示意图，如图13和图14所示，显示结构层包括位于每个子像素中的发光件11，还包括与发光件11连接的像素电路。其中，发光件11可以为微型发光二极管，其发光颜色可以为蓝色、红色或绿色。在一个示例中，多个发光件11可以组成多个重复单元，每个重复单元包括红色发光件R、绿色发光件G和蓝色发光件B。
图15为本公开实施例提供的像素电路的原理示意图，如图15所示，像素电路具体可以包括：第一复位晶体管T1、阈值补偿晶体管T2、驱动晶体管T3、开关晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6、第二复位晶体管T7、第一存储电容C1；其中，第一晶体管T1的第一极连接初始电压信号端Vint，第一复位晶体管T1的第二极连接第一存储电容C1的第二端、阈值补偿晶体管T2的第一极和驱动晶体管T3的控制极，第一复位晶体管T1的控制极连接复位信号端Reset；阈值补偿晶体管T2的第二极连接驱动晶体管T3的第二极和第二发光控制晶体管T6的第一极，阈值补偿晶体管T2的控制极连接栅线Gate；驱动晶体管T3的第一极连接第一电源电压端VD；开关晶体管T4的第一极连接数据线Data，开关晶体管T4的第二极连接第一发光控制晶体管T5的第二极、第二复位晶体管T7的第二极和第一存储电容C1的第一极；开关晶体管T4的控制极连接栅线；第一发光控制晶体管T5的第一极连接基准电压信号端Vref，第一发光控制晶体管T5的控制极连接发光控制线EM；第二发光控制晶体管T6的第二极连接发光件11的第一极，第二发光控制晶体管T6的控制极连接发光控制线EM；第二复位晶体管T7的第一极连接基准电压信号端Vref，第二复位晶体管T7的控制 极连接复位信号端Reset，发光件11的第二极连接第二电源电压端VSS。
下面对图14所示的显示结构层中各膜层的位置关系进行说明，应当理解的是，图14中只是示意了部分器件，例如：开关晶体管T4、驱动晶体管T3等，其中，以开关晶体管T4和驱动晶体管T3为顶栅型薄膜晶体管为例进行说明。
该显示结构层10包括：位于衬底基板1上的缓冲层141；位于缓冲层141之上、且同层设置的开关晶体管T4的有源层和驱动晶体管T3的有源层；位于开关晶体管T4的有源层和驱动晶体管T3的有源层所在层之上的栅极绝缘层142，该栅极绝缘层142可以覆盖显示区AA和外延区NA；位于栅极绝缘层142之上、且同层设置的开关晶体管T4的栅极和驱动晶体管T3的栅极；位于开关晶体管T4的栅极和驱动晶体管T3的栅极所在层之上的第四绝缘层143，该第四绝缘层143可以覆盖显示区AA和外延区NA；位于第四绝缘层143之上，且同层设置的开关晶体管T4的源极和漏极，驱动晶体管T3的源极和漏极，以及与开关晶体管T4源极连接的数据线；位于开关晶体管T4的源极和漏极，驱动晶体管T3的源极和漏极，以及与开关晶体管T4源极连接的数据线所在层之上的第一平坦化层144，该第一平坦化层144仅位于显示区AA；位于第一平坦化层144之上的第一钝化层145，该第一钝化层145覆盖显示区AA和外延区NA；位于第一平坦化层144至上，且同层设置的第二子信号引入线14b和第一连接电极14c；第二子信号引入线14b通过贯穿第一平坦化层144和第一钝化层145的第四过孔与数据线连接，第一连接电极14c通过贯穿第一平坦化层144和第一钝化层145的第四过孔与驱动晶体管T3的漏极连接；位于第二子信号引入线14b和第一连接电极14c所在层之上的第二平坦化层146，该第二平坦化层146仅位于显示区AA；位于第二平坦化层146之上的第二钝化层147，该第二钝化层147可以覆盖显示区AA和外延区NA；位于第二钝化层147之上，且同层 设置的第一子信号引入线14a、第一衬垫14d、第二衬垫14e；第一子信号引入线14a由显示区AA延伸至外延区NA，且通过贯穿第二平坦化层146和第二钝化层147的第五过孔与第二子信号引入线14b连接；第一衬垫14d通过贯穿第二平坦化层146和第二钝化层147的第五过孔与第一连接电极14c连接；位于第一子信号引入线14a、第一衬垫14d、第二衬垫14e之上的第三钝化层148，该第三钝化层148可以覆盖显示区AA和外延区NA；位于外延区NA、且在第三钝化层148之上第一绑定电极2，第一绑定电极2通过贯穿第三钝化层148的第六过孔与第一子信号引入线14a连接；发光件11的第一极通过贯穿第三钝化层148的第七过孔与第一衬垫14d连接，发光件11的第二极通过贯穿第三钝化层148的第八过孔与第二衬垫14e连接。
需要说明的是，上述像素结构仅为示意性说明，在其他示例中，像素结构也可以采用其他结构。
图16为本公开实施例提供的封装层的平面图，在一些实施例中，如图16所示，显示面板还可以设置封装层13，上述封装层13设置于多个发光件11远离衬底基板1一侧。其中，封装层13可以包括：多个透光部、以及将多个透光部彼此间隔开的遮光部，透光部与发光件11一一对应设置，用于透过发光件11所发射的光。其中，遮光部的材料可以为黑色绝缘材料，例如氮化硅、氧化硅、氮氧化硅等无机材料，也可以为环氧树脂类树脂材料。透光部可以为镂空结构，也可以为透明材料制成的膜层。
当发光件11采用微发光二极管时，其发光方向并不是准直的，而是朝向四周发射，这样就会有一部分光射向衬底基板1，而遮光部的设置，可以防止发光件11与衬底基板1的金属结构对光线造成反射；另外，遮光部的设置还可以防止相邻发光件11之间的光发生串扰。
图17为本公开实施例提供的一种显示装置的结构示意图，图18为 本公开实施例提供的外框的平面图，如图17和图18所示，本公开实施例提供的显示装置，包括上述显示面板以及外框14，外框14的至少一部分位于衬底基板1远离显示信号线16的一侧。显示装置还包括粘结胶15，粘结胶15位于衬底基板1远离显示信号线16的一侧，并连接在显示面板与外框14之间。
在拼接显示装置中，外框14与拼接显示装置的箱体进行固定连接，从而对显示面板进行固定。
在一个示例中，图17中的显示装置所包括的显示面板的结构如图9所示，其中，第四绝缘部81完全覆盖第一静电防护部51，此时粘接胶仅用于固定外框14。
图19为本公开实施例提供的另一显示装置的结构示意图，如图19所示，其显示装置所包括的显示面板的结构如图10所示，其中，第四绝缘部81并未完全覆盖第一静电防护部51。此时，粘接胶可以为导电胶，外框可以为金属材料的外框(例如，采用散热性较好且较轻便的铝框)，这样可以使第一静电防护部51可以通过导电胶15连接金属材料的外框14，从而可以将第一静电防护部51上的静电通过金属框导出，进而可以对静电进行更充分的释放，避免对显示面板的显示效果造成影响。
需要说明的是，上述显示装置可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (16)

  1. 一种显示面板，其中，包括：
    衬底基板，具有相对设置的第一面和第二面，以及连接所述第一面和所述第二面的侧面；所述第一面包括显示区和外延区；
    多个第一绑定电极，位于所述外延区，每个所述第一绑定电极与位于所述第一面、且由所述显示区延伸至所述外延区的一条显示信号线电连接；
    多条驱动信号线，设置在所述衬底基板的第二面上，其中所述多条驱动信号线中的至少一条为地线；
    多条侧面走线，每条所述侧面走线经由所述侧面将一条所述驱动信号线与一个所述第一绑定电极电连接；
    静电防护层，与所述地线电连接，且所述静电防护层在所述侧面的正投影与所述侧面走线在所述侧面上的正投影至少部分重叠。
  2. 根据权利要求1所述的显示面板，其中，所述静电防护层至少包括：
    相连的第一静电防护部和第二静电防护部，所述第一静电防护部位于所述衬底基板的第二面上，且在所述第二面上的正投影，覆盖所述侧边走线位于所述第二面上的部分在所述第二面的正投影；所述第一静电防护部与所述地线连接；所述第二静电防护部在所述侧面的正投影覆盖所述侧面走线在所述侧面上的正投影。
  3. 根据权利要求2所述的显示面板，其中，所述显示面板还包括：
    第一绝缘层，所述第一绝缘层位于所述多条驱动信号线远离所述衬底基板的一侧，每条所述侧面走线通过所述第一绝缘层上的第一过孔连 接一条所述驱动信号线；
    所述第一静电防护部位于所述第一绝缘层远离所述衬底基板的一侧，并通过所述第一绝缘层上的第二过孔与所述地线连接。
  4. 根据权利要求3所述的显示面板，其中，所述第一静电防护部远离所述第二静电防护部的边界在所述衬底基板上的正投影与所述第二过孔在所述衬底基板上的正投影之间的最近距离在15～25μm之间。
  5. 根据权利要求3所述的显示面板，其中，所述显示面板还包括：
    第二绝缘层，设置在所述静电防护层靠近所述侧面走线的一侧；
    其中，所述第二绝缘层包括：第一绝缘部和第二绝缘部，所述第一绝缘部位于所述第一静电防护部与所述侧面走线之间，所述第二绝缘部位于所述第二静电防护部与所述侧面走线之间，所述第一绝缘部在所述衬底基板上的正投影与所述第二过孔在所述衬底基板上的正投影无交叠。
  6. 根据权利要求5所述的显示面板，其中，所述第一绝缘部具有远离所述第二绝缘部、且沿第一方向延伸的第一侧边，所述第一方向与由所述显示区指向所述外延区的方向交叉；
    所述侧面走线位于所述第二面上的部分具有靠近所述第一侧边的第一端部，所述第一侧边在所述衬底基板上的正投影与所述第一端部在所述衬底基板上的正投影之间的间隔在15～25μm之间。
  7. 根据权利要求5所述的显示面板，其中，所述第二绝缘层还包括：
    第三绝缘部，所述第三绝缘部位于所述侧面走线位于所述第二面上的部分远离所述第二面一侧，且所述第三绝缘部与所述第二绝缘部连接；
    所述第三绝缘部具有远离所述衬底基板的侧面、且沿第一方向延伸 的第二侧边，所述第一方向与由所述显示区指向所述外延区的方向交叉；所述侧面走线位于所述第一面上的部分具有靠近所述第二侧边的第二端部，所述第二侧边与所述第二端部之间的间隔在15～25μm之间。
  8. 根据权利要求2所述的显示面板，其中，所述静电防护层还包括：
    第三静电防护部，所述第三静电防护部位于所述衬底基板的第一面、且位于所述外延区内，所述第三静电防护部与所述第二静电防护部连接。
  9. 根据权利要求8所述的显示面板，其中，所述第一静电防护部、所述第二静电防护部和所述第三静电防护部连接为一体结构，所述第三静电防护部在所述第一面上的正投影沿第一方向贯穿所述第一面，所述第一静电防护部在所述第二面上的正投影沿所述第一方向贯穿所述第二面，其中，所述第一方向与由所述显示区指向所述外延区的方向交叉。
  10. 根据权利要求2所述的显示面板，其中，所述显示面板还包括：
    第三绝缘层，所述第三绝缘层的至少一部分位于所述第二静电防护部远离所述衬底基板的侧面的一侧。
  11. 根据权利要求10所述的显示面板，其中，所述第三绝缘层覆盖所述第二静电防护部的全部和所述第一静电防护部的至少部分。
  12. 根据权利要求1至11中任一项所述的显示面板，其中，所述显示区包括多个子像素，每个子像素中设置有发光件，每个所述发光件与所述显示信号线连接。
  13. 根据权利要求1至11中任一项所述的显示面板，其中，所述显 示面板还包括：
    驱动结构，所述驱动结构与所述多条驱动信号线连接，用于为所述多条驱动信号线提供驱动信号。
  14. 根据权利要求13所述的显示面板，其中，所述显示面板还包括：
    第一绝缘层，所述第一绝缘层位于所述多条驱动信号线远离所述衬底基板的一侧，所述侧面走线通过所述第一绝缘层上的第一过孔与相应的驱动信号线连接；
    其中，所述驱动结构通过所述第一绝缘层上的第三过孔与所述驱动信号线连接。
  15. 一种显示装置，其中，所述显示装置包括：
    权利要求1至14中任一项所述的显示面板；
    外框，所述外框的至少一部分位于所述衬底基板远离所述显示信号线的一侧；
    粘结胶，所述粘结胶位于所述衬底基板远离所述显示信号线的一侧，并连接在所述显示面板与所述外框之间。
  16. 根据权利要求15所述的显示装置，其中，
    所述外框为金属框；
    所述粘结胶为导电胶，且连接在所述金属框与所述静电防护层之间。
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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100156857A1 (en) * 2008-12-19 2010-06-24 Kabushiki Kaisha Toshiba Display device
CN104698710A (zh) * 2015-04-01 2015-06-10 上海天马微电子有限公司 一种阵列基板以及液晶显示装置
CN111668275A (zh) * 2020-06-19 2020-09-15 京东方科技集团股份有限公司 显示面板、其制作方法及显示装置
CN212256800U (zh) * 2020-09-24 2020-12-29 京东方科技集团股份有限公司 显示面板、显示装置及拼接显示装置
US20210066674A1 (en) * 2019-09-02 2021-03-04 Samsung Display Co., Ltd. Method of manufacturing display device and manufacturing device for display device
CN112599535A (zh) * 2020-12-10 2021-04-02 深圳市华星光电半导体显示技术有限公司 显示面板和显示装置
CN113342203A (zh) * 2021-06-10 2021-09-03 业成科技（成都）有限公司 触控模组以及触控显示装置
CN113920895A (zh) * 2021-10-25 2022-01-11 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN113994414A (zh) * 2019-05-31 2022-01-28 三星电子株式会社 包括抗静电接地电路板的微型led显示器

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100156857A1 (en) * 2008-12-19 2010-06-24 Kabushiki Kaisha Toshiba Display device
CN104698710A (zh) * 2015-04-01 2015-06-10 上海天马微电子有限公司 一种阵列基板以及液晶显示装置
CN113994414A (zh) * 2019-05-31 2022-01-28 三星电子株式会社 包括抗静电接地电路板的微型led显示器
US20210066674A1 (en) * 2019-09-02 2021-03-04 Samsung Display Co., Ltd. Method of manufacturing display device and manufacturing device for display device
CN111668275A (zh) * 2020-06-19 2020-09-15 京东方科技集团股份有限公司 显示面板、其制作方法及显示装置
CN212256800U (zh) * 2020-09-24 2020-12-29 京东方科技集团股份有限公司 显示面板、显示装置及拼接显示装置
CN112599535A (zh) * 2020-12-10 2021-04-02 深圳市华星光电半导体显示技术有限公司 显示面板和显示装置
CN113342203A (zh) * 2021-06-10 2021-09-03 业成科技（成都）有限公司 触控模组以及触控显示装置
CN113920895A (zh) * 2021-10-25 2022-01-11 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

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