WO2024000292A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2024000292A1
WO2024000292A1 PCT/CN2022/102429 CN2022102429W WO2024000292A1 WO 2024000292 A1 WO2024000292 A1 WO 2024000292A1 CN 2022102429 W CN2022102429 W CN 2022102429W WO 2024000292 A1 WO2024000292 A1 WO 2024000292A1
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WIPO (PCT)
Prior art keywords
test
line
signal
area
connection line
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PCT/CN2022/102429
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English (en)
French (fr)
Inventor
卢彦伟
闫卓然
石佺
秦成杰
程羽雕
王胜森
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280002056.3A priority Critical patent/CN117678344A/zh
Priority to PCT/CN2022/102429 priority patent/WO2024000292A1/zh
Publication of WO2024000292A1 publication Critical patent/WO2024000292A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Definitions

  • This article relates to but is not limited to the field of display technology, and specifically refers to a display substrate and a display device.
  • LCD liquid crystal displays
  • OLED organic light-emitting diode
  • PDP plasma display panels
  • FED Field Emission Display
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • a display substrate including: a substrate, a first power line provided on the substrate, a plurality of first signal lead lines, a plurality of test connection lines, and at least one first connection line. And multiple test signal access pins.
  • the substrate at least includes: a display area and a peripheral area located on one side of the display area.
  • the first power cord is located in the perimeter area.
  • a plurality of first signal lead-out lines, a plurality of test connection lines, a plurality of test signal access pins and at least one first connection line are located on a side of the first power line away from the display area. At least one first signal lead-out line is electrically connected to at least one test signal access pin through at least one test connection line.
  • the first connection line is located on one side of the plurality of test connection traces and the plurality of test signal access pins near the edge of the peripheral area in the first direction.
  • the first connection line extends at least along the second direction and is connected with the first power line. Electrical connection.
  • the first direction intersects the second direction.
  • the first connection line, the first power line and the plurality of test connection traces are located on the plurality of first signal leads. lines away from the side of the substrate.
  • the first connection line, the first power line and the plurality of test connection traces are in the same layer structure.
  • an orthographic projection of the first connection line on the substrate overlaps with an orthographic projection of the plurality of first signal lead-out lines on the substrate.
  • the peripheral area at least includes: at least one test signal access area located on one side of the display area, at least one first auxiliary mark and at least one second auxiliary mark; the second auxiliary mark The mark is located on a side of the first auxiliary mark away from the test signal access area in the first direction.
  • the first connection line and the second auxiliary mark are aligned in the second direction.
  • the first connection line is electrically connected to the second auxiliary mark.
  • the first connection line and the second auxiliary mark are an integral structure.
  • the peripheral area at least includes: at least one test signal access area located on one side of the display area, at least one first auxiliary mark and at least one second auxiliary mark; the second auxiliary mark The mark is located on a side of the first auxiliary mark away from the test signal access area in the first direction.
  • the first connecting line is located between the first auxiliary mark and the second auxiliary mark in the first direction.
  • the display substrate further includes: at least one auxiliary power pin, the auxiliary power pin is located between the first auxiliary mark and the second auxiliary mark in the first direction, the The first connection line is electrically connected to the auxiliary power pin.
  • the at least one first signal lead-out trace has a first bending portion protruding toward the side of the second auxiliary mark; the at least one test connection trace is connected to the first The first bending portion of the signal lead-out line is electrically connected.
  • An orthographic projection of the first connection line on the substrate overlaps with an orthographic projection of the first bending portion of the first signal lead-out line on the substrate.
  • the at least one first signal lead-out trace has a first bending portion protruding toward the side of the second auxiliary mark; the at least one test connection trace is connected to the first The first bending portion of the signal lead-out line is electrically connected.
  • the orthographic projection of the first connection line on the substrate does not overlap with the orthographic projection of the first bending portion of the first signal lead-out line on the substrate, and the third signal lead-out line A bending portion is located on a side of the first connection line close to the test signal access area.
  • the first auxiliary mark is electrically connected to the adjacent second auxiliary mark through a third connection line.
  • the first auxiliary mark, the third connecting line and the second auxiliary mark are an integral structure.
  • the peripheral area further includes: a first area located between the display area and the test signal access area.
  • the plurality of test signal access pins are located in the test signal access area, and the first power line, the plurality of first signal lead lines and the plurality of test connection traces are located at least in the first area.
  • the peripheral area further includes: a signal access area located on one side of the display area along the second direction, the signal access area being in contact with the first direction
  • the test signal access area is adjacent;
  • the signal access area includes: a plurality of signal access pins provided on the substrate; the at least one first signal lead-out line is electrically connected to the at least one signal access pin. connect.
  • the display substrate further includes: a second connection line electrically connected to the first power line, and the second connection line is located between the plurality of first signal lead-out lines away from the display area. one side.
  • the second connection line and the first power line are an integral structure.
  • the display substrate further includes: a first peripheral power connection line electrically connected to the first power line, the first peripheral power connection line being located near the first power line and the substrate on one side; the second connection line and the first peripheral power connection line are of an integrated structure.
  • the plurality of first signal lead-out lines are configured to transmit at least one of the following signals: a scan start signal, a scan clock signal, a light-emitting start signal, a light-emitting clock signal, a driving power signal, a test signal Data signals, test control signals.
  • embodiments of the present disclosure provide a display device including the display substrate as described above.
  • Figure 1 is a schematic diagram of the appearance of a display device
  • Figure 2 is a schematic structural diagram of a display device
  • Figure 3 is a partial cross-sectional structural diagram of a display area of a display substrate
  • Figure 4 is an equivalent circuit diagram of a pixel circuit
  • Figure 5 is a schematic diagram of a first frame of a display substrate according to at least one embodiment of the present disclosure
  • Figure 6 is a schematic diagram of the first flat layer of the first frame according to at least one embodiment of the present disclosure.
  • Figure 7 is a partial schematic diagram of the signal access area and the test signal access area of at least one embodiment of the present disclosure
  • Figure 8 is an example diagram of wiring in the peripheral area of at least one embodiment of the present disclosure.
  • Figure 9 is a partial enlarged schematic diagram of area C1 in Figure 5;
  • Figure 10 is a partial cross-sectional schematic diagram along the P-P’ direction in Figure 9;
  • Figure 11A is a schematic diagram of the first gate metal layer in Figure 9;
  • Figure 11B is a schematic diagram of the first source and drain metal layer in Figure 9;
  • Figure 12 is a partial enlarged schematic diagram of area C2 in Figure 9;
  • Figure 13 is a partial cross-sectional view along the R-R’ direction in Figure 12;
  • Figure 14 is another partially enlarged schematic diagram of the first frame of at least one embodiment of the present disclosure.
  • Figure 15 is a schematic diagram of the first gate metal layer in Figure 14;
  • Figure 16 is another partially enlarged schematic diagram of the first frame of at least one embodiment of the present disclosure.
  • Figure 17 is another partially enlarged schematic diagram of the first frame of at least one embodiment of the present disclosure.
  • Figure 18 is another partially enlarged schematic diagram of the first frame of at least one embodiment of the present disclosure.
  • Figure 19 is another partially enlarged schematic diagram of the first frame of at least one embodiment of the present disclosure.
  • FIG. 20 is another partially enlarged schematic diagram of the first frame according to at least one embodiment of the present disclosure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • electrical connection includes the case where the constituent elements are connected together through an element having some electrical effect.
  • element having some electrical function There is no particular limitation on the "element having some electrical function” as long as it can transmit electrical signals between connected components.
  • elements with some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions.
  • a transistor refers to an element including at least three terminals: a gate, a drain, and a source.
  • a transistor has a channel region between a drain (drain electrode terminal, drain region, or drain electrode) and a source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source .
  • the channel region refers to a region through which current mainly flows.
  • one of the electrodes is called the first pole, and the other electrode is called the second pole.
  • the first pole can be the source or the drain
  • the second pole can be is the drain or source
  • the gate of the transistor is called the control electrode.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • triangles, rectangles, trapezoids, pentagons or hexagons are not strictly defined. They can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small differences caused by tolerances. Deformation can include leading angles, arc edges, deformation, etc.
  • a extending along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, line segment or bar-shaped body, the main part extends along direction B, and the main part The length of the portion extending along direction B is greater than the length of the minor portion extending along the other directions.
  • a extends along direction B means “the main body part of A extends along direction B".
  • Figure 1 is a schematic diagram of the appearance of a display device, which has a rectangular shape with rounded corners.
  • the display device may include a display substrate.
  • the display substrate may be a closed polygon including linear sides, a circle or an ellipse including curved sides, a semicircle or semi-ellipse including linear sides and curved sides, or the like.
  • the base substrate has linear edges, at least some corners of the base substrate may be curved.
  • a portion where adjacent linear sides meet each other may be replaced with a curve having a predetermined curvature.
  • the curvature can be set according to the different positions of the curve. For example, the curvature can be changed based on where the curve starts, the length of the curve, etc.
  • the display substrate may include a display area AA and a peripheral area BB located around the display area.
  • the display area AA may include a first edge (lower edge) and a second edge (upper edge) oppositely arranged in the second direction Y, and a third edge (left edge) oppositely arranged in the first direction X. edge) and the fourth edge (right edge). Adjacent edges can be connected by arc-shaped chamfers to form a rounded quadrilateral shape.
  • the peripheral area BB may include: a first border (lower frame) B1 and a second border (upper border) B2 that are relatively disposed in the second direction Y, and a third border that is relatively disposed in the first direction X. (left border) B3 and the fourth border (right border) B4.
  • the first frame B1 is connected to the third frame B3 and the fourth frame B4, and the second frame B2 is connected to the third frame B3 and the fourth frame B4.
  • the display area AA at least includes a plurality of sub-pixels PX, a plurality of gate lines G, and a plurality of data lines D.
  • the plurality of gate lines G may extend along the first direction X
  • the plurality of data lines D may extend along the second direction Y.
  • Orthographic projections of the plurality of gate lines G and the plurality of data lines D on the base substrate intersect to form a plurality of sub-pixel areas, and one sub-pixel PX is provided in each sub-pixel area.
  • the plurality of data lines D are electrically connected to the plurality of sub-pixels PX, and the plurality of data lines D may be configured to provide data signals to the plurality of sub-pixels PX.
  • the plurality of gate lines G are electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines G may be configured to provide gate control signals to the plurality of sub-pixels PX.
  • the gate control signal may include a scan signal and a lighting control signal.
  • the first direction X may be the extending direction (row direction) of the gate line G in the display area
  • the second direction Y may be the extending direction (column direction) of the data line D in the display area.
  • the first direction X and the second direction Y may be perpendicular to each other.
  • one pixel unit of the display area AA may include three sub-pixels, and the three sub-pixels are red sub-pixels, green sub-pixels and blue sub-pixels respectively.
  • this embodiment is not limited to this.
  • one pixel unit may include four sub-pixels, which are red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels.
  • the shape of the subpixel may be a rectangle, a diamond, a pentagon, or a hexagon.
  • a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically or squarely.
  • the four sub-pixels can be arranged horizontally, vertically or squarely. ) arrangement.
  • this embodiment is not limited to this.
  • a sub-pixel may include: a pixel circuit and a light-emitting element connected to the pixel circuit.
  • the pixel circuit may include a plurality of transistors and at least one capacitor.
  • the pixel circuit may be a 3T1C (ie, 3 transistors and 1 capacitor) structure, a 7T1C (ie, 7 transistors and 1 capacitor) structure, or a 5T1C (ie, 5 transistors) structure. and 1 capacitor) structure, 8T1C (ie 8 transistors and 1 capacitor) structure or 8T2C (ie 8 transistors and 2 capacitors) structure, etc.
  • the light-emitting element may be a light-emitting diode (LED, Light Emitting Diode), an organic light-emitting diode (OLED, Organic Light Emitting Diode), a quantum dot light-emitting diode (QLED, Quantum Dot Light Emitting Diodes), or a micro-LED (including: Any of mini-LED or micro-LED), etc.
  • the light-emitting element can be an OLED, and the light-emitting element can emit red light, green light, blue light, or white light, etc., driven by its corresponding pixel circuit.
  • the color of the light-emitting element can be determined according to needs.
  • the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.
  • the anode of the light-emitting element may be electrically connected to the corresponding pixel circuit.
  • this embodiment is not limited to this.
  • Figure 2 is a schematic structural diagram of a display device.
  • the display device may include: a timing controller 21 , a data driver 22 , a scan driving circuit 23 , a light emitting driving circuit 24 and a display substrate 25 .
  • the display area of the display substrate 25 may include a plurality of regularly arranged sub-pixels PX.
  • the scan driving circuit 23 may be configured to provide scan signals to the sub-pixels PX along the scan lines; the data driver 22 may be configured to provide data voltages to the sub-pixels PX along the data lines; and the light-emitting driving circuit 24 may be configured to emit light along the light-emitting control lines.
  • the control signal is provided to the sub-pixel PX; the timing controller 21 may be configured to control the scan driving circuit 23, the light emitting driving circuit 24, and the data driver 22.
  • the timing controller 21 can provide grayscale values and control signals suitable for the specifications of the data driver 22 to the data driver 22; the timing controller 21 can provide the scan clock signal, scan signal, and scan signal suitable for the specifications of the scan driver 23.
  • the start signal and the like are supplied to the scan drive circuit 23; the timing controller 21 can provide a light-emission clock signal, a light-emission start signal, and the like suitable for the specifications of the light-emission drive circuit 24 to the light-emission drive circuit 24.
  • the data driver 22 may generate data voltages to be supplied to the data lines D1 to Dn using the gray value and the control signal received from the timing controller 21 .
  • the data driver 22 may sample grayscale values using a clock signal and apply data voltages corresponding to the grayscale values to the data lines D1 to Dn in units of subpixel rows.
  • the scan driving circuit 23 can generate scan signals to be supplied to the scan lines S1 to Sm by receiving a scan clock signal, a scan start signal, and the like from the timing controller 21 .
  • the scan driving circuit 23 may sequentially supply scan signals having on-level pulses to the scan lines.
  • the scan driver 23 may include a shift register and may generate a scan signal by sequentially transmitting a scan start signal provided in the form of an on-level pulse to a next-stage circuit under the control of a scan clock signal.
  • the light emission driving circuit 24 may generate light emission control signals to be supplied to the light emission control lines E1 to Eo by receiving a light emission clock signal, a light emission start signal, or the like from the timing controller 21 .
  • the light emission driving circuit 24 may sequentially provide the light emission control signals having off-level pulses to the light emission control lines.
  • the light-emitting driving circuit 24 may include a shift register to generate a light-emitting control signal in a manner that sequentially transmits a light-emitting start signal provided in the form of an off-level pulse to a next-stage circuit under the control of a clock signal.
  • n, m and o are all natural numbers.
  • the scan driving circuit and the light emitting driving circuit may be directly disposed on the display substrate.
  • the scan driving circuit can be provided on the third frame of the display substrate, and the light emitting driving circuit can be provided on the fourth frame of the display substrate; or, both the third frame and the fourth frame of the display substrate can be provided with the scanning driving circuit and the light emitting driving circuit.
  • the scan driving circuit and the light emitting driving circuit may be formed together with the sub-pixels in a process of forming the sub-pixels.
  • the data driver may be provided on a separate chip or printed circuit board to connect to the subpixels through signal access pins on the display substrate.
  • the data driver can use a chip on glass, a chip on plastic, a chip on film, etc. to form a first frame disposed on the display substrate to be connected to the signal access pin.
  • the timing controller can be provided separately from the data driver or integrated with the data driver. However, this embodiment is not limited to this.
  • the data driver may be disposed directly on the display substrate.
  • FIG. 3 is a partial cross-sectional structural diagram of a display area of a display substrate.
  • Figure 3 illustrates the structure of three sub-pixels of the display substrate.
  • the display substrate may include: a substrate 101 , and a circuit structure layer 102 , a light-emitting structure layer 103 , and a packaging structure sequentially disposed on the substrate 101 layer 104 and encapsulation cover 200 .
  • the display substrate may include other film layers, such as spacer pillars, etc., which are not limited in this disclosure.
  • substrate 101 may be a rigid substrate, such as a glass substrate.
  • the substrate may be a flexible substrate, for example, made of an insulating material such as resin.
  • the substrate may have a single-layer structure or a multi-layer structure.
  • inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride may be disposed between multiple layers in a single layer or in multiple layers.
  • the circuit structure layer 102 of each sub-pixel may include multiple transistors and storage capacitors that constitute the pixel circuit.
  • each sub-pixel includes one transistor and one storage capacitor as an example.
  • the circuit structure layer 102 of each sub-pixel may include: an active layer provided on the substrate 101; a first insulating layer 11 covering the active layer; A first gate metal layer (for example, including a gate electrode and a first capacitor electrode); a second insulating layer 12 covering the first gate metal layer; a second gate metal layer disposed on the second insulating layer 12 (for example, including a second capacitor electrode).
  • the third insulating layer 13 covering the second gate metal layer, via holes are opened on the first insulating layer 11, the second insulating layer 12 and the third insulating layer 13, and the via holes expose the active layer;
  • the first source and drain metal layer on the three insulating layers 13 (for example, including the source electrode and drain electrode of the transistor), the source electrode and the drain electrode can be connected to the active layer through via holes respectively;
  • the first flat layer 14 covering the aforementioned structure, A via hole is opened on the first flat layer 14, and the via hole exposes the drain electrode.
  • the active layer, gate electrode, source electrode and drain electrode may form the transistor 105, and the first capacitor electrode and the second capacitor electrode may form the storage capacitor 106.
  • the light emitting structure layer 103 may include an anode layer, a pixel definition layer, an organic light emitting layer, and a cathode.
  • the anode layer may include the anode of the light-emitting element, and the anode may be disposed on the flat layer and connected to the drain electrode of the transistor of the pixel circuit through a via hole opened on the flat layer;
  • the pixel definition layer is disposed on the anode layer and the flat layer, and the pixel definition layer A pixel opening is provided on the top, and the pixel opening exposes the anode;
  • the organic light-emitting layer is at least partially set in the pixel opening, and the organic light-emitting layer is connected to the anode;
  • the cathode is set on the organic light-emitting layer, and the cathode is connected to the organic light-emitting layer;
  • the organic light-emitting layer is on the anode Driven by the cathode, light of corresponding colors is
  • the packaging structure layer 104 may include a stacked first packaging layer, a second packaging layer, and a third packaging layer.
  • the first packaging layer and the third packaging layer may be made of inorganic materials, and the second packaging layer may be made of organic materials. material, the second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.
  • the organic light-emitting layer may include at least a hole injection layer, a hole transport layer, a light-emitting layer and a hole blocking layer stacked on the anode.
  • the hole injection layers of all sub-pixels may be a common layer connected together
  • the hole transport layers of all sub-pixels may be a common layer connected together
  • the light-emitting layers of adjacent sub-pixels may have a small amount of Overlapping, or may be separate
  • hole blocking layers may be a common layer connected together.
  • this embodiment is not limited to this.
  • Figure 4 is an equivalent circuit diagram of a pixel circuit.
  • the pixel circuit of this example may include seven transistors (ie, first to seventh transistors T1 to T7 ) and one storage capacitor Cst.
  • the gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3.
  • the third transistor T3 may also be called a driving transistor.
  • the gate electrode of the fourth transistor T4 is electrically connected to the first scan line GL, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the third transistor T3 .
  • the fourth transistor T4 may also be called a data writing transistor.
  • the gate electrode of the second transistor T2 is electrically connected to the first scan line GL.
  • the first electrode of the second transistor T2 is electrically connected to the gate electrode of the third transistor T3.
  • the second electrode of the second transistor T2 is electrically connected to the third electrode of the third transistor T3. Two-pole electrical connection.
  • the second transistor T2 may also be called a threshold compensation transistor.
  • the gate electrode of the fifth transistor T5 is electrically connected to the light-emitting control line EML
  • the first electrode of the fifth transistor T5 is electrically connected to the second power supply line VDD
  • the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3.
  • the gate electrode of the sixth transistor T6 is electrically connected to the light-emitting control line EML
  • the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is electrically connected to the anode of the light-emitting element EL. connect.
  • the fifth transistor T5 and the sixth transistor T6 may also be called light emission control transistors.
  • the first transistor T1 is electrically connected to the gate of the third transistor T3 and is configured to reset the gate of the third transistor T3.
  • the seventh transistor T7 is electrically connected to the anode of the light-emitting element EL and is configured to reset the gate of the light-emitting element EL.
  • the anode is reset.
  • the gate electrode of the first transistor T1 is electrically connected to the second scan line RST1.
  • the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1.
  • the second electrode of the first transistor T1 is electrically connected to the gate electrode of the third transistor T3. Electrical connection.
  • the gate electrode of the seventh transistor T7 is electrically connected to the third scanning line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the anode of the light-emitting element EL. .
  • the first transistor T1 and the seventh transistor T7 may also be called reset control transistors.
  • the first capacitor plate of the storage capacitor Cst is electrically connected to the gate of the third transistor T3, and the second capacitor plate of the storage capacitor Cst is electrically connected to the second power line VDD.
  • the first node N1 is the connection point of the storage capacitor Cst, the first transistor T1, the third transistor T3 and the second transistor T2, and the second node N2 is the fifth transistor T5, the fourth transistor T4 and the third transistor.
  • the third node N3 is the connection point of the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light-emitting element EL.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel drive circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.
  • the second power line VDD may be configured to provide a constant second voltage signal to the pixel circuit
  • the first power line VSS may be configured to provide a constant first voltage signal to the pixel circuit
  • the second voltage signal may be greater than first voltage signal.
  • the first scan line GL may be configured to provide the scan signal SCAN to the pixel circuit
  • the data line DL may be configured to provide the data signal DATA to the pixel circuit
  • the emission control line EML may be configured to provide the emission control signal EM to the pixel circuit
  • the second scan line RST1 may be configured to provide the first reset control signal RESET1 to the pixel circuit
  • the third scan line RST2 may be configured to provide the second reset control signal RESET2 to the pixel circuit.
  • the second scan line RST1 electrically connected to the n-th row of pixel circuits may be electrically connected to the first scan line GL of the n-1th row of pixel circuits to be input with the scan signal SCAN(n-1), that is, the second scan line RST1 electrically connected to the n-th row of pixel circuits.
  • a reset control signal RESET1(n) and a scan signal SCAN(n-1) may be the same.
  • the third scan line RST2 of the n-th row pixel circuit may be electrically connected to the first scan line GL of the n-th row pixel circuit to receive the scan signal SCAN(n), that is, the second reset control signal RESET2(n) and the scan signal SCAN(n) can be the same.
  • n is an integer greater than 0. In this way, the signal lines of the display substrate can be reduced and the narrow frame design of the display substrate can be achieved.
  • this embodiment is not limited to this.
  • the first initial signal line INIT1 may be configured to provide a first initial signal to the pixel circuit
  • the second initial signal line INIT2 may be configured to provide a second initial signal to the pixel circuit.
  • the first initial signal may be different from the second initial signal.
  • the first initial signal and the second initial signal may be constant voltage signals, and their magnitudes may be between, for example, the first voltage signal and the second voltage signal, but are not limited thereto.
  • the first initial signal and the second initial signal may be the same, and only the first initial signal line may be provided to provide the first initial signal.
  • the internal wiring of the display substrate is damaged due to static electricity during the reliability test process.
  • ESD electrostatic discharge
  • long traces generally require the addition of more than one ESD unit.
  • ESD units When the internal space of the display substrate is limited, there is not enough space to arrange enough ESD units. As a result, the anti-static capability of the display substrate cannot be effectively improved. There is a blurred screen phenomenon.
  • This embodiment provides a display substrate, including: a substrate, a first power line provided on the substrate, a plurality of first signal lead lines, a plurality of test connection lines, at least one first connection line, and a plurality of test Signal access pin.
  • the substrate at least includes: a display area and a peripheral area located on one side of the display area.
  • the first power cord is located in the perimeter area.
  • a plurality of first signal lead-out lines, a plurality of test connection lines, a plurality of test signal access pins and at least one first connection line are located on a side of the first power line away from the display area. At least one first signal lead-out line is electrically connected to at least one test signal access pin through at least one test connection line.
  • the first connection line is located on one side of the plurality of test connection traces and the plurality of test signal access pins near the edge of the peripheral area in the first direction.
  • the first connection line extends at least along the second direction and is connected with the first power line. Electrical connection.
  • the first direction intersects the second direction, for example, the first direction is perpendicular to the second direction.
  • the display substrate provided in this embodiment is provided with a first connection line that is electrically connected to the first power line, and the first connection line is positioned between a plurality of test connection traces and a plurality of test signal access pins in the first direction.
  • an electrostatic discharge channel can be provided to protect the test signal access pins and the signal traces electrically connected to the test signal access pins.
  • the first connection line, the first power line and the plurality of test connection traces may be located on a side of the plurality of first signal lead-out lines away from the substrate.
  • the first connection line, the first power line and the plurality of test connection lines may be in the same layer structure, for example, they may be located on the first source-drain metal layer.
  • the plurality of first signal lead-out lines may be located on the first gate metal layer.
  • the orthographic projection of the first connection line on the substrate may overlap with the orthographic projection of the plurality of first signal lead-out lines on the substrate.
  • FIG. 5 is a schematic diagram of a first frame of a display substrate according to at least one embodiment of the present disclosure.
  • the first frame (lower frame) B1 of the display substrate may include at least: a signal access area B15 located on one side of the display area AA and two test signal access areas (for example, the A test signal access area B16a and a second test signal access area B16b), and a first area B10 located between the signal access area B15 and the display area AA.
  • the signal access area B15 and the two test signal access areas may be adjacent in the first direction X.
  • the two test signal access areas may be located on opposite sides of the signal access area B15 in the first direction X.
  • the first test signal access area B16a may be located on the left side of the signal access area B15 in the first direction X
  • the second test signal access area B16b may be located on the right side of the signal access area B15 in the first direction X. side.
  • this embodiment is not limited to this. In other examples, only one test signal access area adjacent to the signal access area may be set. In this example, the test signal access area remains within the display substrate.
  • the first area B10 may include: a peripheral circuit area B11 , a fan-out wiring area B12 , a packaging area B13 and a peripheral circuit area B11 that are sequentially arranged in the second direction Y in a direction away from the display area AA.
  • Test trace area B14 The signal access area B15, the first test signal access area B16a and the second test signal access area B16b may be located on a side of the test wiring area B14 away from the packaging area B13.
  • the encapsulation area B13 may be an area where encapsulation glue is applied or printed.
  • the packaging area B13 may be an annular area surrounding the display area AA, which is beneficial to improving the packaging effect.
  • the peripheral circuit area B11 of the first frame B1 may be provided with a multiplexing circuit (MUX) 311 and an electrostatic discharge (ESD) circuit 312.
  • the electrostatic discharge circuit 312 may be located on a side of the multiplexing circuit 311 away from the display area AA.
  • the multiplexing circuit 311 may include a plurality of multiplexing units, each multiplexing unit may be electrically connected to a plurality of data lines in the display area AA, and may be configured to enable one signal source to provide data for the plurality of data lines. Signal.
  • each multiplexing unit can be electrically connected to a multiplexed data line, and the multiplexed data line can be electrically connected to a signal source that provides a data signal.
  • the multiplexed data line may be electrically connected to the electrostatic discharge circuit 312 to discharge static electricity.
  • the fan-out wiring area B12 may be provided with multiple data fan-out lines 333.
  • the plurality of data fan-out lines 333 may be electrically connected to the plurality of multiplexed data lines in the peripheral circuit area B11.
  • multiple data fan-out lines 333 may be electrically connected to multiple multiplexed data lines in one-to-one correspondence.
  • the plurality of data fan-out lines can extend to the signal access area B15 and be electrically connected to the plurality of first signal access pins in the signal access area B15.
  • the plurality of data fan-out lines 333 may be of the same layer structure, for example, may be located on the first gate metal layer.
  • the first area B10 may also be provided with first power lines 321 a and 321 b and a second power line 322 .
  • the first power line 321a may extend to the third frame, and the first power line 321b may extend to the fourth frame.
  • the first power lines 321a and 321b may be connected within the second frame to form an integrated structure.
  • the first power lines 321a and 321b may be configured to connect low-potential power lines to transmit the first voltage signal.
  • the second power line 322 may be configured to connect the high potential power line of the display area AA to transmit the second voltage signal.
  • the first power lines 321a and 321b may be located on opposite sides of the second power line 322 in the first direction X.
  • the first power lines 321a and 321b can both extend to the signal access area B15 and be electrically connected to the first power access pin of the signal access area B15.
  • the second power line 322 can extend to the signal access area B15, and It is electrically connected to the second power access pin of the signal access area B15.
  • the first power lines 321a and 321b and the second power line 322 may be in the same layer structure, for example, may be located on the first source-drain metal layer.
  • the first power lines 321a and 321b, the second power line 322 and the plurality of data fan-out lines 333 may be arranged in different layers.
  • the front projection of the first power lines 321a and 321b on the substrate and the front projection of the plurality of data fan-out lines 333 on the substrate may partially overlap, and the front projection of the second power line 322 on the substrate and the plurality of data fan-out lines 333 are on Orthographic projections of substrates can partially overlap.
  • the first power lines 321a and 321b and the second power line 322 may extend from the fan-out wiring area B12 through the packaging area B13 to the test wiring area B14.
  • the first power lines 321a and 321b located in the packaging area B13 can serve as the first packaging glue base
  • the second power line 322 located in the packaging area B13 can serve as the second packaging glue base.
  • the first encapsulant base may be electrically connected to the first power line 321a or 321b
  • the second encapsulant base may be electrically connected to the second power line 322.
  • the first encapsulant base and the second encapsulant base may have a plurality of openings.
  • the encapsulating glue By arranging multiple openings in the encapsulating glue base, when the encapsulating glue is applied on the encapsulating glue base, the encapsulating glue will leak into the openings, which is equivalent to having encapsulating glue on and inside the encapsulating glue base.
  • the bonding strength of the encapsulation glue can be further improved, and the bonding force between the substrate substrate and the packaging cover plate can be enhanced, thereby improving the product yield.
  • the first area B10 may also be provided with a first peripheral power connection line 323 .
  • the first peripheral power connection line 323 may be electrically connected to the first power line 321a or 321b.
  • the first peripheral power connection line 323 may be located on a side of the first power lines 321a and 321b close to the substrate, for example, may be located on the first gate metal layer.
  • the first peripheral power connection line 323 may be provided with a plurality of via holes.
  • the first peripheral power connection line 323 may be located on a side of the first power line 321a or 321b away from the second power line 322 in the first direction X.
  • the first peripheral power supply connection line 323 and the first power supply line 321a are adjacent in the second direction Y, and the first peripheral power supply connection line 323 is in the second direction Y.
  • the edge close to the first power line 321a in the second direction Y has a plurality of first protrusions.
  • the edge of the first power line 321a close to the first peripheral power connection line 323 in the second direction Y has a plurality of second protrusions.
  • the plurality of second protrusions and the plurality of first protrusions can be electrically connected in a one-to-one correspondence to realize the electrical connection between the first peripheral power connection line 323 and the first power line 321a.
  • the length of the first power line 321a along the first direction X can be reduced.
  • the situation in which the first encapsulant base is prone to corrosion or cracking in a high temperature and high humidity environment can be improved, thereby improving product yield.
  • the test trace area B14 may be provided with a plurality of first signal lead-out lines 341 and a plurality of test connection traces 342 .
  • the plurality of first signal lead-out lines 341 may extend along the first direction X in the test wiring area B14, and may also extend along the second direction Y toward the display area AA side.
  • the plurality of first signal lead-out lines 341 may be electrically connected to the plurality of signal connection lines in the fan-out wiring area B12 to further extend to the third frame and the fourth frame.
  • the plurality of first signal lead-out lines 341 can extend to the signal access area B15 and be electrically connected to multiple signal access pins in the signal access area B15.
  • the plurality of first signal lead-out lines 341 may be of the same layer structure, for example, may be located on the first gate metal layer.
  • the plurality of first signal lead-out lines 341 may also be electrically connected to the plurality of test signal access pins 361 in the test signal access area B16a or B16b through the plurality of test connection lines 342.
  • the plurality of first signal lead-out lines 341 and the plurality of test connection traces 342 may be electrically connected in a one-to-one correspondence.
  • the plurality of test connection traces 342 may be located on a side of the plurality of first signal lead-out lines 341 away from the substrate, for example, may be located on the first source-drain metal layer.
  • Figure 7 is a partial schematic diagram of a signal access area and a test signal access area according to at least one embodiment of the present disclosure.
  • the signal access area B15 may include a plurality of signal access pins 351 arranged side by side in parallel, and the multiple signal access pins 351 may be arranged sequentially along the first direction X.
  • the plurality of signal access pins 351 may be configured to be bonded to the flexible circuit board or driver chip, thereby obtaining signals from the flexible circuit board or driver chip.
  • the plurality of signal access pins 351 may include: a plurality of first power access pins, a plurality of second power access pins, and a plurality of first signal access pins.
  • the first power access pin may be electrically connected to the first power line 321a or 321b
  • the second power access pin may be electrically connected to the second power line 322
  • at least some of the first signal access pins may be electrically connected to multiple pieces of data.
  • the fan-out line 333 is electrically connected, and at least some of the first signal access pins can be electrically connected to a plurality of first signal lead-out lines 341 .
  • the first power access pin and the second power access pin may be located on opposite sides of the plurality of first signal access pins.
  • the first power access pin may be adjacent to the test signal access area B16a or B16b.
  • the length of the first power access pin and the second power access pin along the first direction X may be greater than the length of the first signal access pin along the first direction X.
  • the first power access pin The lengths of the feet, the second power access pin and the first signal access pin along the second direction Y may be the same.
  • the size of the first power access pin and the second power access pin may be larger than the size of the first signal access pin. However, this embodiment is not limited to this.
  • the first test signal access area B16a is used as an example for explanation.
  • the first test signal access area B16a may include a plurality of test signal access pins 361 arranged side by side in parallel, and the multiple test signal access pins 361 may be arranged sequentially along the first direction X.
  • the multiple test signal access pins 361 and the multiple signal access pins 351 of the signal access area B15 can be arranged in parallel.
  • the plurality of test signal access pins 361 may be configured to contact test probes of a test device (for example, a flexible circuit board) during an electronic test (ET, Electronic Test), thereby obtaining signals from the test probes.
  • a test device for example, a flexible circuit board
  • E test Electronic Test
  • test signal access pin 361 of the first test signal access area B16a can be electrically connected to the test circuit and the scan driving circuit in the frame area through the test connection line 342 and the first signal lead line 341, and is configured as Provide test signals to the test circuit and scan driver circuit.
  • this embodiment is not limited to this.
  • the lengths of the multiple test signal access pins 361 along the first direction X may be approximately the same, and the lengths of the multiple test signal access pins 361 along the second direction Y may be approximately the same. .
  • the dimensions of the multiple test signal access pins 361 can be approximately the same. However, this embodiment is not limited to this.
  • the multiple test signal access pins 361 of the second test signal access area B16b can be connected to the test circuit in the frame area through the test connection traces 342 and the first signal lead-out lines 341 .
  • the light-emitting driving circuit is electrically connected and configured to provide test signals to the test circuit and the light-emitting driving circuit.
  • the test circuit may include: at least one test control signal line, a plurality of test data lines, and a plurality of test units. Each test unit is electrically connected to a test control signal line, a test data line and a plurality of data lines in the display area.
  • the test unit may be configured to provide (simultaneously or separately) the signal of the test data line (test data signal) to multiple data lines of the display area connected thereto according to the control of the test control signal line to detect and position the display area. Bad sub-pixels occur.
  • the test circuit may be located on the second frame. However, this embodiment is not limited to this.
  • the first power access pin and the second power access pin of the signal access area B15 (ie, the pins connecting the first power line and the second power line)
  • the first voltage signal and the second voltage signal are provided to the display substrate.
  • the first power access pin of the signal access area B15 can be used to provide the first voltage signal
  • the second power access pin of the signal access area B15 can be used to provide the second voltage signal.
  • this embodiment is not limited to this.
  • at least part of the test signal access pins may be configured to be electrically connected to the first power line and the second power line.
  • the plurality of first signal lead-out lines may be configured to transmit at least one of the following signals: a scan start signal, a scan clock signal, a light-emitting start signal, a light-emitting clock signal, a driving power signal, and test data. signals, test control signals.
  • a plurality of first signal lead-out lines transmitting the scan start signal, the scan clock signal and the drive power signal may be electrically connected to the scan drive circuit.
  • a plurality of first signal lead-out lines transmitting the light-emitting start signal, the light-emitting clock signal and the driving power signal may be electrically connected to the light-emitting driving circuit.
  • a plurality of first signal lead-out lines for transmitting test data signals and test control signals may be electrically connected to the test circuit.
  • FIG. 8 is an example diagram of wiring in the peripheral area of at least one embodiment of the present disclosure.
  • the second frame B1 of the display substrate may be provided with the test circuit 313
  • the third frame B3 may be provided with the scan driving circuit 23
  • the fourth frame B4 may be provided with the light emitting driving circuit 24 .
  • the multiple test signal access pins in the first test signal access area B16a of the first frame B1 can be supplied to the scan driving circuit through the multiple first signal lead-out lines 341 extending to the third frame B3.
  • the scan start signal (GSTV), scan clock signal and driving power signal, and can also provide test data signals and test control signals to the test circuit 313 through a plurality of first signal lead-out lines 341.
  • the multiple test signal access pins in the second test signal access area B16b of the first frame B1 can be supplied to the light-emitting driving circuit through the multiple first signal lead-out lines 341 extending to the fourth frame B4.
  • 24 provides a light-emitting start signal (ESTV), a light-emitting clock signal and a driving power signal, and can also provide test data signals and test control signals to the test circuit 313 through a plurality of first signal lead-out lines 341.
  • the plurality of first signal lead-out lines 341 may be electrically connected to the test circuit 313 in the second frame B2 via the third frame B3 or the fourth frame B4.
  • the third frame and the fourth frame may each be provided with a scan drive circuit and a light-emitting drive circuit, and the test signal access pins may be provided to the third frame and the fourth frame respectively through a plurality of first signal lead-out lines.
  • the scan driving circuit provides signals to the light-emitting driving circuits in the third frame and the fourth frame respectively.
  • the plurality of first signal lead-out lines 341 may also be electrically connected to signal access pins in the signal access area B15.
  • a plurality of first signal lead-out lines electrically connected to the signal access pin can provide a scan start signal, a scan clock signal, a light-emitting start signal, a light-emitting clock signal, and a driving power signal, so as to provide scanning signals during normal display.
  • the driving circuit and the light-emitting driving circuit provide signals.
  • FIG. 6 is a schematic diagram of the first flat layer of the first frame according to at least one embodiment of the present disclosure.
  • a packaging cover can be attached to the substrate, and subsequently, cutting can be performed along the second cutting line Q2 to obtain a single display substrate.
  • the position of the second cutting lane Q2 may correspond to the edge of the single display substrate after cutting.
  • Cutting along the first cutting line Q1 can remove part of the package cover, exposing the signal access pins of the signal access area B15 and the test signal access pins 361 of the two test signal access areas.
  • the exposed signal access pins can be bonded to flexible circuit boards or driver chips.
  • the exposed test signal access pin 361 can be contacted with the test device for electronic testing.
  • the connection position of the first signal lead-out line 341 and the test connection trace 342 can be located on the side of the first cutting line Q1 away from the first encapsulant base, thereby preventing the distance between the test connection trace and the first encapsulant base from being too close. causing a short circuit.
  • the first frame B1 may also be provided with a first flat layer 14 .
  • the first flat layer 14 in the area covered by the black dot shadow in FIG. 6 can be removed to expose the surface of the first source and drain metal layer.
  • the first flat layer 14 in the peripheral circuit area of the first frame B1 may be retained, and the first flat layer 14 in part of the test wiring area may be retained.
  • the orthographic projection of the first flat layer 14 retained in the first frame B1 on the substrate can cover the connection positions of the plurality of first signal lead lines 341 and the plurality of test connection traces 342 .
  • the distance between the edge of the first flat layer 14 close to the display area AA and the edge of the first encapsulant base away from the display area AA may be greater than or equal to 50 microns, for example, may be greater than or equal to 120 microns. Micron.
  • the orthographic projection of the first scribe line Q1 on the substrate may overlap with the first planar layer 14 .
  • the first cutting line Q1 may be located on a side of an edge of the first flat layer 14 close to the display area AA and away from the display area AA.
  • the distance between the first cutting line Q1 and the edge of the first encapsulant base away from the display area AA may be about 200 microns. However, this embodiment is not limited to this.
  • connection position of the first signal lead-out line 341 and the test connection trace 342 is set on the side of the first cutting line Q1 away from the display area AA, and the connection position can be covered and protected by the first flat layer 14, thereby It can avoid wiring failure under high temperature and high humidity conditions and avoid display abnormalities caused by electrochemical corrosion.
  • the first test signal access area B16a may be provided with a first auxiliary mark 371 on a side away from the signal access area B15 in the first direction X.
  • the first auxiliary mark 371 may be provided with a second auxiliary mark 372 on a side away from the first test signal access area B16a in the first direction X.
  • a first auxiliary mark 371 and a second auxiliary mark 372 are also provided on the side of the second test signal access area B16b away from the signal access area B15.
  • the size of the first auxiliary mark 371 may be smaller than the size of the second auxiliary mark 372 .
  • orthographic projections of the first auxiliary mark 371 and the second auxiliary mark 372 on the substrate may be cross-shaped.
  • this embodiment is not limited to this.
  • at least one of the first auxiliary mark and the second auxiliary mark may be L-shaped.
  • by setting the first auxiliary mark it can help to accurately align the test probe with the test signal access pin in the test signal access area during the electronic test process.
  • only the first auxiliary mark may be set when the space of the first border is limited.
  • the first auxiliary mark 371 and the second auxiliary mark 372 may be in the same layer structure, for example, may be located on the first source and drain metal layer.
  • this embodiment is not limited to this.
  • the first power line 321a may be electrically connected to a second auxiliary mark 372 through a first connection line 381 .
  • the first power line 321b may be electrically connected to another second auxiliary mark 372 through another first connection line 381.
  • the first connection line 381 may extend along the second direction Y.
  • the first power line 321a, the first connection line 381 and the second auxiliary mark 372 may be an integrated structure. However, this embodiment is not limited to this.
  • FIG. 9 is a partially enlarged schematic diagram of area C1 in FIG. 5 .
  • Figure 10 is a partial cross-sectional view along the P-P’ direction in Figure 9.
  • FIG. 11A is a schematic diagram of the first gate metal layer in FIG. 9 .
  • FIG. 11B is a schematic diagram of the first source and drain metal layer in FIG. 9 .
  • the first signal lead-out line 341 of the test trace area may include a first body 341a and a first bending portion 341b.
  • the first body 341a may extend along the first direction X, and the first bending part 341b may protrude toward the second auxiliary mark 372 along the second direction Y.
  • the first bending portion 341b may have a first extension portion, a second extension portion and a third extension portion connected in sequence.
  • the first extension part and the third extension part may be connected to the first body 341a, and the second extension part is connected between the first extension part and the third extension part.
  • the second extension part may extend along the first direction X, and the extension directions of the first extension part and the third extension part may cross each other, and may cross both the first direction X and the second direction Y.
  • the first extension part and the third extension part extend away from the display area AA.
  • the orthographic projection of the first bending portion 341b on the substrate may be in the shape of a groove.
  • the plurality of first signal lead-out lines 341 may all be located in the test trace area.
  • the first bending portion 341b of the at least one first signal lead-out line 341 may extend to overlap the second auxiliary mark 372, or may extend to be located on the second auxiliary mark 372 in the first direction X. In the area far away from the first test signal access area B16b.
  • multiple test connection traces 342 and multiple first signal lead-out lines 341 may be electrically connected in a one-to-one correspondence.
  • a part of the test connection trace 342 may be electrically connected to the first bending part 341b of the corresponding first signal lead-out line 341, for example, may be electrically connected to the second extension part of the first bending part 341b.
  • the test signal access pin 361 close to the first auxiliary mark 371 in the first test signal access area B16b may be electrically connected to the first signal lead-out line 341 close to the first encapsulant base, away from the first auxiliary mark 371 .
  • the test signal access pin 361 marked 371 may be electrically connected to the first signal lead-out line 341 away from the first encapsulant base.
  • the test connection trace 342 electrically connected to the test signal access pin 361 close to the first auxiliary mark 371 may be electrically connected to the corresponding first bending portion 341b of the first signal lead-out line 341 .
  • the test connection trace 342 electrically connected to the test signal access pin 361 away from the first auxiliary mark 371 may extend along the second direction Y and be electrically connected to the first body 341a of the corresponding first signal lead-out line 341.
  • connection positions of the plurality of test connection traces 342 and the plurality of first signal lead-out lines 341 may be located on the side of the first connection line 381 close to the first auxiliary mark 371 in the first direction X.
  • this embodiment is not limited to this.
  • the connection position of the at least one test connection trace and the at least one first signal lead-out line may be located in the first direction X away from the first connection line 381 away from the first auxiliary mark. 371 side.
  • the test signal access pin 361 may include: a first sub-pin 3611 and a second sub-pin 3612.
  • the first sub-pin 3611 and the second sub-pin 3612 may be electrically connected to each other.
  • the first sub-pin 3611 may be located on the first gate metal layer, and the second sub-pin 3612 may be located on the first source-drain metal layer.
  • the second sub-pin 3612 can be electrically connected to the first sub-pin 3611 through the groove formed by the third insulating layer 13 and the second insulating layer 12 .
  • the orthographic projection of the second sub-lead 3612 on the substrate 101 may include the orthographic projection of the first sub-lead 3611 on the substrate 101 .
  • the second sub-pin 3612 and the corresponding electrically connected test connection trace 342 may have an integrated structure.
  • the first connection line 381 may extend along the second direction Y, and may electrically connect the first power line 321 a and the second auxiliary mark 371 .
  • the first connection line 381 and the second auxiliary mark 372 may be aligned in the second direction Y.
  • the center line of the first connection line 381 along the first direction X and the center line of the second auxiliary mark 372 along the first direction X may be aligned.
  • the first connection line 381, the first power line 321a and the second auxiliary mark 371 may be an integral structure, for example, may be located on the first source-drain metal layer.
  • the plurality of first signal lead-out lines 341 may be located on the first gate metal layer.
  • the orthographic projection of the first connection line 381 on the substrate may overlap with the orthographic projection of the plurality of first signal lead-out lines 341 on the substrate.
  • the orthographic projection of the first connection line 381 on the substrate may overlap with the orthographic projection of the first bending portions 341b of the plurality of first signal lead-out lines 341 on the substrate.
  • the first connection line 381 may be located on one side of the plurality of test connection lines 342 in the first direction X.
  • the first connection line 381 is located on the side of the plurality of test connection traces 342 and the plurality of test signal access pins 361 close to the first frame area in the first direction X, that is, the first connection line 381 can Located on the periphery of multiple test connection lines 342 and multiple test signal access pins 361 in the first direction Provide protection, thereby improving the anti-static ability of the display substrate.
  • FIG. 12 is a partially enlarged schematic diagram of area C2 in FIG. 9 .
  • Figure 13 is a partial cross-sectional view along the R-R' direction in Figure 12.
  • the connection end of the test connection trace 342 and the first signal lead-out line 341 may be T-shaped.
  • At least one test connection trace 342 may extend along the second direction Y to a side away from the display area AA and then extend along the first direction X until it is connected to the second sub-pin 3612 of the test signal access pin 361 .
  • At least one test connection trace 342 may extend along the second direction Y toward the side close to the display area AA and then extend along the first direction X until it is connected to the second sub-pin 3612 of the test signal access pin 361 .
  • the first signal lead-out line 341 may be located on the first gate metal layer, and the test connection line 342 may be located on the first source-drain metal layer.
  • this embodiment is not limited to this.
  • the structure of the display substrate of the present disclosure is explained below through an example of the preparation process of the display substrate.
  • the "patterning process” mentioned in this disclosure includes processes such as depositing film layers, coating photoresist, mask exposure, development, etching, and stripping photoresist.
  • the deposition may be any one or more selected from sputtering, evaporation and chemical vapor deposition
  • the coating may be any one or more selected from spraying and spin coating
  • the etching may be selected from dry etching. and any one or more of wet engraving.
  • Thin film refers to a thin film produced by depositing or coating a certain material on a substrate.
  • the "film” does not require a patterning process during the entire production process, the “film” can also be called a “layer.”
  • the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process, and it is called a “layer” after the patterning process.
  • the "layer” after the patterning process contains at least one "pattern”.
  • a and B have the same layer structure means that A and B are formed simultaneously through the same patterning process.
  • “Same layer” does not always mean that the thickness of the layer or the height of the layer is the same in the cross-sectional view.
  • the orthographic projection of A contains the orthographic projection of B means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.
  • the preparation process of the display substrate of this embodiment may include the following steps.
  • substrate 101 may be a rigid substrate, such as a glass substrate.
  • this embodiment is not limited to this.
  • the substrate may be a flexible substrate.
  • the semiconductor layer of the display area may include at least an active layer of a transistor of the pixel circuit.
  • the first gate metal layer in some examples, on the substrate 101 forming the above structure, a first insulating film and a first metal film are sequentially deposited, the first metal film is patterned through a patterning process, and a first insulating layer 11 covering the semiconductor layer is formed, and A first gate metal layer is provided on the first insulating layer 11 .
  • the first gate metal layer in the display area at least includes: the gate electrode of the transistor of the pixel circuit and the first capacitor electrode of the storage capacitor.
  • the first gate metal layer of the first frame may at least include: a plurality of data fan-out lines 333, a first peripheral power connection line 323, a plurality of first signal lead-out lines 341, and a plurality of first signal lead-out lines 341 located in the signal access area B15.
  • the second gate metal layer of the display area may include at least a second capacitor electrode of a storage capacitor of the pixel circuit.
  • a third insulating film is deposited on the substrate 101 forming the above structure, and the third insulating film is patterned through a patterning process to form a third insulating layer.
  • the third insulating layer 13 may be provided with a plurality of via holes or grooves.
  • the first source-drain metal layer of the display area may at least include: source electrodes and drain electrodes of a plurality of transistors of the pixel circuit.
  • the first source-drain metal layer of the first frame may at least include: first power lines 321a and 321b, a second power line 322, a plurality of test connection traces 342, a first auxiliary mark 371, a second Auxiliary mark 372, second sub-pins of multiple signal access pins located in the signal access area, and second sub-pins of multiple test signal access pins 361 located in the test signal access area.
  • the test connection trace 342 may be electrically connected to the first signal lead-out line 341 through the via holes opened in the third insulating layer and the second insulating layer.
  • the second sub-pin of the test signal access pin 361 can be electrically connected to the corresponding first sub-pin through the groove formed in the third insulating layer and the second insulating layer.
  • the second sub-pin of the signal access pin can be electrically connected to the corresponding first sub-pin through the groove formed in the third insulating layer and the second insulating layer.
  • the circuit structure layer of the display area is prepared on the substrate 101, as shown in FIG. 3 .
  • the first to third insulating films may all adopt inorganic materials, such as any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). It can be single layer, multi-layer or composite layer.
  • a flat layer, a light-emitting structure layer and a packaging structure layer on the substrate in sequence.
  • a first flat film is coated on the substrate 101 forming the foregoing structure, and the first flat layer 14 is formed through a patterning process.
  • a portion of the first flat layer 14 is reserved in the first frame B1 to cover the connection positions of the test connection traces 342 and the first signal lead-out lines 341 .
  • a first conductive film is deposited in the display area, and the first conductive film is patterned through a patterning process to form an anode layer pattern.
  • the anode of the anode layer may be electrically connected to the pixel circuit through a via hole on the first flat layer.
  • the pixel definition film is coated, and the pixel definition layer pattern is formed through masking, exposure, and development processes.
  • a pixel definition layer is formed in the display area.
  • a pixel opening is opened on the pixel definition layer of the display area, and the pixel definition film in the pixel opening is developed to expose the surface of the anode.
  • an organic light-emitting layer and a cathode are sequentially formed on the substrate with the aforementioned pattern.
  • the organic light-emitting layer includes a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer and an electron injection layer, and is formed in a pixel opening in the display area to connect the organic light-emitting layer to the anode.
  • a portion of the cathode is formed on the organic light-emitting layer.
  • a packaging structure layer is formed on the substrate on which the foregoing pattern is formed.
  • the encapsulation structure layer can be formed in the display area, and can adopt a laminated structure of inorganic material/organic material/inorganic material.
  • the organic material layer is disposed between the two inorganic material layers.
  • the first flat layer and the pixel definition layer may be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate.
  • the preparation process of the scanning driving circuit and the light emitting driving circuit in the frame area is similar to the preparation process of the circuit structure layer in the display area, so it will not be described again.
  • the substrate and the packaging cover can be bonded through a packaging process, and then a single display substrate is obtained by cutting, and the packaging cover is cut according to the first cutting lane to expose The signal access pin of the signal access area and the test signal access pin of the test signal access area.
  • a touch structure layer may be provided on the side of the package cover away from the base substrate, thereby forming a touch display substrate.
  • this embodiment is not limited to this.
  • the preparation process of this exemplary embodiment can be implemented using existing mature preparation equipment, and is well compatible with the existing preparation process.
  • the process is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.
  • the structure of the display substrate and its preparation process in this exemplary embodiment are only an exemplary illustration. In some exemplary embodiments, the corresponding structure may be changed and the patterning process may be increased or decreased according to actual needs.
  • the display area may be provided with a first source-drain metal layer and a second source-drain metal layer.
  • the first source-drain metal layer may include a source electrode and a drain electrode of a transistor
  • the second source-drain metal layer may include a light-emitting element and a leakage current of the transistor. connecting electrodes between poles.
  • the first power line, the second power line and the test connection trace can be located on the second source-drain metal layer; or the first power line and the second power line can be located on the second source-drain metal layer, and the test connection trace can be located on the second source-drain metal layer. It can be located on the first source and drain metal layer.
  • this embodiment is not limited to this.
  • FIG. 14 is another partially enlarged schematic diagram of the first frame according to at least one embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of the first gate metal layer in FIG. 14 .
  • the right area of the first border is taken as an example for illustration and explanation.
  • the structure of the left area of the first frame is similar to the structure of the right area, so no details are given here.
  • a plurality of first signal lead lines 341 may extend along the first direction X in the test trace area, and a plurality of test connection traces 342 may extend along the second direction Y.
  • One end of the test connection trace 342 can be electrically connected to the first signal lead-out line 341, and the other end can be electrically connected to the test signal access pin 361 of the test lead access area B16b, for example, it can be electrically connected to the test signal access pin 361.
  • the second sub-pin has an integrated structure. However, this embodiment is not limited to this.
  • the display substrate may further include: an auxiliary power pin 391 located on the first gate metal layer.
  • the auxiliary power pin 391 may be located on a side of the test signal access area away from the signal access area in the first direction X.
  • the auxiliary power pin 391 may be aligned with the test signal access pin 361 in the first direction X.
  • the center line of the auxiliary power pin 391 along the second direction Y and the center line of the test signal access pin 361 along the second direction Y may be aligned.
  • the auxiliary power pin 391 and the first sub-pin 3611 of the test signal access pin 361 have the same layer structure, and the shapes and sizes of the two can be approximately the same.
  • the orthographic projection of the auxiliary power pin 391 on the substrate may be located between the orthographic projections of the first auxiliary mark 371 and the second auxiliary mark 372 on the substrate.
  • One end of the first connection line 381 can be electrically connected to the auxiliary power pin 391 through the groove formed in the third insulating layer and the second insulating layer, and the other end can be electrically connected to the first power line 321a.
  • the first connection line 381 and the first power line 321a may have an integrated structure.
  • the first connection line 381 may be a strip trace extending along the second direction Y.
  • auxiliary power pin between the first auxiliary mark and the second auxiliary mark, and electrically connecting the auxiliary power pin and the first power line through the first connection line
  • auxiliary power pin can be connected.
  • Adding an electrostatic discharge path around the access pin can reduce static electricity damage to the signal wiring and provide protection for the test signal access pin, thereby improving the anti-static capability of the display substrate.
  • FIG. 16 is another partially enlarged schematic diagram of the first frame according to at least one embodiment of the present disclosure.
  • the first connection line 381 and the second auxiliary mark 372 may be disconnected.
  • the first connection line 381 may be aligned with the second auxiliary mark 372 in the second direction Y, and the first connection line 381 and the second auxiliary mark 372 may not be electrically connected.
  • the first connection line 381 is located on the periphery of the plurality of test connection lines 342 and the plurality of test signal access pins 361 in the first direction
  • the access pins provide protection, thereby improving the anti-static capability of the display substrate.
  • FIG. 17 is another partially enlarged schematic diagram of the first frame according to at least one embodiment of the present disclosure.
  • the first connection line 381 and the second auxiliary mark 372 may be electrically connected.
  • the second auxiliary mark 372 may be electrically connected to the first auxiliary mark 371 through a third connection line 383 .
  • the third connection line 383 may extend along the first direction X.
  • the second auxiliary mark 372, the first auxiliary mark 371 and the third connection line 383 may be in the same layer structure, such as being located on the first source and drain metal layer.
  • the second auxiliary mark 372, the first auxiliary mark 371 and the third connection line 383 may be an integral structure.
  • this embodiment is not limited to this.
  • the third connection line may be located on a side of the first auxiliary mark and the second auxiliary mark close to the substrate, for example, may be located on the first gate metal layer.
  • the first auxiliary mark and the second auxiliary mark are electrically connected through the third connection line, which can further surround the signal trace electrically connected to the test signal access pin, thereby reducing static electricity damage to the signal trace, thereby Improve the anti-static ability of the display substrate.
  • FIG. 18 is another partially enlarged schematic diagram of the first frame according to at least one embodiment of the present disclosure.
  • the first connection line 381 and the second auxiliary mark 372 may be electrically connected.
  • the orthographic projection of the first connection line 381 on the substrate overlaps with the orthographic projection of the first body 341a of the plurality of first signal lead-out lines 341 on the substrate.
  • the first bending portions 341b of the plurality of first signal lead-out lines 341 may be located on the side of the first connection line 381 close to the second test signal access area B16b in the first direction X.
  • FIG. 19 is another partially enlarged schematic diagram of the first frame according to at least one embodiment of the present disclosure.
  • the first peripheral power connection line 323 located on the first gate metal layer can be electrically connected to the second connection line 382 , for example, the two can be an integrated structure.
  • the portion of the first peripheral power connection line 323 close to the fourth frame may be electrically connected to the second connection line 382 .
  • the second connection line 382 may extend from the first peripheral power connection line 323 along the second direction Y to a side away from the display area, and then extend along the first direction X toward a side close to the test signal access area until it is close to the first connection line. 381.
  • the second connection line 382 and the first connection line 381 may not be electrically connected. However, this embodiment is not limited to this.
  • the second connection line 382 may be electrically connected to the first connection line 381.
  • the second connection line 382 may be located on a side of the plurality of first signal lead-out lines 341 away from the display area.
  • the second connection line 382 may be located on a side of the plurality of first signal lead-out lines 341 close to the edge of the first frame.
  • the second connection lines 382 may surround the outsides of the plurality of first signal lead-out lines 341 .
  • the second connection line 382 in this example can provide an electrostatic discharge path and can also provide protection for the first signal lead-out line, thereby improving the anti-static capability of the display substrate.
  • FIG. 20 is another partially enlarged schematic diagram of the first frame according to at least one embodiment of the present disclosure.
  • the first power line 321a located on the first source-drain metal layer can be electrically connected to the second connection line 382.
  • the two can be an integrated structure.
  • the portion of the first power line 321a close to the fourth frame may be electrically connected to the second connection line 382.
  • the second connection line 382 may extend from the first power line 321 a along the second direction Y to a side away from the display area, and then extend along the first direction X toward a side close to the test signal access area until close to the second auxiliary mark 372 .
  • the second connection line 382 and the second auxiliary mark 372 may be electrically connected.
  • this embodiment is not limited to this.
  • the second connection line 382 may not be electrically connected to the second auxiliary mark 372 .
  • This embodiment can effectively improve the antistatic ability of the display substrate.
  • first connection line and the second connection line may connect the first power line and the second auxiliary mark, and the first auxiliary mark and the second auxiliary mark may be electrically connected through the third connection line.
  • first connection line may not be electrically connected to the second auxiliary mark, and the second connection line may be electrically connected to the second auxiliary mark.
  • this embodiment is not limited to this.
  • An embodiment of the present disclosure also provides a display device, including the display substrate of the aforementioned embodiment.
  • the display substrate may be an OLED display substrate.
  • the display device can be: an OLED display device, a mobile phone, a tablet computer, a television, a monitor, a laptop, a digital photo frame or a navigator, or any other product or component with a display function.
  • this embodiment is not limited to this.

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Abstract

一种显示基板，包括：衬底（101）、第一电源线（321a）、多条第一信号引出线（341）、多条测试连接走线（342）、至少一条第一连接线（381）以及多个测试信号接入引脚（361）。至少一条第一信号引出线（341）通过至少一条测试连接走线（342）与至少一个测试信号接入引脚（361）电连接。第一连接线（381）在第一方向（X）上位于多条测试连接走线（342）和多个测试信号接入引脚（361）靠近周边区域边缘的一侧。第一连接线（381）至少沿第二方向（Y）延伸，并与第一电源线（321a）电连接。

Description

显示基板及显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及显示装置。
背景技术
随着显示技术的不断发展，显示产品的种类越来越多，例如，液晶显示器(LCD，Liquid Crystal Display)、有机发光二极管(OLED，Organic Light-Emitting Diode)显示器、等离子体显示面板(PDP，Plasma Display Panel)、场发射显示器(FED，Field Emission Display)等。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板及显示装置。
一方面，本公开实施例提供一种显示基板，包括：衬底、设置在衬底上的第一电源线、多条第一信号引出线、多条测试连接走线、至少一条第一连接线以及多个测试信号接入引脚。衬底至少包括：显示区域、位于显示区域一侧的周边区域。第一电源线位于周边区域。多条第一信号引出线、多条测试连接走线、多个测试信号接入引脚以及至少一条第一连接线位于第一电源线远离显示区域的一侧。至少一条第一信号引出线通过至少一条测试连接走线与至少一个测试信号接入引脚电连接。第一连接线在第一方向上位于多条测试连接走线和多个测试信号接入引脚靠近周边区域边缘的一侧，第一连接线至少沿第二方向延伸，并与第一电源线电连接。所述第一方向与第二方向交叉。
在一些示例性实施方式中，在垂直于所述显示基板的方向上，所述第一连接线、所述第一电源线和所述多条测试连接走线位于所述多条第一信号引出线远离所述衬底的一侧。
在一些示例性实施方式中，所述第一连接线、所述第一电源线和所述多条测试连接走线为同层结构。
在一些示例性实施方式中，所述第一连接线在所述衬底的正投影与所述多条第一信号引出线在所述衬底的正投影存在交叠。
在一些示例性实施方式中，所述周边区域至少包括：位于所述显示区域一侧的至少一个测试信号接入区、至少一个第一辅助标记和至少一个第二辅助标记；所述第二辅助标记在所述第一方向上位于所述第一辅助标记远离所述测试信号接入区的一侧。所述第一连接线和所述第二辅助标记在所述第二方向上对齐。
在一些示例性实施方式中，所述第一连接线与所述第二辅助标记电连接。
在一些示例性实施方式中，所述第一连接线与所述第二辅助标记为一体结构。
在一些示例性实施方式中，所述周边区域至少包括：位于所述显示区域一侧的至少一个测试信号接入区、至少一个第一辅助标记和至少一个第二辅助标记；所述第二辅助标记在所述第一方向上位于所述第一辅助标记远离所述测试信号接入区的一侧。所述第一连接线在所述第一方向上位于所述第一辅助标记和第二辅助标记之间。
在一些示例性实施方式中，显示基板还包括：至少一个辅助电源引脚，所述辅助电源引脚在所述第一方向上位于所述第一辅助标记和第二辅助标记之间，所述第一连接线与所述辅助电源引脚电连接。
在一些示例性实施方式中，所述至少一条第一信号引出走线具有向所述第二辅助标记一侧凸出的第一弯折部；所述至少一条测试连接走线与所述第一信号引出走线的第一弯折部电连接。所述第一连接线在所述衬底的正投影与所述第一信号引出线的第一弯折部在所述衬底的正投影存在交叠。
在一些示例性实施方式中，所述至少一条第一信号引出走线具有向所述第二辅助标记一侧凸出的第一弯折部；所述至少一条测试连接走线与所述第一信号引出走线的第一弯折部电连接。所述第一连接线在所述衬底的正投影与所述第一信号引出线的第一弯折部在所述衬底的正投影没有交叠，且所述 第一信号引出线的第一弯折部位于所述第一连接线靠近所述测试信号接入区的一侧。
在一些示例性实施方式中，所述第一辅助标记通过第三连接线与相邻的第二辅助标记电连接。
在一些示例性实施方式中，所述第一辅助标记、所述第三连接线和所述第二辅助标记为一体结构。
在一些示例性实施方式中，所述周边区域还包括：位于所述显示区域和所述测试信号接入区之间的第一区域。所述多个测试信号接入引脚位于所述测试信号接入区，所述第一电源线、所述多条第一信号引出线和多条测试连接走线至少位于所述第一区域。
在一些示例性实施方式中，所述周边区域还包括：沿所述第二方向位于所述显示区域一侧的信号接入区，所述信号接入区在所述第一方向上与所述测试信号接入区相邻；所述信号接入区包括：设置在所述衬底上的多个信号接入引脚；所述至少一条第一信号引出线与至少一个信号接入引脚电连接。
在一些示例性实施方式中，显示基板还包括：与所述第一电源线电连接的第二连接线，所述第二连接线位于所述多条第一信号引出线远离所述显示区域的一侧。
在一些示例性实施方式中，所述第二连接线与所述第一电源线为一体结构。
在一些示例性实施方式中，显示基板还包括：与所述第一电源线电连接的第一周边电源连接线，所述第一周边电源连接线位于所述第一电源线靠近所述衬底的一侧；所述第二连接线与所述第一周边电源连接线为一体结构。
在一些示例性实施方式中，所述多条第一信号引出线被配置为传输以下至少之一信号：扫描起始信号、扫描时钟信号、发光起始信号、发光时钟信号、驱动电源信号、测试数据信号、测试控制信号。
另一方面，本公开实施例提供一种显示装置，包括如上所述的显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示装置的外形示意图；
图2为一种显示装置的结构示意图；
图3为一种显示基板的显示区域的局部剖面结构示意图；
图4为一种像素电路的等效电路图；
图5为本公开至少一实施例的显示基板的第一边框的示意图；
图6为本公开至少一实施例的第一边框的第一平坦层的示意图；
图7为本公开至少一实施例的信号接入区和测试信号接入区的局部示意图；
图8为本公开至少一实施例的周边区域的走线示例图；
图9为图5中区域C1的局部放大示意图；
图10为图9中沿P-P’方向的局部剖面示意图；
图11A为图9中第一栅金属层的示意图；
图11B为图9中第一源漏金属层的示意图；
图12为图9中区域C2的局部放大示意图；
图13为图12中沿R-R’方向的局部剖面示意图；
图14为本公开至少一实施例的第一边框的另一局部放大示意图；
图15为图14中第一栅金属层的示意图；
图16为本公开至少一实施例的第一边框的另一局部放大示意图；
图17为本公开至少一实施例的第一边框的另一局部放大示意图；
图18为本公开至少一实施例的第一边框的另一局部放大示意图；
图19为本公开至少一实施例的第一边框的另一局部放大示意图；
图20为本公开至少一实施例的第一边框的另一局部放大示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接 在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，为区分晶体管除栅极之外的两极，将其中一个电极称为第一极，另一电极称为第二极，第一极可以为源极或者漏极，第二极可以为漏极或源极，另外，将晶体管的栅极称为控制极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本公开中，“大致相同”是指数值相差10％以内的情况。
在本公开中，A沿着B方向延伸是指，A可以包括主体部分和与主体部分连接的次要部分，主体部分是线、线段或条形状体，主体部分沿着B方向伸展，且主体部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。以下描述中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。
图1为一种显示装置的外形示意图，外形为一种矩形倒圆角形状。显示装置可以包括：显示基板。在一些示例中，显示基板可以为包括线性边的闭 合多边形、包括弯曲边的圆形或椭圆形、或者包括线性边和弯曲边的半圆形或半椭圆形等。在一些示例中，当衬底基板具有线性边时，衬底基板的至少一些拐角可以为曲线。当衬底基板具有矩形形状时，在相邻的线性边彼此交汇处的部分可以采用具有预定曲率的曲线代替。其中，可以根据曲线的位置不同来设定曲率。例如，可以根据曲线开始的位置、曲线的长度等来改变曲率。
在一些示例中，如图1所示，显示基板可以包括显示区域AA和位于显示区域周边的周边区域BB。在一些示例中，显示区域AA可以包括在第二方向Y上相对设置的第一边缘(下边缘)和第二边缘(上边缘)，以及在第一方向X上相对设置的第三边缘(左边缘)和第四边缘(右边缘)。相邻边缘之间可以通过弧形的倒角连接，形成倒圆角的四边形形状。在一些示例中，周边区域BB可以包括：在第二方向Y上相对设置的第一边框(下边框)B1和第二边框(上边框)B2，在第一方向X上相对设置的第三边框(左边框)B3和第四边框(右边框)B4。第一边框B1与第三边框B3和第四边框B4连通，第二边框B2与第三边框B3和第四边框B4连通。
在一些示例中，如图1所示，显示区域AA至少包括多个子像素PX、多条栅线G以及多条数据线D。多条栅线G可以沿第一方向X延伸，多条数据线D可以沿第二方向Y延伸。多条栅线G和多条数据线D在衬底基板上的正投影交叉形成多个子像素区域，每个子像素区域内设置一个子像素PX。多条数据线D与多个子像素PX电连接，多条数据线D可以被配置为向多个子像素PX提供数据信号。多条栅线G与多个子像素PX电连接，多条栅线G可以被配置为向多个子像素PX提供栅极控制信号。在一些示例中，栅极控制信号可以包括扫描信号和发光控制信号。
在一些示例中，如图1所示，第一方向X可以是显示区域中栅线G的延伸方向(行方向)，第二方向Y可以是显示区域中数据线D的延伸方向(列方向)。第一方向X和第二方向Y可以相互垂直。
在一些示例中，显示区域AA的一个像素单元可以包括三个子像素，三个子像素分别为红色子像素、绿色子像素和蓝色子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像 素分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。
在一些示例中，子像素的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形(Square)方式排列。然而，本实施例对此并不限定。
在一些示例中，子像素可以包括：像素电路以及与像素电路连接的发光元件。像素电路可以包括多个晶体管和至少一个电容，例如，像素电路可以为3T1C(即3个晶体管和1个电容)结构、7T1C(即7个晶体管和1个电容)结构、5T1C(即5个晶体管和1个电容)结构、8T1C(即8个晶体管和1个电容)结构或者8T2C(即8个晶体管和2个电容)结构等。
在一些示例中，发光元件可以是发光二极管(LED，Light Emitting Diode)、有机发光二极管(OLED，Organic Light Emitting Diode)、量子点发光二极管(QLED，Quantum Dot Light Emitting Diodes)、微LED(包括：mini-LED或micro-LED)等中的任一者。例如，发光元件可以为OLED，发光元件在其对应的像素电路的驱动下可以发出红光、绿光、蓝光、或者白光等。发光元件发光的颜色可根据需要而定。在一些示例中，发光元件可以包括：阳极、阴极以及位于阳极和阴极之间的有机发光层。发光元件的阳极可以与对应的像素电路电连接。然而，本实施例对此并不限定。
图2为一种显示装置的结构示意图。在一些示例中，如图2所示，显示装置可以包括：时序控制器21、数据驱动器22、扫描驱动电路23、发光驱动电路24以及显示基板25。在一些示例中，显示基板25的显示区域可以包括规则排布的多个子像素PX。扫描驱动电路23可以配置为沿扫描线将扫描信号提供到子像素PX；数据驱动器22可以配置为沿数据线将数据电压提供到子像素PX；发光驱动电路24可以配置为沿发光控制线将发光控制信号提供到子像素PX；时序控制器21可以配置为控制扫描驱动电路23、发光驱动电路24和数据驱动器22。
在一些示例中，时序控制器21可以将适于数据驱动器22的规格的灰度值和控制信号提供到数据驱动器22；时序控制器21可以将适于扫描驱动器 23的规格的扫描时钟信号、扫描起始信号等提供到扫描驱动电路23；时序控制器21可以将适于发光驱动电路24的规格的发光时钟信号、发光起始信号等提供到发光驱动电路24。数据驱动器22可以利用从时序控制器21接收的灰度值和控制信号来产生将提供到数据线D1至Dn的数据电压。例如，数据驱动器22可以利用时钟信号对灰度值进行采样，并且以子像素行为单位将与灰度值对应的数据电压施加到数据线D1至Dn。扫描驱动电路23可以通过从时序控制器21接收的扫描时钟信号、扫描起始信号等来产生将提供到扫描线S1至Sm的扫描信号。例如，扫描驱动电路23可以将具有导通电平脉冲的扫描信号顺序地提供到扫描线。在一些示例中，扫描驱动器23可以包括移位寄存器，可以在扫描时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号。发光驱动电路24可以通过从时序控制器21接收的发光时钟信号、发光起始信号等来产生将提供到发光控制线E1至Eo的发光控制信号。例如，发光驱动电路24可以将具有截止电平脉冲的发光控制信号顺序地提供到发光控制线。发光驱动电路24可以包括移位寄存器，以在时钟信号的控制下顺序地将截止电平脉冲形式提供的发光起始信号传输到下一级电路的方式产生发光控制信号。其中，n、m和o均为自然数。
在一些示例中，扫描驱动电路和发光驱动电路可以直接设置在显示基板上。例如，扫描驱动电路可以设置在显示基板的第三边框，发光驱动电路可以设置在显示基板的第四边框；或者，显示基板的第三边框和第四边框均可以设置扫描驱动电路和发光驱动电路。在一些示例中，扫描驱动电路和发光驱动电路可以在形成子像素的工艺中与子像素一起形成。
在一些示例中，数据驱动器可以设置在单独的芯片或印刷电路板上，以通过显示基板上的信号接入引脚连接到子像素。例如，数据驱动器可以采用玻璃上芯片、塑料上芯片、膜上芯片等形成设置在显示基板的第一边框，以连接到信号接入引脚。时序控制器可以与数据驱动器分开设置或者与数据驱动器一体设置。然而，本实施例对此并不限定。在一些示例中，数据驱动器可以直接设置在显示基板上。
图3为一种显示基板的显示区域的局部剖面结构示意图。图3示意了显 示基板的三个子像素的结构。在一些示例中，如图3所示，在垂直于显示基板的方向上，显示基板可以包括：衬底101、以及依次设置在衬底101上的电路结构层102、发光结构层103、封装结构层104以及封装盖板200。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在一些示例中，衬底101可以为刚性基底，例如玻璃基底。然而，本实施例对此并不限定。例如，衬底可以为柔性基底，例如由树脂等绝缘材料制备。另外，衬底可以为单层结构或多层结构。当衬底为多层结构时，例如氮化硅、氧化硅和氮氧化硅的无机材料可以以单层或多层置于多个层之间。
在一些示例中，每个子像素的电路结构层102可以包括构成像素电路的多个晶体管和存储电容，图3中以每个子像素包括的一个晶体管和一个存储电容为例进行示意。在一些可能的实现方式中，每个子像素的电路结构层102可以包括：设置在衬底101上的有源层；覆盖有源层的第一绝缘层11；设置在第一绝缘层11上的第一栅金属层(例如包括栅电极和第一电容电极)；覆盖第一栅金属层的第二绝缘层12；设置在第二绝缘层12上的第二栅金属层(例如包括第二电容电极)；覆盖第二栅金属层的第三绝缘层13，第一绝缘层11、第二绝缘层12和第三绝缘层13上开设有过孔，过孔暴露出有源层；设置在第三绝缘层13上的第一源漏金属层(例如包括晶体管的源电极和漏电极)，源电极和漏电极可以分别通过过孔与有源层连接；覆盖前述结构的第一平坦层14，第一平坦层14上开设有过孔，过孔暴露出漏电极。有源层、栅电极、源电极和漏电极可以组成晶体管105，第一电容电极和第二电容电极可以组成存储电容106。
在一些示例中，发光结构层103可以包括阳极层、像素定义层、有机发光层和阴极。阳极层可以包括发光元件的阳极，阳极可以设置在平坦层上，通过平坦层上开设的过孔与像素电路的晶体管的漏电极连接；像素定义层设置在阳极层和平坦层上，像素定义层上设置有像素开口，像素开口暴露出阳极；有机发光层至少部分设置在像素开口内，有机发光层与阳极连接；阴极设置在有机发光层上，阴极与有机发光层连接；有机发光层在阳极和阴极驱动下出射相应颜色的光线。
在一些示例中，封装结构层104可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可采用无机材料，第二封装层可采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层103。
在一些示例中，有机发光层可以至少包括在阳极上叠设的空穴注入层、空穴传输层、发光层和空穴阻挡层。在一些示例中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，空穴阻挡层可以是连接在一起的共通层。然而，本实施例对此并不限定。
图4为一种像素电路的等效电路图。在一些示例中，如图4所示，本示例的像素电路可以包括七个晶体管(即第一晶体管T1至第七晶体管T7)和一个存储电容Cst。其中，第三晶体管T3的栅极与第一节点N1电连接，第三晶体管T3的第一极与第二节点N2电连接，第三晶体管T3的第二极与第三节点N3电连接。第三晶体管T3还可以称为驱动晶体管。第四晶体管T4的栅极与第一扫描线GL电连接，第四晶体管T4的第一极与数据线DL电连接，第四晶体管T4的第二极与第三晶体管T3的第一极电连接。第四晶体管T4还可以称为数据写入晶体管。第二晶体管T2的栅极与第一扫描线GL电连接，第二晶体管T2的第一极与第三晶体管T3的栅极电连接，第二晶体管T2的第二极与第三晶体管T3的第二极电连接。第二晶体管T2还可以称为阈值补偿晶体管。第五晶体管T5的栅极与发光控制线EML电连接，第五晶体管T5的第一极与第二电源线VDD电连接，第五晶体管T5的第二极与第三晶体管T3的第一极电连接。第六晶体管T6的栅极与发光控制线EML电连接，第六晶体管T6的第一极与第三晶体管T3的第二极电连接，第六晶体管T6的第二极与发光元件EL的阳极电连接。第五晶体管T5和第六晶体管T6还可以称为发光控制晶体管。第一晶体管T1与第三晶体管T3的栅极电连接，并配置为对第三晶体管T3的栅极进行复位，第七晶体管T7与发光元件EL的阳极电连接，并配置为对发光元件EL的阳极进行复位。第一晶体管T1的栅极与第二扫描线RST1电连接，第一晶体管T1的第一极与第一初始信号线INIT1电连接，第一晶体管T1的第二极与第三晶体管T3的栅极电连 接。第七晶体管T7的栅极与第三扫描线RST2电连接，第七晶体管T7的第一极与第二初始信号线INIT2电连接，第七晶体管T7的第二极与发光元件EL的阳极电连接。第一晶体管T1和第七晶体管T7还可以称为复位控制晶体管。存储电容Cst的第一电容极板与第三晶体管T3的栅极电连接，存储电容Cst的第二电容极板与第二电源线VDD电连接。
在本示例中，第一节点N1为存储电容Cst、第一晶体管T1、第三晶体管T3和第二晶体管T2的连接点，第二节点N2为第五晶体管T5、第四晶体管T4和第三晶体管T3的连接点，第三节点N3为第三晶体管T3、第二晶体管T2和第六晶体管T6的连接点，第四节点N4为第六晶体管T6、第七晶体管T7和发光元件EL的连接点。
在一些示例中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在一些示例中，第二电源线VDD可以配置为向像素电路提供恒定的第二电压信号，第一电源线VSS可以配置为向像素电路提供恒定的第一电压信号，并且第二电压信号可以大于第一电压信号。第一扫描线GL可以配置为向像素电路提供扫描信号SCAN，数据线DL可以配置为向像素电路提供数据信号DATA，发光控制线EML可以配置为向像素电路提供发光控制信号EM，第二扫描线RST1可以配置为向像素电路提供第一复位控制信号RESET1，第三扫描线RST2可以配置为向像素电路提供第二复位控制信号RESET2。在一些示例中，第n行像素电路电连接的第二扫描线RST1可以与第n-1行像素电路的第一扫描线GL电连接，以被输入扫描信号SCAN(n-1)，即第一复位控制信号RESET1(n)与扫描信号SCAN(n-1)可以相同。第n行像素电路的第三扫描线RST2可以与第n行像素电路的第一扫描线GL电连接，以被输入扫描信号SCAN(n)，即第二复位控制信号RESET2(n)与扫描信号SCAN(n)可以相同。其中，n为大于0的整数。如此，可以减少显示基板的信号线，实现显示基板的窄边框设计。然而，本实施例对此并不限定。
在一些示例中，第一初始信号线INIT1可以配置为向像素电路提供第一初始信号，第二初始信号线INIT2可以配置为向像素电路提供第二初始信号。例如，第一初始信号可以不同于第二初始信号。第一初始信号和第二初始信号可以为恒压信号，其大小例如可以介于第一电压信号和第二电压信号之间，但不限于此。在另一些示例中，第一初始信号与第二初始信号可以相同，可以仅设置第一初始信号线来提供第一初始信号。
在一些实现方式中，显示基板在信赖性测试过程存在由于静电导致内部走线受损的情况。为了改善显示基板的抗静电释放能力，可以给内部走线连接静电释放(ESD)单元。然而，较长走线一般需要增加不止一个ESD单元，在显示基板的内部空间有限的情况下，没有足够的空间来排布足够的ESD单元，导致显示基板的抗静电能力无法得到有效提升，仍存在花屏现象。
本实施例提供一种显示基板，包括：衬底、设置在衬底上的第一电源线、多条第一信号引出线、多条测试连接走线、至少一条第一连接线以及多个测试信号接入引脚。衬底至少包括：显示区域、位于显示区域一侧的周边区域。第一电源线位于周边区域。多条第一信号引出线、多条测试连接走线、多个测试信号接入引脚以及至少一条第一连接线位于第一电源线远离显示区域的一侧。至少一条第一信号引出线通过至少一条测试连接走线与至少一个测试信号接入引脚电连接。第一连接线在第一方向上位于多条测试连接走线和多个测试信号接入引脚靠近周边区域边缘的一侧，第一连接线至少沿第二方向延伸，并与第一电源线电连接。第一方向与第二方向交叉，例如，第一方向垂直于第二方向。
本实施例提供的显示基板，设置与第一电源线电连接的第一连接线，并使第一连接线在第一方向上位于多条测试连接走线和多个测试信号接入引脚的外侧，可以提供静电导出通道，从而保护测试信号接入引脚以及与测试信号接入引脚电连接的信号走线。本实施例可以有效提高显示基板的抗静电能力。
在一些示例性实施方式中，在垂直于显示基板的方向上，第一连接线、第一电源线和多条测试连接走线可以位于多条第一信号引出线远离衬底的一侧。例如，第一连接线、第一电源线和多条测试连接走线可以为同层结构， 比如可以位于第一源漏金属层。多条第一信号引出线可以位于第一栅金属层。
在一些示例性实施方式中，第一连接线在衬底的正投影与多条第一信号引出线在衬底的正投影可以存在交叠。
图5为本公开至少一实施例的显示基板的第一边框的示意图。在一些示例中，如图5所示，显示基板的第一边框(下边框)B1可以至少包括：位于显示区域AA一侧的信号接入区B15和两个测试信号接入区(例如，第一测试信号接入区B16a和第二测试信号接入区B16b)、以及位于信号接入区B15和显示区域AA之间的第一区域B10。信号接入区B15和两个测试信号接入区在第一方向X上可以相邻。例如，两个测试信号接入区在第一方向X上可以位于信号接入区B15的相对两侧。例如，第一测试信号接入区B16a在第一方向X上可以位于信号接入区B15的左侧，第二测试信号接入区B16b在第一方向X上可以位于信号接入区B15的右侧。然而，本实施例对此并不限定。在另一些示例中，可以仅设置一个与信号接入区相邻的测试信号接入区。在本示例中，测试信号接入区保留在显示基板内。
在一些示例中，如图5所示，第一区域B10可以包括：在第二方向Y上沿着远离显示区域AA的方向依次设置的周边电路区B11、扇出走线区B12、封装区B13以及测试走线区B14。信号接入区B15、第一测试信号接入区B16a和第二测试信号接入区B16b可以位于测试走线区B14远离封装区B13的一侧。封装区B13可以为涂覆或印刷封装胶的区域。在一些示例中，封装区B13可以为围绕显示区AA的环形区域，从而有利于提高封装效果。
在一些示例中，如图5所示，第一边框B1的周边电路区B11可以设置有多路复用电路(MUX)311和静电释放(ESD)电路312。静电释放电路312可以位于多路复用电路311远离显示区域AA的一侧。多路复用电路311可以包括多个复用单元，每个复用单元可以与显示区域AA内的多条数据线电连接，可以被配置为使一个信号源为所述多条数据线提供数据信号。例如，每个复用单元可以电连接一条复用数据线，通过复用数据线可以电连接提供数据信号的信号源。复用数据线可以与静电释放电路312电连接，以便释放静电。
在一些示例中，如图5所示，扇出走线区B12可以设置有多条数据扇出 线333。多条数据扇出线333可以与周边电路区B11的多条复用数据线电连接。例如，多条数据扇出线333可以与多条复用数据线一一对应电连接。多条数据扇出线可以延伸至信号接入区B15，并与信号接入区B15内的多个第一信号接入引脚对应电连接。在一些示例中，多条数据扇出线333可以为同层结构，例如可以位于第一栅金属层。
在一些示例中，如图5所示，第一区域B10还可以设置有第一电源线321a和321b以及第二电源线322。第一电源线321a可以延伸至第三边框，第一电源线321b可以延伸至第四边框。例如，第一电源线321a和321b可以在第二边框内连接，形成一体结构。第一电源线321a和321b可以被配置为连接低电位电源线，传输第一电压信号。第二电源线322可以被配置为连接显示区域AA的高电位电源线，传输第二电压信号。第一电源线321a和321b在第一方向X上可以位于第二电源线322的相对两侧。第一电源线321a和321b可以均延伸至信号接入区B15，并与信号接入区B15的第一电源接入引脚电连接，第二电源线322可以延伸至信号接入区B15，并与信号接入区B15的第二电源接入引脚电连接。在一些示例中，第一电源线321a和321b以及第二电源线322可以为同层结构，例如可以位于第一源漏金属层。第一电源线321a和321b和第二电源线322与多条数据扇出线333可以为异层设置。第一电源线321a和321b在衬底的正投影与多条数据扇出线333在衬底的正投影可以部分交叠，第二电源线322在衬底的正投影与多条数据扇出线333在衬底的正投影可以部分交叠。
在一些示例中，如图5所示，第一电源线321a和321b以及第二电源线322可以从扇出走线区B12经过封装区B13延伸至测试走线区B14。位于封装区B13的第一电源线321a和321b可以作为第一封装胶基底，位于封装区B13的第二电源线322可以作为第二封装胶基底。换言之，第一封装胶基底可以与第一电源线321a或321b电连接，第二封装胶基底可以与第二电源线322电连接。第一封装胶基底和第二封装胶基底可以开设有多个开孔。通过在封装胶基底设置多个开孔，使得在封装胶基底上涂覆封装胶时，封装胶会漏入开孔内，相当于在封装胶基底的上面和内部都有封装胶，在通过激光进行封装胶熔融时，可以进一步提高封装胶的粘合强度，增强衬底基板和封装 盖板的结合力，从而提高产品良率。
在一些示例中，如图5所示，第一区域B10还可以设置有第一周边电源连接线323。第一周边电源连接线323可以与第一电源线321a或321b电连接。第一周边电源连接线323可以位于第一电源线321a和321b靠近衬底的一侧，例如可以位于第一栅金属层。第一周边电源连接线323可以设置有多个过孔。第一周边电源连接线323在第一方向X上可以位于第一电源线321a或321b远离第二电源线322的一侧。以第一周边电源连接线323和第一电源线321a电连接为例，第一周边电源连接线323和第一电源线321a在第二方向Y上相邻，第一周边电源连接线323在第二方向Y上与第一电源线321a靠近的边缘具有多个第一凸出部，第一电源线321a在第二方向Y上与第一周边电源连接线323靠近的边缘具有多个第二凸出部，多个第二凸出部和多个第一凸出部可以一一对应电连接，实现第一周边电源连接线323和第一电源线321a之间的电连接。在一些示例中，通过增加第一周边电源连接线323在第一方向X的长度，可以减小第一电源线321a沿第一方向X的长度。通过减少第一电源线沿第一方向的长度，可以改善高温高湿环境下第一封装胶基底容易腐蚀或开裂的情况，从而提高产品良率。
在一些示例中，如图5所示，测试走线区B14可以设置有多条第一信号引出线341和多条测试连接走线342。多条第一信号引出线341在测试走线区B14可以沿第一方向X延伸，还可以沿第二方向Y向显示区域AA一侧延伸。例如，多条第一信号引出线341可以在扇出走线区B12与多条信号连接线电连接，以进一步延伸至第三边框和第四边框。多条第一信号引出线341可以延伸至信号接入区B15，并与信号接入区B15内的多个信号接入引脚电连接。多条第一信号引出线341可以为同层结构，例如可以位于第一栅金属层。多条第一信号引出线341还可以通过多条测试连接走线342与测试信号接入区B16a或B16b内的多个测试信号接入引脚361电连接。例如，多条第一信号引出线341与多条测试连接走线342可以一一对应电连接。多条测试连接走线342可以位于多条第一信号引出线341远离衬底的一侧，例如可以位于第一源漏金属层。
图7为本公开至少一实施例的信号接入区和测试信号接入区的局部示意 图。在一些示例中，如图7所示，信号接入区B15可以包括多个并排平行设置的信号接入引脚351，多个信号接入引脚351可以沿第一方向X依次排布。多个信号接入引脚351可以被配置为与柔性线路板或驱动芯片绑定连接，从而获取来自柔性线路板或驱动芯片的信号。多个信号接入引脚351可以包括：多个第一电源接入引脚、多个第二电源接入引脚以及多个第一信号接入引脚。第一电源接入引脚可以与第一电源线321a或321b电连接，第二电源接入引脚可以与第二电源线322电连接，至少部分第一信号接入引脚可以与多条数据扇出线333电连接，至少部分第一信号接入引脚可以与多条第一信号引出线341电连接。在一些示例中，在第一方向X上，第一电源接入引脚和第二电源接入引脚可以位于多个第一信号接入引脚的相对两侧。第一电源接入引脚可以与测试信号接入区B16a或B16b相邻。在一些示例中，第一电源接入引脚和第二电源接入引脚沿第一方向X的长度可以大于第一信号接入引脚沿第一方向X的长度，第一电源接入引脚、第二电源接入引脚和第一信号接入引脚沿第二方向Y的长度可以相同。在一些示例中，第一电源接入引脚和第二电源接入引脚的尺寸可以大于第一信号接入引脚的尺寸。然而，本实施例对此并不限定。
在一些示例中，如图7所示，以第一测试信号接入区B16a为例进行说明。第一测试信号接入区B16a可以包括多个并排平行设置的测试信号接入引脚361，多个测试信号接入引脚361可以沿第一方向X依次排布。多个测试信号接入引脚361与信号接入区域B15的多个信号接入引脚351可以平行设置。多个测试信号接入引脚361可以配置为在电子测试(ET，Electronic Test)过程中，与测试装置(例如，柔性线路板)的测试探针接触，从而获得来自测试探针的信号。在一些示例中，第一测试信号接入区域B16a的测试信号接入引脚361可以通过测试连接走线342和第一信号引出线341与边框区域的测试电路和扫描驱动电路电连接，配置为给测试电路和扫描驱动电路提供测试信号。然而，本实施例对此并不限定。
在一些示例中，如图7所示，多个测试信号接入引脚361沿第一方向X的长度可以大致相同，多个测试信号接入引脚361沿第二方向Y的长度可以大致相同。多个测试信号接入引脚361的尺寸可以大致相同。然而，本实施 例对此并不限定。
在一些示例中，如图5所示，第二测试信号接入区域B16b的多个测试信号接入引脚361可以通过测试连接走线342和第一信号引出线341与边框区域的测试电路和发光驱动电路电连接，配置为给测试电路和发光驱动电路提供测试信号。关于第二测试信号接入区B16b的测试信号接入引脚的结构可以参照第一测试信号接入区B16a的说明，故于此不再赘述。
在一些示例中，测试电路可以包括：至少一个测试控制信号线、多个测试数据线和多个测试单元。每个测试单元与测试控制信号线、测试数据线以及显示区域的多个数据线电连接。测试单元可以配置为根据测试控制信号线的控制，将测试数据线的信号(测试数据信号)提供给(同时提供或分别提供)与其连接的显示区域的多个数据线，以检测和定位显示区域发生不良的子像素。例如，测试电路可以位于第二边框。然而，本实施例对此并不限定。
在一些示例中，在电子测试过程中，可以通过信号接入区B15的第一电源接入引脚和第二电源接入引脚(即连接第一电源线和第二电源线的引脚)向显示基板提供第一电压信号和第二电压信号。本示例中，在电子测试过程中，可以借用信号接入区B15的第一电源接入引脚提供第一电压信号，借用信号接入区B15的第二电源接入引脚提供第二电压信号。然而，本实施例对此并不限定。例如，可以设置至少部分测试信号接入引脚与第一电源线和第二电源线电连接。
在一些示例性实施方式中，多条第一信号引出线可以被配置为传输以下至少之一信号：扫描起始信号、扫描时钟信号、发光起始信号、发光时钟信号、驱动电源信号、测试数据信号、测试控制信号。例如，传输扫描起始信号、扫描时钟信号和驱动电源信号的多条第一信号引出线可以与扫描驱动电路电连接。传输发光起始信号、发光时钟信号和驱动电源信号的多条第一信号引出线可以与发光驱动电路电连接。传输测试数据信号和测试控制信号的多条第一信号引出线可以与测试电路电连接。
图8为本公开至少一实施例的周边区域的走线示例图。在一些示例中，如图8所示，显示基板的第二边框B1可以设置有测试电路313，第三边框B3可以设置扫描驱动电路23，第四边框B4可以设置发光驱动电路24。在 电子测试过程中，第一边框B1的第一测试信号接入区B16a内的多个测试信号接入引脚可以通过向第三边框B3延伸的多条第一信号引出线341给扫描驱动电路23提供扫描起始信号(GSTV)、扫描时钟信号以及驱动电源信号，还可以通过多条第一信号引出线341给测试电路313提供测试数据信号和测试控制信号。在电子测试过程中，第一边框B1的第二测试信号接入区B16b内的多个测试信号接入引脚可以通过向第四边框B4延伸的多条第一信号引出线341给发光驱动电路24提供发光起始信号(ESTV)、发光时钟信号以及驱动电源信号，还可以通过多条第一信号引出线341给测试电路313提供测试数据信号和测试控制信号。多条第一信号引出线341可以经由第三边框B3或第四边框B4与第二边框B2内的测试电路313电连接。然而，本实施例对此并不限定。在另一些示例中，第三边框和第四边框可以均设置有扫描驱动电路和发光驱动电路，测试信号接入引脚可以通过多条第一信号引出线分别给第三边框和第四边框内的扫描驱动电路提供信号，分别给第三边框和第四边框内的发光驱动电路提供信号。
在一些示例中，多条第一信号引出线341还可以与信号接入区B15内的信号接入引脚电连接。例如，与信号接入引脚电连接的多条第一信号引出线可以提供扫描起始信号、扫描时钟信号、发光起始信号、发光时钟信号以及驱动电源信号，以便在正常显示过程中向扫描驱动电路和发光驱动电路提供信号。
图6为本公开至少一实施例的第一边框的第一平坦层的示意图。在一些示例中，如图6所示，在显示基板的制备过程中，在制备封装结构层后可以在衬底上贴设封装盖板，随后，可以沿第二切割道Q2进行切割以得到单个显示基板。第二切割道Q2所在位置可以对应切割后的单个显示基板的边缘。沿第一切割道Q1进行切割可以将部分封装盖板去除，可以暴露出信号接入区B15的信号接入引脚和两个测试信号接入区的测试信号接入引脚361。暴露的信号接入引脚可以与柔性线路板或驱动芯片进行绑定连接。暴露的测试信号接入引脚361可以与测试装置接触进行电子测试。第一信号引出线341和测试连接走线342的连接位置可以位于第一切割道Q1远离第一封装胶基底的一侧，从而避免测试连接走线与第一封装胶基底之间的距离过近而导致 短路的情况。
在一些示例中，如图6所示，第一边框B1还可以设置有第一平坦层14。图6中黑点阴影覆盖区域的第一平坦层14可以被去除，暴露出第一源漏金属层的表面。第一边框B1的周边电路区内的第一平坦层14可以保留，测试走线区的部分区域的第一平坦层14可以保留。第一边框B1内保留的第一平坦层14在衬底的正投影可以覆盖多条第一信号引出线341和多条测试连接走线342的连接位置。
在一些示例中，如图6所示，第一平坦层14靠近显示区域AA的边缘与第一封装胶基底远离显示区域AA边缘之间的距离可以大于或等于50微米，例如可以大于或等于120微米。在一些示例中，第一切割道Q1在衬底的正投影可以为与第一平坦层14存在交叠。第一切割道Q1可以位于第一平坦层14靠近显示区域AA一侧的边缘远离显示区域AA的一侧。例如，第一切割道Q1与第一封装胶基底远离显示区域AA边缘之间的距离可以约为200微米。然而，本实施例对此并不限定。
本示例通过将第一信号引出线341和测试连接走线342的连接位置设置在第一切割道Q1远离显示区域AA的一侧，且该连接位置可以被第一平坦层14覆盖和保护，从而可以避免走线在高温高湿情况下失效，避免发生电化学腐蚀而引起的显示异常。
在一些示例中，如图5所示，第一测试信号接入区B16a在第一方向X上远离信号接入区B15的一侧可以设置有第一辅助标记371。第一辅助标记371在第一方向X上远离第一测试信号接入区B16a的一侧可以设置有第二辅助标记372。同理，在第二测试信号接入区B16b远离信号接入区B15的一侧也设置有第一辅助标记371和第二辅助标记372。例如，第一辅助标记371的尺寸可以小于第二辅助标记372的尺寸。在一些示例中，第一辅助标记371和第二辅助标记372在衬底的正投影可以为十字型。然而，本实施例对此并不限定。例如，第一辅助标记和第二辅助标记中至少之一可以为L型。本示例通过设置第一辅助标记，可以有助于在电子测试过程中，测试探针与测试信号接入区内的测试信号接入引脚的准确对位。在另一些示例中，第一边框的空间有限时可以仅设置第一辅助标记。
在一些示例中，如图5所示，第一辅助标记371和第二辅助标记372可以为同层结构，例如可以位于第一源漏金属层。然而，本实施例对此并不限定。
在一些示例中，如图5所示，第一电源线321a可以通过一条第一连接线381与一个第二辅助标记372电连接。第一电源线321b可以通过另一条第一连接线381与另一个第二辅助标记372电连接。第一连接线381可以沿第二方向Y延伸。例如，第一电源线321a、第一连接线381和第二辅助标记372可以为一体结构。然而，本实施例对此并不限定。
在一些示例中，第一边框B1的左侧区域和右侧区域的结构可以大致相同，下述示例以第一边框B1的右侧区域为例进行说明。图9为图5中区域C1的局部放大示意图。图10为图9中沿P-P’方向的局部剖面示意图。图11A为图9中第一栅金属层的示意图。图11B为图9中第一源漏金属层的示意图。
在一些示例中，如图9和图11A所示，测试走线区的第一信号引出线341可以包括第一主体341a和第一弯折部341b。第一主体341a可以沿第一方向X延伸，第一弯折部341b可以沿第二方向Y向第二辅助标记372一侧凸出。第一弯折部341b可以具有依次连接的第一延伸部、第二延伸部和第三延伸部。第一延伸部和第三延伸部可以与第一主体341a连接，第二延伸部连接在第一延伸部和第三延伸部之间。第二延伸部可以沿第一方向X延伸，第一延伸部和第三延伸部的延伸方向可以相互交叉，并可以与第一方向X和第二方向Y均交叉。第一延伸部和第三延伸部向远离显示区域AA一侧延伸。第一弯折部341b在衬底的正投影可以呈凹槽状。在本示例中，多条第一信号引出线341可以均位于测试走线区内。然而，本实施例对此并不限定。在另一些示例中，至少一条第一信号引出线341的第一弯折部341b可以延伸至与第二辅助标记372交叠，或者，可以延伸至在第一方向X上位于第二辅助标记372远离第一测试信号接入区B16b一侧的区域内。
在一些示例中，如图9、图11A和图11B所示，多条测试连接走线342与多条第一信号引出线341可以一一对应电连接。例如，一部分测试连接走线342可以与对应的第一信号引出线341的第一弯折部341b电连接，例如可以与第一弯折部341b的第二延伸部电连接。在一些示例中，第一测试信号接 入区B16b内靠近第一辅助标记371的测试信号接入引脚361可以与靠近第一封装胶基底的第一信号引出线341电连接，远离第一辅助标记371的测试信号接入引脚361可以与远离第一封装胶基底的第一信号引出线341电连接。靠近第一辅助标记371的测试信号接入引脚361电连接的测试连接走线342可以与对应的第一信号引出线341的第一弯折部341b电连接。远离第一辅助标记371的测试信号接入引脚361电连接的测试连接走线342可以沿第二方向Y延伸后与对应的第一信号引出线341的第一主体341a电连接。在本示例中，多条测试连接走线342和多条第一信号引出线341的连接位置在第一方向X上可以位于第一连接线381靠近第一辅助标记371的一侧。然而，本实施例对此并不限定。在另一些示例中，在第一边框的空间足够时，至少一条测试连接走线和至少一条第一信号引出线的连接位置在第一方向X上可以位于第一连接线381远离第一辅助标记371的一侧。
在一些示例中，如图10所示，测试信号接入引脚361可以包括：第一子引脚3611和第二子引脚3612。第一子引脚3611与第二子引脚3612可以相互电连接。第一子引脚3611可以位于第一栅金属层，第二子引脚3612可以位于第一源漏金属层。第二子引脚3612可以通过第三绝缘层13和第二绝缘层12开设的凹槽与第一子引脚3611电连接。第二子引脚3612在衬底101的正投影可以包含第一子引脚3611在衬底101的正投影。第二子引脚3612与对应电连接的测试连接走线342可以为一体结构。
在一些示例中，如图9、图11A和图11B所示，第一连接线381可以沿第二方向Y延伸，且可以电连接第一电源线321a和第二辅助标记371。第一连接线381与第二辅助标记372在第二方向Y上可以对齐。例如，第一连接线381沿第一方向X的中线和第二辅助标记372沿第一方向X的中线可以对齐。在一些示例中，第一连接线381、第一电源线321a和第二辅助标记371可以为一体结构，例如可以位于第一源漏金属层。多条第一信号引出线341可以位于第一栅金属层。第一连接线381在衬底的正投影可以与多条第一信号引出线341在衬底的正投影可以存在交叠。其中，第一连接线381在衬底的正投影可以与多条第一信号引出线341的第一弯折部341b在衬底的正投影存在交叠。第一连接线381在第一方向X上可以位于多条测试连接走线342 的一侧。在本示例中，第一连接线381在第一方向X上位于多条测试连接走线342和多个测试信号接入引脚361靠近第一边框区域的一侧，即第一连接线381可以在第一方向X上位于多条测试连走线342和多个测试信号接入引脚361的外围，可以提供静电导出路径，降低静电对信号走线的损伤，可以给测试信号接入引脚提供保护，从而提高显示基板的抗静电能力。
图12为图9中区域C2的局部放大示意图。图13为图12中沿R-R’方向的局部剖面示意图。在一些示例中，如图12和图13所示，测试连接走线342与第一信号引出线341的连接端可以为T字型。至少一条测试连接走线342可以沿第二方向Y向远离显示区域AA一侧延伸后再沿第一方向X延伸，直至连接测试信号接入引脚361的第二子引脚3612。至少一条测试连接走线342可以沿第二方向Y向靠近显示区域AA一侧延伸后再沿第一方向X延伸，直至连接测试信号接入引脚361的第二子引脚3612。
在一些示例中，如图3所示，第一信号引出线341可以位于第一栅金属层，测试连接走线342可以位于第一源漏金属层。然而，本实施例对此并不限定。
下面通过显示基板的制备过程的示例说明本公开显示基板的结构。本公开所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶等处理。沉积可以采用选自溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用选自喷涂和旋涂中的任意一种或多种，刻蚀可以采用选自干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。当在整个制作过程当中该“薄膜”还需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。
本公开中所说的“A和B为同层结构”是指，A和B通过同一次构图工艺同时形成。“相同层”不总是意味着层的厚度或层的高度在截面图中是相同的。“A的正投影包含B的正投影”是指，B的正投影落入A的正投影范围内，或者A的正投影覆盖B的正投影。
在一些示例性实施方式中，本实施例的显示基板的制备过程可以包括以 下步骤。
(1)、提供衬底。在一些示例中，衬底101可以为刚性基板，例如玻璃基板。然而，本实施例对此并不限定。例如，衬底可以为柔性基板。
(2)、制备半导体层。在一些示例中，在衬底101上沉积半导体薄膜，通过构图工艺对半导体薄膜进行构图，形成半导体层。如图3所示，显示区域的半导体层至少可以包括像素电路的晶体管的有源层。
(3)、制备第一栅金属层。在一些示例中，在形成上述结构的衬底101上，依次沉积第一绝缘薄膜和第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成覆盖半导体层的第一绝缘层11，以及设置在第一绝缘层11上的第一栅金属层。如图3所示，显示区域的第一栅金属层至少包括：像素电路的晶体管的栅电极和存储电容的第一电容电极。如图5所示，第一边框的第一栅金属层至少可以包括：多条数据扇出线333、第一周边电源连接线323、多条第一信号引出线341、位于信号接入区B15的多个信号接入引脚的第一子引脚、位于测试信号接入区的多个测试信号接入引脚361的第一子引脚。
(4)、制备第二栅金属层。在一些示例中，在形成上述结构的衬底101上，依次沉积第二绝缘薄膜和第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成第二绝缘层12以及设置在第二绝缘层12上的第二栅金属层。如图3所示，显示区域的第二栅金属层可以至少包括像素电路的存储电容的第二电容电极。
(5)、制备第三绝缘层。在一些示例中，在形成上述结构的衬底101上，沉积第三绝缘薄膜，通过构图工艺对第三绝缘薄膜进行构图，形成第三绝缘层。第三绝缘层13可以开设有多个过孔或凹槽。
(6)、制备第一源漏金属层。在一些示例中，在形成上述结构的衬底101上，沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，形成第一源漏金属层。如图3所示，显示区域的第一源漏金属层可以至少包括：像素电路的多个晶体管的源电极和漏电极。如图5所示，第一边框的第一源漏金属层可以至少包括：第一电源线321a和321b、第二电源线322、多条测试连接走线342、第一辅助标记371、第二辅助标记372、位于信号接入区域 的多个信号接入引脚的第二子引脚、位于测试信号接入区的多个测试信号接入引脚361的第二子引脚。测试连接走线342可以通过第三绝缘层和第二绝缘层开设的过孔与第一信号引出线341电连接。测试信号接入引脚361的第二子引脚可以通过第三绝缘层和第二绝缘层开设的凹槽与对应的第一子引脚电连接。信号接入引脚的第二子引脚可以通过第三绝缘层和第二绝缘层开设的凹槽与对应的第一子引脚电连接。
至此，在衬底101上制备完成显示区域的电路结构层，如图3所示。在一些示例中，第一绝缘薄膜至第三绝缘薄膜可以均采用无机材料，例如，硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。
(7)、在衬底上依次制备平坦层、发光结构层和封装结构层。在一些示例中，在形成前述结构的衬底101上，涂覆第一平坦薄膜，通过构图工艺形成第一平坦层14。在第一边框B1内保留部分第一平坦层14以覆盖测试连接走线342和第一信号引出线341的连接位置。
随后，在显示区域沉积第一导电薄膜，通过构图工艺对第一导电薄膜进行构图，形成阳极层图案。阳极层的阳极可以通过第一平坦层上的过孔与像素电路电连接。随后，涂覆像素定义薄膜，通过掩膜、曝光、显影工艺，形成像素定义层图案。像素定义层形成在显示区域。显示区域的像素定义层上开设有像素开口，像素开口内的像素定义薄膜被显影掉，暴露出阳极的表面。随后，在形成前述图案的衬底上依次形成有机发光层和阴极。例如，有机发光层包括叠设的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层，形成在显示区域的像素开口内，实现有机发光层与阳极连接。阴极的一部分形成在有机发光层上。
在一些示例中，在形成前述图案的衬底上，形成封装结构层。封装结构层可以形成在显示区域，可以采用无机材料/有机材料/无机材料的叠层结构。有机材料层设置在两个无机材料层之间。
在一些示例性实施方式中，第一平坦层、像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。
在上述制备过程中，边框区域的扫描驱动电路和发光驱动电路的制备过 程类似于显示区域的电路结构层的制备过程，故于此不再赘述。
在一些示例中，在制备完成封装结构层之后，可以通过封装工艺贴合衬底和封装盖板，然后通过切割得到单个显示基板，并按照第一切割道对封装盖板进行切割，以暴露出信号接入区的信号接入引脚和测试信号接入区的测试信号接入引脚。在一些示例中，封装盖板远离衬底基板一侧可以设置有触控结构层，从而形成触控显示基板。然而，本实施例对此并不限定。
本示例性实施例的制备工艺利用现有成熟的制备设备即可实现，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本示例性实施例的显示基板的结构及其制备过程仅仅是一种示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，显示区域可以设置第一源漏金属层和第二源漏金属层，第一源漏金属层可以包括晶体管的源电极和漏电极，第二源漏金属层可以包括发光元件和晶体管的漏电极之间的连接电极。此时，第一电源线、第二电源线和测试连接走线可以位于第二源漏金属层；或者，第一电源线和第二电源线可以位于第二源漏金属层，测试连接走线可以位于第一源漏金属层。然而，本实施例对此并不限定。
图14为本公开至少一实施例的第一边框的另一局部放大示意图。图15为图14中第一栅金属层的示意图。在本示例中，以第一边框的右侧区域为例进行示意和说明。第一边框的左侧区域的结构与右侧区域的结构类似，故于此不再赘述。
在一些示例中，如图14和图15所示，多条第一信号引出线341在测试走线区可以沿第一方向X延伸，多条测试连接走线342可以沿第二方向Y延伸。测试连接走线342的一端可以与第一信号引出线341电连接，另一端可以与测试引号接入区B16b的测试信号接入引脚361电连接，例如可以与测试信号接入引脚361的第二子引脚为一体结构。然而，本实施例对此并不限定。
在一些示例中，如图14和图15所示，显示基板还可以包括：位于第一栅金属层的辅助电源引脚391。辅助电源引脚391在第一方向X上可以位于 测试信号接入区远离信号接入区的一侧。辅助电源引脚391在第一方向X上可以与测试信号接入引脚361对齐。例如，辅助电源引脚391沿第二方向Y的中线与测试信号接入引脚361沿第二方向Y的中线可以对齐。辅助电源引脚391与测试信号接入引脚361的第一子引脚3611为同层结构，且两者的形状和尺寸可以大致相同。辅助电源引脚391在衬底的正投影可以位于第一辅助标记371和第二辅助标记372在衬底的正投影之间。第一连接线381的一端可以通过第三绝缘层和第二绝缘层开设的凹槽与辅助电源引脚391电连接，另一端可以与第一电源线321a电连接。第一连接线381与第一电源线321a可以为一体结构。第一连接线381可以为沿第二方向Y延伸的条形走线。
本示例通过在第一辅助标记和第二辅助标记之间增设辅助电源引脚，并通过第一连接线电连接辅助电源引脚和第一电源线，可以在多条测试连接走线和测试信号接入引脚的外围增设静电导出路径，可以降低静电对信号走线的损伤，并给测试信号接入引脚提供保护，从而提高显示基板的抗静电能力。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图16为本公开至少一实施例的第一边框的另一局部放大示意图。在一些示例中，如图16所示，第一连接线381与第二辅助标记372之间可以断开。第一连接线381在第二方向Y可以与第二辅助标记372对齐，第一连接线381与第二辅助标记372可以没有电性连接。本示例中，第一连接线381在第一方向X上位于多条测试连接走线342和多个测试信号接入引脚361的外围，可以降低静电对信号走线的损伤，并给测试信号接入引脚提供保护，从而提高显示基板的抗静电能力。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图17为本公开至少一实施例的第一边框的另一局部放大示意图。在一些示例中，如图17所示，第一连接线381与第二辅助标记372可以电连接。第二辅助标记372可以通过第三连接线383与第一辅助标记371电连接。第三连接线383可以沿第一方向X延伸。在一些示例中，第二辅助标记372、第一辅助标记371和第三连接线383可以为同层结构，比如均位于第一源漏金属层。例如，第二辅助标记372、第一辅助标记371和第三连接线383可以 为一体结构。然而，本实施例对此并不限定。例如，第三连接线可以位于第一辅助标记和第二辅助标记靠近衬底的一侧，比如可以位于第一栅金属层。本示例中，通过第三连接线将第一辅助标记和第二辅助标记电连接，可以进一步包围测试信号接入引脚所电连接的信号走线，可以降低静电对信号走线的损伤，从而提高显示基板的抗静电能力。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图18为本公开至少一实施例的第一边框的另一局部放大示意图。在一些示例中，如图18所示，第一连接线381与第二辅助标记372可以电连接。第一连接线381在衬底的正投影与多条第一信号引出线341的第一主体341a在衬底的正投影存在交叠。多条第一信号引出线341的第一弯折部341b在第一方向X上可以位于第一连接线381靠近第二测试信号接入区B16b的一侧。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图19为本公开至少一实施例的第一边框的另一局部放大示意图。在一些示例中，如图19所示，位于第一栅金属层的第一周边电源连接线323可以与第二连接线382电连接，例如两者可以为一体结构。第一周边电源连接线323靠近第四边框的部分可以与第二连接线382电连接。第二连接线382可以从第一周边电源连接线323沿第二方向Y向远离显示区域一侧延伸，随后沿第一方向X向靠近测试信号接入区一侧延伸，直至靠近第一连接线381。在一些示例中，第二连接线382与第一连接线381可以没有电连接。然而，本实施例对此并不限定。例如，第二连接线382可以与第一连接线381电连接。
在一些示例中，如图19所示，第二连接线382可以位于多条第一信号引出线341远离显示区域的一侧。第二连接线382可以位于多条第一信号引出线341靠近第一边框边缘的一侧。第二连接线382可以包围多条第一信号引出线341的外侧。本示例的第二连接线382可以提供静电释放路径，还可以对第一信号引出线提供保护，从而提高显示基板的抗静电能力。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图20为本公开至少一实施例的第一边框的另一局部放大示意图。在一些示例中，如图20所示，位于第一源漏金属层的第一电源线321a可以与第二 连接线382电连接，例如，两者可以为一体结构。第一电源线321a的靠近第四边框的部分可以与第二连接线382电连接。第二连接线382可以从第一电源线321a沿第二方向Y向远离显示区域一侧延伸，随后沿第一方向X向靠近测试信号接入区一侧延伸，直至靠近第二辅助标记372。在一些示例中，第二连接线382与第二辅助标记372可以电连接。然而，本实施例对此并不限定。例如，第二连接线382可以与第二辅助标记372可以没有电连接。本实施例可以有效提高显示基板的抗静电能力。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
在另一些示例中，上述实施例可以相互组合。例如，第一连接线和第二连接线可以连接第一电源线和第二辅助标记，第一辅助标记和第二辅助标记可以通过第三连接线电连接。又如，第一连接线与第二辅助标记可以没有电连接，第二连接线与第二辅助标记电连接。然而，本实施例对此并不限定。
本公开实施例还提供一种显示装置，包括前述实施例的显示基板。显示基板可以为OLED显示基板。显示装置可以为：OLED显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (20)

  1. 一种显示基板，包括：
    衬底，至少包括：显示区域、位于所述显示区域一侧的周边区域；
    第一电源线，位于所述周边区域；
    多条第一信号引出线、多条测试连接走线、多个测试信号接入引脚和至少一条第一连接线，位于所述第一电源线远离所述显示区域的一侧；至少一条第一信号引出线通过至少一条测试连接走线与至少一个测试信号接入引脚电连接；
    所述第一连接线在第一方向上位于所述多条测试连接走线和所述多个测试信号接入引脚靠近所述周边区域边缘的一侧，所述第一连接线至少沿第二方向延伸，并与所述第一电源线电连接；所述第一方向与第二方向交叉。
  2. 根据权利要求1所述的显示基板，其中，在垂直于所述显示基板的方向上，所述第一连接线、所述第一电源线和所述多条测试连接走线位于所述多条第一信号引出线远离所述衬底的一侧。
  3. 根据权利要求2所述的显示基板，其中，所述第一连接线、所述第一电源线和所述多条测试连接走线为同层结构。
  4. 根据权利要求1至3中任一项所述的显示基板，其中，所述第一连接线在所述衬底的正投影与所述多条第一信号引出线在所述衬底的正投影存在交叠。
  5. 根据权利要求1至4中任一项所述的显示基板，其中，所述周边区域至少包括：位于所述显示区域一侧的至少一个测试信号接入区、至少一个第一辅助标记和至少一个第二辅助标记；所述第二辅助标记在所述第一方向上位于所述第一辅助标记远离所述测试信号接入区的一侧；
    所述第一连接线和所述第二辅助标记在所述第二方向上对齐。
  6. 根据权利要求5所述的显示基板，其中，所述第一连接线与所述第二辅助标记电连接。
  7. 根据权利要求6所述的显示基板，其中，所述第一连接线与所述第二 辅助标记为一体结构。
  8. 根据权利要求1至4中任一项所述的显示基板，其中，所述周边区域至少包括：位于所述显示区域一侧的至少一个测试信号接入区、至少一个第一辅助标记和至少一个第二辅助标记；所述第二辅助标记在所述第一方向上位于所述第一辅助标记远离所述测试信号接入区的一侧；
    所述第一连接线在所述第一方向上位于所述第一辅助标记和第二辅助标记之间。
  9. 根据权利要求8所述的显示基板，还包括：至少一个辅助电源引脚，所述辅助电源引脚在所述第一方向上位于所述第一辅助标记和第二辅助标记之间，所述第一连接线与所述辅助电源引脚电连接。
  10. 根据权利要求5至9中任一项所述的显示基板，其中，所述至少一条第一信号引出走线具有向所述第二辅助标记一侧凸出的第一弯折部；所述至少一条测试连接走线与所述第一信号引出走线的第一弯折部电连接；
    所述第一连接线在所述衬底的正投影与所述第一信号引出线的第一弯折部在所述衬底的正投影存在交叠。
  11. 根据权利要求5至9中任一项所述的显示基板，其中，所述至少一条第一信号引出走线具有向所述第二辅助标记一侧凸出的第一弯折部；所述至少一条测试连接走线与所述第一信号引出走线的第一弯折部电连接；
    所述第一连接线在所述衬底的正投影与所述第一信号引出线的第一弯折部在所述衬底的正投影没有交叠，且所述第一信号引出线的第一弯折部位于所述第一连接线靠近所述测试信号接入区的一侧。
  12. 根据权利要求5至11中任一项所述的显示基板，其中，所述第一辅助标记通过第三连接线与相邻的第二辅助标记电连接。
  13. 根据权利要求12所述的显示基板，其中，所述第一辅助标记、所述第三连接线和所述第二辅助标记为一体结构。
  14. 根据权利要求5至13中任一项所述的显示基板，其中，所述周边区域还包括：位于所述显示区域和所述测试信号接入区之间的第一区域；
    所述多个测试信号接入引脚位于所述测试信号接入区，所述第一电源线、 所述多条第一信号引出线和多条测试连接走线至少位于所述第一区域。
  15. 根据权利要求5至14中任一项所述的显示基板，其中，所述周边区域还包括：沿所述第二方向位于所述显示区域一侧的信号接入区，所述信号接入区在所述第一方向上与所述测试信号接入区相邻；所述信号接入区包括：设置在所述衬底上的多个信号接入引脚；所述至少一条第一信号引出线与至少一个信号接入引脚电连接。
  16. 根据权利要求1至15中任一项所述的显示基板，还包括：与所述第一电源线电连接的第二连接线，所述第二连接线位于所述多条第一信号引出线远离所述显示区域的一侧。
  17. 根据权利要求16所述的显示基板，其中，所述第二连接线与所述第一电源线为一体结构。
  18. 根据权利要求16所述的显示基板，还包括：与所述第一电源线电连接的第一周边电源连接线，所述第一周边电源连接线位于所述第一电源线靠近所述衬底的一侧；所述第二连接线与所述第一周边电源连接线为一体结构。
  19. 根据权利要求1至18中任一项所述的显示基板，其中，所述多条第一信号引出线被配置为传输以下至少之一信号：扫描起始信号、扫描时钟信号、发光起始信号、发光时钟信号、驱动电源信号、测试数据信号、测试控制信号。
  20. 一种显示装置，包括如权利要求1至19中任一项所述的显示基板。
PCT/CN2022/102429 2022-06-29 2022-06-29 显示基板及显示装置 WO2024000292A1 (zh)

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CN110047816A (zh) * 2019-04-30 2019-07-23 厦门天马微电子有限公司 一种阵列基板、显示面板和显示装置
CN110488547A (zh) * 2019-09-03 2019-11-22 业成科技（成都）有限公司 显示面板
CN110827688A (zh) * 2019-11-22 2020-02-21 昆山国显光电有限公司 显示面板、显示面板母版和显示装置
US20200211428A1 (en) * 2018-12-28 2020-07-02 Xiamen Tianma Micro-Electronics Co., Ltd. Display panel and display apparatus
CN112838106A (zh) * 2019-11-22 2021-05-25 京东方科技集团股份有限公司 显示基板及显示装置

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US20200211428A1 (en) * 2018-12-28 2020-07-02 Xiamen Tianma Micro-Electronics Co., Ltd. Display panel and display apparatus
CN110047816A (zh) * 2019-04-30 2019-07-23 厦门天马微电子有限公司 一种阵列基板、显示面板和显示装置
CN110488547A (zh) * 2019-09-03 2019-11-22 业成科技（成都）有限公司 显示面板
CN110827688A (zh) * 2019-11-22 2020-02-21 昆山国显光电有限公司 显示面板、显示面板母版和显示装置
CN112838106A (zh) * 2019-11-22 2021-05-25 京东方科技集团股份有限公司 显示基板及显示装置

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