WO2022068383A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

Info

Publication number
WO2022068383A1
WO2022068383A1 PCT/CN2021/110632 CN2021110632W WO2022068383A1 WO 2022068383 A1 WO2022068383 A1 WO 2022068383A1 CN 2021110632 W CN2021110632 W CN 2021110632W WO 2022068383 A1 WO2022068383 A1 WO 2022068383A1
Authority
WO
WIPO (PCT)
Prior art keywords
voltage signal
sub
lead
layer
display panel
Prior art date
Application number
PCT/CN2021/110632
Other languages
English (en)
French (fr)
Inventor
田雪雁
殷新社
李威
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/926,706 priority Critical patent/US20230209949A1/en
Publication of WO2022068383A1 publication Critical patent/WO2022068383A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05F—STATIC ELECTRICITY; NATURALLY-OCCURRING ELECTRICITY
    • H05F3/00—Carrying-off electrostatic charges
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/179—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/875—Arrangements for extracting light from the devices
    • H10K59/878—Arrangements for extracting light from the devices comprising reflective means

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • a mirror display device which can realize the display function and the mirror function at the same time, that is, when the user sees the display screen from the mirror display device, the mirror display device can also be used as a mirror.
  • a display panel has a display area and a frame area beside the display area.
  • the display panel includes: a substrate; a plurality of sub-pixels disposed on one side of the substrate and located in the display area; a mirror layer disposed on a side of the plurality of sub-pixels away from the substrate; and,
  • the electrostatic protection part is electrically connected to the mirror surface layer and located in the frame area.
  • the static electricity protection part is configured to perform static electricity protection on the mirror surface layer.
  • the border region includes a binding region.
  • the display panel has at least one first fixed voltage signal terminal disposed in the binding area, wherein the electrostatic protection part includes a first sub electrostatic protection part that is also electrically connected to the first fixed voltage signal terminal.
  • the first sub-static protection part is configured to transmit static electricity generated in the mirror layer to the first fixed voltage signal terminal.
  • the display panel further includes: at least one low power supply voltage signal line disposed in the frame region; at least one low power supply voltage signal line disposed in the binding region and electrically connected to the low power supply voltage signal line a first conductive pin; and a flexible circuit board bound to the at least one first conductive pin.
  • the flexible circuit board has low power supply voltage signal points.
  • the flexible circuit board is configured to transmit a low power supply voltage signal to the low power supply voltage signal line through the at least one first conductive pin through the low power supply voltage signal point. Wherein, at least one of the first conductive pins is used as the first fixed voltage signal terminal.
  • the first sub-static protection part includes at least one first lead wire, and the first lead wire is also electrically connected with the first conductive pin serving as the first fixed voltage signal terminal.
  • the first lead is configured to transmit the static electricity generated by the mirror surface layer to the low power supply voltage signal point of the flexible circuit board through the first conductive pin.
  • the display panel further includes: a chip on film bound to the at least one conductive pin.
  • the flexible circuit board is bound with the at least one conductive pin through the chip on film.
  • the first lead is configured to transmit the static electricity generated by the mirror layer to the low power supply voltage signal point of the flexible circuit board through the first conductive pin and the chip on film.
  • the display panel further includes: at least one ground wire disposed in the frame area; at least one second conductive pin disposed in the binding area and electrically connected to the ground wire ; a chip on film bound with the at least one second conductive pin; and a flexible circuit board bound with the chip on film, the flexible circuit board having a ground point.
  • at least one of the second conductive pins is used as the first fixed voltage signal terminal.
  • the first sub-static protection part includes at least one second lead, and the second lead is also electrically connected to a second conductive pin serving as the first fixed voltage signal terminal.
  • the second lead is configured to transmit the static electricity generated by the mirror layer to the ground point of the flexible circuit board through the second conductive lead and the chip on film.
  • the first electrostatic sub-protection part when the first electrostatic sub-protection part includes at least one first lead, the first lead and the mirror layer have the same material and are provided in the same layer. In the case where the first sub-static protection part includes at least one second lead, the second lead and the mirror layer have the same material and are provided in the same layer.
  • the display panel further includes: an encapsulation layer disposed between the plurality of sub-pixels and the mirror layer and covering the plurality of sub-pixels.
  • the first sub-static protection part includes at least one first lead
  • the first lead is in contact with the side surface of the encapsulation layer and extends to the binding area along the side surface of the encapsulation layer.
  • the first sub-electrostatic protection part includes at least one second lead
  • the second lead is in contact with the side surface of the encapsulation layer and extends to the binding area along the side surface of the encapsulation layer.
  • the bisector of the display area and the bisector of the binding area are coincident or substantially coincident.
  • the first sub-static protection portion includes at least one first lead
  • the number of the first leads is multiple
  • the multiple first leads are symmetrically distributed with respect to the bisector of the display area.
  • the first sub-static protection portion includes at least one second lead
  • the number of the second leads is multiple
  • the multiple second leads are symmetrically distributed with respect to the bisector of the display area.
  • the display panel has a plurality of second fixed voltage signal terminals disposed in the frame area; the plurality of second fixed voltage signal terminals include a first voltage signal terminal and a second voltage signal terminal, The voltage of the first voltage signal transmitted by the first voltage signal terminal is higher than the voltage of the second voltage signal transmitted by the second voltage signal terminal.
  • the electrostatic protection part includes a second sub electrostatic protection part that is further electrically connected to the first voltage signal terminal and the second voltage signal terminal.
  • the second sub-static protection part includes at least one electrostatic protection circuit.
  • the electrostatic protection circuit includes at least one first transistor electrically connected to the mirror layer and the first voltage signal terminal, and at least one second transistor electrically connected to the mirror layer and the second voltage signal terminal .
  • the at least one first transistor is configured to be turned on when the voltage of the static electricity generated in the mirror layer is higher than the voltage of the first voltage signal, and to transmit the static electricity to the first voltage signal terminal.
  • the at least one second transistor is configured to be turned on when the voltage of the static electricity generated in the mirror layer is lower than the voltage of the second voltage signal, and to transmit the static electricity to the second voltage signal terminal.
  • the subpixels include pixel drive circuitry.
  • the at least one first transistor, the at least one second transistor, and the pixel driving circuit are formed in synchronization.
  • the bezel area surrounds the display area.
  • the number of the electrostatic protection circuits is multiple, and the multiple electrostatic protection circuits are arranged in the frame area at intervals.
  • the display area is rectangular, and the frame area surrounds the display area.
  • the electrostatic protection part includes the first sub electrostatic protection part and the second sub electrostatic protection part
  • the second electrostatic protection part includes a plurality of electrostatic protection circuits
  • the first electrostatic protection sub The part is arranged on one side of the display area, and the plurality of electrostatic protection circuits are evenly arranged on the remaining side of the display area.
  • the display panel further includes: a pixel defining layer disposed between every two adjacent sub-pixels.
  • the orthographic projection of the specular layer on the substrate is within the range of the orthographic projection of the pixel defining layer on the substrate, or the orthographic projection of the specular layer on the substrate is the same as the pixel.
  • the orthographic projections of the defining layers on the substrate coincide.
  • a display device in another aspect, includes: the display panel according to any one of the above embodiments.
  • FIG. 1 is a structural diagram of a display panel according to some embodiments of the present disclosure
  • FIG. 2 is a structural diagram of another display panel according to some embodiments of the present disclosure.
  • FIG. 3 is a structural diagram of yet another display panel according to some embodiments of the present disclosure.
  • FIG. 4 is a cross-sectional view of the display panel shown in FIG. 3 along the M-M' direction;
  • FIG. 5 is a structural diagram of yet another display panel according to some embodiments of the present disclosure.
  • FIG. 6 is a circuit diagram and an equivalent circuit diagram of a second electrostatic sub-section according to some embodiments of the present disclosure.
  • FIG. 7 is a structural diagram of yet another display panel according to some embodiments of the present disclosure.
  • FIG. 8 is a structural diagram of a display device according to some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • connection and its derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the embodiments disclosed herein are not necessarily limited by the content herein.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally construed to mean “when” or “at” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that" or “if a [statement or event] is detected” are optionally interpreted to mean “in determining" or “in response to determining" or “on detection of [recited condition or event]” or “in response to detection of [recited condition or event]”.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the drawings due to, for example, manufacturing techniques and/or tolerances, are contemplated.
  • example embodiments should not be construed as limited to the shapes of the regions shown herein, but to include deviations in shapes due, for example, to manufacturing. For example, an etched area shown as a rectangle will typically have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • the mirror layer in the mirror display device is usually prepared and formed by using a metal material with high light reflectivity.
  • static electricity is easily generated and accumulated in the mirror layer in the mirror display device, which is easy to cause the phenomenon of electrostatic discharge, and then it is easy to damage the devices in the mirror display device.
  • the structure (such as the light-emitting device or the pixel driving circuit, etc.) causes damage, which affects the normal use of the mirror display device.
  • some embodiments of the present disclosure provide a display device 100 .
  • the display device 100 has a display area A and a frame area B located beside the display area A.
  • the display device 100 has a display area A and a frame area B located beside the display area A.
  • the above-mentioned “side” refers to one side, two sides, three sides, or a peripheral side of the display area A (as shown in FIG. 1 ), and the like.
  • the above-mentioned display device 100 includes: a substrate 1 .
  • the substrate 1 includes various structures, which can be selected and set according to actual needs.
  • the substrate 1 may be a blank base substrate.
  • the substrate 1 may include a blank base substrate and at least one functional thin film (eg, an insulating layer and/or a buffer layer) disposed on the blank base substrate.
  • the blank base substrate may be a rigid base substrate.
  • the rigid substrate can be, for example, a glass substrate or a PMMA (Polymethyl methacrylate, polymethyl methacrylate) substrate, or the like.
  • the blank base substrate may be a flexible base substrate.
  • the flexible substrate can be, for example, a PET (Polyethylene terephthalate, polyethylene terephthalate) substrate, a PEN (Polyethylene naphthalate two formic acid glycol ester, polyethylene naphthalate) substrate or PI (Polyimide, polyimide) substrate substrate, etc.
  • the above-mentioned display device 100 further includes: a plurality of gate lines GL and a plurality of data lines DL disposed on one side of the substrate 1 .
  • the plurality of gate lines GL may extend along the first direction X
  • the plurality of data lines DL may extend along the second direction Y
  • the plurality of data lines DL are located at a position of the plurality of gate lines GL away from the substrate 1 side, the two are insulated from each other.
  • the first direction X and the second direction Y intersect each other, which means that the above-mentioned multiple gate lines GL and multiple data lines DL are arranged to intersect with each other, and the multiple gate lines GL and the multiple data lines DL can be used to cross each other.
  • the line GL and the plurality of data lines DL define a plurality of sub-pixel regions P.
  • the size of the included angle between the first direction X and the second direction Y can be selected and set according to actual needs.
  • the first direction X and the second direction Y may be perpendicular to each other, that is, the included angle between them is 90°.
  • the plurality of gate lines GL and the plurality of data lines DL are perpendicular or approximately perpendicular to each other.
  • the above-mentioned display device 100 further includes: a plurality of sub-pixels 2 disposed on one side of the substrate 1 and located in the display area A.
  • the plurality of sub-pixels 2 may be located in the plurality of sub-pixel regions P, respectively, that is, the plurality of sub-pixels 2 and the plurality of sub-pixel regions P are in one-to-one correspondence.
  • each sub-pixel 2 includes a pixel driving circuit 21 and a light emitting device 22 disposed on the side of the pixel driving circuit 21 away from the substrate 1 and electrically connected to the pixel driving circuit 21 .
  • the pixel driving circuit 21 is configured to supply a driving voltage to the light emitting device 22 electrically connected thereto to control the light emitting state of the light emitting device 22 .
  • the sub-pixel regions P arranged in a row along the first direction X may be referred to as sub-pixel regions P in the same row
  • the sub-pixel regions P arranged in a column along the second direction Y may be referred to as sub-pixel regions P in a row.
  • Each pixel driving circuit 121 in the sub-pixel region P in the same row can be electrically connected with one gate line GL
  • each pixel driving circuit 121 in the sub-pixel region P in the same column can be electrically connected with one data line DL.
  • each pixel driving circuit 121 of the sub-pixel region P in the same row may also be electrically connected to a plurality of gate lines GL, which is not limited in the embodiment of the present invention.
  • the structure of the above-mentioned pixel driving circuit 21 includes various structures, which can be selected and set according to actual needs.
  • the structure of the pixel driving circuit 21 may include structures such as "2T1C", “6T1C”, “7T1C”, “6T2C” or “7T2C”.
  • T represents a thin film transistor
  • a number preceding "T” represents the number of thin film transistors
  • C represents a storage capacitor
  • a number preceding "C” represents the number of storage capacitors.
  • one driving transistor and one switching transistor are included.
  • the types of the above-mentioned thin film transistors include various types.
  • the thin film transistors may be low temperature polysilicon thin film transistors or oxide thin film transistors.
  • the structure of the light-emitting device 22 includes various structures, which can be selected and set according to actual needs.
  • the light emitting device 22 includes an anode layer 221 disposed on the side of the pixel driving optical circuit 21 away from the substrate 1 and electrically connected to the driving transistor in the pixel driving circuit 21 , and is sequentially stacked.
  • the light emitting device 22 may further include a hole injection layer and/or a hole transport layer disposed between the anode layer 221 and the light emitting layer 222 .
  • the light emitting device 22 may further include an electron transport layer and/or an electron injection layer disposed between the light emitting layer 222 and the cathode layer 223 .
  • the structure of the light-emitting layer 222 described above includes various structures.
  • the light-emitting layer 222 may be an organic light-emitting layer prepared by using an organic material.
  • the light-emitting device 22 may be called an OLED (Organic Light Emitting Diode, organic light-emitting diode) light-emitting device.
  • the light-emitting layer 222 may be an inorganic light-emitting layer prepared by using quantum dot materials.
  • the light-emitting device 22 may be referred to as a QLED (Quantum Dot Light Emitting Diodes, quantum dot light-emitting diode) light-emitting device.
  • QLED Quantum Dot Light Emitting Diodes, quantum dot light-emitting diode
  • the above-mentioned light-emitting device 22 may be a top-emission type light-emitting device or a bottom-emission type light-emitting device.
  • the present disclosure schematically illustrates the structure of the display panel 100 by taking the light emitting device 22 as an example of a top emission type light emitting device.
  • the above-mentioned display device 100 further includes: a pixel defining layer 3 disposed between every two adjacent sub-pixels 2 .
  • the above-mentioned pixel defining layer 3 may be located on the side of the plurality of pixel driving circuits 21 away from the substrate 1, and located on every adjacent two light-emitting devices. between devices 22.
  • the display device 100 further includes: an encapsulation layer 4 disposed on the side of the plurality of sub-pixels 2 and the pixel defining layer 3 away from the substrate 1 .
  • the encapsulation layer 4 covers the above-mentioned multiple sub-pixels 2 , that is, the orthographic projections of the multiple sub-pixels 2 on the substrate 1 are located within the orthographic projection range of the encapsulation layer 4 on the substrate 1 .
  • the encapsulation layer 4 can be used to encapsulate and protect the plurality of sub-pixels 2 to avoid corrosion of the light-emitting devices 22 in the plurality of sub-pixels 2 caused by water vapor and/or oxygen in the outside world, thereby affecting the luminous efficiency and use of the display panel 100. life.
  • the above-mentioned display device 100 further includes: a mirror layer 5 disposed on the side of the above-mentioned plurality of sub-pixels 2 away from the substrate 1 .
  • the above-mentioned mirror layer 5 may be located in the display area A, or the outer boundary of the orthographic projection of the mirror layer 3 on the substrate 1 may coincide with the boundary of the display area A.
  • a part of the mirror layer 5 may be located in the display area A, and the other part may be located in the frame area B.
  • the mirror layer 5 may be located on the side of the encapsulation layer 4 away from the substrate 1 , and in direct contact with the surface of the encapsulation layer 4 on the side away from the substrate 1 .
  • the above-mentioned mirror layer 5 is configured to reflect external ambient light incident on the mirror layer 5 .
  • the display device 100 can be made to have a mirror function by using the mirror layer 5 while realizing the display function by using the above-mentioned plurality of sub-pixels 2 .
  • the above-mentioned materials of the mirror surface layer 5 include various materials, which can be selected and set according to actual needs, so that the mirror surface layer 5 can have a higher light reflectivity and achieve a better reflection effect.
  • the material of the mirror layer 5 may include at least one of aluminum, silver, titanium and molybdenum.
  • the positional relationship between the mirror surface layer 5 and the pixel defining layer 3 includes various types, which can be selected and set according to actual needs.
  • the orthographic projection of the mirror layer 5 on the substrate 1 is located within the range of the orthographic projection of the pixel defining layer 3 on the substrate 1, or, the orthographic projection of the mirror layer 5 on the substrate 1 Coinciding with the orthographic projection of the pixel defining layer 3 on the substrate 1 .
  • the light-emitting device 22 in the sub-pixel 2 can be prevented from being blocked by the mirror layer 5 , and the light emitted by the light-emitting device 22 can be prevented from being blocked by the mirror layer 5 , thereby ensuring that the light emitted by the light-emitting device 22 can pass from the light-emitting side of the display panel 100 . It can be ejected normally, so as to avoid affecting the display effect of the display panel 100 .
  • the above-mentioned display device 100 further includes: an electrostatic protection portion 6 that is electrically connected to the mirror layer 5 and located in the frame region B.
  • the static electricity protection part 6 is configured to perform static electricity protection on the mirror surface layer 5 .
  • the mirror layer 5 is made of a metal material with high light reflectivity, static electricity is easily generated and accumulated in the mirror layer 5 .
  • the electrostatic protection part 6 electrically connected to the mirror surface layer 5, the static electricity can be discharged by the electrostatic protection part 6, and then the electrostatic protection of the mirror surface layer 5 can be performed to avoid the phenomenon of electrostatic discharge.
  • the electrostatic protection part 6 by arranging the electrostatic protection part 6 electrically connected to the mirror layer 5 in the binding area B, the electrostatic protection part 6 can prevent the electrostatic protection part 6 from occupying the area of the display area A at the same time. , and the electrostatic protection part 6 is used to protect the mirror surface layer 5 from static electricity. In this way, the accumulation of static electricity generated in the mirror layer 5 can be avoided, and the phenomenon of electrostatic discharge can be avoided, and damage to the device structure in the display device 100 due to electrostatic discharge can be avoided, so as to ensure the normal use of the display device 100.
  • the above-mentioned structure of the electrostatic protection part 6 includes various structures, which can be selected and set according to actual needs.
  • the above-mentioned electrostatic protection part 6 includes a first sub electrostatic protection part 61 and/or a second sub electrostatic protection part 62 . That is, the electrostatic protection part 6 may include the first sub electrostatic protection part 61 , or the electrostatic protection part 6 may include the second electrostatic protection sub 62 , or the electrostatic protection part 6 may include both the first sub electrostatic protection part 61 and the second electrostatic protection part 62 . Sub-static protection part 62 .
  • first sub-static protection portion 61 and the second sub-static protection portion 62 will be schematically described below with reference to the accompanying drawings.
  • the border area B includes a binding area B1.
  • the display panel 100 has at least one first fixed voltage signal terminal G1 disposed in the binding region B1. That is, the number of the first fixed voltage signal terminals G1 may be one or more.
  • the electrostatic protection part 6 may include a first sub electrostatic protection part 61 .
  • the first sub-static protection portion 61 is also electrically connected to the first fixed voltage signal terminal G1, and the first sub-static protection portion 61 is configured to transmit static electricity generated in the mirror layer 5 to the first fixed voltage signal terminal G1.
  • the display panel 100 further includes: a plurality of pins 7 arranged in the binding area B1, and a flexible printed circuit board (Flexible Printed Circuit, referred to as abbreviated as the plurality of pins 7) bound to the plurality of pins 7 FPC) 8.
  • the FPC 8 may transmit electrical signals to the plurality of pins 7 , or the electrical signals transmitted to the plurality of pins 7 may be transmitted to the FPC 8 .
  • the display panel 100 further includes: a chip on film (Chip On Film, or, Chip On Flex, COF for short) 9 bound to the above-mentioned plurality of pins 7 .
  • the FPC 8 can be bound to the plurality of pins 7 through the COF 9, and then the FPC 8 can transmit electrical signals to the plurality of pins 7 through the COF 9, or the electrical signals transmitted to the plurality of pins 7 can pass the COF 9. Transfer to FPC 8.
  • the types of the first fixed voltage signal terminal G1 include multiple types, and the display panel 100 may have different structures.
  • the display panel 100 further includes: at least one low power supply voltage signal line 10 disposed in the frame area B.
  • the low power supply voltage signal line 10 may surround the display area A, or may be disposed on one side of the display area A, for example.
  • the above-mentioned plurality of pins 7 may include at least one first conductive pin 71 .
  • the at least one low power supply voltage signal line 10 can be electrically connected to the at least one first conductive pin 71 .
  • the at least one low power supply voltage signal line 10 may be electrically connected to the at least one first conductive pin 71 in a one-to-one correspondence, or one first conductive pin 71 may be electrically connected to a plurality of low power supply voltage signal lines 10 .
  • the FPC 8 has a low supply voltage signal point.
  • the FPC 8 is configured to directly transmit the low power supply voltage signal (VSS) to the low power supply voltage signal line 10 through the above-mentioned at least one first conductive pin 71 through the low power supply voltage signal point, or, through the COF 9 and the above-mentioned at least one A first conductive pin 71 is transmitted to the low power supply voltage signal line 10 .
  • VSS low power supply voltage signal
  • At least one conductive pin 71 of the at least one first conductive pin 71 can be used as the first fixed voltage signal terminal G1. That is, if the number of the first conductive pins 71 is one, the first conductive pin 71 is used as the first fixed voltage signal terminal G1; if the number of the first conductive pins 71 is multiple, the plurality of first conductive pins 71 At least one of the first conductive pins 71 of the conductive pins 71 is used as the first fixed voltage signal terminal G1.
  • the first sub-electrostatic protection part 61 may include at least one first lead 611 , and the at least one first lead 611 is also electrically connected to the first conductive pin 71 serving as the first fixed voltage signal terminal G1 .
  • connection relationship between the first lead 611 and the first conductive pin 71 may be, for example: the first lead 611 and the first conductive pin 71 are electrically connected in a one-to-one correspondence, or, one first conductive pin 71 may be It is electrically connected to a plurality of first leads 611 .
  • the first lead 611 is configured to transmit the static electricity generated by the mirror layer 5 to the low power supply voltage signal point of the FPC 8 through the first conductive pin 71, or to transmit the static electricity through the COF 9 and the first conductive pin 71 in turn. Low supply voltage signal point to FPC 8.
  • the static electricity generated in the mirror surface layer 5 can be discharged by using the first lead 611 , so as to avoid the accumulation of static electricity generated in the mirror surface layer 5 , thereby avoiding the phenomenon of electrostatic discharge.
  • the arrangement of the first lead 611 may be as follows: the first lead 611 and the mirror layer 5 have the same material and are arranged in the same layer.
  • the "same layer” mentioned herein refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through one patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights Or have different thicknesses.
  • the first leads 611 and the mirror layer 5 can be prepared and formed simultaneously in one patterning process, which is beneficial to simplify the manufacturing process of the display panel 100 .
  • the first lead 611 and the mirror layer 5 may have an integral structure. That is, after the first lead 611 and the mirror layer 5 are prepared and formed, the patterns corresponding to the two are continuous and not disconnected.
  • a metal film can be formed on the surface of the encapsulation layer 4 away from the substrate 1 by a sputtering process, and then the metal film can be patterned by a photolithography process to form a mirror layer. 5 and the first lead 611.
  • the shape of the metal film matches the shape of the surface of the encapsulation layer 4 on the side away from the substrate 1 .
  • the first lead 611 and the encapsulation layer 4 can be The sides of the encapsulation layer 4 are in contact with each other and extend to the binding area B1 along the side of the encapsulation layer 4 .
  • the side surface of the encapsulation layer 4 refers to the side surface of the encapsulation layer 4 away from the substrate 1, which is located in the frame area B, has a slope compared with the substrate 1 and has an included angle with the substrate 1. part of the surface.
  • the first lead 611 and the mirror layer 5 have the same material and are arranged in the same layer, and the first lead 611 extends along the side surface of the encapsulation layer 4 to the bonding area B1 and is electrically connected to the first conductive pin 71, so that the In the process of preparing the plurality of sub-pixels 2 forming the display panel 100, it is possible to avoid redesigning the mask used.
  • the reticle of the 3rd grade is revised, thereby avoiding a significant increase in the production cost of the display device 100 and improving the versatility of the display device 100 .
  • the display panel 100 further includes: at least one ground wire 11 disposed in the frame area B. As shown in FIG. The ground wire 11 may surround the display area A, for example, or may be arranged on one side of the display area A.
  • the above-mentioned plurality of pins 7 may include at least one second conductive pin 72 .
  • the at least one ground wire 11 may be electrically connected to the at least one second conductive pin 72 .
  • the at least one ground wire 11 may be electrically connected to the at least one second conductive pin 72 in a one-to-one correspondence, or one second conductive pin 72 may be electrically connected to a plurality of ground wires 11 .
  • the FPC 8 has a ground point.
  • the at least one ground wire 11 can be sequentially connected to the ground wire point of the FPC 8 through the at least one second conductive pin 72 and the COF 9 to ground the ground wire 11, so that the display panel 100 can be grounded.
  • At least two conductive pins 72 of the at least one second conductive pin 72 can be used as the first fixed voltage signal terminal G1. That is, if the number of the second conductive pins 72 is one, the second conductive pins 72 serve as the first fixed voltage signal terminal G1; if the number of the second conductive pins 72 is multiple, the plurality of first At least one of the two conductive pins 72 is used as the first fixed voltage signal terminal G1.
  • the first sub-electrostatic protection part 61 may include at least one second lead 612, and the at least one second lead 612 is also electrically connected to the second conductive pin 72 serving as the first fixed voltage signal terminal G1.
  • connection relationship between the second lead 612 and the second conductive pin 72 may be, for example, the second lead 612 and the second conductive pin 72 are electrically connected in a one-to-one correspondence, or, one second conductive pin 72 may be It is electrically connected with the plurality of second leads 612 .
  • the second lead 612 is configured to transmit the static electricity generated by the mirror layer 5 to the ground point of the FPC 8 through the second conductive pin 72 and the COF 9 in sequence.
  • the static electricity generated in the mirror surface layer 5 can be discharged by using the first lead 611 , so as to avoid the accumulation of static electricity generated in the mirror surface layer 5 , thereby avoiding the phenomenon of electrostatic discharge.
  • the arrangement of the second lead 612 can be, for example, as follows: the second lead 612 and the mirror layer 5 have the same material and are arranged in the same layer.
  • the second leads 612 and the mirror layer 5 can be prepared and formed at the same time in one patterning process, which is beneficial to simplify the preparation process of the display panel 100 .
  • the second lead 612 and the mirror layer 5 may be in an integral structure. That is, after the first lead 611 and the mirror layer 5 are prepared and formed, the patterns corresponding to the two are continuous and not disconnected.
  • a metal film can be formed on the surface of the encapsulation layer 4 away from the substrate 1 by a sputtering process, and then the metal film can be patterned by a photolithography process to form a mirror layer. 5 and the second lead 612.
  • the shape of the metal film matches the shape of the surface of the encapsulation layer 4 away from the substrate 1 .
  • the second lead 612 and the encapsulation layer 4 can be The sides of the encapsulation layer 4 are in contact with each other and extend to the binding area B1 along the side of the encapsulation layer 4 .
  • the second lead 612 and the mirror layer 5 have the same material and are provided in the same layer, and the second lead 612 extends along the side surface of the encapsulation layer 4 to the bonding area B1 and is electrically connected to the second conductive pin 72, so that the In the process of preparing the plurality of sub-pixels 2 forming the display panel 100, it is possible to avoid redesigning the mask used.
  • the reticle of the 3rd grade is revised, thereby avoiding a significant increase in the production cost of the display device 100 and improving the versatility of the display device 100 .
  • the relative positional relationship between the display area A and the binding area B1 in the border area B includes various types, which can be selected and set according to actual needs.
  • the number of the above-mentioned binding areas B1 may be one or more.
  • the binding area B1 may be located on one side of the display area A, or, in the case where there are multiple binding areas B1, the multiple binding areas B1 may be located on different sides of the display area A, respectively.
  • the shape of the display area A may be arranged symmetrically with respect to its bisector O1
  • the shape of the binding area B1 may be arranged symmetrically with respect to its bisector O2 .
  • the setting manner of the first sub-static protection portion 61 may be, for example:
  • the number of the first lead 611 is multiple, and the plurality of first leads 611 are relative to the display area A.
  • the bisector O 1 is symmetrically distributed.
  • the number of the second lead 612 is multiple, and the plurality of second leads 612 are bisected with respect to the display area A Line O1 is symmetrically distributed.
  • the display panel 100 has a plurality of second fixed voltage signal terminals G2 disposed in the frame area B.
  • the plurality of second fixed voltage signal terminals G2 may include a first voltage signal terminal G21 and a second voltage signal terminal G22.
  • the voltage of the first voltage signal (represented by VGH, for example) transmitted by the first voltage signal terminal G21 is higher than the voltage of the second voltage signal (represented by VGL, for example) transmitted by the second voltage signal terminal G22.
  • the electrostatic protection part 6 may include a second sub electrostatic protection part 62 .
  • the second electrostatic sub-protection portion 62 is also electrically connected to the first voltage signal terminal G21 and the second voltage signal terminal G22.
  • the static electricity generated in the mirror layer 5 may be positive static electricity or negative static electricity.
  • the second sub-static protection part 62 may be configured such that the voltage of the static electricity generated in the mirror layer 5 is higher than the voltage of the first voltage signal VGH (that is, the static electricity generated in the mirror layer 5 is positive static electricity) In the case of , the static electricity is transmitted to the first voltage signal terminal G21.
  • the second sub-static protection unit 62 may also be configured to, when the voltage of the static electricity generated in the mirror layer 5 is lower than the voltage of the second voltage signal VGL (that is, the static electricity generated in the mirror layer 5 is negative static electricity), The static electricity is transmitted to the second voltage signal terminal G22.
  • the static electricity generated in the mirror surface layer 5 can be discharged by the second electrostatic sub-protection portion 62 , so as to avoid the accumulation of static electricity in the mirror surface layer 5 , thereby avoiding the occurrence of electrostatic discharge inside the display panel 100 .
  • the second electrostatic protection part 62 includes at least one electrostatic protection circuit 621 .
  • the electrostatic protection circuit 621 may include a first transistor 6211 and a second transistor 6212 .
  • the first transistor 6211 is electrically connected to the mirror layer 5 and the first voltage signal terminal G21.
  • the first transistor 6211 is configured to be turned on when the voltage of the static electricity generated in the mirror layer 5 is higher than the voltage of the first voltage signal VGH, and to transmit the static electricity to the first voltage signal terminal G21 . That is, when the static electricity generated in the mirror layer 5 is positive static electricity and the voltage of the positive static electricity is higher than the voltage of the first voltage signal VGH, the first transistor 6211 can be between the positive static electricity and the first voltage signal VGH Conduction is conducted under the formed pressure difference, and the positive static electricity is discharged.
  • the second transistor 6212 is electrically connected to the mirror layer 5 and the second voltage signal terminal G22.
  • the second transistor 6212 is configured to be turned on when the voltage of the static electricity generated in the mirror layer 5 is lower than the voltage of the second voltage signal VGL, and to transmit the static electricity to the second voltage signal terminal G22. That is, when the static electricity generated in the mirror layer 5 is negative static electricity and the voltage of the negative static electricity is lower than the voltage of the second voltage signal VGL, the second transistor 6212 can be between the first voltage signal VGH and the negative static electricity Conduction is conducted under the formed pressure difference, and the negative static electricity is discharged.
  • the above-mentioned first transistor 6211 and second transistor 6212 may be thin film transistors, and their types may be the same as those of the thin film transistors in the pixel driving circuit 21 .
  • the first electrostatic discharge sub-circuit 6211, the second electrostatic discharge sub-circuit 6212 and the pixel driving circuit 21 can be formed simultaneously.
  • the numbers of the first transistors 6211 and the second crystals 6212 can be selected and set according to actual needs.
  • the number of the first transistor 6211 may be one or more.
  • the number of the second crystals 6212 may be one or more. When the number of the first transistors 6211 is multiple, the multiple first transistors 6211 are serially connected in sequence, and when the number of the second transistors 6212 is multiple, the multiple second crystals 6212 are serially connected sequentially.
  • the number of the first transistors 6211 is one, and the number of the second transistors 6212 is one, and the connection relationship and the working process of the electrostatic protection circuit 621 are schematically described.
  • the thin film transistor includes an N-type transistor or a P-type transistor, and the conduction directions of the N-type transistor and the P-type transistor are opposite.
  • the types of the first transistor 6211 and the second transistor 6212 may be the same or different. Some embodiments of the present disclosure exemplify that both are of the same type.
  • the first electrode 62111 and the control electrode 62112 of the first transistor 6211 are electrically connected to the first voltage signal terminal G21
  • the second electrode 62113 of the first transistor 6211 is electrically connected to the mirror layer 5
  • the first electrode 62121 of the second transistor 6212 is electrically connected to the control electrode 62122, and is electrically connected to the mirror layer 5, and the second electrode 62123 of the second transistor 6212 is electrically connected to the second voltage signal terminal G22.
  • control electrode 62112 of the first transistor 6211 is the gate of the first transistor 6211
  • control electrode 62122 of the second transistor 6212 is the gate of the second transistor 6212 .
  • the first electrode 62111 of the first transistor 6211 is the drain of the first transistor 6211
  • the second electrode 62113 of the first transistor 6211 is the first electrode 62111.
  • the source of a transistor 6211; the first electrode 62121 of the second transistor 6212 is the drain of the second transistor 6212, and the second electrode 62123 of the second transistor 6212 is the source of the second transistor 6212.
  • the first electrode 62111 of the first transistor 6211 is the source electrode of the first transistor 6211
  • the second electrode 62113 of the first transistor 6211 is the first electrode 62111.
  • the first transistor 6211 and the second transistor 6212 are both P-type transistors as an example.
  • the first transistor 6211 can be equivalent to a first diode, and the first electrode 62111 and the control electrode 62112 of the first transistor 6211 are collectively equivalent to a first diode.
  • the cathode of a diode, the second pole 62113 of the first transistor 6211 is equivalent to the anode of the first diode.
  • the second transistor 6212 can be equivalent to a second diode, and the first electrode 62121 and the control electrode 62122 of the second transistor 6212 can be collectively equivalent to The cathode of the second diode and the second pole 62123 of the second transistor 6212 are equivalent to the anode of the second diode.
  • the first transistor 6211 is turned on, and the static electricity (that is, positive static electricity) is discharged from the mirror surface.
  • the layer 5 is sequentially transferred to the first voltage signal terminal G21 through the source of the first transistor 6211 and the drain of the first transistor 6211 to discharge the static electricity and reduce the potential of the mirror layer 5 .
  • the second transistor 6212 When the voltage of the static electricity generated in the mirror layer 5 is lower than the voltage of the second voltage signal VGL, the second transistor 6212 is turned on, and the static electricity (that is, the negative static electricity) passes from the mirror layer 5 to the second transistor 6212 in sequence.
  • the drain and the source of the second transistor 6212 are transmitted to the second voltage signal terminal G22 to discharge the static electricity, that is, the second voltage signal VGL transmitted by the second voltage signal terminal G22 passes through the second transistor 6212 in turn.
  • the source and the drain of the second transistor 6212 are transmitted to the mirror layer 5 to raise the potential of the mirror layer 5 .
  • the number of the electrostatic protection circuit 621 may be one or multiple.
  • the multiple electrostatic protection circuits 621 may be disposed in the frame area B at intervals. This is beneficial to improve the electrostatic protection effect of the second sub-static protection portion 62 on the mirror surface layer 5 .
  • the above-mentioned frame area B surrounds the display area A.
  • the plurality of electrostatic protection circuits 621 may be disposed in the frame area B at a distance from each other. That is, the plurality of electrostatic protection circuits 621 may be arranged around the mirror layer 5 at intervals.
  • the static electricity can also be discharged through other electrostatic protection circuits 621, so that the second electrostatic protection sub-section 62 can have better reliability.
  • the display area A may be rectangular.
  • the number of electrostatic protection circuits 621 may be, for example, four, and the four electrostatic protection circuits 621 may be distributed at positions corresponding to the four corners of the display area A.
  • the number of electrostatic protection circuits 621 may be, for example, seven, of which four electrostatic protection circuits 621 may be distributed at positions corresponding to the four corners of the display area A, and the other three electrostatic protection circuits 621 may be They are distributed at positions corresponding to each of the four corners of the display area A between two adjacent corners. This is beneficial to improve the balance of electrostatic discharge and improve the effect of electrostatic protection.
  • the electrostatic protection part 6 when the electrostatic protection part 6 includes both the first electrostatic protection sub 61 and the second electrostatic protection sub 62 , the positions of the first electrostatic protection sub 61 and the electrostatic protection sub 62 You can choose settings according to actual needs.
  • the display area A may be rectangular, and the frame area B surrounds the display area A.
  • the binding area B1 in the border area B may be located on one side of the display area A.
  • the first sub-static protection portion 61 may be disposed on one side of the display area A. As shown in FIG. In the case where the second electrostatic protection part 62 includes a plurality of electrostatic protection circuits 621 , the multiple electrostatic protection circuits 621 may be uniformly disposed on the remaining sides of the display area A. As shown in FIG.
  • the remaining sides of the display area A refer to the other three sides in the display area A except the side opposite to the binding area B1.
  • the uniform arrangement refers to that the plurality of electrostatic protection circuits 621 located on the same side of the display area A are arranged at equal intervals.
  • the display device 1000 includes the display panel 100 described in any of the above embodiments.
  • the display device 1000 may further include a housing for carrying the above-mentioned display panel 100 , and the like.
  • the beneficial effects that can be achieved by the display device 1000 provided by some embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the display panel 100 provided in some of the above-mentioned embodiments, which will not be repeated here.
  • the above-mentioned display device 1000 may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板，具有显示区和位于所述显示区旁侧的边框区。所述显示面板包括：衬底；设置在所述衬底的一侧、且位于所述显示区的多个子像素；设置在所述多个子像素远离所述衬底一侧的镜面层；以及，与所述镜面层电连接、且位于所述边框区的静电防护部。其中，所述静电防护部被配置为，对所述镜面层进行静电防护。

Description

显示面板及显示装置
本申请要求于2020年09月30日提交的、申请号为202011062894.9的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
随着科学技术的发展，用户对显示装置的功能类型的需求越来越多。目前，出现了镜面显示装置，该镜面显示装置能够同时实现显示功能和镜子功能，也即在用户从镜面显示装置中看到显示画面的同时，还能够将该镜面显示装置作为镜子使用。
发明内容
一方面，提供一种显示面板。所述显示面板具有显示区和位于所述显示区旁侧的边框区。所述显示面板包括：衬底；设置在所述衬底的一侧、且位于所述显示区的多个子像素；设置在所述多个子像素远离所述衬底一侧的镜面层；以及，与所述镜面层电连接、且位于所述边框区的静电防护部。其中，所述静电防护部被配置为，对所述镜面层进行静电防护。
在一些实施例中，所述边框区包括绑定区。所述显示面板具有设置在所述绑定区的至少一个第一固定电压信号端，其中，所述静电防护部包括还与所述第一固定电压信号端电连接的第一子静电防护部。所述第一子静电防护部被配置为，将所述镜面层中产生的静电传输至所述第一固定电压信号端。
在一些实施例中，所述显示面板，还包括：设置在所述边框区的至少一条低电源电压信号线；设置在所述绑定区、且与所述低电源电压信号线电连接的至少一个第一导电引脚；以及，与所述至少一个第一导电引脚绑定的柔性电路板。所述柔性线路板具有低电源电压信号点位。所述柔性电路板被配置为，通过所述低电源电压信号点位将低电源电压信号经所述至少一个第一导电引脚传输至所述低电源电压信号线。其中，至少一个所述第一导电引脚作为所述第一固定电压信号端。所述第一子静电防护部包括至少一条第一引线，所述第一引线还与作为所述第一固定电压信号端的第一导电引脚电连接。所述第一引线被配置为，将所述镜面层产生的静电经所述第一导电引脚传输至所述柔性电路板的低电源电压信号点位。
在一些实施例中，所述显示面板，还包括：与所述至少一个导电引脚绑定的覆晶薄膜。所述柔性电路板通过所述覆晶薄膜与所述至少一个导电引脚 绑定。所述第一引线被配置为，将所述镜面层产生的静电经所述第一导电引脚及所述覆晶薄膜传输至所述柔性电路板的低电源电压信号点位。
在一些实施例中，所述显示面板，还包括：设置在所述边框区的至少一条地线；设置在所述绑定区、且与所述地线电连接的至少一个第二导电引脚；与所述至少一个第二导电引脚绑定的覆晶薄膜；以及，与所述覆晶薄膜绑定的柔性电路板，所述柔性电路板具有地线点位。其中，至少一个所述第二导电引脚作为所述第一固定电压信号端。所述第一子静电防护部包括至少一条第二引线，所述第二引线还与作为所述第一固定电压信号端的第二导电引脚电连接。所述第二引线被配置为，将所述镜面层产生的静电经所述第二导电引脚及所述覆晶薄膜传输至所述柔性电路板的地线点位。
在一些实施例中，在所述第一子静电防护部包括至少一条第一引线的情况下，所述第一引线与所述镜面层材料相同且同层设置。在所述第一子静电防护部包括至少一条第二引线的情况下，所述第二引线与所述镜面层材料相同且同层设置。
在一些实施例中，所述显示面板，还包括：设置在所述多个子像素和所述镜面层之间、且覆盖所述多个子像素的封装层。在所述第一子静电防护部包括至少一条第一引线的情况下，所述第一引线与所述封装层的侧面接触，并沿所述封装层的侧面延伸至所述绑定区。在所述第一子静电防护部包括至少一条第二引线的情况下，所述第二引线与所述封装层的侧面接触，并沿所述封装层的侧面延伸至所述绑定区。
在一些实施例中，沿所述绑定区和所述显示区的排列方向，所述显示区的平分线和所述绑定区的平分线重合或大致重合。在所述第一子静电防护部包括至少一条第一引线的情况下，所述第一引线的数量为多条，多条第一引线相对于所述显示区的平分线对称分布。在所述第一子静电防护部包括至少一条第二引线的情况下，所述第二引线的数量为多条，多条第二引线相对于所述显示区的平分线对称分布。
在一些实施例中，所述显示面板具有设置在所述边框区的多个第二固定电压信号端；所述多个第二固定电压信号端包括第一电压信号端和第二电压信号端，所述第一电压信号端所传输的第一电压信号的电压高于所述第二电压信号端所传输的第二电压信号的电压。其中，所述静电防护部包括还与所述第一电压信号端和所述第二电压信号端电连接的第二子静电防护部。所述第二子静电防护部包括至少一个静电防护电路。所述静电防护电路包括与所述镜面层和所述第一电压信号端电连接的至少一个第一晶体管，以及与所述 镜面层和所述第二电压信号端电连接的至少一个第二晶体管。所述至少一个第一晶体管被配置为，在所述镜面层中产生的静电的电压高于所述第一电压信号的电压的情况下导通，将静电传输至所述第一电压信号端。所述至少一个第二晶体管被配置为，在所述镜面层中产生的静电的电压低于所述第二电压信号的电压的情况下导通，将静电传输至所述第二电压信号端。
在一些实施例中，子像素包括像素驱动电路。所述至少一个第一晶体管、所述至少一个第二晶体管和所述像素驱动电路同步形成。
在一些实施例中，所述边框区围绕所述显示区。所述静电防护电路的数量为多个，该多个静电防护电路相互间隔地设置在所述边框区内。
在一些实施例中，所述显示区呈矩形，所述边框区围绕所述显示区。在所述静电防护部包括所述第一子静电防护部和所述第二子静电防护部、且所述第二静电防护部包括多个静电防护电路的情况下，所述第一子静电防护部设置在所述显示区的一侧，所述多个静电防护电路均匀地设置在所述显示区的其余侧。
在一些实施例中，所述显示面板，还包括：设置在每相邻的两个子像素之间的像素界定层。所述镜面层在所述衬底上的正投影位于所述像素界定层在所述衬底上的正投影范围内，或，所述镜面层在所述衬底上的正投影与所述像素界定层在所述衬底上的正投影重合。
另一方面，提供一种显示装置。所述显示装置包括：如上述任一实施例所述的显示面板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸等的限制。
图1为根据本公开的一些实施例中的一种显示面板的结构图；
图2为根据本公开的一些实施例中的另一种显示面板的结构图；
图3为根据本公开的一些实施例中的又一种显示面板的结构图；
图4为图3所示显示面板的沿M-M＇向的一种剖视图；
图5为根据本公开的一些实施例中的又一种显示面板的结构图；
图6为根据本公开的一些实施例中的一种第二子静电防护部的电路图及等效电路图；
图7为根据本公开的一些实施例中的又一种显示面板的结构图；
图8为根据本公开的一些实施例中的一种显示装置的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个 所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在相关技术中，镜面显示装置中的镜面层通常采用具有较高光线反射率的金属材料制备形成。在对上述镜面显示装置进行生产、组装、测试或搬运的过程中，镜面显示装置中的镜面层内容易产生并积累静电，这样容易导致静电放电的现象发生，进而容易对镜面显示装置中的器件结构(例如发光器件或像素驱动电路等)造成损伤，影响影响镜面显示装置的正常使用。
基于此，本公开的一些实施例提供了一种显示装置100。如图1～图5及图7所示，该显示装置100具有显示区A和位于该显示区A旁侧的边框区B。
在一些示例中，上述“旁侧”指的是，显示区A的一侧、两侧、三侧或者周侧(如图1所示)等。这也就意味着，边框区B可以位于显示区A的一侧、两侧或三侧，或者，边框区B可以围绕显示区A。
在一些示例中，如图1～图5及图7所示，上述显示装置100包括：衬底1。
上述衬底1的结构包括多种，具体可以根据实际需要选择设置。例如，衬底1可以为空白的衬底基板。又如，衬底1可以包括空白的衬底基板以及设置在该空白的衬底基板上的至少一层功能薄膜(例如绝缘层和/或缓冲层)。
上述空白的衬底基板的类型包括多种，具体可以根据实际需要选择设置。
例如，空白的衬底基板可以为刚性衬底基板。该刚性衬底基板例如可以为玻璃衬底基板或PMMA(Polymethyl methacrylate，聚甲基丙烯酸甲酯)衬底基板等。
又如，空白的衬底基板可以为柔性衬底基板。该柔性衬底基板例如可以 为PET(Polyethylene terephthalate，聚对苯二甲酸乙二醇酯)衬底基板、PEN(Polyethylene naphthalate two formic acid glycol ester，聚萘二甲酸乙二醇酯)衬底基板或PI(Polyimide，聚酰亚胺)衬底基板等。
在一些示例中，如图1所示，上述显示装置100还包括：设置在衬底1一侧的多条栅线GL和多条数据线DL。其中，该多条栅线GL可以沿第一方向X延伸，该多条数据线DL可以沿第二方向Y延伸，且该多条数据线DL位于该多条栅线GL远离衬底1的一侧，两者相互绝缘。
示例性的，如图1所示，第一方向X和第二方向Y相互交叉，这也就意味着，上述多条栅线GL和多条数据线DL相互交叉设置，可以利用该多条栅线GL和多条数据线DL限定出多个子像素区域P。
此处，第一方向X和第二方向Y之间的夹角的大小可以根据实际需要选择设置。例如，第一方向X和第二方向Y可以相互垂直，也即两者之间的夹角为90°。此时，多条栅线GL和多条数据线DL相互垂直或大约致相互垂直。
在一些示例中，如图1所示，上述显示装置100还包括：设置在衬底1的一侧、且位于显示区A的多个子像素2。
示例性的，如图1所示，上述多个子像素2可以分别位于上述多个子像素区域P内，也即，该多个子像素2和多个子像素区域P一一对应。
上述子像素2的结构例如可以为：每个子像素2包括像素驱动电路21，以及设置在该像素驱动电路21远离衬底1的一侧、且与该像素驱动电路21电连接的发光器件22。像素驱动电路21被配置为，提供驱动电压至与其电连接的发光器件22，以控制该发光器件22的发光状态。
示例性的，如图1所示，可以把沿第一方向X排列成一行的子像素区域P称为同一行子像素区域P，可以把沿第二方向Y排列成一列的子像素区域P称为同一列子像素区域P。同一行子像素区域P的各像素驱动电路121可以与一条栅线GL电连接，同一列子像素区域P内的各像素驱动电路121可以与一条数据线DL电连接。
当然，同一行子像素区域P的各像素驱动电路121还可以与多条栅线GL电连接，本发明实施例对此不做限定。
上述像素驱动电路21的结构包括多种，可以根据实际需要选择设置。例如，像素驱动电路21的结构可以包括“2T1C”、“6T1C”、“7T1C”、“6T2C”或“7T2C”等结构。此处，“T”表示为薄膜晶体管，位于“T”前面的数字表示为薄膜晶体管的数量，“C”表示为存储电容器，位于“C”前面的数字 表示为存储电容器的数量。其中，像素驱动电路21所包括的多个薄膜晶体管中，包括一个驱动晶体管和一个开关晶体管。
上述薄膜晶体管的类型包括多种，示例性的，薄膜晶体管可以为低温多晶硅薄膜晶体管或氧化物薄膜晶体管等。
上述发光器件22的结构包括多种，可以根据实际需要选择设置。
示例性的，如图4所示，发光器件22包括设置在像素驱动光电路21远离衬底1的一侧、且与像素驱动电路21中的驱动晶体管电连接的阳极层221，以及依次层叠设置在阳极层221远离衬底1一侧的发光层222和阴极层223。
示例性的，发光器件22还可以包括设置在阳极层221和发光层222之间的空穴注入层和/或空穴传输层。发光器件22还可以包括设置在发光层222和阴极层223之间的电子传输层和/或电子注入层。
上述发光层222的结构包括多种。例如，发光层222可以为采用有机材料制备形成的有机发光层，此时，发光器件22可以称为OLED(Organic Light Emitting Diode，有机发光二极管)发光器件。又如，发光层222可以为采用量子点材料制备形成的无机发光层，此时，发光器件22可以称为QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)发光器件。
上述发光器件22可以为顶发射型发光器件，也可以为底发射型发光器件。本公开以发光器件22为顶发射型发光器件为例，对显示面板100的结构进行示意性说明。
在一些示例中，如图4所示，上述显示装置100还包括：设置在每相邻的两个子像素2之间的像素界定层3。
此处，在子像素2包括像素驱动电路21和发光器件22的情况下，上述像素界定层3可以位于多个像素驱动电路21远离衬底1的一侧，且位于每相邻的两个发光器件22之间。
在一些示例中，如图4所示，上述显示装置100还包括：设置在上述多个子像素2和像素界定层3远离衬底1一侧的封装层4。
示例性的，封装层4覆盖上述多个子像素2，也即，该多个子像素2在衬底1上的正投影位于该封装层4在衬底1的上的正投影范围内。这样可以利用封装层4对该多个子像素2进行封装、保护，避免外界中的水蒸气和/或氧气对该多个子像素2中的发光器件22造成腐蚀，影响显示面板100的发光效率及使用寿命。
在一些示例中，如图4所示，上述显示装置100还包括：设置在上述多个子像素2远离衬底1一侧的镜面层5。
上述镜面层5可以位于显示区A内，或者，镜面层3在衬底1上的正投影外边界，可以与显示区A的边界重合。
当然，镜面层5的一部分可以位于显示区A内，另一部分位于边框区B内。
示例性的，如图4所示，镜面层5可以位于封装层4远离衬底1的一侧，且与封装层4远离衬底1的一侧表面直接接触。
上述镜面层5被配置为，对入射至镜面层5的外界环境光进行反射。这样可以在利用上述多个子像素2实现显示功能的同时，可以利用镜面层5使得显示装置100具有镜子功能。
上述镜面层5的材料包括多种，可以根据实际需要选择设置，能够使得镜面层5具有较高的光线反射率，实现较好的反射效果即可。
示例性的，镜面层5的材料可以包括铝、银、钛和钼中的至少一种。
镜面层5与像素界定层3之间的位置关系包括多种，可以根据实际需要选择设置。
示例性的，如图4所示，镜面层5在衬底1上的正投影位于像素界定层3在衬底1上的正投影范围内，或，镜面层5在衬底1上的正投影与像素界定层3在衬底1上的正投影重合。
这样可以避免镜面层5对子像素2中的发光器件22形成遮挡，进而避免镜面层5对发光器件22中发出的光线形成遮挡，确保发光器件22中发出的光线能够从显示面板100的出光侧正常射出，进而可以避免影响显示面板100的显示效果。
在一些示例中，如图2～图5及图7所示，上述显示装置100还包括：与镜面层5电连接、且位于边框区B的静电防护部6。其中，静电防护部6被配置为，对镜面层5进行静电防护。
通过将静电防护部6设置在边框区B，可以避免静电防护部6占据显示区A的面积，使得显示面板100具有较大的屏占比。
需要说明的是，由于镜面层5采用具有较高光线反射率的金属材料制备形成，使得镜面层5中容易产生并积累静电。通过设置与镜面层5电连接的静电防护部6，可以利用该静电防护部6对静电进行释放，进而可以对镜面层5进行静电防护，避免出现静电放电的现象。
由此，本公开的一些实施例所提供的显示面板100，通过在绑定区B内设置与镜面层5电连接的静电防护部6，在避免静电防护部6占据显示区A的面积的同时，利用静电防护部6对镜面层5进行静电防护。这样可以避免 镜面层5中产生的静电形成积累，进而可以避免出现静电放电的现象，避免出现因静电放电对显示装置100中的器件结构造成损伤的情况，确保显示装置100的正常使用。
上述静电防护部6的结构包括多种，可以根据实际需要选择设置。
在一些实施例中，上述静电防护部6包括第一子静电防护部61和/或第二子静电防护部62。也即，静电防护部6可以包括第一子静电防护部61，或者静电防护部6可以包括第二子静电防护部62，或者静电防护部6可以同时包括第一子静电防护部61和第二子静电防护部62。
下面结合附图对第一子静电防护部61和第二子静电防护部62的结构进行示意性说明。
在一种实现方式中，如图2和图3所示，边框区B包括绑定区B1。显示面板100具有设置在绑定区B1的至少一个第一固定电压信号端G1。也即，第一固定电压信号端G1的数量可以为一个，也可以为多个。
基于此，如图2和图3所示，静电防护部6可以包括第一子静电防护部61。该第一子静电防护部61还与第一固定电压信号端G1电连接，第一子静电防护部61被配置为，将镜面层5中产生的静电传输至第一固定电压信号端G1。
在一些示例中，如图3所示，显示面板100还包括：设置在绑定区B1的多个引脚7，以及与该多个引脚7绑定的柔性电路板(Flexible Printed Circuit，简称FPC)8。FPC 8可以向该多个引脚7传输电信号，或传输至该多个引脚7的电信号可以传输至FPC 8。
在一些示例中，如图3所示，显示面板100还包括：与上述多个引脚7绑定的覆晶薄膜(Chip On Film，or，Chip On Flex，简称COF)9。FPC 8可以通过COF 9与上述多个引脚7绑定，进而FPC 8可以通过COF 9向该多个引脚7传输电信号，或传输至该多个引脚7的电信号可以通过COF 9传输至FPC 8。
需要说明的是，第一固定电压信号端G1的类型包括多种，显示面板100可以具有不同的结构。
在一些实施例中，如图2和图3所示，显示面板100还包括：设置在边框区B的至少一条低电源电压信号线10。该低电源电压信号线10例如可以围绕显示区A，也可以设置在显示区A的一侧。
上述多个引脚7可以包括至少一个第一导电引脚71。上述至少一条低电源电压信号线10可以与该至少一个第一导电引脚71电连接。其中，该至少 一条低电源电压信号线10可以与该至少一个第一导电引脚71一一对应地电连接，或者，一个第一导电引脚71可以与多条低电源电压信号线10电连接。
示例性的，FPC 8具有低电源电压信号点位。FPC 8被配置为，通过低电源电压信号点位将低电源电压信号(VSS)直接经上述至少一个第一导电引脚71传输至低电源电压信号线10，或者，依次经COF 9及上述至少一个第一导电引脚71传输至低电源电压信号线10。
在此情况下，上述至少一个第一导电引脚71中的至少一个导电引脚71可以作为第一固定电压信号端G1。也即，若第一导电引脚71的数量为一个，则该第一导电引脚71作为第一固定电压信号端G1；若第一导电引脚71的数量为多个，则该多个第一导电引脚71中的至少一个第一导电引脚71作为第一固定电压信号端G1。
在一些示例中，第一子静电防护部61可以包括至少一条第一引线611，该至少一条第一引线611还与作为第一固定电压信号端G1的第一导电引脚71电连接。
第一引线611和第一导电引脚71之间的连接关系例如可以为：第一引线611和第一导电引脚71之间一一对应地电连接，或者，一个第一导电引脚71可以与多条第一引线611电连接。
此时，第一引线611被配置为，将镜面层5产生的静电经第一导电引脚71传输至FPC 8的低电源电压信号点位，或者依次经COF 9及第一导电引脚71传输至FPC 8的低电源电压信号点位。这样便可以利用第一引线611对镜面层5中产生的静电进行释放，避免镜面层5中产生的静电形成积累，进而避免出现静电释放的现象。
第一引线611的设置方式例如可以为：第一引线611与镜面层5材料相同且同层设置。
需要说明的是，本文中提及的“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。这样一来，可以在一次构图工艺中，同时制备形成第一引线611与镜面层5，有利于简化显示面板100的制备工艺。
可选的，第一引线611与镜面层5可以呈一体结构。也即，在制备形成第一引线611和镜面层5后，两者所对应的图案是连续的，未断开的。
示例性的，考虑到镜面层5的形成材料，可以采用溅射工艺在封装层4远离衬底1的一侧表面形成金属薄膜，然后采用光刻工艺对该金属薄膜进行图案化，形成镜面层5及第一引线611。这样也就使得该金属薄膜的形状与封装层4远离衬底1一侧的表面的形状相匹配，在得到镜面层5及第一引线611之后，也就可以使得第一引线611与封装层4的侧面相接触，并沿封装层4的侧面延伸至绑定区B1。
此处，封装层4的侧面例如指的是，封装层4远离衬底1的一侧表面中，位于边框区B、相比于衬底1具有坡度且与衬底1之间具有夹角的部分表面。
可以理解的是，由于第一引线611与镜面层5材料相同且同层设置，且第一引线611沿封装层4的侧面延伸至绑定区B1与第一导电引脚71电连接，这样在制备形成显示面板100的多个子像素2的过程中，可以避免对所使用的掩膜板进行改版，例如，可以避免对用于形成但不局限于形成源漏导电层、平坦层或像素界定层3等的掩膜版进行改版，进而可以避免大幅增加显示装置100的生产成本，提高显示装置100的通用性。
在另一些实施例中，如图2和图3所示，显示面板100还包括：设置在边框区B的至少一条地线11。该地线11例如可以围绕显示区A，也可以设置在显示区A的一侧。
上述多个引脚7可以包括至少一个第二导电引脚72。上述至少一条地线11可以与该至少一个第二导电引脚72电连接。其中，该至少一条地线11可以与该至少一个第二导电引脚72一一对应地电连接，或者，一个第二导电引脚72可以与多条地线11电连接。
示例性的，FPC 8具有地线点位。这样上述至少一条地线11可以依次通过上述至少一个第二导电引脚72及COF 9连接至FPC 8的地线点位，将地线11接地，从而可以对显示面板100进行接地保护。
在此情况下，上述至少一个第二导电引脚72中的至少二个导电引脚72可以作为第一固定电压信号端G1。也即，若第二导电引脚72的数量为一个，则该第二导电引脚72作为第一固定电压信号端G1；若第二导电引脚72的数量为多个，则该多个第二导电引脚72中的至少一个第二导电引脚72作为第一固定电压信号端G1。
在一些示例中，第一子静电防护部61可以包括至少一条第二引线612，该至少一条第二引线612还与作为第一固定电压信号端G1的第二导电引脚72电连接。
第二引线612和第二导电引脚72之间的连接关系例如可以为：第二引线 612和第二导电引脚72之间一一对应地电连接，或者，一个第二导电引脚72可以与多条第二引线612电连接。
此时，第二引线612被配置为，将镜面层5产生的静电依次经第二导电引脚72及COF 9传输至FPC 8的地线点位。这样便可以利用第一引线611对镜面层5中产生的静电进行释放，避免镜面层5中产生的静电形成积累，进而避免出现静电释放的现象。
第二引线612的设置方式例如可以为：第二引线612与镜面层5材料相同且同层设置。
这样可以在一次构图工艺中，同时制备形成第二引线612与镜面层5，有利于简化显示面板100的制备工艺。
可选的，第二引线612与镜面层5可以呈一体结构。也即，在制备形成第一引线611和镜面层5后，两者所对应的图案是连续的，未断开的。
示例性的，考虑到镜面层5的形成材料，可以采用溅射工艺在封装层4远离衬底1的一侧表面形成金属薄膜，然后采用光刻工艺对该金属薄膜进行图案化，形成镜面层5及第二引线612。这样也就使得该金属薄膜的形状与封装层4远离衬底1一侧的表面的形状相匹配，在得到镜面层5及第二引线612之后，也就可以使得第二引线612与封装层4的侧面相接触，并沿封装层4的侧面延伸至绑定区B1。
此处，关于封装层4的侧面的说明，可以参照上述一些示例中的示意性说明，此处不再赘述。
可以理解的是，由于第二引线612与镜面层5材料相同且同层设置，且第二引线612沿封装层4的侧面延伸至绑定区B1与第二导电引脚72电连接，这样在制备形成显示面板100的多个子像素2的过程中，可以避免对所使用的掩膜板进行改版，例如，可以避免对用于形成但不局限于形成源漏导电层、平坦层或像素界定层3等的掩膜版进行改版，进而可以避免大幅增加显示装置100的生产成本，提高显示装置100的通用性。
在一些示例中，显示区A和边框区B中的绑定区B1之间的相对位置关系包括多种，可以根据实际需要选择设置。
可选的，上述绑定区B1的数量可以为一个或多个。该绑定区B1可以位于显示区A的一侧，或者，在绑定区B1包括多个的情况下，该多个绑定区B1可以分别位于显示区A的不同侧。
示例性的，如图3所示，以绑定区B1的数量为一个、且该绑定区B1位于显示区A的一侧为例，沿绑定区B1和显示区A的排列方向，显示区A的 平分线O 1和绑定区B1的平分线O 2重合或大致重合。例如，显示区A的形状可以相对于其平分线O 1对称设置，绑定区B1的形状可以相对于其平分线O 2对称设置。
在此情况下，第一子静电防护部61的设置方式例如可以为：
如图3所示，在第一子静电防护部61包括至少一条第一引线611的情况下，该第一引线611的数量为多条，且该多条第一引线611相对于显示区A的平分线O 1对称分布。如图3所示，在第一子静电防护部61包括至少一条第二引线612的情况下，该第二引线612的数量为多条，该多条第二引线612相对于显示区A的平分线O 1对称分布。
这样有利于提高第一子静电防护部61所包括的第一引线611或第二引线612的分布均匀性，提高显示面板100的线路分布的对称性。
在另一种实现方式中，如图5及图7所示，显示面板100具有设置在边框区B的多个第二固定电压信号端G2。该多个第二固定电压信号端G2可以包括第一电压信号端G21和第二电压信号端G22。其中，第一电压信号端G21所传输的第一电压信号(例如可以用VGH表示)的电压高于第二电压信号端G22所传输的第二电压信号(例如可以用VGL表示)的电压。
基于此，如图5及图7所示，静电防护部6可以包括第二子静电防护部62。该第二子静电防护部62还与第一电压信号端G21及第二电压信号端G22电连接。
需要说明的是，镜面层5中产生的静电可以为正静电，也可以为负静电。
在此情况下，第二子静电防护部62可以被配置为，在镜面层5中产生的静电的电压高于第一电压信号VGH的电压(也即镜面层5中产生的静电为正静电)的情况下，将该静电传输至第一电压信号端G21。第二子静电防护部62还可以被配置为，在镜面层5中产生的静电的电压低于第二电压信号VGL的电压(也即镜面层5中产生的静电为负静电)的情况下，将该静电传输至第二电压信号端G22。
这样便可以利用第二子静电防护部62对镜面层5中产生的静电进行释放，避免镜面层5中形成静电积累，进而避免出现显示面板100内部静电放电的情况。
在一些示例中，如图5及图7所示，第二子静电防护部62包括至少一个静电防护电路621。
示例性的，如图6所示，静电防护电路621可以包括第一晶体管6211和第二晶体管6212。
其中，第一晶体管6211与镜面层5和第一电压信号端G21电连接。第一晶体管6211被配置为，在镜面层5中产生的静电的电压高于第一电压信号VGH的电压的情况下导通，将静电传输至第一电压信号端G21。也即，在镜面层5中产生的静电为正静电、且该正静电的电压高于第一电压信号VGH的电压的情况下，第一晶体管6211可以在正静电和第一电压信号VGH之间所形成的压差下导通，对该正静电进行释放。
第二晶体管6212与镜面层5和第二电压信号端G22电连接。第二晶体管6212被配置为，在镜面层5中产生的静电的电压低于第二电压信号VGL的电压的情况下导通，将静电传输至第二电压信号端G22。也即，在镜面层5中产生的静电为负静电、且该负静电的电压低于第二电压信号VGL的电压的情况下，第二晶体管6212可以在第一电压信号VGH和负静电之间所形成的压差下导通，对该负静电进行释放。
示例性的，上述第一晶体管6211和第二晶体管6212可以为薄膜晶体管，其类型可以与像素驱动电路21中的薄膜晶体管的类型相同。这样第一静电释放子电路6211、第二静电释放子电路6212和像素驱动电路21可以同步形成。
这样有利于简化显示面板100的制备工艺，避免因设置静电防护电路62＇而增加制备显示面板100的工艺流程，避免影响显示面板100的生产效率。
上述第一晶体管6211和第二晶体6212的数量可以根据实际需要选择设置。
示例性的，第一晶体管6211的数量可以为一个，也可以为多个。第二晶体6212的数量可以为一个，也可以为多个。在第一晶体管6211的数量为多个的情况下，该多个第一晶体管6211依次串接，在第二晶体6212的数量为多个的情况下，该多个第二晶体6212依次串接。
下面以第一晶体管6211的数量为一个，第二晶体管6212的数量为一个，对静电防护电路621的连接关系及工作过程进行示意性说明。
需要说明的是，薄膜晶体管包括N型晶体管或P型晶体管，N型晶体管和P型晶体管的导通方向相反。
第一晶体管6211和第二晶体管6212的类型可以相同，也可以不同。本公开的一些实施例以两者的类型相同为例。
如图6所示，第一晶体管6211的第一极62111和控制极62112电连接，且与第一电压信号端G21电连接，第一晶体管6211的第二极62113与镜面层5电连接。第二晶体管6212的第一极62121和控制极62122电连接，且与镜面层5电连接，第二晶体管6212的第二极62123与第二电压信号端G22电连 接。
此处，第一晶体管6211的控制极62112即为第一晶体管6211的栅极，第二晶体管6212的控制极62122即为第二晶体管6212的栅极。
在第一晶体管6211和第二晶体管6212均为P型管的情况下，第一晶体管6211的第一极62111则为第一晶体管6211的漏极，第一晶体管6211的第二极62113则为第一晶体管6211的源极；第二晶体管6212的第一极62121则为第二晶体管6212的漏极，第二晶体管6212的第二极62123则为第二晶体管6212的源极。
在第一晶体管6211和第二晶体管6212均为N型管的情况下，第一晶体管6211的第一极62111则为第一晶体管6211的源极，第一晶体管6211的第二极62113则为第一晶体管6211的漏极；第二晶体管6212的第一极62121则为第二晶体管6212的源极，第二晶体管6212的第二极62123则为第二晶体管6212的漏极。
示例性的，以第一晶体管6211和第二晶体管6212均为P型管为例。第一晶体管6211的第一极62111和控制极62112电连接之后，可以将第一晶体管6211等效为第一二极管，第一晶体管6211的第一极62111和控制极62112共同等效为第一二极管的阴极，第一晶体管6211的第二极62113等效为第一二极管的阳极。第二晶体管6212的第一极62121和控制极62122电连接之后，可以将第二晶体管6212等效为第二二极管，第二晶体管6212的第一极62121和控制极62122可以共同等效为第二二极管的阴极，第二晶体管6212的第二极62123等效为第二二极管的阳极。
这样若镜面层5中产生静电，在镜面层5中产生的静电的电压高于第一电压信号VGH的电压的情况下，第一晶体管6211导通，该静电(也即为正静电)从镜面层5，依次经过第一晶体管6211的源极及第一晶体管6211的漏极传输至第一电压信号端G21，对该静电进行释放，降低镜面层5的电位。
在镜面层5中产生的静电的电压低于第二电压信号VGL的电压的情况下，第二晶体管6212导通，该静电(也即为负静电)从镜面层5，依次经过第二晶体管6212的漏极及第二晶体管6212的源极传输至第二电压信号端G22，对该静电进行释放，也即，第二电压信号端G22所传输的第二电压信号VGL依次经过第二晶体管6212的源极及第二晶体管6212的漏极传输至镜面层5，抬高镜面层5的电位。
这样也便可以实现对镜面层5的静电防护。
需要说明的是，静电防护电路621的数量可以为一个，也可以为多个。
在一些示例中，在静电防护电路621的数量为多个的情况下，该多个静电防护电路621可以相互间隔地设置在边框区B内。这样有利于提高第二子静电防护部62对镜面层5的静电防护效果。
示例性的，如图5所示，上述边框区B围绕显示区A。该多个静电防护电路621可以相互间隔地设置在边框区B内。也即，该多个静电防护电路621可以相互间隔地设置在镜面层5的周围。
这样在镜面层5的某一位置产生的静电的电压高于第一电压信号VGH的电压或低于第二电压信号VGL的电压的情况下，便可以通过与该位置相距较近的静电防护电路621进行静电释放，有效提高了对静电进行释放的效率，使得第二子静电防护部62具有较好的静电防护效果。
而且，在某一个静电防护电路621出现异常的情况下，还可以通过其他的静电防护电路621对静电进行释放，这样可以使得第二子静电防护部62具有较好的可靠性。
可选的，如图5所示，显示区A可以呈矩形。此时，静电防护电路621的数量例如可以为四个，该四个静电防护电路621可以分布在显示区A的四个角部所对应的位置处。如图7所示，静电防护电路621的数量例如可以为七个，其中四个静电防护电路621可以分布在显示区A的四个角部所对应的位置处，另外三个静电防护电路621可以分布在显示区A的四个角部中每相邻的两个角部之间所对应的位置处。这样有利于提高静电释放的平衡性，提高静电防护的效果。
在一些实施例中，在静电防护部6同时包括第一子静电防护部61和第二子静电防护部62的情况下，第一子静电防护部61和第二子静电防护部62的设置位置可以根据实际需要选择设置。
在一些示例中，如图7所示，显示区A可以呈矩形，边框区B围绕该显示区A。此时，边框区B中的绑定区B1可以位于显示区A的一侧。
基于此，第一子静电防护部61可以设置在显示区A的一侧。在第二静电防护部62包括多个静电防护电路621的情况下，该多个静电防护电路621可以均匀地设置在显示区A的其余侧。
此处，显示区A的其余侧指的是，显示区A中除与绑定区B1相对的一侧以为的其他三侧。均匀地设置例如指的是，位于显示区A的同一侧的多个静电防护电路621等间隔设置。
本公开的一些实施例提供了一种显示装置1000。如图8所示，该显示装置1000包括如上述任一实施例中所述的显示面板100。
当然，显示装置1000还可以包括承载上述显示面板100的外壳等。
本公开的一些实施例所提供的显示装置1000所能实现的有益效果，与上述一些实施例中提供的显示面板100所能实现的有益效果相同，此处不再赘述。
在一些实施例中，上述显示装置1000可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种显示面板，具有显示区和位于所述显示区旁侧的边框区；所述显示面板包括：
    衬底；
    设置在所述衬底的一侧、且位于所述显示区的多个子像素；
    设置在所述多个子像素远离所述衬底一侧的镜面层；以及，
    与所述镜面层电连接、且位于所述边框区的静电防护部；
    其中，所述静电防护部被配置为，对所述镜面层进行静电防护。
  2. 根据权利要求1所述的显示面板，其中，所述边框区包括绑定区；
    所述显示面板具有设置在所述绑定区的至少一个第一固定电压信号端，其中，所述静电防护部包括还与所述第一固定电压信号端电连接的第一子静电防护部；
    所述第一子静电防护部被配置为，将所述镜面层中产生的静电传输至所述第一固定电压信号端。
  3. 根据权利要求2所述的显示面板，还包括：
    设置在所述边框区的至少一条低电源电压信号线；
    设置在所述绑定区、且与所述低电源电压信号线电连接的至少一个第一导电引脚；以及，
    与所述至少一个第一导电引脚绑定的柔性电路板，所述柔性线路板具有低电源电压信号点位，所述柔性电路板被配置为，通过所述低电源电压信号点位将低电源电压信号经所述至少一个第一导电引脚传输至所述低电源电压信号线；
    其中，至少一个所述第一导电引脚作为所述第一固定电压信号端；
    所述第一子静电防护部包括至少一条第一引线，所述第一引线还与作为所述第一固定电压信号端的第一导电引脚电连接；
    所述第一引线被配置为，将所述镜面层产生的静电经所述第一导电引脚传输至所述柔性电路板的低电源电压信号点位。
  4. 根据权利要求3所述的显示面板，还包括：与所述至少一个导电引脚绑定的覆晶薄膜；
    所述柔性电路板通过所述覆晶薄膜与所述至少一个导电引脚绑定；
    所述第一引线被配置为，将所述镜面层产生的静电经所述第一导电引脚及所述覆晶薄膜传输至所述柔性电路板的低电源电压信号点位。
  5. 根据权利要求2所述的显示面板，还包括：
    设置在所述边框区的至少一条地线；
    设置在所述绑定区、且与所述地线电连接的至少一个第二导电引脚；
    与所述至少一个第二导电引脚绑定的覆晶薄膜；以及，
    与所述覆晶薄膜绑定的柔性电路板，所述柔性电路板具有地线点位；
    其中，至少一个所述第二导电引脚作为所述第一固定电压信号端；
    所述第一子静电防护部包括至少一条第二引线，所述第二引线还与作为所述第一固定电压信号端的第二导电引脚电连接；
    所述第二引线被配置为，将所述镜面层产生的静电经所述第二导电引脚及所述覆晶薄膜传输至所述柔性电路板的地线点位。
  6. 根据权利要求3～5中任一项所述的显示面板，其中，
    在所述第一子静电防护部包括至少一条第一引线的情况下，所述第一引线与所述镜面层材料相同且同层设置；
    在所述第一子静电防护部包括至少一条第二引线的情况下，所述第二引线与所述镜面层材料相同且同层设置。
  7. 根据权利要求3～6中任一项所述的显示面板，还包括：设置在所述多个子像素和所述镜面层之间、且覆盖所述多个子像素的封装层；
    在所述第一子静电防护部包括至少一条第一引线的情况下，所述第一引线与所述封装层的侧面接触，并沿所述封装层的侧面延伸至所述绑定区；
    在所述第一子静电防护部包括至少一条第二引线的情况下，所述第二引线与所述封装层的侧面接触，并沿所述封装层的侧面延伸至所述绑定区。
  8. 根据权利要求3～7中任一项所述的显示面板，其中，沿所述绑定区和所述显示区的排列方向，所述显示区的平分线和所述绑定区的平分线重合或大致重合；
    在所述第一子静电防护部包括至少一条第一引线的情况下，所述第一引线的数量为多条，多条第一引线相对于所述显示区的平分线对称分布；
    在所述第一子静电防护部包括至少一条第二引线的情况下，所述第二引线的数量为多条，多条第二引线相对于所述显示区的平分线对称分布。
  9. 根据权利要求1～8中任一项所述的显示面板，其中，所述显示面板具有设置在所述边框区的多个第二固定电压信号端；所述多个第二固定电压信号端包括第一电压信号端和第二电压信号端，所述第一电压信号端所传输的第一电压信号的电压高于所述第二电压信号端所传输的第二电压信号的电压；
    其中，所述静电防护部包括还与所述第一电压信号端和所述第二电压信 号端电连接的第二子静电防护部；
    所述第二子静电防护部包括至少一个静电防护电路；
    所述静电防护电路包括与所述镜面层和所述第一电压信号端电连接的至少一个第一晶体管，以及与所述镜面层和所述第二电压信号端电连接的至少一个第二晶体管；
    所述至少一个第一晶体管被配置为，在所述镜面层中产生的静电的电压高于所述第一电压信号的电压的情况下导通，将静电传输至所述第一电压信号端；
    所述至少一个第二晶体管被配置为，在所述镜面层中产生的静电的电压低于所述第二电压信号的电压的情况下导通，将静电传输至所述第二电压信号端。
  10. 根据权利要求9所述的显示面板，其中，子像素包括像素驱动电路；
    所述至少一个第一晶体管、所述至少一个第二晶体管和所述像素驱动电路同步形成。
  11. 根据权利要求9或10所述的显示面板，其中，所述边框区围绕所述显示区；
    所述静电防护电路的数量为多个，该多个静电防护电路相互间隔地设置在所述边框区内。
  12. 根据权利要求2～11中任一项所述的显示面板，其中，所述显示区呈矩形，所述边框区围绕所述显示区；
    在所述静电防护部包括所述第一子静电防护部和所述第二子静电防护部、且所述第二静电防护部包括多个静电防护电路的情况下，
    所述第一子静电防护部设置在所述显示区的一侧，所述多个静电防护电路均匀地设置在所述显示区的其余侧。
  13. 根据权利要求1～12中任一项所述的显示面板，还包括：设置在每相邻的两个子像素之间的像素界定层；
    所述镜面层在所述衬底上的正投影位于所述像素界定层在所述衬底上的正投影范围内，或，所述镜面层在所述衬底上的正投影与所述像素界定层在所述衬底上的正投影重合。
  14. 一种显示装置，包括：如权利要求1～13中任一项所述的显示面板。
PCT/CN2021/110632 2020-09-30 2021-08-04 显示面板及显示装置 WO2022068383A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/926,706 US20230209949A1 (en) 2020-09-30 2021-08-04 Display panel and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011062894.9A CN112186019B (zh) 2020-09-30 2020-09-30 显示面板及显示装置
CN202011062894.9 2020-09-30

Publications (1)

Publication Number Publication Date
WO2022068383A1 true WO2022068383A1 (zh) 2022-04-07

Family

ID=73948262

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/110632 WO2022068383A1 (zh) 2020-09-30 2021-08-04 显示面板及显示装置

Country Status (3)

Country Link
US (1) US20230209949A1 (zh)
CN (1) CN112186019B (zh)
WO (1) WO2022068383A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114937420A (zh) * 2022-05-27 2022-08-23 武汉天马微电子有限公司 显示面板和显示装置

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112186019B (zh) * 2020-09-30 2022-10-25 京东方科技集团股份有限公司 显示面板及显示装置
EP4131407A4 (en) * 2020-05-28 2023-09-27 BOE Technology Group Co., Ltd. DISPLAY BOARD AND DISPLAY DEVICE
WO2022236813A1 (zh) * 2021-05-14 2022-11-17 重庆康佳光电技术研究院有限公司 显示面板、显示背板及其制作方法
CN113345376A (zh) * 2021-06-21 2021-09-03 合肥维信诺科技有限公司 一种显示面板和显示装置
CN113571566B (zh) * 2021-07-23 2024-05-28 京东方科技集团股份有限公司 显示面板及其制造方法、显示装置
CN113964139A (zh) * 2021-10-22 2022-01-21 京东方科技集团股份有限公司 显示模组及其制备方法
WO2024065759A1 (zh) * 2022-09-30 2024-04-04 京东方科技集团股份有限公司 发光基板、背光模组及显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103715681A (zh) * 2013-12-30 2014-04-09 京东方科技集团股份有限公司 一种静电放电保护电路及显示装置
US20170116929A1 (en) * 2015-10-23 2017-04-27 Semiconductor Energy Laboratory Co., Ltd. Display panel, input/output device, and data processing device
CN107342284A (zh) * 2017-08-14 2017-11-10 武汉天马微电子有限公司 显示基板及显示装置
CN108766994A (zh) * 2018-06-20 2018-11-06 武汉天马微电子有限公司 有机发光显示面板和有机发光显示装置
CN110767841A (zh) * 2019-10-31 2020-02-07 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置
CN110838509A (zh) * 2019-11-20 2020-02-25 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN112186019A (zh) * 2020-09-30 2021-01-05 京东方科技集团股份有限公司 显示面板及显示装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11600234B2 (en) * 2015-10-15 2023-03-07 Ordos Yuansheng Optoelectronics Co., Ltd. Display substrate and driving method thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103715681A (zh) * 2013-12-30 2014-04-09 京东方科技集团股份有限公司 一种静电放电保护电路及显示装置
US20170116929A1 (en) * 2015-10-23 2017-04-27 Semiconductor Energy Laboratory Co., Ltd. Display panel, input/output device, and data processing device
CN107342284A (zh) * 2017-08-14 2017-11-10 武汉天马微电子有限公司 显示基板及显示装置
CN108766994A (zh) * 2018-06-20 2018-11-06 武汉天马微电子有限公司 有机发光显示面板和有机发光显示装置
CN110767841A (zh) * 2019-10-31 2020-02-07 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置
CN110838509A (zh) * 2019-11-20 2020-02-25 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN112186019A (zh) * 2020-09-30 2021-01-05 京东方科技集团股份有限公司 显示面板及显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114937420A (zh) * 2022-05-27 2022-08-23 武汉天马微电子有限公司 显示面板和显示装置
CN114937420B (zh) * 2022-05-27 2024-02-09 武汉天马微电子有限公司 显示面板和显示装置

Also Published As

Publication number Publication date
CN112186019A (zh) 2021-01-05
US20230209949A1 (en) 2023-06-29
CN112186019B (zh) 2022-10-25

Similar Documents

Publication Publication Date Title
WO2022068383A1 (zh) 显示面板及显示装置
US11925079B2 (en) Display panel and display device
US20220406880A1 (en) Flexible display panel and manufacturing method therefor, and display device
US20220328579A1 (en) Display substrate and display device
CN112714955B (zh) 显示基板、显示面板及显示基板的制备方法
CN110010648B (zh) 电致发光显示器件
US20240194134A1 (en) Display Substrate and Preparation Method Thereof, Display Apparatus
CN114335114A (zh) 阵列基板及显示装置
CN115768213A (zh) 显示面板及其制备方法、显示装置
US20220344441A1 (en) Display apparatus
US20220291779A1 (en) Display device
US11861119B2 (en) Display panel and method for manufacturing the same, and display apparatus
US11997897B2 (en) Display substrate including connection line and power line surrounding display area, preparation method thereof, and display device
WO2024000292A1 (zh) 显示基板及显示装置
CN113206139B (zh) 显示面板及其制作方法、显示装置
US20240134475A1 (en) Touch structure and manufacturing method thereof, display panel, and display device
US20240090272A1 (en) Method of manufacturing display device and mother substrate
US20230403882A1 (en) Display panel and display device
US20230309367A1 (en) Method of manufacturing display device and mother substrate
CN112035012B (zh) 一种显示基板及显示装置
EP4280279A1 (en) Display substrate and display device
WO2023137766A1 (zh) 显示面板、显示模组及显示装置
WO2023070404A1 (zh) 显示面板及其制备方法、显示装置
US20240185770A1 (en) Display device
US20230266843A1 (en) Input sensing part and display device including the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21874045

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 07.07.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 21874045

Country of ref document: EP

Kind code of ref document: A1