WO2024065759A1 - 发光基板、背光模组及显示装置 - Google Patents

发光基板、背光模组及显示装置 Download PDF

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Publication number
WO2024065759A1
WO2024065759A1 PCT/CN2022/123478 CN2022123478W WO2024065759A1 WO 2024065759 A1 WO2024065759 A1 WO 2024065759A1 CN 2022123478 W CN2022123478 W CN 2022123478W WO 2024065759 A1 WO2024065759 A1 WO 2024065759A1
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WIPO (PCT)
Prior art keywords
light
emitting substrate
sub
voltage signal
functional
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PCT/CN2022/123478
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English (en)
French (fr)
Inventor
孙一丁
张冰
高亮
王康丽
康萍
徐佳伟
许邹明
李佑路
王兵
王杰
吴信涛
罗宁雨
韩停伟
Original Assignee
京东方科技集团股份有限公司
合肥京东方瑞晟科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方瑞晟科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280003398.7A priority Critical patent/CN118284966A/zh
Priority to PCT/CN2022/123478 priority patent/WO2024065759A1/zh
Publication of WO2024065759A1 publication Critical patent/WO2024065759A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a light-emitting substrate, a backlight module and a display device.
  • LEDs Light-emitting diodes
  • Mini LEDs sub-millimeter light-emitting diodes
  • Micro LEDs micrometer light-emitting diodes
  • Mini LED can be used in backlight and direct display, usually in backlight applications. By densely arranging a large number of them, it can achieve regional dimming in a smaller range. Compared with traditional backlight design, it can achieve better brightness uniformity and higher color contrast within a smaller mixing distance, thereby achieving ultra-thin, high color rendering, and power saving of terminal products. At the same time, because its design can be matched with flexible substrates, combined with the curved surface of liquid crystal display panels (LCDs), it can also achieve curved displays similar to organic light-emitting diodes (OLEDs) while ensuring picture quality.
  • LCDs liquid crystal display panels
  • Micro LED is generally used for RGB direct display applications, which can overcome the wiring and reliability defects of regular chips.
  • COB Chip on Board
  • COG Chip on Glass
  • flexible substrates high-definition display effects on curved surfaces can also be achieved. Coupled with its self-luminous characteristics, it has a very broad market in some special modeling requirements (such as automotive displays).
  • a light-emitting substrate which has a functional area and a binding area.
  • the binding area and the functional area are arranged in sequence along a first direction.
  • the light-emitting substrate includes: a substrate; a plurality of functional element groups, which are located on one side of the substrate; the plurality of functional element groups are located in the functional area; a first electrostatic path, which is located on the same side of the substrate as the plurality of functional element groups, the first electrostatic path is electrically connected to the binding area, and a part of the first electrostatic path is located in the functional area; the first electrostatic path is configured to conduct static electricity from the functional area to the binding area.
  • the first electrostatic path includes a first annular conductive structure and at least one first conductive pattern;
  • the first annular conductive structure includes a first sub-segment, a second sub-segment and a third sub-segment electrically connected in sequence, the first sub-segment and the second sub-segment are located on opposite sides of the functional area along the second direction, and the third sub-segment is located on a side of the functional area away from the binding area; at least a portion of the first conductive pattern is located in the functional area, and the orthographic projection of the first conductive pattern on the substrate has no overlap with the orthographic projection of the functional element group on the substrate; wherein the first conductive pattern is electrically connected to the third sub-segment; and the first direction intersects with the second direction.
  • first conductive patterns when there are multiple first conductive patterns, in the first direction, two adjacent first conductive patterns are electrically connected, and the first conductive pattern closest to the third subsegment is electrically connected to the third subsegment.
  • the plurality of first conductive patterns are made of the same material as the first annular conductive structure and are disposed in the same layer; the third sub-segment and the first conductive pattern electrically connected to the third sub-segment are an integral structure.
  • the first electrostatic path further includes: a plurality of bridge portions; in any column of the first conductive patterns, two adjacent first conductive patterns are electrically connected via the bridge portions.
  • At least one of the plurality of bridge portions is a jumper resistor.
  • the functional element group includes a driving chip and at least one light-emitting device group, the light-emitting device group includes at least two light-emitting devices; the light-emitting substrate also includes: a first connecting line connecting the driving chip and the light-emitting device group, and a second connecting line connecting any two light-emitting devices belonging to the same light-emitting device group; the orthographic projection of the multiple first conductive patterns on the substrate has no overlap with the orthographic projection of the first connecting line and the second connecting line on the substrate.
  • the plurality of first conductive patterns are made of the same material as the first connecting lines and the second connecting lines and are disposed in the same layer.
  • the first electrostatic path includes a plurality of first voltage lines and at least one third connecting line, the plurality of first voltage lines extend along the first direction and are arranged at intervals along the second direction, and the third connecting line is used to connect at least two first voltage lines.
  • the third connection line is located on a side of the functional area away from the binding area.
  • the (2i-1)th first voltage line and the 2ith first voltage line are connected to the same third connection line; i is a positive integer.
  • a plurality of functional element groups arranged along the first direction are connected to a first voltage line.
  • the multiple third connection lines are connected to form an integrated structure.
  • the plurality of first voltage lines and the plurality of third connection lines are made of the same material and are disposed in the same layer.
  • the multiple functional element groups are arranged in multiple columns; the functional area includes multiple device areas, and one functional element group is located in one device area; the first electrostatic path includes: multiple second voltage lines, one second voltage line is electrically connected to a column of functional element groups; multiple second conductive patterns, and the orthographic projections of the multiple second conductive patterns on the substrate have no overlap with the orthographic projections of the functional element groups on the substrate; wherein the second conductive pattern is electrically connected to the second voltage line, and at least a portion of the second conductive pattern is located in the device area.
  • the plurality of second voltage lines and the plurality of second conductive patterns are made of the same material and are disposed in the same layer.
  • the light-emitting substrate also includes: a plurality of functional pins located in the binding area; a second electrostatic path, the second electrostatic path being a second annular conductive structure surrounding the functional area; the second annular conductive structure includes a first sub-portion, a second sub-portion, a third sub-portion and a fourth sub-portion electrically connected in sequence, the first sub-portion and the second sub-portion being located on opposite sides of the functional area along the second direction, the third sub-portion being located on a side of the functional area away from the binding area, and a portion of the fourth sub-portion being located on a side of the binding area away from the functional area; the second electrostatic path is configured to conduct static electricity from the functional area to the binding area; wherein the plurality of functional pins are electrically connected to a portion of the fourth sub-portion located on a side of the binding area away from the functional area.
  • the light-emitting substrate also includes multiple second voltage signal pin groups, multiple first voltage signal pin groups and multiple floating pins located in the binding area, the second voltage signal pin group includes multiple second voltage signal pins, and the first voltage signal pin group includes multiple first voltage signal pins.
  • At least one floating pin is electrically connected to a portion of the fourth sub-portion located on a side of the binding region away from the functional region.
  • a plurality of the first voltage signal pin groups and a plurality of the second voltage signal pin groups are alternately arranged along the second direction; and at least one floating pin is disposed between any adjacent first voltage signal pin groups and second voltage signal pin groups.
  • a spacing in the first direction between a floating pin electrically connected to the fourth sub-section and a second voltage signal pin of a second voltage signal pin group adjacent to the floating pin is greater than or equal to 200 ⁇ m.
  • a distance between two adjacent first voltage signal pins is greater than or equal to 100 ⁇ m.
  • the second electrostatic path, the plurality of functional pins, the plurality of floating pins, the plurality of second voltage signal pin groups, and the plurality of first voltage signal pin groups are made of the same material and are disposed on the same layer.
  • a backlight module comprising: a light-emitting substrate as described in any of the above embodiments, and an optical film located on the light-emitting side of the light-emitting substrate.
  • a display device comprising: a backlight module as described in the above embodiment; an array substrate located at a light emitting side of the backlight module; and a color film substrate located at a side of the array substrate away from the backlight module.
  • FIG. 1a is a structural diagram of a display device according to some embodiments of the present disclosure.
  • FIG1b is a structural diagram of another display device according to some embodiments of the present disclosure.
  • FIG2 is a structural diagram of a backlight module according to some embodiments of the present disclosure.
  • FIG3a is a schematic diagram of the discharge current and discharge time of a human body charged model and a charging device charged model to a light-emitting substrate;
  • FIG3 b is a schematic diagram of an arrangement of an anti-static loop wire, a driving chip, and a light-emitting device on a light-emitting substrate in an implementation manner;
  • FIG3 c is a schematic diagram of a process of static electricity of a charger charging model generated in a film lamination process of a light-emitting substrate;
  • FIG3d is a schematic diagram of static electricity accumulated on the light-emitting substrate corresponding to FIG3c for the charging device charging model
  • FIG3e is a schematic diagram of an electrostatic breakdown phenomenon of a charged model of a charging device on a light-emitting substrate in an implementation manner
  • FIG4 is a structural diagram of a light-emitting substrate according to some embodiments of the present disclosure.
  • FIG5 is a structural diagram of a first electrostatic path according to some embodiments of the present disclosure.
  • FIG6 is a structural diagram of another light-emitting substrate according to some embodiments of the present disclosure.
  • FIG7 is a structural diagram of another first electrostatic path according to some embodiments of the present disclosure.
  • FIG8 is a structural diagram of yet another first electrostatic path according to some embodiments of the present disclosure.
  • FIG9a is a schematic diagram of a conduction path of static electricity on a light-emitting substrate in an implementation manner
  • FIG9b is a schematic diagram of a light-emitting substrate having a defective lamp explosion in an implementation manner
  • FIG9c is a schematic diagram of an electrostatic conduction path on a light-emitting substrate according to some embodiments of the present disclosure.
  • FIG10 is a partial structural diagram of a first electrostatic path according to some embodiments of the present disclosure.
  • FIG11 is a structural diagram of a second electrostatic path according to some embodiments of the present disclosure.
  • FIG12a is a structural diagram of another second electrostatic path according to some embodiments of the present disclosure.
  • FIG12b is a local structural diagram of the B1 region in FIG12a;
  • FIG12c is another partial structural diagram of the B1 region in FIG12a;
  • FIG12d is a local structural diagram of the B2 region in FIG12a;
  • FIG12e is another partial structural diagram of the B2 region in FIG12a;
  • FIG12f is a local structural diagram of the B3 area in FIG12a;
  • FIG13 is a structural diagram of yet another light-emitting substrate according to some embodiments of the present disclosure.
  • FIG14 is a flow chart of preparing a light-emitting substrate according to some embodiments of the present disclosure.
  • FIG15 is a structural diagram of yet another light-emitting substrate according to some embodiments of the present disclosure.
  • FIG. 16 is a comparison diagram of the antistatic capabilities of light-emitting substrates with different structural designs according to some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of the features.
  • plural means two or more.
  • connection and its derivative expressions may be used.
  • connection should be understood in a broad sense.
  • connection can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.
  • connection may be used to indicate that two or more components are in direct physical or electrical contact with each other.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “upon” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that” or “if [a stated condition or event] is detected” are optionally interpreted to mean “upon determining that” or “in response to determining that” or “upon detecting [a stated condition or event]” or “in response to detecting [a stated condition or event],” depending on the context.
  • perpendicular and “equal” include the conditions described and conditions that are similar to the conditions described, and the range of the similar conditions is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system).
  • perpendicular includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°.
  • “Equal” includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, that the difference between the two equalities is less than or equal to 5% of either one of them.
  • Exemplary embodiments are described herein with reference to cross-sectional views and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and/or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.
  • the display device 1 can be any display device that displays either motion (e.g., video) or fixed (e.g., still images) and whether text or images. More specifically, it is expected that the display device of the embodiment can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, cameras, game consoles, watches, clocks, calculators, TV monitors, flat panel displays, computer monitors, car displays (e.g., odometer displays, etc.), navigators, cockpit controllers and/or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photos, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.
  • PDAs personal data assistants
  • GPS receivers/navigators cameras
  • MP4 video players cameras
  • game consoles
  • the display device 1 may include multiple sub-display devices, and the multiple sub-display devices are spliced together to form a large-size display device to meet the large-size display requirements.
  • the display device can be called a spliced display device.
  • the display device 1 may be an LCD (Liquid Crystal Display) display device.
  • the display device 1 includes: a backlight module 10 , an array substrate 20 located on the light emitting side of the backlight module 10 , and a color film substrate 30 located on a side of the array substrate 20 away from the backlight module 10 .
  • the backlight module 10 can be used as a light source to provide backlight.
  • the backlight provided by the backlight module 10 can be white light or blue light.
  • the light emitting side of the backlight module 10 refers to the side from which the backlight module 10 emits light.
  • the array substrate 20 may include a plurality of pixel driving circuits and a plurality of pixel electrodes, the plurality of pixel driving circuits being arranged in an array, for example, and the plurality of pixel driving circuits being electrically connected to the plurality of pixel electrodes in a one-to-one correspondence, and the pixel driving circuits providing pixel voltages to the corresponding pixel electrodes.
  • the color film substrate 30 may include a variety of color filters, etc.
  • the color filters may include a red filter, a green filter, and a blue-green filter, etc.
  • the red filter can only allow the red light in the incident light to pass through
  • the green filter can only allow the green light in the incident light to pass through
  • the blue filter can only allow the blue light in the incident light to pass through.
  • the color filters may include a red filter and a green filter, etc.
  • the color filter substrate 30 further includes: a common electrode.
  • the common electrode can receive a common voltage.
  • the common electrode can also be disposed in the array substrate 20, which is not limited in the present disclosure.
  • the display device 1 further includes: a liquid crystal layer 40 located between the color filter substrate 30 and the array substrate 20 .
  • the liquid crystal layer 40 includes a plurality of liquid crystal molecules.
  • an electric field may be formed between the pixel electrode and the common electrode, and the liquid crystal molecules between the pixel electrode and the common electrode may be deflected under the action of the electric field.
  • the backlight provided by the backlight module 10 can pass through the array substrate 20 and be incident on the liquid crystal molecules of the liquid crystal layer 40.
  • the liquid crystal molecules flip, thereby changing the amount of light passing through the liquid crystal molecules, so that the light emitted by the liquid crystal molecules reaches a preset brightness.
  • the above light passes through the filters of different colors in the color filter substrate 30 and then emits.
  • the emitted light includes light of various colors, such as red light, green light, blue light, etc. The light of various colors cooperates with each other to enable the display device 1 to achieve display.
  • backlight modules 10 in the display device 1 there are various types of backlight modules 10 in the display device 1 , which can be configured according to actual conditions, and the present disclosure does not limit this.
  • the backlight module 10 may be an edge-type backlight module, or the backlight module 10 may be a direct-type backlight module.
  • the backlight module 10 as a direct-type backlight module as an example.
  • the backlight module 10 includes a light emitting substrate 100 and an optical film 200 located on the light emitting side of the light emitting substrate 100 .
  • Z in FIG. 2 refers to a third direction Z
  • the third direction Z is a thickness direction of the display device 1 .
  • the optical film 200 includes: a diffuser plate 210 , a quantum dot film 220 , a diffuser sheet 230 , and a composite film 240 , which are sequentially stacked on the light-emitting side of the light-emitting substrate 100 .
  • the diffusion plate 210 and the diffusion sheet 230 are used to eliminate lamp shadows and to even out the light emitted by the light-emitting substrate 100 to improve the uniformity of the light.
  • the quantum dot film 220 is used to convert the light emitted by the light emitting substrate 100.
  • the quantum dot film 220 can convert the blue light into white light and improve the purity of the white light.
  • the composite film 240 is used to increase the brightness of the light emitted by the light emitting substrate 100 .
  • the brightness of the light emitted by the light emitting substrate 100 after being incident on the optical film 200 is enhanced, and the purity and uniformity of the emitted light are higher.
  • the backlight module 10 may include a plurality of light-emitting substrates 100 and corresponding optical films.
  • the plurality of light-emitting substrates 100 may be spliced together, and the corresponding optical films may also be spliced together, so that the backlight module 10 has a larger size.
  • the backlight module 10 may be called a spliced display module, and may be applied to the spliced display device.
  • the backlight module 10 further includes: a support column 201 disposed between the light emitting substrate 100 and the diffusion plate 210 of the optical film 200 .
  • the support column 201 can be fixed on the light-emitting substrate 100 by glue.
  • the support column 201 can be used to support the optical film 200, and make the light emitted by the light-emitting substrate 100 obtain a certain light mixing distance, so as to further eliminate the lamp shadow and improve the uniformity of the light.
  • the display device 1 further includes: a frame, a display chip and other electronic accessories.
  • the display device 1 includes a light-emitting substrate 100, and the light-emitting substrate 100 is directly used to display images.
  • the display device is often used in commercial displays, such as display screens in traffic management command centers or display screens in commercial plazas.
  • the discharge model in this case is the human body model (HBM for short).
  • the equivalent resistance of the human body is 1500 ⁇ .
  • the characteristics of the electrostatic discharge in the light-emitting substrate are (as shown in Figure 3a), the discharge time is long, the peak current is small, and an extremely high instantaneous discharge current can be generated within a few hundred nanoseconds, and the discharge current can reach several amperes.
  • One implementation method is to set an anti-static loop at the edge of the light-emitting substrate, thereby reducing the static electricity entering from the edge of the light-emitting substrate and avoiding the discharge of the HBM model.
  • Figure 3b shows the relative arrangement of the signal lines, the driver chip IC and the light-emitting device LED on the light-emitting substrate in one implementation method.
  • the GND Ring is an anti-static loop that surrounds the periphery of the driver chip IC and the light-emitting device LED.
  • the preparation process of the light-emitting substrate generally includes the assembly or transportation process of the light-emitting substrate.
  • the light-emitting substrate will contact other charged conductors, and then the static electricity on the charged conductor will be transmitted to the light-emitting substrate, thereby generating charging and discharging phenomena.
  • the charging and discharging model generated in this preparation process is the Charged Device Model (CDM for short).
  • CDM Charged Device Model
  • the discharge characteristics of the CDM model are that the discharge current rise time is short, about 0.2ns to 0.4ns, and the duration is 6ns to 8ns, but the current peak is extremely large, about 15 times to 20 times that of the HBM model under the same static electricity.
  • the rise time of the CDM model is about 0.2ns, and the current can reach up to about 21A. If such a large current and fast discharge pulse discharge occurs in the light-emitting substrate, it is easy to cause damage to the internal circuit of the light-emitting substrate, and the damage is often concentrated in the binding area of the light-emitting substrate and the side of the functional area away from the binding area.
  • the charging and discharging model of static electricity generated by being transmitted to the light-emitting substrate during the lamination process is the CDM model. As shown in FIG. 3c and FIG.
  • the roller (the roller is generally made of metal material) for transmitting the film and the pressure roller (the roller is generally made of silicone material) for attaching the film will continuously rub against each other during the contact with the film, thereby generating a large amount of static electricity.
  • the static electricity will be injected into the light-emitting substrate. As shown in FIG.
  • the static electricity when the static electricity accumulates to a certain extent in the light-emitting substrate, the static electricity will break down and discharge the pad capacitor (the capacitor formed between two adjacent pads) or the adjacent pin capacitor (the capacitor formed between two adjacent pins) of the light-emitting substrate, causing the pad of the light-emitting substrate to be damaged, affecting the function of the light-emitting substrate.
  • the damage mainly occurs in the area where the electronic components are located on the side of the functional area away from the binding area (that is, the sky side of the light-emitting substrate). Since the damage degree of the CDM model to the light-emitting substrate is much greater than that of the HBM, the anti-static design scheme based on the HBM model is not suitable for the CDM model.
  • the present disclosure provides a light emitting substrate 100 , as shown in FIG4 , the light emitting substrate 100 has a functional area F and a binding area B.
  • the binding area B and the functional area F are arranged in sequence along a first direction X.
  • the binding area B is an area for implementing the binding of the light emitting substrate 100 and the display chip.
  • the shape of the functional area F can be rectangular or circular.
  • the light emitting substrate 100 includes: a substrate 110 , and a plurality of functional element groups 120 .
  • the substrate 110 may be a flexible substrate.
  • the flexible substrate may be, for example, a PET (Polyethylene Terephthalate) substrate, a PEN (Polyethylene Naphthalate Two Formic Acid Glycol Ester) substrate, or a PI (Polyimide) substrate.
  • the substrate 110 may be a rigid substrate.
  • the material of the substrate may be glass, etc.
  • the substrate 110 may also be a printed circuit board (PCB), an aluminum substrate, etc.
  • the functional element group 120 is located on one side of the substrate 110 ; and a plurality of functional element groups 120 are located in the functional region F.
  • the functional element group 120 may include a plurality of micro resistors or micro capacitors, etc.
  • the functional element group 120 may include a driving chip 121 and at least one light emitting device group 122.
  • the light emitting device group 122 includes at least two light emitting devices 123.
  • the functional element group 120 may include a driving chip 121 and a light emitting device group 122 .
  • the functional element group 120 may include a driving chip 121 and a plurality of light emitting device groups 122 .
  • the light emitting device group 122 may include two light emitting devices 123 , four light emitting devices 123 , or six light emitting devices 123 .
  • At least two light emitting devices 123 in the same light emitting device group 122 are connected to each other in series.
  • the light emitting device group 122 emits light.
  • the light emitting device 123 may be a sub-millimeter light emitting diode (Mini Light Emitting Diode, referred to as Mini LED). Since the grain size of Mini LED is smaller, the light mixing distance between adjacent Mini LEDs can be greatly shortened, so that the light emitting substrate has the advantages of adjustable regional brightness, high color rendering, high contrast, etc. It can also make the light emitting substrate 100 thinner and lighter, more energy-saving, and thus make the application of the light emitting substrate including Mini LED more flexible. In addition, compared with OLED (Organic Light Emitting Diode, referred to as OLED), the light emitting substrate including Mini LED has lower cost, longer life, and less risk of screen burn-in.
  • OLED Organic Light Emitting Diode
  • the functional element group 120 may include a driving chip 121 and at least one light emitting device group 122 .
  • the light emitting substrate 100 further includes: a first electrostatic path 130 .
  • the first electrostatic path 130 and the functional element group 120 are located on the same side of the substrate 110, the first electrostatic path 130 is connected to the binding area B, and a portion of the first electrostatic path 130 is located in the functional area F; the first electrostatic path 130 is configured to conduct static electricity from the functional area F to the binding area B.
  • the static electricity accumulated on the functional element group 120 in the functional area F can be transmitted to the portion of the first electrostatic path 130 located in the functional area F, and then transmitted to the binding area B through the first electrostatic path 130, thereby avoiding the charging and discharging of static electricity in the functional area F, thereby preventing this phenomenon from affecting the function of the functional element group 120.
  • a first electrostatic path 130 is provided on the light-emitting substrate 100, so that the first electrostatic path 130 and the plurality of functional element groups are located on the same side of the substrate 110, and the first electrostatic path 130 is connected to the binding area B, and a portion of the first electrostatic path 130 is located in the functional area F, so that the static electricity in the functional area F of the light-emitting substrate can be conducted to the binding area B through the first electrostatic path 130, thereby avoiding the charging and discharging of the static electricity generated during the preparation process of the light-emitting substrate 100, and avoiding affecting the functions of the functional element group 120 and the light-emitting substrate 100.
  • the first electrostatic path 130 includes a first annular conductive structure 131 and at least one first conductive pattern 132;
  • the first annular conductive structure 131 includes a first sub-segment 131a, a second sub-segment 131b and a third sub-segment 131c that are electrically connected in sequence, the first sub-segment 131a and the second sub-segment 131b are located on opposite sides of the functional area F along the second direction Y, and the third sub-segment 131c is located on a side of the functional area F away from the binding area B; at least a portion of the first conductive pattern 132 is located in the functional area B.
  • the first electrostatic path 130 includes a first annular conductive structure 131 and a first conductive pattern 132 .
  • the first electrostatic path 130 includes a first annular conductive structure 131 and a plurality of first conductive patterns 132 .
  • the multiple first conductive patterns 132 are arranged in an array.
  • the multiple first conductive patterns 132 are arranged in multiple rows along the first direction X and in multiple columns along the second direction Y.
  • the first annular conductive structure 131 may not be annular in a strict sense, and may be a part of annular shape.
  • the first ring-shaped conductive structure 131 is a part of a square ring.
  • the third sub-segment 131 c is located on a side of the functional area F away from the binding area B, that is, the third sub-segment 131 c is located on the sky side of the light-emitting substrate 100 .
  • the light emitting substrate 100 further has a peripheral area D.
  • the peripheral area D surrounds the functional area F.
  • first sub-segment 131 a , the second sub-segment 131 b and the third sub-segment 131 c in the first annular conductive structure 131 may be located in the peripheral region D.
  • a portion of the first conductive pattern 132 is located in the functional region B, and another portion of the first conductive pattern 132 is located in the peripheral region D.
  • the first conductive pattern 132 is entirely located in the functional area B.
  • an orthographic projection of the first conductive pattern 132 on the substrate 110 does not overlap with an orthographic projection of the functional element group 120 on the substrate 110 .
  • the orthographic projection of the first conductive pattern 132 on the substrate 110 does not overlap with the orthographic projection of the functional element group 120 on the substrate 110. Also, the boundary line of the orthographic projection of the first conductive pattern 132 on the substrate 110 does not cross the boundary line of the orthographic projection of the functional element group 120 on the substrate 110.
  • the first conductive pattern 132 is located in a gap region between adjacent functional element groups 120 .
  • the first direction X and the second direction Y intersect.
  • the angle between the first direction X and the second direction Y may be 80°, 85°, 90° or 95°.
  • the first conductive pattern 132 is electrically connected to the third subsegment 131 c .
  • each first conductive pattern 132 in a row of first conductive patterns 132 closest to the third sub-segment 131c is electrically connected to the third sub-segment 131c.
  • each first conductive pattern 132 in the row of first conductive patterns 132 is partially located in the functional area F and partially located in the peripheral area D.
  • the static electricity when electrostatic charge accumulates during the preparation process of the light-emitting substrate, the static electricity will be conducted through at least one first conductive pattern 132 to the third sub-segment 131c electrically connected thereto, and continue to be conducted to the first sub-segment 131a or the second sub-segment 131b, and then to the binding area B, so that the static electricity of the light-emitting substrate is conducted from the functional area F to the binding area B, thereby avoiding the accumulation of static electricity in the functional area F, and avoiding the damage of the light-emitting device 123 or the driving chip 121 in the functional element group 120 when the static electricity accumulates to a certain extent, thereby avoiding affecting the function of the functional element group 120, improving the anti-static ability of the light-emitting substrate, and improving the yield rate of the prepared light-emitting substrate.
  • first conductive patterns 132 when there are multiple first conductive patterns 132 , in the first direction X, two adjacent first conductive patterns 132 are electrically connected, and the first conductive pattern 132 closest to the third subsegment 131 c is electrically connected to the third subsegment 131 c .
  • first conductive patterns 132 in a column of first conductive patterns 132 are electrically connected, and along the first direction X, the first first conductive pattern 132 in each column of first conductive patterns 132 is electrically connected to the third sub-segment 131c, so that each first conductive pattern 132 is directly or indirectly electrically connected to the third sub-segment 131c.
  • the static electricity in the functional area F can be conducted to the binding area B through the first conductive pattern 132 in the first electrostatic path, thereby avoiding the influence of static electricity accumulation on the function of the functional element group, improving the anti-static ability of the light-emitting substrate, and improving the yield rate of the light-emitting substrate.
  • two adjacent first conductive patterns 132 may also be electrically connected.
  • the plurality of first conductive patterns 132 are made of the same material and disposed on the same layer as the first annular conductive structure 131 .
  • the material of the first conductive pattern 132 may be a metal material, such as copper.
  • the above-mentioned “same layer” refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process.
  • a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.
  • first conductive patterns 132 are arranged on the same layer as the first annular conductive structure 131.
  • the electrical connection between the first conductive pattern 132 and the third sub-segment 131c can be achieved directly on the same layer without crossing other film layers, thereby simplifying the preparation process of the light-emitting substrate.
  • the third sub-segment 131c and the first conductive pattern 132 electrically connected to the third sub-segment 131c are in an integrated structure.
  • the above-mentioned "integrated structure” means that the two connected patterns are arranged in the same layer, and the two patterns are continuous and not separated.
  • the above-mentioned arrangement can make the third sub-segment 131c and the first conductive pattern 132 electrically connected thereto be formed in one patterning process, thereby simplifying the preparation process of the light-emitting substrate.
  • the setting of the "integrated structure” can improve the reliability of the electrical connection between the third sub-segment 131c and the first conductive pattern 132, and there is no need to set up other conductive structures, thereby reducing the preparation cost of the light-emitting substrate.
  • the first electrostatic path 130 further includes: a plurality of bridge portions 133 .
  • a plurality of bridge portions 133 In any column of the first conductive patterns 132 , two adjacent first conductive patterns 132 are electrically connected via the bridge portions 133 .
  • the bridge portion 133 plays a role of conducting electricity.
  • the bridge portion 133 is located in the functional area F.
  • the bridge portion 133 is made of conductive material, and the bridge portion 133 may also be an electrical component, such as a resistor or a capacitor, etc.
  • Multiple bridge portions 133 may all be conductive materials, or some bridge portions 133 may be electrical components, and some bridge portions 133 may be conductive materials, which only play the role of electrical connection.
  • the plurality of bridge portions 133 and the plurality of functional element groups 120 are located on the same side of the substrate 110 , and the plurality of bridge portions 133 are located on a side of the first conductive pattern 132 away from the substrate 110 .
  • At least one of the plurality of bridge portions 133 is a jumper resistor 133 a .
  • the jumper resistor 133a is a resistor for a special purpose, and the resistance value of the jumper resistor 133a is very small, not completely zero.
  • the jumper resistor 133a can be set between two points in the light-emitting substrate 100 that cannot be directly connected by a line by an automatic placement machine or an automatic insertion machine to achieve electrical connection between the two points. Therefore, setting at least one of the multiple bridge portions 133 as a jumper resistor 133a can improve the processing convenience of the light-emitting substrate 100 and reduce the cost of the light-emitting substrate 100.
  • the plurality of bridge portions 133 may all be jumper resistors. Alternatively, a portion (one or more) of the plurality of bridge portions 133 may be jumper resistors.
  • the light emitting substrate 100 further includes: a first connection line CL1 connecting the driving chip 121 and the light emitting device group 122 , and a second connection line CL2 connecting any two light emitting devices 123 belonging to the same light emitting device group 122 .
  • the same light emitting device group 122 has one second connection line CL2 .
  • the same light emitting device group 122 has five second connection lines CL2 .
  • the arrangement of the second connection lines CL2 is related to the arrangement of the light emitting devices 123 in the light emitting device group 122.
  • the light emitting device group 122 includes six light emitting devices 123
  • the six light emitting devices 123 are connected in series
  • the six light emitting devices 123 are arranged in two rows along the first direction X, and in three columns along the second direction Y
  • two adjacent second connection lines CL2 extend in the first direction X and the second direction Y, respectively
  • the orthographic projection profiles of the light emitting device group 122 and the plurality of second connection lines CL2 on the substrate are concave-convex.
  • the orthographic projections of the first conductive patterns 132 on the substrate 110 do not overlap with the orthographic projections of the first and second connection lines CL1 and CL2 on the substrate 110.
  • the first conductive patterns 132 and the first and second connection lines CL1 and CL2 do not overlap each other.
  • the orthographic projections of the plurality of first conductive patterns 132 on the substrate 110 do not overlap with the orthographic projections of the first connection line CL1 and the second connection line CL2 on the substrate 110 .
  • the orthographic projection shape of the first conductive pattern 132 on the substrate 110 is the same as the shape of the region surrounded by two adjacent light emitting device groups 122 .
  • one first conductive pattern 132 may be located between two adjacent light emitting device groups 122 along the first direction X.
  • One first conductive pattern 132 may also be located between two adjacent functional element groups 120 along the first direction X.
  • One first conductive pattern 132 may also be located between the functional element group 120 closest to the third sub-segment 131c and the third sub-segment 131c.
  • the area of the orthographic projection of the first conductive pattern 132 on the substrate 110 may be smaller than the area of the region surrounded by two adjacent light emitting device groups 122 .
  • the first conductive pattern 132 may almost fill the area surrounded by two adjacent light emitting device groups 122 .
  • the first conductive pattern 132 may fill a portion of the area surrounded by two adjacent light emitting device groups 122 .
  • the plurality of first conductive patterns 132 are made of the same material and disposed on the same layer as the first connection lines CL1 and the second connection lines CL2 .
  • the material of the first connection line CL1 may be a metal material, such as copper.
  • the first conductive pattern 132 , the first connection line CL1 , and the second connection line CL2 can be formed in one patterning process, thereby simplifying the manufacturing process of the light emitting substrate 100 .
  • the first electrostatic path 130 includes a plurality of first voltage lines VL1 and at least one third connection line CL3 , wherein the plurality of first voltage lines VL1 extend along the first direction X and are arranged at intervals along the second direction Y, and the third connection line CL3 is used to connect at least two first voltage lines VL1 .
  • H in Figure 6 is a via, for example, the pin of the driving chip 121 passes through the via to be electrically connected to the signal line (such as the first voltage line VL1, the data line DL, etc.), or the pin of the light-emitting device group 122 passes through the via to be electrically connected to the second voltage signal line VL2.
  • the signal line such as the first voltage line VL1, the data line DL, etc.
  • the pin of the light-emitting device group 122 passes through the via to be electrically connected to the second voltage signal line VL2.
  • a plurality of functional element groups 120 arranged along the first direction X are connected to one first voltage line VL1 .
  • the first voltage line VL1 is located in the functional area F, a first voltage line VL1 is electrically connected to a column of functional element groups 120, and the first voltage line VL1 extends to the binding area B, the first voltage line VL1 is electrically connected to the binding area B (for example, the first voltage signal pin group mentioned below), and can transmit the signal from the display chip to the functional element group 120.
  • the first voltage signal transmitted by the first voltage signal line VL1 may be a constant voltage signal.
  • the first voltage signal line VL1 may be electrically connected to the driver chip 121, and the driver chip 121 provides a first voltage signal for a plurality of light emitting devices 123 in the light emitting device group 122 of the same functional element group 120, and the first voltage signal may be a ground voltage signal of the functional element group 120.
  • the first electrostatic path 130 may include one third connection line CL3.
  • the first electrostatic path 130 may include a plurality of third connection lines CL3 , and a plurality of adjacent third connection lines CL3 may not be connected to each other.
  • the first electrostatic path 130 may include a plurality of third connection lines CL3 , and a plurality of adjacent third connection lines CL3 may be connected to each other.
  • one third connection line CL3 may be used to connect two first voltage lines VL1 .
  • one third connection line CL3 can be used to connect a plurality of first voltage lines VL1 .
  • the static electricity when static electricity accumulates between two adjacent columns of functional element groups 120, the static electricity can be transmitted to the binding area B through the first voltage line VL1 and the third connection line CL3, thereby avoiding the static electricity from being transmitted between the two adjacent columns of functional element groups 120, avoiding the static electricity from being transmitted from the first voltage signal line VL1 to the light-emitting device 123, and then avoiding the static electricity from the light-emitting device 123 to the driver chip 121 along the first connection line CL1, avoiding affecting the accuracy of the signal transmitted from the driver chip 121 to the light-emitting device 123, and avoiding the light-emitting device from having a bad lamp explosion, thereby improving the anti-static ability of the light-emitting substrate, especially the charging and discharging phenomenon of the CDM model.
  • the third connection line CL3 is located on a side of the functional region F away from the binding region B.
  • the antistatic capability of the functional region F away from the binding region B i.e., the sky side of the light-emitting substrate
  • the function of the functional element group 120 near the sky side can be damaged.
  • the light emitting substrate 100 further includes: a plurality of addressing signal lines DL.
  • a plurality of addressing signal lines DL connect two driving chips 121 of two adjacent functional element groups 120.
  • the functional element group closest to the sky in the (2i-1)th column of functional element groups 120 is connected to the functional element group closest to the sky in the 2ith column of functional element groups 120 through one addressing signal line DL.
  • the (2i-1)th first voltage line VL1 and the 2ith first voltage line VL1 are connected to the same third connection line CL3 ; i is a positive integer.
  • the static electricity when static electricity is generated in the light-emitting substrate, the static electricity can be transmitted along the (2i-1)th first voltage line VL1, the 2ith first voltage line VL1 and the corresponding third connecting line CL3, thereby improving the anti-static ability of the light-emitting substrate and improving the yield rate of the light-emitting substrate, thereby preventing the static electricity from being transmitted along the above-mentioned (2i-1)th functional element group 120, the corresponding addressing signal line DL and the 2ith functional element group 120 to the driver chip 121 in the functional element group 120, thereby preventing the static electricity from being greater than 12kV, preventing the static electricity from damaging the driver chip 121, and preventing the light-emitting device group 122 controlled by the driver chip 121 from malfunctioning.
  • FIG. 9a shows a transmission method of static electricity on the light-emitting substrate in an implementation method.
  • the path shown by the dotted line with an arrow in FIG. 9a is the transmission path of static electricity.
  • static electricity is conducted to the light-emitting substrate and transmitted along the GND line. Since the GND lines of the odd columns and the GND lines of the even columns are connected to the driver chip through the addressing signal line, the static electricity will be transmitted to the driver chip through the addressing signal line.
  • the (2i-1)th first voltage line VL1 and the 2ith first voltage line VL1 are arranged along the second direction Y and are connected to the same third connecting line CL3, so that the transmission path of static electricity on the light-emitting substrate is changed (as shown in FIG. 9c ).
  • Static electricity is transmitted on the first voltage line VL1 of the first static electricity path 130, thereby improving the anti-static ability of the light-emitting substrate, avoiding static electricity from being transmitted to the driving chip 121, and further avoiding the pins of the driving chip 121 from being punctured, thereby avoiding the light-explosion defect phenomenon of the light-emitting substrate.
  • the multiple third connection lines CL3 are connected to form an integrated structure.
  • the above arrangement may be that two adjacent third connection lines CL3 are connected to form an integral structure.
  • the above arrangement may also be that a plurality of adjacent third connection lines CL3 are connected to form an integral structure.
  • a plurality of third connection lines CL3 can be formed in one patterning process, thereby simplifying the preparation process of the light-emitting substrate 100 .
  • the plurality of first voltage lines VL1 and the plurality of third connection lines CL3 are made of the same material and are disposed in the same layer.
  • the material of the third connection line CL3 may be metal, for example, the metal may be copper.
  • the above-mentioned “same layer” refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process.
  • a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.
  • the electrical connection between the first voltage line VL1 and the third connecting line material CL3 can be achieved directly in the same layer without crossing other film layers, thereby simplifying the preparation process of the light-emitting substrate.
  • the third connection line CL3 and the first voltage line VL1 electrically connected thereto are in an integrated structure.
  • the third connection line CL3 and the first voltage line VL1 electrically connected thereto can be formed in one patterning process, thereby simplifying the preparation process of the light-emitting substrate.
  • the setting of the "integrated structure" can improve the reliability of the electrical connection between the third connection line CL3 and the first voltage line VL1, and there is no need to set up other conductive structures, thereby reducing the preparation cost of the light-emitting substrate.
  • a plurality of functional element groups 120 are arranged in a plurality of columns.
  • the functional area F includes a plurality of device areas F0, and one functional element group 120 is located in one device area F0.
  • the plurality of device regions F0 are arranged in an array.
  • the first electrostatic path 130 includes: a plurality of second voltage lines VL2 .
  • One second voltage line VL2 is electrically connected to a column of functional element groups 120 .
  • the second voltage line VL2 extends along the first direction X.
  • the second voltage line VL2 is electrically connected to one end of the light emitting device group 122 of a column of functional element groups 120.
  • the second voltage line VL2 is also electrically connected to the binding area B.
  • the second voltage signal line VL2 is used to provide a second voltage signal to the light emitting device group 122.
  • the second voltage signal may be a device power supply voltage signal of the light emitting device group 122.
  • the first electrostatic path 130 further includes: a plurality of second conductive patterns 134 .
  • the orthographic projections of the plurality of second conductive patterns 134 on the substrate 110 do not overlap with the orthographic projections of the functional element group 120 on the substrate 110 .
  • the orthographic projections of the second conductive patterns 134 on the substrate 110 do not overlap with the orthographic projections of the functional element group 120 on the substrate 110.
  • the second conductive patterns 134 and the functional element group 120 do not overlap with each other.
  • the orthographic projections of the second conductive patterns 134 on the substrate 110 do not overlap with the orthographic projections of the first connection lines CL1 and the second connection lines CL2 in the functional element groups 120 on the substrate 110.
  • the second conductive patterns 134 and the first connection lines CL1 and the second connection lines CL2 do not overlap or block each other.
  • the orthographic projection shape of the second conductive pattern 134 on the substrate 110 is the same as the shape of the region surrounded by two adjacent light emitting device groups 122 .
  • the area of the orthographic projection of the second conductive pattern 134 on the substrate 110 may be smaller than the area of the region surrounded by two adjacent light emitting device groups 122 .
  • the second conductive pattern 134 may fill the area surrounded by two adjacent light emitting device groups 122 .
  • the second conductive pattern 134 may fill a portion of the area surrounded by two adjacent light emitting device groups 122 .
  • the second conductive pattern 134 is electrically connected to the second voltage line VL2 , and at least a portion of the second conductive pattern 134 is located in the device region F0 .
  • a portion of the second conductive pattern 134 may be located in one device region F0, and another portion of the second conductive pattern 134 may be located in another adjacent device region F0.
  • the second conductive pattern 134 may be located between two adjacent functional element groups 120 along the first direction X.
  • the second conductive pattern 134 is entirely located in one device region F0 .
  • the second conductive pattern 134 may be located between two adjacent light emitting device groups 122 along the first direction X.
  • a portion of the second conductive pattern 134 is located in the device region F0, while another portion of the second conductive pattern 134 may be located in a region between the functional element group 120 closest to the third sub-segment 131c and the third sub-segment 131c.
  • the second conductive pattern 134 may also be located in the region between two adjacent device regions F0 .
  • the static electricity generated in the preparation process of the light-emitting substrate can be conducted to the second voltage line VL2 through the second conductive pattern 134, and then conducted to the binding area B through the second voltage line VL2, so that the static electricity is conducted from the functional area F to the binding area B, thereby improving the anti-static ability of the light-emitting substrate, thereby avoiding the accumulation of static electricity in the functional area F, and thereby avoiding static electricity from causing the breakdown of the pads of the functional element group 120 in the functional area F, thereby avoiding the phenomenon of lamp explosion.
  • the plurality of second conductive patterns 134 may be arranged in a plurality of rows and columns.
  • One second voltage line VL2 may be electrically connected to a plurality of second conductive patterns 134 in one column of the second conductive patterns 134 .
  • the plurality of second voltage lines VL2 and the plurality of second conductive patterns 134 are made of the same material and are disposed in the same layer.
  • the material of the second conductive pattern 134 may be metal, for example, the metal may be copper.
  • the above-mentioned “same layer” refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process.
  • a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.
  • the electrical connection between the second voltage line VL2 and the multiple second conductive patterns 134 can be achieved directly in the same layer without crossing other film layers, thereby simplifying the preparation process of the light-emitting substrate.
  • the second voltage line VL2 and the plurality of second conductive patterns 134 electrically connected thereto are in an integrated structure.
  • the second voltage line VL2 and the second conductive patterns 134 electrically connected thereto can be formed in one patterning process, thereby simplifying the manufacturing process of the light-emitting substrate.
  • the setting of the "integrated structure" can improve the reliability of the electrical connection between the second voltage line VL2 and the second conductive patterns 134, and does not require the setting of other conductive structures, thereby reducing the manufacturing cost of the light-emitting substrate.
  • the light emitting substrate 100 further includes: a plurality of functional pins FP located in the binding area B and a second electrostatic path 140 .
  • the second electrostatic path 140 is a second annular conductive structure surrounding the functional area F.
  • the second annular conductive structure includes a first sub-portion 141, a second sub-portion 142, a third sub-portion 143 and a fourth sub-portion 144 which are electrically connected in sequence, the first sub-portion 141 and the second sub-portion 142 are located on opposite sides of the functional area F along the second direction Y, the third sub-portion 143 is located on a side of the functional area F away from the binding area B, and a part of the fourth sub-portion 144 is located on a side of the binding area B away from the functional area F.
  • the fourth sub-portion 144 includes a first portion 144a, a second portion 144b, and a third portion 144c.
  • the first portion 144a of the fourth sub-portion 144 is electrically connected to the third sub-portion 143
  • the third portion 144c is electrically connected to the first sub-portion 141
  • the third portion 144c is located on a side of the binding area B away from the functional area F.
  • the first portion 144a, the second portion 144b, and the third portion 144c all extend along the second direction Y, and along the second direction Y, the first portion 144a, the third portion 144c, and the second portion 144b are arranged in sequence and are not connected.
  • the plurality of function pins FP are electrically connected to a portion of the fourth sub-portion 144 located on a side of the binding region B away from the function region F.
  • multiple functional pins FP are electrically connected to the third part 144c and the first part 144a of the fourth sub-section 144
  • multiple functional pins FB are electrically connected to the third part 144c and the second part 144b of the fourth sub-section 144, thereby realizing the electrical connection between the first part 144a, the third part 144c, and the second part 144b of the fourth sub-section 144, so that the second electrostatic path 140 becomes a closed loop shape.
  • the second electrostatic path 140 is configured to conduct static electricity from the functional area F to the binding area B.
  • a second electrostatic path 140 is set in the light-emitting substrate 100.
  • the second electrostatic path 140 is a ring-shaped conductive structure, so that the static electricity generated in the functional area F of the light-emitting substrate 100 can be conducted to the binding area B through the second electrostatic path 140, thereby avoiding the accumulation of static electricity in the functional area F, thereby avoiding the breakdown of the pads of the functional element group 120 in the functional area F caused by static electricity, and avoiding the phenomenon of lamp explosion.
  • the setting of the fourth sub-section 144 allows the fourth sub-section 144 to form a closed loop with the first sub-section 141, the second sub-section 142, and the third sub-section 143 through the functional pin FP before the light-emitting substrate 100 is bound to the display chip, thereby conducting the static electricity generated in the preparation process of the light-emitting substrate to the closed loop, thereby improving the yield rate of the light-emitting substrate and avoiding the damage of the driving chip caused by the static electricity.
  • the light emitting substrate 100 further includes: a plurality of floating pins (Dummy Pins) RP located in the binding area B.
  • a plurality of floating pins (Dummy Pins) RP located in the binding area B.
  • At least one floating pin RP is electrically connected to a portion of the fourth sub-portion 144 located on a side of the binding region B away from the functional region F.
  • a floating pin RP is electrically connected to a portion of the fourth sub-portion 144 located on a side of the binding region B away from the functional region F.
  • the plurality of floating pins RP are electrically connected to a portion of the fourth sub-portion 144 located on a side of the binding region B away from the functional region F.
  • static electricity on the light-emitting substrate 100 can be conducted to the second static electricity path 140 through the floating pin RP, thereby increasing the static electricity conduction path in the functional area F and improving the anti-static ability of the light-emitting substrate.
  • the light-emitting substrate 100 also includes a plurality of first voltage signal pin groups VP1 and a plurality of second voltage signal pin groups VP2 located in the binding area B, the second voltage signal pin group VP2 includes a plurality of second voltage signal pins, and the first voltage signal pin group VP1 includes a plurality of first voltage signal pins.
  • the multiple first voltage signal pins of the first voltage signal pin group VP1 there are intervals between the multiple first voltage signal pins of the first voltage signal pin group VP1, and the multiple first voltage signal pins are arranged in a row.
  • the multiple first voltage signal pin groups VP1 and the multiple second voltage signal pin groups VP2 are arranged in a row.
  • the first voltage signal pin may be electrically connected to at least one first voltage line VL1
  • the second voltage signal pin may be electrically connected to at least one second voltage line VL2 .
  • the first voltage signal pin can be electrically connected to the display chip, so as to receive the first voltage signal transmitted by the display chip, and transmit the first voltage signal to the corresponding first voltage line VL1.
  • the second voltage signal pin can be electrically connected to the display chip, so as to receive the second voltage signal transmitted by the display chip, and transmit the second voltage signal to the corresponding second voltage line VL2.
  • the plurality of first voltage signal pin groups VP1 and the plurality of second voltage signal pin groups VP2 are alternately arranged along the second direction Y; at least one floating pin RP is disposed between any adjacent first voltage signal pin groups VP1 and second voltage signal pin groups VP2.
  • At least one floating pin RP is disposed between the adjacent second voltage signal pin group VP2 and the adjacent first voltage signal pin group VP1.
  • at least one floating pin RP is disposed between the adjacent first voltage signal pin group VP1 and the adjacent second voltage signal pin group VP2.
  • a floating pin RP is disposed between the second voltage signal pin group VP2 and the first voltage signal pin group VP1.
  • a plurality of floating pins RP are disposed between the second voltage signal pin group VP2 and the first voltage signal pin group VP1.
  • the static electricity on the light-emitting substrate can be conducted to the floating pin RP, so that the static electricity can be conducted to the second static electricity path 140 through the floating pin RP, thereby realizing the extraction of static electricity, improving the anti-static ability of the light-emitting substrate 100, thereby avoiding the static electricity on the light-emitting substrate from being conducted to the adjacent second voltage signal pin group VP2 and the first voltage signal pin group VP1, avoiding the accumulation of the static electricity on the adjacent second voltage signal pin group VP2 and the first voltage signal pin group VP1, and then avoiding the static electricity from breaking through the adjacent second voltage signal pin and the first voltage signal pin, avoiding the light-emitting substrate 100 from exploding.
  • the floating pin RP that is not electrically connected to the fourth sub-section 144 can be used to prevent interference between the signals of the second voltage signal pin group VP2 and the address pin DP located on the left and right sides of the floating pin RP, thereby improving the accuracy of the second voltage signal transmitted by the second voltage signal pin group VP2 and the accuracy of the address signal transmitted by the address pin DP, thereby improving the performance of the light-emitting substrate.
  • the floating pin RP may also be located on a side of the function pin FP away from the second voltage pin group VP2 , or may be located between the second voltage pin group VP2 and the data pin DP.
  • a spacing in the second direction Y between a floating pin RP electrically connected to the fourth sub-section 144 and a second voltage signal pin of a second voltage signal pin group VP2 adjacent to the floating pin RP is greater than or equal to 200 ⁇ m.
  • the distance between the floating pin RP electrically connected to the fourth sub-section 144 and the second voltage signal pin of the second voltage signal pin group VP2 adjacent to the floating pin RP in the second direction Y is 200 ⁇ m.
  • the spacing between the floating pin RP electrically connected to the fourth sub-section 144 and the second voltage signal pin of the second voltage signal pin group VP2 adjacent to the floating pin RP in the second direction Y is 210 ⁇ m, 220 ⁇ m, 230 ⁇ m, 240 ⁇ m or 250 ⁇ m.
  • the accuracy of the second voltage signal transmitted by the second voltage signal pin can be improved, and the display chip can achieve precise control of the light-emitting device in the functional element group, avoid the distance between the floating pin RP and the adjacent second voltage signal pin being too small, avoid static electricity on the floating pin RP, and interfere with or affect the second voltage signal transmitted by the adjacent second voltage signal pin, thereby avoiding the impact on the light-emitting device 123 in the functional element group 120.
  • a distance between two adjacent first voltage signal pins is greater than or equal to 100 ⁇ m.
  • the interval between two adjacent first voltage signal pins is 100 ⁇ m, 105 ⁇ m, 110 ⁇ m, 112 ⁇ m or 115 ⁇ m.
  • the distance between two adjacent first voltage signal pins can be made larger, thereby improving the accuracy of the first voltage signal transmitted by the first voltage signal pin, realizing the precise control of the light-emitting device in the functional element group by the display chip, avoiding the distance between adjacent first voltage signal pins being too small, avoiding affecting the binding effect of the first voltage signal pin and the display chip, and thus avoiding the short circuit between the first voltage signal pin and the display chip.
  • the second electrostatic path 140 , the plurality of function pins FP, the plurality of floating pins RP, the plurality of second voltage signal pin groups VP2 , and the plurality of first voltage signal pin groups VP1 are made of the same material and are disposed on the same layer.
  • the material of the function pin FP may be a metal material, such as copper.
  • two electrostatic paths 140, multiple functional pins FP, multiple floating pins RP, multiple second voltage signal pin groups VP2 and multiple first voltage signal pin groups VP1 can be formed in one patterning process, thereby simplifying the preparation process of the light-emitting substrate.
  • the second electrostatic path 140 and the plurality of functional pins FP and the plurality of floating pins RP electrically connected thereto are in an integrated structure.
  • the above-mentioned "integrated structure” means that the two connected patterns are arranged in the same layer, and the two patterns are continuous and not separated.
  • the above-mentioned setting method can make the second electrostatic path 140, and the multiple functional pins FP and multiple floating pins RP electrically connected thereto be formed in a single patterning process, thereby simplifying the preparation process of the light-emitting substrate.
  • the setting of the "integrated structure” can improve the reliability of the electrical connection between the second electrostatic path 140 and the multiple functional pins FP and the multiple floating pins RP, and there is no need to set up other conductive structures, thereby reducing the preparation cost of the light-emitting substrate.
  • the light emitting substrate 100 further includes: a plurality of third voltage lines VL3 and a plurality of data lines SL.
  • the third voltage line VL3 extends along the first direction X, and the plurality of third voltage lines VL3 are arranged at intervals along the second direction Y.
  • One third voltage line VL3 is electrically connected to a driver chip 121 in a column of functional element groups 120.
  • the data line SL extends along the first direction X, and the plurality of data lines SL are arranged at intervals along the second direction Y.
  • One data line SL is electrically connected to a driver chip 121 in a column of functional element groups 120, and the data line SL transmits a data signal to the corresponding driver chip 121.
  • the light emitting substrate 100 further includes: a plurality of addressing pins DP located in the binding area B and a plurality of third voltage signal pins VP3 .
  • the third voltage line VL3 is electrically connected to the third voltage signal pin VP3 of the binding area B.
  • the third voltage signal pin VP3 is used to receive a third voltage signal from the display chip, and transmit the third voltage signal to the third voltage line VL3 and the driver chip 121 in sequence.
  • the third voltage signal may be a constant voltage signal, for example, the third voltage signal may be a device power supply voltage signal of the driver chip 121.
  • the address signal line DL is electrically connected to the address pin DP of the binding area B.
  • the address pin DP is used to receive an address signal from the display chip and transmit the address signal to the address signal line DL and the driving chip 121 in sequence.
  • the third voltage signal pin VP3 located in the binding area B, the third voltage signal pin VP3, multiple function pins FP, multiple floating pins RP, multiple second voltage signal pin groups VP2 and multiple first voltage signal pin groups VP1, which can be set according to actual conditions, and the present disclosure does not impose any restrictions on this.
  • the third voltage signal pin VP3, the third voltage signal pin VP3, multiple function pins FP, multiple floating pins RP, multiple second voltage signal pin groups VP2 and multiple first voltage signal pin groups VP1 are arranged in a row along the second direction Y. As shown in FIG12d, the pins are periodically cycled from left to right in the order of at least one floating pin RP, function pin FP, second voltage signal pin group VP2, at least one floating pin RP, address pin DP, and first voltage signal pin group VP1.
  • the light emitting substrate 100 may include: a first conductive layer 150 located on one side of the substrate 110.
  • the material of the first conductive layer 150 may include a metal material, such as copper.
  • the first conductive layer 150 has a plurality of first pad patterns. At least two adjacent first pad patterns form a first pad group.
  • the driver chip 121 includes at least two pins, and the light emitting device 123 includes two pins.
  • the first pad pattern of the first pad group is welded to the pins of the driver chip 121 to fix the driver chip 121.
  • the first pad pattern of the first pad group can also be welded to the pins of the light emitting device 123 to fix the light emitting device 123.
  • the first voltage line VL1, the second voltage line VL2, the third voltage line VL3, the addressing line DL, the first connection line CL1, the second connection line CL2 and the first annular conductive structure 131 and the first conductive pattern 132 in the above-mentioned light-emitting substrate are all located in the first conductive layer 150.
  • the second voltage line VL2 , the third voltage line VL3 , the address line DL, the first connection line CL1 , the second connection line CL2 in the above-mentioned light-emitting substrate and the first voltage line VL1 and the third connection line CL3 in the first electrostatic path 130 are all located in the first conductive layer 150 .
  • the first voltage line VL1 , the third voltage line VL3 , the address line DL, the first connection line CL1 , the second connection line CL2 , the second voltage line VL2 in the first electrostatic path 130 , and the first conductive pattern 132 in the light emitting substrate are all located in the first conductive layer 150 .
  • the first voltage line VL1, the second voltage line VL2, the third voltage line VL3, the addressing line DL, the first connecting line CL1, the second connecting line CL2, the third voltage signal pin VP3, the third voltage signal pin VP3, the function pin FP, the floating pin RP, the second voltage signal pin group VP2, the first voltage signal pin group VP1 and the annular conductive structure in the second electrostatic path 140 in the above-mentioned light-emitting substrate are all located in the first conductive layer 150.
  • the antistatic capability of the light-emitting substrate 100 can be improved, and the charging and discharging phenomenon of the CDM model occurring during the preparation process of the light-emitting substrate can be avoided.
  • the first conductive layer 150 includes a plurality of patterns, including the above-mentioned first pad pattern, patterns for forming various signal lines (the signal lines include a first voltage line VL1, a second voltage line VL2, a third voltage line VL3, an addressing line DL, a first connection line CL1, a second connection line CL2, etc.), and a pattern for forming a first electrostatic path 130.
  • the signal lines include a first voltage line VL1, a second voltage line VL2, a third voltage line VL3, an addressing line DL, a first connection line CL1, a second connection line CL2, etc.
  • the preparation method of the first conductive layer 150 may include: forming a first conductive film 151 on one side of the substrate, placing a mask plate on the side of the first conductive film 151 away from the substrate, and etching the first conductive film 151 using a wet etching process to form the first conductive layer 150 including multiple patterns.
  • the wet etching process includes etching the first conductive film 151 using an etching solution.
  • the first electrostatic path 130 is provided so that the pattern ratio in the first conductive layer 150 (the pattern ratio here refers to the ratio of the total area of the various patterns in the first conductive layer 150 to the area of the first conductive film 151) is greatly improved, so that the amount of etching solution used can be greatly reduced, and the preparation cost of the light-emitting substrate is greatly reduced.
  • FIG. 14 (a) shows a schematic diagram of the pattern ratio of the first conductive layer 150' after the first conductive film 151 is prepared to form the first conductive layer 150' in an implementation mode
  • FIG. 14 (a) shows a schematic diagram of the pattern ratio of the first conductive layer 150' after the first conductive film 151 is prepared to form the first conductive layer 150' in an implementation mode
  • FIG. 14 (b) shows a schematic diagram of the pattern ratio of the first conductive layer 150 after the first conductive film 151 is prepared to form the first conductive layer 150 in some embodiments of the present disclosure. It can be seen that in the embodiments of the present disclosure, the pattern ratio of the first conductive layer 150 is greatly improved, and the pattern ratio of the first conductive layer 150 is increased from about 20% to 80%, so that the amount of etching solution used can be greatly reduced, and the preparation cost of the light-emitting substrate is greatly reduced.
  • the provision of the first electrostatic path increases the proportion of patterns in the first conductive layer 150, thereby allowing the first conductive layer 150 to have a larger contact area with other film layers (such as the passivation layer PVX or the buffer layer Bf mentioned below), so that the heat on the first conductive layer 150 can be transferred or diffused to other film layers, thereby improving the overall heat dissipation capacity of the light-emitting substrate 100, avoiding excessive temperatures of various patterns in the first conductive layer, and avoiding affecting the stability of signal transmission, etc., and avoiding affecting the function of the light-emitting substrate 100.
  • film layers such as the passivation layer PVX or the buffer layer Bf mentioned below
  • the light emitting substrate 100 further includes a buffer layer Bf located between the first conductive layer 150 and the substrate 110 , and a passivation layer PVX located on a side of the first conductive layer 150 away from the substrate 110 .
  • the material of the buffer layer Bf may be an inorganic material, such as silicon nitride, silicon oxide, etc.
  • the buffer layer B may protect the substrate 110 , so that the substrate 110 is not easily broken under the stress generated by the first conductive layer 150 .
  • the material of the passivation layer PVX may be an inorganic material, such as silicon nitride, silicon oxide, and the like.
  • the light emitting substrate 100 may include: a second conductive layer 160 and a third conductive layer 170 sequentially stacked on one side of the substrate 110 .
  • the third conductive layer 170 has a plurality of second pad patterns 171. At least two adjacent second pad patterns 171 form a second pad group.
  • the driver chip 121 includes at least two pins, and the light emitting device 123 includes two pins.
  • the second pad pattern of the second pad group is welded to the pins of the driver chip 121 to fix the driver chip 121.
  • the second pad pattern of the second pad group can also be welded to the pins of the light emitting device 123 to fix the light emitting device 123.
  • the second pad group is used to achieve electrical connection with the driving chip 121 or the light emitting device 123 .
  • the first voltage line VL1, the second voltage line VL2, the third voltage line VL3, and the third connecting line CL3 in the above-mentioned light-emitting substrate are all located in the second conductive layer 160
  • the addressing signal line DL is located in the third conductive layer 170
  • the second electrostatic path 140, the third voltage signal pin VP3, the third voltage signal pin VP3, the function pin FP, the floating pin RP, the second voltage signal pin group VP2, and the first voltage signal pin group VP1 in the above-mentioned light-emitting substrate are all located in the second conductive layer 160.
  • multiple signal lines for example, the first voltage line VL1, the second voltage line VL2, the third voltage line VL3, the third connection line CL3, the addressing signal line DL
  • the second pad pattern, and multiple pins are set on different conductive layers, which is conducive to optimizing the design method of multiple signal lines, the second pad pattern, and multiple pins, increasing the spacing between adjacent signal lines or adjacent pads or adjacent pins, and avoiding affecting the accuracy of the signals transmitted therefrom.
  • the inventors of the present disclosure tested and verified the anti-static capability of the solution of filling the device area with a conductive pattern, and the verification result is shown in FIG. 16 .
  • a single conductive layer means that the light-emitting substrate includes one conductive layer, such as the first conductive layer, and the pad pattern and the signal line pattern are located in the same conductive layer.
  • a double conductive layer means that the light-emitting substrate includes two conductive layers, such as the second conductive layer and the third conductive layer, and the pad pattern and the signal line pattern are located in different conductive layers.
  • the line width and length of the first voltage line VL1 in Design 1 are small, and the line width and length of the second voltage line VL2 are small, and the first voltage line VL1 and the second voltage line VL2 occupy a small area of the device area F0, that is, the pattern of the first conductive layer accounts for a small proportion.
  • the antistatic voltage value of the device area F0 of the light-emitting substrate is 15KV.
  • Design 2 increases the line width and length of the first voltage line VL1, and the line width and length of the second voltage line VL2, and the first voltage line VL1 and the second voltage line VL2 occupy a large filling area of the device area F0, that is, the pattern of the first conductive layer accounts for a large proportion.
  • the antistatic voltage value of the device area F0 of the light-emitting substrate is 17KV, which is higher than the antistatic ability of the device area F0 of the light-emitting substrate in Design 1.
  • the first voltage line VL1 and the second voltage line VL2 are both located in the second conductive layer closer to the substrate.
  • the line width and length of the first voltage line VL1 in Design Scheme 3, and the line width and length of the first voltage line of the second voltage line VL2, are relatively small, and the first voltage line VL1 and the second voltage line VL2 occupy a small area of the device area F0, that is, the pattern of the second conductive layer accounts for a small proportion.
  • the antistatic voltage value of the device area F0 of the light-emitting substrate is 15KV.
  • Design Scheme 4 increases the line width and length of the first voltage line VL1, and the line width and length of the second voltage line VL2, and the first voltage line VL1 and the second voltage line VL2 occupy a larger filling area of the device area F0, that is, the pattern of the second conductive layer accounts for a larger proportion.
  • the antistatic voltage value of the device area F0 of the light-emitting substrate is greater than 30KV, which is much higher than the antistatic ability of the device area F0 of the light-emitting substrate in Design Scheme 3.

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Abstract

一种发光基板（100），具有功能区（F）和绑定区（B）；绑定区（B）和功能区（F）沿第一方向依次排列；发光基板（100）包括：衬底（110）；多个功能元件组（120），位于衬底（110）的一侧；多个功能元件组（120）位于功能区（F）；第一静电通路（130），与多个功能元件组（120）位于衬底（110）的同一侧，第一静电通路（130）与绑定区（B）电连接，且第一静电通路（130）的一部分位于功能区（F）；第一静电通路（130）被配置为，将静电由功能区（F）导出至绑定区（B）。

Description

发光基板、背光模组及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种发光基板、背光模组及显示装置。
背景技术
发光二极管(LED)、次毫米发光二极管(Mini LED)或微米发光二极管(Micro LED)为主动自发光元器件。其中，Mini LED的尺寸约为80-500μm，MicroLED的尺寸约为小于80μm。
Mini LED可以用在背光和直显，一般为背光应用，通过大数量的密布，从而实现更小范围内的区域调光，对比于传统的背光设计，其能够在更小的混光距离内实现具备更好的亮度均匀性、更高的的色彩对比度，进而实现终端产品的超薄、高显色性、省电。同时，由于其设计能够搭配柔性基板，配合液晶显示面板(LCD)的曲面化也能够在保证画质的情况下实现类似有机发光二极管(OLED)的曲面显示。
Micro LED一般为RGB直显应用，能够克服正装芯片的搭线及可靠性的缺陷，同时结合COB(Chip on Board，板上芯片)或COG(Chip on Glass，玻璃上芯片)封装的优势，使显示屏点间距进一步缩小成为可能，对应的终端产品的视觉效果大幅提升，同时视距能够大幅减小，使得户内显示屏能够进一步取代原有的LCD市场。另一方面，搭配柔性基板的使用，也能够实现曲面的高画质显示效果，加上其自发光的特性，在一些特殊造型需求(如汽车显示)方面有极为广阔的市场。
发明内容
一方面，提供一种发光基板，具有功能区和绑定区。所述绑定区和所述功能区沿第一方向依次排列。所述发光基板包括：衬底；多个功能元件组，位于所述衬底的一侧；所述多个功能元件组位于所述功能区；第一静电通路，与所述多个功能元件组位于所述衬底的同一侧，所述第一静电通路与所述绑定区电连接，且所述第一静电通路的一部分位于所述功能区；所述第一静电通路被配置为，将静电由所述功能区导出至所述绑定区。
在一些实施例中，所述第一静电通路包括第一环状导电结构和至少一个第一导电图案；所述第一环状导电结构包括依次电连接的第一子段、第二子段和第三子段，所述第一子段和所述第二子段位于所述功能区沿第二方向的相对两侧，所述第三子段位于所述功能区远离所述绑定区的一侧；所述第一导电图案的至少一部分位于功能区，所述第一导电图案在所述衬底上的正投影与功能元件组在所述衬底上的正投影无交叠；其中，所述第一导电图案与所述第三子段电连接；所述第一方向与所述第二方向相交。
在一些实施例中，在第一导电图案的数量为多个的情况下，在所述第一方向上，相邻的两个第一导电图案之间电连接，最靠近所述第三子段的第一导电图案与所述第三子段电连接。
在一些实施例中，所述多个第一导电图案与所述第一环状导电结构材料相同且同层设置；所述第三子段，及与所述第三子段电连接的第一导电图案，呈一体结构。
在一些实施例中，所述第一静电通路还包括：多个桥接部；任一列第一导电图案中，相邻两个第一导电图案之间通过桥接部电连接。
在一些实施例中，所述多个桥接部中的至少一个为跨接电阻器。
在一些实施例中，功能元件组包括驱动芯片和至少一个发光器件组，所述发光器件组 包括至少两个发光器件；所述发光基板还包括：连接所述驱动芯片和所述发光器件组的第一连接线，及连接属于同一发光器件组中任意两个发光器件的第二连接线；所述多个第一导电图案在所述衬底上的正投影，与所述第一连接线和所述第二连接线在所述衬底上的正投影无交叠。
在一些实施例中，所述多个第一导电图案与所述第一连接线、所述第二连接线材料相同且同层设置。
在一些实施例中，所述第一静电通路包括多条第一电压线和至少一条第三连接线，所述多条第一电压线沿所述第一方向延伸，且沿第二方向间隔排布，第三连接线用于连接至少两条第一电压线。
在一些实施例中，所述第三连接线位于所述功能区远离所述绑定区的一侧。
在一些实施例中，沿所述第二方向，第(2i-1)条第一电压线及第2i条第一电压线，与同一条第三连接线连接；i为正整数。
在一些实施例中，沿第一方向排布的多个功能元件组与一条第一电压线连接。
在一些实施例中，在所述第三连接线的数量为多条的情况下，所述多条第三连接线相连接、呈一体结构。
在一些实施例中，所述多条第一电压线和所述多条第三连接线材料相同且同层设置。
在一些实施例中，所述多个功能元件组排列为多列；所述功能区包括多个器件区，一个功能元件组位于一个器件区；所述第一静电通路包括：多条第二电压线，一条第二电压线与一列功能元件组电连接；多个第二导电图案，所述多个第二导电图案在所述衬底上的正投影与所述功能元件组在所述衬底上的正投影无交叠；其中，第二导电图案与所述第二电压线电连接，且所述第二导电图案的至少一部分位于所述器件区。
在一些实施例中，所述多条第二电压线和所述多个第二导电图案材料相同且同层设置。
在一些实施例中，所述发光基板还包括：位于所述绑定区的多个功能引脚；第二静电通路，所述第二静电通路为环绕所述功能区的第二环状导电结构；所述第二环状导电结构包括依次电连接的第一子部、第二子部、第三子部和第四子部，所述第一子部和所述第二子部位于所述功能区沿第二方向的相对两侧，所述第三子部位于所述功能区远离所述绑定区的一侧，所述第四子部的一部分位于所述绑定区远离所述功能区的一侧；所述第二静电通路被配置为，将静电由所述功能区导出至所述绑定区；其中，所述多个功能引脚与，所述第四子部的位于所述绑定区远离所述功能区一侧的一部分电连接。
在一些实施例中，所述发光基板还包括位于所述绑定区的多个第二电压信号引脚组、多个第一电压信号引脚组以及多个浮空引脚，第二电压信号引脚组包括多个第二电压信号引脚，第一电压信号引脚组包括多个第一电压信号引脚。
在一些实施例中，至少一个浮空引脚与，所述第四子部的位于所述绑定区远离所述功能区一侧的一部分电连接。
在一些实施例中，多个所述第一电压信号引脚组与多个所述第二电压信号引脚组沿第二方向交替排布；任意相邻的所述第一电压信号引脚组与所述第二电压信号引脚组之间设置有至少一个所述浮空引脚。
在一些实施例中，与所述第四子部电连接的浮空引脚，及与所述浮空引脚相邻的第二电压信号引脚组的第二电压信号引脚之间，在所述第一方向上的间距的尺寸大于或等于200μm。
在一些实施例中，相邻的两个第一电压信号引脚之间的间距大于或等于100μm。
在一些实施例中，所述第二静电通路、所述多个功能引脚、所述多个浮空引脚、所述多个第二电压信号引脚组及所述多个第一电压信号引脚组的材料相同且同层设置。
另一方面，提供一种背光模组，包括：如上述任一实施例中所述的发光基板，以及位于所述发光基板的出光侧的光学膜片。
另一方面，提供一种显示装置，包括：如上述实施例中所述的背光模组；位于所述背光模组出光侧的阵列基板；以及，位于所述阵列基板远离所述背光模组一侧的彩膜基板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程等的限制。
图1a为根据本公开的一些实施例中的一种显示装置的结构图；
图1b为根据本公开的一些实施例中的另一种显示装置的结构图；
图2为根据本公开的一些实施例中的一种背光模组的结构图；
图3a为人体带电模型与充电器件带电模型对发光基板的放电电流及放电时间示意图；
图3b为一种实现方式中发光基板上防静电环线与驱动芯片和发光器件的排布方式的示意图；
图3c为一种在发光基板的覆膜制程中产生的充电器带电模型的静电的过程示意图；
图3d为图3c所对应的发光基板上积累的充电器件带电模型的静电的示意图；
图3e为一种实现方式中发光基板上的充电器件带电模型的静电发生静电击穿现象的示意图；
图4为根据本公开的一些实施例中的一种发光基板的结构图；
图5为根据本公开的一些实施例中的一种第一静电通路的结构图；
图6为根据本公开的一些实施例中的另一种发光基板的结构图；
图7为根据本公开的一些实施例中的另一种第一静电通路的结构图；
图8为根据本公开的一些实施例中的又一种第一静电通路的结构图；
图9a为一种实现方式中发光基板上静电的传导路径的示意图；
图9b为一种实现方式中发光基板发生爆灯不良的实物示意图；
图9c为根据本公开的一些实施例中的发光基板上静电传导路径的示意图；
图10为根据本公开的一些实施例中的一种第一静电通路的局部结构图；
图11为根据本公开的一些实施例中的一种第二静电通路的结构图；
图12a为根据本公开的一些实施例中的另一种第二静电通路的结构图；
图12b为图12a中B1区域的一种局部结构图；
图12c为图12a中B1区域的另一种局部结构图；
图12d为图12a中B2区域的一种局部结构图；
图12e为图12a中B2区域的另一种局部结构图；
图12f为图12a中B3区域的一种局部结构图；
图13为根据本公开的一些实施例中的又一种发光基板的结构图；
图14为根据本公开的一些实施例中发光基板的制备流程图；
图15为根据本公开的一些实施例中的又一种发光基板的结构图；
图16为根据本公开的一些实施例中的采用不同结构设计的发光基板的抗静电能力的对比图。
具体实施方式
面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相 近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的一些实施例提供了一种显示装置1。如图1a所示，该显示装置1可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字的还是图像的任何显示装置中。更明确地说，预期所述实施例的显示装置可实施应用在多种电子中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
示例性的，在上述显示装置1为大尺寸的显示装置的情况下，显示装置1可以包括多个子显示装置，多个子显示装置之间相互拼接形成大尺寸的显示装置，以满足大尺寸显示，该显示装置可以称为拼接显示装置。
在一些示例中，上述显示装置1可以为LCD(Liquid Crystal Display，液晶显示)显示装置。
在一些示例中，如图1b所示，显示装置1包括：背光模组10，位于背光模组10出光侧的阵列基板20，以及，位于阵列基板20远离背光模组10一侧的的彩膜基板30。
示例性的，上述背光模组10可以作为光源，用于提供背光。例如背光模组10提供的背光可以为白光或蓝光。
例如，背光模组10的出光侧，指的是，背光模组10发出光线的一侧。
示例性的，阵列基板20可以包括多个像素驱动电路、多个像素电极，该多个像素驱动电路例如呈阵列状排布。多个像素驱动电路与多个像素电极一一对应电连接，像素驱动电路为相应的像素电极提供像素电压。
示例性的，彩膜基板30可以包括多种彩色滤光片等。例如，在背光模组10提供的背光为白光的情况下，上述彩色滤光片可以包括红色滤光片、绿色滤光片和蓝色绿光片等。例如红色滤光片仅可以使得入射光线中的红光透过，绿色滤光片仅可以使得入射光线中的绿光透过，蓝色滤光片仅可以使得入射光线中的蓝光透过。又如，在在背光模组10提供的背光为蓝光的情况下，上述彩色滤光片可以包括红色滤光片和绿色滤光片等。
示例性的，彩膜基板30还包括：公共电极。公共电极可以接收公共电压。当然，该公共电极也可以设置在阵列基板20中，本公开对此不作限定。
在一些示例中，如图1b所示，显示装置1还包括：位于彩膜基板30与阵列基板20之间的液晶层40。
示例性的，液晶层40包括多个液晶分子。例如，在像素电极和公共电极之间可以形成电场，位于像素电极和公共电极之间的液晶分子可以在该电场的作用下，发生偏转。
可以理解的是，背光模组10所提供的背光，可以透过阵列基板20，入射至液晶层40的液晶分子。液晶分子在像素电极和公共电极之间形成的电场的作用下，发生翻转，从而改变透过液晶分子的光线的量，使得经液晶分子出射的光线达到预设亮度。上述光线穿过彩膜基板30中不同颜色的滤光片后出射。该出射的光线，包括各种颜色的光，例如红色光、绿色光、蓝色光等，各种颜色的光线相互配合，使得显示装置1实现显示。
示例性的，显示装置1中的背光模组10的类型有多种，可以根据实际情况进行设置，本公开对此不作限制。
例如，背光模组10可以为侧入式背光模组，背光模组10也可以为直下式背光模组。
为方便描述，本公开以下的实施例以背光模组10为直下式背光模组为例进行介绍。
在一些实施例中，如图2所示，背光模组10包括：发光基板100及位于发光基板100的出光侧的光学膜片200。
可以理解的是，图2中的Z指的是第三方向Z，第三方向Z为显示装置1的厚度方向。
示例性的，光学膜片200包括：依次层叠设置在发光基板100出光侧的扩散板210、量子点膜220、扩散片230和复合膜240等。
例如，扩散板210和扩散片230用于消除灯影，并将发光基板100发出的光线进行均匀化处理，提高光线的均一性。
例如，量子点膜220用于对发光基板100发出的光进行转换。可选地，在发光基板100发出的光为蓝光的情况下，量子点膜220可以将该蓝光转换为白光，并且提高该白光的纯度。
例如，复合膜240用于提高发光基板100发出的光线的亮度。
可以理解的是，发光基板100发出的光线，入射至上述光学膜片200后射出的光线的亮度得到增强，且射出的光线纯度更高，均匀性更好。
上述背光模组10可以包括多个发光基板100及与其对应的光学膜片，多个发光基板100可以互相拼接，相应的光学膜片也互相拼接，使得背光模组10具有较大的尺寸。此时，该背光模组10可以称为拼接显示模组，可以应用于上述拼接显示装置中。
在一些示例中，如图2所示，背光模组10还包括：设置在发光基板100与光学膜片200的扩散板210之间的支撑柱201。
示例性的，支撑柱201可以通过胶水固定在发光基板100上。支撑柱201可以用于支撑光学膜片200，并使得发光基板100发出的光获得一定的混光距离，从而可以进一步地消除灯影，提高光线的均匀性。
示例性的，示例性的，显示装置1还包括：框架、显示芯片以及其他电子配件等。
而在另一些示例中，显示装置1包括发光基板100，发光基板100直接用于显示画面。该显示装置常用在商业显示，例如交通管理指挥中心显示屏或商业广场显示屏等。
可以理解的是，在发光基板的使用过程中，不可避免的会与人体接触。人体因摩擦等原因带上一定静电后，与发光基板接触时会将静电传输至发光基板并通过发光基板放电。这种情况的放电模型为人体带电模型(Human Body Model，简称HBM)。其中人体的等效电阻为1500Ω，与发光基板接触后，在发光基板中进行的静电放电特点是(如图3a所示)，放电时间长，峰值电流较小，可以在几百纳秒内产生极高的瞬间放电电流，放电电流能达到数安培。目前已有较多的设计方案针对HBM模型的静电放电。一种实现方式是，在发光基板的边缘设置防静电环线，从而以及减少从发光基板的边缘窜入的静电，避免发生HBM模型的放电。图3b为一种实现方式中，发光基板上各信号线及驱动芯片IC和发光器件LED的相对排布方式，GND Ring为防静电环线，环绕驱动芯片IC和发光器件LED的外围。
此外，发光基板的制备过程一般包括对发光基板进行组装或运输过程。例如在发光基板的覆膜制程中，发光基板会接触到其他带电导体，进而该带电导体上的静电会传输至发光基板上，进而产生充电放电现象。该制备过程中产生的充电放电的模型为充电器件模型(Charged Device Model，简称CDM)。CDM模型的放电特点是放电电流上升时间短，大概为0.2ns～0.4ns，持续时间为6ns～8ns，但电流峰值极大，约为相同静电下HBM模型的15倍～20倍。以经验值1000V静电的CDM模型与5000V静电HBM脉冲关联对比(如图3a所示)，可以看到CDM模型的上升时间约为0.2ns，电流最高可达约21A，若是这种大电流并且快速放电脉冲泄放发生在发光基板内，很容易对发光基板的内部电路造成损伤，且该损伤常集中于发光基板的绑定区，以及功能区远离绑定区的一侧。例如，在覆膜制程中传导至发光基板而产生的静电的充电放电模型为CDM模型。如图3c及图3d所示，在该制程中，传输薄膜的滚轮(该滚轮一般由金属材料制成)及用于将该薄膜贴附的压辊(该滚轮一般由硅胶材料制成)，在与该薄膜的接触过程中，会不断摩擦从而产生大量的静电。携带该静电的薄膜在与发光基板相互贴附后，会将该静电注入到发光基板中。如图3e所示，在该静电在发光基板内累积到一定程度的情况下，该静电会将发光基板的焊盘电容器(相邻两个焊盘之间构成的电容器)或相邻的引脚电容器(相邻的两个引脚之间构成的电容器)击穿并放电，使得发光基板的焊盘受到损伤，影响发光基板的功能。且该损伤主要发生在功能区远离绑定区的一侧(也即发光基板的天侧)的电子元件所在的区域。由于CDM模型对发光基板的损伤程度远大于HBM，所以基于HBM模型的防静电设计方案不适用于CDM模型。
基于此，本公开提供一种发光基板100，如图4所示，发光基板100具有功能区F和绑定区B。绑定区B与功能区F沿第一方向X依次排列。
示例性的，绑定区B为实现发光基板100与显示芯片的绑定的区域。
示例性的，功能区B的形状有多种，可以根据实际情况进行选择，本公开对此不作限制。
例如，功能区F的形状可以为矩形，也可以为圆形等。
为方便示意，下面以功能区F的形状为矩形为例进行介绍。
在一些示例中，发光基板100包括：衬底110，以及多个功能元件组120。
在一些示例中，上述衬底110可以为柔性衬底。该柔性衬底例如可以为PET(Polyethylene Terephthalate，聚对苯二甲酸乙二醇酯)衬底、PEN(Polyethylene Naphthalate Two Formic Acid Glycol Ester，聚萘二甲酸乙二醇酯)衬底或PI(Polyimide，聚酰亚胺)衬 底等。
在另一些示例中，上述衬底110可以为刚性衬底。例如，该衬底的材料可以为玻璃等。上述衬底110也可以为印刷电路板(Printed Circuit Board，简称PCB)、铝基板等。
示例性的，功能元件组120位于衬底110的一侧；多个功能元件组120位于功能区F。
在一些示例中，功能元件组120可以包括多个微型电阻器或微型电容器等。
在另一些示例中，功能元件组120可以包括驱动芯片121和至少一个发光器件组122。发光器件组122包括至少两个发光器件123。
例如，功能元件组120可以包括驱动芯片121和一个发光器件组122。
又如，功能元件组120可以包括驱动芯片121和多个发光器件组122。
例如，发光器件组122可以包括两个发光器件123、四个发光器件123或六个发光器件123。
例如，同一个发光器件组122中的至少两个发光器件123通过串联方式相互连接。
示例性的，在驱动芯片121传输的驱动信号的控制下，发光器件组122实现发光。
示例性的，上述发光器件123可以为次毫米发光二极管(Mini Light Emitting Diode，简称Mini LED)。由于Mini LED的晶粒尺寸更小，可极大的缩短相邻Mini LED间的混光距离，使得发光基板具有区域亮度可调、高显色性、高对比度等优点。还可以使得发光基板100更加轻薄化、更省电，进而使得包括Mini LED的发光基板的应用更加灵活。此外，相比于OLED(Organic Light Emitting Diode，有机发光二极管，简称OLED)来说，包括Mini LED的发光基板的成本更低、寿命更长，烧屏的风险较小。
为描述方便，下面以功能元件组120可以包括驱动芯片121和至少一个发光器件组122为例进行介绍。
在一些示例中，如图4所示，发光基板100还包括：第一静电通路130。
示例性的，第一静电通路130与功能元件组120位于衬底110的同一侧，第一静电通路130与绑定区B连接，且第一静电通路130的一部分位于功能区F；第一静电通路130被配置为，将静电由功能区F导出至绑定区B。
例如，功能区F内功能元件组120上集聚的静电可以传导至第一静电通路130中位于功能区F的部分，然后通过第一静电通路130传导至绑定区B，进而可以避免静电在功能区F出现充电放电现象，避免该现象影响功能元件组120的功能。
本公开的实施例通过在发光基板100设置第一静电通路130，使得第一静电通路130与多个功能元件组位于衬底110的同一侧，且第一静电通路130与绑定区B连接，第一静电通路130的一部分位于功能区F，从而可以使得发光基板中功能区F的静电可以通过第一静电通路130导出至绑定区B，避免发光基板100的制备过程中产生的静电出现充电放电现象，避免影响功能元件组120及发光基板100的功能。
可以理解的是，第一静电通路130的设置方式有多种，可以根据实际需要进行设置，本公开对此不作限制。
在一些实施例中，如图4所示，第一静电通路130包括第一环状导电结构131和至少一个第一导电图案132；第一环状导电结构131包括依次电连接的第一子段131a、第二子段131b和第三子段131c，第一子段131a和第二子段131b位于功能区F沿第二方向Y的相对两侧，第三子段131c位于功能区F远离绑定区B的一侧；第一导电图案132的至少一部分位于功能区B。
例如，第一静电通路130包括第一环状导电结构131和一个第一导电图案132。
又如，第一静电通路130包括第一环状导电结构131和多个第一导电图案132。
在上述第一导电图案132的数量为多个的情况下，多个第一导电图案132呈阵列状排布，例如，多个第一导电图案132沿第一方向X排列为多行，沿第二方向Y排列为多列。
示例性的，上述第一环状导电结构131可以为非严格意义的环状，可以为环状的一部分。
在功能区F为矩形的情况下，上述第一环状导电结构131为方环的一部分。
示例性的，第三子段131c位于功能区F远离绑定区B的一侧，也即第三子段131c位于发光基板100的天侧。
示例性的，发光基板100还具有周边区D。周边区D围绕上述功能区F。
示例性的，上述第一环状导电结构131中的第一子段131a、第二子段131b和第三子段131c可以位于周边区D。
例如，第一导电图案132的一部分位于功能区B，第一导电图案132的另一部分位于周边区D。
又如，第一导电图案132整体位于功能区B。
在一些示例中，第一导电图案132在衬底110上的正投影与功能元件组120在衬底110上的正投影无交叠。
示例性的，第一导电图案132在衬底110上的正投影与功能元件组120在衬底110上的正投影，没有重合的部分。且第一导电图案132在衬底110上的正投影的边界线，与功能元件组120在衬底110上的正投影的边界线，无交叉。
例如，第一导电图案132位于相邻的多个功能元件组120之间的间隙区域。
示例性的，上述第一方向X与第二方向Y相交。
例如，第一方向X与第二方向Y之间的夹角可以为80°、85°、90°或95°。
在一些示例中，第一导电图案132与第三子段131c电连接。
示例性的，在第一导电图案132的数量为多个，且多个第一导电图案132沿第一方向X排列为多行的情况下，最靠近第三子段131c的一行第一导电图案132中的每个第一导电图案132的一端均与第三子段131c电连接。且该行第一导电图案132中的每个第一导电图案132均部分位于功能区F，部分位于周边区D。
采用上述设置方式，在发光基板制备过程中发生静电电荷累积的情况下，静电会经过至少一个第一导电图案132传导至与其电连接的第三子段131c，继续传导至第一子段131a或第二子段131b，从而传导至绑定区B，使得发光基板的静电由功能区F传导至绑定区B，进而避免静电在功能区F积累，避免该静电积累至一定程度对功能元件组120中的发光器件123或驱动芯片121的损伤，进而避免影响功能元件组120的功能，提高发光基板的抗静电能力，提高制备发光基板的良品率。
在一些示例中，如图5所示，在第一导电图案132的数量为多个的情况下，在第一方向X上，相邻的两个第一导电图案132之间电连接，最靠近第三子段131c的第一导电图案132与第三子段131c电连接。
示例性的，一列第一导电图案132中相邻的两个第一导电图案132电连接，且沿第一方向X上，每列第一导电图案132中的第一个第一导电图案132与第三子段131c电连接，从而使得每个第一导电图案132均与第三子段131c直接或间接电连接。
采用上述设置方式，可以使得功能区F的静电均能通过第一静电通路中的第一导电图案132导出至绑定区B，进而可以避免静电积累对功能元件组的功能的影响，提高发光基板的抗静电能力，提高制备发光基板的良品率。
示例性的，在第二方向Y上，相邻两个第一导电图案132之间也可以电连接。
在一些示例中，多个第一导电图案132与第一环状导电结构131材料相同且同层设置。
示例性的，第一导电图案132的材料可以为金属材料，例如为铜。
上述“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
采用上述设置，多个第一导电图案132与第一环状导电结构131同层设置，在第一导电图案132与第三子段131c电连接，且第一导电图案132与该第三子段131c之间没有其他结构的情况下，可以使得第一导电图案132与第三子段131c的电连接无需跨过其他膜层，直接在同层即可实现，进而可以简化发光基板的制备流程。
示例性的，第三子段131c，及与第三子段131c电连接的第一导电图案132，呈一体结构。
上述“一体结构”指的是，相连接的两个图案同层设置，且该两个图案是连续的，未分隔开。上述设置方式，可以使得该第三子段131c及与其电连接的第一导电图案132可以在一次构图工艺中形成，进而可以简化发光基板的制备工艺。此外，该“一体结构”的设置，能够提高第三子段131c与第一导电图案132之间电连接的可靠，并且无需设置其他导电结构，降低了发光基板的制备成本。
在一些示例中，第一静电通路130还包括：多个桥接部133。任一列第一导电图案132中，相邻两个第一导电图案132之间通过桥接部133电连接。
可以理解的是，桥接部133起到导电的作用。桥接部133位于功能区F。
示例性的，桥接部133为导电材料制作，桥接部133也可以为电学元器，例如电阻或者电容等。多个桥接部133可以均为导电材料，也可以部分桥接部133为电学元件，部分桥接部133为导电材料，仅起到电连接的作用。
例如，多个桥接部133与多个功能元件组120位于衬底110的同一侧，且该多个桥接部133位于第一导电图案132远离衬底110的一侧。
在一些示例中，多个桥接部133中的至少一个为跨接电阻器133a。
可以理解地，跨接电阻器133a是一种特殊用途的电阻，跨接电阻器133a的电阻值很小，并非完全为零。可以采用自动贴片机或自动插件机将跨接电阻器133a设置在发光基板100中无法通过线路直接连接的两点之间，以实现两点的电连接。因此，设置多个桥接部133中的至少一个为跨接电阻器133a，能够提高发光基板100的加工便捷性，降低发光基板100的成本。
示例性的，多个桥接部133可以均为跨接电阻器。或者，多个桥接部133中的一部分(一个或者更多个)为跨接电阻器。
在一些示例中，如图4所示，发光基板100还包括：连接驱动芯片121和发光器件组122的第一连接线CL1，及连接属于同一发光器件组122中任意两个发光器件123的第二连接线CL2。
例如，在发光器件组122包括两个发光器件123的情况下，同一个发光器件组122中具有一条第二连接线CL2。
又如，在发光器件组122包括六个发光器件123的情况下，同一个发光器件组122中具有五条第二连接线CL2。
可以理解的是，第二连接线CL2的排布方式，与发光器件组122中各个发光器件123的排布方式有关。例如，在发光器件组122包括六个发光器件123的情况下，六个发光器件123之间串联，六个发光器件123沿第一方向X排列为两行，沿第二方向Y排列为三列，相邻的两个第二连接线CL2分别沿第一方向X和第二方向Y延伸，发光器件组122及多个第二连接线CL2在衬底上的正投影轮廓呈凹凸状。
示例性的，多个第一导电图案132在衬底110上的正投影，与第一连接线CL1和第二连接线CL2在衬底110上的正投影无交叠。也就是说，多个第一导电图案132与第一连接线CL1和第二连接线CL2没有相互覆盖的部分。
例如，多个第一导电图案132在衬底110上的正投影，与第一连接线CL1和第二连接线CL2在衬底110上的正投影之间没有重合的部分。
示例性的，沿第一方向X，第一导电图案132在衬底110上的正投影形状，与相邻两个发光器件组122所围成的区域形状，相同。
例如，一个第一导电图案132可以位于沿第一方向X上相邻两个发光器件组122之间。一个第一导电图案132也可以位于沿第一方向X上相邻两个功能元件组120之间。一个第一导电图案132也可以位于最靠近第三子段131c的功能元件组120与该第三子段131c之间。
例如，沿第一方向X，第一导电图案132在衬底110上的正投影的面积，可以小于相邻两个发光器件组122所围成的区域的面积。
例如，沿第一方向X，第一导电图案132可以几乎填满相邻两个发光器件组122所围成的区域。或者，沿第一方向X，第一导电图案132可以填充相邻两个发光器件组122所围成的区域的一部分。
在一些示例中，多个第一导电图案132与第一连接线CL1、第二连接线CL2材料相同且同层设置。
示例性的，第一连接线CL1的材料可以为金属材料，例如为铜。
采用上述设置方式，可以使得第一导电图案132、第一连接线CL1、第二连接线CL2可以在一次构图工艺中形成，从而可以简化发光基板100的制备工艺。
在另一些实施例中，如图6所示，第一静电通路130包括多条第一电压线VL1和至少一条第三连接线CL3，多条第一电压线VL1沿第一方向X延伸，且沿第二方向Y间隔排布，第三连接线CL3用于连接至少两条第一电压线VL1。
可以理解的是，图6中的H为过孔，例如驱动芯片121的引脚穿过该过孔与信号线(例如第一电压线VL1、数据线DL等)电连接，或者，发光器件组122的引脚穿过该过孔与第二电压信号线VL2电连接。
在一些示例中，沿第一方向X排布的多个功能元件组120与一条第一电压线VL1连接。
示例性的，第一电压线VL1位于功能区F，一条第一电压线VL1与一列功能元件组120电连接，且第一电压线VL1延伸至绑定区B，第一电压线VL1与绑定区B(例如下文 中提到的第一电压信号引脚组)电连接，可以将来自显示芯片的信号传输至功能元件组120。
例如，第一电压信号线VL1传输的第一电压信号可以为恒压信号。第一电压信号线VL1可以与驱动芯片121电连接，通过该驱动芯片121为相应的同一个功能元件组120的发光器件组122中的多个发光器件123提供第一电压信号，该第一电压信号可以是功能元件组120的接地电压信号。
例如，第一静电通路130可以包括一条第三连接线CL3。
又如，第一静电通路130可以包括多条第三连接线CL3，多条相邻的第三连接线CL3之间可以不连接。
又如，第一静电通路130可以包括多条第三连接线CL3，多条相邻的第三连接线CL3之间可以相互连接。
例如，一条第三连接线CL3可以用于连接两条第一电压线VL1。
又如，一条第三连接线CL3可以用于连接多条第一电压线VL1。
采用上述设置方式，在相邻两列功能元件组120之间具有静电积累的情况下，该静电可以通过第一电压线VL1及第三连接线CL3传输至绑定区B，从而可以避免静电在相邻两列功能元件组120之间传输，避免由第一电压信号线VL1传输至发光器件123，进而避免由发光器件123沿第一连接线CL1传输至驱动芯片121，避免影响驱动芯片121传输至发光器件123的信号的准确性，避免该发光器件出现爆灯不良的情况，从而可以提高发光基板的抗静电能力，尤其是CDM模型的充电放电现象。
在一些示例中，如图7所示，第三连接线CL3位于功能区F远离绑定区B的一侧。由此，可以极大地增强功能区F远离绑定区B的位置处(也即发光基板的天侧)的抗静电能力，避免靠近天侧位置处的功能元件组120的功能受损。
示例性的，如图8所示，发光基板100还包括：多条寻址信号线DL。
例如，沿第一方向X，多条寻址信号线DL连接相邻两个功能元件组120的两个驱动芯片121。沿第二方向Y，第(2i-1)列功能元件组120中最靠近天侧的功能元件组，与第2i列功能元件组120中最靠近天侧的功能元件组，通过一条寻址信号线DL连接。
在一些示例中，如图8所示，沿第二方向Y，第(2i-1)条第一电压线VL1及第2i条第一电压线VL1，与同一条第三连接线CL3连接；i为正整数。
采用上述设置方式，在发光基板中产生静电的情况下，静电可以随着第(2i-1)条第一电压线VL1、第2i条第一电压线VL1及相应的第三连接线CL3传输，从而提高发光基板的抗静电能力，提高发光基板的良品率，进而可以避免静电沿着上述第(2i-1)个功能元件组120、及相应的寻址信号线DL和第2i个功能元件组120传输至功能元件组120中的驱动芯片121，进而避免使得该静电大于12kV，避免该静电对驱动芯片121的损伤，避免使得该驱动芯片121控制的发光器件组122发生爆灯不良的现象。
可以理解的是，图9a所示的是一种实现方式中，发光基板上静电的传输方式。图9a中的带箭头的虚线所示的路径为静电的传输路径。在发光基板的制备过程中，静电传导至发光基板上，沿着GND线传输。由于奇数列的GND线与偶数列的GND线通过寻址信号线连接驱动芯片，上述静电会经寻址信号线传输至驱动芯片。当该静电大于12KV的情况下，驱动芯片被击伤，驱动芯片IC与寻址信号线的连接引脚(图中的Do及Di)被击穿进而对地漏电，从而使得该驱动芯片IC控制的灯区Zone2-1的发光器件(图中的LED1～LED9)出现爆灯不良现象，具体爆灯不良情况请参考实物图图9b。图9b中，三个方形虚线框圈 住的区域为发生爆灯不良的三个灯区Zone。
而本公开的实施例中，设置沿第二方向Y，第(2i-1)条第一电压线VL1及第2i条第一电压线VL1，与同一条第三连接线CL3连接，使得发光基板上静电的传输路径方式变化(如图9c所示)，静电在第一静电通路130的第一电压线VL1上传输，从而可以提高发光基板的抗静电能力，避免静电传输至驱动芯片121，进而避免驱动芯片121的引脚被击穿，避免发光基板出现的爆灯不良现象。
在一些示例中，如图7所示，在第三连接线CL3的数量为多条的情况下，多条第三连接线CL3相连接、呈一体结构。
例如，上述设置可以是相邻两条第三连接线CL3相连接、呈一体结构。上述设置也可以是相邻的多条第三连接线CL3相连接、呈一体结构。
采用上述设置方式，可以使得多条第三连接线CL3在一次构图工艺中形成，从而可以简化发光基板100的制备工艺。
在一些示例中，多条第一电压线VL1和多条第三连接线材料CL3相同且同层设置。
示例性的，第三连接线CL3的材料可以为金属，例如该金属可以为铜。
上述“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
采用上述设置，在第一电压线VL1与第三连接线材料CL3电连接的情况下，且第一电压线VL1与第三连接线材料CL3之间不存在其他结构的情况下，可以使得第一电压线VL1与第三连接线材料CL3的电连接无需跨过其他膜层，直接在同层即可实现，进而可以简化发光基板的制备流程。
示例性的，第三连接线CL3，及与其电连接的第一电压线VL1，呈一体结构。由此，可以使得该第三连接线CL3及与其电连接的第一电压线VL1可以在一次构图工艺中形成，进而可以简化发光基板的制备工艺。此外，该“一体结构”的设置，能够提高第三连接线CL3与第一电压线VL1之间电连接的可靠，并且无需设置其他导电结构，降低了发光基板的制备成本。
在一些示例中，如图9c所示，多个功能元件组120排列为多列。功能区F包括多个器件区F0，一个功能元件组120位于一个器件区F0。
示例性的，多个器件区F0呈阵列状排布。
示例性的，第一静电通路130包括：多条第二电压线VL2。一条第二电压线VL2与一列功能元件组120电连接。
例如，第二电压线VL2沿第一方向X延伸。
例如，第二电压线VL2与一列功能元件组120的发光器件组122的一端电连接。第二电压线VL2还与绑定区B电连接，第二电压信号线VL2用于向发光器件组122提供第二电压信号。第二电压信号可以是发光器件组122的器件电源电压信号。
示例性的，如图10所示，第一静电通路130还包括：多个第二导电图案134。多个第二导电图案134在衬底110上的正投影与功能元件组120在衬底110上的正投影无交叠。
例如，多个第二导电图案134在衬底110上的正投影，与功能元件组120在衬底110上的正投影之间没有重合的部分。也就是说，多个第二导电图案134与多个功能元件组120 没有相互覆盖的部分。
当然，多个第二导电图案134在衬底110上的正投影，与多个功能元件组120中的第一连接线CL1和第二连接线CL2在衬底110上的正投影也无交叠。多个第二导电图案134与第一连接线CL1及第二连接线CL2没有相互覆盖或遮挡的部分。
示例性的，沿第一方向X，第二导电图案134在衬底110上的正投影形状，与相邻两个发光器件组122所围成的区域形状，相同。
例如，沿第一方向X，第二导电图案134在衬底110上的正投影的面积，可以小于相邻两个发光器件组122所围成的区域的面积。
例如，沿第一方向X，第二导电图案134可以填满相邻两个发光器件组122所围成的区域。或者，沿第一方向X，第二导电图案134可以填充相邻两个发光器件组122所围成的区域的一部分。
示例性的，第二导电图案134与第二电压线VL2电连接，且第二导电图案134的至少一部分位于器件区F0。
例如，第二导电图案134的一部分可以位于一个器件区F0，该第二导电图案134的另一部分可以位于相邻的另一个器件区F0。该第二导电图案134可以位于沿第一方向X上相邻两个功能元件组120之间。
又如，第二导电图案134整体的位于一个器件区F0。该第二导电图案134可以位于沿第一方向X上相邻两个发光器件组122之间。
又如，第二导电图案134的一部分位于器件区F0，而该第二导电图案134的另一部分，可以位于最靠近第三子段131c的功能元件组120与第三子段131c之间的区域。
当然，第二导电图案134也可以位于相邻两个器件区F0之间的区域。
采用上述设置方式，在发光基板的制备过程中产生的静电可以通过第二导电图案134传导至第二电压线VL2，再经由第二电压线VL2传导至绑定区B，从而使得静电由功能区F传导至绑定区B，提高发光基板的抗静电能力，进而避免静电在功能区F积累，进而避免静电造成功能区F中功能元件组120的焊盘等击穿，避免造成爆灯不良现象。
示例性的，多个第二导电图案134可以排列为多行多列。一条第二电压线VL2可以与一列第二导电图案134中的多个第二导电图案134电连接。
示例性的，多条第二电压线VL2和多个第二导电图案134材料相同且同层设置。
示例性的，第二导电图案134的材料可以为金属，例如该金属可以为铜。
上述“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
采用上述设置，在第二电压线VL2和多个第二导电图案134电连接的情况下，且第二电压线VL2和多个第二导电图案134之间不存在其他结构的情况下，可以使得第二电压线VL2和多个第二导电图案134的电连接无需跨过其他膜层，直接在同层即可实现，进而可以简化发光基板的制备流程。
示例性的，第二电压线VL2，及与其电连接的多个第二导电图案134，呈一体结构。由此，可以使得该第二电压线VL2及与其电连接的第二导电图案134可以在一次构图工艺中形成，进而可以简化发光基板的制备工艺。此外，该“一体结构”的设置，能够提高第 二电压线VL2与第二导电图案134之间电连接的可靠，并且无需设置其他导电结构，降低了发光基板的制备成本。
在一些示例中，如图11所示，发光基板100，还包括：位于绑定区B的多个功能引脚FP以及第二静电通路140。
示例性的，第二静电通路140为环绕功能区F的第二环状导电结构。该第二环状导电结构包括依次电连接的第一子部141、第二子部142、第三子部143和第四子部144，第一子部141和第二子部142位于功能区F沿第二方向Y的相对两侧，第三子部143位于功能区F远离绑定区B的一侧，第四子部144的一部分位于绑定区B远离功能区F的一侧。
例如，第四子部144包括第一部分144a、第二部分144b及第三部分144c。第四子部144的第一部分144a与第三子部143电连接，第三部分144c与第一子部141电连接，第三部分144c位于绑定区B远离功能区F的一侧。第一部分144a、第二部分144b及第三部分144c均沿第二方向Y延伸，且沿第二方向Y，第一部分144a、第三部分144c及第二部分144b依次排列，且未连接。
示例性的，多个功能引脚FP与，第四子部144的位于绑定区B远离功能区F一侧的一部分电连接。
例如，多个功能引脚FP与第四子部144的第三部分144c及第一部分144a电连接，多个功能引脚FB与第四子部144的第三部分144c及第二部分144b电连接，从而实现第四子部144的第一部分144a、第三部分144c、第二部分144b的电连接，使得第二静电通路140成为闭合环状的形状。
示例性的，第二静电通路140被配置为，将静电由功能区F导出至绑定区B。
采用上述设置方式，在发光基板100中设置第二静电通路140，第二静电通路140为环状导电结构，从而使得发光基板100中功能区F产生的静电可以通过该第二静电通路140导出至绑定区B，进而可以避免静电在功能区F积累，进而避免静电造成功能区F中功能元件组120的焊盘等击穿，避免造成爆灯不良现象。此外，第四子部144的设置，使得发光基板100未与显示芯片绑定前，第四子部144与第一子部141、第二子部142、第三子部143通过功能引脚FP形成闭合的环路，进而可以将发光基板在制备过程中产生的静电传导至该闭合环路，提高发光基板的良品率，避免该静电造成的驱动芯片的损伤等。
在一些示例中，如图12a所示，发光基板100还包括：位于绑定区B的多个浮空引脚(Dummy Pin)RP。
示例性的，至少一个浮空引脚RP与，第四子部144的位于绑定区B远离功能区F一侧的一部分电连接。
例如，一个浮空引脚RP与，第四子部144的位于绑定区B远离功能区F一侧的一部分电连接。
又如，多个浮空引脚RP与，第四子部144的位于绑定区B远离功能区F一侧的一部分电连接。
采用上述设置方式，可以使得发光基板100上的静电可以通过浮空引脚RP传导至第二静电通路140，从而增加了功能区F内静电的导出路径，从而提高了发光基板的抗静电能力。
在一些示例中，如图12b～图12f所示，发光基板100还包括位于绑定区B的多个第一电压信号引脚组VP1和多个第二电压信号引脚组VP2，第二电压信号引脚组VP2包括多 个第二电压信号引脚，第一电压信号引脚组VP1包括多个第一电压信号引脚。
示例性的，第一电压信号引脚组VP1的多个第一电压信号引脚之间具有间隔，且，多个第一电压信号引脚排列为一行。第二电压信号引脚组VP2的多个第二电压信号引脚之间具有间隔，且，多个第二电压信号引脚排列为一行。多个第一电压信号引脚组VP1和多个第二电压信号引脚组VP2排列为一行。
示例性的，第一电压信号引脚可以与至少一个第一电压线VL1电连接，第二电压信号引脚可以与至少一个第二电压线VL2电连接。
可以理解的是，在发光基板与显示芯片绑定的过程中，上述第一电压信号引脚可以与显示芯片电连接，从而可以接收显示芯片传输的第一电压信号，并将该第一电压信号传输至相应的第一电压线VL1。上述第二电压信号引脚可以与显示芯片电连接，从而可以接收显示芯片传输的第二电压信号，并将该第二电压信号传输至相应的第二电压线VL2。
示例性的，多个第一电压信号引脚组VP1与多个第二电压信号引脚组VP2沿第二方向Y交替排布；任意相邻的第一电压信号引脚组VP1与第二电压信号引脚组VP2之间设置有至少一个浮空引脚RP。
示例性的，相邻的第二电压信号引脚组VP2和第一电压信号引脚组VP1之间设置有至少一个浮空引脚RP。或者，相邻的第一电压信号引脚组VP1和第二电压信号引脚组VP2之间设置有至少一个浮空引脚RP。
例如，第二电压信号引脚组VP2和第一电压信号引脚组VP1之间设置有一个浮空引脚RP。
又如，第二电压信号引脚组VP2和第一电压信号引脚组VP1之间设置有多个浮空引脚RP。
采用上述设置方式，可以使得发光基板上的静电传导至浮空引脚RP，使得静电可以通过浮空引脚RP传导至第二静电通路140上，从而实现静电的导出，提高发光基板100的抗静电能力，从而避免发光基板上的静电传导至相邻的第二电压信号引脚组VP2和第一电压信号引脚组VP1，避免该静电在相邻的第二电压信号引脚组VP2和第一电压信号引脚组VP1上积累，进而避免该静电击穿相邻的第二电压信号引脚及第一电压信号引脚，避免发光基板100出现爆灯不良现象。
可以理解的是，如图12d所示，未与第四子部144电连接的浮空引脚RP，可以用于防止位于该浮空引脚RP左右两侧的第二电压信号引脚组VP2与地址引脚DP之间的信号的干扰，从而可以提高第二电压信号引脚组VP2所传输的第二电压信号的准确性，以及地址引脚DP传输的地址信号的准确性，从而提高发光基板的性能。
示例性，如图12b所示，浮空引脚RP也可以位于功能引脚FP远离第二电压引脚组VP2的一侧，也可以位于第二电压引脚组VP2与数据引脚DP之间。
在一些示例中，与第四子部144电连接的浮空引脚RP，及与该浮空引脚RP相邻的第二电压信号引脚组VP2的第二电压信号引脚之间，在第二方向Y上的间距的尺寸大于或等于200μm。
例如，与第四子部144电连接的浮空引脚RP，及与浮空引脚RP相邻的第二电压信号引脚组VP2的第二电压信号引脚之间，在第二方向Y上的间距的尺寸为200μm。
又如，与第四子部144电连接的浮空引脚RP，及与浮空引脚RP相邻的第二电压信号引脚组VP2的第二电压信号引脚之间，在第二方向Y上的间距的尺寸为210μm、220μm、 230μm、240μm或250μm。
采用上述设置方式，可以提高第二电压信号引脚所传输的第二电压信号的准确性，实现显示芯片对功能元件组中的发光器件的精准控制，避免浮空引脚RP与相邻的第二电压信号引脚之间的间距过小，避免浮空引脚RP上的静电，对相邻的第二电压信号引脚所传输的第二电压信号的干扰或影响，进而避免对功能元件组120中的发光器件123的影响。
在一些示例中，相邻的两个第一电压信号引脚之间的间距大于或等于100μm。
例如，相邻的两个第一电压信号引脚之间的间距为100μm、105μm、110μm、112μm或115μm。
采用上述设置方式，可以使得相邻的两个第一电压信号引脚之间的间距较大，提高第一电压信号引脚所传输的第一电压信号的准确性，实现显示芯片对功能元件组中的发光器件的精准控制，避免相邻的第一电压信号引脚之间的间距过小，避免影响第一电压信号引脚与显示芯片的绑定效果，进而避免第一电压信号引脚与显示芯片之间的短接。
在一些示例中，第二静电通路140、多个功能引脚FP、多个浮空引脚RP、多个第二电压信号引脚组VP2及多个第一电压信号引脚组VP1的材料相同且同层设置。
示例性的，功能引脚FP的材料可以为金属材料，例如为铜。
采用上述设置方式，可以使得二静电通路140、多个功能引脚FP、多个浮空引脚RP、多个第二电压信号引脚组VP2及多个第一电压信号引脚组VP1可以在一次构图工艺中形成，进而可以简化发光基板的制备工艺。
示例性的，第二静电通路140，及与其电连接的多个功能引脚FP、多个浮空引脚RP，呈一体结构。
上述“一体结构”指的是，相连接的两个图案同层设置，且该两个图案是连续的，未分隔开。上述设置方式，可以使得该第二静电通路140，及与其电连接的多个功能引脚FP、多个浮空引脚RP可以在一次构图工艺中形成，进而可以简化发光基板的制备工艺。此外，该“一体结构”的设置，能够提高第二静电通路140与多个功能引脚FP、多个浮空引脚RP之间电连接的可靠，并且无需设置其他导电结构，降低了发光基板的制备成本。
可以理解的是，首先，如图4所示，发光基板100还包括：多条第三电压线VL3和多条数据线SL。第三电压线VL3沿第一方向X延伸，多个第三电压线VL3沿第二方向Y间隔排布。一条第三电压线VL3与一列功能元件组120中的驱动芯片121电连接。数据线SL沿第一方向X延伸，多个数据线SL沿第二方向Y间隔排布。一条数据线SL与一列功能元件组120中的驱动芯片121电连接，且该数据线SL向相应的驱动芯片121传输数据信号。
示例性的，如图12b所示，发光基板100还包括：位于绑定区B的多个寻址引脚DP和多个第三电压信号引脚VP3。
例如，第三电压线VL3与绑定区B的第三电压信号引脚VP3电连接。第三电压信号引脚VP3用于接收来自显示芯片的第三电压信号，并将该第三电压信号依次至第三电压线VL3、驱动芯片121。上述第三电压信号可以为恒压信号，例如第三电压信号可以是驱动芯片121的器件电源电压信号。
例如，上述寻址信号线DL与绑定区B的寻址引脚DP电连接。寻址引脚DP用于接收来自显示芯片的地址信号，并将该地址信号依次传输至地址信号线DL、驱动芯片121。
示例性的，位于绑定区B的第三电压信号引脚VP3、第三电压信号引脚VP3、多个功 能引脚FP、多个浮空引脚RP、多个第二电压信号引脚组VP2及多个第一电压信号引脚组VP1的相对位置关系有多种，可以根据实际情况进行设置，本公开对此不作限制。
例如，第三电压信号引脚VP3、第三电压信号引脚VP3、多个功能引脚FP、多个浮空引脚RP、多个第二电压信号引脚组VP2及多个第一电压信号引脚组VP1，沿第二方向Y排列为一行。如图12d所示，各个引脚从左到右按照至少一个浮空引脚RP、功能引脚FP、第二电压信号引脚组VP2、至少一个浮空引脚RP、地址引脚DP、第一电压信号引脚组VP1的顺序周期性循环。
其次，在一些实施例中，如图13所示，上述发光基板100可以包括：位于衬底110一侧的第一导电层150。第一导电层150的材料可以包括金属材料，例如铜。
示例性的，该第一导电层150中具有多个第一焊盘图案。相邻的至少两个第一焊盘图案构成一个第一焊盘组。
可以理解的，驱动芯片121至少包括两个引脚，发光器件123包括两个引脚。第一焊盘组的第一焊盘图案，与驱动芯片121的引脚进行焊接，实现驱动芯片121的固定。第一焊盘组的第一焊盘图案，也可以与发光器件123的引脚进行焊接，实现发光器件123的固定。
例如，上述发光基板中的第一电压线VL1、第二电压线VL2、第三电压线VL3、寻址线DL、第一连接线CL1、第二连接线CL2及第一静电通路130中的第一环状导电结构131、第一导电图案132均位于第一导电层150。
又如，上述发光基板中的第二电压线VL2、第三电压线VL3、寻址线DL、第一连接线CL1、第二连接线CL2及第一静电通路130中的第一电压线VL1、第三连接线CL3均位于第一导电层150。
又如，上述发光基板中的第一电压线VL1、第三电压线VL3、寻址线DL、第一连接线CL1、第二连接线CL2及第一静电通路130中第二电压线VL2、第一导电图案132均位于第一导电层150。
又如，上述发光基板中的第一电压线VL1、第二电压线VL2、第三电压线VL3、寻址线DL、第一连接线CL1、第二连接线CL2、第三电压信号引脚VP3、第三电压信号引脚VP3、功能引脚FP、浮空引脚RP、第二电压信号引脚组VP2、第一电压信号引脚组VP1及第二静电通路140中的环状导电结构均位于第一导电层150。
采用上述设置方式，可以提高发光基板100的抗静电能力，避免发光基板在制备过程中出现的CDM模型的充电放电现象。
示例性的，第一导电层150上包括多种图案，该图案包括上述第一焊盘图案、形成各种信号线(该信号线包括第一电压线VL1、第二电压线VL2、第三电压线VL3、寻址线DL、第一连接线CL1、第二连接线CL2等)的图案、形成第一静电通路130的图案。
例如，第一导电层150的制备方法可以包括：在衬底的一侧形成第一导电薄膜151，在第一导电薄膜151远离衬底的一侧放置掩膜板，采用湿法刻蚀工艺对第一导电薄膜151进行刻蚀，形成包括多种图案的上述第一导电层150。上述湿法刻蚀工艺包括采用刻蚀液对第一导电薄膜151进行刻蚀。
本公开的一些实施例中，第一静电通路130的设置，使得第一导电层150中的图案占比(此处的图案占比指的是上述第一导电层150中的多种图案的总面积，在第一导电薄膜151的面积中所占的比例)得到极大的提升，从而可以大大减少刻蚀液的用量，极大地降 低了发光基板的制备成本。图14中(a)所示的是一种实现方式中，由第一导电薄膜151制备形成第一导电层150’后，第一导电层150’的图案占比示意图，图14中(b)所示的是本公开的一些实施例中由第一导电薄膜151制备形成第一导电层150后，第一导电层150的图案占比示意图。可见，本公开的实施例中，第一导电层150的图案占比得到了极大的提高，第一导电层150的图案占比大约由20％提升至80％，从而可以大大减少刻蚀液的用量，极大地降低了发光基板的制备成本。
此外，本公开的一些实施例中，第一静电通路的设置，使得第一导电层150中的图案占比得到提升，进而可以使得第一导电层150与其他膜层(例如下文中的钝化层PVX或缓冲层Bf)的接触面积较大，从而可以使得第一导电层150上的热量可以较多的转移或扩散至其他膜层上，提高发光基板100整体的散热能力，可以避免第一导电层中的多种图案的温度过高，进而避免影响信号传输的稳定性等，避免影响发光基板100的功能。
如图13所示，上述发光基板100还包括位于第一导电层150与衬底110之间的缓冲层Bf，以及位于第一导电层150远离衬底110一侧的钝化层PVX。
示例性的，缓冲层Bf的材料可以为无机材料，例如为氮化硅、氧化硅等。缓冲层B可以保护衬底110，使得衬底110在第一导电层150产生的应力下，不容易破碎。
示例性的，钝化层PVX的材料可以为无机材料，例如为氮化硅、氧化硅等。
再次，在另一些实施例中，如图15所示，上述发光基板100可以包括：依次层叠于衬底110一侧的第二导电层160、第三导电层170。
示例性的，该第三导电层170中具有多个第二焊盘图案171。相邻的至少两个第二焊盘图案171构成一个第二焊盘组。
可以理解的，驱动芯片121至少包括两个引脚，发光器件123包括两个引脚。第二焊盘组的第二焊盘图案，与驱动芯片121的引脚进行焊接，实现驱动芯片121的固定。第二焊盘组的第二焊盘图案，也可以与发光器件123的引脚进行焊接，实现发光器件123的固定。
该第二焊盘组用于实现与驱动芯片121或发光器件123的电连接。
例如，上述发光基板中的第一电压线VL1、第二电压线VL2、第三电压线VL3、第三连接线CL3均位于第二导电层160，寻址信号线DL位于第三导电层170，上述发光基板中的第二静电通路140、第三电压信号引脚VP3、第三电压信号引脚VP3、功能引脚FP、浮空引脚RP、第二电压信号引脚组VP2、第一电压信号引脚组VP1均位于第二导电层160。
采用上述设置方式，将多条信号线(例如第一电压线VL1、第二电压线VL2、第三电压线VL3、第三连接线CL3、寻址信号线DL)、第二焊盘图案、多个引脚设置在不同的导电层，有利于优化多条信号线、第二焊盘图案、多个引脚的设计方式，增大相邻信号线或相邻焊盘或相邻引脚之间的间距，避免影响到其传输的信号的准确性。
此外，本公开发明人对于采用导电图案填充器件区的方案进行了抗静电能力的测试验证，验证结果如图16所示。
图16中，单层导电层指的是发光基板中包括一层导电层例如第一导电层，焊盘图案及信号线图案位于同一层导电层。双层导电层指的是发光基板中包括两层导电层例如第二导电层和第三导电层，焊盘图案及信号线图案分别位于不同的导电层。
图16中，在发光基板中包括单层导电层的情况下，设计方案1中第一电压线VL1的线宽和长度较小，以及第二电压线VL2的线宽和长度较小，且第一电压线VL1和第二电 压线VL2占据器件区F0的面积较小，也就是说，第一导电层的图案占比小。经测试该设计方案中，发光基板的器件区F0的抗静电电压值为15KV。图16中，设计方案2中相比于设计方案1，加大了第一电压线VL1的线宽和长度，以及第二电压线VL2的线宽和长度，且第一电压线VL1和第二电压线VL2占据器件区F0的填充面积较大，即第一导电层的图案占比较大。经测试该设计方案中，发光基板的器件区F0的抗静电电压值为17KV，高于设计方案1中发基板的器件区F0的抗静电能力。可见，增大导电层中的第一电压线VL1的线宽和长度，或增大第一导电层中的第二电压线VL2的线宽和长度，增大了第一导电层的图案占比，进而可以有效地将因CDM模型产生的静电导出，进而可以提高器件区F0的抗静电能力，增大发光基板的抗静电能力。
图16中，在发光基板中包括双层导电层的情况下，第一电压线VL1及第二电压线VL2均位于更靠近衬底的第二导电层。设计方案3中第一电压线VL1的线宽和长度，及第二电压线VL2第一电压线的线宽和长度，均相对较小，且第一电压线VL1和第二电压线VL2占据器件区F0的面积较小，也就是说，第二导电层的图案占比小。经测试该设计方案中，发光基板的器件区F0的抗静电电压值为15KV。图16中，设计方案4相比于设计方案3，加大了第一电压线VL1的线宽和长度，以及第二电压线VL2的线宽和长度，且第一电压线VL1和第二电压线VL2占据器件区F0的填充面积较大，即第二导电层的图案占比较大。经测试该设计方案中，发光基板的器件区F0的抗静电电压值大于30KV，远高于设计方案3中发基板的器件区F0的抗静电能力。可见，增大第二导电层中的第一电压线VL1的线宽和长度，或增大导电层中的第二电压线VL2的线宽和长度，可以增大第二导电层在器件区F0的图案占比，进而可以有效地增大发光基板的抗静电能力，可以使得发光基板将因CDM模型的静电导出，进而可以提高器件区F0的抗静电能力，可以增大发光基板的抗静电能力。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (25)

  1. 一种发光基板，具有功能区和绑定区；所述绑定区和所述功能区沿第一方向依次排列；所述发光基板包括：
    衬底；
    多个功能元件组，位于所述衬底的一侧；所述多个功能元件组位于所述功能区；
    第一静电通路，与所述多个功能元件组位于所述衬底的同一侧，所述第一静电通路与所述绑定区电连接，且所述第一静电通路的一部分位于所述功能区；所述第一静电通路被配置为，将静电由所述功能区导出至所述绑定区。
  2. 根据权利要求1所述的发光基板，其中，所述第一静电通路包括第一环状导电结构和至少一个第一导电图案；所述第一环状导电结构包括依次电连接的第一子段、第二子段和第三子段，所述第一子段和所述第二子段位于所述功能区沿第二方向的相对两侧，所述第三子段位于所述功能区远离所述绑定区的一侧；所述第一导电图案的至少一部分位于功能区，所述第一导电图案在所述衬底上的正投影与功能元件组在所述衬底上的正投影无交叠；
    其中，所述第一导电图案与所述第三子段电连接；
    所述第一方向与所述第二方向相交。
  3. 根据权利要求2所述的发光基板，其中，在第一导电图案的数量为多个的情况下，在所述第一方向上，相邻的两个第一导电图案之间电连接，最靠近所述第三子段的第一导电图案与所述第三子段电连接。
  4. 根据权利要求2或3所述的发光基板，其中，所述多个第一导电图案与所述第一环状导电结构材料相同且同层设置；
    所述第三子段，及与所述第三子段电连接的第一导电图案，呈一体结构。
  5. 根据权利要求2～4中任一项所述的发光基板，其中，所述第一静电通路还包括：多个桥接部；
    任一列第一导电图案中，相邻两个第一导电图案之间通过桥接部电连接。
  6. 根据权利要求5所述的发光基板，其中，所述多个桥接部中的至少一个为跨接电阻器。
  7. 根据权利要求2～6中任一项所述的发光基板，其中，功能元件组包括驱动芯片和至少一个发光器件组，所述发光器件组包括至少两个发光器件；
    所述发光基板还包括：连接所述驱动芯片和所述发光器件组的第一连接线，及连接属于同一发光器件组中任意两个发光器件的第二连接线；
    所述多个第一导电图案在所述衬底上的正投影，与所述第一连接线和所述第二连接线在所述衬底上的正投影无交叠。
  8. 根据权利要求7所述的发光基板，其中，所述多个第一导电图案与所述第一连接线、所述第二连接线材料相同且同层设置。
  9. 根据权利要求1所述的发光基板，其中，所述第一静电通路包括多条第一电压线和至少一条第三连接线，所述多条第一电压线沿所述第一方向延伸，且沿第二方向间隔排布，第三连接线用于连接至少两条第一电压线。
  10. 根据权利要求9所述的发光基板，其中，所述第三连接线位于所述功能区远离所述绑定区的一侧。
  11. 根据权利要求9或10所述的发光基板，其中，沿所述第二方向，第(2i-1)条第 一电压线及第2i条第一电压线，与同一条第三连接线连接；i为正整数。
  12. 根据权利要求9～11中任一项所述的发光基板，其中，沿第一方向排布的多个功能元件组与一条第一电压线连接。
  13. 根据权利要求9～12中任一项所述的发光基板，其中，在所述第三连接线的数量为多条的情况下，所述多条第三连接线相连接、呈一体结构。
  14. 根据权利要求13所述的发光基板，其中，所述多条第一电压线和所述多条第三连接线材料相同且同层设置。
  15. 根据权利要求1、9～14中任一项所述的发光基板，其中，所述多个功能元件组排列为多列；所述功能区包括多个器件区，一个功能元件组位于一个器件区；
    所述第一静电通路包括：
    多条第二电压线，一条第二电压线与一列功能元件组电连接；
    多个第二导电图案，所述多个第二导电图案在所述衬底上的正投影与所述功能元件组在所述衬底上的正投影无交叠；
    其中，第二导电图案与所述第二电压线电连接，且所述第二导电图案的至少一部分位于所述器件区。
  16. 根据权利要求15所述的发光基板，其中，所述多条第二电压线和所述多个第二导电图案材料相同且同层设置。
  17. 根据权利要求1、9～16中任一项所述的发光基板，还包括：
    位于所述绑定区的多个功能引脚；
    第二静电通路，所述第二静电通路为环绕所述功能区的第二环状导电结构；所述第二环状导电结构包括依次电连接的第一子部、第二子部、第三子部和第四子部，所述第一子部和所述第二子部位于所述功能区沿第二方向的相对两侧，所述第三子部位于所述功能区远离所述绑定区的一侧，所述第四子部的一部分位于所述绑定区远离所述功能区的一侧；所述第二静电通路被配置为，将静电由所述功能区导出至所述绑定区；
    其中，所述多个功能引脚与，所述第四子部的位于所述绑定区远离所述功能区一侧的一部分电连接。
  18. 根据权利要求17所述的发光基板，其中，所述发光基板还包括位于所述绑定区的多个第二电压信号引脚组、多个第一电压信号引脚组以及多个浮空引脚，任一第二电压信号引脚组包括多个第二电压信号引脚，任一第一电压信号引脚组包括多个第一电压信号引脚。
  19. 根据权利要求18所述的发光基板，其中，至少一个浮空引脚与，所述第四子部的位于所述绑定区远离所述功能区一侧的一部分电连接。
  20. 根据权利要求18或19所述的发光基板，其中，多个所述第一电压信号引脚组与多个所述第二电压信号引脚组沿第二方向交替排布；任意相邻的所述第一电压信号引脚组与所述第二电压信号引脚组之间设置有至少一个所述浮空引脚。
  21. 根据权利要求19或20所述的发光基板，其中，与所述第四子部电连接的浮空引脚，及与所述浮空引脚相邻的第二电压信号引脚组的第二电压信号引脚之间，在所述第一方向上的间距的尺寸大于或等于200μm。
  22. 根据权利要求18～21中任一项所述的发光基板，其中，相邻的两个第一电压信号引脚之间的间距大于或等于100μm。
  23. 根据权利要求18～22中任一项所述的发光基板，其中，所述第二静电通路、所述多个功能引脚、所述多个浮空引脚、所述多个第二电压信号引脚组及所述多个第一电压信号引脚组的材料相同且同层设置。
  24. 一种背光模组，包括：如权利要求1～23中任一项所述的发光基板，以及位于所述发光基板的出光侧的光学膜片。
  25. 一种显示装置，包括：如权利要求24所述的背光模组；
    位于所述背光模组出光侧的阵列基板；
    以及，位于所述阵列基板远离所述背光模组一侧的彩膜基板。
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