WO2024113380A1 - 发光基板、背光模组及显示装置 - Google Patents

发光基板、背光模组及显示装置 Download PDF

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Publication number
WO2024113380A1
WO2024113380A1 PCT/CN2022/136362 CN2022136362W WO2024113380A1 WO 2024113380 A1 WO2024113380 A1 WO 2024113380A1 CN 2022136362 W CN2022136362 W CN 2022136362W WO 2024113380 A1 WO2024113380 A1 WO 2024113380A1
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Prior art keywords
light
signal line
line
electrically connected
signal lines
Prior art date
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PCT/CN2022/136362
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English (en)
French (fr)
Inventor
马亚军
田�健
刘纯建
雷杰
张建英
Original Assignee
京东方科技集团股份有限公司
合肥京东方瑞晟科技有限公司
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Priority to PCT/CN2022/136362 priority Critical patent/WO2024113380A1/zh
Publication of WO2024113380A1 publication Critical patent/WO2024113380A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a light-emitting substrate, a backlight module and a display device.
  • Miniature light-emitting diodes such as Mini-LED (Mini Light-Emitting Diode) and Micro LED (Micro Light-Emitting Diode), are less than 500 ⁇ m in size. Due to their smaller size, ultra-high brightness, long life and other advantages, their use in the display field has increased significantly.
  • a light-emitting substrate which has functional areas and binding areas arranged at intervals along the first direction.
  • the light-emitting substrate includes: a substrate; a plurality of functional element groups located on one side of the substrate and located in the functional area; the plurality of functional element groups are arranged in a plurality of rows along the first direction and in a plurality of columns along the second direction, and the first direction and the second direction intersect; a plurality of signal line groups located in the functional area, which are located on the same side of the substrate as the plurality of functional element groups, and one signal line group is electrically connected to one column of functional element groups; the signal line group includes at least one first-class signal line, each of which extends along the first direction and is arranged at intervals along the second direction; a plurality of first-class connecting lines, which are used to connect first-class signal lines transmitting the same signal in at least two signal line groups; a plurality of binding pins located in the binding area; wherein, among the plurality of first-
  • the functional element group includes at least one light-emitting device group; the first type of signal line includes at least one first voltage signal line, and the first voltage signal line is electrically connected to the light-emitting device group; the multiple first type of connecting lines include at least one first connecting line; the first connecting line is electrically connected to the same end of the first voltage signal lines in the at least two signal line groups.
  • the first connection line extends along the second direction and is located on a side of the functional area away from the binding area.
  • a plurality of light emitting device groups in the same column of functional element groups are arranged into at least one column; and a column of light emitting device groups is electrically connected to one of the first voltage signal lines.
  • an orthographic projection of a column of light-emitting device groups connected to the first voltage signal line on the substrate at least partially overlaps with an orthographic projection of the first voltage signal line on the substrate.
  • the functional element group also includes a driving chip, and multiple driving chips in the same column of functional element groups are arranged in a row along the first direction; the multiple light-emitting device groups in the same column of functional element groups are located on opposite sides of the multiple driving chips in the same column of functional element groups along the first direction.
  • the functional element group includes a driving chip; the first type of signal line includes a ground signal line, and the ground signal line is electrically connected to the driving chip; the multiple first type of connecting lines include at least one second connecting line; the second connecting line is electrically connected to the same end of the ground signal lines in the at least two signal line groups.
  • the second connection line extends along the second direction and is located on a side of the functional area close to the binding area.
  • each functional element group includes a driver chip, the number of functional element groups in each column is N, and the N driver chips in each column of functional element groups are cascaded in sequence;
  • the signal line group also includes at least one second-type signal line, each of the second-type signal lines extends along the first direction and is arranged at intervals along the second direction;
  • the light-emitting substrate also includes: a plurality of second-type connecting lines, the second-type connecting lines are used to connect the second-type signal lines that transmit the same signal in at least two signal line groups; a plurality of binding pins located in the binding area; wherein, among the plurality of second-type signal lines electrically connected to the second-type connecting lines, at least one second-type signal line is arranged at intervals from the binding pins.
  • any two adjacent driver chips among the N driver chips are cascaded through the address signal line; the multiple second-type connection lines also include at least one third connection line; in M columns of adjacent functional element groups, two driver chips belonging to two adjacent columns of functional element groups are cascaded through the third connection line, wherein M ⁇ 2, and M is a positive integer.
  • the third connecting line is electrically connected to the first driver chip of one of the N driver chips in the two adjacent columns, and passes through the gap between the functional element groups in the two adjacent columns to be electrically connected to the Nth driver chip of the other of the N driver chips in the two adjacent columns.
  • the third connection line extends along the second direction and is located on a side of the functional area away from the binding area.
  • the second type of signal line includes a second voltage signal line, which is electrically connected to the driving chip; the multiple second type of connection lines include at least one fourth connection line; among the second voltage signal lines connected to the N driving chips in the M columns, at least two second voltage signal lines are connected through the fourth connection line.
  • the fourth connection line extends along the second direction and is located on a side of the functional area close to the binding area.
  • the fourth connecting line is electrically connected to two adjacent second voltage signal lines of the second voltage signal lines connected to the N driving chips in the M columns; wherein the fourth connecting line is electrically connected to the first end of one of the two adjacent second voltage signal lines, and passes through the gap between two adjacent columns of functional element groups, and is electrically connected to the second end of the other of the two adjacent second voltage signal lines.
  • the second type of signal line includes a data signal line, and the data signal line is electrically connected to the driving chip; the plurality of second type connecting lines include at least one fifth connecting line; among the data signal lines connected to the N driving chips in the M columns, at least two data signal lines are connected through the fifth connecting line.
  • the fifth connection line extends along the second direction and is located on a side of the functional area close to the binding area.
  • the fifth connecting line is electrically connected to two adjacent data signal lines among the data signal lines connecting the N driving chips in the M columns; wherein the fifth connecting line is electrically connected to the first end of one of the two adjacent data signal lines, and passes through the gap between two adjacent columns of functional element groups, and is electrically connected to the second end of the other of the two adjacent data signal lines.
  • the functional element group includes at least one light-emitting device group, and the light-emitting device group includes a plurality of light-emitting devices; the light-emitting devices included in the plurality of light-emitting device groups are arranged into a plurality of rows along a first direction and into a plurality of columns along a second direction; any two adjacent rows of light-emitting devices are staggered.
  • a backlight module comprising: a light-emitting substrate as described in any of the above embodiments, and an optical film located on the light-emitting side of the light-emitting substrate.
  • a display device comprising: a backlight module as described in the above embodiment; an array substrate located at a light emitting side of the backlight module; and a color film substrate located at a side of the array substrate away from the backlight module.
  • FIG1A is a structural diagram of a display device according to some embodiments of the present disclosure.
  • FIG1B is a structural diagram of another display device according to some embodiments of the present disclosure.
  • FIG2 is a structural diagram of a backlight module according to some embodiments of the present disclosure.
  • FIG3A is a structural diagram of a light-emitting substrate in some embodiments of the present disclosure.
  • FIG3B is a structural diagram of another light-emitting substrate in some embodiments of the present disclosure.
  • FIG3C is a structural diagram of another light-emitting substrate in some embodiments of the present disclosure.
  • FIG3D is a structural diagram of another light-emitting substrate in some embodiments of the present disclosure.
  • FIG3E is a structural diagram of another light-emitting substrate in some embodiments of the present disclosure.
  • FIG3F is a structural diagram of another light-emitting substrate in some embodiments of the present disclosure.
  • FIG3G is a partial structural diagram of the ground side of a light-emitting substrate in some embodiments of the present disclosure.
  • FIG3H is a partial structural diagram of the sky side of a light-emitting substrate in some embodiments of the present disclosure.
  • FIG4A is a structural diagram of another light-emitting substrate in some embodiments of the present disclosure.
  • FIG4B is a partial structural diagram of another light-emitting substrate on the sky side in some embodiments of the present disclosure.
  • FIG4C is a partial structural diagram of the ground side of another light-emitting substrate in some embodiments of the present disclosure.
  • FIG5 is a partial structural diagram of another light-emitting substrate in some embodiments of the present disclosure.
  • FIG. 6 is a structural diagram of yet another light-emitting substrate in some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of the features.
  • plural means two or more.
  • connection and its derivative expressions may be used.
  • connection should be understood in a broad sense.
  • connection can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.
  • connection may be used to indicate that two or more components are in direct physical or electrical contact with each other.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “upon” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that” or “if [a stated condition or event] is detected” are optionally interpreted to mean “upon determining that” or “in response to determining that” or “upon detecting [a stated condition or event]” or “in response to detecting [a stated condition or event],” depending on the context.
  • Exemplary embodiments are described herein with reference to cross-sectional views and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and/or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.
  • FIG. 1A is a structural diagram of a display device according to some embodiments.
  • an embodiment of the present disclosure provides a display device 1.
  • the display device 1 may be a product having an image display function.
  • the display device 1 can be any device that displays an image, whether in motion (e.g., video) or fixed (e.g., still image), and whether textual or electronic. More specifically, it is contemplated that the embodiments described may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants, handheld or portable computers, global positioning system receivers/navigators, cameras, video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and/or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.
  • electronic devices such as (but not limited to) mobile phones, wireless devices, personal data assistants, handheld or portable computers, global positioning system receiver
  • the display device 1 may also be a product without an image display function.
  • the display device 1 may be an image board or the like.
  • the embodiment of the present disclosure does not further limit the display device 1 .
  • the following description will be given by taking the display device 1 as a product having an image display function as an example.
  • the display device 1 may be a LCD (Liquid Crystal Display).
  • the display device 1 includes: a backlight module 10 , an array substrate 20 located on the light emitting side of the backlight module 10 , and a color film substrate 30 located on a side of the array substrate 20 away from the backlight module 10 .
  • the backlight module 10 can be used as a light source to provide backlight.
  • the backlight provided by the backlight module 10 can be white light or blue light.
  • the light emitting side of the backlight module 10 refers to the side from which the backlight module 10 emits light.
  • the array substrate 20 may include a plurality of pixel driving circuits and a plurality of pixel electrodes, the plurality of pixel driving circuits being arranged in an array, for example, and the plurality of pixel driving circuits being electrically connected to the plurality of pixel electrodes in a one-to-one correspondence, and the pixel driving circuits providing pixel voltages to the corresponding pixel electrodes.
  • the color filter substrate 30 may include a red filter film, a green filter film, and a blue filter film.
  • red filter film can only allow the red light in the incident light to pass through
  • the green filter film can only allow the green light in the incident light to pass through
  • the blue filter film can only allow the blue light in the incident light to pass through.
  • the color filter substrate 30 may include a color conversion film.
  • the color conversion film may be a quantum dot film. After the blue light is irradiated to the red quantum dot film, it can be converted to red light. After the blue light is irradiated to the green quantum dot film, it can be converted to green light. The red light and green light obtained after the conversion of the quantum dot film are mixed with the blue light provided by the backlight module 10, so that the display device 1 can realize full-color graphic display.
  • the display device 1 includes: and further includes: a common electrode.
  • the common electrode can be arranged in the color filter substrate 30, and the common electrode can receive a common voltage.
  • the common electrode can also be arranged in the array substrate 20, which is not limited in the present disclosure.
  • the display device 1 further includes: a liquid crystal layer 40 located between the color filter substrate 30 and the array substrate 20 .
  • the liquid crystal layer 40 includes a plurality of liquid crystal molecules.
  • an electric field may be formed between the pixel electrode and the common electrode.
  • the intensity of the electric field formed between the common electrode and each pixel electrode can be controlled, thereby controlling the deflection angle of the liquid crystal molecules in the liquid crystal layer 40.
  • the backlight provided by the backlight module 10 can pass through the array substrate 20 and be incident on the liquid crystal molecules of the liquid crystal layer 40.
  • the liquid crystal molecules flip, thereby changing the amount of light passing through the liquid crystal molecules, so that the light emitted by the liquid crystal molecules reaches a preset brightness.
  • the above light passes through the filter films of different colors in the color filter substrate 30 and then emits.
  • the emitted light includes light of various colors, such as red light, green light, blue light, etc. The light of various colors cooperates with each other, so that the display device 1 realizes the image display function.
  • backlight modules 10 in the display device 1 there are various types of backlight modules 10 in the display device 1 , which can be configured according to actual conditions, and the present disclosure does not limit this.
  • the backlight module 10 may be an edge-type backlight module, or the backlight module 10 may be a direct-type backlight module.
  • the backlight module 10 as a direct-type backlight module as an example.
  • the backlight module 10 includes a light emitting substrate 100 and an optical film 200 located on the light emitting side of the light emitting substrate 100 .
  • the optical film 200 includes: a diffuser plate 210 , a quantum dot film 220 , a diffuser sheet 230 , and a composite film 240 , which are sequentially stacked on the light-emitting side of the light-emitting substrate 100 .
  • the diffusion plate 210 and the diffusion sheet 230 are used to eliminate lamp shadows and to even out the light emitted by the light-emitting substrate 100 to improve the uniformity of the light.
  • the quantum dot film 220 is used to convert the light emitted by the light emitting substrate 100.
  • the quantum dot film 220 can convert the blue light into white light and improve the purity of the white light.
  • the composite film 240 is used to increase the brightness of the light emitted by the light emitting substrate 100 .
  • the brightness of the light emitted by the light emitting substrate 100 after being incident on the optical film 200 is enhanced, and the purity and uniformity of the emitted light are higher.
  • the backlight module 10 further includes: a support column 201 disposed between the light emitting substrate 100 and the diffusion plate 210 of the optical film 200 .
  • the support column 201 can be fixed on the light-emitting substrate 100 by glue.
  • the support column 201 can be used to support the optical film 200, and make the light emitted by the light-emitting substrate 100 obtain a certain light mixing distance, so as to further eliminate the lamp shadow and improve the uniformity of the light.
  • the display device 1 also includes: a frame, a display chip and other electronic accessories.
  • the display device 1 includes a light-emitting substrate 100, and the light-emitting substrate 100 is directly used to display images.
  • the display device is often used in commercial displays, such as display screens in traffic management command centers or display screens in commercial plazas.
  • the light emitting substrate 100 has a functional area F and a binding area B. As shown in FIGS. 3A to 3G and 4A , the light emitting substrate 100 has a functional area F and a binding area B. As shown in FIGS. 3A to 3G and 4A , the light emitting substrate 100 has a functional area F and a binding area B. As shown in FIGS. 3A to 3G and 4A , the light emitting substrate 100 has a functional area F and a binding area B. As shown in FIGS.
  • the binding area B and the functional area F are arranged in sequence along the first direction X.
  • the edges of the functional area F shown in the dotted box and the edges of the binding area B are arranged at intervals from each other, only to clearly distinguish the functional area F from the binding area B, and the edge positions of the functional area F and the binding area B are not further limited.
  • the binding area B is an area for implementing the binding of the light emitting substrate 100 and the display chip.
  • the shape of the functional area F can be rectangular or circular.
  • the light emitting substrate 100 includes: a substrate 110 , and a plurality of functional element groups 120 .
  • the substrate 110 There are many types of the substrate 110 , which can be selected according to actual needs.
  • the substrate 110 may be a flexible substrate or a rigid substrate.
  • the flexible substrate can be, for example, a PET (Polyethylene Terephthalate) substrate, a PEN (Polyethylene Naphthalate Two Formic Acid Glycol Ester) substrate or a PI (Polyimide) substrate, etc.
  • a PET Polyethylene Terephthalate
  • PEN Polyethylene Naphthalate Two Formic Acid Glycol Ester
  • PI Polyimide
  • the substrate 110 when the substrate 110 is a rigid substrate, the rigid substrate may be a glass substrate or a PMMA (Polymethyl methacrylate) substrate, etc.
  • PMMA Polymethyl methacrylate
  • a plurality of functional element groups 120 are located on one side of the substrate 110; and the plurality of functional element groups 120 are located in the functional region F.
  • the plurality of functional element groups 120 are arranged in a plurality of rows along the first direction X, and in a plurality of columns along the second direction Y. It can be understood that the plurality of rows of functional element groups 120 are arranged at intervals along the first direction X, and the plurality of columns of functional element groups 120 are arranged at intervals along the second direction Y.
  • the second direction Y intersects the first direction X.
  • the angle between the first direction X and the second direction Y can be set according to actual needs.
  • the angle between the first direction X and the second direction Y is 85°, 88° or 90°.
  • the functional element group 120 may include a plurality of micro resistors or micro capacitors, etc.
  • the functional element group 120 may include a driving chip 121 and at least one light emitting device group 122.
  • the light emitting device group 122 may include one light emitting device 123 or may include a plurality of light emitting devices 123.
  • the functional element group 120 may include a driving chip 121 and a light emitting device group 122 .
  • the functional element group 120 may include a driver chip 121 and a plurality of light emitting device groups 122.
  • the functional element group 120 may include a driver chip 121 and four light emitting device groups 122, as shown in FIGS. 3A to 3F, the four light emitting device groups 122 are respectively distributed on the extension lines of the four corners of the driver chip 121, and the driver chip 121 is located in the middle of the four light emitting device groups 122.
  • the light emitting device group 122 may include two light emitting devices 123 , four light emitting devices 123 , or six light emitting devices 123 .
  • a light emitting device group 122 includes multiple light emitting devices 123
  • the multiple light emitting devices 123 in the light emitting device group 122 can also be arranged at the vertices of a hexagon, an octagon or other irregular shapes.
  • the multiple light emitting devices 123 in the light emitting device group 122 can also be arranged in a circular or elliptical shape to meet different usage requirements. The embodiments of the present disclosure are not limited to this.
  • a light emitting device group 122 includes multiple light emitting devices 123
  • the multiple light emitting devices 123 in the same light emitting device group 122 can be used to emit light of the same color, and the multiple light emitting devices 123 in the same light emitting device group 122 can also be used to emit light of multiple different colors.
  • the number of light emitting devices 123 included in different light emitting device groups 122 may be the same or different.
  • the embodiment of the present disclosure does not further limit the number of light emitting devices 123 in a light emitting device group 122.
  • multiple light emitting devices 123 in the same light emitting device group 122 are connected in series. In this way, by providing an electrical signal to any light emitting device 123 in a light emitting device group 122, it is possible to provide an electrical signal to each light emitting device 123 in a light emitting device group 122, thereby improving the wiring convenience of the light emitting substrate 100.
  • the light emitting device group 122 emits light.
  • the above-mentioned light-emitting devices 123 include but are not limited to Mini LED (Mini Light-Emitting Diode), Micro LED (Micro Light-Emitting Diode), etc.
  • the grain size of the light-emitting devices 123 is smaller, which can greatly shorten the light mixing distance between adjacent light-emitting devices 123, so that the light-emitting substrate has the advantages of adjustable regional brightness, high color rendering, high contrast, etc. It can also make the light-emitting substrate 100 thinner and lighter, more energy-saving, and thus make the application of the light-emitting substrate including mini LEDs or micro LEDs more flexible.
  • the light-emitting substrate including mini LEDs or micro LEDs has lower cost, longer life, and less risk of screen burn-in.
  • the light-emitting substrate 100 further includes a plurality of signal line groups 130.
  • the plurality of signal line groups 130 are located in the functional area F, and the plurality of signal line groups 130 and the plurality of functional element groups 120 are located on the same side of the substrate 110.
  • One signal line group 130 is electrically connected to a column of functional element groups 120.
  • the signal line group 130 includes at least one first-type signal line 1301, and each first-type signal line 1301 extends along the first direction X and is arranged at intervals along the second direction Y.
  • the multiple signal line groups 130 include multiple first-class signal lines 1301, and the lengths and/or widths of the multiple first-class signal lines 1301 are not exactly the same.
  • the length of a portion of the first-class signal lines 1301 along the first direction X is basically equal to the length of a column of functional element groups 120 along the first direction X, while the length of another portion of the first-class signal lines 1301 along the first direction X is greater than the length of a column of functional element groups 120 along the first direction X.
  • multiple signal line groups 130 are arranged on the same layer, that is, multiple signal line groups 130 are arranged on the same conductive layer. It can be understood that in addition to multiple signal line groups 130, other routing lines can also be arranged on the conductive layer.
  • multiple first-class signal lines 1301 in multiple signal line groups 130 can be set in different conductive layers.
  • some of the multiple first-class signal lines 1301 in the multiple signal line groups 130 are located in the same layer, and at least two first-class signal lines 1301 are respectively set on two conductive layers.
  • the arrangement of multiple signal line groups 130 on the same layer can reduce the steps of patterning the conductive layer, thereby simplifying the preparation process of the light-emitting substrate 100, reducing the number of masks, and reducing the cost of the light-emitting substrate 100, and can also reduce the occurrence of short circuits and other adverse failures of the light-emitting substrate 100, thereby improving the yield rate of the light-emitting substrate 100.
  • the wiring flexibility of the signal line groups 130 is higher.
  • the embodiment of the present disclosure is described by taking a plurality of signal line groups 130 arranged on the same layer as an example.
  • the light emitting substrate 100 includes an insulating layer, which is located on a side of the conductive layer away from the substrate 110 and covers the conductive layer. That is, the insulating layer can cover the plurality of signal line groups 130 in the conductive layer and other conductive structures in the conductive layer.
  • the first type signal line 1301 can be used to transmit a voltage signal with a constant amplitude.
  • the signal line group 130 includes multiple first type signal lines 1301, the multiple first type signal lines 1301 can be used to transmit different signals respectively; or, some of the multiple first type signal lines 1301 can be used to transmit the same signal.
  • the material of the first type signal line 1301 is metal or metal alloy.
  • the material of the first type signal line 1301 may include copper or aluminum, etc., so as to improve the conductivity of the first type signal line 1301.
  • the number of first type signal lines 1301 included in each signal line group 130 may be the same or different.
  • the intervals between any two adjacent first type signal lines 1301 in a signal line group 130 along the second direction Y may be the same or different.
  • Figure 3G is a partial structural diagram of the ground side of the light-emitting substrate 100 (the ground side of the light-emitting substrate 100 refers to: the side of the functional area F close to the binding area B), the light-emitting substrate 100 also includes a plurality of binding pins (Bonding Pins) 140 located in the binding area B.
  • the ground side of the light-emitting substrate 100 refers to: the side of the functional area F close to the binding area B
  • the light-emitting substrate 100 also includes a plurality of binding pins (Bonding Pins) 140 located in the binding area B.
  • the number of the binding pins 140 may be multiple, and the multiple binding pins 140 may be arranged at intervals along the second direction Y.
  • a plurality of binding pins 140 are disposed in one binding area B.
  • one end of the first type signal line 1301 is electrically connected to the binding pin 140 in the binding area B, and the other end extends along the first direction X to extend from the binding area B to the functional area F, and is electrically connected to a column of functional element groups 120 arranged along the first direction X. It can be understood that the first type signal line 1301 can be directly electrically connected to the functional element group 120, or can be electrically connected to the functional element group 120 through other components or conductive patterns.
  • the light-emitting substrate 100 also includes a flexible printed circuit (FPC) and a printed circuit board (PCB).
  • FPC flexible printed circuit
  • PCB printed circuit board
  • One end of the flexible printed circuit is bound and connected to the binding pin 140 in the binding area B, and the other end is bound and connected to the printed circuit board, so that signals can be transmitted between the multiple signal line groups 130 and the printed circuit board, thereby realizing the driving of the multiple functional element groups 120.
  • one signal line group 130 may include first-type signal lines 1301 for transmitting different signals, so as to transmit different signals to the functional element groups 120 , thereby realizing driving of multiple functional element groups 120 .
  • the signal line group 130 includes a device power signal line VLED, a chip power signal line VCC, an input signal line Dis, a data signal line Data, a ground signal line GND, and an output signal line FB, and each signal line is used to transmit a different signal.
  • the power signal line VLED, the chip power signal line VCC, the input signal line Dis, the data signal line Data, the ground signal line GND, and the output signal line FB in each signal line group 130 are electrically connected to different binding pins 140 to transmit signals to different functional element groups 120.
  • multiple binding areas B are generally required to set the binding pins 140; for example, when 64 signal line groups are included, 7 to 12 binding areas B are set. The more the number of binding areas B, the larger the space occupied.
  • the more binding areas B cannot be set, resulting in the light-emitting substrate 100 failing to meet the requirements.
  • the more the number of binding areas B the more the number of flexible circuit boards required, which correspondingly increases the cost of the light-emitting substrate 100; and the more the number of binding areas B, the greater the process difficulty in the production process of the light-emitting substrate 100, resulting in a higher defect rate of the light-emitting substrate 100.
  • the light emitting substrate 100 further includes a plurality of first type connecting wires 150.
  • the first type connecting wires 150 are used to connect the first type signal wires 1301 in at least two signal wire groups 130 that transmit the same signal.
  • the first type connection line 150 extends along the second direction Y. At this time, the size of the first type signal line 150 in the second direction Y at least exceeds the size of one light emitting device group 122 in the second direction Y.
  • the plurality of first-type connection lines 150 and the signal line group 130 may be arranged on the same conductive layer, or may be arranged on different conductive layers, for example, the plurality of first-type connection lines 150 and the signal line group 130 may be arranged on two conductive layers respectively.
  • the embodiments of the present disclosure are not limited to this.
  • the first-category connecting wire 150 can be used to connect the first-category signal wires 1301 transmitting the same signal in two signal wire groups 130, or can be used to connect the first-category signal wires 1301 transmitting the same signal in three signal wire groups 130, or can be used to connect the first-category signal wires 1301 transmitting the same signal in four signal wire groups 130.
  • the embodiments of the present disclosure are not limited to this.
  • the first-type signal lines 1301 transmitting the same signal in at least two signal line groups 130 are arranged in parallel through the first-type connecting lines 150; or the first-type signal lines 1301 transmitting the same signal in at least two signal line groups 130 are arranged in series through the first-type connecting lines 150.
  • At least one first-type signal line 1301 is spaced apart from the binding pin 140 .
  • At least one first-class signal line 1301 is spaced apart from the binding pin 140, and the two do not contact each other in the binding area.
  • the at least one first-class signal line 1301 is indirectly connected to the binding pin 140 through the first-class connecting line 150 electrically connected thereto and other first-class signal lines 1301 connected in series or in parallel thereto.
  • the signal provided by the printed circuit board can be transmitted to a column of functional element groups 120 connected to the at least one first-class signal line 1301 through the binding pin 140, other first-class signal lines 1301 connected in series or in parallel with the at least one first-class signal line 1301, and the first-class connecting line 150 electrically connected to the at least one first-class signal line 1301, thereby realizing driving of the column of functional element groups 120.
  • first-type signal lines 1301 when there are four first-type signal lines 1301 electrically connected to the first-type connection line 150, only one first-type signal line 1301 may be spaced apart from the binding pin 140; or two or three first-type signal lines 1301 may be spaced apart from the binding pin 140.
  • first-type signal lines 1301 when there are four first-type signal lines 1301 electrically connected to the first-type connection line 150, only one first-type signal line 1301 may be spaced apart from the binding pin 140; or two or three first-type signal lines 1301 may be spaced apart from the binding pin 140.
  • three first-type signal lines 1301 are spaced apart from the binding pin 140.
  • the first-type signal lines 1301 in the two signal line groups 130 connected to the same first-type connecting line 150 are used to transmit the same electrical signal.
  • one of the first-class signal lines 1301 is electrically connected to the binding pin 140 in the binding area B (for example, direct contact or indirect contact), and the flexible circuit board is electrically connected to the first-class signal line 1301 through the binding pin 140, so that the signal provided by the printed circuit board can be transmitted to at least two signal line groups 130 through the flexible circuit board, thereby realizing the driving of at least two functional element groups 120.
  • the main body of the first type signal line 1301 or the second type signal line 1302 that is electrically connected to the binding pin 140 in the binding area B by direct contact has a shape similar to the letter "L", including a first portion whose extension direction has an angle of no more than 5° with the first direction X and a second portion whose extension direction has an angle of no more than 5° with the second direction Y.
  • the length of the first portion is equivalent to the length of a column of functional element groups 120 along the first direction X; along the second direction Y, the distance from the first portion to the binding area B is positively correlated with the length of the second portion; and along the second direction Y, the longer the second portion of the signal line, the closer its second portion is to the binding area B in the first direction X, and the closer its first portion is to the binding area B in the second direction Y.
  • first type signal line 1301 or a portion of the second type signal line 1302 having a shape similar to the letter "L" also includes a third portion, one end of the third portion is connected to its second portion, and the other end is connected to at least one binding pin 140; the angle between the extension direction of the third portion and the first direction X does not exceed 5°.
  • At least one first-type signal line 1301 or at least one second-type signal line 1302 spaced apart from the binding pin 140 has a polygonal shape, such as a rectangular shape.
  • the projection of the first type signal line 1301 electrically connected to the binding pin 140 by direct contact in the binding area on the substrate 110 does not overlap with the orthographic projection of the light emitting device group 122 on the substrate 110, as shown in FIG. 3G .
  • the projection of the first type signal line 1301 electrically connected to the binding pin 140 through direct contact on the substrate 110 partially overlaps with the positive projection of some light-emitting device groups 122 close to the binding area B among the multiple light-emitting device groups 122 on the substrate 110. Therefore, the size of the light-emitting substrate 100 in the first direction X can be further reduced.
  • the light-emitting substrate 100 is applied to the display device 1, it can meet the requirement of realizing a narrow bezel design of the display device 1.
  • the light-emitting substrate 100 connects the first-class signal lines 1301 transmitting the same signal in at least two signal line groups 130 through the first-class connecting lines 150.
  • at least one first-class signal line 1301 is arranged at intervals from the binding pins 140, thereby reducing the number of first-class signal lines 1301 that need to be electrically connected to the binding pins 140.
  • the number of binding pins 140 that need to be set is reduced, so that fewer binding areas B are required to set the binding pins 140, effectively reducing the number of binding areas B and reducing the space occupied by the binding areas B.
  • the light-emitting substrate 100 When the light-emitting substrate 100 is applied to the display device 1, it can overcome the problem of insufficient space in some display devices 1 (for example, a laptop computer (Notebook)), improve the adaptability of the light-emitting substrate 100, and broaden the application scenarios of the light-emitting substrate 100.
  • some display devices 1 for example, a laptop computer (Notebook)
  • the reduction in the number of binding areas B can reduce the difficulty of the manufacturing process of the light-emitting substrate 100 to a certain extent, improve the yield of the light-emitting substrate 100, and shorten the time required for the process of the binding area B of the light-emitting substrate 100, reduce the load of the production line, and improve production efficiency; and the number of binding areas B is reduced, and the number of flexible circuit boards required is also reduced, thereby reducing the production cost of the light-emitting substrate 100.
  • the light-emitting substrate 100 provided in the embodiment of the present disclosure improves the reliability of the light-emitting substrate 100 on the basis of realizing fewer binding areas B.
  • the first type signal line 1301 includes at least one first voltage signal line VL1.
  • the first voltage signal line VL1 is electrically connected to the light-emitting device group 122.
  • the plurality of first type connection lines 150 include at least one first connection line 1511.
  • the first connection line 1511 is electrically connected to the same end of the first voltage signal line VL1 in at least two signal line groups 130.
  • the plurality of first-type connection lines 150 may include one first connection line 1511 , or may include a plurality of first connection lines 1511 .
  • the first connection line 1511 may be used to connect any number of first voltage signal lines VL1 , or the first connection line 1511 may be used for all first voltage signal lines VL1 in the plurality of signal line groups 130 .
  • the number of first voltage signal lines VL1 connected to the same first connection line 1511 may be the same or different, and the embodiments of the present disclosure are not limited thereto.
  • the plurality of first-type connection lines 150 include a plurality of first connection lines 1511
  • the plurality of first-type connection lines 150 extend along the second direction Y, and the plurality of first-type connection lines 150 are sequentially spaced apart in the second direction Y.
  • the same first connection line 1511 can be used to connect two first voltage signal lines VL1.
  • the same first connection line 1511 can be used to connect multiple first voltage signal lines VL1.
  • Figures 3A and 4A illustrate that the same first connection line 1511 can be used to connect four first voltage signal lines VL1.
  • the first type signal line 1301 may include two first voltage signal lines VL1 .
  • the first type signal line 1301 may include one first voltage signal line VL1 .
  • a plurality of light emitting device groups 122 arranged along the first direction X are connected to one first voltage signal line VL1.
  • the plurality of first voltage signal lines VL1 connected to the same first connection line 1511 belong to different signal line groups 130 .
  • some of the first voltage signal lines VL1 belong to the same signal line group 130.
  • two first voltage signal lines VL1 belong to the same signal line group 130, as shown in FIGS. 3A and 3H .
  • the first voltage signal line VL1 is located in the functional area F, and one first voltage signal line VL1 is electrically connected to a column of light-emitting device groups 122.
  • the multiple first voltage signal lines VL1 electrically connected to the first connecting line 1511 at least one first voltage signal line VL1 is spaced apart from the binding pin 140.
  • Some first voltage signal lines VL1 extend from the functional area F to the binding area B, and are electrically connected to the binding pin 140 located in the binding area B through direct contact, so that the signal from the printed circuit board can be transmitted to the light-emitting device group 122.
  • the first voltage signal line VL1 is used to provide a relatively large constant current voltage for the light emitting device 123 in the light emitting device group 122.
  • the light emitting device group 122 includes a plurality of light emitting devices 123, and the plurality of light emitting devices 123 are connected to each other in series
  • the first light emitting device 123 of the plurality of light emitting devices 123 connected in series is electrically connected to the first voltage signal line VL1
  • the last light emitting device 123 of the plurality of light emitting devices 123 connected in series is electrically connected to the driving chip 121.
  • one first voltage signal line VL1 extends from the functional area F to the binding area B, and is electrically connected to the binding pin 140 located in the binding area B.
  • the power supply outside the light-emitting substrate 100 is electrically connected to the first voltage signal line VL1 through the printed circuit board and the binding pin 140, so that the power supply can supply power to the light-emitting device 123 in a column of light-emitting device groups 122 through the first voltage signal line VL1, thereby enabling the light-emitting device 123 to emit light.
  • the material of the first connection line 1511 is the same as that of the first voltage signal line VL1 and they are disposed in the same layer, that is, disposed in the same conductive layer, as shown in FIGS. 3A to 3F and 4A .
  • the material of the first connection line 1511 and the material of the first voltage signal line VL1 may both be metal, for example, the metal may be copper.
  • the above-mentioned “same layer” refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process.
  • a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.
  • the first connection line 1511 and the first voltage signal line VL1 can be arranged in different conductive layers, for example, the first connection line 1511 and the first voltage signal line VL1 can be arranged on two conductive layers respectively.
  • the material of the first connection line 1511 and the material of the first voltage signal line VL1 can be the same or different. The embodiments of the present disclosure are not limited to this.
  • the same end of the first voltage signal line VL1 in at least two signal line groups 130 can be an end of the first voltage signal line VL1 in at least two signal line groups 130 close to the binding area B, or it can be an end of the first voltage signal line VL1 in at least two signal line groups 130 away from the binding area B, and the embodiments of the present disclosure do not limit this.
  • the multiple first voltage signal lines VL1 electrically connected to the multiple columns of light-emitting device groups 122 are electrically connected through the first connecting line 1511.
  • the multiple first voltage signal lines VL1 connected by the first connecting line 1511 at least one first voltage signal line VL1 is arranged at an interval with the binding pin 140, and some first voltage signal lines VL1 are electrically connected to the binding pin 140 located in the binding area B through direct contact, so that the signal provided by the printed circuit board is transmitted to the multiple columns of light-emitting device groups 122 through the part of the first voltage signal lines VL1 and the binding pin 140, thereby reducing the number of first voltage signal lines VL1 that need to be directly electrically connected to the binding pin 140 in the binding area B, thereby reducing the number of binding pins 140 that need to be set, so that fewer binding areas B are required to set the binding pins 140, effectively reducing the number of binding areas B, and reducing the space occupied by the binding area B.
  • the first connection line 1511 extends along the second direction Y and is located on a side of the functional area F away from the binding area B (ie, the sky side of the light-emitting substrate).
  • multiple first voltage signal lines VL1 connected to the same first connection line 1511 are arranged in parallel, thereby reducing the voltage drop between the light emitting device groups 122 connected to the multiple first voltage signal lines VL1 and improving the light emitting efficiency of the light emitting device groups 122 .
  • the first connecting line 1511 extends along the second direction Y and is electrically connected to the same end of the first voltage signal line VL1 in at least two signal line groups 130, which can reduce the number of first voltage signal lines VL1 that need to be electrically connected to the binding pins 140 in the binding area B, thereby reducing the number of binding areas B; on this basis, the first connecting line 1511 is located on the side of the functional area F away from the binding area B, and there is no other structure between the first connecting line 1511 and the end of the first voltage signal line VL1 away from the binding area B, so that the electrical connection between the first connecting line 1511 and the first voltage signal line VL1 does not need to cross other film layers, but can be achieved directly in the same layer, thereby simplifying the preparation process of the light-emitting substrate 100, reducing the number of masks, reducing the cost of the light-emitting substrate 100, and also reducing the occurrence of short circuits and other adverse failures in the light-emitting substrate 100, thereby improving
  • the first connection line 1511 and the first voltage signal line VL1 electrically connected thereto are in an integrated structure.
  • the above-mentioned "integrated structure” means that the two connected patterns are arranged in the same layer, and the two patterns are continuous and not separated.
  • the above-mentioned arrangement can make the first connecting line 1511 and the first voltage signal line VL1 electrically connected thereto be formed in one patterning process, thereby simplifying the preparation process of the light-emitting substrate 100.
  • the setting of the "integrated structure” can improve the reliability of the electrical connection between the first connecting line 1511 and the first voltage signal line VL1, and there is no need to set up other conductive structures, thereby reducing the preparation cost of the light-emitting substrate 100.
  • a plurality of light emitting device groups 122 in the same column of functional element groups 120 are arranged in at least one column; a column of light emitting device groups 122 is electrically connected to a first voltage signal line VL1 .
  • the plurality of light emitting device groups 122 in the same column of functional element groups 120 are arranged in multiple columns.
  • the plurality of light emitting device groups 122 in the same column of functional element groups 120 are arranged in two columns, as shown in FIGS. 3A to 3F .
  • the first voltage signal line VL1 connected to the two columns of the plurality of light emitting device groups 122 is located between the two columns of the plurality of light emitting device groups 122 .
  • a plurality of light emitting device groups 122 in the same column of functional element groups 120 are arranged in a row, as shown in FIG. 4A .
  • a first voltage signal line VL1 is used to provide a voltage signal of a working power supply to a column of light-emitting device groups 122, so that the light-emitting devices 123 in the column of light-emitting device groups 122 can emit light, which can simplify the circuit arrangement of the light-emitting substrate 100, thereby simplifying the structure of the light-emitting substrate 100 and reducing the difficulty of preparing the light-emitting substrate 100.
  • the orthographic projection of a column of light emitting device groups 122 connected to the first voltage signal line VL1 on the substrate 110 at least partially overlaps with the orthographic projection of the first voltage signal line VL1 on the substrate 110 .
  • the orthographic projection of a column of light emitting device groups 122 connected to the first voltage signal line VL1 on the substrate 110 partially overlaps with the orthographic projection of the first voltage signal line VL1 on the substrate 110 .
  • a plurality of light emitting devices 123 in a light emitting device group 122 are connected by wires, and the orthographic projection of the wires connecting the light emitting devices 123 on the substrate 110 partially overlaps with the orthographic projection of the first voltage signal line VL1 on the substrate 110 .
  • the signal line group 130 is usually located on a conductive layer close to the substrate 110, and the wires connecting the light-emitting devices 123 are usually located on a conductive layer away from the substrate 110; and the material of the two conductive layers usually includes copper.
  • the above-mentioned "negative voltage difference” means that the voltage of the wire connecting each light-emitting device 123 is greater than the voltage of the signal line located below each light-emitting device 123, thereby forming a negative voltage difference.
  • the positive projection of a column of light-emitting device groups 122 on the substrate 110 partially overlaps with the positive projection of the ground signal line on the substrate 110, and the ground signal line is usually at zero potential.
  • the voltage of the wire connecting each light-emitting device 123 is greater than the voltage of the ground signal line, thereby forming a negative voltage difference.
  • a “positive voltage difference” means that the voltage of the wire connecting each light emitting device 123 is less than the voltage of the signal line located below each light emitting device 123, thereby forming a positive voltage difference.
  • the voltage of the wire connecting each light emitting device 123 is less than the voltage of the first voltage signal line VL1 located below each light emitting device 123, thereby forming a positive voltage difference.
  • the orthographic projection of a column of light-emitting device groups 122 connected to the first voltage signal line VL1 on the substrate 110 partially overlaps with the orthographic projection of the first voltage signal line VL1 on the substrate 110.
  • the voltage of the first voltage signal line VL1 is greater than the voltage of the wire connecting each light-emitting device 123, thereby forming a positive voltage difference, thereby suppressing the migration and growth of copper ions in the two conductive layers, thereby further effectively reducing the probability of a short circuit between the two conductive layers, improving the yield, safety and stability of the light-emitting substrate 100, and extending the service life of the light-emitting substrate 100.
  • the light-emitting devices 123 included in the plurality of light-emitting device groups 122 are arranged into a plurality of rows along a first direction X, and are arranged into a plurality of columns along a second direction Y; any two adjacent rows of light-emitting devices 123 are staggered.
  • the distance between any two adjacent rows of light emitting devices 123 may be equal or unequal, and the embodiments of the present disclosure are not limited to this.
  • the light mixing vacancy area between any two adjacent columns of light emitting devices 123 can be reduced, thereby achieving a better light mixing effect of the light emitting substrate 100 .
  • the plurality of driving chips 121 in the same column of functional element groups 120 are arranged in a row along the first direction X.
  • the plurality of light emitting device groups 122 in the same column of functional element groups 120 are located on opposite sides of the plurality of driving chips 121 in the same column of functional element groups 120 along the first direction X.
  • multiple light-emitting device groups 122 in the same column of functional element groups 120 are arranged in two columns along the second direction Y.
  • the two columns of light-emitting device groups 122 are located on opposite sides of multiple driving chips 121 in the same column of functional element groups 120 along the second direction Y.
  • the two columns of light-emitting device groups 122 can emit light under the control of the driving signal transmitted by the same column of driving chip 121; when the number of columns of the light-emitting device groups 122 is the same, the number of signal line groups 130 required is relatively small, and the number of first voltage signal lines VL1 that need to extend from the functional area F to the binding area B and are electrically connected to the binding pins 140 located in the binding area B is reduced. At the same time, the number of required binding pins 140 is reduced, so that fewer binding areas B are required to set the binding pins 140, which effectively reduces the number of binding areas B and reduces the space occupied by the binding areas B.
  • the light-emitting substrate 100 When the light-emitting substrate 100 is applied to the display device 1, it can overcome the problem of insufficient space in some display devices 1 (for example, a laptop computer (Notebook)), improve the adaptability of the light-emitting substrate 100, and broaden the application scenarios of the light-emitting substrate 100.
  • some display devices 1 for example, a laptop computer (Notebook)
  • the first type of signal line 1301 includes a ground signal line VL2 , and the ground signal line VL2 is electrically connected to the driving chip 121 .
  • the plurality of first-type connection lines 150 include at least one second connection line 1512 .
  • the second connection line 1512 is electrically connected to the same end of the ground signal lines VL2 in at least two signal line groups 130 .
  • the voltage signal transmitted by the ground signal line VL2 may be a constant voltage signal.
  • the ground signal line VL2 is used to ground the driving chip 121 .
  • multiple light-emitting device groups 122 in the same column of functional element groups 120 are arranged into two columns along the second direction Y, that is, when each column of driving chips 121 controls two columns of light-emitting device groups 122, the ground signal line VL2 is located between the two columns of light-emitting device groups 122 controlled by driving chips 121 in different columns.
  • the plurality of first-type connection lines 150 may include one second connection line 1512 , or may include a plurality of second connection lines 1512 .
  • the second connection line 1512 may be used to connect any number of ground signal lines VL2 , or the second connection line 1512 may be used for all ground signal lines VL2 in the plurality of signal line groups 130 .
  • the number of ground signal lines VL2 connected to the same second connection line 1512 may be the same or different, and the embodiments of the present disclosure are not limited thereto.
  • the same second connection line 1512 can be used to connect two ground signal lines VL2, as shown in Figure 3B.
  • the same second connection line 1512 can be used to connect multiple ground signal lines VL2;
  • Figure 4A shows that the same second connection line 1512 can be used to connect four ground signal lines VL2.
  • the ground signal line VL2 is located in the functional area F, a ground signal line VL2 is electrically connected to a column of driving chips 121, and among the multiple ground signal lines VL2 electrically connected to the same second connection line 1512, at least one ground signal line VL2 is spaced apart from the binding pin 140, and some ground signal lines VL2 extend from the functional area F to the binding area B and are electrically connected to the binding pin 140 located in the binding area B.
  • one end of a ground signal line VL2 is electrically connected to the binding pin 140 in the binding area B, and the other end extends to the functional area F and is electrically connected to a column of driver chips 121.
  • the driver chip 121 is electrically connected to the light emitting device group 122, so that the ground signal line VL2 can be electrically connected to the light emitting device group 122 through the driver chip 121.
  • the driver chip 121 has at least one ground pin GND.
  • One end of the ground signal line VL2 is electrically connected to the printed circuit board through the binding pin 140, and the other end of the ground signal line VL2 is electrically connected to the ground pin GND of the driver chip 121 to ground the driver chip 121.
  • the second connection line 1512 and the ground signal line VL2 may be disposed on the same conductive layer.
  • the second connection line 1512 and the ground signal line VL2 can be arranged on different conductive layers.
  • the second connection line 1512 and the ground signal line VL2 can be arranged on two conductive layers respectively.
  • the materials of the second connection line 1512 and the ground signal line VL2 can be the same or different. The embodiments of the present disclosure are not limited to this.
  • the multiple ground signal lines VL2 electrically connected to the multi-column driver chip 121 are electrically connected through the second connecting line 1512.
  • the multiple ground signal lines VL2 connected by the second connecting line 1512 at least one ground signal line VL2 is spaced apart from the binding pin 140, and some ground signal lines VL2 are electrically connected to the binding pin 140 located in the binding area B through direct contact, so that the multi-column driver chip 121 can be grounded, reducing the number of ground signal lines VL2 that need to be directly electrically connected to the binding pin 140 in the binding area B, thereby reducing the number of binding pins 140 that need to be set, so that fewer binding areas B are required to set the binding pins 140, effectively reducing the number of binding areas B, and reducing the space occupied by the binding area B.
  • the light-emitting substrate 100 When the light-emitting substrate 100 is applied to the display device 1, it can overcome the problem of insufficient space in some display devices 1 (for example, a laptop computer (Notebook)), improve the adaptability of the light-emitting substrate 100, and broaden the application scenarios of the light-emitting substrate 100.
  • some display devices 1 for example, a laptop computer (Notebook)
  • the second connection line 1512 extends along the second direction Y and is located on a side of the functional area F close to the binding area B.
  • a plurality of ground signal lines VL2 connected to the same second connection line 1512 are arranged in parallel.
  • the second connecting line 1512 extends along the second direction Y and is electrically connected to the same end of the ground signal line VL2 in at least two signal line groups 130.
  • the multiple ground signal lines VL2 connected to the second connecting line 1512 at least one ground signal line VL2 is spaced apart from the binding pin 140, and only a portion of the ground signal lines VL2 are electrically connected to the binding pins 140 located in the binding area B through direct contact, thereby reducing the number of ground signal lines VL2 that need to be directly electrically connected to the binding pins 140 in the binding area B, thereby reducing the number of binding areas B.
  • the number of functional element groups 120 in each column is N, and the N driving chips in each column of functional element groups 120 are cascaded in sequence.
  • the signal line group 130 further includes at least one second-type signal line 1302 .
  • Each second-type signal line 1302 extends along the first direction X and is arranged at intervals along the second direction Y.
  • the light emitting substrate 100 further includes a plurality of second type connection lines 160.
  • the second type connection lines 160 are used to connect the second type signal lines 1302 in at least two signal line groups 130 that transmit the same signal.
  • the plurality of second-type connection lines 160 and the signal line group 130 may be arranged on the same conductive layer or on different conductive layers, for example, the plurality of second-type connection lines 160 and the signal line group 130 may be arranged on two conductive layers respectively.
  • the embodiments of the present disclosure are not limited to this.
  • the second-type connecting wire 160 can be used to connect the second-type signal wires 1302 transmitting the same signal in two signal wire groups 130, or can be used to connect the second-type signal wires 1302 transmitting the same signal in three signal wire groups 130, or the second-type signal wires 1302 transmitting the same signal in four signal wire groups 130.
  • the embodiments of the present disclosure are not limited to this.
  • the second-type signal lines 1302 transmitting the same signal in at least two signal line groups 130 are arranged in parallel through the second-type connecting lines 160; or the second-type signal lines 1302 transmitting the same signal in at least two signal line groups 130 are arranged in series through the second-type connecting lines 160.
  • At least one second-type signal line 1302 is spaced apart from the binding pin 140 .
  • At least one second-type signal line 1302 is spaced apart from the binding pin 140, and the two are not in contact in the binding area.
  • the at least one second-type signal line 1302 is indirectly connected to the binding pin 140 through the second-type connection line 160 electrically connected thereto and other second-type signal lines 1302 connected in series or in parallel thereto.
  • the signal provided by the printed circuit board can be transmitted to a column of functional element groups 120 connected to the at least one second-type signal line 1302 through the binding pin 140, other second-type signal lines 1302 connected in series or in parallel with the at least one second-type signal line 1302, and the second-type connection line 160 electrically connected to the at least one second-type signal line 1302, thereby realizing driving of the column of functional element groups 120.
  • second-type signal lines 1302 when there are four second-type signal lines 1302 electrically connected to the second-type connecting lines 160 , only one second-type signal line 1302 may be spaced apart from the binding pin 140 , or two or three second-type signal lines 1302 may be spaced apart from the binding pin 140 .
  • one of the second-class signal lines 1302 is electrically connected to the binding pin 140, and the flexible circuit board is electrically connected to the second-class signal line 1302 through the binding pin 140, so that the signal provided by the printed circuit board can be transmitted to at least two signal line groups 130 through the flexible circuit board, thereby realizing the driving of at least two functional element groups 120.
  • the light-emitting substrate 100 connects the second-type signal lines 1302 transmitting the same signal in at least two signal line groups 130 through the second-type connecting lines 160.
  • at least one second-type signal line 1302 is spaced apart from the binding pins 140, thereby reducing the number of second-type signal lines 1302 that need to be electrically connected to the binding pins 140.
  • the number of binding pins 140 that need to be set is reduced, and fewer binding areas B are required to set the binding pins 140, effectively reducing the number of binding areas B and reducing the space occupied by the binding areas B.
  • the light-emitting substrate 100 When the light-emitting substrate 100 is applied to the display device 1, it can overcome the problem of insufficient space in some display devices 1 (for example, a laptop computer (Notebook)), improve the adaptability of the light-emitting substrate 100, and broaden the application scenarios of the light-emitting substrate 100.
  • some display devices 1 for example, a laptop computer (Notebook)
  • the second type signal line 1302 includes a plurality of address signal lines DL, and any two adjacent driver chips 121 in each column of N driver chips are electrically connected via the address signal lines DL.
  • the plurality of second type connection lines 160 include at least one third connection line 1611. Any two adjacent columns of N driver chips in M columns are electrically connected via the third connection line 1611, where M ⁇ 2, and M is a positive integer.
  • the driver chip 121 has an input port Dis and an output port Dos.
  • One end of the address signal line DL is electrically connected to the input port Dis of one of the two adjacent driver chips 121
  • the other end of the address signal line DL is electrically connected to the output port Dos of the other of the two adjacent driver chips 121 .
  • the specific cascade structure of the N driver chips can be that, in the direction away from the binding area B along the functional area F, the input port Dis of the first-stage driver chip 121 is electrically connected to the binding pin 140 located in the binding area B, and except for the first-stage driver chip 121, the input port Dis of any stage driver chip 121 is electrically connected to the output port Dos of the previous stage driver chip 121 of the stage driver chip 121 through the address signal line DL; the output port Dos of the last stage driver chip 121 is electrically connected to an address signal line DL. In this way, the signal output by the printed circuit board can be transmitted to multiple driver chips 121 through the address signal line DL.
  • the plurality of second-type connection lines 160 may include one third connection line 1611 , or may include a plurality of third connection lines 1611 .
  • one third connection line 1611 is used to connect two columns of N driver chips.
  • FIG3C illustrates one row and two columns of driver chips. The two columns of driver chips are electrically connected via one third connection line 1611 .
  • the plurality of second-type connection lines 160 may include one third connection line 1611 , two columns of N driving chips are electrically connected via one third connection line 1611 .
  • the number of third connection lines 1611 electrically connected to the M columns of N driver chips may be M-1, and any two adjacent columns of N driver chips are connected through the third connection lines 1611; the M columns of N driver chips are connected in series through M-1 third connection lines 1611.
  • FIG. 4A illustrates two rows and four columns of driver chips. Any two adjacent columns of N driver chips in the four columns of driver chips are electrically connected through the third connection lines 1611. And the four columns of driver chips are connected in series through three third connection lines 1611.
  • the signal line group 130 also includes a signal output line FB, which is implemented by M-1 third connection lines 1611 to realize the M columns of N driver chips connected in series, wherein the address signal line DL connected to the first-level driver chip 121 of the first column of N driver chips extends from the functional area F to the binding area B, and is electrically connected to the binding pin 140 located in the binding area B; wherein one end of the Mth column of N driver chips is electrically connected to the third connection line 1611, and the other end is electrically connected to the output line FB, and the output line FB extends from the functional area F to the binding area B, and is electrically connected to the printed circuit board through the binding pin 140.
  • the signal output by the printed circuit board can be transmitted to the multiple driver chips 121 through the address signal line DL, and then fed back to the printed circuit board through the output line FB, thereby realizing the driving of the multiple driver chips 121.
  • any two adjacent columns of N driver chips in M columns of N driver chips are electrically connected through the third connecting line 1611.
  • the M columns of N driver chips only some columns of N driver chips are electrically connected to the binding pins 140 located in the binding area B through the signal output line FB, so that the driving signals can be provided for the multiple columns of driver chips 121, thereby reducing the number of address signal lines DL that need to be electrically connected to the binding pins 140 in the binding area B, thereby reducing the number of binding pins 140 that need to be set, so that fewer binding areas B are required to set the binding pins 140, effectively reducing the number of binding areas B, and reducing the space occupied by the binding areas B.
  • the light-emitting substrate 100 When the light-emitting substrate 100 is applied to the display device 1, it can overcome the problem of insufficient space in some display devices 1 (for example, a laptop computer (Notebook)), improve the adaptability of the light-emitting substrate 100, and broaden the application scenarios of the light-emitting substrate 100.
  • some display devices 1 for example, a laptop computer (Notebook)
  • the third connection line 1611 extends along the second direction Y and is located on a side of the functional area F away from the binding area B.
  • any two adjacent columns of N driver chips in M columns of N driver chips are connected through the third connection line 1611, thereby realizing the series arrangement of M columns of N driver chips.
  • the address signal line DL connected to the last-level driver chip 121 of one column of N driver chips is electrically connected to the address signal line DL connected to the last-level driver chip 121 of another column of N driver chips through a third connection line 1611.
  • the address signal line DL connected to the first-level driver chip 121 of one column of N driver chips is electrically connected to the address signal line DL connected to the first-level driver chip 121 of another column of N driver chips through a third connection line 1611.
  • M columns of N driver chips are connected via a third connecting line 1611.
  • M columns of N driver chips only some columns of N driver chips are electrically connected to the binding pins 140 located in the binding area B via the address signal lines DL, thereby reducing the number of address signal lines DL that need to be electrically connected to the binding pins 140 in the binding area B, thereby reducing the number of binding areas B.
  • the third connecting line 1611 is electrically connected to the first driver chip 121 of one of the N driver chips in two adjacent columns, and passes through the gap between the functional element groups 120 in two adjacent columns to be electrically connected to the Nth driver chip 121 of the other of the N driver chips in the two adjacent columns.
  • the third connection line 1611 is made of the same material as the address signal line DL and is disposed in the same layer, that is, in the same conductive layer.
  • the material of the third connection line 1611 and the material of the address signal line DL may both be metal, for example, the metal may be copper.
  • the third connection line 1611 and the address signal line DL electrically connected thereto are in an integrated structure.
  • the third connection line 1611 and the address signal line DL electrically connected thereto can be formed in one patterning process, thereby simplifying the manufacturing process of the light-emitting substrate 100.
  • the setting of the "integrated structure" can improve the reliability of the electrical connection between the third connection line 1611 and the address signal line DL, and does not require the setting of other conductive structures, thereby reducing the manufacturing cost of the light-emitting substrate 100.
  • the third connection line 1611 and the address signal line DL may be arranged in different conductive layers.
  • the third connection line 1611 and the address signal line DL may be arranged on two conductive layers respectively.
  • the materials of the third connection line 1611 and the address signal line DL may be the same or different. The embodiments of the present disclosure are not limited to this.
  • the third connecting line 1611 adopts a winding method to pass through the gap between two adjacent columns of functional element groups 120 to achieve electrical connection between two columns of N driver chips.
  • the third connecting line 1611 only the address signal lines DL electrically connected to the N driver chips in some columns are electrically connected to the binding pins 140 located in the binding area B, so as to provide driving signals for the multiple columns of driver chips 121, thereby reducing the number of address signal lines DL that need to be electrically connected to the binding pins 140 in the binding area B, thereby reducing the number of binding pins 140 that need to be set, thereby reducing the number of binding areas B and reducing the space occupied by the binding area B.
  • the light-emitting substrate 100 When the light-emitting substrate 100 is applied to the display device 1, it can overcome the problem of insufficient space in some display devices 1 (for example, a laptop computer (Notebook)), improve the adaptability of the light-emitting substrate 100, and broaden the application scenarios of the light-emitting substrate 100.
  • some display devices 1 for example, a laptop computer (Notebook)
  • the second type of signal line 1302 includes: a second voltage signal line VL3 , and the second voltage signal line VL3 is electrically connected to the driving chip 121 .
  • the plurality of second-type connection lines 160 include at least one fourth connection line 1612 .
  • the second voltage signal lines VL3 connected to the M columns of N driving chips at least two second voltage signal lines VL3 are electrically connected through the fourth connection line 1612 .
  • the signal transmitted by the second voltage signal line VL3 may be a constant voltage signal.
  • the second voltage signal line VL3 is electrically connected to the driving chip 121 to supply power to the driving chip 121 .
  • the plurality of second-type connection lines 160 may include one fourth connection line 1612 , or may include a plurality of fourth connection lines 1612 .
  • the number of second voltage signal lines VL3 connected to the same fourth connection line 1612 may be the same or different, and the embodiments of the present disclosure do not limit this.
  • the number of second voltage signal lines VL3 connected to the M columns of N driver chips is M, and the same fourth connection line 1612 can be used to connect two of the M second voltage signal lines VL3.
  • the same fourth connection line 1612 can be used to connect multiple second voltage signal lines VL3 of the M second voltage signal lines VL3.
  • FIG3D and FIG4A illustrate that the same fourth connection line 1612 can be used to connect two second voltage signal lines VL3.
  • the second voltage signal line VL3 is located in the functional area F, a second voltage signal line VL3 is electrically connected to a column of driving chips 121, and among the multiple second voltage signal lines VL3 electrically connected to the same fourth connecting line 1612, at least one second voltage signal line VL3 is spaced apart from the binding pin 140, and some second voltage signal lines VL3 extend from the functional area F to the binding area B, and are electrically connected to the binding pin 140 located in the binding area B through direct contact.
  • one end of a second voltage signal line VL3 is electrically connected to the binding pin 140 in the binding area B, and the other end extends to the functional area F and is electrically connected to a column of driver chips 121.
  • the driver chip 121 is electrically connected to the light emitting device group 122, so that the second voltage signal line VL3 can be electrically connected to the light emitting device group 122 through the driver chip 121.
  • the driver chip 121 has a power pin Vcc.
  • One end of the second voltage signal line VL3 is electrically connected to the power supply outside the light-emitting substrate 100 through the binding pin 140 and the printed circuit board, and the other end is electrically connected to the power pin Vcc of the driver chip 121, so that the second voltage signal line VL3 can realize power supply for the driver chip 121.
  • the fourth connection line 1612 and the second voltage signal line VL3 may be disposed on the same conductive layer.
  • the fourth connection line 1612 and the second voltage signal line VL3 can be arranged in different conductive layers, for example, the fourth connection line 1612 and the second voltage signal line VL3 can be arranged on two conductive layers respectively. In this case, the materials of the fourth connection line 1612 and the second voltage signal line VL3 can be the same or different.
  • the embodiments of the present disclosure are not limited to this.
  • the second voltage signal lines VL3 connecting the M columns of N driver chips at least two second voltage signal lines VL3 are electrically connected through the fourth connection line 1612, and among the multiple second voltage signal lines VL3 connected by the fourth connection line 1612, at least one second voltage signal line VL3 is spaced apart from the binding pin 140, and some second voltage signal lines VL3 are electrically connected to the binding pin 140 located in the binding area B through direct contact, thereby enabling power supply to the multiple columns of driver chips 121, reducing the number of second voltage signal lines VL3 that need to be directly electrically connected to the binding pin 140 in the binding area B, thereby reducing the number of binding pins 140 that need to be set, thereby requiring fewer binding areas B to set the binding pins 140, effectively reducing the number of binding areas B, and reducing the space occupied by the binding areas B.
  • the light-emitting substrate 100 When the light-emitting substrate 100 is applied to the display device 1, it can overcome the problem of insufficient space in some display devices 1 (for example, a laptop computer (Notebook)), improve the adaptability of the light-emitting substrate 100, and broaden the application scenarios of the light-emitting substrate 100.
  • some display devices 1 for example, a laptop computer (Notebook)
  • the fourth connection line 1612 extends along the second direction Y and is located on a side of the functional area F close to the binding area B (ie, the ground side of the light-emitting substrate).
  • the fourth connection line 1612 is electrically connected to the same end of at least two of the second voltage signal lines VL3 connected to the M columns of N driving chips.
  • At least two second voltage signal lines VL3 connected to the same fourth connection line 1612 are arranged in parallel.
  • the fourth connection line 1612 and the second voltage signal line VL3 can be arranged on different conductive layers, for example, the fourth connection line 1612 and the second voltage signal line VL3 can be arranged on two conductive layers respectively.
  • the material of the fourth connection line 1612 and the material of the second voltage signal line VL3 can be the same or different.
  • the embodiments of the present disclosure are not limited to this.
  • the fourth connecting line 1612 extends along the second direction Y and is electrically connected to the same end of at least two of the second voltage signal lines VL3 connecting the M columns of N driver chips, and among the multiple second voltage signal lines VL3 connected by the fourth connecting line 1612, at least one second voltage signal line VL3 is spaced apart from the binding pin 140, and some of the second voltage signal lines VL3 are electrically connected to the binding pins 140 located in the binding area B through direct contact, thereby enabling power supply to the multiple columns of driver chips 121, reducing the number of second voltage signal lines VL3 that need to be directly electrically connected to the binding pins 140 in the binding area B, thereby reducing the number of binding pins 140 that need to be set, thereby requiring fewer binding areas B to set the binding pins 140, effectively reducing the number of binding areas B.
  • the fourth connection line 1612 is electrically connected to two adjacent second voltage signal lines VL3 of the second voltage signal lines VL3 connected to the N driving chips in the M columns.
  • the fourth connection line 1612 is electrically connected to a first end of one of the two adjacent second voltage signal lines VL3, passes through a gap between two adjacent columns of functional element groups 120, and is electrically connected to a second end of the other of the two adjacent second voltage signal lines VL3.
  • two second voltage signal lines VL3 connected to the same fourth connection line 1612 are connected in series.
  • the number of second voltage signal lines VL3 electrically connected to the M columns of N driver chips is M, and the M second voltage signal lines VL3 are connected in series through M-1 fourth connection lines 1612.
  • FIG4A illustrates two rows and four columns of driver chips.
  • the number of second voltage signal lines VL3 connected to the four columns of driver chips is four, and the four second voltage signal lines VL3 are connected in series through three fourth connection lines 1612.
  • the fourth connection line 1612 and the second voltage signal line VL3 can be arranged in different conductive layers, for example, the fourth connection line 1612 and the second voltage signal line VL3 can be arranged on two conductive layers respectively.
  • the material of the fourth connection line 1612 and the material of the second voltage signal line VL3 can be the same or different. The embodiments of the present disclosure are not limited to this.
  • the material of the fourth connection line 1612 is the same as that of the second voltage signal line VL3 and they are disposed in the same layer, that is, disposed in the same conductive layer.
  • the material of the fourth connection line 1612 and the material of the second voltage signal line VL3 may both be metal, for example, the metal may be copper.
  • the fourth connection line 1612 and the second voltage signal line VL3 electrically connected thereto are in an integrated structure.
  • the fourth connection line 1612 and the second voltage signal line VL3 electrically connected thereto can be formed in one patterning process, thereby simplifying the preparation process of the light-emitting substrate 100.
  • the setting of the "integrated structure" can improve the reliability of the electrical connection between the fourth connection line 1612 and the second voltage signal line VL3, and there is no need to set up other conductive structures, thereby reducing the preparation cost of the light-emitting substrate 100.
  • first end and second end are relative.
  • first end of the second voltage signal line VL3 refers to the end of the second voltage signal line VL3 away from the binding area B
  • second end of the second voltage signal line VL3 refers to the end of the second voltage signal line VL3 close to the binding area B.
  • first end of the second voltage signal line VL3 refers to the end of the second voltage signal line VL3 close to the binding area B
  • second end of the second voltage signal line VL3 refers to the end of the second voltage signal line VL3 away from the binding area B.
  • the fourth connecting line 1612 adopts a winding method to pass through the gap between two adjacent columns of functional element groups 120, thereby realizing the electrical connection between two adjacent second voltage signal lines VL3 among the second voltage signal lines VL3 connecting the N driver chips in the M columns.
  • At least one second voltage signal line VL3 is arranged at intervals with the binding pin 140, and some second voltage signal lines VL3 are electrically connected to the binding pins 140 located in the binding area B through direct contact, thereby realizing power supply for the multiple columns of driver chips 121, reducing the number of second voltage signal lines VL3 that need to be directly electrically connected to the binding pins 140 in the binding area B, thereby reducing the number of binding pins 140 that need to be set, thereby reducing the number of binding areas B, and reducing the space occupied by the binding area B.
  • the light-emitting substrate 100 When the light-emitting substrate 100 is applied to the display device 1, it can overcome the problem of insufficient space in some display devices 1 (for example, a laptop computer (Notebook)), improve the adaptability of the light-emitting substrate 100, and broaden the application scenarios of the light-emitting substrate 100.
  • some display devices 1 for example, a laptop computer (Notebook)
  • the fourth connecting line 1612 and the second voltage signal line VL3 can be set in the same conductive layer or in different conductive layers, thereby realizing flexible wiring of the light-emitting substrate 100; when the fourth connecting line 1612 and the second voltage signal line VL3 are set in the same conductive layer, the steps of patterning the conductive layer can be reduced, thereby simplifying the preparation process of the light-emitting substrate 100, reducing the number of masks, reducing the cost of the light-emitting substrate 100, and also reducing the occurrence of short circuits and other adverse failures of the light-emitting substrate 100, thereby improving the yield rate of the light-emitting substrate 100.
  • the second type signal line 1302 includes a data signal line VL4, and the data signal line VL4 is electrically connected to the driving chip 121.
  • the plurality of second type connection lines 160 include at least one fifth connection line 1613.
  • the data signal lines VL4 connected to the above-mentioned M columns and N driving chips at least two data signal lines VL4 are electrically connected through the fifth connection line 1613.
  • the data signal line VL4 is used to transmit a data signal.
  • the plurality of second-type connection lines 160 may include one fifth connection line 1613 , or may include a plurality of fifth connection lines 1613 .
  • the number of data signal lines VL4 connected to the same fifth connection line 1613 may be the same or different, and the embodiments of the present disclosure are not limited thereto.
  • the same fifth connection line 1613 may be used to connect two data signal lines VL4.
  • the number of data signal lines VL4 connected to the above-mentioned M columns of N driving chips is M, and the same fifth connection line 1613 can be used to connect two data signal lines VL4 among the M data signal lines VL4.
  • the same fifth connection line 1613 can be used to connect multiple data signal lines VL4 among the M data signal lines VL4.
  • FIG. 3E and FIG. 4A illustrate that the same fourth connection line 1612 can be used to connect two data signal lines VL4.
  • the data signal line VL4 is located in the functional area F, one data signal line VL4 is electrically connected to a column of driver chips 121, and among the multiple data signal lines VL4 electrically connected to the same fifth connection line 1613, at least one data signal line VL4 is spaced apart from the binding pin 140, and some data signal lines VL4 extend from the functional area F to the binding area B and are electrically connected to the binding pin 140 located in the binding area B.
  • one end of a data signal line VL4 is electrically connected to the binding pin 140 in the binding area B, and the other end extends to the functional area F and is electrically connected to a column of driver chips 121.
  • the driver chip 121 is electrically connected to the light emitting device group 122, so that the data signal line VL4 can be electrically connected to the light emitting device group 122 through the driver chip 121.
  • the driver chip 121 has a data pin Dip.
  • One end of the data signal line VL4 is electrically connected to the printed circuit board through the binding pin 140 , and the other end of the data signal line VL4 is electrically connected to the data pin Dip of the driver chip 121 (one or more).
  • the driver chip 121 has two data ports Data.
  • One of the two data ports Data is a data input port, and the other is a data output port.
  • the data signal line VL4 may include a plurality of sub-data signal lines.
  • the sub-data signal line is used to connect two adjacent driver chips 121.
  • One end of the sub-data signal line is electrically connected to the data output port of one of the two adjacent driver chips 121, and the other end of the sub-data signal line is electrically connected to the data input port of the other of the two adjacent driver chips 121.
  • the fifth connection line 1613 and the data signal line VL4 may be disposed on the same conductive layer.
  • the fifth connection line 1613 and the data signal line VL4 may be arranged on different conductive layers.
  • the fifth connection line 1613 and the data signal line VL4 may be arranged on two conductive layers respectively.
  • the materials of the fifth connection line 1613 and the data signal line VL4 may be the same or different. The embodiments of the present disclosure are not limited to this.
  • At least two data signal lines VL4 are electrically connected through the fifth connecting line 1613, and among the multiple data signal lines VL4 connected to the fifth connecting line 1613, at least one data signal line VL4 is spaced apart from the binding pin 140, and some data signal lines VL4 are electrically connected to the binding pin 140 located in the binding area B through direct contact, so as to provide data signals for the multiple columns of driver chips 121, thereby reducing the number of data signal lines VL4 that need to be directly electrically connected to the binding pin 140 in the binding area B, thereby reducing the number of binding pins 140 that need to be set, so that fewer binding areas B are required to set the binding pins 140, effectively reducing the number of binding areas B, and reducing the space occupied by the binding areas B.
  • the light-emitting substrate 100 When the light-emitting substrate 100 is applied to the display device 1, it can overcome the problem of insufficient space in some display devices 1 (for example, a laptop computer (Notebook)), improve the adaptability of the light-emitting substrate 100, and broaden the application scenarios of the light-emitting substrate 100.
  • some display devices 1 for example, a laptop computer (Notebook)
  • the fifth connection line 1613 extends along the second direction Y and is located on a side of the functional area F close to the binding area B.
  • the fifth connection line 1613 is electrically connected to the same end of at least two of the data signal lines VL4 connected to the M columns of N driving chips.
  • the same fifth connection line 1613 is used to connect two data signal lines VL4 , and the fifth connection line 1613 and the two data signal lines VL4 connected to the fifth connection line 1613 are S-shaped as a whole.
  • a plurality of data signal lines VL4 connected to the same fifth connection line 1613 are arranged in parallel.
  • the fifth connecting line 1613 extends along the second direction Y and is electrically connected to the same end of at least two of the data signal lines VL4 connecting the above-mentioned M columns of N driving chips.
  • the multiple data signal lines VL4 connected by the fifth connecting line 1613 at least one data signal line VL4 is spaced apart from the binding pin 140, and some data signal lines VL4 are electrically connected to the binding pins 140 located in the binding area B through direct contact, thereby reducing the number of ground signal lines VL2 that need to be directly electrically connected to the binding pins 140 in the binding area B, thereby reducing the number of binding areas B.
  • the fifth connection line 1613 is electrically connected to two adjacent data signal lines VL4 of the data signal lines VL4 connected to the N driving chips in the M columns.
  • the fifth connection line 1613 is electrically connected to a first end of one of the two adjacent data signal lines VL4, passes through a gap between two adjacent columns of functional element groups 120, and is electrically connected to a second end of the other of the two adjacent data signal lines VL4.
  • the number of data signal lines VL4 connected to the above-mentioned M columns of N driver chips is M, and the M data signal lines VL4 are connected in series through M-1 data signal lines VL4.
  • FIG. 4A illustrates two rows and four columns of driver chips.
  • the number of data signal lines VL4 connected to the four columns of driver chips is four, and the four data signal lines VL4 are connected in series through three fifth connection lines 1613.
  • the fifth connection line 1613 and the data signal line VL4 can be arranged on different conductive layers, for example, the fifth connection line 1613 and the data signal line VL4 can be arranged on two conductive layers respectively.
  • the material of the fifth connection line 1613 and the material of the data signal line VL4 can be the same or different. The embodiments of the present disclosure are not limited to this.
  • the material of the fifth connection line 1613 is the same as that of the data signal line VL4 and they are disposed in the same layer, that is, disposed in the same conductive layer, as shown in FIG. 4A .
  • the material of the fifth connection line 1613 and the material of the data signal line VL4 may both be metal, for example, the metal may be copper.
  • the fifth connection line 1613 and the data signal line VL4 electrically connected thereto are in an integrated structure.
  • the fifth connection line 1613 and the data signal line VL4 electrically connected thereto can be formed in one patterning process, thereby simplifying the manufacturing process of the light-emitting substrate 100.
  • the setting of the "integrated structure" can improve the reliability of the electrical connection between the fifth connection line 1613 and the data signal line VL4, and does not require the setting of other conductive structures, thereby reducing the manufacturing cost of the light-emitting substrate 100.
  • the fifth connecting line 1613 adopts a winding method to pass through the gap between two adjacent columns of functional element groups 120, thereby realizing the electrical connection between two adjacent data signal lines VL4 among the data signal lines VL4 connecting the M columns of N driver chips.
  • At least one data signal line VL4 is arranged at intervals with the binding pin 140, and some data signal lines VL4 are electrically connected to the binding pins 140 located in the binding area B through direct contact, so as to provide data signals for the multiple columns of driver chips 121, thereby reducing the number of data signal lines VL4 that need to be directly electrically connected to the binding pins 140 in the binding area B, thereby reducing the number of binding pins 140 that need to be set, thereby reducing the number of binding areas B, and reducing the space occupied by the binding area B.
  • the light-emitting substrate 100 When the light-emitting substrate 100 is applied to the display device 1, it can overcome the problem of insufficient space in some display devices 1 (for example, a laptop computer (Notebook)), improve the adaptability of the light-emitting substrate 100, and broaden the application scenarios of the light-emitting substrate 100.
  • some display devices 1 for example, a laptop computer (Notebook)
  • the fifth connecting line 1613 and the data signal line VL4 can be set in the same conductive layer or in different conductive layers, thereby realizing flexible wiring of the light-emitting substrate 100; when the fifth connecting line 1613 and the data signal line VL4 are set in the same conductive layer, the steps of patterning the conductive layer can be reduced, thereby simplifying the preparation process of the light-emitting substrate 100, reducing the number of mask plates, reducing the cost of the light-emitting substrate 100, and also reducing the occurrence of short circuits and other adverse failures of the light-emitting substrate 100, thereby improving the yield rate of the light-emitting substrate 100.
  • multiple light-emitting device groups 122 in the same column of functional element groups 120 are arranged into n columns along the second direction Y, that is, each column of driving chips 121 controls n columns of light-emitting device groups 122, and the number of columns of light-emitting device groups 122 controlled by the M columns of N driving chips is M ⁇ n, and the M ⁇ n first voltage signal lines VL1 connected to the M ⁇ n columns of light-emitting device groups 122 are arranged in parallel.
  • each column of driver chips 121 controls two columns of light-emitting device groups 122 , and two columns of N driver chips are arranged in series through a third connecting line 1611 , and the two columns of N driver chips control four columns of light-emitting device groups 122 .
  • the four first voltage signal lines VL1 connected to the four columns of light-emitting device groups 122 are arranged in parallel.
  • each column of driver chips 121 controls a column of light-emitting device groups 122 , and four columns of N driver chips are arranged in series through a third connecting line 1611 .
  • the four columns of N driver chips control four columns of light-emitting device groups 122 .
  • the four first voltage signal lines VL1 connected to the four columns of light-emitting device groups 122 are arranged in parallel.
  • a column of N driver chips is connected to a second voltage signal line VL3, and M columns of N driver chips are connected to M second voltage signal lines VL3 in parallel.
  • two columns of N driving chips are connected in series via the third connection line 1611 , and two second voltage signal lines VL3 connected to the two columns of N driving chips are connected in parallel.
  • a column of N driver chips is connected to a second voltage signal line VL3, and M columns of N driver chips are connected to M second voltage signal lines VL3 in series.
  • FIG. 4A For example, as shown in FIG. 4A , four columns of N driving chips are arranged in series through the third connection line 1611 , and four second voltage signal lines VL3 connected to the four columns of N driving chips are arranged in series.
  • a column of N driver chips is connected to a ground signal line VL2, and M columns of N driver chips are connected to M ground signal lines VL2 in parallel.
  • two columns of N driving chips are connected in series via a third connection line 1611 , and two ground signal lines VL2 connected to the two columns of N driving chips are connected in parallel.
  • a column of N driver chips is connected to a data signal line VL4, and the M data signal lines VL4 connected to the M columns of N driver chips are arranged in series, and any two data signal lines VL4 among the M data signal lines VL4 and the fifth connecting line 1613 connecting the any two data signal lines VL4 are overall S-shaped, as shown in Figure 4A.
  • multiple first-type connecting lines 150 may simultaneously include a first connecting line 1511 and a second connecting line 1512; multiple second-type connecting lines 160 may simultaneously include one or more of a third connecting line 1611, a fourth connecting line 1612 and a fifth connecting line 1613.
  • the plurality of first-type connection lines 150 may include a first connection line 1511 and a second connection line 1512 ; and the plurality of second-type connection lines 160 may include a third connection line 1611 , a fourth connection line 1612 and a fifth connection line 1613 .
  • connection lines 1511 and the second connection lines 1512 included in the multiple first-type connection lines 150 and the more the third connection lines 1611, the fourth connection lines 1612 and the fifth connection lines 1613 included in the multiple second-type connection lines 160, the more the number of binding pins 140 can be reduced, and the fewer the number of binding areas B.
  • the plurality of first-type connection lines 150 may include a first connection line 1511 and a second connection line 1512 ; and the plurality of second-type connection lines 160 may include a third connection line 1611 , a fourth connection line 1612 and a fifth connection line 1613 .
  • first voltage signal lines VL1 connected by the first connection line 1511 only one first voltage signal line VL1 is electrically connected to the binding pin 140; among the four ground signal lines VL2 connected by the second connection line 1512, only one ground signal line VL2 is electrically connected to the binding pin 140; among the four second voltage signal lines VL3 connected by the fourth connection line 1612, only one second voltage signal line is electrically connected to the binding pin 140; among the four data signal lines VL4 connected by the fifth connection line 1613, only one data signal line VL4 is electrically connected to the binding pin 140; among the four columns of N driver chips, the address signal line DL connected to the first-level driver chip 121 of one column of N driver chips extends from the functional area F to the binding area B, and is electrically connected to the binding pin 140 located in the binding area B; one end of the other column of N driver chips is electrically connected to the third connection line 1611, and the other end is electrically connected to the output line FB, and the output line FB extends from the
  • the light-emitting substrate 100 connects the first-class signal lines 1301 transmitting the same signal in at least two signal line groups 130 through the first-class connecting lines 150.
  • the multiple first-class signal lines 1301 electrically connected to the first-class connecting lines 150 only a part of the first-class signal lines 1301 are electrically connected to the binding pins 140, thereby reducing the number of first-class signal lines 1301 that need to be electrically connected to the binding pins 140.
  • the number of binding pins 140 that need to be set is reduced, so that fewer binding areas B are required to set the binding pins 140, thereby effectively reducing the number of binding areas B and meeting the requirements of narrow bezel design of some products.

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Abstract

一种发光基板（100），具有沿第一方向间隔排列的功能区和绑定区；发光基板（100）包括：衬底（110）；位于衬底（110）一侧、且位于功能区的多个功能元件组（120）；多个功能元件组（120）分别沿第一方向排列成多行，且沿第二方向排列成多列，第一方向和第二方向相交；位于功能区的多个信号线组（130），与多个功能元件组（120）位于衬底（110）的同一侧，一个信号线组（130）与一列功能元件组（120）电连接；信号线组（130）包括至少一条第一类信号线（1301），各第一类信号线（1301）沿第一方向延伸，且沿第二方向间隔排布；多条第一类连接线（150），第一类连接线（150）用于连接至少两个信号线组（130）中传输相同信号的第一类信号线（1301）；位于绑定区的多个绑定引脚（140）；其中，与第一类连接线（150）电连接的多条第一类信号线（1301）中，至少一条第一类信号线（1301）与绑定引脚（140）间隔设置。

Description

发光基板、背光模组及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种发光基板、背光模组及显示装置。
背景技术
微型发光二极管，例如Mini-LED(Mini Light-Emitting Diode，迷你发光二极管)和Micro LED(Micro Light-Emitting Diode，微型发光二极管)，其尺寸小于500μm，由于其具有更小的尺寸和超高的亮度、寿命长等优势，因此在显示领域使用趋势明显增大。
发明内容
一方面，提供一种发光基板，具有沿所述第一方向间隔排列的功能区和绑定区。所述发光基板包括：衬底；位于所述衬底一侧、且位于所述功能区的多个功能元件组；所述多个功能元件组分别沿第一方向排列成多行，且沿第二方向排列成多列，所述第一方向和所述第二方相交；位于所述功能区的多个信号线组，与所述多个功能元件组位于所述衬底的同一侧，一个信号线组与一列功能元件组电连接；所述信号线组包括至少一条第一类信号线，各所述第一类信号线沿所述第一方向延伸，且沿第二方向间隔排布；多条第一类连接线，第一类连接线用于连接至少两个信号线组中传输相同信号的第一类信号线；位于所述绑定区的多个绑定引脚；其中，与所述第一类连接线电连接的多条第一类信号线中，至少一条第一类信号线与绑定引脚间隔设置。
在一些实施例中，功能元件组包括至少一个发光器件组；所述第一类信号线包括至少一条第一电压信号线，所述第一电压信号线与所述发光器件组电连接；所述多条第一类连接线包括至少一条第一连接线；所述第一连接线，与所述至少两个信号线组中的第一电压信号线的同一端电连接。
在一些实施例中，所述第一连接线沿所述第二方向延伸，且位于所述功能区远离所述绑定区的一侧。
在一些实施例中，同一列功能元件组中的多个发光器件组排列为至少一列；一列发光器件组与一条所述第一电压信号线电连接。
在一些实施例中，与该第一电压信号线连接的一列发光器件组在所述衬底上的正投影，与该第一电压信号线在所述衬底上的正投影至少部分交叠。
在一些实施例中，所述功能元件组还包括驱动芯片，同一列功能元件组中的多个驱动芯片沿所述第一方向排列为一列；所述同一列功能元件组中的多个发光器件组，位于所述同一列功能元件组中的多个驱动芯片沿所述第一方 向的相对两侧。
在一些实施例中，功能元件组包括驱动芯片；所述第一类信号线包括接地信号线，所述接地信号线与所述驱动芯片电连接；所述多条第一类连接线包括至少一条第二连接线；所述第二连接线，与所述至少两个信号线组中的接地信号线的同一端电连接。
在一些实施例中，所述第二连接线沿所述第二方向延伸，且位于所述功能区靠近所述绑定区的一侧。
在一些实施例中，每个功能元件组包括一个驱动芯片，每列功能元件组的数目为N，所述每列功能元件组中的N个驱动芯片依次级联；所述信号线组还包括至少一条第二类信号线，各所述第二类信号线沿所述第一方向延伸，且沿第二方向间隔排布；所述发光基板还包括：多条第二类连接线，第二类连接线用于连接至少两个信号线组中传输相同信号的第二类信号线；位于所述绑定区的多个绑定引脚；其中，与所述第二类连接线电连接的多条第二类信号线中，至少一条第二类信号线与绑定引脚间隔设置。
在一些实施例中，所述N个驱动芯片中任意相邻的两个驱动芯片之间通过所述地址信号线级联；所述多条第二类连接线还包括至少一条第三连接线；M列相邻的功能元件组中，两个分别属于相邻两列功能元件组的驱动芯片通过所述第三连接线级联，其中，M≥2，且M为正整数。
在一些实施例中，所述第三连接线与所述相邻两列所述N个驱动芯片中的一者的第1个驱动芯片电连接，并穿过相邻两列功能元件组之间的间隙，与所述相邻两列所述N个驱动芯片中的另一者的第N个驱动芯片电连接。
在一些实施例中，所述第三连接线沿所述第二方向延伸，且位于所述功能区远离所述绑定区的一侧。
在一些实施例中，所述第二类信号线包括第二电压信号线，所述第二电压信号线与所述驱动芯片电连接；所述多条第二类连接线包括至少一条第四连接线；与所述M列所述N个驱动芯片的连接的所述第二电压信号线中，至少两条第二电压信号线通过所述第四连接线相连接。
在一些实施例中，所述第四连接线沿所述第二方向延伸，且位于所述功能区靠近所述绑定区的一侧。
在一些实施例中，所述第四连接线与所述M列所述N个驱动芯片的连接的所述第二电压信号线中的相邻两条第二电压信号线电连接；其中，所述第四连接线与所述相邻两条第二电压信号线中的一条的第一端电连接，并穿过相邻两列功能元件组之间的间隙，与所述相邻两条第二电压信号线中的另一条 的第二端电连接。
在一些实施例中，所述第二类信号线包括数据信号线，所述数据信号线与所述驱动芯片电连接；所述多条第二类连接线包括至少一条第五连接线；与所述M列所述N个驱动芯片的连接的所述数据信号线中，至少两条数据信号线通过所述第五连接线相连接。
在一些实施例中，所述第五连接线沿所述第二方向延伸，且位于所述功能区靠近所述绑定区的一侧。
在一些实施例中，所述第五连接线与所述M列所述N个驱动芯片的连接的所述数据信号线中的相邻两条数据信号线电连接；其中，所述第五连接线与所述相邻两条数据信号线中的一条的第一端电连接，并穿过相邻两列功能元件组之间的间隙，与所述相邻两条数据信号线中的另一条的第二端电连接。
在一些实施例中，功能元件组包括至少一个发光器件组，所述发光器件组包括多个发光器件；多个所述发光器件组所包括的发光器件沿第一方向排列成多行，且沿第二方向排列成多列；任意相邻的两行发光器件错开设置。
另一方面，提供一种背光模组，包括：如上述任一实施例中所述的发光基板，以及位于所述发光基板的出光侧的光学膜片。
另一方面，提供一种显示装置，包括：如上述实施例中所述的背光模组；位于所述背光模组出光侧的阵列基板；以及，位于所述阵列基板远离所述背光模组一侧的彩膜基板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程等的限制。
图1A为根据本公开的一些实施例中的一种显示装置的结构图；
图1B为根据本公开的一些实施例中的另一种显示装置的结构图；
图2为根据本公开的一些实施例中的一种背光模组的结构图；
图3A为本公开的一些实施例中的一种发光基板的结构图；
图3B为本公开的一些实施例中的另一种发光基板的结构图；
图3C为本公开的一些实施例中的又一种发光基板的结构图；
图3D为本公开的一些实施例中的又一种发光基板的结构图；
图3E为本公开的一些实施例中的又一种发光基板的结构图；
图3F为本公开的一些实施例中的又一种发光基板的结构图；
图3G为本公开的一些实施例中的一种发光基板的地侧的局部结构图；
图3H为本公开的一些实施例中的一种发光基板的天侧的局部结构图；
图4A为本公开的一些实施例中的又一种发光基板的结构图；
图4B为本公开的一些实施例中的另一种发光基板的天侧的局部结构图；
图4C为本公开的一些实施例中的另一种发光基板的地侧的局部结构图；
图5为本公开的一些实施例中的又一种发光基板的局部结构图；
图6为本公开的一些实施例中的又一种发光基板的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
图1A为根据一些实施例的显示装置的结构图。
如图1A所示，本公开的实施例提供了一种显示装置1。在一些示例中，显示装置1可以为具有图像显示功能的产品。
在一些示例中，显示装置1可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理、手持式或便携式计算机、全球定位系统接收器/导航器、相机、视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的 显示器)等。
在另一些示例中，显示装置1也可以为不具有图像显示功能的产品。例如，显示装置1可以为影像板等。
本公开的实施例对显示装置1不做进一步限定，下面以显示装置1为具有图像显示功能的产品为例，进行举例说明。
在一些示例中，上述显示装置1可以为LCD(Liquid Crystal Display，液晶显示装置)。
在一些示例中，如图1B所示，显示装置1包括：背光模组10，位于背光模组10出光侧的阵列基板20，以及，位于阵列基板20远离背光模组10一侧的彩膜基板30。
示例性的，上述背光模组10可以作为光源，用于提供背光。例如背光模组10提供的背光可以为白光或蓝光。
例如，背光模组10的出光侧，指的是，背光模组10发出光线的一侧。
示例性的，阵列基板20可以包括多个像素驱动电路、多个像素电极，该多个像素驱动电路例如呈阵列状排布。多个像素驱动电路与多个像素电极一一对应电连接，像素驱动电路为相应的像素电极提供像素电压。
在一些示例中，当背光模组10提供的背光为白光时，彩膜基板30可以包括红色滤光膜、绿色滤光膜和蓝色滤光膜。通过控制照射至红色滤光膜、绿色滤光膜和蓝色滤光膜的光线强度，即可得到不同强度的红光、绿光和蓝光，使得显示装置1能够显示彩色图像。例如红色滤光膜仅可以使得入射光线中的红光透过，绿色滤光膜仅可以使得入射光线中的绿光透过，蓝色滤光膜仅可以使得入射光线中的蓝光透过。
在另一些示例中，在背光模组10提供的背光为蓝光时，彩膜基板30可以包括色转换膜。示例的，色转换膜可以为量子点膜。蓝光照射至红色量子点膜之后，能够被转换为红光。蓝光照射至绿色量子点膜之后，能够被转换为绿光。量子点膜转换后的得到的红光和绿光，与背光模组10提供的蓝光相混合，即可使得显示装置1实现全彩化图形显示。
示例性的，显示装置1包括：还包括：公共电极。公共电极可以设置在彩膜基板30中，该公共电极可以接收公共电压。当然，该公共电极也可以设置在阵列基板20中，本公开对此不作限定。
在一些示例中，如图1B所示，显示装置1还包括：位于彩膜基板30与阵列基板20之间的液晶层40。
示例性的，液晶层40包括多个液晶分子。例如，在像素电极和公共电极 之间可以形成电场，通过控制各个像素电极的电压值，就能够对公共电极和各个像素电极之间形成的电场的强度起到控制作用，从而对液晶层40中的液晶分子的偏转角度起到控制作用。
可以理解的是，背光模组10所提供的背光，可以透过阵列基板20，入射至液晶层40的液晶分子。液晶分子在像素电极和公共电极之间形成的电场的作用下，发生翻转，从而改变透过液晶分子的光线的量，使得经液晶分子出射的光线达到预设亮度。上述光线穿过彩膜基板30中不同颜色的滤光膜后出射。该出射的光线，包括各种颜色的光，例如红色光、绿色光、蓝色光等，各种颜色的光线相互配合，使得显示装置1实现图像显示功能。
示例性的，显示装置1中的背光模组10的类型有多种，可以根据实际情况进行设置，本公开对此不作限制。
例如，背光模组10可以为侧入式背光模组，背光模组10也可以为直下式背光模组。
为方便描述，本公开以下的实施例以背光模组10为直下式背光模组为例进行介绍。
在一些实施例中，如图2所示，背光模组10包括：发光基板100及位于发光基板100的出光侧的光学膜片200。
示例性的，光学膜片200包括：依次层叠设置在发光基板100出光侧的扩散板210、量子点膜220、扩散片230和复合膜240等。
例如，扩散板210和扩散片230用于消除灯影，并将发光基板100发出的光线进行均匀化处理，提高光线的均一性。
例如，量子点膜220用于对发光基板100发出的光进行转换。可选地，在发光基板100发出的光为蓝光的情况下，量子点膜220可以将该蓝光转换为白光，并且提高该白光的纯度。
例如，复合膜240用于提高发光基板100发出的光线的亮度。
可以理解的是，发光基板100发出的光线，入射至上述光学膜片200后射出的光线的亮度得到增强，且射出的光线纯度更高，均匀性更好。
在一些示例中，如图2所示，背光模组10还包括：设置在发光基板100与光学膜片200的扩散板210之间的支撑柱201。
示例性的，支撑柱201可以通过胶水固定在发光基板100上。支撑柱201可以用于支撑光学膜片200，并使得发光基板100发出的光获得一定的混光距离，从而可以进一步地消除灯影，提高光线的均匀性。
示例性的，显示装置1还包括：框架、显示芯片以及其他电子配件等。
而在另一些示例中，显示装置1包括发光基板100，发光基板100直接用于显示画面。该显示装置常用在商业显示，例如交通管理指挥中心显示屏或商业广场显示屏等。
在一些实施例中，如图3A～图3G和图4A所示，发光基板100具有功能区F和绑定区B。
其中，绑定区B与功能区F沿第一方向X依次排列。需要说明的是，本公开的说明书附图中，以图3A～图3G和图4A为例，虚线框示出的功能区F的边缘与绑定区B的边缘相互间隔设置，仅仅是为了清晰区分出功能区F和绑定区B，不对功能区F和绑定区B的边缘位置做进一步限定。
示例性的，绑定区B为实现发光基板100与显示芯片的绑定的区域。
示例性的，功能区F的形状有多种，可以根据实际情况进行选择，本公开对此不作限制。
例如，功能区F的形状可以为矩形，也可以为圆形等。
为方便示意，下面以功能区F的形状为矩形为例进行介绍。
在一些示例中，发光基板100包括：衬底110，以及多个功能元件组120。
上述衬底110的类型包括多种，可以根据实际需要选择设置。
示例性的，上述衬底110可以为柔性衬底，也可以为刚性衬底。
例如，在衬底110为柔性衬底的情况下，该柔性衬底例如可以为PET(Polyethylene Terephthalate，聚对苯二甲酸乙二醇酯)衬底、PEN(Polyethylene Naphthalate Two Formic Acid Glycol Ester，聚萘二甲酸乙二醇酯)衬底或PI(Polyimide，聚酰亚胺)衬底等。
又如，在衬底110为刚性衬底的情况下，该刚性衬底可以为玻璃衬底或PMMA(Polymethyl methacrylate，聚甲基丙烯酸甲酯)衬底等。
示例性的，多个功能元件组120位于衬底110的一侧；且多个功能元件组120位于功能区F。多个功能元件组120分别沿第一方向X排列成多行，且沿第二方向Y排列成多列。可以理解地，多行功能元件组120沿第一方向X间隔设置，多列功能元件组120沿第二方向Y间隔设置。
需要说明的是，本公开的说明书附图中，为了清楚地示出发光基板100的结构，仅仅示出了一行、两列功能元件组120(如图3A～图3F所示)，或者示出了两行、四列功能元件组120(如图4A所示)，不对本公开的实施例中功能元件组120的数量以及排布方式做进一步限定。
示例性的，第二方向Y与第一方向X相交。
此处，第一方向X和第二方向Y之间的夹角，可以根据实际需要选择设 置。例如，第一方向X和第二方向Y之间的夹角为85°、88°或90°等。
在一些示例中，功能元件组120可以包括多个微型电阻器或微型电容器等。
在另一些示例中，功能元件组120可以包括一个驱动芯片121和至少一个发光器件组122。发光器件组122可以包括一个发光器件123，也可以包括多个发光器件123。
示例性的，功能元件组120可以包括驱动芯片121和一个发光器件组122。
示例性的，功能元件组120可以包括驱动芯片121和多个发光器件组122。例如，功能元件组120可以包括驱动芯片121和四个发光器件组122，如图3A～图3F所示，四个发光器件组122分别分布在驱动芯片121的四角的延长线上，驱动芯片121位于四个发光器件组122的中间。
例如，发光器件组122可以包括两个发光器件123、四个发光器件123或六个发光器件123。
当一个发光器件组122中包括多个发光器件123时，一个发光器件组122中的多个发光器件123也可以排布在六边形、八边形或者其他不规则形状的顶点。或者，一个发光器件组122中的多个发光器件123还可以排布成圆形或者椭圆形等，满足不同的使用需求。本公开的实施例对此不做限制。
例如，当一个发光器件组122中包括多个发光器件123时，同一个发光器件组122中的多个发光器件123可以用于发出同一种颜色的光线，同一个发光器件组122中的多个发光器件123也可以用于发出多种不同颜色的光线。
可以理解地，不同的发光器件组122中包括的发光器件123的数量可以相同，也可以不同。本公开的实施例对一个发光器件组122中，发光器件123的数量不做进一步限定。
例如，同一个发光器件组122中的多个发光器件123通过串联方式相互连接。这样一来，向一个发光器件组122中的任一个发光器件123提供电信号，即可实现向一个发光器件组122中的各个发光器件123提供电信号，提高了发光基板100的布线便捷性。
示例性的，在驱动芯片121传输的驱动信号的控制下，发光器件组122实现发光。
示例性的，上述发光器件123包括但不限于Mini LED(Mini Light-Emitting Diode，迷你发光二极管)、Micro LED(Micro Light-Emitting Diode，微型发光二极管)等。
采用迷你发光二极管或微型发光二极管作为发光器件123时，发光器件 123的晶粒尺寸更小，可极大的缩短相邻发光器件123间的混光距离，使得发光基板具有区域亮度可调、高显色性、高对比度等优点。还可以使得发光基板100更加轻薄化、更省电，进而使得包括迷你发光二极管或微型发光二极管的发光基板的应用更加灵活。此外，相比于OLED(Organic Light Emitting Diode，有机发光二极管，简称OLED)来说，包括迷你发光二极管或微型发光二极管的发光基板的成本更低、寿命更长，烧屏的风险较小。
示例性的，如图3A～图3F和图4A所示，发光基板100还包括多个信号线组130。多个信号线组130位于功能区F，且多个信号线组130与多个功能元件组120位于衬底110的同一侧。一个信号线组130与一列功能元件组120电连接。信号线组130包括至少一条第一类信号线1301，各第一类信号线1301沿第一方向X延伸，且沿第二方向Y间隔排布。
可以理解的是，多个信号线组130包括多条第一类信号线1301，多条第一类信号线1301的长度和/或宽度并不完全相同，一部分第一类信号线1301的沿第一方向X的长度基本等于一列功能元件组120沿第一方向X的长度，而另一部分第一类信号线1301沿第一方向X的长度大于一列功能元件组120沿第一方向X的长度。
在一些示例中，如图3H所示，多个信号线组130同层设置，也即是多个信号线组130设置在同一导电层。可以理解地，导电层上除了设置有多个信号线组130之外，还可以设置有其他走线。
在另一些示例中，多个信号线组130中的多条第一类信号线1301可以设置在不同导电层，示例的，多个信号线组130中的多条第一类信号线1301中部分第一类信号线1301位于同一层，且至少两条第一类信号线1301分别设置在两层导电层上。
可以理解地，多个信号线组130同层设置，能够减少图案化导电层的步骤，从而简化发光基板100的制备工艺，减少掩模版、的数量，降低发光基板100的成本，并且还能够减少发光基板100发生短路等不良故障的情况，提高发光基板100的良品率。多个信号线组130设置在不同导电层上时，信号线组130的布线灵活性更高。
本公开的实施例以多个信号线组130同层设置为例，进行举例说明。
在一些示例中，发光基板100包括绝缘层，绝缘层位于导电层远离衬底110的一侧，且覆盖导电层。也即是，绝缘层能够覆盖导电层中的多个信号线组130，和导电层中的其他导电结构。
可以理解地，第一类信号线1301可以用于传输具有与恒定幅值的电压信 号。在信号线组130在包括多条第一类信号线1301时，多条第一类信号线1301可以分别用于传输不同的信号；或者，多条第一类信号线1301中的部分第一类信号线1301可以用于传输相同的信号。
示例性的，第一类信号线1301的材料为金属或金属合金。示例的，第一类信号线1301的材料可以包括铜或者铝等，从而提高第一类信号线1301的导电性能。
在一些示例中，各个信号线组130中包括的第一类信号线1301的数量可以相同，也可以不同。一个信号线组130中任意相邻的两个第一类信号线1301沿第二方向Y排布的间隔可以相同，也可以不同。
示例性的，如图3A～图3G所示，其中图3G为发光基板100的地侧的局部结构图(发光基板100的地侧是指：功能区F靠近绑定区B的一侧)，发光基板100还包括位于绑定区B的多个绑定引脚(Bonding Pin)140。
绑定引脚140的数量可以为多个，多个绑定引脚140可以沿第二方向Y间隔设置。
示例性的，一个绑定区B内设置有多个绑定引脚140。
示例性的，如图3A所示，第一类信号线1301的一端与绑定区B内的绑定引脚140电连接，另一端沿第一方向X延伸，以从绑定区B延伸至功能区F，并与沿第一方向X排列的一列功能元件组120电连接。可以理解地，第一类信号线1301可以直接与功能元件组120电连接，也可以通过其他元器件或导电图案与功能元件组120电连接。
可以理解的是，发光基板100还包括柔性电路板(Flexible Printed Circuit，简称FPC)和印刷电路板(Printed Circuit Board，简称PCB)。柔性电路板的一端与绑定区B内的绑定引脚140绑定连接，另一端与印刷电路板绑定连接，使得信号能够在多个信号线组130和印刷电路板之间传输，从而实现对于多个功能元件组120的驱动。
可以理解的是，一个信号线组130中可以包括传输不同信号的第一类信号线1301，以向功能元件组120传输不同的信号，实现对于多个功能元件组120的驱动。
示例性的，如图5和图6所示，信号线组130中包括器件电源信号线VLED、芯片电源信号线VCC、输入信号线Dis、数据信号线Data、接地信号线GND、输出信号线FB，且各信号线分别用于传输不同的信号。
在一些实现方式中，如图6所示，每个信号线组130中的电源信号线VLED、芯片电源信号线VCC、输入信号线Dis、数据信号线Data、接地信号线GND、 输出信号线FB分别与不同的绑定引脚140电连接，以向不同的功能元件组120分别传输信号。在包括多个信号线组130的情况下，一般需要多个绑定区B来设置绑定引脚140；例如，在包括64个信号线组时，会设置7～12个绑定区B。绑定区B的数量越多，占用的空间越大，当发光基板100应用于显示装置1时，在一些显示装置1(例如，笔记本电脑(Notebook))中时，由于空间的限制，无法设置该较多的绑定区B，导致发光基板100无法满足要求。在此基础上，绑定区B的数量越多，需要的柔性电路板的数量也较多，相应的导致发光基板100的成本增大；而且绑定区B的数量越多，在发光基板100的制作过程中，工艺难度越大，导致发光基板100的不良率也越高。
基于此，在本公开提供的发光基板100中，如图3A～图3B和图4A所示，发光基板100还包括多条第一类连接线150。第一类连接线150用于连接至少两个信号线组130中传输相同信号的第一类信号线1301。
示例性的，第一类连接线150沿第二方向Y延伸，此时，第一类信号线150在第二方向Y上的尺寸至少超过一个发光器件组122在第二方向Y上的尺寸。
示例性的，多条第一类连接线150与信号线组130可以设置在同一导电层；也可以设置在不同的导电层，例如多条第一类连接线150与信号线组130可以分别设置在两层导电层上。本公开的实施例对此不做限制。
示例性的，第一类连接线150可以用于连接两个信号线组130中传输相同信号的第一类信号线1301，也可以用于连接三个信号线组130中传输相同信号的第一类信号线1301或者四个信号线组130中传输相同信号的第一类信号线1301。本公开的实施例对此不做限制。
示例性的，至少两个信号线组130中传输相同信号的第一类信号线1301通过第一类连接线150并联设置；又或者至少两个信号线组130中传输相同信号的第一类信号线1301通过第一类连接线150串联设置。
示例性的，如图3A～图3B和图4A，与第一类连接线150电连接的多条第一类信号线1301中，至少一条第一类信号线1301与绑定引脚140间隔设置。
例如，与第一类连接线150电连接的多条第一类信号线1301中，至少一条第一类信号线1301与绑定引脚140间隔设置，二者在绑定区不接触，该至少一条第一类信号线1301通过与其电连接的第一类连接线150以及与其串联或者并联的其它第一类信号线1301与绑定引脚140间接连接。由此，印刷电路板所提供的信号，能够通过绑定引脚140、与该至少一条第一类信号线1301 串联或者并联的其它第一类信号线1301以及该至少一条第一类信号线1301电连接的第一类连接线150传输至该至少一条第一类信号线1301所连接的一列功能元件组120，从而实现对该列功能元件组120的驱动。
示例性的，与第一类连接线150电连接的第一类信号线1301的数量为四条时，可以是仅一条第一类信号线1301与绑定引脚140间隔设置；也可以是两条或者三条第一类信号线1301与绑定引脚140间隔设置。例如，如图3A所示，与第一类连接线150电连接的四条第一类信号线1301中，三条第一类信号线1301与绑定引脚140间隔设置。
示例性的，同一条第一类连接线150连接的两个信号线组130中的第一类信号线1301用于传输相同的电信号等。
示例性的，与第一类连接线150电连接的多条第一类信号线1301中，其中一条第一类信号线1301与绑定引脚140在绑定区B实现电连接(例如直接接触或间接接触)，柔性电路板与该条第一类信号线1301通过绑定引脚140实现电连接，使得印刷电路板所提供的信号，能够通过柔性电路板传输至至少两个信号线组130，从而实现对至少两个功能元件组120的驱动。
示例性的，与绑定引脚140在绑定区B通过直接接触实现电连接的第一类信号线1301或第二类信号线1302的主体具有类似字母“L“的形状，包括延伸方向与第一方向X的夹角不超过5°的第一部和延伸方向与第二方向Y的夹角不超过5°的第二部。其中，第一部的长度与一列功能元件组120沿第一方向X的长度相当；沿第二方向Y上，所述第一部到绑定区B的距离，与所述第二部的长度正相关；且沿第二方向Y，具有第二部越长的信号线，其第二部在第一方向X上越靠近绑定区B，其第一部在第二方向Y上越靠近远离绑定区B。可以理解的是，具有类似字母“L“的形状的第一类信号线1301或一部分第二类信号线1302，其还包括第三部，第三部的一端与其第二部连接，另一端与至少一个绑定引脚140连接；第三部的延伸方向与第一方向X的夹角不超过5°。
示例性的，与绑定引脚140间隔设置的至少一个第一类信号线1301或至少一个第二类信号线1302，其具有类似多边形的形状，例如为矩形状。
示例性的，与绑定引脚140在绑定区通过直接接触实现电连接的第一类信号线1301在衬底110上的投影与发光器件组122在衬底110上的正投影不重叠，如图3G所示。
在另一些实施例中，与绑定引脚140通过直接接触实现电连接的第一类信号线1301在衬底110上的投影，与多个发光器件组122中靠近绑定区B的 部分发光器件组122在衬底110上的正投影存在部分交叠，由此，可以进一步减小发光基板100在第一方向X上的尺寸，当发光基板100应用于显示装置1，能够满足显示装置1实现窄边框设计的需求。
由此，本公开的一些实施例所提供的发光基板100，通过第一类连接线150连接至少两个信号线组130中传输相同信号的第一类信号线1301，同时，与第一类连接线150电连接的多条第一类信号线1301中，至少一条第一类信号线1301与绑定引脚140间隔设置，减少了需要与绑定引脚140电连接的第一类信号线1301的数量，由此需要设置的绑定引脚140的数量得以减少，从而需要较少的绑定区B，来设置绑定引脚140，有效减少了绑定区B的数量，减小了绑定区B所占用的空间，当发光基板100应用于显示装置1时，能够克服一些显示装置1(例如，笔记本电脑(Notebook))空间不足的问题，提高了发光基板100的适应性，拓宽了发光基板100的应用场景。
另外，绑定区B数量的减少，能够在一定程度上降低发光基板100的制作工艺难度，提高发光基板100的良率，还可以缩短发光基板100的绑定区B的制程所需的时间，减小产线负荷，提高生产效率；而且绑定区B数量减小，需要的柔性电路板的数量也随之减小，从而降低了发光基板100的生产成本。在此基础上，相比于选用PCB基板作为发光基板100的基板相比，本公开实施例提供的发光基板100在实现少绑定区B的基础上，提高了发光基板100的可依赖性。
在一些实施例中，如图3A、图3H和图4A所示，其中图3H为发光基板100的天侧的局部结构图(发光基板100的天侧是指：功能区F远离绑定区B的一侧)，第一类信号线1301包括至少一条第一电压信号线VL1。第一电压信号线VL1与发光器件组122电连接。多条第一类连接线150包括至少一条第一连接线1511。第一连接线1511与至少两个信号线组130中的第一电压信号线VL1的同一端电连接。
示例性的，多条第一类连接线150可以包括一条第一连接线1511，也可以包括多条第一连接线1511。
示例性的，在多条第一类连接线150包括一条第一连接线1511时，第一连接线1511可以用于连接任意数量的第一电压信号线VL1，或者，第一连接线1511可以用于多个信号线组130中的所有的第一电压信号线VL1。
示例性的，在多条第一类连接线150包括多条第一连接线1511时，同一条第一连接线1511连接的第一电压信号线VL1的数量可以相同，也可以不同，本公开的实施例对此不做限制。
示例性的，在多条第一类连接线150包括多条第一连接线1511时，多条第一类连接线150沿第二方向Y延伸，且多条第一类连接线150在第二方向Y上依次间隔设置。
示例性的，同一条第一连接线1511可以用于连接两条第一电压信号线VL1。或者，同一条第一连接线1511可以用于连接多条第一电压信号线VL1。图3A和图4A示意出了同一条第一连接线1511可以用于连接四条第一电压信号线VL1。
示例性的，如图3A和图3H所示，第一类信号线1301可以包括两条第一电压信号线VL1。或者，如图4A所示，第一类信号线1301可以包括一条第一电压信号线VL1。
在一些示例中，沿第一方向X排列的多个发光器件组122与一条第一电压信号线VL1连接。
在一些示例中，同一条第一连接线1511连接的多条第一电压信号线VL1分别属于不同的信号线组130。
在又一些示例中，同一条第一连接线1511连接的多条第一电压信号线VL1中，其中部分第一电压信号线VL1属于同一个信号线组130。例如，同一条第一连接线1511连接的多条第一电压信号线VL1中，其中两条第一电压信号线VL1属于同一个信号线组130，如图3A和图3H所示。
示例性的，第一电压信号线VL1位于功能区F，一条第一电压信号线VL1与一列发光器件组122电连接，且与第一连接线1511电连接的多条第一电压信号线VL1中，至少一条第一电压信号线VL1与绑定引脚140间隔设置，部分第一电压信号线VL1从功能区F延伸至绑定区B，且与位于绑定区B内的绑定引脚140通过直接接触实现电连接，从而可以将来自印刷电路板的信号传输至发光器件组122。
示例性的，第一电压信号线VL1用于为发光器件组122中的发光器件123提供一个较大的恒流电压。在发光器件组122包括多个发光器件123，且多个发光器件123通过串联方式相互连接时，多个串联的发光器件123中，第一个发光器件123与第一电压信号线VL1电连接，多个串联的发光器件123中，最后一个发光器件123与驱动芯片121电连接。
示例性的，与同一条第一连接线1511电连接的多条第一电压信号线VL1中，一条第一电压信号线VL1从功能区F延伸至绑定区B，且与位于绑定区B内的绑定引脚140电连接。
示例性的，发光基板100外部的供电电源通过印刷电路板和绑定引脚140与第一电压信号线VL1电连接，使得供电电源能够通过第一电压信号线VL1对一列发光器件组122中的发光器件123供电，从而使得发光器件123能够发光。
在一些示例中，第一连接线1511的材料与第一电压信号线VL1的材料相同且同层设置，即设置在同一导电层，如图3A～图3F和图4A所示。
示例性的，第一连接线1511的材料与第一电压信号线VL1的材料可以均为金属，例如该金属可以为铜。
上述“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
在又一些示例中，第一连接线1511与第一电压信号线VL1可以设置在不同的导电层，例如第一连接线1511与第一电压信号线VL1可以分别设置在两层导电层上。此时，第一连接线1511的材料与第一电压信号线VL1的材料可以相同，也可以不同。本公开的实施例对此不做限制。
可以理解的是，上述“至少两个信号线组130中的第一电压信号线VL1的同一端”可以是至少两个信号线组130中的第一电压信号线VL1的靠近绑定区B的一端，也可以是至少两个信号线组130中的第一电压信号线VL1的远离绑定区B的一端，本公开的实施例对此不做限制。
本实施例中，多列发光器件组122电连接的多条第一电压信号线VL1通过第一连接线1511实现电连接，第一连接线1511连接的多条第一电压信号线VL1中，至少一条第一电压信号线VL1与绑定引脚140间隔设置，部分第一电压信号线VL1与位于绑定区B内的绑定引脚140通过直接接触实现电连接，将来自印刷电路板所提供的信号，通过该部分第一电压信号线VL1和绑定引脚140，传输至该多列发光器件组122，减小了需要与绑定区B内的绑定引脚140直接电连接的第一电压信号线VL1的数量，由此需要设置的绑定引脚140的数量得以减少，从而需要较少的绑定区B，来设置绑定引脚140，有效减少了绑定区B的数量，减小了绑定区B所占用的空间，当发光基板100应用于显示装置1时，能够克服一些显示装置1(例如，笔记本电脑(Notebook))空间不足的问题，从而拓宽了发光基板100的应用场景。
在一些实施例中，如图3A和图4A所示，第一连接线1511沿第二方向 Y延伸，且位于功能区F远离绑定区B的一侧(也即发光基板的天侧)。
示例性的，同一条第一连接线1511连接的多条第一电压信号线VL1并联设置。由此，可以减少与该多条第一电压信号线VL1连接的发光器件组122之间的压降，提高发光器件组122的发光效率。
本实施例中，第一连接线1511沿第二方向Y延伸，与至少两个信号线组130中的第一电压信号线VL1的同一端电连接，能够减小需要与绑定区B内的绑定引脚140电连接的第一电压信号线VL1的数量，从而减少绑定区B的数量；在此基础上，第一连接线1511位于功能区F远离绑定区B的一侧，第一连接线1511与第一电压信号线VL1的远离绑定区B的一端之间不存在其他结构，可以使得第一连接线1511与第一电压信号线VL1的电连接无需跨过其他膜层，直接在同层即可实现，进而可以简化发光基板100的制备工艺，减少掩模版(Mask)的数量，降低发光基板100的成本，并且还能够减少发光基板100发生短路等不良故障的情况，提高发光基板100的良品率。
示例性的，第一连接线1511，与其电连接的第一电压信号线VL1呈一体结构。
上述“一体结构”指的是，相连接的两个图案同层设置，且该两个图案是连续的，未分隔开。上述设置方式，可以使得该第一连接线1511及与其电连接的第一电压信号线VL1可以在一次构图工艺中形成，进而可以简化发光基板100的制备工艺。此外，该“一体结构”的设置，能够提高第一连接线1511与第一电压信号线VL1之间电连接的可靠，并且无需设置其他导电结构，降低了发光基板100的制备成本。
在一些实施例中，如图3A～图3F和图4A所示，同一列功能元件组120中的多个发光器件组122排列为至少一列；一列发光器件组122与一条第一电压信号线VL1电连接。
在一些示例中，同一列功能元件组120中的多个发光器件组122排列为多列。例如，同一列功能元件组120中的多个发光器件组122排列为两列，如图3A～图3F所示。
示例性的，在同一列功能元件组120中的多个发光器件组122排列为两列时，与该两列多个发光器件组122连接的第一电压信号线VL1位于该两列多个发光器件组122之间。
在另一些示例中，同一列功能元件组120中的多个发光器件组122排列为一列，如图4A所示。
本实施例中，一条第一电压信号线VL1用于为一列发光器件组122提供 工作电源的电压信号，使得一列发光器件组122中的发光器件123能够发光，能够简化发光基板100的线路排布，从而简化发光基板100的结构，降低制备形成发光基板100的难度。
在一些实施例中，如图3A～图3F所示，与该第一电压信号线VL1连接的一列发光器件组122在衬底110上的正投影，与该第一电压信号线VL1在衬底110上的正投影至少部分交叠。
在一些示例中，如图3A～图3F所示，与该第一电压信号线连接VL1的一列发光器件组122在衬底110上的正投影，与该第一电压信号线VL1在衬底110上的正投影部分交叠。
例如，一个发光器件组122中的多个发光器件123之间通过导线连接，连接各个发光器件123之间的导线在衬底110上的正投影，与该第一电压信号线VL1在衬底110上的正投影部分交叠。
本领域技术人员可以理解的是，在发光基板100包括两层导电层时，信号线组130通常位于靠近衬底110的一层导电层上，连接各个发光器件123之间的导线通常位于远离衬底110的一层导电层上；且两层导电层的材料通常包括铜，在连接各个发光器件123之间的连接线，与位于各个发光器件123下方的信号线之间产生负压差时，铜离子更容易发生迁移、生长，从而造成两层导电层之间的短路(即，DGS(Data Gate Short，电源线和数据线短接)不良)，由此会降低了发光基板100的产品稳定性。
上述“负压差”是指，连接各个发光器件123之间的导线的电压，大于位于各个发光器件123下方的信号线的电压，从而形成负压差。例如，一列发光器件组122在衬底110上的正投影，与接地信号线在衬底110上的正投影部分交叠，接地信号线通常是零电势，此时，连接各个发光器件123之间的导线的电压，大于接地信号线的电压，从而形成负压差。
相反的，“正压差”是指，与连接各个发光器件123之间的导线的电压，小于位于各个发光器件123下方的信号线的电压，从而形成正压差。具体到本公开实施例中，与连接各个发光器件123之间的导线的电压，小于位于各个发光器件123下方的第一电压信号线VL1的电压，从而形成正压差。
本实施例中，与该第一电压信号线VL1连接的一列发光器件组122在衬底110上的正投影，与该第一电压信号线VL1在衬底110上的正投影部分交叠，第一电压信号线VL1的电压大于连接各个发光器件123之间的导线的电压，从而形成正压差，从而抑制两层导电层中的铜离子更发生迁移和生长，从而进一步有效降低两层导电层之间发生短路的概率，提高了发光基板100的 良率、安全性和稳定性，延长了发光基板100的使用寿命。
在一些实施例中，结合图4B和图4C所示，其中，图4B为本公开的一些实施例提供的发光基板100的天侧的局部结构图，图4C为本公开的一些实施例提供的发光基板100的地侧的局部结构图，多个发光器件组122所包括的发光器件123沿第一方向X排列成多行，且沿第二方向Y排列成多列；任意相邻的两行发光器件123错开设置。
示例性的，任意相邻的两行发光器件123之间的距离可以相等，也可以不等，本公开的实施例对此不做限制。
本实施例中，通过使任意相邻的两行发光器件123错开设置，可以使得任意相邻两列发光器件123之间混光空缺区域减小，进而使得发光基板100的混光效果更好。
在一些实施例中，如图3A～图3F所示，同一列功能元件组120中的多个驱动芯片121沿第一方向X排列为一列。同一列功能元件组120中的多个发光器件组122，位于同一列功能元件组120中的多个驱动芯片121沿第一方向X的相对两侧。
示例性的，如图3A～图3F所示，同一列功能元件组120中的多个发光器件组122沿第二方向Y排列为两列，该两列发光器件组122位于同一列功能元件组120中的多个驱动芯片121沿第二方向Y的相对两侧。
采用上述设置，可以使得该两列发光器件组122在同一列驱动芯片121传输的驱动信号的控制下，实现发光；在发光器件组122的列数相同时，所需要的信号线组130的数量较少，需要从功能区F延伸至绑定区B，且与位于绑定区B内的绑定引脚140电连接的第一电压信号线VL1的数量减少，同时需要的绑定引脚140的数量得以减少，从而需要较少的绑定区B，来设置绑定引脚140，有效减少了绑定区B的数量，减小了绑定区B所占用的空间，当发光基板100应用于显示装置1时，能够克服一些显示装置1(例如，笔记本电脑(Notebook))空间不足的问题，提高了发光基板100的适应性，拓宽了发光基板100的应用场景。
在一些实施例中，如图3A～图3F和图4A所示，第一类信号线1301包括接地信号线VL2，接地信号线VL2与驱动芯片121电连接。
示例性的，如图3B所示，多条第一类连接线150包括至少一条第二连接线1512。第二连接线1512，与至少两个信号线组130中的接地信号线VL2的同一端电连接。
示例性的，接地信号线VL2传输的电压信号可以为恒压信号。
示例性的，接地信号线VL2用于将驱动芯片121接地。
示例性的，在同一列功能元件组120中的多个发光器件组122沿第二方向Y排列为两列，也即，每列驱动芯片121控制两列发光器件组122时，接地信号线VL2位于受不同列的驱动芯片121控制的两列发光器件组122之间。
示例性的，多条第一类连接线150可以包括一条第二连接线1512，也可以包括多条第二连接线1512。
示例性的，在多条第一类连接线150包括一条第二连接线1512时，第二连接线1512可以用于连接任意数量的接地信号线VL2，或者，第二连接线1512可以用于多个信号线组130中的所有的接地信号线VL2。
示例性的，在多条第一类连接线150包括多条第二连接线1512时，同一条第二连接线1512连接的接地信号线VL2的数量可以相同，也可以不同，本公开的实施例对此不做限制。
示例性的，同一条第二连接线1512可以用于连接两条接地信号线VL2，如图3B所示。或者，同一条第二连接线1512可以用于连接多条接地信号线VL2；图4A示意出了同一条第二连接线1512可以用于连接四条接地信号线VL2。
示例性的，接地信号线VL2位于功能区F，一条接地信号线VL2与一列驱动芯片121电连接，且与同一条第二连接线1512电连接的多条接地信号线VL2中，至少一条接地信号线VL2与绑定引脚140间隔设置，部分接地信号线VL2从功能区F延伸至绑定区B，且与位于绑定区B内的绑定引脚140电连接。
例如，同一条第二连接线1512连接的多条接地信号线VL2中，一条接地信号线VL2的一端与绑定区B内的绑定引脚140电连接，另一端延伸至功能区F，且与一列驱动芯片121电连接。由上述可知，驱动芯片121与发光器件组122电连接，从而使得接地信号线VL2能够通过驱动芯片121与发光器件组122电连接。
在一些示例中，如图3B和图4A所示，驱动芯片121具有至少一个接地引脚GND。接地信号线VL2的一端通过绑定引脚140与印刷电路板电连接，接地信号线VL2的另一端与驱动芯片121的接地引脚GND电连接，以将驱动芯片121接地。
在一些示例中，第二连接线1512与接地信号线VL2可以设置在同一导电层。
在又一些示例中，第二连接线1512与接地信号线VL2可以设置在不同的导电层。例如，第二连接线1512与接地信号线VL2可以分别设置在两层导电层上。此时，第二连接线1512与接地信号线VL2的材料可以相同，也可以不同。本公开的实施例对此不做限制。
本实施例中，多列驱动芯片121电连接的多条接地信号线VL2通过第二连接线1512实现电连接，第二连接线1512连接的多条接地信号线VL2中，至少一条接地信号线VL2与绑定引脚140间隔设置，部分接地信号线VL2与位于绑定区B内的绑定引脚140通过直接接触实现电连接，从而能够使得该多列驱动芯片121接地，减小了需要与绑定区B内的绑定引脚140直接电连接的接地信号线VL2的数量，由此需要设置的绑定引脚140的数量得以减少，从而需要较少的绑定区B，来设置绑定引脚140，有效减少了绑定区B的数量，减小了绑定区B所占用的空间，当发光基板100应用于显示装置1时，能够克服一些显示装置1(例如，笔记本电脑(Notebook))空间不足的问题，提高了发光基板100的适应性，拓宽了发光基板100的应用场景。
在一些实施例中，如图3B和图4A所示，第二连接线1512沿第二方向Y延伸，且位于功能区F靠近绑定区B的一侧。
示例性的，同一条第二连接线1512连接的多条接地信号线VL2并联设置。
本实施例中，第二连接线1512沿第二方向Y延伸，与至少两个信号线组130中的接地信号线VL2的同一端电连接，第二连接线1512连接的多条接地信号线VL2中，至少一条接地信号线VL2与绑定引脚140间隔设置，仅一部分接地信号线VL2与位于绑定区B内的绑定引脚140通过直接接触实现电连接，从而能够减小需要与绑定区B内的绑定引脚140直接电连接的接地信号线VL2的数量，从而减少绑定区B的数量。
在一些实施例中，如图3A～图3F和图4A所示，每列功能元件组120的数目为N，每列功能元件组120中的N个驱动芯片依次级联。
示例性的，如图3A～图3F和图4A，信号线组130还包括至少一条第二类信号线1302，各第二类信号线1302沿第一方向X延伸，且沿第二方向Y间隔排布。
示例性的，如图3C～图3F和图4A所示，发光基板100还包括多条第二类连接线160。第二类连接线160用于连接至少两个信号线组130中传输相同信号的第二类信号线1302。
多条第二类连接线160与信号线组130可以设置在同一导电层；也可以 设置在不同的导电层，例如多条第二类连接线160与信号线组130可以分别设置在两层导电层上。本公开的实施例对此不做限制。
示例性的，第二类连接线160可以用于连接两个信号线组130中传输相同信号的第二类信号线1302，也可以用于连接三个信号线组130中传输相同信号的第二类信号线1302或者四个信号线组130中传输相同信号的第二类信号线1302。本公开的实施例对此不做限制。
示例性的，至少两个信号线组130中传输相同信号的第二类信号线1302通过第二类连接线160并联设置；又或者至少两个信号线组130中传输相同信号的第二类信号线1302通过第二类连接线160串联设置。
示例性的，如图3C～图3F和图4A所示，与第二类连接线160电连接的多条第二类信号线1302中，至少一条第二类信号线1302与绑定引脚140间隔设置。
例如，与第二类连接线160电连接的多条第二类信号线1302中，至少一条第二类信号线1302与绑定引脚140间隔设置，二者在绑定区不接触，该至少一条第二类信号线1302通过与其电连接的第二类连接线160以及与其串联或者并联的其它第二类信号线1302与绑定引脚140间接连接。由此，印刷电路板所提供的信号，能够通过绑定引脚140、与该至少一条第二类信号线1302串联或者并联的其它第二类信号线1302以及该至少一条第二类信号线1302电连接的第二类连接线160传输至该至少一条第二类信号线1302所连接的一列功能元件组120，从而实现对该列功能元件组120的驱动。
示例性的，与第二类连接线160电连接的第二类信号线1302的数量为四条时，可以是仅一条第二类信号线1302与绑定引脚140间隔设置，也可以是两条或者三条第二类信号线1302与绑定引脚140间隔设置。
示例性的，与第二类连接线160电连接的多条第二类信号线1302中，其中一条第二类信号线1302与绑定引脚140电连接，柔性电路板与该条第二类信号线1302通过绑定引脚140实现电连接，使得印刷电路板所提供的信号，能够通过柔性电路板传输至至少两个信号线组130，从而实现对至少两个功能元件组120的驱动。
由此，本公开的一些实施例所提供的发光基板100，通过第二类连接线160连接至少两个信号线组130中传输相同信号的第二类信号线1302，同时，与第二类连接线160电连接的多条第二类信号线1302中，至少一条第二类信号线1302与绑定引脚140间隔设置，减少了需要与绑定引脚140电连接的第二类信号线1302的数量，由此需要设置的绑定引脚140的数量得以减少，从 而需要较少的绑定区B，来设置绑定引脚140，有效减少了绑定区B的数量，减小了绑定区B所占用的空间，当发光基板100应用于显示装置1时，能够克服一些显示装置1(例如，笔记本电脑(Notebook))空间不足的问题，提高了发光基板100的适应性，拓宽了发光基板100的应用场景。
在一些实施例中，如图4A所示，第二类信号线1302包括多条地址信号线DL，每列N个驱动芯片中任意相邻的两个驱动芯片121之间通过地址信号线DL电连接。多条第二类连接线160包括至少一条第三连接线1611。M列N个驱动芯片中任意相邻两列N个驱动芯片通过第三连接线1611电连接，其中，M≥2，且M为正整数。
示例性的，如图4A所示，驱动芯片121具有输入端口Dis和输出端口Dos。地址信号线DL的一端与相邻的两个驱动芯片121中一者的输入端口Dis电连接，地址信号线DL的另一端与该相邻的两个驱动芯片121中另一者的输出端口Dos电连接。
具体的，如图4A所示，上述N个驱动芯片的具体级联结构可以为，在沿功能区F远离绑定区B的方向上，第一级驱动芯片121的输入端口Dis与位于绑定区B内的绑定引脚140电连接，除第一级驱动芯片121以外，任一级驱动芯片121的输入端口Dis与该级驱动芯片121的上一级驱动芯片121的输出端口Dos通过地址信号线DL电连接；最后一级驱动芯片121的输出端口Dos与一条地址信号线DL电连接。这样一来，印刷电路板输出的信号能够通过地址信号线DL传输至多个驱动芯片121。
示例性的，多条第二类连接线160可以包括一条第三连接线1611，也可以包括多条第第三连接线1611。
示例性的，一条第三连接线1611用于连接两列N个驱动芯片。例如，如图3C所示，图3C中示意出了一行、两列驱动芯片。该两列驱动芯片通过一条第三连接线1611电连接。
示例性的，在多条第二类连接线160可以包括一条第三连接线1611时，两列N个驱动芯片通过一条第三连接线1611电连接。
示例性的，在多条第二类连接线160可以包括多条第三连接线1611时，与所述M列N个驱动芯片电连接的第三连接线1611的数量可以为M-1条，任意相邻的两列N个驱动芯片通过第三连接线1611相连接；M列N个驱动芯片通过M-1条第三连接线1611实现串联连接。例如，如图4A所示，图4A中示意出了两行、四列驱动芯片。该四列驱动芯片中任意相邻两列N个驱动芯片通过第三连接线1611电连接。且该四列驱动芯片通过三条第三连接线 1611实现串联连接。
示例性的，信号线组130还包括信号输出线FB，通过M-1条第三连接线1611实现串联连接的M列N个驱动芯片中，其中第一列N个驱动芯片的第一级驱动芯片121所连接的地址信号线DL从功能区F延伸至绑定区B，且与位于绑定区B内的绑定引脚140电连接；其中第M列N个驱动芯片的一端与第三连接线1611电连接，另一端与输出线FB电连接，该输出线FB从功能区F延伸至绑定区B，且通过绑定引脚140与印刷电路板电连接。由此，印刷电路板输出的信号能够通过地址信号线DL传输至多个驱动芯片121之后，再通过输出线FB反馈至印刷电路板，从而实现对于多个驱动芯片121的驱动。
本实施例中，M列N个驱动芯片中任意相邻两列N个驱动芯片通过第三连接线1611实现电连接，M列N个驱动芯片中，仅部分列的N个驱动芯片通过信号输出线FB与位于绑定区B内的绑定引脚140电连接，就能够为该多列驱动芯片121提供驱动信号，减小了需要与绑定区B内的绑定引脚140电连接的地址信号线DL的数量，由此需要设置的绑定引脚140的数量得以减少，从而需要较少的绑定区B，来设置绑定引脚140，有效减少了绑定区B的数量，减小了绑定区B所占用的空间，当发光基板100应用于显示装置1时，能够克服一些显示装置1(例如，笔记本电脑(Notebook))空间不足的问题，提高了发光基板100的适应性，拓宽了发光基板100的应用场景。
在一些实施例中，如图3C所示，第三连接线1611沿第二方向Y延伸，且位于功能区F远离绑定区B的一侧。
示例性的，通过第三连接线1611连接M列N个驱动芯片中任意相邻两列N个驱动芯片，从而实现了M列N个驱动芯片的串联设置。
在一些示例中，在沿远离绑定区B的方向上，M列N个驱动芯片中，任意相邻的两列N个驱动芯片中，其中一列N个驱动芯片的最后一级驱动芯片121连接的地址信号线DL，与另一列N个驱动芯片的最后一级驱动芯片121连接的地址信号线DL之间通过第三连接线1611电连接。
在又一些示例中，在沿远离绑定区B的方向上，M列N个驱动芯片中，任意相邻的两列N个驱动芯片中，其中一列N个驱动芯片的第一级驱动芯片121连接的地址信号线DL，与另一列N个驱动芯片的第一级驱动芯片121连接的地址信号线DL之间通过第三连接线1611电连接。
本实施例中，M列N个驱动芯片通过第三连接线1611连接，M列N个驱动芯片中，仅部分列的N个驱动芯片通过地址信号线DL与位于绑定区B 内的绑定引脚140电连接，从而能够减小需要与绑定区B内的绑定引脚140电连接的地址信号线DL的数量，从而减少绑定区B的数量。
在一些实施例中，如图4A所示，第三连接线1611与相邻两列所述N个驱动芯片中的一者的第1个驱动芯片121电连接，并穿过相邻两列功能元件组120之间的间隙，与该相邻两列N个驱动芯片中的另一者的第N个驱动芯片121电连接。
在一些示例中，第三连接线1611的材料与地址信号线DL的材料相同且同层设置，即设置在同一导电层。
示例性的，第三连接线1611的材料与地址信号线DL的材料可以均为金属，例如该金属可以为铜。
示例性的，第三连接线1611，与其电连接的地址信号线DL呈一体结构。由此，可以使得该第三连接线1611，与其电连接的地址信号线DL可以在一次构图工艺中形成，进而可以简化发光基板100的制备工艺。此外，该“一体结构”的设置，能够提高第三连接线1611与地址信号线DL之间电连接的可靠性，并且无需设置其他导电结构，降低了发光基板100的制备成本。
在又一些示例中，第三连接线1611与地址信号线DL可以设置在不同的导电层。例如，第三连接线1611与地址信号线DL可以分别设置在两层导电层上。此时，第三连接线1611与地址信号线DL的材料可以相同，也可以不同。本公开的实施例对此不做限制。
本实施例中，第三连接线1611采用绕线的方式，穿过相邻两列功能元件组120之间的间隙，实现两列N个驱动芯片之间的电连接，第三连接线1611连接的多列N个驱动芯片中，仅部分列的N个驱动芯片电连接的地址信号线DL与位于绑定区B内的绑定引脚140电连接，从而能够为该多列驱动芯片121提供驱动信号，减小了需要与绑定区B内的绑定引脚140电连接的地址信号线DL的数量，由此需要设置的绑定引脚140的数量得以减少，从而减少了绑定区B的数量，减小了绑定区B所占用的空间，当发光基板100应用于显示装置1时，能够克服一些显示装置1(例如，笔记本电脑(Notebook))空间不足的问题，提高了发光基板100的适应性，拓宽了发光基板100的应用场景。
在一些实施例中，如图3A～图3F和图4A所示，第二类信号线1302包括：第二电压信号线VL3，第二电压信号线VL3与驱动芯片121电连接。
示例性的，如图3D和图4A所示，多条第二类连接线160包括至少一条第四连接线1612。与上述M列N个驱动芯片连接的第二电压信号线VL3中，至少两条第二电压信号线VL3通过第四连接线1612电连接。
示例性的，第二电压信号线VL3传输的信号可以为恒压信号。第二电压信号线VL3与驱动芯片121电连接，用于为驱动芯片121供电。
示例性的，如图3D和图4A所示，多条第二类连接线160可以包括一条第四连接线1612，也可以包括多条第四连接线1612。
示例性的，在多条第二类连接线160包括多条第四连接线1612时，同一条第四连接线1612连接的第二电压信号线VL3的数量可以相同，也可以不同，本公开的实施例对此不做限制。
示例性的，与上述M列N个驱动芯片的连接的第二电压信号线VL3的数量为M条，同一条第四连接线1612可以用于连接所述M条第二电压信号线VL3中的两条第二电压信号线VL3。或者，同一条第四连接线1612可以用于连接所述M条第二电压信号线VL3中的多条第二电压信号线VL3。图3D和图4A示意出了同一条第四连接线1612可以用于连接两条第二电压信号线VL3。
示例性的，如图3D和图4A所示，第二电压信号线VL3位于功能区F，一条第二电压信号线VL3与一列驱动芯片121电连接，且与同一条第四连接线1612电连接的多条第二电压信号线VL3中，至少一条第二电压信号线VL3与绑定引脚140间隔设置，部分第二电压信号线VL3从功能区F延伸至绑定区B，且与位于绑定区B内的绑定引脚140通过直接接触实现电连接。
例如，同一条第四连接线1612连接的多条第二电压信号线VL3中，一条第二电压信号线VL3的一端与绑定区B内的绑定引脚140电连接，另一端延伸至功能区F，且与一列驱动芯片121电连接。由上述可知，驱动芯片121与发光器件组122电连接，从而使得第二电压信号线VL3能够通过驱动芯片121与发光器件组122电连接。
在一些示例中，如图3D所示，驱动芯片121具有电源引脚Vcc。第二电压信号线VL3的一端通过绑定引脚140和印刷电路板与发光基板100外部的供电电源电连接，另一端与驱动芯片121的电源引脚Vcc电连接，使得第二电压信号线VL3能够实现对于驱动芯片121的供电。
在一些示例中，第四连接线1612与第二电压信号线VL3可以设置在同一导电层。
在又一些示例中，第四连接线1612与第二电压信号线VL3可以设置在不同的导电层，例如第四连接线1612与第二电压信号线VL3可以分别设置在两层导电层上。此时，第四连接线1612与第二电压信号线VL3的材料可以相同，也可以不同。本公开的实施例对此不做限制。
本实施例中，M列N个驱动芯片的连接的第二电压信号线VL3中，至少两条第二电压信号线VL3通过第四连接线1612实现电连接，且第四连接线1612连接的多条第二电压信号线VL3中，至少一条第二电压信号线VL3与绑定引脚140间隔设置，部分第二电压信号线VL3与位于绑定区B内的绑定引脚140通过直接接触实现电连接，从而能够实现对于该多列驱动芯片121的供电，减小了需要与绑定区B内的绑定引脚140直接电连接的第二电压信号线VL3的数量，由此需要设置的绑定引脚140的数量得以减少，从而需要较少的绑定区B，来设置绑定引脚140，有效减少了绑定区B的数量，减小了绑定区B所占用的空间，当发光基板100应用于显示装置1时，能够克服一些显示装置1(例如，笔记本电脑(Notebook))空间不足的问题，提高了发光基板100的适应性，拓宽了发光基板100的应用场景。
在一些实施例中，如图3D所示，第四连接线1612沿第二方向Y延伸，且位于功能区F靠近绑定区B的一侧(也即发光基板的地侧)。
示例性的，第四连接线1612与上述M列N个驱动芯片的连接的第二电压信号线VL3中的至少两条第二电压信号线VL3的同一端电连接。
示例性的，同一条第四连接线1612连接的至少两条第二电压信号线VL3并联设置。
示例性的，第四连接线1612与第二电压信号线VL3可以设置在不同的导电层，例如第四连接线1612与第二电压信号线VL3可以分别设置在两层导电层上。此时，第四连接线1612的材料与第二电压信号线VL3的材料可以相同，也可以不同。本公开的实施例对此不做限制。
本实施例中，第四连接线1612沿第二方向Y延伸，与M列N个驱动芯片的连接的第二电压信号线VL3中的至少两条第二电压信号线VL3的同一端电连接，且第四连接线1612连接的多条第二电压信号线VL3中，至少一条第二电压信号线VL3与绑定引脚140间隔设置，部分第二电压信号线VL3与位于绑定区B内的绑定引脚140通过直接接触实现电连接，从而能够实现对于该多列驱动芯片121的供电，减小了需要与绑定区B内的绑定引脚140直接电连接的第二电压信号线VL3的数量，由此需要设置的绑定引脚140的数量得以减少，从而需要较少的绑定区B，来设置绑定引脚140，有效减少了绑定 区B的数量。
在一些实施例中，如图4A所示，第四连接线1612与M列N个驱动芯片的连接的第二电压信号线VL3中的相邻两条第二电压信号线VL3电连接。其中，第四连接线1612与相邻两条第二电压信号线VL3中的一条的第一端电连接，并穿过相邻两列功能元件组120之间的间隙，与相邻两条第二电压信号线VL3中的另一条的第二端电连接。
示例性的，同一条第四连接线1612连接的两条第二电压信号线VL3之间串联设置。
示例性的，与所述M列N个驱动芯片电连接的第二电压信号线VL3的数量为M条，该M条第二电压信号线VL3通过M-1条第四连接线1612实现串联连接。例如，如图4A所示，图4A中示意出了两行、四列驱动芯片。该四列驱动芯片连接的第二电压信号线VL3的数量为四条，该四条第二电压信号线VL3通过三条第四连接线1612实现串联连接。
在一些示例中，第四连接线1612与第二电压信号线VL3可以设置在不同的导电层，例如第四连接线1612与第二电压信号线VL3可以分别设置在两层导电层上。此时，第四连接线1612的材料与第二电压信号线VL3的材料可以相同，也可以不同。本公开的实施例对此不做限制。
在又一些示例中，第四连接线1612的材料与第二电压信号线VL3的材料相同且同层设置，即设置在同一导电层。
示例性的，第四连接线1612的材料与第二电压信号线VL3的材料可以均为金属，例如该金属可以为铜。
示例性的，第四连接线1612，与其电连接的第二电压信号线VL3呈一体结构。由此，可以使得该第四连接线1612，与其电连接的第二电压信号线VL3可以在一次构图工艺中形成，进而可以简化发光基板100的制备工艺。此外，该“一体结构”的设置，能够提高第四连接线1612与第二电压信号线VL3之间电连接的可靠，并且无需设置其他导电结构，降低了发光基板100的制备成本。
可以理解的是，上述第一端和第二端是相对而言。示例性的，第二电压信号线VL3的第一端是指第二电压信号线VL3远离绑定区B的一端，第二电压信号线VL3的第二端是指第二电压信号线VL3靠近绑定区B的一端。或者，第二电压信号线VL3的第一端是指第二电压信号线VL3靠近绑定区B的一端，第二电压信号线VL3的第二端是指第二电压信号线VL3远离绑定区B的一端。
本实施例中，第四连接线1612采用绕线的方式，穿过相邻两列功能元件组120之间的间隙，实现了M列N个驱动芯片的连接的第二电压信号线VL3中的相邻两条第二电压信号线VL3之间的电连接，M列N个驱动芯片的连接的第二电压信号线VL3中，至少一条第二电压信号线VL3与绑定引脚140间隔设置，部分第二电压信号线VL3与位于绑定区B内的绑定引脚140通过直接接触实现电连接，从而能够实现对于该多列驱动芯片121的供电，减小了需要与绑定区B内的绑定引脚140直接电连接的第二电压信号线VL3的数量，由此需要设置的绑定引脚140的数量得以减少，从而减少了绑定区B的数量，减小了绑定区B所占用的空间，当发光基板100应用于显示装置1时，能够克服一些显示装置1(例如，笔记本电脑(Notebook))空间不足的问题，提高了发光基板100的适应性，拓宽了发光基板100的应用场景。
在此基础上，第四连接线1612与第二电压信号线VL3既可以设置在同一导电层，也可以设置在不同的导电层，实现了发光基板100的灵活布线；第四连接线1612与第二电压信号线VL3设置在同一导电层时，能够减少图案化导电层的步骤，从而简化发光基板100的制备工艺，减少掩模版(Mask)的数量，降低发光基板100的成本，并且还能够减少发光基板100发生短路等不良故障的情况，提高发光基板100的良品率。
在一些实施例中，如图3E和图4A所示，第二类信号线1302包括数据信号线VL4，数据信号线VL4与驱动芯片121电连接。多条第二类连接线160包括至少一条第五连接线1613。与上述M列N个驱动芯片连接的数据信号线VL4中，至少两条数据信号线VL4通过第五连接线1613电连接。
示例性的，数据信号线VL4用于传输数据信号。
示例性的，如图3E和图4A所示，多条第二类连接线160可以包括一条第五连接线1613，也可以包括多条第五连接线1613。
示例性的，在多条第二类连接线160包括多条第五连接线1613时，同一条第五连接线1613连接的数据信号线VL4的数量可以相同，也可以不同，本公开的实施例对此不做限制。示例性的，如图3E和图4A所示，同一条第五连接线1613可以用于连接两条数据信号线VL4。
示例性的，与上述M列N个驱动芯片的连接的数据信号线VL4的数量为M条，同一条第五连接线1613可以用于连接所述M条数据信号线VL4中的两条数据信号线VL4。或者，同一条第五连接线1613可以用于连接所述M条数据信号线VL4中的多条数据信号线VL4。图3E和图4A示意出了同一条第四连接线1612可以用于连接两条数据信号线VL4。
示例性的，如图3E和图4A所示，数据信号线VL4位于功能区F，一条数据信号线VL4与一列驱动芯片121电连接，且与同一条第五连接线1613电连接的多条数据信号线VL4中，至少一条数据信号线VL4与绑定引脚140间隔设置，部分数据信号线VL4从功能区F延伸至绑定区B，且与位于绑定区B内的绑定引脚140电连接。
示例性的，同一条第五连接线1613连接的多条数据信号线VL4中，一条数据信号线VL4的一端与绑定区B内的绑定引脚140电连接，另一端延伸至功能区F，且与一列驱动芯片121电连接。由上述可知，驱动芯片121与发光器件组122电连接，从而使得数据信号线VL4能够通过驱动芯片121与发光器件组122电连接。
在一些示例中，如图3E所示，驱动芯片121具有一个数据引脚Dip。数据信号线VL4的一端通过绑定引脚140与印刷电路板电连接，数据信号线VL4的另一端与驱动芯片121(一个或多个)的数据引脚Dip电连接。
在一些示例中，如图4A所示，驱动芯片121具有两个数据端口Data。两个数据端口Data中一个为数据输入端口，另一个为数据输出端口，此时，数据信号线VL4可以包括多个子数据信号线。子数据信号线用于连接相邻的两个驱动芯片121。子数据信号线的一端与该相邻的两个驱动芯片121中一者的数据输出端口电连接，子数据信号线的另一端与该相邻的两个驱动芯片121中另一者的数据输入端口电连接。
在一些示例中，第五连接线1613与数据信号线VL4可以设置在同一导电层。
在又一些示例中，第五连接线1613与数据信号线VL4可以设置在不同的导电层。例如，第五连接线1613与数据信号线VL4可以分别设置在两层导电层上。此时，第五连接线1613与数据信号线VL4的材料可以相同，也可以不同。本公开的实施例对此不做限制。
本实施例中，M列N个驱动芯片的连接的多条数据信号线VL4中，至少两条数据信号线VL4通过第五连接线1613实现电连接，第五连接线1613连接的多条数据信号线VL4中，至少一条数据信号线VL4与绑定引脚140间隔设置，部分数据信号线VL4与位于绑定区B内的绑定引脚140通过直接接触实现电连接，就能够为该多列驱动芯片121提供数据信号，减小了需要与绑定区B内的绑定引脚140直接电连接的数据信号线VL4的数量，由此需要设置的绑定引脚140的数量得以减少，从而需要较少的绑定区B，来设置绑定引脚140，有效减少了绑定区B的数量，减小了绑定区B所占用的空间，当发 光基板100应用于显示装置1时，能够克服一些显示装置1(例如，笔记本电脑(Notebook))空间不足的问题，提高了发光基板100的适应性，拓宽了发光基板100的应用场景。
在一些实施例中，如图3E所示，第五连接线1613沿第二方向Y延伸，且位于功能区F靠近绑定区B的一侧。
示例性的，第五连接线1613与上述M列N个驱动芯片的连接的数据信号线VL4中的至少两条数据信号线VL4的同一端电连接。
示例性的，同一条第五连接线1613用于连接两条数据信号线VL4，该第五连接线1613以及与该第五连接线1613连接的两条数据信号线VL4整体呈S型。
示例性的，同一条第五连接线1613连接的多条数据信号线VL4并联设置。
本实施例中，第五连接线1613沿第二方向Y延伸，与上述M列N个驱动芯片的连接的数据信号线VL4中的至少两条数据信号线VL4的同一端电连接，第五连接线1613连接的多条数据信号线VL4中，至少一条数据信号线VL4与绑定引脚140间隔设置，部分数据信号线VL4与位于绑定区B内的绑定引脚140通过直接接触实现电连接，从而能够减小需要与绑定区B内的绑定引脚140直接电连接的接地信号线VL2的数量，从而减少绑定区B的数量。
在一些实施例中，如图4A所示，第五连接线1613与上述M列N个驱动芯片的连接的数据信号线VL4中的相邻两条数据信号线VL4电连接。其中，第五连接线1613与相邻两条数据信号线VL4中的一条的第一端电连接，并穿过相邻两列功能元件组120之间的间隙，与相邻两条数据信号线VL4中的另一条的第二端电连接。
示例性的，同一条第五连接线1613连接的两条数据信号线VL4之间串联设置。
示例性的，与上述M列N个驱动芯片连接的数据信号线VL4的数量为M条，该M条数据信号线VL4通过M-1条数据信号线VL4实现串联连接。例如，如图4A所示，图4A中示意出了两行、四列驱动芯片。该四列驱动芯片连接的数据信号线VL4的数量为四条，该四条数据信号线VL4通过三条第五连接线1613实现串联连接。
在一些示例中，第五连接线1613与数据信号线VL4可以设置在不同的导电层，例如第五连接线1613与数据信号线VL4可以分别设置在两层导电 层上。此时，第五连接线1613的材料与数据信号线VL4的材料可以相同，也可以不同。本公开的实施例对此不做限制。
在又一些示例中，第五连接线1613的材料与数据信号线VL4的材料相同且同层设置，即设置在同一导电层，如图4A所示。
示例性的，第五连接线1613的材料与数据信号线VL4的材料可以均为金属，例如该金属可以为铜。
示例性的，第五连接线1613，与其电连接的数据信号线VL4呈一体结构。由此，可以使得该第五连接线1613，与其电连接的数据信号线VL4可以在一次构图工艺中形成，进而可以简化发光基板100的制备工艺。此外，该“一体结构”的设置，能够提高第五连接线1613与数据信号线VL4之间电连接的可靠，并且无需设置其他导电结构，降低了发光基板100的制备成本。
本实施例中，第五连接线1613采用绕线的方式，穿过相邻两列功能元件组120之间的间隙，实现了M列N个驱动芯片的连接的数据信号线VL4中的相邻两条数据信号线VL4之间的电连接，M列N个驱动芯片连接的多条数据信号线VL4中，至少一条数据信号线VL4与绑定引脚140间隔设置，部分数据信号线VL4与位于绑定区B内的绑定引脚140通过直接接触实现电连接，从而能够为该多列驱动芯片121提供数据信号，减小了需要与绑定区B内的绑定引脚140直接电连接的数据信号线VL4的数量，由此需要设置的绑定引脚140的数量得以减少，从而减少了绑定区B的数量，减小了绑定区B所占用的空间，当发光基板100应用于显示装置1时，能够克服一些显示装置1(例如，笔记本电脑(Notebook))空间不足的问题，提高了发光基板100的适应性，拓宽了发光基板100的应用场景。
在此基础上，第五连接线1613与数据信号线VL4既可以设置在同一导电层，也可以设置在不同的导电层，实现了发光基板100的灵活布线；第五连接线1613与数据信号线VL4设置在同一导电层时，能够减少图案化导电层的步骤，从而简化发光基板100的制备工艺，减少掩模版的数量，降低发光基板100的成本，并且还能够减少发光基板100发生短路等不良故障的情况，提高发光基板100的良品率。
以下，以M列N个驱动芯片串联设置为例，进行说明。
示例性的，同一列功能元件组120中的多个发光器件组122沿第二方向Y排列为n列，也即，每列驱动芯片121控制n列发光器件组122，该M列N个驱动芯片所控制的发光器件组122的列数为M×n，该M×n列发光器件组122连接的M×n条第一电压信号线VL1并联设置。
例如，如图3A所示，每列驱动芯片121控制两列发光器件组122，两列N个驱动芯片通过第三连接线1611串联设置，该两列N个驱动芯片控制四列发光器件组122，此时，该四列发光器件组122所连接的四条第一电压信号线VL1并联设置。
又例如，如图4A所示，每列驱动芯片121控制一列发光器件组122，四列N个驱动芯片通过第三连接线1611串联设置，该四列N个驱动芯片控制四列发光器件组122，此时，该四列发光器件组122所连接的四条第一电压信号线VL1并联设置。
示例性的，一列N个驱动芯片与一条第二电压信号线VL3连接，该M列N个驱动芯片连接的M条第二电压信号线VL3之间并联设置。
例如，如图3D所示，两列N个驱动芯片通过第三连接线1611串联设置，该两列N个驱动芯片连接的两条第二电压信号线VL3并联设置。
示例性的，一列N个驱动芯片与一条第二电压信号线VL3连接，该M列N个驱动芯片连接的M条第二电压信号线VL3之间串联设置。
例如，如图4A所示，四列N个驱动芯片通过第三连接线1611串联设置，该四列N个驱动芯片连接的四条第二电压信号线VL3串联设置。
示例性的，一列N个驱动芯片与一条接地信号线VL2连接，该M列N个驱动芯片连接的M条接地信号线VL2之间并联设置。
例如，如图3B所示，两列N个驱动芯片通过第三连接线1611串联设置，该两列N个驱动芯片连接的两条接地信号线VL2并联设置。
又例如，如图4A所示，四列N个驱动芯片通过第三连接线1611串联设置，该四列N个驱动芯片连接的四条接地信号线VL2并联设置。
示例性的，一列N个驱动芯片与一条数据信号线VL4连接，该M列N个驱动芯片连接的M条数据信号线VL4之间串联设置，且该M条数据信号线VL4中任意两条数据信号线VL4，与连接该任意两条数据信号线VL4的第五连接线1613整体呈S型，如图4A所示。
在本公开的一些实施例中，多条第一类连接线150可以同时包括第一连接线1511、第二连接线1512；多条第二类连接线160可以同时包括第三连接线1611、第四连接线1612以及第五连接线1613中的一个或多个，基于前述的各种组合变型均不脱离本公开的原理，对此不再赘述。
示例性的，如图3F和图4A所示，多条第一类连接线150同时包括第一连接线1511、第二连接线1512；且多条第二类连接线160可以包括第三连接线1611、第四连接线1612以及第五连接线1613。
可以理解的是，多条第一类连接线150包括的第一连接线1511、第二连接线1512，以及多条第二类连接线160包括的第三连接线1611、第四连接线1612以及第五连接线1613中的数量越多，得以减少的绑定引脚140的数量越多，绑定区B的数量越少。
示例性的，以四列功能元件组120为例进行说明。
如图6所示，在每个信号线组130中的电源信号线VLED、芯片电源信号线VCC、输入信号线Dis、数据信号线Data、接地信号线GND、输出信号线FB分别与不同的绑定引脚140电连接时，该四列功能元件组120中的信号线组130所包括的电源信号线VLED、芯片电源信号线VCC、输入信号线Dis、数据信号线Data、接地信号线GND、输出信号线FB分别与不同的绑定引脚140电连接，此时，与该四列功能元件组120中的信号线组130连接的绑定引脚的数量为24个。
如图4A所示，多条第一类连接线150可以同时包括第一连接线1511、第二连接线1512；且多条第二类连接线160可以包括第三连接线1611、第四连接线1612以及第五连接线1613。第一连接线1511连接的四条第一电压信号线VL1中，仅一条第一电压信号线VL1与绑定引脚140电连接；第二连接线1512连接的四条接地信号线VL2中，仅一条接地信号线VL2与绑定引脚140电连接；第四连接线1612连接的四条第二电压信号线VL3中，仅一条第二电压信号线与绑定引脚140电连接；第五连接线1613连接的四条数据信号线VL4中，仅一条数据信号线VL4与绑定引脚140电连接；四列N个驱动芯片中，其中一列N个驱动芯片的第一级驱动芯片121所连接的地址信号线DL从功能区F延伸至绑定区B，且与位于绑定区B内的绑定引脚140电连接；其中另一列N个驱动芯片的一端与第三连接线1611电连接，另一端与输出线FB电连接，该输出线FB从功能区F延伸至绑定区B，与位于绑定区B内的绑定引脚140电连接。此时，与该四列功能元件组120中的信号线组130连接的绑定引脚的数量为6个。显然，需要设置的绑定引脚140的数量得以减少。
综上，本公开提供的发光基板100，通过第一类连接线150连接至少两个信号线组130中传输相同信号的第一类信号线1301，同时，与第一类连接线150电连接的多条第一类信号线1301中，仅一部分第一类信号线1301与绑定引脚140电连接，减少了需要与绑定引脚140电连接的第一类信号线1301的数量，由此需要设置的绑定引脚140的数量得以减少，从而需要较少的绑定区B，来设置绑定引脚140，有效减少了绑定区B的数量，满足了一些产品窄 边框设计的需求。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种发光基板，具有沿第一方向间隔排列的功能区和绑定区；所述发光基板包括：
    衬底；
    位于所述衬底一侧、且位于所述功能区的多个功能元件组；所述多个功能元件组分别沿第一方向排列成多行，且沿第二方向排列成多列，所述第一方向和所述第二方相交；
    位于所述功能区的多个信号线组，与所述多个功能元件组位于所述衬底的同一侧，一个信号线组与一列功能元件组电连接；所述信号线组包括至少一条第一类信号线，各所述第一类信号线沿所述第一方向延伸，且沿第二方向间隔排布；
    多条第一类连接线，第一类连接线用于连接至少两个信号线组中传输相同信号的第一类信号线；
    位于所述绑定区的多个绑定引脚；
    其中，与所述第一类连接线电连接的多条第一类信号线中，至少一条第一类信号线与绑定引脚间隔设置。
  2. 根据权利要求1所述的发光基板，其中，功能元件组包括至少一个发光器件组；
    所述第一类信号线包括至少一条第一电压信号线，所述第一电压信号线与所述发光器件组电连接；
    所述多条第一类连接线包括至少一条第一连接线；
    所述第一连接线，与所述至少两个信号线组中的第一电压信号线的同一端电连接。
  3. 根据权利要求2所述的发光基板，其中，所述第一连接线沿所述第二方向延伸，且位于所述功能区远离所述绑定区的一侧。
  4. 根据权利要求2或3所述的发光基板，其中，同一列功能元件组中的多个发光器件组排列为至少一列；
    一列发光器件组与一条所述第一电压信号线电连接。
  5. 根据权利要求4所述的发光基板，其中，与该第一电压信号线连接的一列发光器件组在所述衬底上的正投影，与该第一电压信号线在所述衬底上的正投影至少部分交叠。
  6. 根据权利要求2～5中任一项所述的发光基板，其中，所述功能元件组还包括驱动芯片，同一列功能元件组中的多个驱动芯片沿所述第一方向排列 为一列；
    所述同一列功能元件组中的多个发光器件组，位于所述同一列功能元件组中的多个驱动芯片沿所述第一方向的相对两侧。
  7. 根据权利要求1～6中任一项所述的发光基板，其中，功能元件组包括驱动芯片；
    所述第一类信号线包括接地信号线，所述接地信号线与所述驱动芯片电连接；
    所述多条第一类连接线包括至少一条第二连接线；
    所述第二连接线，与所述至少两个信号线组中的接地信号线的同一端电连接。
  8. 根据权利要求7所述的发光基板，其中，所述第二连接线沿所述第二方向延伸，且位于所述功能区靠近所述绑定区的一侧。
  9. 根据权利要求1～8中任一项所述的发光基板，其中，每个功能元件组包括一个驱动芯片，每列功能元件组的数目为N，所述每列功能元件组中的N个驱动芯片依次级联；所述信号线组还包括至少一条第二类信号线，各所述第二类信号线沿所述第一方向延伸，且沿第二方向间隔排布；
    所述发光基板还包括：多条第二类连接线，第二类连接线用于连接至少两个信号线组中传输相同信号的第二类信号线；
    位于所述绑定区的多个绑定引脚；
    其中，与所述第二类连接线电连接的多条第二类信号线中，至少一条第二类信号线与绑定引脚间隔设置。
  10. 根据权利要求9所述的发光基板，其中，
    所述第二类信号线包括多条地址信号线，所述N个驱动芯片中任意相邻的两个驱动芯片之间通过地址信号线级联；
    所述多条第二类连接线包括至少一条第三连接线；
    M列相邻的功能元件组中，两个分别属于相邻两列功能元件组的驱动芯片通过所述第三连接线级联，其中，M≥2，且M为正整数。
  11. 根据权利要求10所述的发光基板，其中，所述第三连接线与所述相邻两列所述N个驱动芯片中的一者的第1个驱动芯片电连接，并穿过相邻两列功能元件组之间的间隙，与所述相邻两列所述N个驱动芯片中的另一者的第N个驱动芯片电连接。
  12. 根据权利要求10所述的发光基板，其中，所述第三连接线沿所述第二方向延伸，且位于所述功能区远离所述绑定区的一侧。
  13. 根据权利要求10～12中任一项所述的发光基板，其中，
    所述第二类信号线包括第二电压信号线，所述第二电压信号线与所述驱动芯片电连接；
    所述多条第二类连接线包括至少一条第四连接线；
    与所述M列所述N个驱动芯片的连接的所述第二电压信号线中，至少两条第二电压信号线通过所述第四连接线相连接。
  14. 根据权利要求13所述的发光基板，其中，所述第四连接线沿所述第二方向延伸，且位于所述功能区靠近所述绑定区的一侧。
  15. 根据权利要求13所述的发光基板，其中，所述第四连接线与所述M列所述N个驱动芯片的连接的所述第二电压信号线中的相邻两条第二电压信号线电连接；
    其中，所述第四连接线与所述相邻两条第二电压信号线中的一条的第一端电连接，并穿过相邻两列功能元件组之间的间隙，与所述相邻两条第二电压信号线中的另一条的第二端电连接。
  16. 根据权利要求10～15中任一项所述的发光基板，其中，
    所述第二类信号线包括数据信号线，所述数据信号线与所述驱动芯片电连接；
    所述多条第二类连接线包括至少一条第五连接线；
    与所述M列所述N个驱动芯片的连接的所述数据信号线中，至少两条数据信号线通过所述第五连接线相连接。
  17. 根据权利要求16所述的发光基板，其中，所述第五连接线沿所述第二方向延伸，且位于所述功能区靠近所述绑定区的一侧。
  18. 根据权利要求16所述的发光基板，所述第五连接线与所述M列所述N个驱动芯片的连接的所述数据信号线中的相邻两条数据信号线电连接；
    其中，所述第五连接线与所述相邻两条数据信号线中的一条的第一端电连接，并穿过相邻两列功能元件组之间的间隙，与所述相邻两条数据信号线中的另一条的第二端电连接。
  19. 根据权利要求1～18中任一项所述的发光基板，其中，功能元件组包括至少一个发光器件组，所述发光器件组包括多个发光器件；
    多个所述发光器件组所包括的发光器件沿第一方向排列成多行，且沿第二方向排列成多列；
    任意相邻的两行发光器件错开设置。
  20. 一种背光模组，包括：
    如权利要求1～19中任一项所述的发光基板；以及，
    位于所述发光基板的出光侧的光学膜片。
  21. 一种显示装置，包括：
    如权利要求20所述的背光模组；
    位于所述背光模组出光侧的阵列基板；以及，
    位于所述阵列基板远离所述背光模组一侧的彩膜基板。
PCT/CN2022/136362 2022-12-02 2022-12-02 发光基板、背光模组及显示装置 WO2024113380A1 (zh)

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CN211457461U (zh) * 2020-01-19 2020-09-08 酷矽半导体科技(上海)有限公司 发光二极管驱动芯片
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CN114512062A (zh) * 2020-10-28 2022-05-17 北京京东方光电科技有限公司 一种发光模组及其驱动方法、显示装置
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