WO2022160216A1 - 阵列基板和显示装置 - Google Patents

阵列基板和显示装置 Download PDF

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Publication number
WO2022160216A1
WO2022160216A1 PCT/CN2021/074256 CN2021074256W WO2022160216A1 WO 2022160216 A1 WO2022160216 A1 WO 2022160216A1 CN 2021074256 W CN2021074256 W CN 2021074256W WO 2022160216 A1 WO2022160216 A1 WO 2022160216A1
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WIPO (PCT)
Prior art keywords
sub
conductive
opening area
opening
conductive portion
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PCT/CN2021/074256
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English (en)
French (fr)
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WO2022160216A9 (zh
Inventor
雷杰
许邹明
田�健
刘纯建
吴信涛
王杰
曾琴
张建英
张志�
王庆浦
张传稳
方振中
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/074256 priority Critical patent/WO2022160216A1/zh
Priority to CN202180000084.7A priority patent/CN115362556A/zh
Priority to DE112021003516.9T priority patent/DE112021003516T5/de
Priority to TW110136840A priority patent/TWI806179B/zh
Priority to US17/517,640 priority patent/US20220238771A1/en
Publication of WO2022160216A1 publication Critical patent/WO2022160216A1/zh
Publication of WO2022160216A9 publication Critical patent/WO2022160216A9/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate and a display device.
  • Mini-LED is a new type of LED display technology derived from small-pitch LEDs, also known as sub-millimeter light-emitting diodes. Its die size is about 100 to 200um, which is between traditional LED and Micro LED. Due to its good display effect, thin and light experience, high contrast ratio, long life and other advantages, it has an obvious trend of use in the high-end display field.
  • the purpose of the present disclosure is to provide an array substrate and a display device.
  • an array substrate including:
  • a first conductive layer disposed on one side of the base substrate, including a first conductive portion
  • a second conductive layer disposed on the side of the first conductive layer away from the base substrate, includes a second conductive portion
  • the first conductive portion has an opening area, and at least part of the projection of the second conductive portion on the base substrate is located in an area surrounded by the projection of the opening area Inside.
  • a projected edge of a portion of the second conductive portion corresponding to the opening area has a gap with a projected edge of the opening area.
  • the second conductive portion includes at least any one of a pad, a first lead, a second lead, and a functional unit;
  • the open area includes at least any one of a first open area, a second open area, a third open area, and a fourth open area.
  • the opening area includes a first opening area, and the first opening area includes a plurality of first sub-opening areas;
  • the second conductive part includes a plurality of groups of pads, and each group of the pads includes a plurality of sub-pads;
  • the projections of at least part of the sub-pads on the base substrate are located in the area enclosed by the projections of the first sub-opening regions, and the projected outer peripheries of the sub-pads are the same as those of the sub-pads.
  • the projected edge of the corresponding first sub-opening area has a gap.
  • each of the first sub-opening areas corresponding to each of the sub-pads of the same group of the pads is communicated with each other
  • the opening area includes a second opening area
  • the second opening area includes at least one second sub-opening Area
  • the second conductive part includes a first lead extending along the first direction
  • At least part of the projection of the first lead on the base substrate overlaps with the projection of the second opening area, and the projected edge of at least one side of the first lead and the projected edge of the second opening area have gap.
  • the number of the second sub-opening areas is plural, and at least two of the second sub-opening areas are communicated with each other.
  • the opening area includes a third opening area
  • the third opening area includes at least one third sub-opening Area
  • the second conductive portion includes a second lead extending along a second direction, the second direction intersecting the first direction;
  • At least part of the projection of the second lead on the base substrate overlaps with the area enclosed by the projection of the third sub-opening area, and the edges on opposite sides of the second lead overlap with the third sub-opening area.
  • the projected edge of the open area has a gap.
  • the number of the third sub-opening regions is plural, and at least two of the third sub-opening regions are communicated with each other.
  • the opening area includes a fourth opening area, and the fourth opening area includes at least one fourth sub-opening area;
  • the second conductive part includes several functional units
  • the projections of each of the functional units on the base substrate are located within the projected area shadow of each of the fourth sub-opening areas, and the projected outer peripheries of the functional units are all corresponding to the corresponding
  • the projected edge of the fourth sub-opening area has a gap.
  • the number of the fourth sub-opening areas is plural, and at least two of the fourth sub-opening areas are communicated with each other.
  • the functional unit includes a first test conductive portion electrically connected to the pad, the first lead or the second lead, and the first test conductive portion is used to detect all the the electrical properties of the pad, the first lead or the second lead.
  • At least two of the first open area, the second open area, the third open area, and the fourth open area communicate with each other.
  • the gap between the projected edge of the second conductive portion and the corresponding projected edge of the sub-opening area is greater than or equal to a predetermined value, and the predetermined value includes Sum of process tolerance, maximum size of impurities and reserved spacing;
  • the process tolerance refers to the allowable size deviation in the manufacturing process of the first conductive part and/or the second conductive part
  • the maximum size of impurities refers to the maximum diameter of the impurity particles in the process
  • the reserved spacing is the size of the The spacing value that is set manually according to the gap.
  • the preset value is 20 ⁇ m.
  • the first conductive layer further includes a plurality of conductive islands, at least one of the sub-opening regions has the conductive islands, and the outer periphery of the conductive islands corresponds to the corresponding The edge of the sub-opening area has a gap;
  • the projection of at least one of the sub-pad, the first lead, the second lead, or the first test conductive portion on the base substrate is located within the projection of the corresponding conductive island or with the projection of each of the conductive islands.
  • the projections are completely coincident.
  • the gap between the periphery of the conductive island and the edge of the corresponding sub-opening region is greater than or equal to a predetermined value, and the predetermined value includes a process tolerance, a maximum size of impurities and The sum of reserved spacing.
  • the preset value is 20 ⁇ m.
  • the material of the conductive island is the same as the material of the first conductive portion.
  • At least two of the sub-opening regions in the same opening region are connected to each other, and each of the conductive islands in the interconnected sub-opening regions is independent of each other or connected to each other as one.
  • At least two of the first open area, the second open area, the third open area, and the fourth open area are communicated with each other, and the open areas in the interconnected open areas are in communication with each other.
  • Each of the conductive islands is independent of each other or connected as a whole.
  • the second conductive layer further includes a second test conductive portion, the second test conductive portion overlaps with the projection of the first conductive portion on the base substrate, and Electrically connected through via holes, the second test conductive part is used to detect the electrical performance of the first conductive part
  • a display device including the above-mentioned array substrate.
  • 1 is a schematic structural diagram of an array substrate of a mini LED
  • Fig. 2 is a partial enlarged view of M area in Fig. 1;
  • FIG. 3 is a schematic diagram of a pad structure of an LED light-emitting device in an embodiment
  • Fig. 4 is the cross-sectional schematic diagram of A-A in Fig. 3;
  • FIG. 5 is a schematic diagram of another pad structure of the LED light-emitting device
  • Fig. 6 is the cross-sectional schematic diagram of A-A in Fig. 5;
  • FIG. 7 is a schematic diagram of a pad structure of an IC driving chip pad
  • Fig. 8 is another kind of pad structure schematic diagram of IC driving chip pad
  • Fig. 9 is a kind of structural schematic diagram of the first lead
  • FIG. 10 is a schematic structural diagram of a second lead
  • FIG. 11 is a schematic structural diagram of a first test conductive portion
  • Fig. 12 is a kind of structural schematic diagram that each opening area is connected
  • FIG. 13 is a schematic diagram of a pad structure of an LED light-emitting device including conductive islands
  • Fig. 14 is the cross-sectional schematic diagram of the A-A direction in Fig. 9;
  • 15 is a schematic diagram of another pad structure of the LED light-emitting device including conductive islands;
  • Fig. 16 is the cross-sectional schematic diagram of A-A in Fig. 11;
  • FIG. 17 is a schematic diagram of a pad structure in which a pad of an IC driver chip includes a conductive island;
  • FIG. 18 is a schematic diagram of another pad structure in which the pad of the IC driver chip includes a conductive island;
  • 19 is a schematic diagram of a structure in which the first lead and the second lead include conductive islands;
  • FIG. 20 is a schematic structural diagram of a first test conductive portion including a conductive island and a second test conductive portion;
  • Fig. 21 is the cross-sectional schematic diagram of the direction A-A in Fig. 20;
  • FIG. 22 is another partial enlarged view of the M area in FIG. 1 .
  • the first conductive layer; 10, the first conductive part; 110 the opening area; 111, the first opening area; 1110, the first sub-opening area; 112, the second opening area; 1120, the second sub-opening area; 113, third opening area; 1130, third sub-opening area; 114, fourth opening area; 1140, fourth sub-opening area; 120, conductive island; 200, second conductive layer; 20, second conductive portion 210, pad; 2110, sub-pad; 220, first lead; 230, second lead; 241, first test conductive part; 242, second test conductive part; 300, first insulating layer; 400, first An inorganic layer; 500, a second insulating layer; 600, a second inorganic layer; 900, a base substrate.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • a certain structure When a certain structure is "on” other structures, it may mean that a certain structure is integrally formed on other structures, or that a certain structure is “directly” arranged on other structures, or that a certain structure is “indirectly” arranged on another structure through another structure. other structures.
  • FIG. 1 it is a schematic structural diagram of an array substrate of a mini LED.
  • FIG. 2 is a partial enlarged view of the M region in FIG. 1, showing the structure of a light-emitting unit.
  • the light-emitting unit includes four light-emitting devices connected in series, the light-emitting device electrically connected to the driving voltage line VLED is used as the starting point of the series connection of the four light-emitting devices, and the light-emitting device electrically connected with the driving IC is used as the end point of the series connection of the four light-emitting devices.
  • the four light-emitting devices are driven by one driver IC.
  • the number of light-emitting devices in each light-emitting unit is not limited, and may be any number such as 5, 6, 7, and 8, but is not limited to 4.
  • the light-emitting device may be Mini LED, OLED or any other light-emitting device.
  • the Mini-LED array substrate includes a base substrate 900 , a first conductive layer 100 and a second conductive layer 200 .
  • the first conductive layer 100 is disposed on one side of the base substrate 900 and includes the first conductive portion 10 .
  • the second conductive layer 200 is disposed on the side of the first conductive layer 100 away from the base substrate 900 and includes the second conductive portion 20 .
  • a first insulating layer 300 and a first inorganic layer 400 are provided between the first conductive layer 100 and the second conductive layer 200 , and a second insulating layer 500 and a second inorganic layer 600 are provided above the second conductive layer 200 .
  • the first conductive layer 100 is usually used for arranging various signal lines, that is, the first conductive portion 10 can be various signal lines, such as a common voltage line GND, a driving voltage line VLED, a source power line PWR, a source address line DI, and the like.
  • the thickness of the film layer is about 1.5-7 ⁇ m, and its material includes copper.
  • a laminated material such as MoNb/Cu/MoNb can be formed by sputtering, and the bottom layer is Used to improve adhesion, the middle layer Cu is used to transmit electrical signals, the top layer Used to prevent oxidation.
  • the film layer can also be formed by electroplating. First, a seed layer MoNiTi is formed to increase the nucleation density of crystal grains, and then an anti-oxidation layer MoNiTi is formed after electroplating.
  • the second conductive layer 200 is usually used to set various pads, that is, the second conductive portion 20 can be various pads, such as pads for mounting functional elements or pads for mounting functional element driver chips;
  • the conductive layer 200 may also be provided with a lead for connection, that is, the second conductive portion 20 may also be a lead.
  • the thickness of the film layer is about 6000, and its material can be, for example, a laminated material of MoNb/Cu/CuNi, the bottom layer MoNb is used to improve the adhesion, the middle layer Cu is used to transmit electrical signals, and the top layer CuNi can take into account the protection Oxidation and solid state fastness.
  • An insulating layer is provided between the first conductive layer 100 and the second conductive layer 200 .
  • the pads on the upper layer overlap with the signal lines on the lower layer, during subsequent soldering of functional components, such as when using SMT reflow soldering technology to solder LED chips, since the temperature in the soldering zone reaches 260-265°C, this temperature is likely to exceed the intermediate insulation.
  • the temperature resistance value of the layer causes the OC at the pad to be damaged, which in turn leads to a short circuit between the pad and the signal line.
  • the sharp-angled particles of the LED may also stab the pad and the insulating layer, resulting in a short circuit between the pad and the signal line.
  • the air-type static electricity generated at the edge of the overlap will easily break down the insulating layer, resulting in a short circuit between the leads and the signal lines.
  • the particles generated in the process cannot be completely eliminated.
  • the particles fall on the overlapping area of the lead and the signal line, it is easy to cause unstable conduction between the lead and the signal line, which affects the reliability of the product.
  • the upper-layer lead wire is tested for current or voltage by the needle-stick test method, it is easy to break the insulating layer and tie the signal line below, resulting in inaccurate test or reduced accuracy.
  • the first conductive part 10 is usually thicker and wider to provide a larger voltage/current and lower resistance
  • the second conductive part 20 is usually set narrower and shorter, and exists as structures such as leads and pads. Therefore, there is a certain potential difference between the two. Since the insulating layer between the two conductive parts is in a semi-solid and semi-liquid state before curing in the glass-based film manufacturing process, the water vapor introduced during the process may remain in the insulating layer.
  • the essence of the growth of Cu in the conductive part is electrochemical corrosion, water easily triggers an electrochemical reaction in the presence of a potential difference, and the formation of OH - in the insulating layer, OH - will cause the first conductive part 10 and the second conductive part 20 to short-circuit .
  • the projections of at least part of the second conductive part 20 and the first conductive part 10 on the base substrate do not overlap, that is, in the thickness direction of the array substrate, at least part of the second conductive part 20 and the first conductive part 10 do not overlap. If the conductive parts 10 do not overlap, the non-overlapping places can avoid short circuits between the two due to static electricity, process technology, testing and other reasons, thereby improving product performance stability. Of course, in a completely ideal situation, if the projections of all the second conductive parts 20 and the first conductive parts 10 on the base substrate do not overlap, short circuits can be completely avoided.
  • the first conductive part 10 needs to provide a larger voltage/current and a lower IR drop, it is usually set wider, and the second conductive part 20 is usually a smaller structure such as a lead, a pad, etc., and is usually set narrower.
  • the line width ratio of the first conductive portion 10 and the second conductive portion 20 is about 20 to 30, and for a large-sized product, the line width ratio of the first conductive portion 10 and the second conductive portion 20 can be as high as 100 times or even more, so the second conductive part and the first conductive part 10 must overlap.
  • the present disclosure provides an opening area 110 in the first conductive portion 10 , which includes a hollow area located in the middle of the first conductive portion 10 , and the hollow area has an annular complete edge, It also includes a hollow area located at the edge of the first conductive portion 10, and the hollow area has a part of the edge.
  • the opening area 110 is a hollow area
  • the present disclosure considers that its projection on the base substrate is the projection of the edge of the surrounding film layer, that is, an annular edge.
  • the present disclosure uses the area enclosed by the annular projected edge as a reference.
  • the projection of at least part of the second conductive portion 20 (ie, the second conductive portion 20 at the overlapping portion) on the base substrate 900 is located within the area enclosed by the projection of the opening area 110 .
  • the projection of the second conductive part 20 at the overlap referred to in the present disclosure is located in the area enclosed by the projection of the opening area 110 , including two cases, one is at least a partial projection of the second conductive part 20
  • the edge is located inside the projected edge of the opening area, and the projected area of the second conductive portion 20 is smaller than the area of the area enclosed by the projection of the opening area.
  • the projection of the second conductive portion 20 completely coincides with the area enclosed by the projection of the opening area 110 , which means that the shapes of the two projections are the same and completely coincident. In either case, it refers to hollowing out the first conductive portion 10 under the overlapping area, so as to avoid the first conductive portion 10 and the second conductive portion 20 in the overlapping area due to static electricity, process technology, testing and other reasons. A short circuit occurs to avoid affecting product performance stability.
  • a certain gap may be set between the projected edge of the portion of the second conductive portion 20 corresponding to the opening region 110 and the projected edge of the opening region 110, so that a certain distance is reserved between the second conductive portion 20 and the edge of the first conductive portion 10, and further The possibility of a short circuit between the two is reduced.
  • the second conductive portion 20 includes multiple groups of pads 210 .
  • the pad 210 may be a pad for mounting a functional device, such as a light-emitting device, a sensor, etc., or a pad for mounting a functional device driver chip.
  • FIG. 3 it is a partially enlarged schematic diagram of the N region in FIG. 2 .
  • the pad 210 includes two sub-pads 2110, one is an anode pad (shown by P in the figure), and the other is a cathode pad (shown by N in the figure).
  • FIG. 4 it is a schematic cross-sectional view along the A-A direction in FIG. 3 .
  • the first conductive portion 10 is the common voltage line GND, and the pads of the light emitting device overlap with the common voltage line GND in the thickness direction of the array substrate.
  • the opening area 110 of the first conductive portion 10 includes a first opening area 111, and the first opening area 111 includes two first sub-opening areas 1110; in the thickness direction of the substrate, the projection of the anode pad on the substrate.
  • the projection on the substrate 900 is located in an area enclosed by the projection of a first sub-opening area 1110 , and the projected peripheral edge of the anode pad has a gap with the projected edge of the first sub-opening area 1110 .
  • the projection of the cathode pad on the base substrate 900 is located in the area enclosed by the projection of the other first sub-opening area 1110 , and the projected outer peripheral edge of the cathode pad is the same as the projection of the first sub-opening area 1110 .
  • the projected edges have gaps.
  • the two first sub-opening regions 1110 are separated by the first conductive portion 10 that is not hollowed out, so that each first sub-opening region 1110 corresponds to a respective sub-pad 2110 .
  • the area where the first conductive portion 10 is facing the anode pad and the cathode pad is hollowed out, so that the anode pad, the cathode pad and the first conductive portion 10 below no longer overlap, thereby avoiding the bonding between the pad and the cathode pad.
  • the first conductive portion 10 is short-circuited due to soldering, die bonding and other reasons.
  • FIG. 6 is a schematic cross-sectional view along the A-A direction in FIG. 5 .
  • the two first sub-opening areas 1110 communicate with each other to form an opening, that is, the projections of the anode pad and the cathode pad are located in the area 110 enclosed by the projection of the same large opening area.
  • This structure can not only avoid the short circuit between the anode pad, the cathode pad and the first conductive part 10 , but also reduces the technological difficulty of hollowing out the first conductive part 10 .
  • the shapes of the sub-pads 2110 and the first sub-opening regions 1110 are the same, and both are substantially rectangular.
  • the pad includes four sub-pads 2110, which are the first input pad Di, the second input pad Pwr, the output pad Out and the common voltage respectively Pad Gnd.
  • the above-mentioned first input pad Di is configured to receive a first input signal, such as an address signal, for gating an IC driving chip of a corresponding address.
  • the first input signal may be an 8-bit address signal from the source address line DI, and the address to be transmitted may be obtained by parsing the address signal.
  • the second input pad Pwr is configured to receive a second input signal, eg, a power line carrier communication signal from the source power line PWR.
  • the second input signal not only provides power for the IC driver chip, but also transmits communication data to the IC driver chip.
  • the communication data can be used to control the luminous duration of the corresponding light-emitting unit, thereby controlling its visual luminous brightness.
  • the output pad Out is configured to output a driving signal.
  • the driving signal may be a driving voltage from the driving voltage line VLED for driving the light-emitting element to emit light.
  • the common voltage pad Gnd is configured to receive a common voltage signal, eg, a ground signal from the common voltage line GND.
  • the first conductive portion 10 is the common voltage line GND, and the pads of the IC driving chip overlap the common voltage line GND in the thickness direction of the array substrate.
  • the first opening area 111 of the first conductive portion 10 includes four first sub-opening areas 1110; in the thickness direction of the substrate, the projection of the first input pad Di on the base substrate 900 is located in the first first sub-opening area 1110, and there is a gap between the projected peripheral edge of the first input pad Di and the projected edge of the first sub-opening area 1110.
  • the projection of the second input pad Pwr on the base substrate 900 is located in the area enclosed by the projection of the second first sub-opening area 1110 , and the projected peripheral edge of the second input pad Pwr and the first sub-opening area
  • the projected edges of 1110 have gaps.
  • the projection of the output pad Out on the base substrate 900 is located in the area enclosed by the projection of the third first sub-opening area 1110 , and the projected outer peripheral edge of the output pad Out and the projected edge of the first sub-opening area 1110 with gaps.
  • the projection of the common voltage pad Gnd on the base substrate 900 is located in the area enclosed by the projection of the fourth first sub-opening region 1110 , and the projected outer peripheral edge of the common voltage pad Gnd and the projection of the first sub-opening region 1110 The edges have gaps.
  • the four first sub-opening regions 1110 are separated by the first conductive parts 10 that are not hollowed out, so that each of the first sub-opening regions 1110 corresponds to a respective sub-pad 2110 .
  • the area where the first conductive portion 10 is facing the four sub-pads 2110 is hollowed out, so that the four sub-pads 2110 and the first conductive portion 10 below do not overlap, thereby avoiding the pad and the first conductive portion. 10 short circuit problems.
  • first sub-opening regions 1110 corresponding to the sub-pads of the same group of pads are connected to each other, thereby reducing the difficulty of hollowing out.
  • the four first sub-opening areas 1110 are connected to each other to form an opening, that is, the first input pad Di, the second input pad Pwr, the output pad Out and the common voltage
  • the projection of the pad Gnd is located in the area enclosed by the projection of the same large opening area 110 . This structure can not only avoid short circuit between each sub-pad 2110 and the first conductive part 10 below, but also lowers the precision requirement for the hollowing process of the first conductive part 10 .
  • the shape of the sub-pad 2110 is substantially a pentagon, and the shape of the first sub-opening region 1110 is substantially a rectangle.
  • first sub-opening region 1110 does not limit the specific shape of the first sub-opening region 1110 , which may or may not be consistent with the shape of the sub-pad 2110 .
  • substantially pentagonal and substantially rectangular means that the outer contour of the sub-pad 2110 and the shape of the boundary of the first sub-opening area 1110 are in the shape of a pentagon or a rectangle as a whole, but are not limited to It is a standard pentagon or rectangle.
  • the pad may also have other numbers of sub-pads, such as 1, 3, etc. sub-pads.
  • the first opening area 111 includes a corresponding number of first sub-opening areas 1110 , so that each sub-pad corresponds to a first sub-opening area 1110 under each sub-pad to avoid overlapping at the sub-pads. It is not repeated here.
  • the array substrate includes a plurality of light-emitting device pads and a plurality of IC driver chip pads.
  • the first sub-opening regions 1110 corresponding to all the pads for binding the same functional device are connected to each other, for example, the first sub-opening regions 1110 corresponding to all the pads for binding the light-emitting device
  • the first sub-opening areas 1110 corresponding to all the pads bound to the IC driver chip are connected to each other.
  • the second conductive part 20 includes a first lead 220 , and the first lead 220 extends along the longitudinal direction (first direction) in the figure.
  • the first lead 220 is a longitudinal lead extending from the LED light emitting device.
  • the first lead 220 may also be a longitudinal lead extended from the pad of the IC driver chip.
  • the first conductive portion 10 is also the common voltage line GND, and the longitudinally extending first leads overlap with the longitudinally extending portion of the common voltage line GND in the thickness direction of the array substrate.
  • the opening of the first conductive portion 10 includes a second opening area 112 , and the second opening area 112 is located at a longitudinally extending portion of the first conductive portion 10 .
  • the second opening area 112 includes at least one second sub-opening area, and the projection of at least one section of the first lead 220 on the base substrate 900 is located in the area enclosed by the projection of the second sub-opening area 112 , that is, the At least one section of the first lead 220 corresponding to the first conductive portion 10 below is hollowed out, so that the first lead 220 and the lower first conductive portion 10 no longer overlap in this area, thereby avoiding the first lead 220 There is a short circuit with the first conductive portion 10 due to static electricity, testing and manufacturing.
  • the bottom of the first lead 220 may be hollowed out entirely, as shown in FIG. 9 , or only one section may be hollowed out. That is to say, the second opening area 112 may be provided below all the first leads 220 , or may be provided only below a partial area of the first leads 220 .
  • the corresponding second opening area 112 under the first lead 220 includes only one second sub-opening area 1120. In other embodiments, it may also include a plurality of second sub-opening areas. When the number of the second sub-opening regions 1120 is multiple, at least two second sub-opening regions 1120 may also be communicated with each other, thereby reducing the difficulty of hollowing out.
  • the second opening area 112 on the right is a closed area disposed inside the first conductive portion 10 , and has four boundaries, and the first lead 220 on the right side is on the left and right sides.
  • the second opening area 112 on the left side is a semi-closed area disposed on the inner edge of the first conductive portion 10 , that is, the second opening area 112 has three boundaries, the left side communicates with the blank area outside the first conductive portion 10 , and the left
  • the projected edge of the right side of the first lead 220 and the projected edge of the right side of the second opening area 112 have a gap.
  • the second conductive portion 20 further includes a second lead 230 extending in a lateral direction.
  • the second lead 230 may be a lateral lead extending from the IC driving chip pad, or may be a lateral lead extending from the LED light emitting device.
  • the first conductive portion 10 is also the common voltage line GND, and the laterally extending second leads 230 overlap with the longitudinally extending portion of the common voltage line GND in the thickness direction of the array substrate.
  • the opening of the first conductive part 10 includes a third opening area 113 , and the third opening area 113 is located in the longitudinally extending part of the first conductive part 10 ; the third opening area 113 includes at least one third sub-opening area, and at least one of the second leads 230
  • the projection of a section on the base substrate 900 is located in the area enclosed by the projection of the third sub-opening area 113 . That is, at least one section of the second lead 230 is hollowed out to the corresponding first conductive part 10 so that the second lead 230 and the first conductive part 10 below do not overlap in this area, so as to avoid The short circuit between the second lead 230 and the first conductive portion 10 is avoided due to static electricity, testing and manufacturing.
  • the bottom of the second lead 230 may be hollowed out entirely, or only a section may be hollowed out. That is to say, the third opening area 113 may be provided below all the second leads 230 , or may be provided only below a partial area of the second leads 230 .
  • the corresponding third opening area 113 below the second lead 230 includes only one third sub-opening area 1130 , and in other embodiments, may also include a plurality of third sub-opening areas 1130 . When the number of the third sub-opening regions 1130 is multiple, at least two third sub-opening regions can also be communicated with each other, thereby reducing the difficulty of hollowing out.
  • the first conductive portion 10 under the second lead 230 is hollowed out, thereby avoiding a short circuit between the second lead 230 and the first conductive portion 10 due to static electricity and process reasons.
  • the third opening area 113 corresponding to the second lead 230 may be located at the upper edge or the lower edge of the first conductive part 10 , or may be located in the middle of the first conductive part 10 . Therefore, there is a gap between the projected edge of at least one of the upper and lower sides of the second lead 230 and the projected edge of the third opening area 113 .
  • the third opening area 113 shown in FIG. 10 is a closed opening area, the projection of a section of the second lead 230 overlaps the projection of the third opening area 113 , and the projected edge of at least one of the upper and lower sides is the same as the projection of the third opening area 113 .
  • the projected edges of the three opening areas 113 have gaps.
  • the third open area 113 also extends in the lateral direction.
  • the lateral length of the third open area 113 should be is smaller than the width of the first conductive portion 10 , otherwise the first conductive portion 10 will be cut off. Therefore, when the second lead 230 passes through the entire first conductive part 10 in the lateral direction, only a part of the second lead 230 should be hollowed out below. It can be understood that, the longer the length of the third opening region 113 in the lateral direction, the greater the influence on the IR Drop of the longitudinally extending first conductive portion 10, resulting in a decrease in signal strength.
  • the longer the length of the third opening area 113 in the lateral direction the less the overlapping area of the second lead 230 and the first conductive portion 10, and the less likely to generate static electricity.
  • the lateral length of the third opening area 113 needs to be set comprehensively considering two reasons.
  • the second lead 230 can also span a plurality of longitudinally extending first conductive parts 10 at the same time, then, one or more third sub-opening regions 1130 can be provided in each of the first conductive parts 10 .
  • the corresponding third opening area 113 may include a plurality of third subsections.
  • the opening areas 1130 correspond to a plurality of parts on the second lead 230 respectively.
  • the second direction in which the second lead 230 extends may not be perpendicular to the first direction. Regardless of the direction, it should be ensured that the third opening region 113 corresponding to the second lead 230 will not cut off the first conductive portion 10, and the influence on the IR Drop should be minimized.
  • the shape of the first lead 220 or the second lead 230 is generally a strip shape
  • the shape of the second opening region 112 and the third opening region 113 is also generally a strip shape.
  • the present disclosure does not limit the specific shapes of the second opening area 112 and the third opening area 113 , which may or may not be consistent with the shape of the lead.
  • the second conductive portion 20 further includes several functional units for implementing specific functions.
  • the functional unit may be the first test conductive part 241, and the first test conductive part 241 is electrically connected to the pad, the first lead or the second lead, and is used to detect the pad or the first lead, the second lead Electrical properties of leads.
  • the current or voltage characteristics of the pads can be tested by using the pin-pin test method.
  • FIG. 11 shows the first test conductive portion 241 and the fourth opening area 114 corresponding to the three sub-pads in the IC driver chip pad.
  • the three first test conductive parts 241 are respectively arranged in the vicinity of the first input pad Di, the second input pad Pwr, and the output pad Out, and one end is connected to the sub-pad for testing the voltage and/or the sub-pad. Or current, the other end of which can also be connected with the first lead or the second lead.
  • the film layer (eg, the second insulating layer 500 and the second inorganic layer 600 ) above the first test conductive portion 241 is opened, so that the first test conductive portion 241 is exposed, so that the needle stick test can be performed there.
  • the opening area 110 includes a fourth opening area 114, the fourth opening area 114 includes three fourth sub-opening areas 1140, and the projections of the three first test conductive parts 241 on the base substrate are located in each fourth sub-opening area in a one-to-one correspondence.
  • the projection of the opening area 1140 there is a gap between the projection of the first test conductive portion 241 and the projection edge of the corresponding fourth sub-opening area 1140 .
  • the corresponding first conductive portion 10 below the first test conductive portion 241 is hollowed out, so that the first test conductive portion 241 and the lower first conductive portion 10 no longer overlap in this area, thereby avoiding Therefore, when the needle stick test is performed, the needle pierces the first test conductive portion 241 and contacts the first conductive portion 10, resulting in a short circuit or inaccurate test.
  • the common voltage pad Gnd is connected to the common voltage line GND through a via hole, the current or voltage of the common voltage pad Gnd can be directly tested on the common voltage line GND.
  • the number of the first test conductive parts 241 in this embodiment is only an example, and the specific number can be set as required.
  • first test conductive part 241 can be set for a certain sub-pad, and this application does not use the first test conductive part 241
  • the number of the conductive parts 241 is specifically limited.
  • the three fourth sub-opening regions 1140 are connected with each other, thereby reducing the difficulty of hollowing out.
  • the fourth sub-opening regions 1140 may also be independent of each other.
  • the array substrate of the present disclosure may only include any one of the above-mentioned second conductive parts 10 and corresponding opening areas 110 , or may include at least any two types of second conductive parts 10 and their corresponding two opening areas 110 .
  • the array substrate may include pads 210 and longitudinally disposed first leads 220, and further include the first opening area 111 and the second opening area 112; may also include the pads 210 and the first test conductive portion 241, and also include the first opening area 111 and the second opening area 112.
  • An open area 111 and a fourth open area 114 may also include the pad 210, the first lead 220, the second lead 230 and the first test conductive portion 241, and also include the first open area 111, the second open area 112, The third opening area 113 and the fourth opening area 114, etc., will not be listed one by one here.
  • the multiple opening areas can be communicated with each other, so as to further form larger openings, thereby reducing the difficulty of hollowing out, that is, when the first opening area 111 and the second opening area are At least two of the 112 , the third open area 113 and the fourth open area 114 communicate with each other.
  • the corresponding pads 210 , the first leads 220 , the second leads 230 or the first test conductive parts 241 in the larger opening may be connected to each other or not.
  • each of the fourth opening regions 114 of the first test conductive portion 241 may communicate with each of the first opening regions 111 corresponding to adjacent sub-pads to form a large opening region.
  • the first opening area 111 corresponding to the bottom of the pad of the first LED light-emitting device on the lower left, the second opening area 112 corresponding to the bottom of the first lead 220 on the left, The first opening area 111 corresponding to the bottom of the pad 210 of the second LED light-emitting device on the upper left, and the third opening area 113 corresponding to the bottom of the second lead 230 in the horizontal direction are connected in turn; the pad 210 of the third LED light-emitting device on the upper right
  • the first opening area 111 corresponding to the bottom, the second opening area 112 corresponding to the bottom of the first lead 220 on the right, and the first opening area 111 corresponding to the pad 210 of the fourth LED light emitting device at the bottom right are connected in sequence.
  • the first opening area 111 corresponding to the pad of the IC driving chip and the first opening area 111 corresponding to the pad 210 of the LED light emitting device are also connected to each other.
  • a certain gap d should be ensured between the projected edge of the second conductive portion 20 on the base substrate 900 and the projected edge corresponding to the sub-opening area, so as to ensure that the second conductive portion 20 does not interact with each other.
  • the lower first conductive portion 10 is in contact.
  • the gap is greater than or equal to a preset value, and the preset value includes the sum of the process tolerance, the maximum size of impurities and the reserved spacing.
  • the process tolerance refers to the allowable dimensional deviation in the process related to the process. Since the gap d is formed between the first conductive portion 10 and the second conductive portion 120, the tolerances of these two layers will affect the gap.
  • the maximum size of the impurity refers to the maximum diameter of the impurity particles (partical) encountered in the process. If the impurity particles fall into the gap, it may cause the connection between the first conductive part and the second conductive part. Therefore, when designing the gap size, it is necessary to Consider the effect of impurity size.
  • the reserved spacing refers to a spacing value that is artificially set to form a gap.
  • the contact between the two can be avoided due to process tolerances, and the contact between the two can also be avoided due to the presence of impurity particles, ensuring that the A sufficient distance is reserved between the second conductive portion 20 and the lower first conductive portion 10 to prevent short circuit.
  • the preset value may further include dimensional deviations caused by other factors.
  • the minimum gap d between the projected edge of the sub-pad 2110 and the projected edge corresponding to the first opening area 111 is greater than or equal to the default value.
  • the process tolerance is about ⁇ 5um
  • the maximum size of impurities is about ⁇ 10um
  • the reserved spacing is preferably 5um. Therefore, the gap d between the second conductive portion 20 and the projected edge of the opening region 110 is greater than or equal to 20um.
  • the IR Drop of the first conductive part 10 may be too large, so the gap between the second conductive part 20 and the projected edge of the opening area 110 is preferably less than or equal to 100 ⁇ m, which can reduce the IR Drop as much as possible.
  • the first conductive layer 100 further includes a plurality of conductive islands 120 , at least one of the sub-opening regions has a conductive island 120 , and the outer periphery of the conductive island 120 is connected to the first conductive portion 10 . There are gaps between them.
  • the conductive island 120 and the first conductive portion 10 are made of the same material, and it can also be understood that an annular groove is dug into the first conductive portion 10 to form a separate conductive area, that is, the conductive island 120 .
  • the second conductive portion 20 above the opening area with the conductive island 120 is located just above the conductive island 120 , and the projection of the second conductive portion 20 on the base substrate 900 corresponds to the projection of the conductive island 120 or within the projection of the conductive island 120 .
  • the projections are completely coincident. Since the second conductive portion 20 is located above the conductive island 120 and the conductive island 120 is spaced from the first conductive portion 10 , even if the second conductive portion 20 and the conductive island 120 are short-circuited, the first conductive portion 10 will not be affected.
  • a conductive island 120 is correspondingly disposed in the first sub-opening area 1110 under the anode pad, and the first sub-opening area 1110 under the anode pad
  • a conductive island 120 is correspondingly disposed in the sub-opening region 1110 , and there is a gap between the outer periphery of the two conductive islands 120 and the first conductive portion 10 .
  • the two first sub-opening regions 1110 are connected to each other to form an opening, and the two conductive islands 120 are connected to each other to form an integral structure, thereby reducing the difficulty of slotting and facilitating processing.
  • a conductive island 120 is correspondingly provided, and there are gaps between the outer periphery of the four conductive islands 120 and the first conductive portion 10 , and the four first sub-opening regions 1110 communicate with each other to form an opening.
  • four conductive islands 120 are connected to each other into a unitary structure.
  • a conductive island 120 is disposed in the second opening area 112 under the first lead 220 , and there is a gap between the outer circumference of the conductive island 120 and the first conductive portion 10 . .
  • each of the three fourth sub-opening regions 114 under the three first test conductive portions 241 is provided with a conductive island 120 , and the outer periphery of the conductive island 120 is connected to the first conductive portion 10 . There are gaps in between.
  • each sub-opening area of the opening area under the same pad is connected to each other, and the conductive islands 120 in each sub-opening area are independent of each other.
  • each sub-opening area of the opening area under the same pad is connected to each other, and the conductive islands 120 in each sub-opening area are connected to each other, so as to reduce the difficulty of fabrication.
  • at least two of the first opening area 111 , the second opening area 112 , the third opening area 113 , and the fourth opening area 114 may be connected to each other, and each conductive island in the connected opening area 120 can also be independent of each other or connected as a whole.
  • first lead 220 and the two conductive islands 120 under the pad 210 can also be connected to each other to form an integral structure, and the two conductive islands 120 below the first lead 220 and the second lead 230 can also be connected to each other to form an integral structure, or
  • the pads 210 and the conductive islands 120 under the first test conductive portion 241 may also be connected to each other, that is, the conductive islands in any interconnected opening area may be connected as a whole.
  • a certain gap d should also be ensured between the outer periphery of the conductive island 120 and the edge of the sub-opening area of the first conductive portion 10 to ensure that the second conductive portion 20 above the conductive island 120 does not form an electrical connection with the first conductive portion 10 below. touch.
  • the gap h is also preferably greater than or equal to a preset value including the sum of the process tolerance, the maximum size of impurities and the reserved spacing. The difference is that, since the gap h is formed between the first conductive portion 10 and the conductive island 120 in the first conductive layer, when calculating the preset value, the process tolerance in it refers to the process tolerance when the first conductive portion is fabricated. Process tolerances caused by related processes.
  • the gap h between the outer circumference of the conductive island 120 and the edge of the sub-opening region of the first conductive portion 10 is preferably greater than or equal to 20 ⁇ m, so that the conductive island 120 and the first conductive portion 10 can be prevented from contacting due to factors such as process variation. . Further, the gap h between the outer periphery of the conductive island 120 and the edge of the sub-opening region of the first conductive portion 10 is preferably less than or equal to 100 ⁇ m, which can reduce the IR Drop of the first conductive portion 10 as much as possible.
  • the first conductive portion may be formed by two processes of magnetron sputtering or electroplating. Since electroplating is usually used to form a thick film layer, if a hollowed-out structure is formed in the opening area, a large difference in film thickness often occurs at the edge of the opening area. For the consideration of the uniformity or flatness of the film layer, it is actually not desirable to have a large thickness difference. Therefore, when the electroplating process is used, it is preferably used to prepare an array substrate containing a conductive island structure. Thicker and smoother. However, the thickness of the film usually formed by the magnetron sputtering process is thinner than that of the electroplating process, which is more suitable for forming the structure with the opening area hollowed out.
  • FIG. 21 is a schematic cross-sectional view at A-A in FIG. 20, the second conductive layer further includes a second test conductive part 242, the second test conductive part 242 and the first conductive part 10 on the base substrate The projections overlap and are electrically connected through vias.
  • the second test conductive portion 242 is used to test the electrical performance of the first conductive portion 10 .
  • a second test conductive portion 242 can be provided in the second conductive layer, and the second test conductive portion 242 can be electrically connected to the common voltage line GND through a via hole, that is, we can obtain Performance data for common voltage line GND.
  • the film layer above the to-be-tested area of the first conductive portion 10 is opened, so that the first conductive portion 10 is directly tested. Then, during the preparation process, the area to be tested of the first conductive part 10 needs to be exposed to the air to wait for other film layers to be prepared above. Due to the limitation of material properties, the first conductive part 10 is easily corroded due to the limitation of material properties, and the exposure time is too long, which affects signal transmission. .
  • the second test conductive portion 242 covers the first conductive portion 10 to protect the first conductive portion 10 from being corroded.
  • the second test conductive portion 242 belongs to the second conductive layer, and the copper-nickel alloy in the material has strong corrosion resistance, and is not easily corroded even when exposed to the outside, which can ensure a good test effect.
  • FIG. 22 it is another partial enlarged view of the M area in FIG. 1 , that is, another A schematic diagram of the layout of an array substrate.
  • Each pad and lead can also overlap with other signal lines, for example, with the driving voltage line VLED, that is, the first conductive portion 10 can also be the driving voltage line VLED, then the corresponding opening area 110 is arranged on the driving voltage line. inside the VLED.
  • the specific structure is similar to that of the foregoing embodiment, and is not repeated here.
  • the array substrate of the present disclosure can be used as a substrate with a light-emitting function by binding a light-emitting device, and can be further applied to a display device as a backlight unit.
  • Embodiments of the present invention further provide a display device including the array substrate in the above-mentioned embodiments. Since the display device includes the above-mentioned array substrate, it has the same beneficial effects, and details are not described herein again in the present invention.
  • the present invention does not specifically limit the application of display devices, which can be TVs, notebook computers, tablet computers, wearable display devices, mobile phones, vehicle-mounted displays, navigation, e-books, digital photo frames, advertising light boxes, etc. products or parts.
  • display devices which can be TVs, notebook computers, tablet computers, wearable display devices, mobile phones, vehicle-mounted displays, navigation, e-books, digital photo frames, advertising light boxes, etc. products or parts.

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Abstract

一种阵列基板和显示装置。阵列基板包括衬底基板（900）、第一导电层（100）和第二导电层（200），第一导电层（100）设于衬底基板（900）的一侧，包括第一导电部（10）；第二导电层（200）设于第一导电层（100）背离衬底基板（900）的一侧，包括第二导电部（20），至少部分第二导电部（20）和第一导电部（10）在衬底基板（900）上的投影不重叠。将第二导电部（20）和第一导电部（10）交叠区域下方的第一导电部（10）挖空，由此可以避免交叠区域因静电、制程工艺、测试等原因发生短路，提高产品性能稳定性。

Description

阵列基板和显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种阵列基板和显示装置。
背景技术
Mini-LED是在小间距LED基础上衍生出来的一种新型LED显示技术，也被称为亚毫米发光二极管。它的晶粒尺寸大约在100到200um之间，即介于传统LED和Micro LED之间。由于其具有较好的显示效果以及轻薄体验，同时具有较高的对比度、寿命长等优势，因此在高端显示领域使用趋势明显。
发明内容
本公开的目的在于提供一种阵列基板和显示装置。
根据本公开的第一个方面，提供一种阵列基板，其中，包括：
衬底基板；
第一导电层，设于所述衬底基板的一侧，包括第一导电部；
第二导电层，设于所述第一导电层背离所述衬底基板的一侧，包括第二导电部；
其中，至少部分所述第二导电部和所述第一导电部在所述衬底基板上的投影不重叠。
在本公开的一种示例性实施方式中，所述第一导电部具有开口区，至少部分所述第二导电部在所述衬底基板上的投影位于所述开口区投影投影围成的区域内。
在本公开的一种示例性实施方式中，所述第二导电部中与开口区对应的部分的投影边缘与所述开口区的投影边缘具有间隙。
在本公开的一种示例性实施方式中，所述第二导电部包括焊盘、第一引线、第二引线、功能单元中的至少任意一者；
所述开口区包括第一开口区、第二开口区、第三开口区和第四开口区中的至少任意一者。
在本公开的一种示例性实施方式中，所述开口区包括第一开口区，所述第一开口区包括多个第一子开口区；
所述第二导电部包括多组焊盘，每组所述焊盘包括多个子焊盘；
至少部分所述子焊盘在所述衬底基板上的投影分别一一对应的位于各所述第一子开口区的投影围成的区域内，且各所述子焊盘的投影外周均与对应的所述第一子开口区的投影边缘具有间隙。
在本公开的一种示例性实施方式中，同一组所述焊盘的各子焊盘对应的 各所述第一子开口区相互连通
在本公开的一种示例性实施方式中，所述第一导电部的至少部分沿第一方向延伸，所述开口区包括第二开口区，所述第二开口区包括至少一个第二子开口区；
所述第二导电部包括沿所述第一方向延伸的第一引线，
至少部分所述第一引线在所述衬底基板上的投影与所述第二开口区的投影重叠，且所述第一引线至少一侧的投影边缘与所述第二开口区的投影边缘具有间隙。
在本公开的一种示例性实施方式中，所述第二子开口区的数量为多个，至少两个所述第二子开口区相互连通。
在本公开的一种示例性实施方式中，所述第一导电部的至少部分沿第一方向延伸，所述开口区包括第三开口区，所述第三开口区包括至少一个第三子开口区；
所述第二导电部包括沿第二方向延伸第二引线，所述第二方向与所述第一方向相交；
至少部分所述第二引线在所述衬底基板上的投影与所述第三子开口区的投影围成的区域重叠，且所述第二引线的相对两侧的边缘与所述第三子开口区的投影边缘具有间隙。
在本公开的一种示例性实施方式中，所述第三子开口区的数量为多个，至少两个所述第三子开口区相互连通。
在本公开的一种示例性实施方式中，所述开口区包括第四开口区，所述第四开口区包括至少一个第四子开口区；
所述第二导电部包括若干功能单元；
各所述功能单元在所述衬底基板上的投影一一对应的位于各所述第四子开口区的投围成的区域影内，且所述功能单元的投影外周均与对应的所述第四子开口区的投影边缘具有间隙。
在本公开的一种示例性实施方式中，所述第四子开口区的数量为多个，至少两个所述第四子开口区相互连通。
在本公开的一种示例性实施方式中，所述功能单元包括与所述焊盘、第一引线或第二引线电连接的第一测试导电部，所述第一测试导电部用于检测所述焊盘、第一引线或第二引线的电学性能。
在本公开的一种示例性实施方式中，所述第一开口区、第二开口区、第三开口区、第四开口区中的至少两种相互连通。
在本公开的一种示例性实施方式中，所述第二导电部的投影边缘与对应的所述子开口区的投影边缘之间的间隙大于或等于一预设值，所述预设值包括制程公差、杂质最大尺寸和预留间距之和；
其中，所述制程公差指第一导电部和/或第二导电部制备工艺中允许的尺寸偏差量，所述杂质最大尺寸是指制程中杂质颗粒的最大直径，所述预留间距是形成所述间隙而人为设定的间距数值。
在本公开的一种示例性实施方式中，所述预设值为20μm。
在本公开的一种示例性实施方式中，所述第一导电层还包括多个导电岛，至少一个所述子开口区内具有所述导电岛，且所述导电岛外周与对应的所述子开口区的边缘具有间隙；
所述子焊盘、第一引线、第二引线或第一测试导电部中至少一种在所述衬底基板上的投影位于对应的所述导电岛的投影内或与各所述导电岛的投影完全重合。
在本公开的一种示例性实施方式中，所述导电岛外周与对应的所述子开口区的边缘的间隙大于或等于一预设值，所述预设值包括制程公差、杂质最大尺寸和预留间距之和。
在本公开的一种示例性实施方式中，所述预设值为20μm。
在本公开的一种示例性实施方式中，所述导电岛的材料与所述第一导电部的材料相同。
在本公开的一种示例性实施方式中，同一所述开口区的至少两个所述子开口区相互连通，，相互连通的所述子开口区内的各所述导电岛相互独立或连接为一体。
在本公开的一种示例性实施方式中，所述第一开口区、第二开口区、第三开口区、第四开口区中的至少两种相互连通，相互连通的所述开口区内的各所述导电岛相互独立或连接为一体。
在本公开的一种示例性实施方式中，所述第二导电层还包括第二测试导电部，所述第二测试导电部与第一导电部在所述衬底基板上的投影重叠，且通过过孔电连接，所述第二测试导电部用于检测所述第一导电部电学性能
根据本公开另一个方面，提供一种显示装置，包括以上所述的阵列基板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种mini LED的阵列基板的结构示意图；
图2为图1中M区的局部放大图；
图3为一种实施方式中LED发光器件的一种焊盘结构示意图；
图4为图3中A-A向的截面示意图；
图5为LED发光器件的另一种焊盘结构示意图；
图6为图5中A-A向的截面示意图；
图7为IC驱动芯片焊盘的一种焊盘结构示意图；
图8为IC驱动芯片焊盘的另一种焊盘结构示意图；
图9为第一引线的一种结构示意图；
图10为第二引线的一种结构示意图；
图11为第一测试导电部的一种结构示意图；
图12为各开口区相连通的一种结构示意图；
图13为LED发光器件包含导电岛的一种焊盘结构示意图；
图14为图9中A-A向的截面示意图；
图15为LED发光器件包含导电岛的另一种焊盘结构示意图；
图16为图11中A-A向的截面示意图；
图17为IC驱动芯片焊盘包含导电岛的一种焊盘结构示意图；
图18为IC驱动芯片焊盘包含导电岛的另一种焊盘结构示意图；
图19为第一引线和第二引线包含导电岛的一种结构示意图；
图20为第一测试导电部包含导电岛、第二测试导电部的结构示意图；
图21为图20中A-A向的截面示意图；
图22为图1中M区的另一种局部放大图。
图中：100、第一导电层；10、第一导电部；110、开口区；111、第一开口区；1110、第一子开口区；112、第二开口区；1120、第二子开口区；113、第三开口区；1130、第三子开口区；114、第四开口区；1140、第四子开口区；120、导电岛；200、第二导电层；20、第二导电部；210、焊盘；2110、子焊盘；220、第一引线；230、第二引线；241、第一测试导电部；242、第二测试导电部；300、第一绝缘层；400、第一无机层；500、第二绝缘层；600、第二无机层；900、衬底基板。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多 实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料等。在其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本公开的主要技术创意。
当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
如图1所示，为一种mini LED的阵列基板的结构示意图。图2为图1中M区的局部放大图，示出了一个发光单元的结构。该发光单元包括4个串联的发光器件，以与驱动电压线VLED电连接的发光器件作为这4个发光器件串联的起点，与驱动IC电连接的发光器件作为这4个发光器件串联的终点。4个发光器件由一个驱动IC进行驱动。
需要说明的是，本公开的实施例中，每个发光单元中的发光器件的数量不受限制，可以为5个、6个、7个、8个等任意数量，而不限于4个。同时，发光器件可以是Mini LED、OLED或其他任意形式的发光器件。
本公开实施方式中，Mini-LED阵列基板包括衬底基板900、第一导电层100和第二导电层200。第一导电层100设于衬底基板900的一侧，包括第一导电部10。第二导电层200设于第一导电层100背离衬底基板900的一侧，包括第二导电部20。第一导电层100和第二导电层200之间设有第一绝缘层300和第一无机层400，第二导电层200上方设有第二绝缘层500和第二无机层600。
第一导电层100通常用于布置各种信号线，即第一导电部10可以为各种信号线，例如公共电压线GND、驱动电压线VLED、源电源线PWR、源地址线DI等。可选的，该膜层厚度约为1.5～7μm，其材料包括铜，例如可以通过溅射的方式形成例如MoNb/Cu/MoNb的叠层材料，底层
Figure PCTCN2021074256-appb-000001
用于提高粘附力，中间层Cu用于传递电信号，顶层
Figure PCTCN2021074256-appb-000002
用于防氧化。该膜层还可以通过电镀的方式形成，先形成种子层MoNiTi提高晶粒成核密度，电镀后再制作防氧化层MoNiTi。
第二导电层200通常用于设置各种焊盘，即第二导电部20可以为各种焊盘，例如用于安装功能元件的焊盘或用于安装功能元件驱动芯片的焊盘；第二导电层200还可以设置起连接作用的引线，即第二导电部20也可以为引线。可选的，该膜层厚度约为6000，其材料可以为例如MoNb/Cu/CuNi的叠层材料，底层MoNb用于提高粘附力，中间层Cu用于传递电信号，顶层CuNi可兼顾防氧化和固晶牢固性。
第一导电层100和第二导电层200之间设置有绝缘层。
由于基板尺寸、工艺等限制，在制作位于上层的第二导电部20时，往往不可避免的会与下方的第一导电部10形成交叠，二者的交叠区为性能薄弱区域，容易发生短路或断路，导致发生不良或影响信赖性。
例如，若上层的焊盘与下层的信号线交叠，则在后续焊接功能元件时，例如采用SMT回流焊技术焊接LED芯片时，由于焊接区间温度达到260～265℃，此温度易超出中间绝缘层的耐温值，导致焊盘处OC破损，进而导致焊盘与信号线短路。此外，在LED芯片固晶时，LED的锐角颗粒也可能会刺伤焊盘和绝缘层，导致焊盘与信号线短路。
再例如，若上层的引线与下层的信号线交叠，交叠处边缘产生的空气式静电容易将绝缘层击穿，导致引线与信号线短路。另外，制程中产生的颗粒无法完全消除，当颗粒掉落在引线与信号线的交叠区时，容易导致引线与信号线不稳定性的导通，影响产品的信赖性。再者，在采用扎针测试法对上层引线进行电流或电压测试时，容易扎破绝缘层扎到下方的信号线，导致测试不准或精度降低。
第一导电部10和第二导电部20发生短路的一种原因在于，第一导电部10通常设置的较厚较宽，以提供较大的电压/电流和较低的电阻，第二导电部20通常设置的较窄较短，作为引线、焊盘等结构存在。因此二者之间存在一定的电势差。由于玻璃基薄膜制程中，两个导电部之间的绝缘层在固化前为半固半液状态，该过程中引入的水汽可能会留在绝缘层内。而导电部中Cu生长的本质为电化学腐蚀，水在电势差的存在下容易引发电化学反应，在绝缘层中形成OH -，OH -则会引发第一导电部10和第二导电部20短路。
可见，为了确保产品质量和性能，应当尽量避免第一导电部10和第二导电部20之间短路。
本公开的阵列基板中的至少部分第二导电部20和第一导电部10在衬底基板上的投影不重叠，也就是说，在阵列基板厚度方向上，至少部分第二导电部20和第一导电部10不交叠，那么，不交叠的地方就可以避免二者之间因静电、制程工艺、测试等原因发生短路，从而提高产品性能稳定性。当然，在完全理想的情况下，使所有第二导电部20和第一导电部10在衬底基板上的投影都不重叠，则可以完全避免短路。
在本公开中，描述两个结构之间“交叠”时，指的是其中一个结构在衬底基板上的正投影，与另一个结构在衬底基板上的正投影至少部分重叠。下面对本公开实施方式的阵列基板进行详细说明：
由于第一导电部10需要提供较大的电压/电流和较低的IR drop，通常设置的较宽，第二导电部20通常作为引线、焊盘等较小的结构，通常设置的较窄。例如，对于小尺寸产品，第一导电部10和第二导电部20的线宽比值约为20到30，对于大尺寸产品，第一导电部10和第二导电部20的线宽比值可高达100倍甚至更多，因此第二导电部与第一导电部10必然存在交叠。
参考图2，在一种实施方式中，本公开在第一导电部10内设置开口区110，其中，既包括位于第一导电部10中部的镂空区，该镂空区具有一环形的完整边缘，也包括位于第一导电部10边缘的镂空区，该镂空区具有部分边缘，具体结合附图见下文详细说明。由于开口区110为一镂空的区域，本公开认为其在衬底基板上的投影为其周边膜层边缘的投影，即一环形边缘，本公开以该环形的投影边缘围成的区域作为参照，使至少部分第二导电部20(即交叠处的第二导电部20)在衬底基板900上的投影位于开口区110的投影围成的区域内。需要说明的是，本公开所指的交叠处的第二导电部20的投影位于开口区110的投影围成的区域内，包括两种情况，一种是第二导电部20的至少部分投影边缘位于开口区的投影边缘内侧，且第二导电部20的投影面积比开口区投影围成的区域面积小。另一种是第二导电部20的投影与开口区110的投影围成的区域完全重合，是指两个投影的形状相同且完全重合。无论哪种情况，都是指将交叠区域下方的第一导电部10挖空，由此可以避免第一导电部10与第二导电部20在交叠区域因静电、制程工艺、测试等原因发生短路，从而避免影响产品性能稳定性。
进一步地，第二导电部20中与开口区110对应的部分的投影边缘与开口区110的投影边缘可以设置一定间隙，使得第二导电部20与第一导电部10的边缘保留一定距离，进一步降低了二者之间发生短路的可能性。
在一种实施例中，第二导电部20包括多组焊盘210。本实施方式中，焊盘210可以是用于安装功能器件的焊盘，例如发光器件、传感器等，也可以是用于安装功能器件驱动芯片的焊盘。
参考图3，为图2中N区的局部放大示意图。以用于安装发光器件的焊盘为例，该焊盘210包括两个子焊盘2110，一个为阳极焊盘(图中P所示)，另一个为阴极焊盘(图中N所示)。参考图4，为图3中A-A向的截面示意图。
本实施例中，第一导电部10为公共电压线GND，发光器件的焊盘在阵列基板厚度方向上与公共电压线GND发生交叠。本实施例中，第一导电部10的开口区110包括第一开口区111，第一开口区111包括两个第一子开口区1110；在基板厚度方向上，阳极焊盘的投影在衬底基板900上的投影位于一个第一子开口区1110的投影围成的区域内，且阳极焊盘的投影外周边缘与该第一子开口区1110的投影边缘具有间隙。同样的，阴极焊盘的投影在衬底基板900上的投影位于另一个第一子开口区1110的投影围成的区域内，且阴极焊盘的投影外周边缘与该第一子开口区1110的投影边缘具有间隙。本实施例中，两个第一子开口区1110之间被未挖空的第一导电部10分隔，以使每个第一子开口区1110对应各自的子焊盘2110。
将第一导电部10正对阳极焊盘和阴极焊盘的区域进行了挖空，使得阳极焊盘、阴极焊盘与下方的第一导电部10不再形成交叠，从而避免了焊盘与第一导电部10因焊接、固晶等原因发生短路的问题。
进一步地，同一组焊盘的各子焊盘对应的各第一子开口区1110相互连 通。参考图5和图6，图6为图5中A-A向的截面示意图。在本实施例中，两个第一子开口区1110相互连通，形成一个开口，也就是说，阳极焊盘和阴极焊盘的投影位于同一个大的开口区的投影围成的区域110内。该结构既可以避免阳极焊盘、阴极焊盘与第一导电部10短路，又降低了对第一导电部10进行挖空处理的工艺难度。
本实施例中，子焊盘2110和第一子开口区1110的形状一致，大致均为矩形。
参考图7，以用于安装IC驱动芯片的焊盘为例，该焊盘包括四个子焊盘2110，分别为第一输入焊盘Di、第二输入焊盘Pwr、输出焊盘Out以及公共电压焊盘Gnd。上述第一输入焊盘Di被配置为接收第一输入信号，该第一输入信号例如为地址信号，以用于选通相应地址的IC驱动芯片。例如，第一输入信号可以为来自于源地址线DI的8bit的地址信号，通过解析该地址信号可以获知待传输的地址。第二输入焊盘Pwr被配置为接收第二输入信号，第二输入信号例如为来自于源电源线PWR的电力线载波通信信号。第二输入信号不仅为IC驱动芯片提供电能，还向IC驱动芯片传输通信数据，该通信数据可用于控制相应的发光单元的发光时长，进而控制其视觉上的发光亮度。输出焊盘Out被配置为输出驱动信号。例如，驱动信号可以为来自于驱动电压线VLED的驱动电压，用于驱动发光元件发光。公共电压焊盘Gnd被配置为接收公共电压信号，例如来自于公共电压线GND的接地信号。
本实施例中，第一导电部10为公共电压线GND，IC驱动芯片的焊盘在阵列基板厚度方向上与公共电压线GND发生交叠。第一导电部10的第一开口区111包括四个第一子开口区1110；在基板厚度方向上，第一输入焊盘Di在衬底基板900上的投影位于第一个第一子开口区1110的投影围成的区域内，且第一输入焊盘Di的投影外周边缘与该第一子开口区1110的投影边缘具有间隙。第二输入焊盘Pwr在衬底基板900上的投影位于第二个第一子开口区1110的投影围成的区域内，且第二输入焊盘Pwr的投影外周边缘与该第一子开口区1110的投影边缘具有间隙。输出焊盘Out在衬底基板900上的投影位于第三个第一子开口区1110的投影围成的区域内，且输出焊盘Out的投影外周边缘与该第一子开口区1110的投影边缘具有间隙。公共电压焊盘Gnd在衬底基板900上的投影位于第四个第一子开口区1110的投影围成的区域内，公共电压焊盘Gnd的投影外周边缘与该第一子开口区1110的投影边缘具有间隙。本实施例中，四个第一子开口区1110之间被未挖空的第一导电部10分隔，以使每个第一子开口区1110对应各自的子焊盘2110。
将第一导电部10正对四个子焊盘2110的区域进行了挖空，使得四个子焊盘2110与下方的第一导电部10不再形成交叠，从而避免了焊盘与第一导电部10短路的问题。
进一步地，同一组焊盘的各子焊盘对应的各第一子开口区1110相互连 通，从而降低挖空难度。参考图8，在本实施例中，四个第一子开口区1110相互连通，形成一个开口，也就是说，第一输入焊盘Di、第二输入焊盘Pwr、输出焊盘Out以及公共电压焊盘Gnd的投影位于同一个大的开口区110的投影围成的区域内。该结构既可以避免各子焊盘2110与下方第一导电部10短路，又降低了对第一导电部10挖空处理的精度要求。
本实施例中，子焊盘2110的形状大致为五边形，第一子开口区1110的形状大致为矩形。
需要说明的是，本公开不限定第一子开口区1110的具体形状，其可以与子焊盘2110形状一致，也可以不一致。其中，“大致为五边形”、“大致为矩形”是指，子焊盘2110的外轮廓以及第一子开口区1110边界的形状整体上呈五边形形状或矩形形状，但是并不局限为标准的五边形或矩形。
在其他实施例中，焊盘还可以具有其他数量的子焊盘，例如具有1个、3个等数量的子焊盘。相应的，第一开口区111包括相应数量的第一子开口区1110，以使每个子焊盘下方都对应一个第一子开口区1110，避免在子焊盘处形成交叠。此处不再一一赘述。
本公开不限定焊盘的数量，以图1中所示结构为例，该阵列基板上包含多个发光器件焊盘和多个IC驱动芯片焊盘。在一种实施例中，用于绑定同一功能器件的所有焊盘所对应的各第一子开口区1110相互连通，例如，所有绑定发光器件的焊盘对应的各第一子开口区1110相互连通，所有绑定IC驱动芯片的焊盘对应的各第一子开口区1110相互连通。
在一种实施例中，参考图9，第二导电部20包括第一引线220，第一引线220沿图中纵向(第一方向)延伸。以图中所示为例，第一引线220为由LED发光器件延伸出的纵向引线。在其他实施例中，第一引线220还可以为由IC驱动芯片焊盘延伸出的纵向引线。
继续参考图9，本实施例中，第一导电部10也为公共电压线GND，纵向延伸的第一引线在阵列基板厚度方向上与公共电压线GND纵向延伸的部分发生交叠。
第一导电部10的开口包括第二开口区112，第二开口区112位于第一导电部10纵向延伸的部分。第二开口区112包括至少一个第二子开口区，第一引线220中的至少一段在衬底基板900上的投影位于第二子开口区112的投影围成的区域内，也就是说，将第一引线220中的至少一段下方对应的第一导电部10进行挖空处理，使得第一引线220与下方的第一导电部10在该区域不再形成交叠，从而避免了第一引线220与第一导电部10之间因静电、测试、制程的原因短路。
第一引线220下方可以全部挖空，如图9中所示，也可以只有一段挖空。也就是说，第二开口区112可以设置在全部第一引线220的下方，也可以仅设置在第一引线220的部分区域的下方。图9中第一引线220下方对应的第二开口区112仅包含一个第二子开口区1120，在其他实施方式中，也可以 包含多个第二子开口区。当第二子开口区1120的数量为多个，至少两个第二子开口区1120也可以相互连通，从而降低挖空难度。
本公开中，第一引线220至少一侧的投影边缘与该第二开口区112的投影边缘具有间隙。具体而言，在一种实施例中，参考图2，右侧的第二开口区112为设置在第一导电部10内部的封闭区域，具有四个边界，右侧第一引线220左右两侧的投影边缘与第二开口区112的左右两侧投影边缘都具有间隙。左侧的第二开口区112为设置在第一导电部10内部边缘的半封闭区域，即该第二开口区112具有三个边界，左侧与第一导电部10外部的空白区连通，左侧的第一引线220右侧的投影边缘与第二开口区112的右侧投影边缘具有间隙。
在一种实施例中，参考图10，第二导电部20还包括第二引线230，第二引线230沿横向方向延伸。第二引线230可以为由IC驱动芯片焊盘延伸出的横向引线，也可以为由LED发光器件延伸出的横向引线。
本实施例中，第一导电部10也为公共电压线GND，横向延伸的第二引线230在阵列基板厚度方向上与公共电压线GND纵向延伸的部分发生交叠。
第一导电部10的开口包括第三开口区113，第三开口区113位于第一导电部10纵向延伸的部分；第三开口区113包括至少一个第三子开口区，第二引线230中至少一段在衬底基板900上的投影位于第三子开口区113的投影围成的区域内。也就是说，将第二引线230中的至少一段下方对应的第一导电部10进行挖空处理，使得第二引线230与下方的第一导电部10在该区域不再形成交叠，从而避免了第二引线230与第一导电部10之间因静电、测试、制程的原因短路。
第二引线230下方可以全部挖空，也可以只有一段挖空。也就是说，第三开口区113可以设置在全部第二引线230的下方，也可以仅设置在第二引线230的部分区域的下方。图9中第二引线230下方对应的第三开口区113仅包含一个第三子开口区1130，在其他实施方式中，也可以包含多个第三子开口区1130。当第三子开口区1130的数量为多个，至少两个第第三子开口区也可以相互连通，从而降低挖空难度。
在本实施例中，将该第二引线230下方的第一导电部10进行挖空，由此可以避免第二引线230与第一导电部10之间因静电、制程的原因短路。
本公开中，在纵向方向上，第二引线230对应的第三开口区113可以位于第一导电部10的上边缘或下边缘，也可以位于第一导电部10的中间。因此，第二引线230上下两侧中至少一侧的投影边缘与第三开口区113的投影边缘具有间隙。图10中所示的第三开口区113为一封闭的开口区，第二引线230中的一段的投影与第三开口区113的投影重叠，且上下两侧中至少一侧的投影边缘与第三开口区113的投影边缘具有间隙。
需要注意的是，由于第二引线230沿横向方向延伸，第三开口区113也沿横向延伸，对于一个第一导电部10内的第三开口区113而言，第三开 口区113横向长度应当小于第一导电部10的宽度，否则会截断第一导电部10。因此，当第二引线230在横向上穿过整个第一导电部10时，应当只对第二引线230中的一部分下方进行挖空。可以理解的是，第三开口区113在横向上的长度越长，对纵向延伸的第一导电部10的IR Drop影响越大，导致信号强度降低。但第三开口区113在横向上的长度越长，第二引线230与第一导电部10交叠区越少，越不容易产生静电。实际产品中，需综合考虑两方面原因设置第三开口区113的横向长度。此外，第二引线230也可以同时横跨多个纵向延伸的第一导电部10，那么，每个第一导电部10内都可以设置一个或多个第三子开口区1130。一条第二引线230不横跨第一导电部10时，即第二引线230的投影仅位于一个第一导电部10的投影内时，其对应的第三开口区113可以包括多个第三子开口区1130，分别对应第二引线230上的多个部分。
在其他实施例中，第二引线230延伸的第二方向也可以不垂直于第一方向。无论方向如何，都应保证第二引线230对应的第三开口区113不会截断第一导电部10，且尽量降低对IR Drop的影响。
本实施例中，由于第一引线220或第二引线230的形状一般大致为条形，因此第二开口区112和第三开口区113的形状大致也为条形。本公开不限定第二开口区112和第三开口区113的具体形状，其可以与引线形状一致，也可以不一致。
在一种实施例中，第二导电部20还包括若干功能单元，用于实现特定功能。例如，本实施例中，功能单元可以为第一测试导电部241，第一测试导电部241与焊盘、第一引线或第二引线电连接，用于检测焊盘或第一引线、第二引线的电学性能。例如可采用扎针测试方法测试焊盘的电流或电压特性，具体而言，图11中示出了IC驱动芯片焊盘中的三种子焊盘对应的第一测试导电部241及第四开口区114，三个第一测试导电部241分别对应设置在第一输入焊盘Di、第二输入焊盘Pwr、输出焊盘Out附近，一端与子焊盘连接，用于测试子焊盘的电压和/或电流，其另一端还可以与第一引线或第二引线连接。第一测试导电部241上方膜层(例如第二绝缘层500、第二无机层600)开口，使第一测试导电部241裸露在外，以便在此处进行扎针测试。
开口区110包括第四开口区114，该第四开口区114包括三个第四子开口区1140，三个第一测试导电部241在衬底基板上的投影一一对应的位于各第四子开口区1140的投影内，第一测试导电部241的投影与对应的第四子开口区1140的投影边缘具有间隙。也就是说，将第一测试导电部241下方对应的第一导电部10进行挖空处理，使得第一测试导电部241与下方的第一导电部10在该区域不再形成交叠，从而避免了在进行扎针测试时，针头扎破第一测试导电部241而与第一导电部10接触造成短路或测试不准。由于公共电压焊盘Gnd与公共电压线GND通过过孔相连，因此公共电压焊盘Gnd的电流或电压可以直接在公共电压线GND上测试。本实施例中第一 测试导电部241的数量仅为示例，具体数量可根据需要进行设置，例如，也可以仅针对某一子焊盘设置一个第一测试导电部241，本申请不对第一测试导电部241的数量进行特殊限定。本实施例中，三个第四子开口区1140相互连通，从而降低挖空难度。其他实施例中，各第四子开口区1140也可以相互独立。
以上对各种第二导电部10的类型及其对应第一导电部的开口区110进行了详细说明。本公开的阵列基板可以只包括上述任意一种第二导电部10及其对应的开口区110，也可以包括至少任意两种第二导电部10及其对应的两种开口区110。例如，阵列基板上可以包括焊盘210及纵向设置的第一引线220，还包括第一开口区111和第二开口区112；也可以包括焊盘210及第一测试导电部241，还包括第一开口区111和第四开口区114；也可以同时包括焊盘210、第一引线220、第二引线230及第一测试导电部241，还包括第一开口区111、第二开口区112、第三开口区113和第四开口区114，等，此处不再一一列举。
本公开中，当包含多种开口区时，多种开口区可以相互连通，以便于进一步形成较大的开口，从而降低挖空难度，也就是说时，第一开口区111、第二开口区112、第三开口区113和第四开口区114中的至少两种相互连通。该较大的开口内对应的焊盘210、第一引线220、第二引线230或第一测试导电部241可以相互连接或不连接。
举例而言，参考图11，第一测试导电部241的各第四开口区114可以与相近的子焊盘对应的各第一开口区111相互连通，以形成一个大的开口区。
再举例而言，参考图12，在该阵列基板中，左下方第一个LED发光器件的焊盘下方对应的第一开口区111、左侧第一引线220下方对应的第二开口区112、左上方第二个LED发光器件的焊盘210下方对应的第一开口区111、横向的第二引线230下方对应的第三开口区113依次连通；右上方第三个LED发光器件的焊盘210下方对应的第一开口区111、右侧第一引线220下方对应的第二开口区112、右下方第四个LED发光器件的焊盘210下方对应的第一开口区111依次连通。
同时，如图所示，IC驱动芯片的焊盘对应的第一开口区111与LED发光器件的焊盘210下方对应的第一开口区111也相互连通。
上述实施方式中，参考图7，第二导电部20在衬底基板900上的投影边缘与子开口区对应的投影边缘之间应当保证一定的间隙d，以确保第二导电部20不会与下方的第一导电部10接触。本实施例中，该间隙大于或等于一预设值，该预设值包括制程公差、杂质最大尺寸和预留间距之和。其中，制程公差是指制程相关工艺过程中允许的尺寸偏差量，由于该间隙d是第一导电部10和第二导电部120之间形成的，这两个膜层的公差都会影响到间隙的尺寸，因此包含第一导电部的制程公差和第二导电部的制程公差。杂质最大尺寸是指制程中遇到的杂质颗粒(partical)的最大直径，若杂质颗粒落入该间隙，则有可能会导致第一导电部和第二导电部连接，因此在设计间 隙尺寸时需要考虑杂质尺寸的影响。预留间距是指为了形成间隙而人为设定的一个间距数值。当第二导电部20与子开口区的投影边缘之间的间隙大于或等于上述各数值之和时，可以避免因制程公差导致二者接触，也可以避免因存在杂质颗粒导致二者接触，确保第二导电部20与下方的第一导电部10之间保留足够的距离，防止短路。当然在此基础上，预设值还可以进一步包括其他因素引起的尺寸偏差。在图7所示的结构中，由于第一开口区111边缘与子焊盘2110边缘形状不同，应当保证子焊盘2110投影边缘与第一开口区111对应的投影边缘之间的最小间隙d大于或等于预设值。
根据目前制程工艺，制程公差约为±5um，杂质最大尺寸约为±10um，预留间距优选为5um，因此第二导电部20与开口区110的投影边缘之间间隙d大于或等于20um。进一步地，由于开口区过大有可能会导致第一导电部10的IR Drop过大，因此第二导电部20与开口区110的投影边缘之间的间隙优选小于或等于100μm，可以尽量降低第一导电部10的IR Drop。
在一种实施例中，参照图13-图20，第一导电层100还包括多个导电岛120，至少一个子开口区内具有一个导电岛120，且导电岛120外周与第一导电部10之间均具有间隙。导电岛120和第一导电部10为相同材料，也可以理解为，对第一导电部10挖环形槽，以形成单独的导电区域，即导电岛120。具有导电岛120的开口区上方的第二导电部20正好位于导电岛120上方，且第二导电部20在衬底基板900上的投影对应的位于导电岛120的投影内或与导电岛120的投影完全重合。由于第二导电部20位于导电岛120上方，而导电岛120与第一导电部10具有间隔，因此，即使第二导电部20与导电岛120短路，也不会影响第一导电部10。
在本公开中，描述两个结构之间“完全重合”时，指的是其中一个结构在衬底基板上的正投影，完全位于另一个结构在衬底基板上的正投影内。
举例而言，以用于安装LED发光器件的焊盘为例，参照图13和图14，阳极焊盘下方的第一子开口区1110内对应设置有一导电岛120，阴极焊盘下方的第一子开口区1110内对应也设置有一导电岛120，两个导电岛120外周与第一导电部10之间均具有间隙。在一种实施例中，参照图15和16，两个第一子开口区1110相互连通成一个开口，两个导电岛120相互连接成一体结构，由此可以降低开槽难度，便于加工。
以用于安装IC驱动芯片的焊盘为例，参照图17，第一输入焊盘Di2113、第二输入焊盘Pwr2114、输出焊盘Out2115以及公共电压焊盘Gnd2116下方的第一子开口区1110内分别对应设置有一导电岛120，四个导电岛120外周与第一导电部10之间均具有间隙，且四个第一子开口区1110相互连通成一个开口。在一种实施例中，参照图18，四个导电岛120相互连接成一体结构。
以第一引线220、第二引线230为例，参照图19，第一引线220下方的第二开口区112内设置有一导电岛120，导电岛120外周与第一导电部10之间均具有间隙。
以第一测试导电部241为例，参照图20，三个第一测试导电部241下方的三个第四子开口区114内各设置有一导电岛120，导电岛120外周与第一导电部10之间具有间隙。
在图14、17所示的结构中，同一焊盘下方的开口区的各子开口区相互连通，各子开口区内的导电岛120相互独立。在图15、18所示的结构中，同一焊盘下方的开口区的各子开口区相互连通，各子开口区内的导电岛120相互连接，以降低制备难度。当然，在其他实施例中，第一开口区111、第二开口区112、第三开口区113、第四开口区114中的至少两种可以相互连通，相互连通的开口区内的各导电岛120也可以相互独立或连接为一体。例如，第一引线220和焊盘210下方的两个导电岛120也可以相互连接成一体结构，第一引线220和第二引线230下方的两个导电岛120也可以相互连接成一体结构，或者焊盘210和第一测试导电部241下方的导电岛120也可以相互连接，也就是说，任意相互连通的开口区内的各导电岛都可以连接为一体。
导电岛120外周与第一导电部10的子开口区的边缘之间也应当保证一定的间隙d，以确保导电岛120上方的第二导电部20不会与下方的第一导电部10形成电接触。与间隙d类似，该间隙h也优选大于或等于包括制程公差、杂质最大尺寸和预留间距之和的预设值。不同之处在于，由于该间隙h是同属于第一导电层内第一导电部10和导电岛120之间形成的，在计算预设值时，其中的制程公差是指在制作第一导电部时相关工艺带来的制程公差。同样的，导电岛120外周与第一导电部10的子开口区的边缘之间的间隙h优选大于或等于20μm，由此可避免因工艺偏差等因素使导电岛120与第一导电部10接触。进一步地，导电岛120外周与第一导电部10的子开口区的边缘之间的间隙h还优选小于或等于100μm，可以尽量降低第一导电部10的IR Drop。
本公开的实施方式中，第一导电部可以采用磁控溅射或电镀两种工艺来形成。由于电镀通常用于形成厚度较厚的膜层，若在开口区形成挖空的结构，开口区边缘往往会出现较大的膜层厚度断差。出于对膜层均一性或平整性的考虑，实际上并不希望出现大的厚度断差，因此当采用电镀工艺时，优选用于制备包含导电岛结构的阵列基板，由此形成的膜层厚度较厚且平整性较好。而磁控溅射工艺通常形成的膜层厚度相对电镀工艺来说较薄，更适合用于形成开口区挖空的结构。
参照图20和图21，图21为图20中A-A处的截面示意图，第二导电层还包括第二测试导电部242，第二测试导电部242与第一导电部10在衬底基板上的投影重叠，且通过过孔电连接，第二测试导电部242用于检测第一导电部10的电学性能。例如，当需要对公共电压线GND进行测试时，可以在第二导电层内设置第二测试导电部242，并通过过孔将第二测试导电部242与公共电压线GND电连接，即可以得到公共电压线GND的性能数据。而在现有技术中，是对第一导电部10待测试区域上方的膜层 进行开口，从而直接对第一导电部10进行测试。那么在制备过程中，第一导电部10待测试区域需要暴露在空气中，以等待上方还有其他膜层制备，第一导电部10由于材料性能限制，暴露时间过长容易腐蚀，影响信号传输。第二测试导电部242覆盖在第一导电部10上方，对第一导电部10形成保护，避免其受到腐蚀。而第二测试导电部242属于第二导电层，其材料中的铜镍合金抗腐蚀能力强，即使暴露在外也不易腐蚀，能保证良好的测试效果。
以上实施方式中均以各焊盘、引线与公共电压线GND交叠为例进行了说明，在其他实施方式中，参考图22，为图1中M区的另一种局部放大图，即另一种阵列基板的版图示意图。各焊盘、引线也可以与其他信号线交叠，例如与驱动电压线VLED交叠，即第一导电部10还可以为驱动电压线VLED，那么，对应的开口区110则设置在驱动电压线VLED内。具体结构与前述实施例类似，此处不再赘述。
本公开的阵列基板既可以绑定发光器件作为具有发光功能的基板使用，也可以进一步作为背光单元应用到显示装置中。
本发明实施方式还提供一种显示装置，该显示装置包括上述实施方式中的阵列基板。由于该显示装置包括上述阵列基板，因此具有相同的有益效果，本发明在此不再赘述。
本发明对于显示装置的适用不做具体限制，其可以是电视机、笔记本电脑、平板电脑、可穿戴显示设备、手机、车载显示、导航、电子书、数码相框、广告灯箱等任何具有柔性显示功能的产品或部件。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (24)

  1. 一种阵列基板，其中，包括：
    衬底基板；
    第一导电层，设于所述衬底基板的一侧，包括第一导电部；
    第二导电层，设于所述第一导电层背离所述衬底基板的一侧，包括第二导电部；
    其中，至少部分所述第二导电部和所述第一导电部在所述衬底基板上的投影不重叠。
  2. 根据权利要求1所述的阵列基板，其中，所述第一导电部具有开口区，至少部分所述第二导电部在所述衬底基板上的投影位于所述开口区投影围成的区域内。
  3. 根据权利要求2所述的阵列基板，其中，所述第二导电部中与开口区对应的部分的投影边缘与所述开口区的投影边缘具有间隙。
  4. 根据权利要求3所述的阵列基板，其中，所述第二导电部包括焊盘、第一引线、第二引线、功能单元中的至少任意一者；
    所述开口区包括第一开口区、第二开口区、第三开口区和第四开口区中的至少任意一者。
  5. 根据权利要求4所述的阵列基板，其中，所述开口区包括第一开口区，所述第一开口区包括多个第一子开口区；
    所述第二导电部包括多组焊盘，每组所述焊盘包括多个子焊盘；
    至少部分所述子焊盘在所述衬底基板上的投影分别一一对应的位于各所述第一子开口区的投影围成的区域内，且各所述子焊盘的投影外周均与对应的所述第一子开口区的投影边缘具有间隙。
  6. 根据权利要求5所述的阵列基板，其中，同一组所述焊盘的各子焊盘对应的各所述第一子开口区相互连通。
  7. 根据权利要求4所述的阵列基板，其中，所述第一导电部的至少部分沿第一方向延伸，所述开口区包括第二开口区，所述第二开口区包括至少一个第二子开口区；
    所述第二导电部包括沿所述第一方向延伸的第一引线，
    至少部分所述第一引线在所述衬底基板上的投影与所述第二子开口区的投影围成的区域重叠，且所述第一引线至少一侧的投影边缘与所述第二子开口区的投影边缘具有间隙。
  8. 根据权利要求7所述的阵列基板，其中，所述第二子开口区的数量为多个，至少两个所述第二子开口区相互连通。
  9. 根据权利要求4所述的阵列基板，其中，所述第一导电部的至少部分沿第一方向延伸所述开口区包括第三开口区，所述第三开口区包括至少一个第三子开口区；
    所述第二导电部包括沿第二方向延伸第二引线，所述第二方向与所 述第一方向相交；
    至少部分所述第二引线在所述衬底基板上的投影与所述第三子开口区的投影围成的区域重叠，且所述第二引线的相对两侧的边缘与所述第三子开口区的投影边缘具有间隙。
  10. 根据权利要求9所述的阵列基板，其中，所述第三子开口区的数量为多个，至少两个所述第三子开口区相互连通。
  11. 根据权利要求4所述的阵列基板，其中，所述开口区包括第四开口区，所述第四开口区包括至少一个第四子开口区；
    所述第二导电部包括若干功能单元；
    各所述功能单元在所述衬底基板上的投影一一对应的位于各所述第四子开口区的投影围成的区域内，且所述功能单元的投影外周均与对应的所述第四子开口区的投影边缘具有间隙。
  12. 根据权利要求11所述的阵列基板，其中，所述第四子开口区的数量为多个，至少两个所述第四子开口区相互连通。
  13. 根据权利要求12所述的阵列基板，其中，所述功能单元包括与所述焊盘、第一引线或第二引线电连接的第一测试导电部，所述第一测试导电部用于检测所述焊盘、第一引线或第二引线的电学性能。
  14. 根据权利要求5-13中任意一项所述的阵列基板，其中，所述第一开口区、第二开口区、第三开口区、第四开口区中的至少两种相互连通。
  15. 根据权利要求5-13中任意一项所述的阵列基板，其中，所述第二导电部的投影边缘与对应的所述子开口区的投影边缘之间的间隙大于或等于一预设值，所述预设值包括所述制程公差、杂质最大尺寸和预留间距之和；
    其中，所述制程公差指第一导电部和/或第二导电部制备工艺中允许的尺寸偏差量，所述杂质最大尺寸是指制程中杂质颗粒的最大直径，所述预留间距是形成所述间隙而人为设定的间距数值。
  16. 根据权利要求15所述的阵列基板，其中，所述预设值为20μm。
  17. 根据权利要求5-13中任意一项所述的阵列基板，其中，所述第一导电层还包括多个导电岛，至少一个所述子开口区内具有所述导电岛，且所述导电岛外周与对应的所述子开口区的边缘具有间隙；
    所述子焊盘、第一引线、第二引线或第一测试导电部中至少一种在所述衬底基板上的投影位于对应的所述导电岛的投影内或与各所述导电岛的投影完全重合。
  18. 根据权利要求17所述的阵列基板，其中，所述导电岛外周与对应的所述子开口区的边缘的间隙大于或等于一预设值，所述预设值包括制程公差、杂质最大尺寸和预留间距之和。
  19. 根据权利要求18所述的阵列基板，其中，所述预设值为20μm。
  20. 根据权利要求17所述的阵列基板，其中，所述导电岛的材料与 所述第一导电部的材料相同。
  21. 根据权利要求17所述的阵列基板，其中，同一所述开口区的至少两个所述子开口区相互连通，相互连通的所述子开口区内的各所述导电岛相互独立或连接为一体。
  22. 根据权利要求17所述的阵列基板，其中，所述第一开口区、第二开口区、第三开口区、第四开口区中的至少两种相互连通，相互连通的所述开口区内的各所述导电岛相互独立或连接为一体。
  23. 根据权利要求1所述的阵列基板，其中，所述第二导电层还包括第二测试导电部，所述第二测试导电部与第一导电部在所述衬底基板上的投影重叠，且通过过孔电连接，所述第二测试导电部用于检测所述第一导电部电学性能。
  24. 一种显示装置，其中，包括权利要求1-23中任一项所述的阵列基板。
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