WO2023159393A1 - 发光基板、背光模组及显示装置 - Google Patents

发光基板、背光模组及显示装置 Download PDF

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Publication number
WO2023159393A1
WO2023159393A1 PCT/CN2022/077474 CN2022077474W WO2023159393A1 WO 2023159393 A1 WO2023159393 A1 WO 2023159393A1 CN 2022077474 W CN2022077474 W CN 2022077474W WO 2023159393 A1 WO2023159393 A1 WO 2023159393A1
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WIPO (PCT)
Prior art keywords
light
driver chip
driver
voltage signal
electrically connected
Prior art date
Application number
PCT/CN2022/077474
Other languages
English (en)
French (fr)
Inventor
马亚军
张志�
尹利
方振中
王鹏华
Original Assignee
京东方科技集团股份有限公司
合肥京东方瑞晟科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 京东方科技集团股份有限公司, 合肥京东方瑞晟科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/017,268 priority Critical patent/US20240248357A1/en
Priority to CN202280000249.5A priority patent/CN117242511A/zh
Priority to PCT/CN2022/077474 priority patent/WO2023159393A1/zh
Publication of WO2023159393A1 publication Critical patent/WO2023159393A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present disclosure relates to the field of display technology, in particular to a light emitting substrate, a backlight module and a display device.
  • Mini-LED sub-millimeter light-emitting diode
  • Micro-LED micro Light Emitting Diode
  • a light emitting substrate includes a plurality of driving chipsets, a plurality of grounding wires, and at least one connection wire.
  • At least one driver chip group includes multiple driver chip subsets, and at least one driver chip subset includes cascaded multiple driver chips; multiple driver chip subsets of the same driver chip group are cascaded. Multiple driver chips of the same driver chip subset are electrically connected to the same grounding wire, and the grounding wires connected to different driver chip subsets are different. Multiple ground traces connected to multiple driver chip subgroups of the same driver chip group are electrically connected through at least one connection wire.
  • the light-emitting substrate further includes a plurality of first voltage signal lines. At least one first voltage signal line roughly extends along the first direction, and along the second direction, the first voltage signal line and the grounding line are alternately arranged, and one of the first voltage signal lines is connected to a driver chip subgroup Corresponding; the multiple first voltage signal lines are made of the same material as the multiple grounding traces and are arranged on the same layer.
  • the light-emitting substrate includes a light-emitting area and a fan-out area arranged side by side along the first direction, and the plurality of driving chip groups are located in the light-emitting area.
  • the at least one connection line includes a first connection line located on the side of the first voltage signal line away from the fan-out area, and the end of the first connection line and the ground trace is far away from the fan-out area electrical connection.
  • the first connection line and the grounding line are made of the same material and arranged on the same layer, and the first connection line and the end of the first voltage signal line away from the fan-out area There are gaps in between.
  • the gap between the first connection line and the first voltage signal line is greater than or equal to 200 ⁇ m.
  • the light-emitting substrate further includes a plurality of first voltage signal lines. At least one first voltage signal line roughly extends along the first direction, and along the second direction, the first voltage signal line and the grounding line are alternately arranged, and one of the first voltage signal lines is connected to a driver chip subgroup correspond.
  • the light-emitting substrate includes a substrate, a first wiring layer, a first insulating layer, and a second wiring layer that are sequentially stacked. The multiple ground traces and the multiple first voltage signal lines are located on the first trace layer. A first via hole is provided in the first insulating layer.
  • the at least one connection line includes a second connection line located on the second wiring layer, and the orthographic projection of the second connection line on the first insulating layer is the same as that of the first voltage signal line on the second wiring layer. Partially overlapping orthographic projections on an insulating layer.
  • the second connection wire is electrically connected to the ground trace through the first via hole.
  • the light-emitting substrate includes a light-emitting area and a fan-out area arranged side by side along the first direction, and the plurality of driving chip groups are located in the light-emitting area.
  • the ground trace includes a main body and a connection part, the main body extends along the first direction, and the connection part electrically connects the main body with the driving chip.
  • the second connection line is electrically connected to the connection part through the first via hole, and the line width of the connection part electrically connected to the second connection line is larger than that of a connection not electrically connected to the second connection line The line width of the section.
  • the light-emitting substrate includes a light-emitting area and a fan-out area arranged side by side along a first direction, and the plurality of driving chip groups are located in the light-emitting area.
  • the light-emitting substrate includes a substrate, a first wiring layer arranged on the substrate, and an insulating pattern arranged on the side of the first wiring layer away from the substrate, and a first wiring layer is arranged in the insulating pattern.
  • the ground wiring includes a first lead-out section located in the fan-out area, and the first lead-out section is located in the first wiring layer.
  • the at least one connection line includes a third connection line located in the fan-out area, the third connection line is located on the side of the insulating pattern away from the substrate, and the third connection line passes through the second The via hole is electrically connected to the first lead-out segment.
  • the third connection line is a grid structure.
  • the light-emitting substrate further includes a first insulating layer disposed on the side of the first wiring layer away from the substrate, and a first insulating layer disposed on the side of the first insulating layer away from the substrate.
  • the insulating pattern is located on the first insulating layer, and the third connection line is located on the second wiring layer.
  • the plurality of driving chips of the driving chip subset are roughly arranged along a first direction
  • the multiple driving chip subsets of the driving chip group are roughly arranged along a second direction
  • the plurality of driving chips The groups are generally arranged along the second direction.
  • the first direction and the second direction intersect each other.
  • the ground traces extend approximately along the first direction, and along the second direction, the ground traces and the sub-group of driving chips are alternately arranged, and the plurality of driving chips of the sub-group of driving chips are connected to the Adjacent ones of the ground traces are electrically connected.
  • the last-level driver chip of one driver chip subset is electrically connected to the first-level driver chip of the other driver chip subset.
  • the driver chip includes signal input pins, signal output pins, ground pins, and power pins.
  • the light-emitting substrate further includes multiple groups of light-emitting devices, multiple first voltage signal lines, multiple second voltage signal lines, multiple address signal lines, multiple address transfer lines, and multiple feedback signal lines. At least one group of light emitting devices includes a plurality of light emitting devices, and the plurality of light emitting devices in the same group are electrically connected to the signal output pin of the same driving chip.
  • a plurality of groups of light emitting devices electrically connected to a plurality of driving chips of a driving chip subset are electrically connected to a first voltage signal line.
  • a second voltage signal line is electrically connected to the power supply pins of a plurality of driver chips of a driver chip subset.
  • One addressing signal line is electrically connected to the first-level driver chip among the plurality of driver chips in a driver chip group.
  • the signal output pin of the upper driving chip is electrically connected with the signal input pin of the lower driving chip through an addressing transfer line.
  • a feedback signal line is electrically connected to the last-level driver chip among the plurality of driver chips in a driver chip set.
  • the static electricity can be transmitted to the driving chip electrically connected to the grounding wire, and then transmitted to the driver chip connected to the grounding wire through the driving chip.
  • the pins of the cascaded driver chips in this way, the driver chip electrically connected to the ground trace and the pins of the driver chips cascaded with the driver chip form an equipotential body.
  • Multiple driver chip subgroups of the same driver chip group are cascaded, and multiple driver chip subgroups of the same driver chip group are cascaded; that is, all driver chips included in the same driver chip group are cascaded.
  • the multiple ground wires connected to the multiple driver chip subsets of the same driver chip group are electrically connected through at least one connection wire, that is, the multiple ground wires are electrically connected to the multiple cascaded driver chips that are electrically connected to each other.
  • an equipotential body is formed between the plurality of grounding wires electrically connected to the plurality of driver chip subsets of the same driver chip set, and the plurality of driver chips of the same driver chip set.
  • the risk of voltage difference formed between the driving chip and the grounding wire electrically connected to it is reduced, the risk of breakdown of the driving chip is reduced, and the reliability of the light-emitting substrate is improved.
  • a backlight module comprising the light-emitting substrate described in any one of the above embodiments.
  • the backlight module provided by the embodiments of the present disclosure can improve the reliability and reliability of the backlight module due to the adoption of the light-emitting substrate.
  • a display device including a display panel and the above-mentioned backlight module, and the backlight module is disposed on the backlight side of the display panel.
  • the display device provided by the embodiments of the present disclosure can achieve the same beneficial effect as that achieved by the aforementioned light-emitting substrate, and will not be repeated here.
  • FIG. 1 is a structural diagram of a display device according to some embodiments.
  • Fig. 2 is a sectional view along section line A-A in Fig. 1;
  • FIG. 3 is a structural diagram of a light emitting substrate according to some embodiments.
  • FIG. 4A is a structural diagram of a driver chip according to some embodiments.
  • 4B is a structural diagram of the internal circuit of the driver chip according to some embodiments.
  • FIG. 5 is a wiring structure diagram of a light-emitting substrate in the related art
  • Fig. 6 is a wiring structure diagram of a light-emitting substrate according to some embodiments.
  • Fig. 7 is a sectional view along section line B-B in Fig. 3;
  • Fig. 8 is a sectional view along section line C-C in Fig. 3;
  • Fig. 9 is a partial enlarged view of area D in Fig. 3;
  • Fig. 10 is a structural diagram of a second wiring according to some embodiments.
  • Fig. 11 is a sectional view along section line E-E in Fig. 10;
  • Fig. 12 is a structural diagram of a third wiring according to some embodiments.
  • Fig. 13 is a cross-sectional view along the section line F-F in Fig. 12 .
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality” means two or more.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • Standard layer refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous, and these specific patterns may also be at different heights Or have different thicknesses.
  • parallel As used herein, “parallel”, “perpendicular”, and “equal” include the stated situation and the situation similar to the stated situation, the range of the similar situation is within the acceptable deviation range, wherein the The stated range of acceptable deviation is as determined by one of ordinary skill in the art taking into account the measurement in question and errors associated with measurement of the particular quantity (ie, limitations of the measurement system).
  • “parallel” includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; Deviation within 5°.
  • “Equal” includes absolute equality and approximate equality, where the difference between the two that may be equal is less than or equal to 5% of either within acceptable tolerances for approximate equality, for example.
  • a layer or element when referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or that the layer or element can be on another layer or substrate. There is an intermediate layer in between.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • the display device 1000 may be any device that displays images whether moving (for example, video) or fixed (for example, still images) and whether text or text.
  • the display device 1000 may be a TV, a notebook computer, a tablet computer, a mobile phone, a personal digital assistant (English: personal digital assistant; PDA for short), a navigator, a wearable device, an augmented reality (English: Augmented Reality ; Abbreviation: AR) equipment, virtual reality (English: Virtual Reality; abbreviation: VR) equipment and any other products or components with display functions.
  • the above-mentioned display device 1000 may be a liquid crystal display device (Liquid Crystal Display; LCD for short).
  • the display device may include a backlight module 100 , a display panel 200 and a glass cover 300 .
  • the display panel 200 includes a light emitting side and a backlight side.
  • the light emitting side refers to the side of the display panel 200 for displaying images (the upper side of the display panel 200 in FIG. 2 ), and the backlight side refers to the other side opposite to the light emitting side.
  • the backlight module 100 is disposed on the backlight side of the display panel 200 (the lower side of the display panel 200 in FIG. 2 ), and the backlight module 100 is used to provide a light source for the display panel 200 .
  • the display panel 200 includes an array substrate 210 , a cell substrate 220 and a liquid crystal layer 230 disposed between the array substrate 210 and the cell substrate 220 .
  • Each sub-pixel of the array substrate 210 is provided with a thin-film transistor 212 (Thin-film transistor; TFT for short) and a pixel electrode 213 on the first substrate 211 .
  • the TFT 212 includes an active layer, a source, a drain, a gate and a gate insulating layer. The source and the drain are respectively in contact with the active layer.
  • the pixel electrode 213 is electrically connected to the drain of the TFT 212 .
  • the array substrate 210 further includes a common electrode 214 disposed on the first substrate 211 .
  • the pixel electrode 213 and the common electrode 214 may be disposed on different layers.
  • a first insulating layer 215 is disposed between the pixel electrode 213 and the common electrode 214 .
  • a second insulating layer 216 is further disposed between the common electrode 214 and the thin film transistor 212 .
  • the pixel electrode 213 and the common electrode 214 can also be arranged on the same layer (not shown in the figure), in this case, both the pixel electrode 213 and the common electrode 214 have a comb structure including a plurality of strip-shaped sub-electrodes.
  • the common electrode 214 may also be disposed in the cell-matching substrate 220 .
  • the box-to-box substrate 220 may include a color filter layer 222 disposed on the second substrate 221.
  • the box-to-box substrate 220 may also be called a color filter substrate (Color filter, CF for short).
  • the color filter layer 222 at least includes a red photoresist unit, a green photoresist unit and a blue photoresist unit, and the red photoresist unit, the green photoresist unit and the blue photoresist unit are respectively in direct contact with the sub-pixels on the array substrate 210. right.
  • the matching substrate 220 further includes a black matrix pattern 223 disposed on the second substrate 120 , and the black matrix pattern 223 is used to separate the red photoresist unit, the green photoresist unit and the blue photoresist unit.
  • the liquid crystal display panel 200 may further include a first polarizer 240 disposed on the side of the cell-aligning substrate 220 away from the liquid crystal layer 230 and a second polarizer 250 disposed on the side of the array substrate 210 away from the liquid crystal layer 230 .
  • the backlight module 100 includes a light emitting substrate 110 .
  • the light-emitting substrate 110 can directly emit white light, and the white light is emitted to the display panel 200 after uniform light treatment.
  • the light-emitting substrate 10 may also emit other colors of light, and then irradiate to the display panel 200 after color conversion and uniform light treatment.
  • the light-emitting substrate 10 emits blue light, which is then directed to the display panel 200 after color conversion and uniform light treatment.
  • the backlight module 100 includes a light emitting substrate 110 , a quantum dot film 120 and an optical film 130 .
  • the light emitting substrate 110 may emit blue light.
  • the quantum dot film 30 may include a red quantum dot material, a green quantum dot material, and a transparent material. When the blue light emitted by the light-emitting substrate 110 passes through the red quantum dot material, it is converted into red light; when it passes through the green quantum dot material, it is converted into green light; when it passes through the transparent material, no color conversion occurs.
  • the optical film 130 may include a diffusion plate and/or an optical brightness enhancement film, which is not specifically limited in embodiments of the present disclosure.
  • the diffusion plate has a scattering and diffusion effect, and can further mix the white light; the optical brightness enhancement film can improve the light extraction efficiency of the backlight module 100 .
  • the light-emitting substrate 110 includes multiple groups of light-emitting devices 10 , multiple driver chipsets 20 and multiple signal lines 30 . Wherein, only two driver chipsets 20 are shown in FIG. 3 as an example.
  • At least one group of light emitting devices 10 includes a plurality of light emitting devices 11 .
  • the light emitting device 11 may be Mini-LED and/or Micro-LED.
  • a set of light emitting devices 10 may include 4, 6, 8, or 9 light emitting devices 10 .
  • Multiple light emitting devices 10 can be connected in series and/or in parallel.
  • a plurality of light emitting devices 10 can be connected in series in sequence (as shown in FIG. 3 ); or, some of the plurality of light emitting devices 10 are connected in series and part of them are connected in parallel (not shown in the figure); or, a plurality of light emitting devices 10 are connected in parallel with each other (not shown in the figure).
  • the number of light emitting devices 10 in a group of light emitting devices 10 and the connection manner of multiple light emitting devices in a group of light emitting devices 10 are not specifically limited. Therefore, it should be understood that, in FIG. 3 , only a plurality of light emitting devices 11 of one group of light emitting devices 10 are exemplarily shown, and the remaining groups of light emitting devices 10 are all simply expressed by frames. And in FIG. 3 , a group of light emitting devices 10 includes nine light emitting devices 11 , and the sequential series connection of the nine light emitting devices 11 is only an exemplary display and does not constitute a limitation to the present disclosure.
  • At least one driver chip set 20 includes multiple driver chip subsets 201, and at least one driver chip subset 201 includes multiple driver chips 12 cascaded; multiple driver chip subsets 201 of the same driver chip set 20 are cascaded. That is, all the driver chips 12 included in the plurality of driver chip subsets 201 in one driver chip group 20 are cascaded in sequence.
  • a driver chip subgroup 201 includes a plurality of driver chips 12 arranged along a first direction Y; a driver chip group 20 includes two driver chip subgroups 201 distributed along a second direction X.
  • the driver chip 12 may include a signal input pin Di (the input pin of the addressing signal ADDR), a signal output pin Out, a ground pin GND, and a power pin PWR .
  • the cascading of a plurality of driver chips 12 refers to: a plurality of driver chips 12 are cascaded in sequence, and among the two driver chips 12 cascaded with each other, the output pin Do of the upper driver chip is connected to the signal input pin Di of the lower driver chip. electrical connection.
  • the internal circuit of the driving chip 12 shown in FIG. 4B is only an exemplary expression, rather than the actual circuit inside the driving chip 12.
  • This circuit is only used to indicate that static electricity can be transmitted from the ground pin GND of the driving chip 12 to the signal The input pin Di and the signal output pin Out; however, the signal input pin Di and the signal output pin Out of the driver chip 12 cannot be transmitted to the ground pin GND.
  • the driving chip 12 may be broken down (damaged).
  • the multiple signal lines 30 include multiple ground wires 13 , and the ground wires 13 are used to electrically connect with the ground pin GND of the driver chip 12 .
  • driver chips 12 of each driver chip subset 201 are electrically connected to one ground wire 13 , and the ground wires 13 connected to different driver chip subsets 201 are different and electrically insulated from each other.
  • the static electricity can be transmitted to the ground pins GND of the plurality of driving chips 12 electrically connected to the ground wire 13 .
  • the driver chip subgroup 201 in which the above-mentioned plurality of driver chips 12 are located is called the first driver chip subgroup 201A
  • Static electricity can be transferred to the pins of the driver chip 12 (hereinafter referred to as: target driver chip 12A) cascaded with the first driver chip subset 201A in the second driver chip subset 201B (for example, static electricity can be generated by the first driver chip subset
  • the signal output pin Out of the last-level driver chip 12 of 201A is transmitted to the signal input pin Di) of the first-level driver chip 12 of the second driver chip subgroup 201B.
  • a potential difference to appear between the pins cascaded with the driver chips 12 of the first driver chip subgroup 201A on the target driver chip 12A and the ground wiring 13 (the ground wiring 13 electrically connected to the target driver chip 12A).
  • the target driving chip 12A may be broken down, causing a group of light emitting devices 10 electrically connected to the target driving chip 12A to emit light abnormally.
  • a driving chip group 20 includes two driving chip subgroups 201 distributed along the second direction X, wherein the two driving chip subgroups 201 are respectively the first driving chip subgroup 201A and the second driving chip subgroup 201A.
  • the first driver chip subgroup 201A is electrically connected to the first ground wire 13A
  • the second driver chip subgroup 201B is electrically connected to the second ground wire 13B
  • the first ground wire 13A is electrically insulated from the second ground wire 13B.
  • the static electricity can enter the driver chip 12 from the ground pin GND of the driver chip 12, and be transmitted to the upper driver chip along the path L1 and the path L2 respectively.
  • the last driver chip 12 of the first driver chip subgroup 201A (the uppermost driver chip 12 in FIG. 5 ) to the first driver chip 12A (the target driver chip 12A) signal input pin Di.
  • the driver chips 12 cascaded with the second driver chip subset 201B in the first driver chip subset 201A (the first driver chip subset 201A in FIG. A potential difference is generated between the uppermost driver chip 12) and the first ground wire 13A, which may break down the driver chips 12 in the first driver chip subgroup 201A cascaded with the second driver chip subgroup 201B.
  • the light-emitting substrate 110 includes multiple driving chipsets 20 , multiple ground wires 13 and at least one connection wire 14 .
  • At least one driver chip group 20 in a plurality of driver chip groups 20 includes a plurality of driver chip subgroups 201, and at least one driver chip subgroup 201 includes a plurality of cascaded driver chips 12; a plurality of driver chips in the same driver chip group 20 Subgroup 201 cascaded settings. That is, all the driver chips 12 included in the plurality of driver chip subsets 201 in one driver chip group 20 are cascaded. Multiple driver chips 12 of the same driver chip subset 201 are electrically connected to the same ground wire 13 , and different driver chip subsets 201 are connected to different ground wires 13 .
  • FIG. 3 only exemplarily shows two driver chipsets 20 .
  • Each of the two driver chip sets 20 includes two driver chip subsets 201 .
  • Each driver chip subset 201 includes a plurality of driver chips 12 cascaded. All the driver chips 12 included in the two driver chip subsets 201 are cascaded.
  • ground wires 13 connected to multiple driver chip subsets 201 of the same driver chip group 20 are electrically connected through at least one connection wire 14 . Based on this, after one of the grounding wires 13 generates static electricity, the static electricity can be transferred to the driver chip 12 electrically connected to the grounding wire 13, and passed through the driver chip 12 to the pins of the cascaded driver chip 12. In this way, the driver chip 12 electrically connected to the ground wire 13 and the pins of the driver chip 12 cascaded with the driver chip 12 form an equipotential body.
  • Multiple driver chips 12 of the same driver chip subgroup 201 are cascaded, and multiple driver chip subgroups 201 of the same driver chip group 20 are cascaded; that is, all the driver chips 12 included in the same driver chip group 20 are cascaded. set up.
  • Multiple ground wires 13 connected to multiple driver chip subsets 201 of the same driver chip group 20 are electrically connected through at least one connection wire 14, that is, multiple ground wires electrically connected to multiple driver chips 12 cascaded with each other.
  • Wire 14 is electrically connected.
  • an equipotential body is formed between the plurality of ground wires 13 electrically connected to the plurality of driver chip subsets 201 of the same driver chip set 20 and all the driver chips 12 of the same driver chip set 20 .
  • the risk of voltage difference formed between the driving chip 12 and the ground wire 13 electrically connected to it is reduced, the risk of breakdown of the driving chip 12 is reduced, and the reliability of the light-emitting substrate 110 is improved.
  • a driving chip group 20 includes two driving chip subgroups 201 distributed along the second direction X, wherein the two driving chip subgroups 201 are respectively a first driving chip subgroup 201A and a second driving chip subgroup 201B.
  • the first driver chip subset 201A is electrically connected to the first ground wire 13A
  • the second driver chip subset 201B is electrically connected to the second ground wire 13B
  • the first ground wire 13A and the second ground wire 13B pass at least
  • a connection line 14 is electrically connected.
  • the static electricity When static electricity is generated on one of the ground traces 13 (such as the first ground trace 13A), the static electricity can be transferred to the second ground trace 13B, so that the first ground trace 13A and the second ground trace 13B form an equipotential body. Then, the ground pins GND of the plurality of driving chips 12 of the driving chipset 20 enter the driving chips 12 , and pass through the driving chips 12 to the signal input pin Di and the signal output pin Out of the driving chip 12 . In this way, there is no potential difference between the signal input pin Di and the signal output pin Out of the driver chip 12 and the ground pin GND, which can reduce the risk of breakdown of the driver chip 12 and improve the reliability of the light-emitting substrate 110 .
  • the light-emitting substrate 110 includes a light-emitting region 101 , a fan-out region 102 and a bonding region 103 arranged side by side along a first direction Y in order.
  • the fan-out area 102 is used to lead a plurality of signal lines 30 to the binding area 103, and the binding area 103 is provided with a plurality of binding pins, and the binding pins are used for connecting with other electronic components (such as FPC, PCB and control chip, etc.) electrical connection.
  • other electronic components such as FPC, PCB and control chip, etc.
  • the multiple driver chips 12 of the driver chip subgroup 201 are arranged roughly along the first direction Y, the multiple driver chip subgroups 201 of the driver chip group 20 are roughly arranged along the second direction X, and the multiple driver chip groups 20 are roughly arranged along the second direction X.
  • the direction X is arranged. That is: all the driving chips 12 included in the light-emitting substrate 10 are arranged in a row along the first direction Y, multiple rows of driving chips 12 are distributed along the second direction X, and multiple driving chips 12 in each column are cascaded to form a driving chip subgroup 201 , multiple columns of driver chips (multiple driver chip subsets 201 ) are cascaded to form a driver chip group 20 .
  • first direction Y and the second direction X cross each other.
  • first direction Y and the second direction X are perpendicular to each other.
  • the driving chips 12 included in the light emitting substrate 10 may also be arranged in other forms.
  • the embodiments of the present disclosure are only described exemplarily by taking the driving chips 12 arranged in a matrix as an example.
  • the grounding wire 13 generally extends along the first direction Y.
  • the ground wire 13 extends roughly along the first direction Y, and in the fan-out area 102 , the ground wire 13 may form a certain angle with the first direction Y.
  • the ground wiring 13 and the driver chip subgroup 201 are alternately arranged, so that when multiple driver chips 12 of a driver chip subgroup 201 are electrically connected to one ground wiring 13, it is beneficial for the ground wiring 13 to Spatial arrangement, and facilitate the electrical connection between the ground wire 13 and the plurality of driver chips 12 of the driver chip subset 201 .
  • the multiple driver chips 12 of the driver chip subset 201 are electrically connected to an adjacent ground wire 13 .
  • the plurality of driver chips 12 of the driver chip subgroup 201 are electrically connected to a ground wire 13 on the left side thereof.
  • FIGS. 3 , 7 and 8 are cross-sectional structure diagram in the light-emitting region 101 of the light-emitting substrate 110 shown in FIG. 3
  • FIG. 8 is a cross-sectional structure diagram in the fan-out region 102 of the light-emitting substrate 110 shown in FIG. 3
  • the light-emitting substrate 110 (multiple signal lines 30) also includes a plurality of first voltage signal lines 15, a plurality of second voltage signal lines 16, a plurality of addressing signal lines 17, a plurality of addressing transfer lines 18, and a plurality of feedback lines.
  • Signal line 19 is a plurality of first voltage signal lines 15, a plurality of second voltage signal lines 16, a plurality of addressing signal lines 17, a plurality of addressing transfer lines 18, and a plurality of feedback lines.
  • At least one first voltage signal line 15 among the plurality of first voltage signal lines 15 roughly extends along the first direction Y, and along the second direction X, the first voltage signal lines 15 and the grounding lines 13 are arranged alternately , one first voltage signal line 15 corresponds to one driving chip subset 201 .
  • each of the plurality of first voltage signal lines 15 generally extends along the first direction Y.
  • One first voltage signal line 15 corresponds to one driver chip subgroup 201, that is, multiple groups of light emitting devices 10 electrically connected to a plurality of driver chips 12 of one driver chip subgroup 201 are electrically connected to one first voltage signal line 15 .
  • the first voltage signal line 15 is configured to provide a positive voltage signal to the light emitting device 10 .
  • the first voltage signal line 15 and the grounding line 13 are located on the same layer, the first voltage signal line 15 and the grounding line 13 are arranged alternately along the second direction X, and one first voltage signal line 15 is located on the side of a ground wire 13 away from the driver chip subset 201 .
  • the light emitting device 11 is also electrically connected to the signal output pin Out of the driver chip 12 , and the signal output pin Out is configured to output a negative voltage signal to the light emitting device 10 and output an addressing signal to the lower driver chip 12 .
  • the driving chip 12 can control whether a group of light emitting devices 10 electrically connected to the control chip 12 emit light, and the brightness of the light.
  • the multiple first voltage signal lines 15 are made of the same material as the multiple ground traces 13 and are arranged on the same layer.
  • the multiple first voltage signal lines 15 and the multiple ground traces 13 are made of copper and are located on the first trace layer 22 .
  • a second voltage signal line 16 (for example, a power supply voltage signal line) is electrically connected to the power supply pins PWR of a plurality of driving chips 12 of a driving chip subgroup 201 .
  • the second voltage signal line 16 is configured to provide a power supply voltage signal to the driving chip 12 .
  • the second voltage signal lines 16 and ground traces 13 are alternately arranged.
  • the second voltage signal line 16 and the grounding line 13 are made of the same material and arranged on the same layer.
  • the multiple first voltage signal lines 15 and the multiple ground traces 13 are made of copper and are located on the first trace layer 22 . Wherein, only one of the first voltage signal lines 15 and one grounding line 13 are shown in FIG. 7 .
  • One addressing signal line 17 is electrically connected to the first level driver chip 12 among the plurality of driver chips 12 in a driver chip group 20 .
  • the address signal line 17 is configured to supply an address signal (ADDR signal) to a plurality of driving chips 12 of one driving chip set 20 .
  • the signal output pin Out of the upper driving chip 12 is electrically connected to the signal input pin Di of the lower driving chip 12 through an addressing transfer line 18 .
  • a feedback signal line 18 (also referred to as a return signal line FB) is electrically connected to the last-level driver chip 12 among the plurality of driver chips 12 in a driver chip set 20 .
  • the feedback signal line 18 is configured to output a return signal for driving the chipset 20 .
  • the addressing signal line 17 , the addressing transfer line 18 , and the feedback signal line 19 are made of the same material and arranged on the same layer.
  • the addressing signal line 17 , the addressing transition line 18 , and the feedback signal line 19 are made of copper, and are located on the second wiring layer 24 .
  • FIG. 7 only shows the addressing transfer line 18 as an example.
  • the addressing signal line 17 and the feedback signal line 19 are arranged on the same layer, and both are located in the first wiring layer 22 . In this way, it is beneficial to arrange multiple binding pins of multiple signal lines 30 on the same film layer, which facilitates the binding connection between the binding pins and other electronic components.
  • FIG. 8 exemplarily shows a cross-sectional view of a plurality of signal lines 30 at the fan-out region 30 .
  • the ground wiring 13 In the fan-out area 102 , the ground wiring 13 , the first voltage signal line 15 , the second voltage signal line 16 , the addressing signal line 17 and the feedback signal line 19 are arranged on the same layer and located on the first wiring layer.
  • the address transfer wire 18 is used to electrically connect the two cascaded driver chips 12, and the plurality of driver chips 12 of the plurality of driver chip groups 20 are all arranged in the light emitting area 101, therefore, the address transfer wire 18 Only disposed in the light emitting region 101 , or partly disposed in the light emitting region 101 , and partly disposed in the fan-out region 102 close to the edge of the light emitting region 101 .
  • FIG. 9 is a partially enlarged view of area D in FIG. 3 .
  • the end of the ground trace 13 away from the fan-out area 102 exceeds the end of the first voltage signal line 15 away from the fan-out area 102 (the first voltage signal The upper end of the line 15 along the first direction Y).
  • At least one connection line 14 includes a first connection line 141 located on a side of the first voltage signal line 15 away from the fan-out area 102 , and the first connection line 141 is electrically connected to an end of the ground trace 13 away from the fan-out area 102 .
  • the first connection line 141 can avoid other signal lines (such as the first voltage signal line 15 and the second voltage signal line 16, the address transfer line 18, etc.), does not affect the arrangement of other signal lines, and does not need to adjust other signal lines.
  • the preparation process of the line; and the signal interference between the first connection line 141 and other signal lines can be reduced.
  • the first connecting wire 141 and the grounding wire 13 are made of the same material and arranged on the same layer. In this way, the first connecting wire 141 can be formed by using the preparation process of the grounding wire 13, and the light-emitting substrate 110 does not need to add additional The processing steps are beneficial to reduce the manufacturing difficulty and cost of the light-emitting substrate 110 .
  • the gap D1 between the first connection line 141 and the end of the first voltage signal line 15 away from the fan-out region 102 is greater than or equal to 200 ⁇ m. In this way, the signal interference caused by the first connection line 14 to the first voltage signal line 15 can be reduced.
  • the above-mentioned gap D may be 200 ⁇ m, 250 ⁇ m, 300 ⁇ m, etc., which are not listed in the embodiments of the present disclosure.
  • the size of the gap D can be increased, and the specific value of the gap D can be set according to actual needs.
  • the gap D1 is not necessarily as large as possible. If the gap D1 is too large, the area of the non-light-emitting region of the light-emitting substrate 110 may increase, which is not conducive to reducing the frame width of the display device 1000 .
  • FIG. 10 is a structural diagram when the connecting wire 14 (the second connecting wire 142 ) is disposed in the light emitting region 101 .
  • the light-emitting substrate 110 includes a substrate 21, a first wiring layer 22 disposed on the substrate 21, a first insulating layer 23 disposed on the side of the first wiring layer 21 away from the substrate 21, and a first insulating layer disposed on the first insulating layer 21. 23 away from the second wiring layer 24 on the side of the substrate 21 .
  • a plurality of first via holes 231 are disposed in the first insulating layer 23 .
  • At least one connection line 14 includes a second connection line 142 located on the second wiring layer 24, and the orthographic projection of the second connection line 142 on the first insulating layer 23 is the same as that of the first voltage signal line 15 on the first insulating layer 23.
  • the orthographic projections partially overlap.
  • the second connection wire 142 is electrically connected to the ground wire 13 through the first via hole 231 .
  • the second connection line 142 is arranged in the light-emitting region 101, which is beneficial to reduce the width of the non-light-emitting region (the side of the light-emitting region 101 away from the fan-out region), which is conducive to reducing the frame width of the light-emitting substrate 110 and reducing the frame width of the display device 1000.
  • the second connection line 142 is disposed on the second wiring layer 24 , which can avoid short circuit with the first voltage signal line 15 and the second voltage signal line 16 , and improve the reliability of the light-emitting substrate 110 .
  • one driver chip set 20 includes two driver chip subgroups 201 , and the multiple driver chips 12 of each driver chip subgroup 201 are electrically connected to one ground wire 13 .
  • the second connecting wire 142 is electrically connected to the two grounding wires 13 respectively through a first via hole 231 .
  • the two ground wires 13 may be electrically connected through one, two, or more second connection wires 142 .
  • At least one second connecting wire 142 may be electrically connected between every two adjacent grounding wires 13 .
  • any number of adjacent ground traces 13 may be electrically connected through at least one second connecting wire 142 .
  • the ground trace 13 includes a main body 131 and a connecting portion 132 , the main body 131 extends along the first direction Y, and the connecting portion 132 is configured to electrically connect the main body 131 and the driver chip 12 .
  • the connecting portion 132 is electrically connected to the main body portion 131 , and the other end is electrically connected to the ground pin GND of the driving chip 12 .
  • the second connection line 142 is electrically connected to the connection portion 132 through the first via hole 231, and the line width D2 of the connection portion 132 electrically connected to the second connection line 142 is greater than that of the connection portion 132 not electrically connected to the second connection line 142.
  • Line width D3 By increasing the line width of the connecting portion 132 electrically connected to the second connecting line 142, the risk of damaging the connecting portion 132 electrically connected to the second connecting line 142 due to the excessive current of the second connecting line 142 can be reduced, and the light-emitting substrate 110 can be improved.
  • the antistatic ability improves the reliability of the light-emitting substrate 110 .
  • the ground wiring 13 includes a first lead-out section 133 located in the fan-out region 102 , and the first lead-out section 133 is located in the first wiring layer 22 .
  • the light-emitting substrate 110 further includes an insulating pattern 40 located in the fan-out region 102 and covering at least a part of the first lead-out segment 133 .
  • At least one connection line 14 includes a third connection line 143 located in the fan-out area 102, the third connection line 143 is located on the side of the insulating pattern 40 away from the substrate 21, and the third connection line 143 is connected to the first lead-out through the second via hole 41. Segment 133 is electrically connected.
  • the light emitting area 101 includes a large number of light emitting devices 11 , driving chips 12 and a plurality of signal lines 30 , and the space for setting the signal lines is relatively small. Therefore, disposing the third connection line 143 in the fan-out area 102 can reduce the lead wires of the third connection line 143 to the plurality of signal lines 30 in the light emitting area 101, and the wiring space of the third connection line 143 is large without affecting Arrangement of the remaining signal lines 30 .
  • the third connection line 143 has a grid structure, so that the third connection line 143 can reduce the impact on other signal lines 30 without reducing the resistance of the third connection line 143 . signal interference, and improve the reliability of the light-emitting substrate 110 .
  • the insulating pattern 40 is located on the first insulating layer 23
  • the third connection line 143 is located on the second wiring layer 24 .
  • the insulating pattern 40 and the third connection line 143 can be formed by using the existing film forming process, which is beneficial to simplify the manufacturing process of the light-emitting substrate 110 and reduce the manufacturing cost of the light-emitting substrate 110 .
  • the insulating pattern 40 can also be formed after the second wiring layer 24, that is, the insulating pattern 40 and the first insulating layer 23 adopt two film-forming processes (for example, including coating, exposure, development, and etching processes). )form.
  • the third connection line 143 and the second wiring layer 24 are also formed by two-side film forming process.

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Abstract

一种发光基板（110），发光基板（110）包括多个驱动芯片组（20）、多条接地走线（13）、和至少一条连接线（14）。至少一个驱动芯片组（20）包括多个驱动芯片子组（201，201A，201B），至少一个驱动芯片子组（201，201A，201B）包括级联的多个驱动芯片（12）；同一驱动芯片组（20）的多个驱动芯片子组（201，201A，201B）级联设置。同一驱动芯片子组（201，201A，201B）的多个驱动芯片（12）与同一条接地走线（13）电连接，且不同驱动芯片子组（201，201A，201B）连接的接地走线（13）不同。与同一驱动芯片组（20）的多个驱动芯片子组（201，201A，201B）连接的多条接地走线（13）通过至少一条连接线（14）电连接。

Description

发光基板、背光模组及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种发光基板、背光模组及显示装置。
背景技术
次毫米发光二极管(Mini Light Emitting Diode；简称：Mini-LED)尺寸约为100μm～300μm，微型发光二极管(Micro Light Emitting Diode；简称：Micro-LED)尺寸约小于100μm。Mini-LED和Micro-LED由于尺寸小亮度高，应用于背光模组时，可以对背光进行精细调节，从而实现高动态范围图像(High-Dynamic Range，HDR)的显示，从而受到越来越多的关注。提升采用Mini-LED或Micro-LED的发光基板的信赖性是当前亟需解决的问题。
公开内容
一方面，提供一种发光基板。所述发光基板包括多个驱动芯片组、多条接地走线、和至少一条连接线。至少一个驱动芯片组包括多个驱动芯片子组，至少一个驱动芯片子组包括级联的多个驱动芯片；同一驱动芯片组的多个驱动芯片子组级联设置。同一驱动芯片子组的多个驱动芯片与同一条接地走线电连接，且不同驱动芯片子组所连接的接地走线不同。与同一驱动芯片组的多个驱动芯片子组所连接的多条接地走线通过至少一条所述连接线电连接。
在一些实施例中，所述发光基板还包括多条第一电压信号线。至少一条第一电压信号线大致沿第一方向延伸，且沿第二方向，所述第一电压信号线与所述接地走线交替设置，一条所述第一电压信号线与一个驱动芯片子组对应；所述多条第一电压信号线与所述多条接地走线材料相同且同层设置。其中，所述发光基板包括沿所述第一方向并排设置的发光区和扇出区，所述多个驱动芯片组位于所述发光区。所述接地走线远离所述扇出区的一端超出所述第一电压信号线远离所述扇出区的端部。所述至少一条连接线包括位于所述第一电压信号线远离所述扇出区一侧的第一连接线，所述第一连接线与所述接地走线远离所述扇出区的端部电连接。
在一些实施例中，所述第一连接线和所述接地走线材料相同且同层设置，且所述第一连接线与所述第一电压信号线的远离所述扇出区的端部之间具有间隙。
在一些实施例中，所述第一连接线与所述第一电压信号线之间的间隙大于或等于200μm。
在一些实施例中，所述发光基板还包括多条第一电压信号线。至少一条第一电压信号线大致沿第一方向延伸，且沿第二方向，所述第一电压信号线与所述接地走线交替设置，一条所述第一电压信号线与一个驱动芯片子组对应。其中，所述发光基板包括依次层叠设置的衬底、第一走线层、第一绝缘层和第二走线层。所述多条接地走线和所述多条第一电压信号线位于所述第一走线层。所述第一绝缘层中设有第一过孔。所述至少一条连接线包括位于所述第二走线层的第二连接线，所述第二连接线在所述第一绝缘层上的正投影与所述第一电压信号线在所述第一绝缘层上的正投影部分交叠。所述第二连接线通过所述第一过孔与所述接地走线电连接。
在一些实施例中，所述发光基板包括沿所述第一方向并排设置的发光区和扇出区，所述多个驱动芯片组位于所述发光区。所述接地走线包括主体部和连接部，所述主体部沿所述第一方向延伸，所述连接部将所述主体部与所述驱动芯片电连接。所述第二连接线通过所述第一过孔与所述连接部电连接，且与所述第二连接线电连接的连接部的线宽大于不与所述第二连接线电连接的连接部的线宽。
在一些实施例中，所述发光基板包括沿第一方向并排设置的发光区和扇出区，所述多个驱动芯片组位于所述发光区。所述发光基板包括衬底，设置于所述衬底上的第一走线层，设置于所述第一走线层远离所述衬底一侧的绝缘图案，所述绝缘图案中设有第二过孔。所述接地走线包括位于所述扇出区的第一引出段，且所述第一引出段位于所述第一走线层。所述至少一条连接线包括位于所述扇出区的第三连接线，所述第三连接线位于所述绝缘图案远离所述衬底一侧，且所述第三连接线通过所述第二过孔与所述第一引出段电连接。
在一些实施例中，所述第三连接线为网格状结构。
在一些实施例中，所述发光基板还包括设置于所述第一走线层远离所述衬底一侧的第一绝缘层，设置于所述第一绝缘层远离所述衬底一侧的第二走线层。所述绝缘图案位于所述第一绝缘层，所述第三连接线位于所述第二走线层。
在一些实施例中，所述驱动芯片子组的多个驱动芯片大致沿第一方向排列，所述驱动芯片组的多个驱动芯片子组大致沿第二方向排布，所述多个驱动芯片组大致沿所述第二方向排布。所述第一方向和所述第二方向相互交叉。所述接地走线大致沿所述第一方向延伸，且沿所述第二方向，所述接地走线和所述驱动芯片子组交替排布，所述驱动芯片子组的多个驱动芯片与相邻的 一条所述接地走线电连接。
在一些实施例中，同一驱动芯片组的任意相邻两个驱动芯片子组中，其中一个驱动芯片子组的最后一级驱动芯片与另外一个驱动芯片子组的第一级驱动芯片电连接。
在一些实施例中，所述驱动芯片包括信号输入引脚、信号输出引脚、接地引脚、及电源引脚。所述发光基板还包括多组发光器件、多条第一电压信号线、多条第二电压信号线、多条寻址信号线、多条寻址转接线、和多条反馈信号线。至少一组发光器件包括多个发光器件，同一组的多个发光器件与同一个所述驱动芯片的信号输出引脚电连接。与一个驱动芯片子组的多个驱动芯片电连接的多组发光器件与一条第一电压信号线电连接。一条第二电压信号线与一个驱动芯片子组的多个驱动芯片的所述电源引脚电连接。一条寻址信号线与一个驱动芯片组中的多个驱动芯片中的第一级驱动芯片电连接。级联的两个驱动芯片中，上级驱动芯片的信号输出引脚，与下级驱动芯片的信号输入引脚通过一条寻址转接线电连接。一条反馈信号线与一个驱动芯片组的多个驱动芯片中的最后一级驱动芯片电连接。
本公开实施例提供的发光基板，接地走线产生静电(Electro-Static discharge；简称：ESD)时，静电能够传递至与该接地走线电连接的驱动芯片，并通过该驱动芯片传递至与之级联的驱动芯片的引脚上；这样，与接地走线电连接的驱动芯片，以及与该驱动芯片级联的驱动芯片的引脚形成等电势体。同一个驱动芯片子组的多个驱动芯片级联设置，同一个驱动芯片组的多个驱动芯片子组级联；即同一个驱动芯片组所包含的全部驱动芯片级联设置。与同一驱动芯片组的多个驱动芯片子组所连接的多条接地走线通过至少一条连接线电连接，即与相互级联的多个驱动芯片电连接的多条接地走线电连接。这样，与同一个驱动芯片组的多个驱动芯片子组电连接的多条接地走线，以及同一个驱动芯片组的多个驱动芯片之间形成等电势体。进而降低驱动芯片与其电连接的接地走线之间形成电压差的风险，降低驱动芯片被击穿的风险，提升发光基板的信赖性。
另一方面，提供一种背光模组，包括上述任一实施例中所述的发光基板。
本公开的实施例提供的背光模组，由于采用了上述发光基板，能够提升背光模组的信赖性和可靠性。
又一方面，提供一种显示装置，包括显示面板和上述背光模组，背光模组设置于显示面板的背光侧。
本公开的实施例提供的显示装置，能够实现的有益效果与前述发光基板 能够实现的效果相同，在此不再赘述。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示装置的结构图；
图2为沿图1中剖面线A-A的剖视图；
图3为根据一些实施例的发光基板的结构图；
图4A为根据一些实施例的驱动芯片的结构图；
图4B为根据一些实施例的驱动芯片内部电路结构图；
图5为相关技术中的发光基板的走线结构图；
图6为根据一些实施例的发光基板的走线结构图；
图7为沿图3中剖面线B-B的剖视图；
图8为沿图3中剖面线C-C的剖视图；
图9为图3中D区域的局部放大图；
图10为根据一些实施例的第二接线的一种结构图；
图11为沿图10中剖面线E-E的剖视图；
图12为根据一些实施例的第三接线的一种结构图；
图13为沿图12中剖面线F-F的剖视图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)” 或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或 元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的一些实施例提供了一种显示装置1000，参阅图1，显示装置1000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。示例性地，该显示装置1000可以为电视机、笔记本电脑、平板电脑、手机、个人数字助理(英文：personal digital assistant；简称：PDA)、导航仪、可穿戴设备、增强现实(英文：Augmented Reality；简称：AR)设备、虚拟现实(英文：Virtual Reality；简称：VR)设备等任何具有显示功能的产品或者部件。
在一些实施例中，上述显示装置1000可以为液晶显示装置(Liquid Crystal Display；简称：LCD)。参阅图2，显示装置可以包括背光模组100、显示面板200和玻璃盖板300。显示面板200包括出光侧和背光侧。出光侧是指显示面板200用于显示画面的一侧(图2中显示面板200的上侧)，背光侧是指与出光侧相对的另一侧。背光模组100设置于显示面板200的背光侧(图2中显示面板200的下侧)，背光模组100用于为显示面板200提供光源。
在一些实施例中，参阅图2，显示面板200包括阵列基板210、对盒基板220以及设置在阵列基板210和对盒基板220之间的液晶层230。
阵列基板210的每个子像素均设置有位于第一衬底211上的薄膜晶体管212(Thin-film transistor；简称：TFT)和像素电极213。薄膜晶体管212包括有源层、源极、漏极、栅极及栅绝缘层，源极和漏极分别与有源层接触，像素电极213与薄膜晶体管212的漏极电连接。
在一些实施例中，如图2所示，阵列基板210还包括设置在第一衬底211上的公共电极214。像素电极213和公共电极214可以设置在不同层，在此情况下，如图2所示，像素电极213和公共电极214之间设置有第一绝缘层215。在公共电极214设置在薄膜晶体管212和像素电极213之间的情况下，如图2所示，公共电极214与薄膜晶体管212之间还设置有第二绝缘层216。
像素电极213和公共电极214也可以设置在同一层(图中未示出)，在此情况下，像素电极213和公共电极214均为包括多个条状子电极的梳齿结构。在另一些实施例中，公共电极214还可以设置于对盒基板220中。
如图2所示，对盒基板220可以包括设置在第二衬底221上的彩色滤光层222，在此情况下，对盒基板220也可以称为彩膜基板(Color filter，简称CF)。其中，彩色滤光层222至少包括红色光阻单元、绿色光阻单元以及蓝色光阻单元，红色光阻单元、绿色光阻单元以及蓝色光阻单元分别与阵列基板210上的子像素一一正对。对盒基板220还包括设置在第二衬底120上的黑矩阵图案223，黑矩阵图案223用于将红色光阻单元、绿色光阻单元以及蓝色光阻单元间隔开。
如图2所示，液晶显示面板200还可以包括设置在对盒基板220远离液晶层230一侧的第一偏光片240以及设置在阵列基板210远离液晶层230一侧的第二偏光片250。
在一些实施例中，背光模组100包括发光基板110。发光基板110可以直接发射白色光线，白色光线经匀光处理后射向显示面板200。或者，发光基板10也可以发色其他色光，然后经色转换和匀光处理后射向显示面板200。
示例性地，参阅图2，发光基板10发射蓝色光线，然后经色转换和匀光处理后射向显示面板200。此时，背光模组100包括发光基板110、量子点膜120和光学膜片130。发光基板110可以为发射蓝色光线。量子点膜30可以包括红色量子点材料、绿色量子点材料和透明材料。发光基板110发射的蓝色光线穿过红色量子点材料时，被转换为红色光线；穿过绿色量子点材料时，被转换为绿色光线；穿过透明材料时，不会发生色转换。然后，蓝色光线、红色光线和绿色光线以一定比例混合叠加后呈现为白光。光学膜片130可以包括扩散板和/或光学增亮膜，本公开的实施例对此不做具体限定。其中，扩散板具有散射和扩散效应，能够将上述白色光进一步混匀；光学增亮膜能够提升背光模组100的出光效率。
在一些实施例中，参阅图3，发光基板110包括多组发光器件10、多个驱动芯片组20和多条信号线30。其中，图3中仅示例性地展示了两个驱动芯片组20。
其中，至少一组发光器件10包括多个发光器件11。示例性地，发光器件11可以为Mini-LED和/或Micro-LED。一组发光器件10可以包括4个、6个、8个、或9个发光器件10。多个发光器件10的连接方式可以为串联和/或并联。示例性地，多个发光器件10可以依次串联(如图3所示)；或者，多个发光 器件10的部分串联，部分并联(图中未示出)；或者，多个发光器件10相互并联(图中未示出)。
本公开的实施例中，对一组发光器件10中发光器件10的数量，以及一组发光器件10中多个发光器件的连接方式不作具体限定。因此，应当理解的是，在图3中，仅示例性地展示了一组发光器件10的多个发光器件11，其余多组发光器件10均以图框进行简易表达。且在图3中，一组发光器件10包括9个发光器件11，9个发光器件11依次串联仅仅是一个示例性地展示，不构成对本公开的限定。
至少一个驱动芯片组20包括多个驱动芯片子组201，至少一个驱动芯片子组201包括级联的多个驱动芯片12；同一驱动芯片组20的多个驱动芯片子组201级联设置。即一个驱动芯片组20中的多个驱动芯片子组201所包括的所有驱动芯片12依次级联设置。
示例性地，参阅图3，一个驱动芯片子组201包括沿第一方向Y排布的多个驱动芯片12；一个驱动芯片组20包括沿第二方向X分布的两个驱动芯片子组201。
在一些实施例中，参阅图4A和图4B，驱动芯片12可以包括信号输入引脚Di(寻址信号ADDR的输入引脚)、信号输出引脚Out、接地引脚GND、及电源引脚PWR。多个驱动芯片12级联是指：多个驱动芯片12依次级联设置，且相互级联的两个驱动芯片12中，上级驱动芯片的输出引脚Do与下级驱动芯片的信号输入引脚Di电连接。
其中，图4B中所示驱动芯片12的内部电路仅为示例性表达，而非驱动芯片12内部的实际电路，该电路仅仅用于表示：静电可以从驱动芯片12的接地引脚GND传输至信号输入引脚Di和信号输出引脚Out；但是不能由驱动芯片12的信号输入引脚Di和信号输出引脚Out传输至接地引脚GND。这样，在驱动芯片12的信号输入引脚Di和信号输出引脚Out与接地引脚GND之间具有正向的(信号输入引脚Di和信号输出引脚Out的电势大于接地引脚GND的电势)电势差时，可能将驱动芯片12击穿(损毁)。
多条信号线30包括多条接地走线13，接地走线13用于与驱动芯片12的接地引脚GND电连接。
相关技术中，每个驱动芯片子组201的多个驱动芯片12与一条接地走线13电连接，不同的驱动芯片子组201连接的接地走线13不同且相互电绝缘。当其中一条接地走线13上产生静电时，静电可以传递至与该接地走线13电连接的多个驱动芯片12的接地引脚GND。示例性地，参阅图5，将上述多个 驱动芯片12所在的驱动芯片子组201称为第一驱动芯片子组201A，并将与第一驱动芯片子组201A级联的驱动芯片子组201称为第二驱动芯片子组201B。
静电可以传递至第二驱动芯片子组201B中与第一驱动芯片子组201A级联的驱动芯片12(下文称：目标驱动芯片12A)的引脚处(比如静电可以由第一驱动芯片子组201A的最后一级驱动芯片12的信号输出引脚Out，传递至第二驱动芯片子组201B的第一级驱动芯片12的信号输入引脚Di)。继而导致目标驱动芯片12A上与第一驱动芯片子组201A的驱动芯片12级联的引脚，与接地走线13(与目标驱动芯片12A电连接的接地走线13)之间出现电势差，在上述电势差的作用下，可能将目标驱动芯片12A击穿，导致与目标驱动芯片12A电连接的一组发光器件10发光异常。
示例性地，参阅图5，一个驱动芯片组20包括沿第二方向X分布的两个驱动芯片子组201，其中，两个驱动芯片子组201分别为第一驱动芯片子组201A和第二驱动芯片子组201B。第一驱动芯片子组201A与第一接地走线13A电连接，第二驱动芯片子组201B与第二接地走线13B电连接，且第一接地走线13A与第二接地走线13B电绝缘。当其中一条接地走线13(例如第一接地走线13A)上产生静电时，静电能够由驱动芯片12的接地引脚GND进入驱动芯片12，并沿路径L1和路径L2分别传递至上级驱动芯片12的信号输出引脚Out，及下级驱动芯片12的信号输入引脚Di。并由第一驱动芯片子组201A的最后一级驱动芯片12(图5中最上侧的驱动芯片12)沿路径L3传递至第二驱动芯片子组201B的第一级驱动芯片12A(目标驱动芯片12A)的信号输入引脚Di。目标驱动芯片12A的信号输入引脚Di，与第二接地走线13B之间具有电势差，该电势差可能将第二驱动芯片子组201B的第一级驱动芯片12击穿，进而导致与该第一级驱动芯片12电连接的一组发光器件10显示异常。
反之，当第二接地走线13B上产生静电时，会使第一驱动芯片子组201A中与第二驱动芯片子组201B级联的驱动芯片12(图5中第一驱动芯片子组201A的最上侧的驱动芯片12)与第一接地走线13A之间产生电势差，该电势差可能将第一驱动芯片子组201A中与第二驱动芯片子组201B级联的驱动芯片12击穿。
为了解决上述问题，本公开的一些实施例提供的发光基板110，参阅图3和图6，发光基板110包括多个驱动芯片组20、多条接地走线13和至少一条连接线14。
多个驱动芯片组20中的至少一个驱动芯片组20包括多个驱动芯片子组201，至少一个驱动芯片子组201包括级联的多个驱动芯片12；同一驱动芯片组20的多个驱动芯片子组201级联设置。即一个驱动芯片组20中的多个驱动芯片子组201所包括的所有驱动芯片12级联设置。同一驱动芯片子组201的多个驱动芯片12与同一条接地走线13电连接，且不同驱动芯片子组201所连接的接地走线13不同。
示例性地，参阅图3，图3仅示例性地展示了两个驱动芯片组20。两个驱动芯片组20中的每个驱动芯片组20均包括两个驱动芯片子组201。每个驱动芯片子组201包括级联的多个驱动芯片12。两个驱动芯片子组201所包括的所有驱动芯片12级联。
与同一驱动芯片组20的多个驱动芯片子组201所连接的多条接地走线13通过至少一条所述连接线14电连接。基于此，在其中一条接地走线13产生静电后，静电能够传递至与该接地走线13电连接的驱动芯片12，并通过该驱动芯片12传递至与之级联的驱动芯片12的引脚上；这样，与接地走线13电连接的驱动芯片12，以及与该驱动芯片12级联的驱动芯片12的引脚形成等电势体。
同一个驱动芯片子组201的多个驱动芯片12级联设置，同一个驱动芯片组20的多个驱动芯片子组201级联；即同一个驱动芯片组20所包含的全部驱动芯片12级联设置。与同一驱动芯片组20的多个驱动芯片子组201所连接的多条接地走线13通过至少一条连接线14电连接，即与相互级联的多个驱动芯片12电连接的多条接地走线14电连接。这样，与同一个驱动芯片组20的多个驱动芯片子组201电连接的多条接地走线13，以及同一个驱动芯片组20的所有驱动芯片12之间形成等电势体。进而降低驱动芯片12与其电连接的接地走线13之间形成电压差的风险，降低驱动芯片12被击穿的风险，提升发光基板110的信赖性。
示例性地，参与图6，图6为图3所示发光基板110的等效电路图。一个驱动芯片组20包括沿第二方向X分布的两个驱动芯片子组201，其中，两个驱动芯片子组201分别为第一驱动芯片子组201A和第二驱动芯片子组201B。第一驱动芯片子组201A与第一接地走线13A电连接，第二驱动芯片子组201B与第二接地走线13B电连接，且第一接地走线13A与第二接地走线13B通过至少一条连接线14电连接。
当其中一条接地走线13(例如第一接地走线13A)上产生静电时，静电能够传递至第二接地走线13B，使第一接地走线13A和第二接地走线13B形 成一个等电势体。然后由驱动芯片组20的多个驱动芯片12的接地引脚GND进入驱动芯片12，并穿过驱动芯片12传递至驱动芯片12的信号输入引脚Di和信号输出引脚Out。这样，驱动芯片12的信号输入引脚Di和信号输出引脚Out与接地引脚GND之间没有电势差，可以降低驱动芯片12被击穿的风险，提升发光基板110的信赖性。
在一些实施例中，参阅图3，发光基板110包括沿第一方向Y依次并排设置的发光区101、扇出区102和绑定区103。
多组发光器件10和多个驱动芯片组20均设置于发光区101内。扇出区102用于将多条信号线30引出至绑定区103，绑定区103上设有多个绑定引脚，绑定引脚用于与其他电子元器件(比如FPC、PCB和控制芯片等)电连接。
驱动芯片子组201的多个驱动芯片12大致沿第一方向Y排列，驱动芯片组20的多个驱动芯片子组201大致沿第二方向X排布，多个驱动芯片组20大致沿第二方向X排布。即：发光基板10所包括的全部驱动芯片12沿第一方向Y排列成列，多列驱动芯片12沿第二方向X分布，每列的多个驱动芯片12级联形成一个驱动芯片子组201，多列驱动芯片(多个驱动芯片子组201)级联形成一个驱动芯片组20。
其中，第一方向Y和第二方向X相互交叉。示例性地，第一方向Y和第二方向X相互垂直。
需要理解的是，发光基板10所包括的驱动芯片12还可以以其他形成排布。本公开的实施例仅以驱动芯片12呈矩阵式排布为例对本公开的实施例进行示例性地描述。
接地走线13大致沿第一方向Y延伸。比如，在发光区101内，接地走线13大致沿第一方向Y延伸，在扇出区102内，接地走线13可以与第一方向Y呈一定夹角。
沿第二方向X，接地走线13和驱动芯片子组201交替排布，这样，一个驱动芯片子组201的多个驱动芯片12与一条接地走线13电连接时，有利于接地走线13的空间排布，且便于接地走线13与驱动芯片子组201的多个驱动芯片12电连接。
在一些实施例中，驱动芯片子组201的多个驱动芯片12与相邻的一条接地走线13电连接。示例性地，参阅图3，驱动芯片子组201的多个驱动芯片12与其左侧的一条接地走线13电连接。
在一些实施例中，参阅图3、图7和图8。图7为在图3所示的发光基板 110的发光区101中的一个截面结构图，图8在图3所示的发光基板110的扇出区102中的一个截面结构图。发光基板110(多条信号线30)还包括多条第一电压信号线15、多条第二电压信号线16、多条寻址信号线17、多条寻址转接线18、和多条反馈信号线19。
多条第一电压信号线15中的至少一条第一电压信号线15大致沿第一方向Y延伸，且沿第二方向X，所述第一电压信号线15与所述接地走线13交替设置，一条所述第一电压信号线15与一个驱动芯片子组201对应。
示例性地，多条第一电压信号线15中的每一条第一电压信号线15均大致沿第一方向Y延伸。一条所述第一电压信号线15与一个驱动芯片子组201对应，即与一个驱动芯片子组201的多个驱动芯片12电连接的多组发光器件10与一条第一电压信号线15电连接。第一电压信号线15被配置为向发光器件10提供正极电压信号。
示例性地，参阅图3，第一电压信号线15和接地走线13位于同一层，第一电压信号线15和接地走线13沿第二方向X交替排布，且一条第一电压信号线15位于一条接地走线13远离驱动芯片子组201的一侧。
发光器件11还与驱动芯片12的信号输出引脚Out电连接，信号输出引脚Out被配置为向发光器件10输出负极电压信号，并向下级驱动芯片12输出寻址信号。通过驱动芯片12可以控制与该控制芯片12电连接的一组发光器件10是否发光，以及发光亮度等。
所述多条第一电压信号线15与所述多条接地走线13材料相同且同层设置。示例性地，参阅图7，所述多条第一电压信号线15与所述多条接地走线13采用铜制作形成，且均位于第一走线层22。
一条第二电压信号线16(比如可以是电源电压信号线)与一个驱动芯片子组201的多个驱动芯片12的所述电源引脚PWR电连接。第二电压信号线16被配置为向驱动芯片12提供电源电压信号。沿第二方向X，第二电压信号线16接地走线13交替排布。
在一些实施例中，第二电压信号线16与接地走线13材料相同且同层设置。示例性地，参阅图7，所述多条第一电压信号线15与所述多条接地走线13采用铜制作形成，且均位于第一走线层22。其中，图7中仅展示了其中一条第一电压信号线15和一条接地走线13。
一条寻址信号线17与一个驱动芯片组20中的多个驱动芯片12中的第一级驱动芯片12电连接。寻址信号线17被配置为向一个驱动芯片组20的多个驱动芯片12提供寻址信号(ADDR信号)。
级联的两个驱动芯片12中，上级驱动芯片12的信号输出引脚Out，与下级驱动芯片12的信号输入引脚Di通过一条寻址转接线18电连接。
一条反馈信号线18(也称：回流信号线FB)与一个驱动芯片组20的多个驱动芯片12中的最后一级驱动芯片12电连接。反馈信号线18被配置为将驱动芯片组20的回流信号输出。
在一些实施例中，在显示区101内，寻址信号线17、寻址转接线18、和反馈信号线19材料相同且同层设置。示例性地，参阅图7，寻址信号线17、寻址转接线18、和反馈信号线19采用铜制作形成，且均位于第二走线层24。其中，图7中仅示例性地展示了寻址转接线18。
在扇出区102和绑定区103内，寻址信号线17和反馈信号线19同层设置，且均位于第一走线层22内。这样，有利于将多条信号线30的多个绑定引脚设置于相同膜层，便于绑定引脚与其他电子元器件进行绑定连接。
示例性地，参阅图8，图8经示例性地展示了多条信号线30在扇出区30处的剖面视图。在扇出区102，接地走线13、第一电压信号线15、第二电压信号线16、寻址信号线17和反馈信号线19同层设置且均位于第一走线层。
需要说明的是，寻址转接线18用于将级联的两个驱动芯片12电连接，多个驱动芯片组20的多个驱动芯片12均设置于发光区101，因此，寻址转接线18仅设置于发光区101，或者部分设置于发光区101，部分设置于扇出区102靠近发光区101的边缘。
在一些实施例中，参阅图3和图9，图9为图3中D区域的局部放大图。接地走线13远离扇出区102的一端(图9中接地走线13沿第一方向Y的上端)超出第一电压信号线15远离扇出区102的端部(图9中第一电压信号线15沿第一方向Y的上端)。
至少一条连接线14包括位于第一电压信号线15远离扇出区102一侧的第一连接线141，第一连接线141与接地走线13远离扇出区102的端部电连接。这样，第一连接线141可以避开其他信号线(比如第一电压信号线15和第二电压信号线16、寻址转接线18等)，不影响其他信号线的布置，不需要调整其他信号线的制备工艺；而且可以降低第一连接线141与其他信号线之间的信号干扰。
在一些实施例中，第一连接线141和接地走线13材料相同且同层设置，这样，第一连接线141可以利用接地走线13的制备工序制作形成，发光基板110不需要增加额外的加工工序，有利于降低发光基板110的制作难度和制作成本。
第一连接线141与第一电压信号线15的远离扇出区102的端部之间具有间隙D1，这样，可以避免第一连接线141与第一电压信号线15之间发生短路。
在一些实施例中，上述第一连接线141与第一电压信号线15远离扇出区102的端部的间隙D1大于或等于200μm。这样，可以降低第一连接线14对第一电压信号线15造成信号干扰。示例性地，上述间隙D可以为200μm、250μm、300μm等，本公开的实施例不再一一列举。
需要理解的是，当第一电压信号线15的工作电压较大时，可以增加上述间隙D的大小，间隙D的具体值可以根据实际需要进行设置。间隙D1不是越大越好，间隙D1过大可能会导致发光基板110非发光区域的面积增加，不利于降低显示装置1000的边框宽度。
在一些实施例中，参阅图10和图11，图10为连接线14(第二连接线142)设置于发光区101内时的结构图。发光基板110包括衬底21、设置于衬底21上的第一走线层22、设置于第一走线层21远离衬底21一侧的第一绝缘层23、以及设置于第一绝缘层23远离衬底21一侧的第二走线层24。其中，第一绝缘层23中设置有多个第一过孔231。
至少一条连接线14包括位于第二走线层24的第二连接线142，第二连接线142在第一绝缘层23上的正投影与第一电压信号线15在第一绝缘层23上的正投影部分交叠。第二连接线142通过第一过孔231与接地走线13电连接。第二连接线142设置于发光区101内，有利于降低非发光区(发光区101远离扇出区的一侧)的宽度，有利于降低发光基板110的边框宽度，降低显示装置1000的边框宽度。第二连接线142设置于第二走线层24，能够避免与第一电压信号线15和第二电压信号线16发生短路，提升发光基板110的信赖性。
示例性地，一个驱动芯片组20包括两个驱动芯片子组201，每个驱动芯片子组201的多个驱动芯片12与一条接地走线13电连接。第二连接线142分别通过一个第一过孔231与两条接地走线13电连接。
示例性地，两条接地走线13之间可以通过一条、两条、或者更多第二连接线142电连接。
示例性地，驱动芯片组20包括三个或三个以上驱动芯片子组201时，可以每相邻两条接地走线13之间通过至少一条第二连接线142电连接。或者，也可以任意相邻多条接地走线13通过至少一条第二连接线142电连接。
在一些实施例中，参阅图10，接地走线13包括主体部131和连接部132， 主体部131沿第一方向Y延伸，连接部132被配置为将主体部131与驱动芯片12电连接。具体的，连接部132的一端与主体部131电连接，另一端与驱动芯片12的接地引脚GND电连接。
第二连接线142通过第一过孔231与连接部132电连接，且与第二连接线142电连接的连接部132的线宽D2大于不与第二连接线142电连接的连接部132的线宽D3。通过增加与第二连接线142电连接的连接部132的线宽，可以降低因第二连接线142电流过大，损坏与第二连接线142电连接的连接部132的风险，提升发光基板110的抗静电能力，提升发光基板110的信赖性。
在一些实施例中，参阅图12和图13，接地走线13包括位于扇出区102的第一引出段133，且第一引出段133位于第一走线层22。
发光基板110还包括绝缘图案40，绝缘图案40位于扇出区102，且至少覆盖第一引出段133的部分区域。至少一条连接线14包括位于扇出区102的第三连接线143，第三连接线143位于绝缘图案40远离衬底21一侧，且第三连接线143通过第二过孔41与第一引出段133电连接。
发光区101内包括数量较多的发光器件11、驱动芯片12以及多条信号线30，设置信号线的空间较小。因此，将第三连接线143设置于扇出区102内，可以降低第三连接线143对发光区101的多条信号线30的引线，第三连接线143的布线空间较大，且不影响其余信号线30的布置。
在一些实施例中，参阅图12，第三连接线143为网格状结构，这样，可以在不降低第三连接线143的电阻的前提下，降低第三连接线143对其他信号线30产生的信号干扰，提升发光基板110的信赖性。
在一些实施例中，绝缘图案40位于第一绝缘层23，第三连接线143位于第二走线层24。这样，可以利用既有的成膜工艺形成绝缘图案40和第三连接线143，有利于简化发光基板110的制作工艺，降低发光基板110的制作成本。
需要说明的是，绝缘图案40也可以形成于第二走线层24之后，即绝缘图案40与第一绝缘层23采用两次成膜工艺(比如包括涂覆、曝光、显影和刻蚀等工序)形成。此时，第三连接线143与第二走线层24也采用两侧成膜工艺制作形成。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种发光基板，包括：
    多个驱动芯片组，至少一个驱动芯片组包括多个驱动芯片子组，至少一个驱动芯片子组包括级联的多个驱动芯片；同一驱动芯片组的多个驱动芯片子组级联设置；
    多条接地走线，同一驱动芯片子组的多个驱动芯片与同一条接地走线电连接，且不同驱动芯片子组所连接的接地走线不同；
    至少一条连接线，与同一驱动芯片组的多个驱动芯片子组所连接的多条接地走线通过至少一条所述连接线电连接。
  2. 根据权利要求1所述的发光基板，还包括：
    多条第一电压信号线，至少一条第一电压信号线大致沿第一方向延伸，且沿第二方向，所述第一电压信号线与所述接地走线交替设置，一条所述第一电压信号线与一个驱动芯片子组对应；所述多条第一电压信号线与所述多条接地走线材料相同且同层设置；所述第一方向和所述第二方向相互交叉；
    其中，所述发光基板包括沿所述第一方向并排设置的发光区和扇出区，所述多个驱动芯片组位于所述发光区；
    所述接地走线远离所述扇出区的一端超出所述第一电压信号线远离所述扇出区的端部；
    所述至少一条连接线包括位于所述第一电压信号线远离所述扇出区一侧的第一连接线，所述第一连接线与所述接地走线远离所述扇出区的端部电连接。
  3. 根据权利要求2所述的发光基板，其中，所述第一连接线和所述接地走线材料相同且同层设置，且所述第一连接线与所述第一电压信号线的远离所述扇出区的端部之间具有间隙。
  4. 根据权利要求3所述的发光基板，其中，所述第一连接线与所述第一电压信号线之间的间隙大于或等于200μm。
  5. 根据权利要求1所述的发光基板，还包括：
    多条第一电压信号线，至少一条第一电压信号线大致沿第一方向延伸，且沿第二方向，所述第一电压信号线与所述接地走线交替设置，一条所述第一电压信号线与一个驱动芯片子组对应；所述第一方向和所述第二方向相互交叉；
    其中，所述发光基板包括依次层叠设置的衬底、第一走线层、第一绝缘层和第二走线层，所述多条接地走线和所述多条第一电压信号线位于所述第 一走线层，所述第一绝缘层中设有第一过孔；
    所述至少一条连接线包括位于所述第二走线层的第二连接线，所述第二连接线在所述第一绝缘层上的正投影与所述第一电压信号线在所述第一绝缘层上的正投影部分交叠；所述第二连接线通过所述第一过孔与所述接地走线电连接。
  6. 根据权利要求5所述的发光基板，其中，所述发光基板包括沿所述第一方向并排设置的发光区和扇出区，所述多个驱动芯片组位于所述发光区；
    所述接地走线包括主体部和连接部，所述主体部沿所述第一方向延伸，所述连接部将所述主体部与所述驱动芯片电连接；
    所述第二连接线通过所述第一过孔与所述连接部电连接，且与所述第二连接线电连接的连接部的线宽大于不与所述第二连接线电连接的连接部的线宽。
  7. 根据权利要求1所述的发光基板，其中，所述发光基板包括沿第一方向并排设置的发光区和扇出区，所述多个驱动芯片组位于所述发光区；
    所述发光基板包括衬底，设置于所述衬底上的第一走线层，设置于所述第一走线层远离所述衬底一侧的绝缘图案，所述绝缘图案中设有第二过孔；
    所述接地走线包括位于所述扇出区的第一引出段，且所述第一引出段位于所述第一走线层；
    所述至少一条连接线包括位于所述扇出区的第三连接线，所述第三连接线位于所述绝缘图案远离所述衬底一侧，且所述第三连接线通过所述第二过孔与所述第一引出段电连接。
  8. 根据权利要求7所述的发光基板，其中，所述第三连接线为网格状结构。
  9. 根据权利要求7或8所述的发光基板，其中，所述发光基板还包括设置于所述第一走线层远离所述衬底一侧的第一绝缘层，设置于所述第一绝缘层远离所述衬底一侧的第二走线层；
    所述绝缘图案位于所述第一绝缘层，所述第三连接线位于所述第二走线层。
  10. 根据权利要求1～9中任一项所述的发光基板，其中，
    所述驱动芯片子组的多个驱动芯片大致沿第一方向排列，所述驱动芯片组的多个驱动芯片子组大致沿第二方向排布，所述多个驱动芯片组大致沿所述第二方向排布；所述第一方向和所述第二方向相互交叉；
    所述接地走线大致沿所述第一方向延伸，且沿所述第二方向，所述接地 走线和所述驱动芯片子组交替排布，所述驱动芯片子组的多个驱动芯片与相邻的一条所述接地走线电连接。
  11. 根据权利要求10所述的发光基板，其中，同一驱动芯片组的任意相邻两个驱动芯片子组中，其中一个驱动芯片子组的最后一级驱动芯片与另外一个驱动芯片子组的第一级驱动芯片电连接。
  12. 根据权利要求1～11中任一项所述的发光基板，其中，所述驱动芯片包括信号输入引脚、信号输出引脚、接地引脚、及电源引脚；
    所述发光基板还包括：
    多组发光器件，至少一组包括多个发光器件，同一组的多个发光器件与同一个所述驱动芯片的信号输出引脚电连接；
    多条第一电压信号线，与一个驱动芯片子组的多个驱动芯片电连接的多组发光器件与一条第一电压信号线电连接；
    多条第二电压信号线，一条第二电压信号线与一个驱动芯片子组的多个驱动芯片的所述电源引脚电连接；
    多条寻址信号线，一条寻址信号线与一个驱动芯片组中的多个驱动芯片中的第一级驱动芯片电连接；
    多条寻址转接线，级联的两个驱动芯片中，上级驱动芯片的信号输出引脚，与下级驱动芯片的信号输入引脚通过一条寻址转接线电连接；
    多条反馈信号线，一条反馈信号线与一个驱动芯片组的多个驱动芯片中的最后一级驱动芯片电连接。
  13. 一种背光模组，包括如权利要求1～12中任一项所述的发光基板。
  14. 一种显示装置，包括：
    显示面板；
    如权利要求13所述的背光模组，设置于所述显示面板的背光侧。
PCT/CN2022/077474 2022-02-23 2022-02-23 发光基板、背光模组及显示装置 WO2023159393A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
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US20050184403A1 (en) * 2004-02-24 2005-08-25 Canon Kabushiki Kaisha Semiconductor integrated circuit device
US20090207633A1 (en) * 2008-02-15 2009-08-20 Ye Byoung-Dae Backlight Unit and Display Including the Same
CN105806851A (zh) * 2016-05-20 2016-07-27 无锡研奥电子科技有限公司 基于数字信号处理器的自动检测系统及其控制方法
CN110764639A (zh) * 2018-07-27 2020-02-07 京东方科技集团股份有限公司 功能面板及其制造方法、终端
CN113870770A (zh) * 2021-09-26 2021-12-31 合肥京东方瑞晟科技有限公司 驱动芯片、显示面板及显示装置

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US20050184403A1 (en) * 2004-02-24 2005-08-25 Canon Kabushiki Kaisha Semiconductor integrated circuit device
US20090207633A1 (en) * 2008-02-15 2009-08-20 Ye Byoung-Dae Backlight Unit and Display Including the Same
CN105806851A (zh) * 2016-05-20 2016-07-27 无锡研奥电子科技有限公司 基于数字信号处理器的自动检测系统及其控制方法
CN110764639A (zh) * 2018-07-27 2020-02-07 京东方科技集团股份有限公司 功能面板及其制造方法、终端
CN113870770A (zh) * 2021-09-26 2021-12-31 合肥京东方瑞晟科技有限公司 驱动芯片、显示面板及显示装置

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