WO2020238063A1 - 阵列基板及阵列基板母板 - Google Patents

阵列基板及阵列基板母板 Download PDF

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Publication number
WO2020238063A1
WO2020238063A1 PCT/CN2019/118327 CN2019118327W WO2020238063A1 WO 2020238063 A1 WO2020238063 A1 WO 2020238063A1 CN 2019118327 W CN2019118327 W CN 2019118327W WO 2020238063 A1 WO2020238063 A1 WO 2020238063A1
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Prior art keywords
array substrate
shorting
display area
metal structure
array
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Application number
PCT/CN2019/118327
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English (en)
French (fr)
Inventor
刘权
秦旭
李威龙
张露
胡思明
韩珍珍
Original Assignee
昆山国显光电有限公司
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Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Publication of WO2020238063A1 publication Critical patent/WO2020238063A1/zh
Priority to US17/358,419 priority Critical patent/US11961846B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • This application relates to the field of display, in particular to an array substrate and an array substrate mother board.
  • the array substrate needs to be prepared, and during multiple manufacturing processes of the array substrate, static electricity is usually generated on the array substrate.
  • the presence of static electricity will affect the subsequent manufacturing process of the array substrate, thereby reducing the manufacturing yield of the array substrate and the display panel.
  • the existing treatment method for generating static electricity on the array substrate is to disperse the static electricity on the array substrate through a short-circuit component.
  • the existing short-circuit component adopts a semiconductor structure, which has a large impedance, so that the accumulated charges on the array substrate cannot be quickly conducted and dispersed. There are still problems caused by static electricity.
  • the present application provides an array substrate and an array substrate mother board to improve the static electricity dispersion capability of the array substrate and the array substrate mother board.
  • an embodiment of the present application provides an array substrate having a display area and a non-display area located on the periphery of the display area.
  • the non-display area is provided with an interface area.
  • the array substrate includes: a plurality of signal lines extending in the display area and leading to Non-display area; multiple pads located in the interface area, each of the multiple pads is connected to a corresponding one of the multiple signal lines; and short-circuit components located in the non-display area, the short-circuit components are connected to multiple pads , The multiple signal lines connected to the multiple pads are short-circuited, wherein the short-circuit assembly includes a patterned first metal structure.
  • the array substrate includes a plurality of pixel circuits arranged in the display area, each of the plurality of pixel circuits is connected to at least one of the plurality of signal lines, and the plurality of pixel circuits include gate conductors.
  • the material of the first metal structure is the same as the material of the gate conductor.
  • the first metal structure and the gate conductor are provided in the same layer.
  • each of the plurality of pads includes a first pad unit and a second pad unit arranged at intervals in the first direction, the first pad unit and a plurality of signals The corresponding one of the lines is connected, the second pad unit is connected to the shorting assembly, the first pad unit and the second pad unit are both connected to the interconnection block through the via hole, so that the first pad unit and the second pad The unit is electrically connected.
  • the array substrate includes a plurality of pixel circuits arranged in the display area, each of the plurality of pixel circuits is connected to at least one of the plurality of signal lines, and the plurality of pixel circuits include:
  • the material of the source layer and the interconnect block is the same as the material of the active layer.
  • the interconnection block and the active layer are arranged in the same layer.
  • the shorting assembly further includes a patterned semiconductor structure, and the orthographic projection of the semiconductor structure in the thickness direction of the array substrate coincides with the orthographic projection of the first metal structure in the thickness direction of the array substrate.
  • an insulating layer is provided between the first metal structure and the semiconductor structure.
  • the array substrate includes a plurality of pixel circuits arranged in the display area, each of the plurality of pixel circuits is connected to at least one of the plurality of signal lines, and the plurality of pixel circuits include:
  • the source layer, the semiconductor structure and the active layer are made of the same material.
  • the semiconductor structure and the active layer are arranged in the same layer.
  • the shorting assembly includes: a shorting bar; and a plurality of connecting wires, and each of the plurality of pads is connected to the shorting bar through a corresponding one of the plurality of connecting wires.
  • the array substrate further includes: a protective layer, which covers the shorting component.
  • a channel is provided on the protective layer, the channel penetrates from the surface of the protective layer to the first metal structure, and the channel intersects a plurality of connecting lines.
  • an embodiment of the present application provides an array substrate mother board.
  • the array substrate mother board includes a plurality of array substrates according to any one of the foregoing embodiments, and the plurality of array substrates are arranged in an array.
  • the plurality of array substrates are arranged in multiple rows, each row is arranged with a plurality of array substrates, the array substrate mother board further includes a shorting interconnection assembly, and the shorting interconnection assembly includes a first An interconnection unit and a second interconnection unit.
  • the first interconnection unit is serially connected to a plurality of array substrates in the same row, and the second interconnection unit is connected in parallel to at least two rows of the multiple array substrates.
  • the shorting interconnection assembly includes a patterned second metal structure, and the second metal structure can be connected to the first metal structure through a via hole.
  • the multiple pads in the interface area can be short-circuited by the short-circuiting component, so that multiple signal lines connected to the multiple pads are short-circuited.
  • the electrostatic charge can be dispersed on the entire array substrate through the shorting component.
  • the shorting component can be connected to a stable voltage source, so that the charge on the array substrate can be conducted and eliminated through the shorting component.
  • the shorting component includes a patterned first metal structure. Compared with the shorting component of the semiconductor structure, the impedance between the connected pads can be greatly reduced, and the static electricity can be generated more quickly Disperse the charge to avoid problems such as electrostatic shock caused by static electricity or product defects caused by static electricity.
  • the pads include a first pad unit and a second pad unit that are arranged at intervals and are electrically connected to each other through an interconnection block, so that the shorting assembly can still pass through the pads and multiple signal lines. Connect to short-circuit multiple signal wires. Since the first pad unit and the second pad unit are spaced apart, and the second pad unit is connected to the shorting assembly, when external moisture or the like corrodes the pad, the corroded part will be cut off between the first pad unit and the second pad unit. The gap between the two pad units prevents water vapor corrosion from further invading the first pad unit connected to the signal line, and improves the corrosion resistance of the pads in the interface area of the array substrate.
  • the shorting component on each array substrate includes a patterned first metal structure.
  • the impedance between the connected pads can be greatly reduced. After static electricity is generated, the charge can be dispersed more quickly, avoiding electrostatic shock caused by static electricity and product manufacturing defects.
  • the array substrate mother board further includes a shorting interconnection assembly, which connects at least part of the shorting assembly of the array substrate on the array substrate mother board to each other, thereby realizing the array substrate mother board
  • the electrostatic dispersion on the multiple array substrates further increases the electrostatic dispersion capability of the array substrate mother board.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • Figure 2 is a schematic cross-sectional view taken along the E-E direction in Figure 1;
  • FIG. 3 is a schematic structural diagram of an array substrate mother board provided by an embodiment of the present application.
  • Fig. 4 is a schematic cross-sectional view in the direction of F-F in Fig. 3.
  • An embodiment of the application provides an array substrate, which may be an array substrate of an organic light-emitting diode (OLED) display panel, or may be a liquid crystal display (LCD) or micro light-emitting diode (Micro-LED) and other display panel array substrates.
  • OLED organic light-emitting diode
  • LCD liquid crystal display
  • Micro-LED micro light-emitting diode
  • array substrate can refer to a finished array substrate that has completed all the manufacturing processes of the array section, or can refer to a semi-finished array substrate at any process stage of the array section.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present application
  • FIG. 2 is a schematic cross-sectional view taken along the E-E direction in FIG. 1.
  • the array substrate 100 of the embodiment of the present application has a display area AA and a non-display area NA located on the periphery of the display area AA, and the non-display area NA is provided with an interface area BD.
  • the array substrate 100 may include a plurality of signal lines 110, a plurality of pads 120, and a plurality of shorting components 130. Among them, a plurality of signal lines 110 extend in the display area AA and lead to the non-display area NA. In some embodiments, the array substrate 100 further includes a plurality of pixel circuits arranged in the display area AA. Each pixel circuit corresponds to a pixel of the display panel. Taking the pixel as an OLED pixel as an example, each pixel circuit is used to drive the corresponding pixel circuit. The pixels emit light. The multiple pixel circuits are arranged in a predetermined pattern in the display area AA of the array substrate 100, and each pixel circuit can be connected to at least one of the multiple signal lines 110.
  • the array substrate 100 may include multiple scan lines and multiple data lines.
  • the multiple scan lines may extend in the same direction and are spaced apart from each other.
  • the multiple data lines may also extend in the same direction and are spaced apart from each other.
  • the extension direction of the scan lines is the same as that of the data lines.
  • the extension direction crosses.
  • Each pixel circuit is connected to a scan line and a data line.
  • the scan line can provide a switching signal to the pixel circuit
  • the data line can provide a grayscale signal to the pixel circuit.
  • the multiple signal lines 110 may be the aforementioned multiple scan lines; in other embodiments, the multiple signal lines 110 may be the aforementioned multiple data lines.
  • the interface area BD can be used to connect with an external circuit board.
  • the external circuit board is a flexible printed circuit (FPC), on which a driver chip and a control chip can be provided.
  • FPC flexible printed circuit
  • the plurality of pads 120 are located in the interface area BD, and each of the plurality of pads 120 is connected to a corresponding one of the plurality of signal lines 110. In some embodiments, at least part of the plurality of signal lines 110 are correspondingly connected to the plurality of pads 120.
  • the plurality of bonding pads 120 may be electrically connected with an external circuit board, for example, by bonding to a circuit on the FPC, so as to achieve electrical connection between the signal line 110 and the driving chip on the FPC.
  • the shorting component 130 is located in the non-display area NA, and the shorting component 130 is connected to the multiple pads 120 so that the multiple signal lines 110 connected to the multiple pads 120 are shorted.
  • the shorting assembly 130 includes a patterned first metal structure 130a.
  • the multiple pads 120 of the interface area BD can be short-circuited by the shorting component 130, so that the multiple signal lines 110 connected to the multiple pads 120 are short-circuited.
  • the shorting assembly 130 can disperse the electrostatic charge on the entire array substrate 100.
  • the shorting component 130 may be connected to a stable voltage source, so that the charge on the array substrate 100 can be conducted and eliminated through the shorting component 130.
  • the shorting component 130 includes a patterned first metal structure 130a. Compared with the shorting component of a semiconductor structure, the impedance between the interconnected pads 120 can be greatly reduced. After static electricity is generated It can disperse the charge more quickly and avoid problems such as electrostatic damage or product defects caused by static electricity.
  • the pixel circuit includes transistors. According to different designs of the pixel circuit, the number of transistors included in each pixel circuit can be adjusted and changed according to its specific design.
  • the pixel circuit may include an active layer for forming a source electrode and a drain electrode, and a gate conductor arranged above the channel of the active layer, and the gate conductor is insulated from the active layer.
  • the gate conductor can be made by patterning using metal materials such as molybdenum (Mo).
  • the material of the first metal structure 130a is the same as the material of the gate conductor; in some embodiments, the first metal structure 130a and the gate conductor are arranged in the same layer, so that the first metal structure 130a can be the same as the gate conductor.
  • the conductors are formed at the same time during the same patterning process, so that the shorting assembly 130 with lower impedance is provided without increasing the manufacturing process of the array substrate, which improves the anti-static performance and saves the production cost.
  • the shorting assembly 130 further includes a patterned semiconductor structure 130b, the orthographic projection of the semiconductor structure 130b in the thickness direction of the array substrate 100 and the first metal structure 130a in the thickness direction of the array substrate 100 The orthographic projections coincide.
  • the array substrate 100 in the non-display area NA of the array substrate 100, includes a substrate 190.
  • the substrate 190 may be glass or a polymer substrate such as a polyimide (PI) film. Or a substrate containing polymer materials such as PI.
  • PI polyimide
  • the semiconductor structure 130b is located on the substrate 190.
  • a buffer layer may be provided between the semiconductor structure 130b and the substrate 190.
  • the buffer layer may be an oxide layer or a nitride layer, for example made of silicon nitride. .
  • the first metal structure 130a is located on the semiconductor structure 130b.
  • an insulating layer 180 may be provided between the first metal structure 130a and the semiconductor structure 130b.
  • the insulating layer 180 may be an oxide layer or a nitride layer, for example, Made of silicon nitride.
  • the orthographic projection of the semiconductor structure 130b in the thickness direction of the array substrate 100 coincides with the orthographic projection of the first metal structure 130a in the thickness direction of the array substrate 100. That is, the shorting assembly 130 includes a stacked semiconductor structure in its layer structure dimension. 130b and the first metal structure 130a have the same structure in a plane dimension perpendicular to the thickness direction of the array substrate 100.
  • the pixel circuit may include an active layer, which may be polycrystalline silicon (PSi), amorphous silicon ( ⁇ -Si), low temperature polysilicon (low temperature polysilicon). -silicon, LTPS) and other semiconductor materials.
  • the material of the patterned semiconductor structure 130b can be the same as the material of the active layer, and the semiconductor structure 130b can be arranged in the same layer as the active layer, so that the two can be formed in the same patterning process, saving process.
  • the shorting assembly 130 includes a laminated first metal structure 130a and a semiconductor structure 130b. In some other embodiments, the shorting assembly 130 may only include the first metal structure 130a.
  • the pad 120 includes a first pad unit 121 and a second pad unit 122 arranged at intervals in the first direction X.
  • the first pad unit 121 is connected to a corresponding one of the plurality of signal lines 110, and the second pad unit 122 is connected to the short circuit assembly 130.
  • the array substrate is rectangular, and the first direction X is, for example, parallel to the length direction of the array substrate.
  • a gap 123 is formed between the first pad unit 121 and the second pad unit 122. Both the first pad unit 121 and the second pad unit 122 are connected to the interconnection block 140 through via holes, so that the first pad unit 121 and the second pad unit 122 are electrically connected.
  • the pad 120 includes the first pad unit 121 and the second pad unit 122 that are arranged at intervals and are electrically connected to each other through the interconnection block 140, so that the shorting assembly 130 can still be connected to multiple pads through the pad 120.
  • the signal line 110 is connected to short-circuit a plurality of signal lines 110. Since the first pad unit 121 and the second pad unit 122 are spaced apart, when external moisture or the like corrodes the pad 120, the corroded part will be cut off between the first pad unit 121 and the second pad unit 122.
  • the gap 123 prevents water vapor corrosion from further invading the first pad unit 121 connected to the signal line 110, and improves the corrosion resistance of the BD pad 120 in the interface area of the array substrate 100.
  • the material of the interconnection block 140 is the same as the material of the active layer of the pixel circuit; the interconnection block 140 can be arranged in the same layer as the active layer of the pixel circuit.
  • the interconnection block 140, the semiconductor structure 130b of the shorting assembly 130, and the active layer of the pixel circuit are arranged in the same layer, so that they can be formed in the same patterning process, saving process.
  • the interconnection block 140 may also be made of other conductive materials. In some other embodiments, the interconnection block 140 can be arranged in the same layer as a certain metal layer of the array substrate 100 and can be formed in the same patterning process.
  • the shorting assembly 130 includes a shorting rod 131 and a plurality of connecting wires 132.
  • the shorting bar 131 may be a strip-shaped conductor structure extending in a predetermined direction. In this embodiment, the shorting bar 131 extends in the second direction Y.
  • Each pad 120 is connected to the shorting bar 131 through a corresponding connecting wire 132. Every two adjacent pads 120 are sequentially electrically connected by a connecting wire 132, a shorting bar 131, and a connecting wire 132.
  • the resistance in the electrical connection structure between two adjacent pads 120 is less than 50 ohms. .
  • the multiple connecting lines 132 can be cut off by physical cutting or the like, so that the multiple bonding pads 120 are independent of each other and are no longer shorted by the shorting assembly 130.
  • the extending direction of the dividing line for cutting off the plurality of connecting lines 132 is shown by the line L-L.
  • the multiple connecting lines 132 all extend along the first direction X, the second direction Y crosses the first direction X, and the dividing line extends along the second direction Y and intersects all the connecting lines 132.
  • the array substrate 100 further includes a protective layer 150, and the protective layer 150 covers the shorting assembly 130.
  • the protective layer 150 covers the first metal structure 130 a of the shorting assembly 130.
  • a channel 151 is provided on the protective layer 150, and the channel 151 penetrates from the surface of the protective layer 150 to the first metal structure 130a, so that the first metal structure 130a is exposed at the channel 151.
  • the location and extension direction of the channel 151 correspond to the location and extension direction of the aforementioned dividing line, so that the channel 151 intersects with a plurality of connecting lines 132.
  • the dividing device divides the array substrate 100 along the groove 151, so that the above-mentioned multiple connecting lines 132 can be cut off.
  • the embodiments of the present application also provide an array substrate mother board.
  • the array substrate mother board may include a plurality of array substrates arranged in an array.
  • the array substrate may be the array substrate of any one of the above embodiments.
  • the array substrate will be used as The array substrate 100 provided in the above embodiment of the present application is taken as an example for description.
  • FIG. 3 is a schematic structural diagram of an array substrate mother board provided according to an embodiment of the present application, and FIG. 4 shows a schematic cross-sectional view in the direction F-F in FIG. 3.
  • a plurality of array substrates 100 are arranged in multiple rows, and a plurality of array substrates 100 are arranged in each row.
  • the arrangement and the number of array substrates 100 in FIG. 3 are merely illustrative. In an arrangement formed by multiple array substrates 100, the number of rows of array substrates 100 and the number of array substrates 100 in each row can be set according to actual needs.
  • the interface area BD of each array substrate 100 included therein has a plurality of pads 120, and the plurality of pads 120 can be short-circuited by the shorting assembly 130, thereby making The multiple signal lines 110 connected to the pad 120 are short-circuited.
  • the shorting assembly 130 can disperse the electrostatic charge on the entire array substrate 100.
  • the shorting component 130 may be connected to a stable voltage source, so that the charge on the array substrate 100 can be conducted and eliminated through the shorting component 130.
  • the shorting component 130 includes a patterned first metal structure 130a. Compared with the shorting component of a semiconductor structure, the impedance between the interconnected pads 120 can be greatly reduced. After static electricity is generated It can disperse the charge more quickly, and avoid problems such as electrostatic damage caused by static electricity and product defects caused by static electricity.
  • the array substrate mother board 1000 further includes a short interconnection assembly 200.
  • the shorting interconnection assembly 200 can connect at least a part of the shorting assembly 130 of the array substrate 100 on the array substrate mother board 1000 to each other.
  • the short-circuit interconnection assembly 200 includes a first interconnection unit 210 and a second interconnection unit 220.
  • the first interconnection unit 210 is connected in series with a plurality of array substrates 100 in the same line, and the second interconnection unit 220 is connected in parallel with at least two rows of the array substrates 100 in a plurality of rows.
  • the short-circuit interconnection assembly 200 connects the short-circuit assemblies 130 of all the array substrates 100 on the array substrate mother board 1000 to each other, so as to realize the electrostatic dispersion on all the array substrates 100 on the array substrate mother board 1000 and further increase the array substrate The electrostatic dispersion capability of the motherboard 1000.
  • the shorting interconnection assembly 200 can connect a part of the shorting assembly 130 of the array substrate 100 on the array substrate mother board 1000 to each other, and the static electricity on the plurality of array substrates 100 connected to each other is dispersed.
  • the short-circuit interconnection assembly 200 is provided with a connection terminal 300, and the short-circuit interconnection assembly 200 can be connected to a stable voltage source through the connection terminal 300, so that the array substrate 1000 on the multiple array substrates 100 The electric charge of the battery can be conducted and eliminated through the short-circuit assembly 130, the short-circuit interconnect assembly 200, and the connection terminal 300.
  • the shorting interconnection assembly 200 includes a patterned second metal structure 200a, and the second metal structure 200a can be connected to the first metal structure 130a through a via hole.
  • the first metal structure 130 a at the right end is a part of the structure of the first interconnect unit 210
  • the first metal structure 130 a at the left end is a part of the structure of the second interconnect unit 220.
  • the second metal structure 200a can be arranged in the same layer as a certain metal layer of the array substrate 100 and can be formed in the same patterning process to save process.

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Abstract

一种阵列基板(100)及阵列基板母板(1000)，阵列基板(100)具有显示区(AA)以及位于显示区(AA)外周的非显示区(NA)，非显示区(NA)设有接口区(BD)，阵列基板(100)包括：多条信号线(110)，延伸于显示区(AA)并引出至非显示区(NA)；多个焊盘(120)，位于接口区(BD)，多个焊盘(120)中的每个连接多条信号线(110)中的对应一条；以及短接组件(130)，位于非显示区(NA)，短接组件(130)与多个焊盘(120)连接，使得多个焊盘(120)连接的多条信号线(110)短接，其中，短接组件(130)包括图案化的第一金属结构(130a)。该阵列基板能够避免由于静电引起的静电击伤或产品缺陷等问题。

Description

阵列基板及阵列基板母板
相关申请的交叉引用
本申请要求2019年5月28日提交的、申请号为201910452389.6、申请名称为“阵列基板及阵列基板母板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示领域，具体涉及一种阵列基板及阵列基板母板。
背景技术
显示面板制作过程中，需要进行阵列基板的制备，而在阵列基板的多个制程中，通常会在阵列基板上产生静电。静电的存在会对阵列基板的后续制程产生影响，从而降低阵列基板以及显示面板的制作良率。
现有的对阵列基板产生静电的处理方式为通过短路组件分散阵列基板上的静电，然而现有的短路组件采用半导体结构，其阻抗较大，使得阵列基板上的积累的电荷无法快速传导分散，仍然存在静电引起的问题。
发明内容
本申请提供一种阵列基板及阵列基板母板，提高阵列基板及阵列基板母板的静电分散能力。
一方面，本申请实施例提供一种阵列基板，具有显示区以及位于显示区外周的非显示区，非显示区设有接口区，阵列基板包括：多条信号线，延伸于显示区并引出至非显示区；多个焊盘，位于接口区，多个焊盘中的每个连接多条信号线中的对应一条；以及短接组件，位于非显示区，短接组件与多个焊盘连接，使得多个焊盘连接的多条信号线短接，其中，短接组件包括图案化的第一金属结构。
根据本申请一方面的前述实施方式，阵列基板包括设置于显示区的多个像素电路，多个像素电路中的每个与多条信号线中的至少一条连接，多个像素电路包括栅极导体，第一金属结构的材质与栅极导体的材质相同。
根据本申请一方面的前述任一实施方式，第一金属结构与栅极导体同层设置。
根据本申请一方面的前述任一实施方式，多个焊盘中的每个包括在第一方向上间隔排列的第一焊盘单元、第二焊盘单元，第一焊盘单元与多条信号线中的对应一条连接，第二焊盘单元与短接组件连接，第一焊盘单元、第二焊盘单元均通过过孔连接至互连块，使得第一焊盘单元与第二焊盘单元电连接。
根据本申请一方面的前述任一实施方式，阵列基板包括设置于显示区的多个像素电路，多个像素电路中的每个与多条信号线中的至少一条连接，多个像素电路包括有源层，互连块的材质与有源层的材质相同。
根据本申请一方面的前述任一实施方式，互连块与有源层同层设置。
根据本申请一方面的前述任一实施方式，短接组件还包括图案化的半导体结构，半导体结构在阵列基板厚度方向上的正投影与第一金属结构在阵列基板厚度方向上的正投影重合。
根据本申请一方面的前述任一实施方式，第一金属结构与半导体结构之间设置有绝缘层。
根据本申请一方面的前述任一实施方式，阵列基板包括设置于显示区的多个像素电路，多个像素电路中的每个与多条信号线中的至少一条连接，多个像素电路包括有源层，半导体结构与有源层的材质相同。
根据本申请一方面的前述任一实施方式，半导体结构与所述有源层同层设置。
根据本申请一方面的前述任一实施方式，短接组件包括：短接棒；以及多条连接线，多个焊盘中的每个通过多条连接线中的对应一条与短路棒连接。
根据本申请一方面的前述任一实施方式，阵列基板还包括：保护层，保护层覆盖短接组件。
根据本申请一方面的前述任一实施方式，保护层上设有槽道，槽道从保护层的表面贯穿至第一金属结构，槽道与多条连接线相交设置。
另一方面，本申请实施例提供一种阵列基板母板，该阵列基板母板包括多个根据上述任一实施方式的阵列基板，多个阵列基板阵列排布。
根据本申请另一方面的前述实施方式，多个阵列基板排布为多行，每行排布有多个阵列基板，阵列基板母板还包括短接互连组件，短接互连组件包括第一互连单元和第二互连单元，第一互连单元串接同行的多个阵列基板，第二互连单元并接多行阵列基板中的至少两行。
根据本申请另一方面的前述任一实施方式，短接互连组件包括图案化的第二金属结构，第二金属结构能够通过过孔与第一金属结构连接。
根据本申请实施例的阵列基板，其接口区的多个焊盘能够通过短接组件短接，进而使得多个焊盘连接的多条信号线短接。当阵列基板上某个局部产生静电电荷时，能够通过该短接组件将静电电荷分散在整个阵列基板上。短接组件可以连接至稳定电压源，使得阵列基板上的电荷能够通过短接组件传导和消除。在本申请实施例的阵列基板中，短接组件包括图案化的第一金属结构，相对于半导体结构的短接组件，能够大大降低所连接的焊盘间的阻抗，静电产生后能够更快速地分散电荷，避免由于静电引起的静电击伤或静电引起的产品缺陷等问题。
在一些可选的实施方式中，焊盘包括相互间隔排列且通过互连块相互电连接的第一焊盘单元、第二焊盘单元，使得短接组件仍然能够通过焊盘与多条信号线连接以将多条信号线短接。由于第一焊盘单元与第二焊盘单元间隔设置，其中第二焊盘单元与短接组件连接，当外界水汽等对焊盘产生腐蚀时，腐蚀部分会截止在第一焊盘单元与第二焊盘单元之间的间隙处，从而避免水汽腐蚀进一步侵入与信号线连接的第一焊盘单元，提高阵列基板接口区焊盘的防腐蚀性能。
根据本申请实施例的阵列基板母板，每个阵列基板上的短接组件包括图案化的第一金属结构，相对于半导体结构的短接组件，能够大大降低相连接的焊盘间的阻抗，静电产生后能够更快速地分散电荷，避免由于静电引起的静电击伤、产品制备缺陷等问题。
在一些可选的实施方式中，阵列基板母板还包括短接互连组件，短接互连组件将阵列基板母板上的至少部分阵列基板的短接组件互相连接，从而实现阵列基板母板上多个阵列基板上的静电分散，进一步增加阵列基板母板的静电分散能力。
附图说明
通过阅读以下参照附图对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显，其中，相同或相似的附图标记表示相同或相似的特征，附图并未按照实际的比例绘制。
图1是本申请一种实施例提供的阵列基板的结构示意图；
图2是图1中E-E向的剖面示意图；
图3是本申请一种实施例提供的阵列基板母板的结构示意图；
图4是图3中F-F向的剖面示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及具体实施例，对本申请进行进一步详细描述。应理解，此处所描述的具体实施例仅被配置为解释本申请，并不被配置为限定本申请。对于本领域技术人员来说，本申请可以在不需要这些具体细节中的一些细节的情况下实施。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。
应当理解，在描述部件的结构时，当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时，可以指直接位于另一层、另一个区域上面，或者在其与另一层、另一个区域之间还包含其它的层或区域。并且，如果将部件翻转，该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。
本申请实施例提供一种阵列基板，该阵列基板可以是有机发光二极管 (Organic Light-Emitting Diode，OLED)显示面板的阵列基板，也可以是液晶显示面板(Liquid Crystal Display，LCD)、微发光二极管(Micro-LED)等显示面板的阵列基板。本文中，术语“阵列基板”可以指完成全部阵列段制程的成品阵列基板，也可以指在阵列段的任意制程阶段时的半成品阵列基板。
图1是本申请一种实施例提供的阵列基板的结构示意图，图2是图1中E-E向的剖面示意图。本申请实施例的阵列基板100具有显示区AA以及位于显示区AA外周的非显示区NA，非显示区NA设有接口区BD。
阵列基板100可以包括多条信号线110、多个焊盘120以及多个短接组件130。其中，多条信号线110延伸于显示区AA并引出至非显示区NA。在一些实施例中，阵列基板100还包括设置于显示区AA的多个像素电路，每个像素电路与显示面板的一个像素对应，以像素是OLED像素为例，每个像素电路用于驱动对应像素发光。多个像素电路在阵列基板100的显示区AA呈预定规律排布，每个像素电路可以与多条信号线110中的至少一条连接。
阵列基板100可以包括多条扫描线以及多条数据线，多条扫描线可以同向延伸并且相互间隔设置，多个数据线也可以同向延伸并且相互间隔设置，扫描线的延伸方向与数据线的延伸方向交叉。每个像素电路连接至一条扫描线和一条数据线，扫描线可以向像素电路提供开关信号，数据线可以向像素电路提供灰阶信号。
在一些实施例中，多条信号线110可以是上述的多条扫描线；在另外一些实施例中，多条信号线110可以是上述的多条数据线。
接口区BD可以用于与外界电路板连接，在一些实施例中，该外界电路板为柔性电路板(Flexible Printed Circuit，FPC)，其上可以设置驱动芯片以及控制芯片。
多个焊盘120位于接口区BD，多个焊盘120中的每个连接多条信号线110中的对应一条。在一些实施例中，多个信号线110中的至少部分对应连接至多个焊盘120。多个焊盘120可以与外界电路板电连接，例如是通过键合绑定(bonding)的方式与FPC上的电路电连接，从而实现信号线 110与FPC上的驱动芯片的电连接。
短接组件130位于非显示区NA，该短接组件130与多个焊盘120连接，使得多个焊盘120连接的多条信号线110短接。其中，如图2，在本实施例中，短接组件130包括图案化的第一金属结构130a。
根据本申请实施例的阵列基板100，其接口区BD的多个焊盘120能够通过短接组件130短接，进而使得多个焊盘120连接的多条信号线110短接。当阵列基板100上某个局部产生静电电荷时，能够通过该短接组件130将静电电荷分散在整个阵列基板100上。
短接组件130可以连接至稳定电压源，使得阵列基板100上的电荷能够通过短接组件130传导和消除。在本申请实施例的阵列基板100中，短接组件130包括图案化的第一金属结构130a，相对于半导体结构的短接组件，能够大大降低相互连接的焊盘120间的阻抗，静电产生后能够更快速地分散电荷，避免由于静电引起的静电击伤或静电引起的产品缺陷等问题。
在一些实施例中，像素电路包括有晶体管，根据像素电路的不同设计，每个像素电路包括的晶体管的数量随其具体设计可以调整变化。其中，像素电路可以包括用于形成源极、漏极的有源层，以及设置在该有源层沟道上方的栅极导体，栅极导体与有源层绝缘设置。
栅极导体可以采用钼(Mo)等金属材料通过图案化制成。在一些实施例中，第一金属结构130a的材质与栅极导体的材质相同；在一些实施例中，第一金属结构130a与栅极导体同层设置，使得第一金属结构130a可以与栅极导体在同一图案化过程中同时形成，从而在未增加阵列基板的制作工序的情况下提供阻抗更小的短接组件130，提高防静电性能的同时节省生产成本。
如图2，在一些实施例中，短接组件130还包括图案化的半导体结构130b，半导体结构130b在阵列基板100厚度方向上的正投影与第一金属结构130a在阵列基板100厚度方向上的正投影重合。
具体地，如图2，在阵列基板100的非显示区NA，阵列基板100包括衬底190，衬底190可以是玻璃，也可以是聚酰亚胺(polyimide，PI)薄膜等聚合物衬底或者包含PI等聚合物材料的衬底。
半导体结构130b位于该衬底190上，在一些实施例中，半导体结构130b与衬底190之间可以设置有缓冲层，缓冲层可以是氧化物层或氮化物层，例如是氮化硅制成。
第一金属结构130a位于半导体结构130b上，在一些实施例中，第一金属结构130a与半导体结构130b之间可以设置有绝缘层180，绝缘层180可以是氧化物层或氮化物层，例如是氮化硅制成。
半导体结构130b在阵列基板100厚度方向上的正投影与第一金属结构130a在阵列基板100厚度方向上的正投影重合，即，短接组件130在其层结构维度上包括叠层设置的半导体结构130b和第一金属结构130a，两者在垂直于阵列基板100厚度方向的平面维度上的结构相同。通过设置叠层结构的短接组件130，一方面能够进一步减小短接组件130阻抗以获得更快速的静电分散能力，另一方面能够增强短接组件130的结构稳定性。
如前所述，在一些实施例中，像素电路可以包括有源层，有源层可以是多晶硅(polycrystalline silicon，PSi)、非晶硅(amorphous silicon，α-Si)、低温多晶硅(low temperature poly-silicon，LTPS)等半导体材料制成。图案化的半导体结构130b的材质可以与该有源层的材质相同，该半导体结构130b可以与该有源层的同层设置，使得两者能在同一图案化过程中形成，节省工艺制程。
上述实施例中，短接组件130包括叠层的第一金属结构130a和半导体结构130b。在其它一些实施例中，短接组件130可以仅包括第一金属结构130a。
如图1，在一些实施例中，焊盘120包括在第一方向X上间隔排列的第一焊盘单元121、第二焊盘单元122。其中第一焊盘单元121与多条信号线110中的对应一条连接，第二焊盘单元122与短接组件130连接。在一些实施例中，阵列基板为矩形，第一方向X例如是平行于阵列基板的长度方向。
如图2，第一焊盘单元121与第二焊盘单元122之间间隔形成间隙123。第一焊盘单元121、第二焊盘单元122均通过过孔连接至互连块140，使得第一焊盘单元121与第二焊盘单元122电连接。
在上述实施例中，焊盘120包括间隔排列且通过互连块140相互电连接的第一焊盘单元121、第二焊盘单元122，使得短接组件130仍然能够通过焊盘120与多条信号线110连接以将多条信号线110短接。由于第一焊盘单元121与第二焊盘单元122间隔设置，当外界水汽等对焊盘120产生腐蚀时，腐蚀部分会截止在第一焊盘单元121与第二焊盘单元122之间的间隙123处，从而避免水汽腐蚀进一步侵入与信号线110连接的第一焊盘单元121，提高阵列基板100接口区BD焊盘120的防腐蚀性能。
在一些实施例中，互连块140的材质与像素电路的有源层的材质相同；互连块140可以与像素电路的有源层同层设置。在本实施例中，互连块140、短接组件130的半导体结构130b以及像素电路的有源层同层设置，从而能在同一图案化过程中形成，节省工艺制程。
在其它一些实施例中，互连块140也可以是其它的导电材料制成。在其它一些实施例中，互连块140可以与阵列基板100的某个金属层同层布置并能够在同一图案化过程中形成。
如图1，在本实施例中，短接组件130包括短接棒131以及多条连接线132。短接棒131可以是沿预定方向延伸的条形导体结构，本实施例中，短接棒131沿第二方向Y延伸。每个焊盘120通过对应一条连接线132与短路棒131连接。每相邻两个焊盘120依次通过连接线132、短路棒131、连接线132电连接，在一些实施例中，相邻两个焊盘120之间的电连接结构中的电阻为50欧以下。
在一些实施例中，阵列基板100在经过检测后，可以通过物理切割等方式截断多条连接线132，使得多个焊盘120相互独立而不再通过短接组件130短接。图1和图2中，以L-L线示出用于截断多条连接线132的分割线的延伸方向。在一些实施例中，多条连接线132均沿第一方向X延伸，第二方向Y与第一方向X交叉，分割线沿第二方向Y延伸，并与全部连接线132相交。
如图2，在一些实施例中，阵列基板100还包括保护层150，保护层150覆盖短接组件130。本实施例中，保护层150覆盖短接组件130的第一金属结构130a。其中，保护层150上设有槽道151，槽道151从保护层150 的表面贯穿至第一金属结构130a，使得第一金属结构130a在该槽道151处裸露。槽道151的位置以及延伸方向与上述分割线的位置以及延伸方向对应，使得槽道151与多条连接线132相交设置。分割装置沿该槽道151对阵列基板100进行分割，可以实现上述多条连接线132的截断。
本申请实施例还提供一种阵列基板母板，该阵列基板母板可以包括多个阵列排布的阵列基板，其中阵列基板可以是上述任一实施方式的阵列基板，以下将以该阵列基板为上述本申请实施例提供的阵列基板100为例进行说明。
图3是根据本申请一种实施例提供的阵列基板母板的结构示意图，图4示出图3中F-F向的剖面示意图。
阵列基板母板1000中，多个阵列基板100排布为多行，每行排布有多个阵列基板100。其中，图3中的排列方式和阵列基板100的数量仅为示意，多个阵列基板100形成的排列中，阵列基板100的行数以及每行中阵列基板100的数量可以根据实际需要设置。
根据本申请实施例的阵列基板母板1000，其包括的每个阵列基板100的接口区BD具有多个焊盘120，并且多个焊盘120能够通过短接组件130短接，进而使得多个焊盘120连接的多条信号线110短接。当阵列基板100上某个局部产生静电电荷时，能够通过该短接组件130将静电电荷分散在整个阵列基板100上。
在一些实施例中，可以将短接组件130连接至稳定电压源，使得阵列基板100上的电荷能够通过短接组件130传导和消除。在本申请实施例的阵列基板100中，短接组件130包括图案化的第一金属结构130a，相对于半导体结构的短接组件，能够大大降低相互连接的焊盘120间的阻抗，静电产生后能够更快速地分散电荷，避免由于静电引起的静电击伤、静电引起的产品缺陷等问题。
在一些实施例中，阵列基板母板1000还包括短接互连组件200。短接互连组件200能够将将阵列基板母板1000上的至少部分阵列基板100的短接组件130互相连接。
其中，短接互连组件200包括第一互连单元210和第二互连单元220。 第一互连单元210串接同行的多个阵列基板100，第二互连单元220并接多行阵列基板100中的至少两行。
在图3所示的实施例中，以多个阵列基板100呈3×3的排列布局为例进行说明。其中，短接互连组件200将阵列基板母板1000上的全部阵列基板100的短接组件130互相连接，从而可以实现阵列基板母板1000上全部阵列基板100上的静电分散，进一步增加阵列基板母板1000的静电分散能力。
在其它一些实施例中，短接互连组件200可以将阵列基板母板1000上的一部分阵列基板100的短接组件130互相连接，相互连接的多个阵列基板100上的静电分散。
在一些实施例中，短接互连组件200上设有连接端子300，短接互连组件200可以通过该连接端子300与稳定电压源连接，使得阵列基板母板1000的多个阵列基板100上的电荷能够通过短接组件130、短接互连组件200以及连接端子300传导和消除。
如图4，在一些实施例中，短接互连组件200包括图案化的第二金属结构200a，该第二金属结构200a能够通过过孔与第一金属结构130a连接。在图4中，右端的第一金属结构130a为第一互连单元210的一部分结构，左端的第一金属结构130a为第二互连单元220的一部分结构。在一些实施例中第二金属结构200a可以与阵列基板100的某个金属层同层布置并能够在同一图案化过程中形成，以节省工艺制程。
依照本申请如上文所述的实施例，这些实施例并没有详尽叙述所有的细节，也不限制该申请仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本申请的原理和实际应用，从而使所属技术领域技术人员能很好地利用本申请以及在本申请基础上进行修改使用。本申请仅受权利要求书及其全部范围和等效物的限制。

Claims (16)

  1. 一种阵列基板，具有显示区以及位于所述显示区外周的非显示区，所述非显示区设有接口区，所述阵列基板包括：
    多条信号线，延伸于所述显示区并引出至所述非显示区；
    多个焊盘，位于所述接口区，所述多个焊盘中的每个连接所述多条信号线中的对应一条；以及
    短接组件，位于所述非显示区，所述短接组件与所述多个焊盘连接，使得所述多个焊盘连接的所述多条信号线短接，其中，所述短接组件包括图案化的第一金属结构。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括设置于所述显示区的多个像素电路，所述多个像素电路中的每个与所述多条信号线中的至少一条连接，所述多个像素电路包括栅极导体，所述第一金属结构的材质与所述栅极导体的材质相同。
  3. 根据权利要求2所述的阵列基板，其中，所述第一金属结构与所述栅极导体同层设置。
  4. 根据权利要求1所述的阵列基板，其中，所述多个焊盘中的每个包括在第一方向上间隔排列的第一焊盘单元、第二焊盘单元，所述第一焊盘单元与所述多条信号线中的对应一条连接，所述第二焊盘单元与所述短接组件连接，所述第一焊盘单元、所述第二焊盘单元均通过过孔连接至互连块，使得所述第一焊盘单元与所述第二焊盘单元电连接。
  5. 根据权利要求4所述的阵列基板，其中，所述阵列基板包括设置于所述显示区的多个像素电路，所述多个像素电路中的每个与所述多条信号线中的至少一条连接，所述多个像素电路包括有源层，所述互连块的材质与所述有源层的材质相同。
  6. 根据权利要求5所述的阵列基板，其中，所述互连块与所述有源层同层设置。
  7. 根据权利要求1所述的阵列基板，其中，所述短接组件还包括图案化的半导体结构，所述半导体结构在所述阵列基板厚度方向上的正投影与 所述第一金属结构在所述阵列基板厚度方向上的正投影重合。
  8. 根据权利要求7所述的阵列基板，其中，所述第一金属结构与所述半导体结构之间设置有绝缘层。
  9. 根据权利要求7所述的阵列基板，其中，所述阵列基板包括设置于所述显示区的多个像素电路，所述多个像素电路中的每个与所述多条信号线中的至少一条连接，所述多个像素电路包括有源层，所述半导体结构与所述有源层的材质相同。
  10. 根据权利要求9所述的阵列基板，其中，所述半导体结构与所述有源层同层设置。
  11. 根据权利要求1所述的阵列基板，其中，所述短接组件包括：
    短接棒；以及
    多条连接线，所述多个焊盘中的每个通过所述多条连接线中的对应一条与所述短路棒连接。
  12. 根据权利要求11所述的阵列基板，其中，所述阵列基板还包括：
    保护层，所述保护层覆盖所述短接组件。
  13. 根据权利要求12所述的阵列基板，其中，所述保护层上设有槽道，所述槽道从所述保护层的表面贯穿至所述第一金属结构，所述槽道与所述多条连接线相交设置。
  14. 一种阵列基板母板，包括多个根据权利要求1至13任一项所述的阵列基板，多个所述阵列基板阵列排布。
  15. 根据权利要求14所述的阵列基板母板，其中，多个所述阵列基板排布为多行，每行排布有多个所述阵列基板，
    所述阵列基板母板还包括短接互连组件，所述短接互连组件包括第一互连单元和第二互连单元，所述第一互连单元串接同行的多个所述阵列基板，所述第二互连单元并接多行所述阵列基板中的至少两行。
  16. 根据权利要求15所述的阵列基板母板，其中，所述短接互连组件包括图案化的第二金属结构，所述第二金属结构能够通过过孔与所述第一金属结构连接。
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