WO2021168730A1 - 母板及其制作方法 - Google Patents

母板及其制作方法 Download PDF

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Publication number
WO2021168730A1
WO2021168730A1 PCT/CN2020/076944 CN2020076944W WO2021168730A1 WO 2021168730 A1 WO2021168730 A1 WO 2021168730A1 CN 2020076944 W CN2020076944 W CN 2020076944W WO 2021168730 A1 WO2021168730 A1 WO 2021168730A1
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Prior art keywords
line
motherboard
line segment
thin film
resistors
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PCT/CN2020/076944
Other languages
English (en)
French (fr)
Inventor
李永谦
袁粲
李蒙
冯雪欢
吴仲远
袁志东
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/076944 priority Critical patent/WO2021168730A1/zh
Priority to US17/435,098 priority patent/US20220344224A1/en
Priority to EP20921617.5A priority patent/EP4113611A4/en
Priority to CN202080000170.3A priority patent/CN114127944A/zh
Publication of WO2021168730A1 publication Critical patent/WO2021168730A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05F—STATIC ELECTRICITY; NATURALLY-OCCURRING ELECTRICITY
    • H05F3/00—Carrying-off electrostatic charges
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors

Definitions

  • the embodiment of the present disclosure relates to a motherboard and a manufacturing method thereof.
  • Organic Light Emitting Diode (OLED) display devices have the characteristics of wide viewing angle, high contrast, and fast response speed. In addition, compared with inorganic light-emitting display devices, organic light-emitting diode display devices have advantages such as higher light-emitting brightness and lower driving voltage. Due to the above-mentioned characteristics and advantages, organic light-emitting diode (OLED) display devices have gradually received widespread attention and can be applied to devices with display functions such as mobile phones, displays, notebook computers, digital cameras, and instrumentation.
  • At least one embodiment of the present disclosure provides a motherboard that includes at least one display area, a peripheral area surrounding the at least one display area, a plurality of test terminals, an electrostatic discharge line, a plurality of resistors, and at least one thin film Transistor.
  • the plurality of test terminals, the electrostatic discharge line, and the plurality of resistors are located in the peripheral area; the at least one thin film transistor is located in at least one of the at least one display area and the peripheral area; A plurality of test terminals are respectively electrically connected to the electrostatic discharge line via the plurality of resistors; at least one of the plurality of resistors includes an inorganic non-metal wiring; the at least one thin film transistor includes an active layer; and the The inorganic non-metal wiring and the active layer of the at least one thin film transistor comprise the same semiconductor base material.
  • the semiconductor base material is an oxide semiconductor material.
  • the oxide semiconductor material is indium gallium zinc oxide.
  • the active layer includes a source region, a drain region, and a channel region, and the channel region is located between the source region and the drain region
  • the conductivity of the inorganic non-metallic trace is higher than the conductivity of the channel region; and the conductivity of the inorganic non-metallic trace is not higher than the conductivity of the source region and the drain region The conductivity.
  • the inorganic non-metallic trace contains doped impurities, the source region and the drain region contain the doped impurities; and the inorganic non-metallic trace
  • the concentration of the doping impurity in the line is not higher than the concentration of the doping impurity in the source region and the drain region.
  • the channel region does not contain the doping impurities.
  • the plurality of test terminals are sequentially arranged in a first direction, and the plurality of resistors are sequentially arranged in the first direction; and the plurality of test terminals The terminals and the plurality of resistors are alternately arranged in the first direction.
  • the inorganic non-metallic trace includes a broken line, and the first end of the broken line is electrically connected to a corresponding one of the plurality of test terminals, And the second end of the broken line is electrically connected with the electrostatic discharge line.
  • the fold line routing includes a plurality of first fold line units sequentially arranged in the first direction and connected to each other.
  • At least one of the plurality of first fold line units includes a first line segment, a second line segment, a third line segment, and The fourth line segment; the first line segment and the third line segment extend in the first direction, and the second line segment and the fourth line segment extend in a second direction crossing the first direction; so The first line segment and the third line segment are spaced apart in the second direction, the second line segment and the fourth line segment are spaced apart in the first direction; and the first line segment The end point is connected to the start point of the second line segment, the end point of the second line segment is connected to the start point of the third line segment, and the end point of the third line segment is connected to the start point of the fourth line segment.
  • the length of the second line segment is equal to 1/16-1/2 of the distance between two adjacent test terminals in the first direction.
  • the first fold line unit is located on a straight line where the upper edges of the plurality of test terminals are located and the plurality of test terminals in a second direction crossing the first direction Between the straight line where the lower edge of the test terminal is located.
  • the extension length of the first fold line unit in the second direction is equal to 1/2-4 of the size of the plurality of test terminals in the second direction /5.
  • the square resistance of the folded line is 100 ohms to 300 ohms.
  • the ratio of the physical length of the fold line to the line width of the fold line is greater than or equal to 700 and less than or equal to 2,000.
  • the fold line is a rectangular fold line or a zigzag fold line.
  • each of the at least one display area includes a plurality of first signal lines that extend side by side to the outside of each of the at least one display area; and the plurality of test The terminal includes a first test terminal, and the plurality of first signal wires are electrically connected to the first test terminal.
  • each of the at least one display area further includes a plurality of second signal lines that extend side by side to the outside of each of the at least one display area; A signal line crosses the plurality of second signal lines; the plurality of test terminals further include a second test terminal; and the plurality of second signal lines are electrically connected to the second test terminal.
  • the motherboard further includes a gate driving circuit.
  • the gate driving circuit is located in the peripheral area and includes a first number of thin film transistors among the at least one thin film transistor; and the first number is less than or equal to the number of the at least one thin film transistor.
  • each of the at least one display area further includes a plurality of sub-pixels arranged in an array; each of the sub-pixels includes a pixel drive circuit and a light-emitting element; the pixel drive The circuit includes a second number of thin film transistors among the at least one thin film transistor and is configured to drive the light emitting element; and the second number is less than or equal to the number of the at least one thin film transistor.
  • the motherboard further includes an insulating layer between the electrostatic discharge line and the plurality of resistors.
  • the insulating layer includes a plurality of via holes, and the electrostatic discharge line and the plurality of resistors are electrically connected through the plurality of via holes, respectively.
  • At least one embodiment of the present disclosure provides a method of manufacturing a motherboard, the motherboard including at least one display area and a peripheral area surrounding the at least one display area, the manufacturing method including: forming in the peripheral area A plurality of test terminals, an electrostatic discharge line, and a plurality of resistors; and at least one thin film transistor is formed in at least one of the at least one display area and the peripheral area.
  • the plurality of test terminals are respectively electrically connected to the electrostatic discharge line via the plurality of resistors; at least one of the plurality of resistors includes an inorganic non-metallic wiring, and the at least one thin film transistor includes an active layer; And the same semiconductor base material is used to form the wiring and the active layer.
  • the formation of the plurality of resistors in the peripheral area and the formation of the at least one thin film in at least one of the at least one display area and the peripheral area includes: forming a semiconductor base material layer; patterning the semiconductor base material layer to form a first pattern and a second pattern; and conducting the first pattern to form the wiring.
  • the second pattern is used to form the active layer of the at least one thin film transistor.
  • the active layer includes a source region, a drain region, and a channel region, and the channel region is located between the source region and the drain region
  • the manufacturing method further includes: conducting part of the second pattern to form the source region and the drain region, and not conducting part of the second pattern to form the groove Road area.
  • the conductorization includes at least one of doping and plasma treatment.
  • FIG. 1A is a motherboard
  • FIG. 1B is an equivalent schematic diagram of the connection relationship among multiple test terminals, electrostatic discharge lines, and multiple resistors of the motherboard shown in FIG. 1A;
  • Fig. 1C is an enlarged view of the resistor shown in Fig. 1A;
  • FIG. 2 is a schematic plan view of a motherboard provided by at least one embodiment of the present disclosure
  • 3A is another schematic plan view of a motherboard provided by at least one embodiment of the present disclosure.
  • 3B is a schematic plan view of the display area and the first peripheral area of the motherboard described in FIG. 3A;
  • 3C is a schematic plan view of an active layer of a thin film transistor of a motherboard provided by at least one embodiment of the present disclosure
  • FIG. 4A shows a schematic plan view of a broken line routing of a resistor provided by at least one embodiment of the present disclosure
  • 4B is a schematic plan view of the test terminals of the motherboard shown in FIG. 2 and the broken line routing of the resistor;
  • FIG. 4C shows another example of the broken line routing of the resistor provided by at least one embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of the interface of the connection relationship between the electrostatic discharge line and multiple resistors provided by at least one embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a 3T1C pixel circuit provided by at least one embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a GOA using a 4T1C circuit structure as a GOA unit provided by at least one embodiment of the present disclosure.
  • FIGS. 8A-8D show a method for fabricating a resistor and a thin film transistor provided by at least one embodiment of the present disclosure.
  • FIG. 1A is a motherboard 500.
  • the motherboard 500 includes at least one display area 501 and a peripheral area (not marked in the figure) surrounding the at least one display area 501; the peripheral area includes a plurality of test terminals (pads) 511, electrostatic discharge wires 512, and Multiple resistors 513.
  • FIG. 1B is an equivalent schematic diagram of the connection relationship among a plurality of test terminals 511, an electrostatic discharge line 512, and a plurality of resistors 513 of the motherboard 500 shown in FIG. 1A. As shown in FIG. 1B, the plurality of test terminals 511 are electrically connected to the electrostatic discharge line 512 via the plurality of resistors 513, respectively.
  • the display area 501 includes a plurality of signal lines extending side by side to the outside of the display area 501 (the portion of the signal line located in the display area 501 is not shown in FIG. 1A), and the plurality of test terminals 511 are respectively connected via a plurality of short circuits.
  • the wire 514 (for example, a short-circuit ring) is electrically connected to the corresponding signal wire.
  • a plurality of test terminals 511 are arranged in sequence in the first direction D1, and a plurality of resistors 513 are arranged in sequence in the first direction D1; the plurality of test terminals 511 and the plurality of resistors 513 are arranged in the first direction D1. Arranged alternately.
  • the plurality of signal lines includes a plurality of first signal lines and a plurality of second signal lines, and the plurality of first signal lines and the plurality of second signal lines respectively extend along, for example, the first direction D1 and the second direction D2, and the plurality of The first signal line crosses a plurality of second signal lines;
  • the plurality of test terminals 511 include a first test terminal 5111 and a second test terminal 5112; the plurality of first signal lines are electrically connected to the first test terminal 5111;
  • the signal line is electrically connected to the second test terminal 5112.
  • the first signal line and the second signal line are gate lines and data lines, respectively.
  • the display area 501 further includes a plurality of sub-pixels arranged in an array, and each sub-pixel includes a pixel driving circuit and a light-emitting element, and the pixel driving circuit is configured to drive the light-emitting element.
  • the light-emitting element is a bottom emission type light-emitting element.
  • the light-emitting element includes a first electrode, a light-emitting layer, and a second electrode that are sequentially arranged.
  • the first electrode and the second electrode are respectively an anode and a cathode
  • the light-emitting layer is an organic light-emitting layer.
  • the first electrode has a first reflectivity for the light emitted by the light-emitting layer
  • the second electrode has a second reflectivity for the light emitted by the light-emitting layer, and the first reflectivity is less than the second reflectivity, so the light emitted by the light-emitting layer It leaves the light emitting element via the first electrode, that is, the light emitting element is a bottom emission type light emitting element.
  • the first electrode is formed of a transparent conductive material; for example, the transparent conductive material is indium tin oxide (ITO) or indium zinc oxide (IZO).
  • FIG. 1C is an enlarged view of the resistor 513 shown in FIG. 1A.
  • at least one of the plurality of resistors 513 is implemented as a wire, and the material of the wire is the same as the material of the first electrode.
  • the wiring and the first electrode are formed in the same patterning process.
  • the traces may be formed of indium tin oxide (ITO).
  • each test terminal 511 is connected to a plurality of signal lines, a large amount of electrostatic charge is accumulated on at least one test terminal 511, and the test terminal 511 is not connected to the electrostatic discharge line 512 Next, the test terminal 511 that has accumulated a large amount of electrostatic charge may cause defects caused by electrostatic discharge (for example, a burnout phenomenon caused by the accumulation of electrostatic charge).
  • the electrostatic charge on the test terminal 511 on which a large amount of electrostatic charge has accumulated may be directed to the adjacent test terminal via the electrostatic discharge line 512.
  • the terminal 511 passes.
  • the corresponding resistor 513 will lose at least part of the electrostatic charge to protect the structure electrically connected to the other test terminal 511.
  • each resistor 513 when the resistance of each resistor 513 is greater than 70,000 ohms, the resistor 513 can effectively dissipate the electrostatic charge.
  • the inventors of the present disclosure noticed that in the case where the wiring of the resistor 513 and the first electrode (for example, the anode) of the top emission type light-emitting element are formed in the same patterning process, since the conductivity of the first electrode is relatively large, In order to make the resistance of each resistor 513 greater than 70,000 ohms, the physical length of the trace of each resistor 513 is relatively long; because the distance between adjacent test terminals 511 in the first direction D1 is limited, it is necessary to pass the wire The wiring is arranged in a way (that is, the wiring of the resistor 513 is a broken line), and the distance between the line segments arranged side by side of the broken line is small, which increases the difficulty of production and reduces the broken line.
  • the yield rate of the line (for example, the broken line traces are arranged side by side and the adjacent line segments may have short circuits, or the broken line traces may have open circuits caused by reducing the trace width).
  • the physical length of the trace refers to the length of the trace in the first direction assuming that the trace is stretched to be a straight line parallel to the first direction.
  • the inventors of the present disclosure have also noticed that the application range of the technical solution for forming the wiring of the resistor 513 and the first electrode (for example, the anode) of the light-emitting element in the same patterning process is narrow.
  • the light-emitting element is implemented as a top-emission light-emitting element
  • it is difficult to use the above-mentioned technical solution because the conductivity of the anode of the top-emission light-emitting element is greater than that of the anode of the bottom-emission light-emitting element (due to the top
  • the anode of the emissive light-emitting element includes a metal material).
  • a motherboard that does not include a self-luminous light-emitting element (for example, a motherboard for forming a liquid crystal display panel).
  • At least one embodiment of the present disclosure provides a motherboard and a manufacturing method thereof.
  • the motherboard includes at least one display area, a peripheral area surrounding the at least one display area, a plurality of test terminals, an electrostatic discharge line, a plurality of resistors, and at least A thin film transistor.
  • a plurality of test terminals, an electrostatic discharge line, and a plurality of resistors are located in the peripheral area; at least one thin film transistor is located in at least one of the display area and the peripheral area; the plurality of test terminals are electrically connected to the electrostatic discharge line via a plurality of resistors, respectively; At least one of the plurality of resistors includes an inorganic non-metallic wiring; at least one thin film transistor includes an active layer; and the inorganic non-metallic wiring and the active layer of the at least one thin film transistor include the same semiconductor base material.
  • the motherboard and its manufacturing method can improve the yield rate.
  • FIG. 2 is a schematic plan view of a motherboard 100 provided by at least one embodiment of the present disclosure.
  • the motherboard 100 includes a plurality of test terminals 111, an electrostatic discharge line 112 and a plurality of resistors 113.
  • the motherboard 100 further includes at least one display area 101 and a peripheral area (not marked in FIG. 2) surrounding the at least one display area 101.
  • a plurality of test terminals 111, an electrostatic discharge line 112, and a plurality of resistors 113 are all Located in the surrounding area.
  • FIG. 2 and other drawings only show one display area 101 and a peripheral area surrounding the display area 101, but the embodiments of the present disclosure are not limited thereto.
  • the motherboard 100 may include a plurality of display areas 101 arranged in an array and a plurality of peripheral areas respectively surrounding the plurality of display areas 101, which will not be repeated here.
  • a plurality of test terminals 111 are sequentially arranged in the first direction D1, and a plurality of resistors 113 are sequentially arranged in the first direction D1; the plurality of test terminals 111 and the plurality of resistors 113 are arranged in the first direction D1. Alternately arranged in the direction D1.
  • the plurality of test terminals 111 are electrically connected to the electrostatic discharge line 112 via the plurality of resistors 113, respectively.
  • at least one of the plurality of resistors 113 includes an inorganic non-metallic wire.
  • the inorganic non-metallic wire includes a broken wire.
  • the first end 1131 of the broken line is electrically connected with a corresponding one of the test terminals 111, and the second end 1132 of the broken line is electrically connected with the electrostatic discharge line 112.
  • FIG. 3A is another schematic plan view of a motherboard 100 provided by at least one embodiment of the present disclosure.
  • the schematic plan view of the motherboard 100 shown in FIG. 3A is similar to the schematic plan view of the motherboard 100 shown in FIG.
  • the display area 101 includes a plurality of first signal lines 141 extending side by side to the outside of the display area 101; the plurality of test terminals 111 include a first test terminal 1111, and the plurality of first signal lines 141 and the first The test terminal 1111 is electrically connected.
  • the display area 101 further includes a plurality of second signal lines 142 extending side by side to the outside of the display area 101; the plurality of first signal lines 141 cross the plurality of second signal lines 142; and the plurality of test terminals 111 also includes a second test terminal 1112; a plurality of second signal wires 142 are electrically connected to the second test terminal 1112.
  • the peripheral area further includes a plurality of short-circuit connection wires 114, and the plurality of short-circuit connection wires 114 correspond to the plurality of test terminals 111, for example, in a one-to-one correspondence.
  • the motherboard 100 includes two first test terminals 1111 and two second test terminals 1112; the multiple short-circuit connection lines 114 include two first short-circuit connection lines 1141 and two second short-circuit connections.
  • Line 1142; one first test terminal 1111 is electrically connected to the first signal line 141 in the odd-numbered row via a first short-circuit connection line 1141, and the other first test terminal 1111 is electrically connected to the first signal line 141 in the odd-numbered row via another first short-circuit connection line 1141.
  • the first signal line 141 in the even-numbered row is electrically connected; one second test terminal 1112 is electrically connected to the second signal line 142 in the odd-numbered column via a second short-circuit connection line 1142, and the other second test terminal 1112 is electrically connected via another The second short-circuit connection line 1142 is electrically connected to the second signal line 142 located in the even-numbered column.
  • the first signal line 141 and the second signal line 142 extend in a first direction D1 and a second direction D2, respectively, and the first direction D1 and the second direction D2 are, for example, perpendicular.
  • the first signal line 141 and the second signal line 142 are gate lines and data lines, respectively.
  • the plurality of test terminals 111 further include a third test terminal 1113
  • the plurality of short-circuit connection lines 114 include a third short-circuit connection line 1143
  • the display area 101 includes a common terminal extending outside the display area 101
  • the electrode line (the part of the common electrode line located in the display area 101 is not shown in the figure), the common electrode line is electrically connected to the third test terminal 1113 via the third short-circuit connection line 1143.
  • the peripheral area includes a first peripheral area 102 surrounding the display area 101 and a second peripheral area 103 surrounding the first peripheral area 102.
  • the first peripheral area 102 is located in the display area 101 and the second peripheral area 103.
  • multiple test terminals 111, electrostatic discharge lines 112 and multiple resistors 113 are located in the second peripheral area 103.
  • the motherboard 100 provided by the above-mentioned embodiment of the present disclosure will be cut after the preparation, testing and other processes are completed, and finally a single independent display panel is obtained, and the obtained independent display panel is then subjected to subsequent processes.
  • the obtained single panel still retains the first peripheral area 102, but at least part of the second peripheral area 103 (for example, all of the second peripheral area 103) is cut away, therefore, the obtained single panel may not remain
  • the test terminal 111, the electrostatic discharge line 112, the resistor 113, and the short-circuit connection line 114 are tested.
  • test terminal 111 the electrostatic discharge line 112, the resistor 113, and the short-circuit connection line 114 may also be retained in the resulting single panel.
  • FIG. 3B is a schematic plan view of the display area 101 and the first peripheral area 102 of the motherboard 100 described in FIG. 3A.
  • the motherboard 100 further includes a gate driving circuit 117.
  • the gate driving circuit 117 is located in the peripheral area (the first peripheral area 102) and includes a thin film transistor (not shown in FIG. 3B).
  • the plurality of signal output terminals of the gate driving circuit 117 are electrically connected to the plurality of first signal lines (eg, gate lines) 141 to provide gate scanning signals for the plurality of gate lines.
  • the peripheral area (the first peripheral area 102) further includes a data driving circuit, and a plurality of signal output terminals of the data driving circuit are electrically connected to a plurality of second signal lines (for example, data lines) to provide data signals for the plurality of data lines .
  • the display area 101 further includes a plurality of sub-pixels 143 arranged in an array.
  • Each sub-pixel 143 includes a pixel driving circuit and a light-emitting element.
  • the pixel driving circuit includes a thin film transistor (not shown in FIG. 3B) and is configured to Drive the light-emitting element.
  • the structures of the gate driving circuit 117 and the sub-pixel 143 will be described in the examples shown in FIGS. 6 and 7 and will not be repeated here.
  • inorganic non-metallic traces may include semiconductor matrix materials.
  • the inorganic non-metal wiring and the active layer of the thin film transistor of at least one of the gate driving circuit 117 and the pixel driving circuit include the same semiconductor base material.
  • the semiconductor base material is an oxide semiconductor material or a polysilicon material.
  • the oxide semiconductor material is indium gallium zinc oxide.
  • the conductivity of the inorganic non-metallic wiring can be reduced, thereby In the case of ensuring that the inorganic non-metallic wiring can effectively dissipate the electrostatic charge (for example, when the resistance of the inorganic non-metallic wiring is greater than 70,000 ohms), the physical length of the inorganic non-metallic wiring is as short as possible; In this case, it is possible to reduce the number of windings of inorganic non-metallic traces and polyline traces, as well as the parallel arrangement of polyline traces and the spacing between adjacent line segments (for example, the adjacent first line shown in FIG. 4A) The distance between the segment 122 and the third line segment 124 in the second direction D2), thereby reducing the manufacturing difficulty and yield of inorganic non-metal wiring.
  • the inorganic non-metal wiring and the active layer of the thin film transistor of at least one of the gate driving circuit 117 and the pixel driving circuit include the same semiconductor base material
  • the inorganic non-metallic trace can also be made by the manufacturing process of the thin film transistor. Wire routing can simplify the manufacturing process of the motherboard 100 provided by at least one embodiment of the present disclosure.
  • the motherboard provided by at least one embodiment of the present disclosure can also be made 100 is suitable for forming display panels with top-emission light-emitting elements, display panels with bottom-emission light-emitting elements, liquid crystal display panels, or other display panels with thin film transistors.
  • the active layer includes a source region 144, a drain region 145, and a channel region 146, and the channel region 146 is located between the source region 144 and the drain region 145.
  • the conductivity of the inorganic non-metallic trace is higher than the conductivity of the channel region 146 (for example, the conductivity of the channel region 146 when the thin film transistor is not turned on).
  • the conductivity of the inorganic non-metallic trace is not higher than the conductivity of the source region 144 and the conductivity of the drain region 145.
  • the electrostatic charge can be transferred along the electrostatic discharge line 112 toward the other test terminals 111 while ensuring the effective loss of electrostatic charge.
  • the conductivity of the inorganic non-metallic wiring can be improved by conducting the conductorization of the semiconductor matrix material forming the inorganic non-metallic wiring.
  • the method of conducting the conductorization of the semiconductor matrix material forming the inorganic non-metallic wiring can be set according to actual application requirements, which is not specifically limited in the embodiments of the present disclosure.
  • the conductorization includes at least one of doping and plasma treatment.
  • the method of conducting conduction through doping or plasma treatment can refer to the related technology, which will not be repeated here.
  • inorganic non-metallic traces can better control the conductivity of the inorganic non-metallic traces without increasing the complexity of the process, thereby increasing the degree of design freedom while increasing the yield of the motherboard 100.
  • the square resistance of inorganic non-metallic traces is between 100 ohms and 300 ohms (for example, 200 ohms).
  • the square resistance of the trace is equal to the ratio of the electrical conductivity of the trace material to the thickness of the trace.
  • the ratio of the physical length of the polyline trace to the line width of the polyline trace is greater than or equal to 700 and less than or equal to 2000 (for example, 1000-1500; for example, 1200).
  • the resistance value of the polyline trace is equal to the product of the square resistance of the polyline trace and the ratio of the physical length of the polyline trace to the line width of the polyline trace
  • the resistance value of the polyline trace is located at 7 Between 10,000 ohms and 600,000 ohms (for example, 100,000 ohms to 450,000 ohms; for example, 240,000 ohms).
  • the method of conductorizing the semiconductor base material for forming inorganic non-metallic traces may be the same as the method of conductorizing part of the semiconductor layer of the thin film transistor to form the source region 144 and the drain region 145.
  • the inorganic non-metallic trace contains doped impurities, and the source region 144 and the drain region 145 contain doped impurities.
  • the channel region 146 does not contain dopant impurities or the channel region 146 contains dopant impurities that are different from the dopant impurities contained in the source region 144 and the drain region 145.
  • the doping impurities contained in the inorganic non-metallic traces are the same as the doping impurities contained in the source region 144 and the drain region 145.
  • the inorganic non-metallic traces, the source region 144 and the drain region 145 are formed through the same patterning process and the same doping process.
  • the concentration of the above-mentioned doping impurities in the inorganic non-metal wiring is not higher than the concentration of the above-mentioned doping impurities in the source region 144 and the drain region 145.
  • the shape of the broken line can be set according to actual application requirements, which is not specifically limited in the embodiments of the present disclosure.
  • the fold lines shown in FIGS. 2 and 3A may be rectangular fold lines, zigzag fold lines, or other suitable shapes. An exemplary description will be given below with reference to FIGS. 4A to 4C.
  • FIG. 4A shows an example of the folding line routing of the resistor 113 provided by at least one embodiment of the present disclosure.
  • the fold line routing includes a plurality of first fold line units 121 sequentially arranged in the first direction D1 and connected to each other.
  • At least one of the plurality of first fold line units 121 includes a first line segment 122, a second line segment 123, and a third line segment that are sequentially connected in the first direction D1 124 and the fourth line segment 125; the first line segment 122 and the third line segment 124 extend along the first direction D1, the second line segment 123 and the fourth line segment 125 extend along the second direction D2 crossing the first direction D1; the first line The segment 122 and the third line segment 124 are arranged at intervals in the second direction D2, and the second line segment 123 and the fourth line segment 125 are arranged at intervals in the first direction D1; the end point of the first line segment 122 is connected with the start point of the second line segment 123, The end point of the second line segment 123 is connected with the start point of the third line segment 124, and the end point of the third line segment 124 is connected with the start point of the fourth line segment 125.
  • the starting point of the first line segment 122 is connected with the start point of the second line segment
  • the fold line routing further includes a second fold line unit 128;
  • the second fold line unit 128 includes a fifth line segment 126 and a sixth line segment 127 arranged in sequence in the first direction D1; the fifth line segment 126 extends along the first The sixth line segment 127 extends in the second direction D2; the end point of the fourth line segment 125 is connected to the start point of the fifth line segment 126, and the end point of the fifth line segment 126 is connected to the start point of the sixth line segment 127.
  • the end point is electrically connected to the electrostatic discharge line 112.
  • the length of the first line segment 122 and the third line segment 124 is less than the length of the second line segment 123 and the fourth line segment 125.
  • the length of the fifth line segment 126 is less than the length of the sixth line segment 127.
  • the second line segment 123, the fourth line segment 125, and the sixth line segment 127 can be used as sub-resistors connected in series with each other, and the first line segment 122, the third line segment 124, and the fifth line segment 126 can be used as traces connecting adjacent sub-resistors.
  • at least one of the plurality of resistors 113 (for example, each of the plurality of resistors 113) can be regarded as a resistor string.
  • the lengths of the multiple first line segments 122 are not completely the same, the lengths of the multiple third line segments 124 are not completely the same, and the lengths of the multiple second line segments 123 and the multiple fourth line segments 125 are the same.
  • the embodiments of the present disclosure are not limited to this.
  • the lengths of the plurality of first line segments 122 and the plurality of third line segments 124 are completely the same, and the lengths of the plurality of second line segments 123 and the plurality of fourth line segments 125 are the same.
  • the lengths of the multiple first line segments 122 and the multiple third line segments 124 are completely the same, the lengths of the multiple second line segments 123 are not completely the same, and the lengths of the multiple fourth line segments 125 are not completely the same.
  • FIG. 4B shows a schematic plan view of the test terminal 111 of the motherboard 100 shown in FIG. 2 and the broken line routing of the resistor 113.
  • the first fold line unit 121 is located on a straight line (a dotted line on the upper side shown in FIG. 4B) and multiple test terminals 111 in a second direction D2 that crosses the first direction D1. Between the straight lines (the dotted lines on the lower side shown in FIG. 4B) where the lower edges of the test terminals 111 are located.
  • the first fold line unit 121 located in the second direction D2 between the line where the upper edges of the plurality of test terminals 111 are located and the line where the lower edges of the plurality of test terminals 111 are located, it is possible to prevent the first fold line unit 121 from being extra. Occupies space in the peripheral area, thereby facilitating reduction in the size of the motherboard 100.
  • the extension length of the first fold line unit 121 in the second direction D2 is equal to 1/2-4/5 of the size of the plurality of test terminals 111 in the second direction D2 (for example, 2 /3).
  • the extension length of the first fold line unit 121 in the second direction D2 refers to the maximum length of the first fold line unit 121 in the second direction D2; for example, the extension length of the first fold line unit 121 in the second direction D2 is equal to the second line segment 123 and the length of the fourth line segment 125 in the second direction D2.
  • the length of the second line segment 123 (or/and the length of the fourth line segment 125) is equal to 1/16-1/2 (for example, 1/5) of the distance between two adjacent test terminals 111 in the first direction D1. -1/3, for example, 1/4).
  • the adjacent first line segment 122 and the third line segment 122 can be increased.
  • the line width of the folded line is 10 ⁇ m-20 ⁇ m (for example, equal to 10 ⁇ m, 15 ⁇ m, or 20 ⁇ m).
  • the fold line has a uniform line width.
  • the line width of the fold line is equal to the width of the second line segment 123
  • the width of the second line segment 123 is equal to the extension of the second line segment 123 perpendicular to the second line segment 123 The width in the direction.
  • the polyline routing may also have a non-uniform line width.
  • the line widths of the first line segment 122 and the third line segment 124 are greater than the line widths of the second line segment 123 and the fourth line segment 125.
  • FIG. 4C shows another example of the broken line routing of the resistor 113 provided by at least one embodiment of the present disclosure. As shown in FIG. 4C, the broken wires of the resistor 113 are zigzag wires.
  • the motherboard 100 further includes an insulating layer 115 between the electrostatic discharge line 112 and the plurality of resistors 113; the insulating layer 115 includes a plurality of via holes 116, and the electrostatic discharge line 112 and the plurality of resistors 113 respectively pass through the The via holes 116 are electrically connected.
  • the electrostatic discharge line 112 may be formed in the same patterning process as the source and drain of the thin film transistor.
  • the insulating layer 115 and the passivation layer of the thin film transistor may be formed in the same patterning process.
  • the electrostatic discharge line 112 can also be formed in the same patterning process as the gate of the thin film transistor.
  • the insulating layer 115 and the gate insulating layer 115 of the thin film transistor can be formed in the same patterning process.
  • the pixel driving circuit of the sub-pixel provided by at least one embodiment of the present disclosure may be a 2T1C pixel circuit (that is, a pixel circuit including two thin film transistors and a storage capacitor), a 3T1C pixel circuit (that is, including three thin film transistors).
  • One storage capacitor pixel circuit 4T1C pixel circuit (that is, a pixel circuit including four thin film transistors and one storage capacitor), or other applicable pixel circuits.
  • FIG. 6 is a schematic diagram of a 3T1C pixel circuit provided by at least one embodiment of the present disclosure.
  • the pixel circuit includes a driving transistor CT3 (including a gate, a first electrode, and a second electrode), a switching transistor CT1, a sensing transistor CT2, and a storage capacitor Cst.
  • the semiconductor base material included in the inorganic non-metallic trace is the same as the semiconductor base material included in the switching transistor CT1, the sensing transistor CT2, and the driving transistor CT3 (for example, both are indium gallium zinc oxide).
  • the switching transistor CT1 is used as an input write switch, and the gate of the switching transistor CT1 is used as a control terminal G1 to connect to a gate line (not shown in FIG. 6, see the first signal line 141 in FIG.
  • the first pole of the switching transistor CT1 and the second pole of the switching transistor CT1 are respectively connected to the data line (the second signal line 142) and the gate of the driving transistor CT3 to receive the data voltage and the The data voltage is applied to the gate of the driving transistor CT3; the first terminal and the second terminal of the storage capacitor Cst are respectively connected to the gate of the driving transistor CT3 and the first electrode of the driving transistor CT3, thereby storing the gate applied to the driving transistor CT3 And the data voltage at the first end of the storage capacitor Cst.
  • the sensing transistor CT2 serves as a sensing switch, the first pole of the sensing transistor CT2 is connected to the first pole of the driving transistor CT3; the second pole of the sensing transistor CT2 is connected to the sensing line SENL, It is used to charge the capacitance related to the sensing line SENL to form a sensing voltage, so that the sensing voltage can be detected through the sensing line SENL; the gate of the sensing transistor CT2 serves as the control terminal G2 and the sensing voltage
  • the scan line (not shown in FIG. 6, see the first signal line 141 of FIG. 3B) is connected to receive the sensing control signal.
  • the pixel circuit is also connected to the first power supply terminal VDD and the second power supply terminal VSS. For example, the voltage provided by the first power terminal VDD is greater than the voltage provided by the second power terminal VSS.
  • the parasitic capacitance Cvc can be charged by the current from the driving transistor CT3, so that the corresponding voltage on the sensing line SENL changes happened.
  • the embodiments of the present disclosure are not limited to this.
  • control terminal G1 and the control terminal G2 are connected to different scan lines (for example, different first signal lines 141), so that the switching transistor CT1 and the sensing transistor CT2 can be in the on state at different times.
  • the driving transistor CT3, the switching transistor CT1, and the sensing transistor CT2 are all N-type transistors.
  • the light-emitting element includes a first electrode, a light-emitting layer, and a second electrode that are sequentially arranged.
  • the first electrode and the second electrode are respectively an anode and a cathode
  • the light-emitting layer is an organic light-emitting layer.
  • the first electrode has a first reflectivity to the light emitted by the light-emitting layer
  • the second electrode has a second reflectivity to the light emitted by the light-emitting layer, and the first reflectivity is greater than the second reflectivity, so the light emitted from the light-emitting layer It leaves the light emitting element via the second electrode, that is, the light emitting element is a top emission type light emitting element.
  • the first electrode includes a metal material; for example, the second electrode is formed of a transparent conductive material.
  • the gate drive circuit can be implemented as GOA (Gate on Array, gate drive integration on the array substrate).
  • GOA Gate on Array, gate drive integration on the array substrate.
  • the frame size of the display panel obtained from the motherboard can be reduced. Reduce the cost of manufacturing materials for the display panel.
  • the GOA may include a plurality of GOA units (that is, shift registers) connected in sequence.
  • the GOA unit can be implemented as a 4T1C circuit structure (that is, a circuit structure including four thin film transistors and a storage capacitor), an 8T1C structure (that is, a circuit structure including eight thin film transistors and a storage capacitor), and a 12T1C structure (also That is, a circuit structure including twelve thin film transistors and one storage capacitor).
  • FIG. 7 is a schematic diagram of a GOA 150 using a 4T1C circuit structure as the GOA unit 151 provided by at least one embodiment of the present disclosure.
  • the GOA 150 includes a plurality of GOA units 151 connected in sequence.
  • the GOA shown in FIG. 7 only shows GOA units of the nth and n+1th stages.
  • the structure of the GOA unit is illustrated below by taking the GOA unit of the nth level as an example.
  • the GOA unit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a first capacitor C1.
  • the first pole of the first transistor T1 is connected to the clock signal CLK, and the second pole of the first transistor T1 is connected to the first pole of the second transistor T2 to obtain the output terminal Oup of the GOA unit.
  • the output terminal Oup can output the gate scanning signal G(n) for the pixel unit of the nth row (the signal is a square wave pulse signal, and the pulse part is at the on level instead of the pulse part at the off level).
  • the output terminal Oup of the GOA unit is electrically connected to the signal input terminal InP of the next-stage GOA unit to provide the gate scan signal G(n) (as the next-stage GOA unit) to the next-stage GOA unit Input signal or turn on signal).
  • the gate of the first transistor T1 is connected to the pull-up node PU, thereby connecting the first electrode of the third transistor T3 and the second electrode of the fourth transistor T4.
  • the second electrode of the second transistor T2 is connected to the second electrode of the third transistor T3 and the second power terminal (providing a low-level signal VGL).
  • the gate of the second transistor T2 is connected to the gate of the third transistor T3 to obtain the reset control signal terminal RST.
  • the reset control signal terminal RST is connected to the output terminal Oup of the GOA unit of the next stage (that is, the n+1th stage) to receive the output of the next stage (that is, the n+1th stage)
  • the gate scan signal G(n+1) provided by the output terminal Oup of the GOA unit is used as an output pull-down control signal (that is, a reset control signal).
  • the first pole of the second transistor T2 is connected to the second pole of the first transistor T1, so the second transistor T2 can be turned on under the control of the pull-down control signal, thereby resetting the GOA unit of the nth stage, that is, without When the GOA of the nth stage outputs the gate scan signal G(n), the output signal provided by the output terminal Oup of the GOA unit of the nth stage is pulled down to the low-level signal VGL.
  • the reset control signal terminal RST of the GOA unit of the n+1th stage receives the gate scan signal G(n+2) provided by the output terminal of the GOA unit of the n+2th stage.
  • the first pole of the third transistor T3 is also connected to the pull-up node PU, thereby being electrically connected to the second pole of the fourth transistor T4 and the gate of the first transistor T1.
  • the second electrode of the third transistor T3 is connected to the low-level signal VGL.
  • the gate of the third transistor T3 is also connected to the output terminal Oup of the GOA unit of the next stage (that is, the n+1th stage) to receive the gate scan signal G(n+1) as a pull-down control signal (that is, , The reset control signal), so that the third transistor T3 can be turned on under the control of the reset control signal to reset the pull-up node PU to the low-level signal VGL, thereby turning off the first transistor T1.
  • the first electrode of the fourth transistor T4 is connected to the gate of the fourth transistor T4 to obtain the signal input terminal InP of the GOA unit.
  • the signal input terminal InP is connected to the GOA unit of the previous stage (that is, the n-1th stage)
  • the output terminal Oup is connected to receive the gate scan signal G(n-1) provided by the output terminal Oup of the GOA unit of the previous stage as an input signal (and an input control signal);
  • the second electrode of the fourth transistor T4 is connected to The pull-up node PU is connected, so that the pull-up node PU can be charged when the fourth transistor T4 is turned on, so that the voltage of the pull-up node PU can turn on the first transistor T1, so that the clock signal CLK passes through the output of the GOA unit Terminal Oup output.
  • One end of the first capacitor C1 is connected to the gate of the first transistor T1, that is, the pull-up node PU, and the other end is connected to the second electrode of the first transistor T1, so that the level of the pull-up node PU can be stored and can be connected to the first transistor T1.
  • the level of the pull-up node PU is continued to be pulled up through its own bootstrap effect to improve the output performance.
  • the semiconductor base material included in the inorganic non-metallic trace is the same as the semiconductor base material included in the first transistor T1 to the fourth transistor T4 (for example, both are indium gallium zinc oxide).
  • At least one embodiment of the present disclosure provides a manufacturing method of a motherboard, the manufacturing method including: forming a plurality of test terminals, an electrostatic discharge line, a plurality of resistors, and a thin film transistor.
  • the multiple test terminals are electrically connected to the electrostatic discharge line via multiple resistors; at least one of the multiple resistors includes inorganic non-metal wiring, and the thin film transistor includes an active layer; the same semiconductor base material is used to form the wiring and the active Floor.
  • forming a plurality of resistors and thin film transistors includes the following steps S101 to S104.
  • Step S101 forming a semiconductor base material layer 181 (see FIG. 8A).
  • the semiconductor base material layer 181 may be made of an oxide semiconductor material or a polysilicon material.
  • the oxide semiconductor material is indium gallium zinc oxide (IGZO).
  • Step S102 patterning the semiconductor base material layer 181 to form a first pattern 182 and a second pattern 183.
  • a first pattern 182 and a second pattern 183 is shown in FIG. 8B.
  • the method for patterning the semiconductor base material layer 181 can refer to the related technology, which will not be repeated here.
  • Step S103 Conduct the first pattern 182 (see FIG. 8D) to form a wiring 120.
  • the conductorization includes at least one of doping and plasma treatment.
  • the second pattern 183 includes a first area 1831, a second area 1832, and a third area 1833 located between the first area 1831 and the second area 1832. While conducting the conductorization of the first pattern 182, the manufacturing method further includes conducting the first region 1831 and the second region 1832 to form the source region 144 and the drain region 145 of the active layer, respectively. For example, when conducting conduction, the third region 1833 is shielded, and therefore, the third region 1833 is not conductorized to form the channel region 146 of the active layer.
  • the inorganic non-metal is formed by using a method of conducting a semiconductor base material (the same semiconductor base material as the inorganic non-metal trace and the active layer of the thin film transistor of at least one of the gate drive circuit and the pixel drive circuit).
  • the wiring can better control the conductivity of the inorganic non-metallic wiring without increasing the complexity of the process, thereby improving the design freedom while improving the yield of the motherboard.

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Abstract

一种母板(100)及其制作方法，该母板(100)包括至少一个显示区域(101)、围绕所述至少一个显示区域(101)的周边区域、多个测试端子(111)、静电释放线(112)、多个电阻(113)以及至少一个薄膜晶体管。多个测试端子(111)、静电释放线(112)、多个电阻(113)位于周边区域中；至少一个薄膜晶体管位于至少一个显示区域(101)和周边区域的至少一个中。多个测试端子(111)分别经由多个电阻(113)与静电释放线(112)电连接；多个电阻(113)中的至少一个包括无机非金属走线；至少一个薄膜晶体管包括有源层；无机非金属走线与至少一个薄膜晶体管的有源层包括相同的半导体基体材料。该母板(100)及其制作方法可以提升良率。

Description

母板及其制作方法 技术领域
本公开的实施例涉及一种母板及其制作方法。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示器件具有视角宽、对比度高、响应速度快等特点。并且，相比于无机发光显示器件，有机发光二极管显示器件具有更高的发光亮度、更低的驱动电压等优势。由于具有上述特点和优势，有机发光二极管(OLED)显示器件逐渐受到人们的广泛关注并且可以适用于手机、显示器、笔记本电脑、数码相机、仪器仪表等具有显示功能的装置。
发明内容
本公开的至少一个实施例提供了一种母板，该母板包括至少一个显示区域、围绕所述至少一个显示区域的周边区域、多个测试端子、静电释放线、多个电阻以及至少一个薄膜晶体管。所述多个测试端子、所述静电释放线、所述多个电阻位于所述周边区域中；所述至少一个薄膜晶体管位于所述至少一个显示区域和所述周边区域的至少一个中；所述多个测试端子分别经由所述多个电阻与所述静电释放线电连接；所述多个电阻中的至少一个包括无机非金属走线；所述至少一个薄膜晶体管包括有源层；以及所述无机非金属走线与所述至少一个薄膜晶体管的有源层包括相同的半导体基体材料。
例如，在所述母板的至少一个示例中，所述半导体基体材料为氧化物半导体材料。
例如，在所述母板的至少一个示例中，所述氧化物半导体材料为铟镓锌氧化物。
例如，在所述母板的至少一个示例中，所述有源层包括源极区、漏极区以及沟道区，所述沟道区位于所述源极区和所述漏极区之间；所述无机非金属走线的电导率高于所述沟道区的电导率；以及所述无机非金属走线的电导率不高于所述源极区的电导率和所述漏极区的电导率。
例如，在所述母板的至少一个示例中，所述无机非金属走线含有掺杂杂质，所述源极区和所述漏极区含有所述掺杂杂质；以及所述无机非金属走线中所述掺杂杂质的浓度不高于所述源极区和所述漏极区中所述掺杂杂质的浓度。
例如，在所述母板的至少一个示例中，所述沟道区不含有所述掺杂杂质。
例如，在所述母板的至少一个示例中，所述多个测试端子在第一方向上顺次布置，所述多个电阻在所述第一方向上顺次布置；以及所述多个测试端子和所述多个电阻在所述第一方向上交替布置。
例如，在所述母板的至少一个示例中，所述无机非金属走线包括折线走线，所述折线走线的第一端与所述多个测试端子中对应的一个测试端子电连接，以及所述折线走线的第二端与所述静电释放线电连接。
例如，在所述母板的至少一个示例中，所述折线走线包括在所述第一方向上顺次布置且彼此连接的多个第一折线单元。
例如，在所述母板的至少一个示例中，所述多个第一折线单元中至少一个包括在所述第一方向上顺次相接的第一线段、第二线段、第三线段和第四线段；所述第一线段和所述第三线段沿所述第一方向延伸，所述第二线段和所述第四线段沿与所述第一方向交叉的第二方向延伸；所述第一线段和所述第三线段在所述第二方向上间隔设置，所述第二线段和所述第四线段在所述第一方向上间隔设置；以及所述第一线段的终点与所述第二线段的起点相连，所述第二线段的终点与所述第三线段的起点相连，所述第三线段的终点与所述第四线段的起点相连。
例如，在所述母板的至少一个示例中，所述第二线段的长度等于相邻的两个测试端子在所述第一方向上的间距的1/16-1/2。
例如，在所述母板的至少一个示例中，所述第一折线单元在与所述第一方向交叉的第二方向上位于所述多个测试端子的上边缘所在的直线和所述多个测试端子的下边缘所在的直线之间。
例如，在所述母板的至少一个示例中，所述第一折线单元在所述第二方向的延伸长度等于所述多个测试端子在所述第二方向上的尺寸的1/2-4/5。
例如，在所述母板的至少一个示例中，所述折线走线的方阻为100欧姆-300欧姆。
例如，在所述母板的至少一个示例中，所述折线走线的物理长度与所述 折线走线的线宽的比值大于等于700且小于等于2000。
例如，在所述母板的至少一个示例中，所述折线走线为矩形折线或锯齿形折线。
例如，在所述母板的至少一个示例中，所述至少一个显示区域的每个包括并排延伸到所述至少一个显示区域的每个外的多根第一信号线；以及所述多个测试端子包括第一测试端子，所述多根第一信号线与所述第一测试端子电连接。
例如，在所述母板的至少一个示例中，所述至少一个显示区域的每个还包括并排延伸到所述至少一个显示区域的每个外的多根第二信号线；所述多根第一信号线与所述多根第二信号线交叉；所述多个测试端子还包括第二测试端子；以及所述多根第二信号线与所述第二测试端子电连接。
例如，在所述母板的至少一个示例中，所述母板还包括栅极驱动电路。所述栅极驱动电路位于所述周边区域中且包括所述至少一个薄膜晶体管中的第一数目的薄膜晶体管；以及所述第一数目小于等于所述至少一个薄膜晶体管的数目。
例如，在所述母板的至少一个示例中，所述至少一个显示区域的每个还包括阵列排布的多个子像素；每个所述子像素包括像素驱动电路和发光元件；所述像素驱动电路包括所述至少一个薄膜晶体管中的第二数目的薄膜晶体管且配置为驱动所述发光元件；以及所述第二数目小于等于所述至少一个薄膜晶体管的数目。
例如，在所述母板的至少一个示例中，所述母板还包括位于静电释放线与所述多个电阻之间的绝缘层。所述绝缘层包括多个过孔，所述静电释放线与所述多个电阻分别经由所述多个过孔电连接。
本公开的至少一个实施例提供了一种母板的制作方法，所述母板包括至少一个显示区域和围绕所述至少一个显示区域的周边区域，该制作方法包括：在所述周边区域中形成多个测试端子、静电释放线以及多个电阻；以及在所述至少一个显示区域和所述周边区域的至少一个中形成至少一个薄膜晶体管。所述多个测试端子分别经由所述多个电阻与所述静电释放线电连接；所述多个电阻中的至少一个的包括无机非金属走线，所述至少一个薄膜晶体管包括有源层；以及使用相同的半导体基体材料形成所述走线与所述有源层。
例如，在所述制作方法的至少一个示例中，所述在所述周边区域中形成 所述多个电阻以及在所述至少一个显示区域和所述周边区域的至少一个中形成所述至少一个薄膜晶体管包括：形成半导体基体材料层；对所述半导体基体材料层进行图案化，以形成第一图案和第二图案；对所述第一图案进行导体化，以形成所述走线。所述第二图案用于形成所述至少一个薄膜晶体管的有源层。
例如，在所述制作方法的至少一个示例中，所述有源层包括源极区、漏极区以及沟道区，所述沟道区位于所述源极区和所述漏极区之间；以及所述制作方法还包括：对于所述第二图案的部分导体化以形成所述源极区和所述漏极区，且不对所述第二图案的部分进行导体化以形成所述沟道区。
例如，在所述制作方法的至少一个示例中，所述导体化包括掺杂和等离子体处理中的至少一个。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A是一种母板；
图1B是图1A所示的母板的多个测试端子、静电释放线和多个电阻的连接关系的等效示意图；
图1C是图1A所示的电阻的放大图；
图2是本公开至少一个实施例的提供的母板的平面示意图；
图3A是本公开至少一个实施例的提供的母板的另一个平面示意图；
图3B是图3A所述的母板的显示区域和第一周边区域的平面示意图；
图3C是本公开至少一个实施例提供的母板的薄膜晶体管的有源层的平面示意图；
图4A示出了本公开至少一个实施例提供的电阻的折线走线的一个平面示意图；
图4B是图2所示的母板的测试端子以及电阻的折线走线的平面示意图；
图4C示出了本公开至少一个实施例提供的电阻的折线走线的另一个示例；
图5是本公开至少一个实施例提供的静电释放线与多个电阻连接关系的 界面示意图；
图6是本公开至少一个实施例提供的3T1C像素电路的示意图；
图7是本公开至少一个实施例提供的将4T1C电路结构作为GOA单元的GOA的示意图；以及
图8A-图8D示出了本公开至少一个实施例提供的电阻和薄膜晶体管的制作方法。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1A是一种母板500。如图1A所示，该母板500包括至少一个显示区域501和围绕至少一个显示区域501的周边区域(图中未标注)；周边区域包括多个测试端子(pad)511、静电释放线512和多个电阻513。
图1B是图1A所示的母板500的多个测试端子511、静电释放线512和多个电阻513的连接关系的等效示意图。如图1B所示，多个测试端子511分别经由多个电阻513与静电释放线512电连接。
如图1A所示，显示区域501包括并排延伸到显示区域501外的多根信号线(图1A未示出信号线的位于显示区域501的部分)，多个测试端子511 分别经由多根短路连接线514(例如，短路环)与对应的信号线电连接。
如图1A所示，多个测试端子511在第一方向D1上顺次布置，多个电阻513在第一方向D1上顺次布置；多个测试端子511和多个电阻513在第一方向D1上交替布置。
例如，多根信号线包括多根第一信号线和多根第二信号线，多根第一信号线和多根第二信号线分别沿例如第一方向D1和第二方向D2延伸，多根第一信号线与多根第二信号线交叉；多个测试端子511包括第一测试端子5111和第二测试端子5112；多根第一信号线与第一测试端子5111电连接；多根第二信号线与第二测试端子5112电连接。例如，第一信号线和第二信号线分别为栅线和数据线。
例如，显示区域501还包括阵列排布的多个子像素，每个子像素包括像素驱动电路和发光元件，像素驱动电路配置为驱动发光元件。例如，发光元件为底发射型发光元件。例如，发光元件包括顺次设置的第一电极、发光层和第二电极。例如，第一电极和第二电极分别为阳极和阴极，发光层为有机发光层。例如，第一电极对发光层发射的光线具有第一反射率，第二电极对发光层发射的光线具有第二反射率，且第一反射率小于第二反射率，由此发光层发射的光线经由第一电极离开发光元件，也即，发光元件为底发射型发光元件。例如，第一电极由透明导电材料形成；例如，透明导电材料为氧化铟锡(ITO)或氧化铟锌(IZO)。
图1C是图1A所示的电阻513的放大图。例如，如图1C所示，多个电阻513的至少一个实现为走线，且走线的材料与第一电极的材料相同。例如，走线与第一电极在同一图案化工艺中形成。例如，走线可以由氧化铟锡(ITO)形成。
本公开的发明人注意到，由于每个测试端子511与多根信号线相连，因此，在至少一个测试端子511上聚集了大量的静电电荷，且测试端子511未与静电释放线512相连的情况下，聚集了大量的静电电荷的测试端子511可能会导致静电释放引发的不良(例如，静电电荷聚集引发的烧毁现象)。
例如，在多个测试端子511分别经由多个电阻513与静电释放线512相连的情况下，聚集了大量的静电电荷的测试端子511上的静电电荷可以经由静电释放线512朝向与其相邻的测试端子511传递。例如，在静电电荷朝向其它测试端子511传递的过程中，对应的电阻513将损耗至少部分静电电荷， 以保护与其它测试端子511电连接的结构。
本公开的发明人注意到，在每个电阻513的电阻大于7万欧姆的情况下，电阻513能够有效损耗静电电荷。本公开的发明人注意到，在电阻513的走线与顶发射型发光元件的第一电极(例如，阳极)在同一图案化工艺中形成的情况下，由于第一电极的电导率较大，为了使得每个电阻513的电阻大于7万欧姆，每个电阻513的走线的物理长度较长；由于相邻的测试端子511在第一方向D1上的间距有限，因此，需要通过绕线的方式对走线进行排布(也即，电阻513的走线为折线走线)，且折线走线的并列布置的线段之间的间距较小，由此增加的制作难度，并降低了折线走线的良率(例如，折线走线的并列布置且相邻的线段可能存在短路，或者折线走线存在因降低走线宽度导致的断路)。需要说明的是，走线的物理长度是指在假设将走线拉伸为平行于第一方向上的直线时，走线在第一方向上的长度。
此外，本公开的发明人还注意到，使得电阻513的走线与发光元件的第一电极(例如，阳极)在同一图案化工艺中形成的技术方案应用范围较窄。例如，在发光元件实现为顶发射型发光元件的情况下，则难以使用上述技术方案，这是因为顶发射型发光元件的阳极的电导率大于底发射型发光元件的阳极的电导率(由于顶发射型发光元件的阳极包括金属材料)。又例如，不包括自发光型发光元件的母板(例如，用于形成液晶显示面板的母板)也难以使用上述技术方案。
本公开的至少一个实施例提供了一种母板及其制作方法，该母板包括至少一个显示区域、围绕至少一个显示区域的周边区域、多个测试端子、静电释放线、多个电阻以及至少一个薄膜晶体管。多个测试端子、静电释放线、多个电阻位于周边区域中；至少一个薄膜晶体管位于至少一个显示区域和周边区域的至少一个中；多个测试端子分别经由多个电阻与静电释放线电连接；多个电阻中的至少一个包括无机非金属走线；至少一个薄膜晶体管包括有源层；以及无机非金属走线与至少一个薄膜晶体管的有源层包括相同的半导体基体材料。该母板及其制作方法可以提升良率。
下面通过几个示例对根据本公开实施例提供的母板进行非限制性的说明，如下面所描述的，在不相互抵触的情况下这些具体示例中不同特征可以相互组合，从而得到新的示例，这些新的示例也都属于本公开保护的范围。
图2是本公开至少一个实施例的提供的母板100的平面示意图。如图2 所示，该母板100包括多个测试端子111、静电释放线112和多个电阻113。如图2所示，母板100还包括至少一个显示区域101和围绕至少一个显示区域101的周边区域(图2中未标注)，多个测试端子111、静电释放线112和多个电阻113均位于周边区域中。
需要说明的是，为清楚起见，图2和其它附图仅示出了一个显示区域101以及围绕该显示区域101的周边区域，但本公开的实施例不限于此。例如，该母板100可以包括阵列排布的多个显示区域101以及分别围绕多个显示区域101的多个周边区域，此处不再赘述。
例如，如图2所示，多个测试端子111在第一方向D1上顺次布置，多个电阻113在第一方向D1上顺次布置；多个测试端子111和多个电阻113在第一方向D1上交替布置。
例如，如图2所示，多个测试端子111分别经由多个电阻113与静电释放线112电连接。例如，多个电阻113中的至少一个(例如，多个电阻113中的每个)包括无机非金属走线，如图2所示，无机非金属走线包括折线走线。例如，如图2所示，折线走线的第一端1131与多个测试端子111中对应的一个测试端子111电连接，以及折线走线的第二端1132与静电释放线112电连接。
图3A是本公开至少一个实施例的提供的母板100的另一个平面示意图。图3A所示的母板100的平面示意图与图2所示的母板100的平面示意图相似，区别主要在于，图3A所示的母板100的平面示意图还示出了显示区域101中的多根第一信号线141和多根第二信号线142。
例如，如图3A所示，显示区域101包括并排延伸到显示区域101外的多根第一信号线141；多个测试端子111包括第一测试端子1111，多根第一信号线141与第一测试端子1111电连接。例如，如图3A所示，显示区域101还包括并排延伸到显示区域101外的多根第二信号线142；多根第一信号线141与多根第二信号线142交叉；多个测试端子111还包括第二测试端子1112；多根第二信号线142与第二测试端子1112电连接。
例如，如图3A所示，周边区域还包括多根短路连接线114，多根短路连接线114与多个测试端子111例如一一对应。
例如，如图3A所示，母板100包括两个第一测试端子1111和两个第二测试端子1112；多根短路连接线114包括两根第一短路连接线1141和两根第 二短路连接线1142；一个第一测试端子1111经由一根第一短路连接线1141与位于奇数行的第一信号线141电连接，另一个第一测试端子1111经由另一根第一短路连接线1141与位于偶数行的第一信号线141电连接；一个第二测试端子1112经由一根第二短路连接线1142与位于奇数列的第二信号线142电连接，另一个第二测试端子1112经由另一根第二短路连接线1142与位于偶数列的第二信号线142电连接。
例如，如图3A所示，第一信号线141和第二信号线142分别沿第一方向D1和第二方向D2延伸，第一方向D1和第二方向D2例如垂直。例如，第一信号线141和第二信号线142分别为栅线和数据线。
例如，如图3A所示，多个测试端子111还包括一个第三测试端子1113，多根短路连接线114包括一根第三短路连接线1143；显示区域101包括延伸到显示区域101外的公共电极线(图中未示出公共电极线的位于显示区域101的部分)，公共电极线经由第三短路连接线1143与第三测试端子1113电连接。
例如，如图3A所示，周边区域包括围绕显示区域101的第一周边区域102以及围绕第一周边区域102的第二周边区域103，第一周边区域102位于显示区域101和第二周边区域103之间；多个测试端子111、静电释放线112和多个电阻113均位于第二周边区域103。
例如，在本公开的上述实施例提供的母板100在完成了制备、测试等工序之后，将进行切割，最后得到单个独立的显示面板，所得到的独立的显示面板再进行后续的工序。例如，所得到的单个面板中仍保留第一周边区域102，但第二周边区域103的至少部分(例如，第二周边区域103的全部)被切割掉，因此，所得到的单个面板中可不保留测试端子111、静电释放线112、电阻113和短路连接线114。
在一些示例中，所得到的单个面板中也可以保留测试端子111、静电释放线112、电阻113和短路连接线114的至少一个。
图3B是图3A所述的母板100的显示区域101和第一周边区域102的平面示意图。例如，如图3B所示，母板100还包括栅极驱动电路117。栅极驱动电路117位于周边区域(第一周边区域102)中且包括薄膜晶体管(图3B未示出)。如图3B所示，栅极驱动电路117的多个信号输出端与多根第一信号线(例如，栅线)141电连接，以为多根栅线提供栅极扫描信号。例如，周边区域(第一周边区域102)还包括数据驱动电路，数据驱动电路的多个信号 输出端与多根第二信号线(例如，数据线)电连接，以为多根数据线提供数据信号。例如，如图3B所示，显示区域101还包括阵列排布的多个子像素143，每个子像素143包括像素驱动电路和发光元件，像素驱动电路包括薄膜晶体管(图3B未示出)且配置为驱动发光元件。为清楚起见，栅极驱动电路117和子像素143的结构将在图6和图7所示的示例进行描述，此处不再赘述。
例如，无机非金属走线可以包括半导体基体(matrix)材料。例如，无机非金属走线与栅极驱动电路117和像素驱动电路至少之一的薄膜晶体管的有源层包括相同的半导体基体材料。例如，半导体基体材料为氧化物半导体材料或多晶硅材料。例如，氧化物半导体材料为铟镓锌氧化物。
例如，通过使得无机非金属走线与栅极驱动电路117和像素驱动电路至少之一的薄膜晶体管的有源层包括相同的半导体基体材料，可以使得降低无机非金属走线的电导率，由此在保证无机非金属走线能够有效损耗静电电荷的情况下(例如，使得无机非金属走线的电阻大于7万欧姆的情况下)，使得无机非金属走线的物理长度尽可能的短；此种情况下，可以降低无机非金属走线和折线走线的绕线次数，以及折线走线的并列布置且相邻的线段之间的间距(例如，图4A所示的相邻的第一线段122和第三线段124在第二方向D2上的间距)，由此可以降低无机非金属走线的制造难度和良率。
例如，通过使得无机非金属走线与栅极驱动电路117和像素驱动电路至少之一的薄膜晶体管的有源层包括相同的半导体基体材料，使得还可以利用薄膜晶体管的制作工艺来制作无机非金属走线，由此可以简化本公开的至少一个实施例提供的母板100的制作工艺。
例如，通过使得无机非金属走线与栅极驱动电路117和像素驱动电路至少之一的薄膜晶体管的有源层包括相同的半导体基体材料，还可以使得本公开的至少一个实施例提供的母板100适用于形成具有顶发射发光元件的显示面板、具有底发射型的发光元件的显示面板、液晶显示面板或者其它具有薄膜晶体管的显示面板。
图3C是本公开至少一个实施例提供的母板100的薄膜晶体管的有源层的平面示意图。如图3C所示有源层包括源极区144、漏极区145以及沟道区146，沟道区146位于源极区144和漏极区145之间。例如，无机非金属走线的电导率高于沟道区146的电导率(例如，在薄膜晶体管未导通情况下的沟道区146的电导率)。例如，无机非金属走线的电导率不高于源极区144的电导率 和漏极区145的电导率。
例如，通过使得无机非金属走线的电导率高于沟道区146的电导率，可以在保证有效损耗静电电荷的情况下，使得静电电荷能够沿静电释放线112朝向其它测试端子111传输。
例如，可以通过对形成无机非金属走线的半导体基体材料进行导体化来提升无机非金属走线的电导率。例如，对形成无机非金属走线的半导体基体材料进行导体化的方法可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。例如，导体化包括掺杂和等离子体处理中的至少一个。例如，通过掺杂或等离子体处理进行导体化的方法可以参照相关技术，在此不再赘述。
例如，通过采用对半导体基体材料(与无机非金属走线与栅极驱动电路117和像素驱动电路至少之一的薄膜晶体管的有源层的半导体基体材料相同的半导体基体材料)进行导体化的方法来形成无机非金属走线可以在不增加工艺复杂度的情况下更好的控制无机非金属走线的电导率，由此可以在提升母板100的良率的情况下提升设计自由度。
例如，无机非金属走线(折线走线)的方阻位于100欧姆-300欧姆之间(例如，200欧姆)。例如，走线的方阻等于走线材料的电导率与走线的厚度的比值。例如，折线走线的物理长度与折线走线的线宽的比值大于等于700且小于等于2000(例如，1000-1500；例如，1200)。例如，由于折线走线的电阻值等于折线走线的方阻与折线走线的物理长度与折线走线的线宽的比值的乘积，因此，折线走线(或电阻113)的电阻值位于7万欧姆-60万欧姆之间(例如，10万欧姆-45万欧姆；例如，24万欧姆)。
例如，对形成无机非金属走线的半导体基体材料进行导体化的方法可以与对薄膜晶体管的半导体层的部分区域进行导体化以形成源极区144和漏极区145的方法相同。
例如，无机非金属走线含有掺杂杂质，源极区144和漏极区145含有掺杂杂质。例如，沟道区146不含有掺杂杂质或者沟道区146含有的掺杂杂质与源极区144和漏极区145含有的掺杂杂质不同。例如，无机非金属走线含有的掺杂杂质与源极区144和漏极区145含有的掺杂杂质相同。例如，无机非金属走线、源极区144和漏极区145经由同一图案化工艺和同一掺杂工艺形成。例如，无机非金属走线中上述掺杂杂质的浓度不高于源极区144和漏 极区145中上述掺杂杂质的浓度。
折线走线的具有形状可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。例如，图2和图3A所示的折线走线可以为矩形折线、锯齿形折线或者具有其它适用形状的走线。下面结合图4A-图4C进行示例性说明。
图4A示出了本公开至少一个实施例提供的电阻113的折线走线的一个示例。如图4A所示，折线走线包括在第一方向D1上顺次布置且彼此连接的多个第一折线单元121。多个第一折线单元121中至少一个(例如，多个第一折线单元121的每个)包括在第一方向D1上顺次相接的第一线段122、第二线段123、第三线段124和第四线段125；第一线段122和第三线段124沿第一方向D1延伸，第二线段123和第四线段125沿与第一方向D1交叉的第二方向D2延伸；第一线段122和第三线段124在第二方向D2上间隔设置，第二线段123和第四线段125在第一方向D1上间隔设置；第一线段122的终点与第二线段123的起点相连，第二线段123的终点与第三线段124的起点相连，第三线段124的终点与第四线段125的起点相连。例如，多个第一折线单元121中与测试端子111相邻的第一折线单元121的第一线段122的起点实现为折线走线的第一端。
如图4A所示，折线走线还包括第二折线单元128；第二折线单元128包括在第一方向D1上顺次布置的第五线段126和第六线段127；第五线段126沿第一方向D1延伸，第六线段127沿第二方向D2延伸；第四线段125的终点与第五线段126的起点相连，第五线段126的终点与第六线段127的起点相连，第六线段127的终点与静电释放线112电连接。
例如，第一线段122和第三线段124的长度小于第二线段123和第四线段125长度。例如，第五线段126的长度小于第六线段127的长度。例如，可以将第二线段123、第四线段125和第六线段127作为彼此串联的子电阻，第一线段122、第三线段124和第五线段126作为连接相邻的子电阻的走线；此种情况下，多个电阻113中的至少一个(例如，多个电阻113中的每个)可以看做电阻串。
例如，如图4A所示，多个第一线段122的长度不完全相同，多个第三线段124的长度不完全相同，多个第二线段123和多个第四线段125的长度相同，但本公开的实施例不限于此。又例如，多个第一线段122和多个第三线 段124的长度完全相同，多个第二线段123和多个第四线段125的长度相同。再例如，多个第一线段122和多个第三线段124的长度完全相同，多个第二线段123的长度不完全相同，多个第四线段125的长度不完全相同。
图4B示出了图2所示的母板100的测试端子111以及电阻113的折线走线的平面示意图。如图4B所示，第一折线单元121在与第一方向D1交叉的第二方向D2上位于多个测试端子111的上边缘所在的直线(图4B所示的位于上侧的虚线)和多个测试端子111的下边缘所在的直线(图4B所示的位于下侧的虚线)之间。例如，通过使得第一折线单元121在第二方向D2上位于多个测试端子111的上边缘所在的直线和多个测试端子111的下边缘所在的直线之间，可以避免第一折线单元121额外占用周边区域的空间，由此有利于降低母板100的尺寸。
例如，如图2和图4B所示，第一折线单元121在第二方向D2的延伸长度等于多个测试端子111在第二方向D2上的尺寸的1/2-4/5(例如，2/3)。例如，第一折线单元121在第二方向D2的延伸长度是指第一折线单元121在第二方向D2的最大长度；例如，第一折线单元121在第二方向D2的延伸长度等于第二线段123和第四线段125在第二方向D2上的长度。
例如，第二线段123的长度(或/和第四线段125的长度)等于相邻的两个测试端子111在第一方向D1上的间距的1/16-1/2(例如，1/5-1/3，例如，1/4)。例如，通过使得第二线段123的长度等于相邻的两个测试端子111在第一方向D1上的间距的1/16-1/2，可以增大相邻的第一线段122和第三线段124在第一方向D1上的间距，此种情况下，可以降低相邻的第一线段122和第三线段124存在短路的可能性或者可以降低因走线宽度较小导致的断路的可能性，由此可以提升折线走线和母板100的良率。
例如，折线走线的线宽为10微米-20微米(例如，等于10微米、15微米或20微米)。例如，折线走线具有均一的线宽，此种情况下，折线走线的线宽等于第二线段123的宽度，第二线段123的宽度等于第二线段123在垂直于第二线段123的延伸方向上的宽度。在一些示例中，折线走线还可以具有不均一的线宽。例如，第一线段122和第三线段124的线宽大于第二线段123和第四线段125的线宽。
图4C示出了本公开至少一个实施例提供的电阻113的折线走线的另一个示例。如图4C所示，电阻113的折线走线为锯齿形走线。
图5是本公开至少一个实施例提供的静电释放线112与多个电阻113(电阻113的折射走线的第二端)连接关系的截面示意图。如图5所示，母板100还包括位于静电释放线112与多个电阻113之间的绝缘层115；绝缘层115包括多个过孔116，静电释放线112与多个电阻113分别经由多个过孔116电连接。例如，静电释放线112可以与薄膜晶体管的源极和漏极在同一个图案化工艺中形成，此种情况下，绝缘层115可以与薄膜晶体管的钝化层在同一图案化工艺中形成。又例如，静电释放线112还可以与薄膜晶体管的栅极在同一个图案化工艺中形成，此种情况下，绝缘层115可以与薄膜晶体管的栅绝缘层115在同一图案化工艺中形成。
下面结合图6对本公开至少一个实施例提供的子像素的像素驱动电路和发光元件进行示例性说明。例如，本公开至少一个实施例提供的子像素的像素驱动电路可以为2T1C像素电路(也即，包括两个薄膜晶体管一个存储电容的像素电路)、3T1C像素电路(也即，包括三个薄膜晶体管一个存储电容的像素电路)、4T1C像素电路(也即，包括四个薄膜晶体管一个存储电容的像素电路)或其它适用的像素电路。
图6是本公开至少一个实施例提供的3T1C像素电路的示意图。例如，如图6所示，像素电路包括驱动晶体管CT3(包括栅极、第一极和第二极)、开关晶体管CT1、感测晶体管CT2和存储电容Cst。例如，无机非金属走线包括的半导体基体材料与开关晶体管CT1、感测晶体管CT2和驱动晶体管CT3包括的半导体基体材料均相同(例如，均为铟镓锌氧化物)。
例如，如图6所示，开关晶体管CT1作为输入写入开关，开关晶体管CT1的栅极作为控制端G1与栅线(图6中未示出，参见图3B的第一信号线141)连接以接收栅极扫描信号，开关晶体管CT1的第一极和开关晶体管CT1的第二极分别与数据线(第二信号线142)和驱动晶体管CT3的栅极连接，以分别接收数据电压以及将接收的数据电压施加至驱动晶体管CT3的栅极；存储电容Cst的第一端和第二端分别与驱动晶体管CT3的栅极和驱动晶体管CT3的第一极连接，从而存储施加至驱动晶体管CT3的栅极和存储电容Cst的第一端的数据电压。
例如，如图6所示，感测晶体管CT2作为感测开关，感测晶体管CT2的第一极与驱动晶体管CT3的第一极连接；感测晶体管CT2的第二极与感测线SENL连接，以用于对于与感测线SENL相关的电容充电以形成感测电压，由 此可以通过该感测线SENL实现对感测电压的检测；感测晶体管CT2的栅极作为控制端G2与感测扫描线(图6中未示出，参见图3B的第一信号线141)连接以接收感测控制信号。例如，根据实际应用需求，像素电路还连接到第一电源端VDD和第二电源端VSS。例如，第一电源端VDD提供的电压大于第二电源端VSS提供的电压。
例如，在感测线SENL上有寄生电容Cvc和寄生电阻Rvc的情况下，如图6所示，该寄生电容Cvc可以被来自驱动晶体管CT3的电流充电，从而相应的感测线SENL上的电压发生改变。然而，本公开的实施例不限于此，除利用感测线SENL上的寄生电容Cvc之外，也可以单独提供一端与感测线SENL连接而另一端例如与某一固定电压(例如接地)的感测电容Csc。
例如，控制端G1和控制端G2连接至不同的扫描线(例如，不同的第一信号线141)，以使得开关晶体管CT1和感测晶体管CT2可以在不同的时间处于开启状态。例如，驱动晶体管CT3、开关晶体管CT1和感测晶体管CT2均为N型晶体管。
例如，发光元件包括顺次设置的第一电极、发光层和第二电极。例如，第一电极和第二电极分别为阳极和阴极，发光层为有机发光层。例如，第一电极对发光层发射的光线具有第一反射率，第二电极对发光层发射的光线具有第二反射率，且第一反射率大于第二反射率，由此发光层发射的光线经由第二电极离开发光元件，也即，发光元件为顶发射型发光元件。例如，第一电极包括金属材料；例如，第二电极由透明导电材料形成。
下面结合图7对本公开至少一个实施例提供的母板的栅极驱动电路进行示例性说明。栅极驱动电路可以实现为GOA(Gate on Array，阵列基板上栅驱动集成)。例如，在母板的栅极驱动电路117实现为GOA的情况下，相比于采用栅极驱动电路实现为栅极驱动芯片(IC)示例，可以降低由母板获得的显示面板的边框尺寸，降低显示面板的制作材料成本。
例如，GOA可以包括顺次级联的多个GOA单元(也即，移位寄存器)。例如，GOA单元可以实现为4T1C电路结构(也即，包括四个薄膜晶体管一个存储电容的电路结构)、8T1C结构(也即，包括八个薄膜晶体管一个存储电容的电路结构)和12T1C结构(也即，包括十二个薄膜晶体管一个存储电容的电路结构)。
图7是本公开至少一个实施例提供的将4T1C电路结构作为GOA单元151 的GOA 150的示意图。
如图7所示，GOA 150包括顺次级联的多个GOA单元151。为清楚起见，图7所示的GOA仅示出了第n级和第n+1级的GOA单元。下面以第n级的GOA单元为例对GOA单元的结构做示例性说明。
如图7所示，GOA单元包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第一电容C1。
如图7所示，第一晶体管T1的第一极连接时钟信号CLK，第一晶体管T1的第二极连接第二晶体管T2的第一极以得到该GOA单元的输出端Oup，该GOA单元的输出端Oup可输出用于第n行像素单元的栅极扫描信号G(n)(该信号为方波脉冲信号，相应地脉冲部分为开启电平而非脉冲部分为关断电平)。如图7所示，GOA单元的输出端Oup与下一级GOA单元的信号输入端InP电连接，以向下一级GOA单元提供栅极扫描信号G(n)(作为下一级GOA单元的输入信号或开启信号)。第一晶体管T1的栅极连接上拉节点PU，并由此连接第三晶体管T3的第一极以及第四晶体管T4的第二极。
如图7所示，第二晶体管T2的第二极连接第三晶体管T3的第二极以及第二电源端(提供低电平信号VGL)。第二晶体管T2的栅极连接第三晶体管T3的栅极，以得到复位控制信号端RST。如图7所示，复位控制信号端RST与下一级(也即，第n+1级)的GOA单元的输出端Oup相连，以接收下一级(也即，第n+1级)的GOA单元的输出端Oup提供的栅极扫描信号G(n+1)以作为输出下拉控制信号(也即，复位控制信号)。第二晶体管T2的第一极连接第一晶体管T1的第二极，因此第二晶体管T2可以在下拉控制信号的控制下导通，由此使得第n级的GOA单元复位，也即，在无需第n级的GOA输出栅极扫描信号G(n)时将第n级的GOA单元的输出端Oup提供的输出信号下拉至低电平信号VGL。如图7所示，第n+1级的GOA单元的复位控制信号端RST接收第第n+2级的GOA单元的输出端提供的栅极扫描信号G(n+2)。
如图7所示，第三晶体管T3的第一极也连接至上拉节点PU，由此与第四晶体管T4的第二极以及第一晶体管T1的栅极电连接。第三晶体管T3的第二极连接至低电平信号VGL。第三晶体管T3的栅极同样连接下一级(也即，第n+1级)的GOA单元的输出端Oup，以接收栅极扫描信号G(n+1)以作为下拉控制信号(也即，复位控制信号)，从而第三晶体管T3可以在该复位 控制信号的控制下导通，将上拉节点PU复位至低电平信号VGL，从而关闭第一晶体管T1。
第四晶体管T4的第一极和第四晶体管T4的栅极相连，以得到GOA单元的信号输入端InP，该信号输入端InP与上一级(也即，第n-1级)的GOA单元的输出端Oup相连，以接收上一级的GOA单元的输出端Oup提供的栅极扫描信号G(n-1)以作为输入信号(以及输入控制信号)；第四晶体管T4的第二极与上拉节点PU连接，从而在第四晶体管T4导通时可以对上拉节点PU充电，以使上拉节点PU的电压可以将第一晶体管T1导通，从而使时钟信号CLK通过GOA单元的输出端Oup输出。
第一电容C1的一端连接第一晶体管T1的栅极即上拉节点PU，另一端连接第一晶体管T1的第二极，从而可以存储上拉节点PU的电平，并且可以在第一晶体管T1导通时通过自身的自举效应将上拉节点PU的电平继续上拉以提升输出性能。
例如，无机非金属走线包括的半导体基体材料与第一晶体管T1-第四晶体管T4包括的半导体基体材料均相同(例如，均为铟镓锌氧化物)。
需要说明的是，对于该母板的其它组成部分(例如，控制装置、图像数据编码/解码装置、时钟电路等)可以采用适用的部件，这些均是本领域的普通技术人员所应该理解的，在此不做赘述，也不应作为对本公开的限制。
本公开的至少一个实施例提供了一种母板的制作方法，该制作方法包括：形成多个测试端子、静电释放线、多个电阻以及薄膜晶体管。多个测试端子分别经由多个电阻与静电释放线电连接；多个电阻中的至少一个的包括无机非金属走线，薄膜晶体管包括有源层；使用相同的半导体基体材料形成走线与有源层。
下面结合图8A-图8D对电阻和薄膜晶体管的制作方法进行示例性说明。
例如，形成多个电阻和薄膜晶体管包括以下的步骤S101-步骤S104。
步骤S101：形成半导体基体材料层181(参见图8A)。例如，半导体基体材料层181可以由氧化物半导体材料或多晶硅材料。例如，氧化物半导体材料为铟镓锌氧化物(IGZO)。
步骤S102：对半导体基体材料层181进行图案化，以形成第一图案182和第二图案183。例如，第一图案182和第二图案183的一个示例如图8B所示。例如，对半导体基体材料层181进行图案化的方法可以参见相关技术， 在此不再赘述。
步骤S103：对第一图案182进行导体化(参见图8D)，以形成走线120。例如，导体化包括掺杂和等离子体处理中的至少一个。
例如，如图8C所示，第二图案183包括第一区域1831、第二区域1832以及位于第一区域1831、第二区域1832之间的第三区域1833。在对第一图案182进行导体化的同时，制作方法还包括对第一区域1831和第二区域1832进行导体化，以分别形成有源层的源极区144和漏极区145。例如，在进行导体化时，第三区域1833被遮挡，因此，第三区域1833未被导体化，以形成有源层的沟道区146。
例如，通过采用对半导体基体材料(与无机非金属走线与栅极驱动电路和像素驱动电路至少之一的薄膜晶体管的有源层相同的半导体基体材料)进行导体化的方法来形成无机非金属走线可以在不增加工艺复杂度的情况下更好的控制无机非金属走线的电导率，由此可以在提升母板的良率的情况下提升设计自由度。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (25)

  1. 一种母板，包括：至少一个显示区域、围绕所述至少一个显示区域的周边区域、多个测试端子、静电释放线、多个电阻以及至少一个薄膜晶体管，
    其中，所述多个测试端子、所述静电释放线、所述多个电阻位于所述周边区域中；
    所述至少一个薄膜晶体管位于所述至少一个显示区域和所述周边区域的至少一个中；
    所述多个测试端子分别经由所述多个电阻与所述静电释放线电连接；
    所述多个电阻中的至少一个包括无机非金属走线；
    所述至少一个薄膜晶体管包括有源层；以及
    所述无机非金属走线与所述至少一个薄膜晶体管的有源层包括相同的半导体基体材料。
  2. 根据权利要求1所述的母板，其中，所述半导体基体材料为氧化物半导体材料。
  3. 根据权利要求2所述的母板，其中，所述氧化物半导体材料为铟镓锌氧化物。
  4. 根据权利要求1-3任一所述的母板，其中，所述有源层包括源极区、漏极区以及沟道区，所述沟道区位于所述源极区和所述漏极区之间；
    所述无机非金属走线的电导率高于所述沟道区的电导率；以及
    所述无机非金属走线的电导率不高于所述源极区的电导率和所述漏极区的电导率。
  5. 根据权利要求4所述的母板，其中，所述无机非金属走线含有掺杂杂质，所述源极区和所述漏极区含有所述掺杂杂质；以及
    所述无机非金属走线中所述掺杂杂质的浓度不高于所述源极区和所述漏极区中所述掺杂杂质的浓度。
  6. 根据权利要求5所述的母板，其中，所述沟道区不含有所述掺杂杂质。
  7. 根据权利要求1-6任一所述的母板，其中，所述多个测试端子在第一方向上顺次布置，所述多个电阻在所述第一方向上顺次布置；以及
    所述多个测试端子和所述多个电阻在所述第一方向上交替布置。
  8. 根据权利要求7所述的母板，其中，所述无机非金属走线包括折线走 线，所述折线走线的第一端与所述多个测试端子中对应的一个测试端子电连接，以及所述折线走线的第二端与所述静电释放线电连接。
  9. 根据权利要求8所述的母板，其中，所述折线走线包括在所述第一方向上顺次布置且彼此连接的多个第一折线单元。
  10. 根据权利要求9所述的母板，其中，所述多个第一折线单元中至少一个包括在所述第一方向上顺次相接的第一线段、第二线段、第三线段和第四线段；
    所述第一线段和所述第三线段沿所述第一方向延伸，所述第二线段和所述第四线段沿与所述第一方向交叉的第二方向延伸；
    所述第一线段和所述第三线段在所述第二方向上间隔设置，所述第二线段和所述第四线段在所述第一方向上间隔设置；以及
    所述第一线段的终点与所述第二线段的起点相连，所述第二线段的终点与所述第三线段的起点相连，所述第三线段的终点与所述第四线段的起点相连。
  11. 根据权利要求10所述的母板，其中，所述第二线段的长度等于相邻的两个测试端子在所述第一方向上的间距的1/16-1/2。
  12. 根据权利要求8-11任一所述的母板，其中，所述第一折线单元在与所述第一方向交叉的第二方向上位于所述多个测试端子的上边缘所在的直线和所述多个测试端子的下边缘所在的直线之间。
  13. 根据权利要求12所述的母板，其中，所述第一折线单元在所述第二方向的延伸长度等于所述多个测试端子在所述第二方向上的尺寸的1/2-4/5。
  14. 根据权利要求8-13任一所述的母板，其中，所述折线走线的方阻为100欧姆-300欧姆。
  15. 根据权利要求8-14任一所述的母板，其中，所述折线走线的物理长度与所述折线走线的线宽的比值大于等于700且小于等于2000。
  16. 根据权利要求8或9所述的母板，其中，所述折线走线为矩形折线或锯齿形折线。
  17. 根据权利要求1-16任一所述的母板，其中，所述至少一个显示区域的每个包括并排延伸到所述至少一个显示区域的每个外的多根第一信号线；以及
    所述多个测试端子包括第一测试端子，所述多根第一信号线与所述第一 测试端子电连接。
  18. 根据权利要求17所述的母板，其中，所述至少一个显示区域的每个还包括并排延伸到所述至少一个显示区域的每个外的多根第二信号线；
    所述多根第一信号线与所述多根第二信号线交叉；
    所述多个测试端子还包括第二测试端子；以及
    所述多根第二信号线与所述第二测试端子电连接。
  19. 根据权利要求17或18所述的母板，还包括栅极驱动电路，
    其中，所述栅极驱动电路位于所述周边区域中且包括所述至少一个薄膜晶体管中的第一数目的薄膜晶体管；以及
    所述第一数目小于等于所述至少一个薄膜晶体管的数目。
  20. 根据权利要求17或18所述的母板，其中，所述至少一个显示区域的每个还包括阵列排布的多个子像素；
    每个所述子像素包括像素驱动电路和发光元件；
    所述像素驱动电路包括所述至少一个薄膜晶体管中的第二数目的薄膜晶体管且配置为驱动所述发光元件；以及
    所述第二数目小于等于所述至少一个薄膜晶体管的数目。
  21. 根据权利要求1-20任一所述的母板，还包括位于静电释放线与所述多个电阻之间的绝缘层，
    其中，所述绝缘层包括多个过孔，所述静电释放线与所述多个电阻分别经由所述多个过孔电连接。
  22. 一种母板的制作方法，所述母板包括至少一个显示区域和围绕所述至少一个显示区域的周边区域，包括：
    在所述周边区域中形成多个测试端子、静电释放线以及多个电阻；以及
    在所述至少一个显示区域和所述周边区域的至少一个中形成至少一个薄膜晶体管，
    其中，所述多个测试端子分别经由所述多个电阻与所述静电释放线电连接；
    所述多个电阻中的至少一个的包括无机非金属走线，所述至少一个薄膜晶体管包括有源层；以及
    使用相同的半导体基体材料形成所述走线与所述有源层。
  23. 根据权利要求22所述的制作方法，其中，所述在所述周边区域中形 成所述多个电阻以及在所述至少一个显示区域和所述周边区域的至少一个中形成所述至少一个薄膜晶体管包括：
    形成半导体基体材料层；
    对所述半导体基体材料层进行图案化，以形成第一图案和第二图案；
    对所述第一图案进行导体化，以形成所述走线，
    其中，所述第二图案用于形成所述至少一个薄膜晶体管的有源层。
  24. 根据权利要求23所述的制作方法，其中，所述有源层包括源极区、漏极区以及沟道区，所述沟道区位于所述源极区和所述漏极区之间；以及
    所述制作方法还包括：对于所述第二图案的部分导体化以形成所述源极区和所述漏极区，且不对所述第二图案的部分进行导体化以形成所述沟道区。
  25. 根据权利要求24所述的制作方法，其中，所述导体化包括掺杂和等离子体处理中的至少一个。
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