WO2021143846A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

Info

Publication number
WO2021143846A1
WO2021143846A1 PCT/CN2021/072161 CN2021072161W WO2021143846A1 WO 2021143846 A1 WO2021143846 A1 WO 2021143846A1 CN 2021072161 W CN2021072161 W CN 2021072161W WO 2021143846 A1 WO2021143846 A1 WO 2021143846A1
Authority
WO
WIPO (PCT)
Prior art keywords
fan
array substrate
pixel columns
power input
pixel
Prior art date
Application number
PCT/CN2021/072161
Other languages
English (en)
French (fr)
Inventor
刘冬妮
齐琪
曲峰
玄明花
郑皓亮
赵蛟
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/615,514 priority Critical patent/US11955075B2/en
Publication of WO2021143846A1 publication Critical patent/WO2021143846A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel and a display device.
  • the IR drop (voltage drop) on the anode or cathode traces will cause uneven brightness.
  • the horizontal IR drop is much larger than the vertical IR drop. Therefore, how to solve the horizontal IR drop of the display panel Drop is essential to improve the uniformity of the display panel's brightness.
  • an array substrate has a display area and a non-display area.
  • the non-display area includes a first binding area.
  • the array substrate includes a plurality of pixel columns arranged in the display area and at least three first power input terminals arranged in the first bonding area.
  • Each of the plurality of pixel columns includes a plurality of light-emitting units.
  • Each first power input terminal is connected to at least one pixel column of the plurality of pixel columns to provide a first power signal to the at least one pixel column.
  • different pixel columns connected to the first power input terminals are different.
  • the non-display area further includes a fan-out area, and the fan-out area is located between the display area and the first binding area.
  • the fan-out area includes at least three first fan-out structures, and each first power input terminal is electrically connected to at least one pixel column of the plurality of pixel columns through a first fan-out structure. The resistance of the fan-out structure is equal.
  • each of the at least three first fan-out structures includes a first conductive unit, and the first conductive unit is connected to at least one of the plurality of pixel columns.
  • the pixel columns are electrically connected.
  • the first fan-out structure includes a plurality of first conductive units, and each conductive unit of the plurality of first conductive units is electrically connected to at least one of the plurality of pixel columns.
  • each of the first power input terminals is electrically connected to one of the pixel columns.
  • each of the first power input terminals is electrically connected to at least two of the pixel columns.
  • the light-emitting unit includes a first electrode.
  • Each anode wire is electrically connected to the first electrode of the plurality of light-emitting units included in at least one of the plurality of pixel columns.
  • the array substrate further includes pixel circuits distributed in an array, each pixel circuit is configured to provide a driving signal to each light-emitting unit, and the light-emitting unit includes a first electrode.
  • Each pixel circuit is electrically connected to a first electrode, and each first power input terminal provides a first power signal to a pixel circuit in at least one pixel column of the plurality of pixel columns.
  • the array substrate further includes: at least three second power input terminals arranged in the first binding area. Each second power input terminal is connected to at least one pixel column of the plurality of pixel columns to provide a second power signal to the at least one pixel column.
  • different pixel columns connected to the second power input terminals are different.
  • the non-display area further includes a fan-out area.
  • the fan-out area is located between the display area and the first binding area.
  • the fan-out area includes at least three second fan-out structures, and each second power input terminal is electrically connected to at least one of the plurality of pixel columns through a second fan-out structure, and each second The resistance of the fan-out structure is equal.
  • the fan-out area includes at least three first fan-out structures, in the first direction, the first fan-out structures and the second fan-out structures are alternately arranged.
  • each of the at least three second fan-out structures includes a second conductive unit, and the second conductive unit is connected to at least one of the plurality of pixel columns.
  • the pixel columns are electrically connected.
  • the second fan-out structure includes a plurality of second conductive units, and each conductive unit of the plurality of second conductive units is electrically connected to one of the pixel columns.
  • each of the second power input terminals is electrically connected to one of the pixel columns.
  • each of the second power input terminals is electrically connected to at least two of the pixel columns.
  • the array substrate further includes pixel circuits distributed in an array.
  • Each pixel circuit is configured to provide a driving signal to each light-emitting unit, and the light-emitting unit includes a second electrode.
  • Each second power input terminal provides a second power signal to a second electrode of a light-emitting unit included in at least one pixel column of the plurality of pixel columns.
  • the non-display area further includes a second binding area located on a side of the display area away from the first binding area, and the second binding area includes a plurality of light emitting units. Provide the data signal input terminal of the data signal.
  • a display panel in a second aspect, includes any of the array substrates described above.
  • a display device in a third aspect, includes any of the above-mentioned display panels.
  • the display device in the case that the non-display area of the array substrate includes a first binding area and a second binding area, the display device further includes: a first outer portion bound to the first binding area. A circuit, and a second external circuit bound to the second binding area.
  • FIG. 1 is a schematic diagram of a top view structure of an OLED array substrate in the related art
  • Figure 2 is a diagram of the relationship between IR drop and display panel size in related technologies
  • FIG. 3 is a structural diagram of an array substrate provided according to some embodiments of the present disclosure.
  • FIG. 4 is a structural diagram of another array substrate provided according to some embodiments of the present disclosure.
  • FIG. 5 is a schematic diagram of inputting a first power signal and a second power signal of an array substrate according to some embodiments of the present disclosure
  • FIG. 6 is a schematic diagram of inputting a first power signal and a second power signal of another array substrate according to some embodiments of the present disclosure
  • FIG. 7 is a structural diagram of an array substrate using micro light-emitting diodes as light-emitting units according to some embodiments of the present disclosure
  • FIG. 8 is a partial structure diagram of an array substrate using micro light emitting diodes as light emitting units according to some embodiments of the present disclosure
  • FIG. 9 is another partial structure diagram of an array substrate using micro light-emitting diodes as light-emitting units according to some embodiments of the present disclosure.
  • FIG. 10 is another partial structure diagram of an array substrate using micro light-emitting diodes as light-emitting units according to some embodiments of the present disclosure
  • FIG. 11 is still another partial structure diagram of an array substrate using micro light-emitting diodes as light-emitting units according to some embodiments of the present disclosure
  • FIG. 12 is a top structural view of an array substrate using organic light-emitting diodes as light-emitting units according to some embodiments of the present disclosure
  • FIG. 13 is a cross-sectional view of the array substrate shown in FIG. 12 along the line M-M;
  • FIG. 14 is a partial structural diagram of an array substrate using organic light emitting diodes as light emitting units according to some embodiments of the present disclosure
  • 15 is another partial structure diagram of an array substrate using organic light-emitting diodes as light-emitting units according to some embodiments of the present disclosure
  • FIG. 16 is another partial structure diagram of an array substrate using organic light-emitting diodes as light-emitting units according to some embodiments of the present disclosure
  • FIG. 17 is still another partial structure diagram of an array substrate using organic light-emitting diodes as light-emitting units according to some embodiments of the present disclosure.
  • FIG. 18 is a schematic structural diagram of yet another array substrate provided according to some embodiments of the present disclosure.
  • FIG. 19 is a structural diagram of a display panel provided according to some embodiments of the present disclosure.
  • FIG. 20 is a structural diagram of a display device provided according to some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and the combination of A and B.
  • exemplary embodiments are described herein with reference to cross-sectional views and/or plan views as idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Therefore, variations in the shape with respect to the drawings due to, for example, manufacturing technology and/or tolerances are conceivable. Therefore, the exemplary embodiments should not be construed as being limited to the shape of the area shown herein, but include shape deviations due to, for example, manufacturing.
  • an etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the area of the device, and are not intended to limit the scope of the exemplary embodiments.
  • the display device may be a product or a component, and the component may be a display panel, a display substrate, or the like.
  • the display device may be a self-luminous display device, such as an OLED (Organic Light Emitting Diode, organic electroluminescence) display device, a QLED (Quantum Dot Light Emitting Diodes) display device, etc.; in this case, the display device may also include Display panel bonding FPC (Flexible Printed Circuit) and other components.
  • the above-mentioned display device may be a product or component with any display function, such as a display, a TV, a digital camera, a mobile phone, a tablet computer, and so on.
  • an OLED display panel with a common cathode design for the display device is taken as an example.
  • the OLED display panel has a display area (Active Area, AA area), a non-display area BM, and a driver chip IC arranged on the non-display area BM.
  • the anode power line 401' is usually a mesh design, and is electrically connected to the driving chip IC through two anode power signal input terminals 201'.
  • the anode power signal is input to the display area AA by the driver chip IC, where the voltage drop from the near IC end to the far IC end is the vertical IR drop, that is, the voltage drop in the pixel column direction is the vertical IR drop; and the voltage drop in the pixel row direction It is a horizontal IR drop.
  • the voltage at the anode signal collection point B is the highest, and the remaining positions are affected by the horizontal IR drop (voltage drop) and/or the vertical IR drop, and the voltage value of the anode power signal is lower than the anode signal collection Point B. Since the current of the horizontal IR drop is collected to the anode signal collection point B, the horizontal IR drop of the anode power signal is much larger than the longitudinal IR drop of the anode power signal.
  • the horizontal IR drop is higher than the vertical IR drop, and as the size of the display panel increases, both the horizontal IR drop and the vertical IR drop have increased.
  • the pixel current is uA, which is about 1000 times that of OLED. Therefore, compared with OLED display panels, Micro-LED display panels and Mini-LED display panels have a more serious horizontal IR drop.
  • the voltage Vds between the source and drain electrodes of the driving thin film transistors at different positions in the display area AA of the array substrate is different.
  • array substrates such as LTPS (Low Temperature Poly-Silicon)
  • the characteristics of thin film transistors are different under different Vds, which will further cause the difference in the driving current of the light-emitting unit, and exacerbate the problem of uneven display brightness.
  • the array substrate includes a display area AA and a non-display area BM, wherein the non-display area BM includes a first bonding area BM1.
  • the array substrate includes a plurality of pixel columns 10 arranged in the display area AA, and at least three first power input terminals 201 arranged in the first bonding area BM1, each of the first power input terminals 201 and the plurality of pixel columns At least one pixel column of is connected to provide a first power signal to at least one pixel column 10.
  • each of the plurality of pixel columns 10 includes a plurality of light-emitting units, and different first power input terminals 201 are connected to different pixel columns.
  • the first power signal refers to the anode power signal VDD.
  • the first power input terminal may also be referred to as a first power input pad (Pad) or a first power input pattern.
  • each first power input terminal 201 is electrically connected to a pixel column 10 to provide the first power signal VDD. That is, the first power input terminal 201 corresponds to the pixel column 10 in a one-to-one manner. Therefore, the horizontal IR drop can be completely avoided, and the uniformity of the display brightness is significantly improved.
  • the first power input terminal 201 is electrically connected to at least two (two or more) pixel columns 10 to provide the first power signal VDD. That is, the first power input terminal 201 corresponds to a plurality of pixel columns 10, therefore, it can effectively reduce the lateral IR drop, improve the uniformity of the display brightness, and can prevent the driver chip from being overloaded.
  • the non-display area BM further includes a fan-out area BM2, the fan-out area BM2 is located between the display area AA and the first binding area BM1; the fan-out area BM2 includes at least three third A fan-out structure 301.
  • Each first power input terminal 201 is electrically connected to at least one pixel column of a plurality of pixel columns through a first fan-out structure 301, and the resistance of each first fan-out structure 301 is equal.
  • each first power input terminal 201 is electrically connected to a pixel column through a first fan-out structure 301 to provide the first power signal VDD.
  • each first fan-out structure 301 in the fan-out area BM2 is larger. Therefore, each first fan-out structure The width of 301 in the first direction X is small, and the first fan-out structure 301 can be regarded as a conductive line, which transmits the first power signal or the second power signal input from the power input terminal to the corresponding pixel column.
  • each first power input terminal 201 is electrically connected to at least two (two or more) pixel columns through a first fan-out structure 301 to provide a first power signal VDD. .
  • the first fan-out structure 201 is in the first direction X
  • the width of can be designed according to the width of the fan-out area BM in the first direction X and the number of the first fan-out structures 301.
  • the shape of the first fan-out structure 301 can be trapezoidal, triangular, rectangular, etc., as long as the resistance of each first fan-out structure 301 is equal.
  • the first fan-out structure 301 of the fan-out area BM2 is designed with equal resistance, so that the anode power signal VDD (that is, the first power signal VDD) is uniformly affected by the IR drop of the fan-out area BM2. Further reduce the impact of IR drop on the brightness of the display, thereby further improving the uniformity of the display brightness.
  • VDD anode power signal
  • each of the at least three first fan-out structures 301 includes a first conductive unit 3011, and each first conductive unit 3011 is connected to At least one pixel column among the plurality of pixel columns is electrically connected.
  • a first fan-out structure 301 includes one first conductive unit 3011, and each first conductive unit 3011 is electrically connected to a pixel column.
  • a one-to-one correspondence between the first power input terminal 201 and the second power input terminal 201 and the pixel column can be achieved, and the horizontal IR drop can be completely avoided, and the uniformity of the display brightness can be significantly improved.
  • the first fan-out structure 301 includes one first conductive unit 3011, and each first conductive unit 3011 is electrically connected to at least two pixel columns.
  • one first power input terminal 201 corresponds to a plurality of pixel columns, which can effectively reduce the lateral IR drop, improve the uniformity of display brightness, and can prevent the driving chip from being overloaded.
  • the first fan-out structure 301 includes a plurality of first conductive units 3011, and each first conductive unit 3011 of the plurality of first conductive units 3011 is connected to at least One pixel column is electrically connected.
  • each first power input terminal 201 corresponds to multiple pixel columns, the lateral IR drop can be effectively reduced, the uniformity of display brightness can be improved, and the driving chip can be prevented from being overloaded; and each fan-out structure Designing multiple conductive units can avoid the problem of separation between the fan-out structure and the substrate caused by the excessively large area of the fan-out structure.
  • each first fan-out structure 301 includes a plurality of first conductive units 3011, wherein each first conductive unit 3011 of the plurality of first conductive units 3011 is electrically connected to one pixel column. connect.
  • the first fan-out structure 301 includes a plurality of first conductive units 3011, wherein each first conductive unit 3011 of the plurality of first conductive units 3011 and at least two pixel columns Electric connection.
  • one first power input terminal 201 can be realized to correspond to multiple pixel columns, which can effectively reduce the horizontal IR drop, improve the uniformity of display brightness, and prevent the driver chip from being overloaded; and each fan-out structure is designed
  • the plurality of conductive units can avoid the problem of separation of the fan-out structure from the substrate caused by the excessively large area of the fan-out structure.
  • the array substrate further includes at least three second power input terminals 202 arranged in the first bonding area BM1, and each second power input terminal is connected to a plurality of pixel columns. At least one pixel column in is connected to provide a second power signal to at least one pixel column. Wherein, the pixel columns connected to different second power input terminals are different.
  • the second power signal refers to the cathode power signal VSS.
  • the second power input terminal may also be referred to as a second power input pad (Pad) or a second power input pattern.
  • each second power input terminal 202 is electrically connected to a pixel column to provide the second power signal VSS. That is, the second power input terminal 202 corresponds to the pixel column one-to-one, and therefore, the horizontal IR drop can be completely avoided, and the uniformity of the display brightness is significantly improved.
  • each second power input terminal 202 is electrically connected to at least two (two or more) pixel columns 10 to provide a second power signal VSS. In this way, It can effectively improve the problem of poor display brightness uniformity caused by large horizontal IR drop caused by current collection, and can prevent the driver chip from being overloaded, thereby improving the display quality.
  • the non-display area BM further includes a fan-out area BM2, the fan-out area BM2 is located between the display area AA and the first binding area BM1; the fan-out area BM2 includes at least three third Two fan-out structures 302, each second power input terminal 202 is electrically connected to at least one pixel column of the plurality of pixel columns through a second fan-out structure 302, and the resistance of each second fan-out structure 302 is equal.
  • the second fan-out structure 302 of the fan-out area BM2 is designed with equal resistance, so that each cathode power signal VSS is affected by the IR drop of the fan-out area BM2 uniformly, which further reduces the IR drop effect on the display screen. The influence of brightness, thereby further improving the uniformity of display brightness.
  • each second power input terminal 202 is electrically connected to a pixel column through a second fan-out structure 302 to provide the second power signal VSS.
  • each second fan-out structure 302 has a small width in the second direction X, and each second fan-out structure 302 can be regarded as a conductive line, which transmits the first power signal or the second power signal input from the power input terminal to the corresponding pixel row .
  • each second power input terminal 202 is electrically connected to at least two (two or more) pixel columns through a second fan-out structure 302 to provide a second power signal VSS. .
  • the width of the second fan-out structure 202 in the first direction X can be determined according to the fan-out area BM
  • the width in the first direction X and the number of second fan-out structures 302 are designed.
  • the shape of the second fan-out structure 302 can be trapezoidal, triangular, rectangular, etc., as long as the resistance of each second fan-out structure 302 is equal.
  • the first fan-out structure 301 and the second fan-out structure 302 are alternately arranged, and the first fan-out structure 301 is a regular trapezoid.
  • the second fan-out structure 302 has an inverted trapezoid shape.
  • the first fan-out structure 301 and the second fan-out structure 302 are alternately arranged.
  • the first fan-out structure 301 that provides the first power signal VDD for the same pixel column and the second fan-out structure 302 that increases the second power signal VSS can be adjacent to each other, thereby facilitating the fan-out area BM2 to the display area AA.
  • the wiring can make the horizontal IR drop of the first fan-out structure 301 and the second fan-out structure 302 more balanced, further reduce the influence of the horizontal IR drop on the uniformity of display brightness, and improve the uniformity of display brightness.
  • the fan-out structure can be designed as a plurality of conductive units, and each conductive unit in the same fan-out structure is the same
  • the second power input terminal 202 is electrically connected, and each conductive unit provides the first power signal VDD or the second power signal VSS for one or more pixel columns.
  • the fan-out structure can also be partially hollowed out, for example, the fan-out structure is designed as a mesh structure to prevent separation between the fan-out structure and the substrate.
  • the substrate refers to a film layer located under and in contact with the fan-out structure, and is usually an insulating layer material.
  • each of the at least three second fan-out structures 302 includes one second conductive unit 3021, and each second conductive unit 3021 is connected to At least one pixel column among the plurality of pixel columns is electrically connected.
  • a second fan-out structure 302 includes one second conductive unit 3021, and each second conductive unit 3021 is electrically connected to a pixel column.
  • a one-to-one correspondence between the second power input terminal 201 and the pixel column can be realized, and the horizontal IR drop can be completely avoided, and the uniformity of the display brightness can be significantly improved.
  • each second fan-out structure 302 includes one second conductive unit 3021, and each second conductive unit 3021 is electrically connected to at least two (two or more) pixel columns.
  • one second power input terminal 201 corresponds to a plurality of pixel columns, which can effectively reduce the lateral IR drop, improve the uniformity of display brightness, and can prevent the driving chip from being overloaded.
  • each of the at least three second fan-out structures 302 includes a plurality of second conductive units 3021, and each second conductive unit 3021 It is electrically connected to at least one pixel column.
  • each second power input terminal 201 corresponds to multiple pixel columns, it can effectively reduce the lateral IR drop, improve the uniformity of display brightness, and prevent the driver chip from being overloaded; and each fan-out structure Designing multiple conductive units can avoid the problem of separation between the fan-out structure and the substrate caused by the excessively large area of the fan-out structure.
  • each second fan-out structure 302 includes a plurality of second conductive units 3021, wherein each second conductive unit of the plurality of second conductive units 3021 is electrically connected to a pixel column .
  • the second fan-out structure 302 includes a plurality of second conductive units 3021, wherein each second conductive unit 3021 of the plurality of second conductive units 3021 is electrically connected to at least two pixel columns. connect.
  • each second power input terminal 201 can be realized to correspond to multiple pixel columns, which can effectively reduce the horizontal IR drop, improve the uniformity of display brightness, and prevent the driver chip from being overloaded; and each fan-out structure is designed
  • the plurality of conductive units can avoid the problem of separation of the fan-out structure from the substrate caused by the excessively large area of the fan-out structure.
  • the light emitting unit may be a micro light emitting diode, that is, the array substrate is a micro LED array substrate or a mini LED array substrate; the light emitting unit may also be an organic light emitting diode, that is, the array substrate is an OLED array substrate.
  • the array substrates of these two light-emitting units will be described in detail.
  • the light-emitting unit includes a first electrode and a second electrode, and each anode wire is electrically connected to a first electrode of a plurality of light-emitting units included in at least one of the plurality of pixel columns.
  • the light emitting unit 101 is a micro light emitting diode 101a, which includes a first electrode and a second electrode;
  • the display area of the array substrate includes a plurality of anode wirings 401 and a plurality of cathode wirings 402
  • Each anode wire 401 is electrically connected to the first electrode of the plurality of micro light emitting diodes 101a included in each pixel column, and each cathode wire 402 is connected to the first electrode of the plurality of micro light emitting diodes 101a included in each pixel column.
  • the second electrode is electrically connected.
  • the light-emitting unit 101 is a miniature light-emitting diode 101a, and each anode wiring 301 is connected to at least two (two or more) pixel columns among the multiple pixel columns.
  • the first electrode of each of the micro light emitting diodes 101a is electrically connected, and each cathode wiring 402 is connected to the first electrode of the plurality of micro light emitting diodes 101a included in at least two (two or more) pixel columns in the plurality of pixel columns.
  • the two electrodes are electrically connected.
  • the first fan-out structure 301 is electrically connected to at least one anode wire 401
  • the second fan-out structure 302 is electrically connected to at least one cathode wire 402.
  • the first fan-out structure 301 is electrically connected to one anode wire 401
  • the second fan-out structure 302 is electrically connected to at least one cathode wire 402.
  • the first fan-out structure 301 is electrically connected to a plurality of (at least two) anode wires 401
  • the second fan-out structure 302 is electrically connected to a plurality of (at least two) cathode wires 402. connect.
  • micro LED array substrate or mini LED array substrate does not include the micro light emitting diode 101a.
  • the micro light emitting diode 101a is transferred to the array substrate after the circuit of the array substrate is completed, and is electrically connected to the circuit on the array substrate. Connect, and then perform subsequent binding and packaging to obtain a micro LED display or mini LED display.
  • the corresponding relationship between the power input terminal and the pixel column can be designed according to specific conditions, thereby reducing the lateral IR drop. Because the driving current of the micro LED or mini LED is relatively large, therefore, The effect of reducing the horizontal IR drop is obvious, and it has a significant improvement effect on improving the uniformity of display brightness.
  • the light-emitting unit 101 is an organic light-emitting diode 101b
  • the first electrode is an anode unit 1013b
  • the second electrode is a cathode layer 1012b
  • the display area AA of the array substrate includes a cathode layer 1012b and an organic light emitting diode.
  • Layer 1012b multiple columns of anode units 1013b, and anode wiring 401.
  • the organic light-emitting layer 1012b is located between the cathode layer 1011b and the corresponding anode unit 1013b; the anode wiring 401 is connected to the multiple columns included in at least one of the multiple pixel columns.
  • the anode unit 1013b of each organic light emitting diode 101b is electrically connected to the second fan-out structure 302 and the cathode layer 1012b.
  • anode wire 401 and the anode unit 1013b in FIG. 12 is only an exemplary illustration. In practical applications, the anode wire 401 and the anode unit 1013b can be arranged in the same layer; the anode wire 401 and the anode unit 1013b can also be located on a different film layer, which facilitates the via hole connection.
  • the first fan-out structure 301 includes one first conductive unit 3011, and each first conductive unit 3011 is electrically connected to an anode trace 401; the second fan-out structure 302 includes one The second conductive unit 3021, each second conductive unit 3021 is electrically connected to the cathode layer 1011b.
  • the first fan-out structure 301 includes a plurality of first conductive units 3011, and each first conductive unit 3011 of the plurality of first conductive voltages 3011 is connected to an anode wiring 401 Electrically connected;
  • the second fan-out structure 302 includes a plurality of second conductive units 3021, each of the plurality of second conductive units 3021 is electrically connected to the cathode layer 1011b.
  • one first power input terminal 201 can be realized to correspond to multiple pixel columns, which can effectively reduce the horizontal IR drop, improve the uniformity of display brightness, and prevent the driver chip from being overloaded; and each fan-out structure is designed
  • the plurality of conductive units can avoid the problem of separation of the fan-out structure from the substrate caused by the excessively large area of the fan-out structure.
  • the first fan-out structure 301 includes one first conductive unit 3011, and each first conductive unit 3011 is electrically connected to a plurality of anode wires 401; the second fan-out structure 302 It includes one second conductive unit 3021, and each second conductive unit 3021 is electrically connected to the cathode layer 1011b. In this way, it is possible to realize that one first power input terminal 201 corresponds to a plurality of pixel columns.
  • the first fan-out structure 301 includes a plurality of first conductive units 3011, and each first conductive unit 3011 is electrically connected to a plurality of anode wires 401;
  • the second fan-out structure 302 includes one or more second conductive units 3021, and each second conductive unit 3021 is electrically connected to the cathode layer 1011b.
  • one first power input terminal 201 can be realized to correspond to multiple pixel columns, which can effectively reduce the horizontal IR drop, improve the uniformity of display brightness, and prevent the driver chip from being overloaded; and each fan-out structure is designed
  • the plurality of conductive units can avoid the problem of separation of the fan-out structure from the substrate caused by the excessively large area of the fan-out structure.
  • the array substrate further includes pixel circuits distributed in an array, each pixel circuit is configured to provide a driving signal to each light-emitting unit, the light-emitting unit includes a first electrode and a second electrode; each pixel circuit is associated with a first electrode.
  • An electrode is electrically connected, each first power input terminal provides a first power signal to the pixel circuit in at least one of the plurality of pixel columns, and each second power input terminal provides at least one pixel of the plurality of pixel columns The second electrode of the light emitting unit included in the column provides a second power signal.
  • the micro light emitting diode 101a when the light emitting unit 101 is a micro light emitting diode 101a, the micro light emitting diode 101a includes a first electrode and a second electrode, wherein the pixel circuit is electrically connected to the first electrode of each micro light emitting diode 101a, and each The first power input terminal 201 provides a first power signal VDD to one of a plurality of pixel columns or a plurality of pixel circuits, and each second power input terminal 202 provides a first power signal VDD to one of a plurality of pixel columns or a plurality of pixel columns.
  • the second electrode of the included micro light emitting diode provides a second power signal VSS.
  • the organic light-emitting diode 101b when the light-emitting unit 101 is an organic light-emitting diode 101b, the organic light-emitting diode 101b includes a first electrode (that is, an anode) and a second electrode (that is, a cathode). The anode of the diode 101b is electrically connected.
  • Each first power input terminal 201 provides a first power signal VDD to one of a plurality of pixel columns or a plurality of pixel circuits
  • each second power input terminal 202 provides a first power signal VDD to a plurality of pixel columns.
  • the cathode of the organic light emitting diode included in one or more pixel columns provides the second power signal VSS.
  • the non-display area BM further includes a second binding area BM3 located on the side of the display area AA away from the first binding area BM1, the second binding area BM3, and the second binding area BM3.
  • the area BM3 includes a plurality of data signal input terminals 501 for providing data signals for the light-emitting unit.
  • the data signal input terminal 501 and the power signal input terminal on opposite sides of the array substrate, the interference between the data signal and the power signal can be prevented, and the wiring difficulty can be reduced.
  • this embodiment provides a display panel.
  • the display panel provided in this embodiment includes the array substrate 1 in the above embodiment, and has the beneficial effects of the array substrate in the above embodiment. I won't repeat them here.
  • the display panel in this embodiment further includes a cover plate 2.
  • the micro-light-emitting diode is not a part of the array substrate, but is transferred to the array substrate after the array substrate is manufactured; and when the light-emitting unit is an organic light-emitting diode, the array The substrate includes organic light emitting diodes.
  • the display device provided by this embodiment includes the display panel 1 in the above-mentioned embodiment, and has the beneficial effects of the display panel in the above-mentioned embodiment. No longer.
  • the display device provided in this embodiment further includes a driving chip II and a power supply III.
  • the driver chip II should include a first driver chip and a second driver chip.
  • the first driving chip is bound in the first binding area and is electrically connected to the power supply III.
  • the power supply III is driven by the first driving chip to provide the first power input terminal and the second power input terminal respectively.
  • Signal and a second power signal; the second driving chip is bound in the second binding area to provide a data signal for the array substrate.
  • the display device when the non-display area of the array substrate includes the first binding area and the second binding area, the display device further includes a first external driving circuit that is bound to the first binding area BM1, And a second external circuit bound to the second binding area BM3.
  • the first external drive circuit and the second external drive circuit may be drive chips, that is, the two drive chips are directly bound to the first bonding area and the second bonding area, respectively; the first external drive circuit and the second external drive circuit
  • the driving circuit may also include a flexible circuit board and a driving chip, that is, the driving chip is bound on the flexible circuit board, and the flexible circuit board is bound in the first binding area or the second binding area.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板、显示面板及显示装置。该阵列基板具有显示区和非显示区，所述阵列基板的显示区承载有多至少一个像素列，所述非显示区包括第一绑定区，每个所述像素列包括多个沿第一方向排布的发光单元，其特征在于，所述阵列基板包括：设置在所述显示区的多个像素列，所述多个像素列中的每个像素列包括多个发光单元；非显示区，包括第一绑定区，设置在所述第一绑定区包括中的至少三个第一电源输入端和第二电源输入端，所述每个第一电源输入端与所述多个像素列中的至少一个像素列连接，以向所述至少一个列所述像素列提供第一电源信号。

Description

阵列基板、显示面板及显示装置
本申请要求于2020年1月16日提交的、申请号为202010049497.1的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板、显示面板及显示装置。
背景技术
对于显示面板来说，阳极走线或阴极走线上的IR drop(电压降)会引发亮度不均的问题，通常情况下，横向IR drop远大纵向IR drop，因此，如何解决显示面板的横向IR drop对提升显示面板亮度的均一性至关重要。
发明内容
第一方面，提供一种阵列基板。该阵列基板具有显示区和非显示区。所述非显示区包括第一绑定区。所述阵列基板包括：设置在所述显示区的多个像素列以及设置在所述第一绑定区的至少三个第一电源输入端。所述多个像素列中的每个像素列包括多个发光单元。每个第一电源输入端与所述多个像素列中的至少一个像素列连接，以向所述至少一个像素列提供第一电源信号。
在一些实施例中，不同的所述第一电源输入端连接的像素列不同。
在一些实施例中，所述非显示区还包括扇出区，所述扇出区位于所述显示区与所述第一绑定区之间。所述扇出区包括至少三个第一扇出结构，每个第一电源输入端通过一个第一扇出结构与所述多个像素列中的至少一个像素列电连接，各所述第一扇出结构的电阻相等。
在一些实施例中，所述至少三个第一扇出结构中的每个第一扇出结构包括一个第一导电单元，所述第一导电单元与所述多个像素列中的至少一个所述像素列电连接。或者，所述第一扇出结构包括多个第一导电单元，所述多个第一导电单元中的每个导电单元与所述多个像素列中的至少一个所述像素列电连接。
在一些实施例中，每个所述第一电源输入端与一个所述像素列电连接。或者，每个所述第一电源输入端与至少两个所述像素列电连接。
在一些实施例中，所述发光单元包括第一电极。每条阳极走线与所述多个像素列中的至少一个像素列中包括的所述多个发光单元的第一电极电连接。
在一些实施例中，所述阵列基板还包括阵列分布的像素电路，每个像素 电路被配置为向每个发光单元提供驱动信号，所述发光单元包括第一电极。每个像素电路与一个第一电极电连接，每个第一电源输入端向所述多个像素列中的至少一个像素列中的像素电路提供第一电源信号。
在一些实施例中，所述阵列基板还包括：设置在所述第一绑定区的至少三个第二电源输入端。每个第二电源输入端与所述多个像素列中的至少一个像素列连接，以向所述至少一个像素列提供第二电源信号。
在一些实施例中，不同的所述第二电源输入端连接的像素列不同。
在一些实施例中，所述非显示区还包括扇出区。所述扇出区位于所述显示区与所述第一绑定区之间。所述扇出区包括至少三个第二扇出结构，每个第二电源输入端通过一个第二扇出结构与所述多个像素列中的至少一个像素列电连接，各所述第二扇出结构的电阻相等。
在一些实施例中，在扇出区包括至少三个第一扇出结构的情况下，在第一方向上，所述第一扇出结构和所述第二扇出结构交替排布。
在一些实施例中，所述至少三个第二扇出结构中的每个第二扇出结构包括一个第二导电单元，所述第二导电单元与所述多个像素列中的至少一个所述像素列电连接。或者，所述第二扇出结构包括多个第二导电单元，所述多个第二导电单元中的每个导电单元与一个所述像素列电连接。
在一些实施例中，每个所述第二电源输入端与一个所述像素列电连接。或者，每个所述第二电源输入端与至少两个所述像素列电连接。
在一些实施例中，所述阵列基板还包括阵列分布的像素电路。每个像素电路被配置为向每个发光单元提供驱动信号，所述发光单元包括第二电极。每个第二电源输入端向所述多个像素列中的至少一个像素列中包括的发光单元的第二电极提供第二电源信号。
在一些实施例中，所述非显示区还包括位于所述显示区远离所述第一绑定区一侧的第二绑定区，所述第二绑定区包括多个为所述发光单元提供数据信号的数据信号输入端。
第二方面，提供了一种显示面板，该显示面板包括如上所述的任一种阵列基板。
第三方面，提供了一种显示装置，该显示装置包括如上所述的任一种显示面板。
在一些实施例中，在阵列基板的非显示区包括第一绑定区和第二绑定区的情况下，所述显示装置还包括：与所述第一绑定区绑定的第一外部电路，以及与所述第二绑定区绑定的第二外部电路。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为相关技术中的一种OLED阵列基板的俯视结构示意图；
图2为相关技术中IR drop与显示面板尺寸的关系图；
图3为根据本公开一些实施例提供的一种阵列基板的结构图；
图4为根据本公开一些实施例提供的另一种阵列基板的结构图；
图5为根据本公开一些实施例提供的一种阵列基板的第一电源信号和第二电源信号的输入示意图；
图6为根据本公开一些实施例提供的另一种阵列基板的第一电源信号和第二电源信号的输入示意图；
图7为根据本公开一些实施例提供的一种以微型发光二极管作为发光单元的阵列基板的结构图；
图8为根据本公开一些实施例提供的以微型发光二极管作为发光单元的阵列基板的一种局部结构图；
图9为根据本公开一些实施例提供的以微型发光二极管作为发光单元的阵列基板的另一种局部结构图；
图10为根据本公开一些实施例提供的以微型发光二极管作为发光单元的阵列基板的又一种局部结构图；
图11为根据本公开一些实施例提供的以微型发光二极管作为发光单元的阵列基板的再一种局部结构图；
图12为根据本公开一些实施例提供的一种以有机发光二极管作为发光单元的阵列基板的俯视结构图；
图13为图12中所示的阵列基板沿M-M线的截面图；
图14为根据本公开一些实施例提供的以有机发光二极管作为发光单元的阵列基板的一种局部结构图；
图15为根据本公开一些实施例提供的以有机发光二极管作为发光单元的阵列基板的另一种局部结构图；
图16为根据本公开一些实施例提供的以有机发光二极管作为发光单元的 阵列基板的又一种局部结构图；
图17为根据本公开一些实施例提供的以有机发光二极管作为发光单元的阵列基板的再一种局部结构图；
图18为根据本公开一些实施例提供的又一种阵列基板的结构示意图；
图19为根据本公开一些实施例提供的一种显示面板的结构图；
图20为根据本公开一些实施例提供的一种显示装置的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
本技术领域技术人员可以理解，除非特意声明，这里使用的单数形式“一”、“一个”、“所述”和“该”也可包括复数形式。应该进一步理解的是，本申请的说明书中使用的措辞“包括”是指存在所述特征、整数、步骤、操作、元件和/或组件，但是并不排除存在或添加一个或多个其他特征、整数、步骤、操作、元件、组件和/或它们的组。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术 语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
本技术领域技术人员可以理解，除非另外定义，这里使用的所有术语(包括技术术语和科学术语)，具有与本申请所属领域中的普通技术人员的一般理解相同的意义。还应该理解的是，诸如通用字典中定义的那些术语，应该被理解为具有与现有技术的上下文中的意义一致的意义，并且除非像这里一样被特定定义，否则不会用理想化或过于正式的含义来解释。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
下面详细描述本申请，本申请的实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的部件或具有相同或类似功能的部件。此外，如果已知技术的详细描述对于示出的本申请的特征是不必要的，则将其省略。下面通过参考附图描述的实施例是示例性的，仅用于解释本申请，而不能解释为对本申请的限制。
本公开的一些实施例提供了一种显示装置，该显示装置可以是产品或部件，部件可以是显示面板，显示基板等。示例的，显示装置可以是自发光的显示装置，例如OLED(Organic Light Emitting Diode，有机电致发光)显示装置、QLED(Quantum Dot Light Emitting Diodes)显示装置等；此时，显示装置还可以包含与显示面板邦定的FPC(Flexible Printed Circuit)等部件。上述显示装置可以是显示器、电视、数码相机、手机、平板电 脑等具有任何显示功能的产品或者部件。
如图1所示，以显示装置为共阴极设计的OLED显示面板为例，OLED显示面板具有显示区(Active Area，AA区)，非显示区BM以及设置在非显示区BM上的驱动芯片IC。其中，阳极电源线401′通常为网状设计，并通过两个阳极电源信号输入端201′与驱动芯片IC电连接。阳极电源信号由驱动芯片IC输入到显示区AA，其中，由近IC端到远IC端的电压降为纵向IR drop，即像素列方向上的电压降为纵向IR drop；而像素行方向上的电压降为横向IR drop。
对于阳极电源线401′来说，阳极信号汇集点B处的电压最高，其余位置受横向IR drop(电压降)和/或纵向IR drop的影响，阳极电源信号的电压值都低于阳极信号汇集点B。由于横向IR drop的电流都汇集到了阳极信号汇集点B，因此，阳极电源信号的横向IR drop要远大于阳极电源信号的纵向IR drop。
如图2所示，在不同尺寸的显示面板中，横向IR drop都高于纵向IR drop，且随着显示面板的尺寸的增加，无论是横向IR drop还是纵向IR drop都有所上升。
对于Micro-LED(Micro Light-Emitting Diode，微发光二极管)或Mini-LED(Mini Light-Emitting Diode，迷你发光二极管)显示面板来说，像素电流为uA级，是OLED像素电流的1000倍左右，因此Micro-LED显示面板和Mini-LED显示面板与OLED显示面板相比，横向IR drop更为严重。
并且，由于IR drop的影响，使得阵列基板的显示区域AA不同位置的驱动薄膜晶体管的源漏电极之间的电压Vds不同，对于LTPS(Low Temperature Poly-Silicon，低温多晶硅)等类型的阵列基板来说，薄膜晶体管的特性在不同的Vds下具有差异，这将进一步导致发光单元的驱动电流的差异，加剧显示亮度不均的问题。
下面以具体地实施例对本公开的技术方案以及本公开的技术方案如何解决上述技术问题进行详细说明。
本公开一些实施例提供了一种阵列基板，如图3或图4所示，该阵列基板包括显示区AA和非显示区BM，其中，非显示区BM包括第一绑定区BM1。
该阵列基板包括设置在显示区AA的多个像素列10，以及设置在第一绑定区BM1的至少三个第一电源输入端201，每个第一电源输入端201与多个像素列中的至少一个像素列连接，以向至少一个像素列10提供第一电源信号。其中，多个像素列10中的每个像素列包括多个发光单元，不同的第一电源输 入端201连接的像素列不同。
需要说明的是，第一电源信号是指阳极电源信号VDD。第一电源输入端还可以称为第一电源输入衬垫(Pad)或者第一电源输入图案。
在一些实施例中，如图5所示，每个第一电源输入端201与一个像素列10电连接，以提供第一电源信号VDD。即第一电源输入端201与像素列10一一对应，因此，能够完全避免横向IR drop，显著提升显示亮度的均一性。
在另一些实施例中，如图6所示，第一电源输入端201与至少两个(两个或两个以上)的列像素列10电连接，以提供第一电源信号VDD。即第一电源输入端201与多个像素列10对应，因此，既能够有效降低横向IR drop，提升显示亮度的均一性，又能够防止驱动芯片负载过重。
在一些实施例中，如图5所示，非显示区BM还包括扇出区BM2，扇出区BM2位于显示区AA与第一绑定区BM1之间；扇出区BM2包括至少三个第一扇出结构301，每个第一电源输入端201通过一个第一扇出结构301与多个像素列中的至少一个像素列电连接，各第一扇出结构301的电阻相等。
示例的，如图5所示，每个第一电源输入端201通过一个第一扇出结构301与一个像素列电连接，以提供第一电源信号VDD。
进一步地，如图5所示，当第一电源输入端201与像素列10一一对应时，扇出区BM2的第一扇出结构301个数较多，因此，每个第一扇出结构301在第一方向X上的宽度都较小，可将第一扇出结构301看作是导电线，将电源输入端输入的第一电源信号或第二电源信号传递至相应的像素列。
再示例的，如图6所示，每个第一电源输入端201通过一个第一扇出结构301与至少两个(两个或两个以上)像素列电连接，以提供第一电源信号VDD。
进一步地，如图6所示，在每个第一电源输入端201与至少两个(两个或两个以上)像素列10对应的情况下，第一扇出结构201在第一方向X上的宽度可根据扇出区BM在第一方向X上的宽度，以及第一扇出结构301的个数来进行设计。第一扇出结构301的形状可为梯形、三角形、矩形等形状，只要保证各第一扇出结构301的电阻相等即可。
在本实施例中，通过将扇出区BM2的第一扇出结构301进行等电阻设计，使得各阳极电源信号VDD(即第一电源信号VDD)受扇出区BM2的IR drop的影响一致，进一步降低IR drop对显示屏亮度的影响，从而进一步提升显示屏亮度的均一性。
在一些实施例中，如图8和图10所示，至少三个第一扇出结构301中的 每个第一扇出结构301包括一个第一导电单元3011，每个第一导电单元3011与多个像素列中的至少一个像素列电连接。
示例的，如图8所示，一个第一扇出结构301包括一个第一导电单元3011，每个第一导电单元3011与一个像素列电连接。如此，可实现第一电源输入端201和第二电源输入端201与像素列一一对应，能够完全避免横向IR drop，显著提升显示亮度的均一性。
再示例的，如图10所示，第一扇出结构301包括一个第一导电单元3011，每个第一导电单元3011与至少两个像素列电连接。如此，可实现一个第一电源输入端201与多个像素列对应，既能够有效降低横向IR drop，提升显示亮度的均一性，又能够防止驱动芯片负载过重。
在另一些实施例中，如图9和图11所示，第一扇出结构301包括多个第一导电单元3011，该多个第一导电单元3011中的每个第一导电单元3011与至少一个像素列电连接。如此，在一个第一电源输入端201与多个像素列对应的情况下，既能够有效降低横向IR drop，提升显示亮度的均一性，又能够防止驱动芯片负载过重；并且每个扇出结构中设计多个导电单元能够避免扇出结构的面积过大而引起的扇出结构与基材分离的问题。
示例的，如图9所示，每个第一扇出结构301包括多个第一导电单元3011，其中，该多个第一导电单元3011中的每个第一导电单元3011与一个像素列电连接。
再示例的，如图11所示，第一扇出结构301包括多个第一导电单元3011，其中，该多个第一导电单元3011中的每个第一导电单元3011与至少两个像素列电连接。如此，可实现一个第一电源输入端201与多个像素列对应，既能够有效降低横向IR drop，提升显示亮度的均一性，又能够防止驱动芯片负载过重；并且每个扇出结构中设计多个导电单元能够避免扇出结构的面积过大而引起的扇出结构与基材分离的问题。
在一些实施例中，如图3和图4所示，阵列基板还包括设置在第一绑定区BM1的至少三个第二电源输入端202，每个第二电源输入端与多个像素列中的至少一个像素列连接，以向至少一个像素列提供第二电源信号。其中，不同的第二电源输入端连接的像素列不同。
需要说明的是，第二电源信号是指阴极电源信号VSS。第二电源输入端还可以称为第二电源输入衬垫(Pad)或者第二电源输入图案。
在一些实施例中，如图5所示，每个第二电源输入端202与一个像素列电连接，以提供第二电源信号VSS。即第二电源输入端202与像素列一一对 应，因此，能够完全避免横向IR drop，显著提升显示亮度的均一性。
在另一些实施例中，如图6所示，每个第二电源输入端202与至少两个(两个或两个以上)像素列10电连接，以提供第二电源信号VSS，这样，能够有效改善电流汇集导致的横向IR drop大而引起的显示亮度均一性差的问题，又能够防止驱动芯片负载过重，从而提升显示质量。
在一些实施例中，如图5所示，非显示区BM还包括扇出区BM2，扇出区BM2位于显示区AA与第一绑定区BM1之间；扇出区BM2包括至少三个第二扇出结构302，每个第二电源输入端202通过一个第二扇出结构302与多个像素列中的至少一个像素列电连接，各第二扇出结构302的电阻相等。
在本实施例中，通过将扇出区BM2的第二扇出结构302进行等电阻设计，使得各各阴极电源信号VSS受扇出区BM2的IR drop的影响一致，进一步降低IR drop对显示屏亮度的影响，从而进一步提升显示屏亮度的均一性。
示例的，如图5所示，每个第二电源输入端202通过一个第二扇出结构302与一个像素列电连接，以提供第二电源信号VSS。
进一步地，如图5所示，当第二电源输入端202与像素行10一一对应时，扇出区BM2的第二扇出结构302个数较多，因此，每个第二扇出结构302在第二方向X上的宽度都较小，可将每个第二扇出结构302看作是导电线，将电源输入端输入的第一电源信号或第二电源信号传递至相应的像素行。
再示例的，如图6所示，每个第二电源输入端202通过一个第二扇出结构302与至少两个(两个或两个以上)像素列电连接，以提供第二电源信号VSS。
进一步地，如图6所示，当每个第二电源输入端202与至少两个像素列10对应，此时，第二扇出结构202在第一方向X上的宽度可根据扇出区BM在第一方向X上的宽度，以及第二扇出结构302的个数来进行设计。第二扇出结构302的形状可为梯形、三角形、矩形等形状，只要保证各第二扇出结构302的电阻相等即可。如图6所示，本实施例提供的阵列基板中，在第一方向X上，第一扇出结构301和第二扇出结构302交替排布，且第一扇出结构301为正梯形，第二扇出结构302为倒梯形。
进一步地，如图5或图6所示，本实施例提供的阵列基板中，在第一方向X上，第一扇出结构301和第二扇出结构302交替排布。这样，能够使为同一像素列提供第一电源信号VDD的第一扇出结构301和提高第二电源信号VSS的第二扇出结构302是相邻的，从而便于扇出区BM2向显示区AA的布线，且能够使第一扇出结构301和第二扇出结构302受到的横向IR drop都较 为均衡，进一步降低横向IR drop对显示亮度均一性的影响，提升显示屏亮度的均一性。
为了防止扇出结构在第一方向X的宽度过大而引起扇出结构与基材之间产生分离，可将扇出结构设计为多个导电单元，同一扇出结构中的各导电单元与同一第二电源输入端202电连接，每个导电单元为一个或多个像素列提供第一电源信号VDD或第二电源信号VSS。也可以将扇出结构进行局部镂空设计，例如，将扇出结构设计为网状结构，来防止扇出结构与基材之间产生分离。
需要说明的是，基材是指位于扇出结构之下且与扇出结构接触的膜层，通常为绝缘层材料。
在一些实施例中，如图8和图10所示，至少三个第二扇出结构302中的每个第二扇出结构302包括一个第二导电单元3021，每个第二导电单元3021与多个像素列中的至少一个像素列电连接。
示例的，如图8所示，一个第二扇出结构302包括一个第二导电单元3021，每个第二导电单元3021与一个像素列电连接。如此，可实现第二电源输入端201与像素列一一对应，能够完全避免横向IR drop，显著提升显示亮度的均一性。
再示例的，如图10所示，每个第二扇出结构302包括一个第二导电单元3021，每个第二导电单元3021与至少两个(两个或两个以上)像素列电连接。如此，可实现一个第二电源输入端201与多个像素列对应，既能够有效降低横向IR drop，提升显示亮度的均一性，又能够防止驱动芯片负载过重。
在另一些实施例中，如图9和图11所示，至少三个第二扇出结构302中每个第二扇出结构302包括多个第二导电单元3021，每个第二导电单元3021与至少一个像素列电连接。如此，在一个第二电源输入端201与多个像素列对应的情况下，既能够有效降低横向IR drop，提升显示亮度的均一性，又能够防止驱动芯片负载过重；并且每个扇出结构中设计多个导电单元能够避免扇出结构的面积过大而引起的扇出结构与基材分离的问题。
示例的，如图9所示，每个第二扇出结构302包括多个第二导电单元3021，其中，该多个第二导电单元3021中的每个第二导电单元与一个像素列电连接。
再示例的，如图11所示，第二扇出结构302包括多个第二导电单元3021，其中，该多个第二导电单元3021中每个第二导电单元3021与至少两个像素列电连接。如此，可实现一个第二电源输入端201与多个像素列对应，既能够有效降低横向IR drop，提升显示亮度的均一性，又能够防止驱动芯片负载 过重；并且每个扇出结构中设计多个导电单元能够避免扇出结构的面积过大而引起的扇出结构与基材分离的问题。
在一些实施例中，发光单元可以为微型发光二极管，即该阵列基板为micro LED阵列基板或mini LED阵列基板；发光单元还可以为有机发光二极管，即该阵列基板为OLED阵列基板，以下将对这两种发光单元的阵列基板进行详细说明。
在一些实施例中，发光单元包括第一电极和第二电极，每条阳极走线与多个像素列中的至少一个像素列中包括的多个发光单元的第一电极电连接。
示例的，如图7所示，发光单元101为微型发光二极管101a，微型发光二极管101a包括第一电极和第二电极；阵列基板的显示区包括多条阳极走线401和多条阴极走线402，每条阳极走线401与每个个像素列中包括的多个微型发光二极管101a的第一电极电连接，每条阴极走线402与每个像素列中包括的多个微型发光二极管101a的第二电极电连接。
再示例的，如图10所示，发光单元101为微型发光二极管101a，每条阳极走线301与多个像素列中的至少两个(两个或两个)以上的像素列中包括的多个微型发光二极管101a的第一电极电连接，每条阴极走线402与多个像素列中的至少两个(两个或两个)以上的像素列中包括的多个微型发光二极管101a的第二电极电连接。
在一些实施例中，第一扇出结构301与至少一条阳极走线401电连接，第二扇出结构302与至少一条阴极走线402电连接。示例的，如图8所示，第一扇出结构301与一条阳极走线401电连接，第二扇出结构302与至少一条阴极走线402电连接。再示例的，如图10所示，第一扇出结构301与多条(至少两条)阳极走线401电连接，第二扇出结构302与多条(至少两条)阴极走线402电连接。
需要说明的是，micro LED阵列基板或mini LED阵列基板并不包括微型发光二极管101a，微型发光二极管101a是在阵列基板的电路制作完成之后转移到阵列基板上，且与阵列基板上的电路进行电连接，再进行后续的绑定、封装以获得micro LED显示屏或mini LED显示屏。
当阵列基板为micro LED阵列基板或mini LED阵列基板时，可根据具体条件设计电源输入端与像素列的对应关系，从而降低横向IR drop，由于micro LED或mini LED的驱动电流较大，因此，降低横向IR drop的效果明显，对提升显示亮度的均一性具有显著的改善效果。
示例的，如图12和图13所示，发光单元101为有机发光二极管101b， 第一电极为阳极单元1013b，第二电极为阴极层1012b；阵列基板的显示区AA包括阴极层1012b、有机发光层1012b、多列阳极单元1013b以及阳极走线401，有机发光层1012b位于阴极层1011b与相应的阳极单元1013b之间；阳极走线401与多个像素列中的至少一个像素列中包括的多个有机发光二极管101b的阳极单元1013b电连接第二扇出结构302与阴极层1012b电连接。
需要说明的是，图12中的阳极走线401与阳极单元1013b的相对位置仅是示例性说明。在实际应用中，阳极走线401可与阳极单元1013b同层设置；阳极走线401也可以与阳极单元1013b位于不同膜层，并利于过孔进行连接。
在一些实施例中，如图14所示，第一扇出结构301包括一个第一导电单元3011，每个第一导电单元3011与一条阳极走线401电连接；第二扇出结构302包括一个第二导电单元3021，每个第二导电单元3021与阴极层1011b电连接。如此，可实现第一电源输入端201与像素列一一对应，能够完全避免横向IR drop，显著提升显示亮度的均一性。
在另一些实施例中，如图15所示，第一扇出结构301包括多个第一导电单元3011，该多个第一导电电压3011中每个第一导电单元3011与一条阳极走线401电连接；第二扇出结构302包括多个第二导电单元3021，该多个第二导电单元3021每个第二导电单元3021与阴极层1011b电连接。如此，可实现一个第一电源输入端201与多个像素列对应，既能够有效降低横向IR drop，提升显示亮度的均一性，又能够防止驱动芯片负载过重；并且每个扇出结构中设计多个导电单元能够避免扇出结构的面积过大而引起的扇出结构与基材分离的问题。
在又一些实施例中，如图16所示，第一扇出结构301包括一个第一导电单元3011，每个第一导电单元3011与多条阳极走线401电连接；第二扇出结构302包括一个第二导电单元3021，每个第二导电单元3021与阴极层1011b电连接。如此，可实现一个第一电源输入端201与多个像素列对应。
在又一些实施例中，如图17所示，第一扇出结构301包括多个第一导电单元3011，每个第一导电单元3011与多条阳极走线401电连接；第二扇出结构302包括一个或多个第二导电单元3021，每个第二导电单元3021与阴极层1011b电连接。如此，可实现一个第一电源输入端201与多个像素列对应，既能够有效降低横向IR drop，提升显示亮度的均一性，又能够防止驱动芯片负载过重；并且每个扇出结构中设计多个导电单元能够避免扇出结构的面积过大而引起的扇出结构与基材分离的问题。
在一些实施例中，阵列基板还包括阵列分布的像素电路，每个像素电路 被配置为向每个发光单元提供驱动信号，发光单元包括第一电极和第二电极；每个像素电路与一个第一电极电连接，每个第一电源输入端向多个像素列中的至少一个像素列中的像素电路提供第一电源信号，每个第二电源输入端向多个像素列中的至少一个像素列中包括的发光单元的第二电极提供第二电源信号。
示例的，在发光单元101为微型发光二极管101a的情况下，该微型发光二极管101a包括第一电极和第二电极，其中，像素电路与每个微型发光二极管101a的第一电极电连接，每个第一电源输入端201向多个像素列中的一个，或者多个像素电路提供第一电源信号VDD，每个第二电源输入端202向多个像素列中的一个，或者多个像素列中包括的微型发光二极管的第二电极提供第二电源信号VSS。
再示例的，在发光单元101为有机发光二极管101b的情况下，该有机发光二极管101b包括第一电极(即阳极)和第二电极(即阴极)，其中，像素地阿奴与每个有机发光二极管101b的阳极电连接，每个第一电源输入端201向多个像素列中的一个，或者多个像素电路提供第一电源信号VDD，每个第二电源输入端202向多个像素列中的一个，或者多个像素列中包括的有机发光二极管的阴极提供第二电源信号VSS。
在一些实施例中，如图18所示，非显示区BM还包括位于显示区AA远离第一绑定区BM1一侧的第二绑定区BM3，第二绑定区BM3，第二绑定区BM3包括多个为发光单元提供数据信号的数据信号输入端501。
在本实施例中，通过将数据信号输入端501和电源信号输入端设计在阵列基板的相对侧，能够防止数据信号和电源信号之间的干扰，并降低布线难度。
基于同一发明构思，本实施例提供了一种显示面板，如图19所示，本实施例提供的显示面板包括上述实施例中的阵列基板1，具有上述实施例中的阵列基板的有益效果，在此不再赘述。
具体地，本实施例中的显示面板还包括盖板2。
需要说明的是，当发光单元为微型发光二极管时，微型发光二极管并不是阵列基板的一部分，而是在阵列基板制成之后再转移到阵列基板上；而当发光单元为有机发光二极管时，阵列基板包括有机发光二极管。
本公开一些实施例还提供了一种显示装置，如图20所示，本实施例提供的显示装置包括上述实施例中的显示面板I，具有上述实施例中的显示面板的有益效果，在此不再赘述。
具体地，本实施例提供的显示装置还包括驱动芯片II和供电电源III。当阵列基板中包括设置在显示区相对两侧的第一绑定区和第二绑定区，驱动芯片II应包括第一驱动芯片和第二驱动芯片。其中，第一驱动芯片绑定在第一绑定区且与供电电源III电连接，供电电源III在第一驱动芯片的驱动下分别为第一电源输入端和第二电源输入端提供第一电源信号和第二电源信号；第二驱动芯片绑定在第二绑定区，为阵列基板提供数据信号。
在一些实施例中，在阵列基板的非显示区包括第一绑定区和第二绑定区的情况下，显示装置其还包括与第一绑定区BM1绑定的第一外部驱动电路，以及与第二绑定区BM3绑定的第二外部电路。
具体地，第一外部驱动电路和第二外部驱动电路可以是驱动芯片，即两个驱动芯片分别直接绑定在第一绑定区和第二绑定区；第一外部驱动电路和第二外部驱动电路也可以包括柔性电路板和驱动芯片，即驱动芯片绑定在柔性电路板上，柔性电路板再绑定在第一绑定区或第二绑定区。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种阵列基板，具有显示区和非显示区，所述非显示区包括第一绑定区，所述阵列基板包括：
    设置在所述显示区的多个像素列，所述多个像素列中的每个像素列包括多个发光单元；
    设置在所述第一绑定区的至少三个第一电源输入端，每个第一电源输入端与所述多个像素列中的至少一个像素列连接，以向所述至少一个像素列提供第一电源信号。
  2. 根据权利要求1所述的阵列基板，其中，不同的所述第一电源输入端连接的像素列不同。
  3. 根据权利要求1或2所述的阵列基板，其中，所述非显示区还包括扇出区，所述扇出区位于所述显示区与所述第一绑定区之间；
    所述扇出区包括至少三个第一扇出结构，每个第一电源输入端通过一个第一扇出结构与所述多个像素列中的至少一个像素列电连接，各所述第一扇出结构的电阻相等。
  4. 根据权利要求1～3任一项所述的阵列基板，其中，
    所述至少三个第一扇出结构中的每个第一扇出结构包括一个第一导电单元，所述第一导电单元与所述多个像素列中的至少一个所述像素列电连接；
    或者，
    所述第一扇出结构包括多个第一导电单元，所述多个第一导电单元中的每个导电单元与所述多个像素列中的至少一个所述像素列电连接。
  5. 根据权利要求1～4任一项所述的阵列基板，其中，
    每个所述第一电源输入端与一个所述像素列电连接；
    或者，每个所述第一电源输入端与至少两个所述像素列电连接。
  6. 根据权利要求1～5任一项所述的阵列基板，其中，所述发光单元包括第一电极；
    每条阳极走线与所述多个像素列中的至少一个像素列中包括的所述多个发光单元的第一电极电连接。
  7. 根据权利要求1～5任一项所述的阵列基板，其中，所述阵列基板还包括阵列分布的像素电路，每个像素电路被配置为向每个发光单元提供驱动信号，所述发光单元包括第一电极；
    每个像素电路与一个第一电极电连接，每个第一电源输入端向所述多个像素列中的至少一个像素列中的像素电路提供第一电源信号。
  8. 根据权利要求1～7任一项所述的阵列基板，其中，所述阵列基板还包 括：
    设置在所述第一绑定区的至少三个第二电源输入端，每个第二电源输入端与所述多个像素列中的至少一个像素列连接，以向所述至少一个像素列提供第二电源信号。
  9. 根据权利要求8所述的阵列基板，其中，不同的所述第二电源输入端连接的像素列不同。
  10. 根据权利要求8或9所述的阵列基板，其中，所述非显示区还包括扇出区，所述扇出区位于所述显示区与所述第一绑定区之间；
    所述扇出区包括至少三个第二扇出结构，每个第二电源输入端通过一个第二扇出结构与所述多个像素列中的至少一个像素列电连接，各所述第二扇出结构的电阻相等。
  11. 根据权利要求10所述的阵列基板，其中，
    在扇出区包括至少三个第一扇出结构的情况下，在第一方向上，所述第一扇出结构和所述第二扇出结构交替排布。
  12. 根据权利要求8～11任一项所述的阵列基板，其中，
    所述至少三个第二扇出结构中的每个第二扇出结构包括一个第二导电单元，所述第二导电单元与所述多个像素列中的至少一个所述像素列电连接；
    或者，
    所述第二扇出结构包括多个第二导电单元，所述多个第二导电单元中的每个导电单元与一个所述像素列电连接。
  13. 根据权利要求8～12任一项所述的阵列基板，其中，
    每个所述第二电源输入端与一个所述像素列电连接；
    或者，每个所述第二电源输入端与至少两个所述像素列电连接。
  14. 根据权利要求8～13任一项所述的阵列基板，其中，所述阵列基板还包括阵列分布的像素电路，每个像素电路被配置为向每个发光单元提供驱动信号，所述发光单元包括第二电极；
    每个第二电源输入端向所述多个像素列中的至少一个像素列中包括的发光单元的第二电极提供第二电源信号。
  15. 根据权利要求1～14任一项所述的阵列基板，其中，所述非显示区还包括位于所述显示区远离所述第一绑定区一侧的第二绑定区，所述第二绑定区包括多个为所述发光单元提供数据信号的数据信号输入端。
  16. 一种显示面板，包括权利要求1～15任一项所述的阵列基板。
  17. 一种显示装置，包括权利要求16所述的显示面板。
  18. 根据权利要求17所述的显示装置，其中，在阵列基板的非显示区包括第一绑定区和第二绑定区的情况下，所述显示装置还包括：与所述第一绑定区绑定的第一外部电路，以及与所述第二绑定区绑定的第二外部电路。
PCT/CN2021/072161 2020-01-16 2021-01-15 阵列基板、显示面板及显示装置 WO2021143846A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/615,514 US11955075B2 (en) 2020-01-16 2021-01-15 Array substrate, display panel and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010049497.1 2020-01-16
CN202010049497.1A CN113140589B (zh) 2020-01-16 2020-01-16 阵列基板、显示面板及显示装置

Publications (1)

Publication Number Publication Date
WO2021143846A1 true WO2021143846A1 (zh) 2021-07-22

Family

ID=76808518

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/072161 WO2021143846A1 (zh) 2020-01-16 2021-01-15 阵列基板、显示面板及显示装置

Country Status (3)

Country Link
US (1) US11955075B2 (zh)
CN (1) CN113140589B (zh)
WO (1) WO2021143846A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114530121A (zh) * 2022-03-18 2022-05-24 成都京东方光电科技有限公司 显示模组及显示装置
WO2023044985A1 (zh) * 2021-09-24 2023-03-30 惠州华星光电显示有限公司 显示面板及电子设备

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114200714B (zh) * 2021-12-10 2023-01-10 Tcl华星光电技术有限公司 背光源以及显示装置
CN114823837A (zh) * 2022-05-12 2022-07-29 云谷（固安）科技有限公司 显示面板和显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006084503A (ja) * 2004-09-14 2006-03-30 Seiko Epson Corp 電気光学装置及び電子機器
CN101488518A (zh) * 2008-01-18 2009-07-22 三星移动显示器株式会社 有机发光显示设备
CN103778884A (zh) * 2012-10-24 2014-05-07 乐金显示有限公司 有机发光显示装置
CN103811519A (zh) * 2012-11-01 2014-05-21 乐金显示有限公司 有机发光显示设备
CN103839516A (zh) * 2012-11-22 2014-06-04 乐金显示有限公司 有机发光显示器

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070002278A (ko) * 2005-06-30 2007-01-05 삼성전자주식회사 표시 기판 및 이를 구비한 표시 장치
JP6042187B2 (ja) * 2012-11-30 2016-12-14 株式会社ジャパンディスプレイ Ｏｌｅｄ表示装置
CN107195660B (zh) * 2017-05-27 2020-01-07 上海天马有机发光显示技术有限公司 有机发光显示面板及显示装置
CN108241240B (zh) * 2018-02-08 2021-05-14 上海天马微电子有限公司 一种显示面板以及显示装置
KR20200086771A (ko) * 2019-01-09 2020-07-20 삼성디스플레이 주식회사 유기 발광 표시 장치
CN109686312B (zh) * 2019-03-04 2021-01-22 京东方科技集团股份有限公司 显示面板及其驱动方法、显示装置
CN110310976B (zh) 2019-07-12 2022-01-18 京东方科技集团股份有限公司 显示基板和显示装置
CN110518048B (zh) * 2019-08-30 2022-04-08 武汉天马微电子有限公司 显示面板和显示装置
KR20210058399A (ko) * 2019-11-14 2021-05-24 엘지디스플레이 주식회사 투명 표시 패널 및 이를 포함하는 투명 표시 장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006084503A (ja) * 2004-09-14 2006-03-30 Seiko Epson Corp 電気光学装置及び電子機器
CN101488518A (zh) * 2008-01-18 2009-07-22 三星移动显示器株式会社 有机发光显示设备
CN103778884A (zh) * 2012-10-24 2014-05-07 乐金显示有限公司 有机发光显示装置
CN103811519A (zh) * 2012-11-01 2014-05-21 乐金显示有限公司 有机发光显示设备
CN103839516A (zh) * 2012-11-22 2014-06-04 乐金显示有限公司 有机发光显示器

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023044985A1 (zh) * 2021-09-24 2023-03-30 惠州华星光电显示有限公司 显示面板及电子设备
CN114530121A (zh) * 2022-03-18 2022-05-24 成都京东方光电科技有限公司 显示模组及显示装置
CN114530121B (zh) * 2022-03-18 2023-09-29 成都京东方光电科技有限公司 显示模组及显示装置

Also Published As

Publication number Publication date
CN113140589B (zh) 2022-12-09
US20230178016A1 (en) 2023-06-08
CN113140589A (zh) 2021-07-20
US11955075B2 (en) 2024-04-09

Similar Documents

Publication Publication Date Title
WO2021143846A1 (zh) 阵列基板、显示面板及显示装置
WO2022089071A1 (zh) 显示基板及显示装置
US20210296394A1 (en) Array substrate and preparation method therefor, and display panel and display device
CN109116626B (zh) 一种背光源及其制作方法、显示装置
CN113920943B (zh) 显示装置及其制作方法
CN111584757B (zh) 显示母板和显示基板的制作方法
US20110157114A1 (en) Electroluminescence device
US20240078960A1 (en) Display device
KR102443121B1 (ko) 디스플레이 패널 및 그 제조 방법 및 디스플레이 디바이스
KR20150095988A (ko) 표시 장치 및 이의 제조 방법
WO2022062761A1 (zh) 显示组件及显示装置
EP3462492B1 (en) Array substrate and display panel
WO2021217994A1 (zh) 显示基板及显示装置
WO2021121095A1 (zh) 阵列基板、显示面板及显示装置
WO2022156039A1 (zh) 显示面板及显示装置
WO2022083348A1 (zh) 显示基板和显示装置
CN112310140B (zh) Led背板的像素结构、led显示面板及其制作方法
CN110071068B (zh) 显示装置及其制造方法
EP4319536A1 (en) Display device
US20220399380A1 (en) Display device
WO2022057542A1 (zh) 一种显示背板及其制备方法、显示装置
WO2021244279A1 (zh) 显示面板和显示装置
WO2022110015A1 (zh) 显示基板、显示面板、显示装置
US20220320241A1 (en) Display Substrate and Preparing Method Thereof, and Display Apparatus
US11404009B2 (en) Array substrate and display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21741997

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21741997

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 13/02/2023)

122 Ep: pct application non-entry in european phase

Ref document number: 21741997

Country of ref document: EP

Kind code of ref document: A1