WO2023004798A1 - 发光基板及其制造方法、背光源、显示装置 - Google Patents

发光基板及其制造方法、背光源、显示装置 Download PDF

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Publication number
WO2023004798A1
WO2023004798A1 PCT/CN2021/109837 CN2021109837W WO2023004798A1 WO 2023004798 A1 WO2023004798 A1 WO 2023004798A1 CN 2021109837 W CN2021109837 W CN 2021109837W WO 2023004798 A1 WO2023004798 A1 WO 2023004798A1
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WO
WIPO (PCT)
Prior art keywords
light
emitting
signal line
terminal
driving circuit
Prior art date
Application number
PCT/CN2021/109837
Other languages
English (en)
French (fr)
Inventor
刘纯建
郝卫
许邹明
田�健
吴信涛
雷杰
王杰
张建英
范文金
徐佳伟
李乐
张健
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/109837 priority Critical patent/WO2023004798A1/zh
Priority to CN202180002041.2A priority patent/CN115918294A/zh
Priority to US17/786,975 priority patent/US20240170628A1/en
Priority to KR1020237043318A priority patent/KR20240041868A/ko
Priority to EP21951388.4A priority patent/EP4340566A1/en
Publication of WO2023004798A1 publication Critical patent/WO2023004798A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present disclosure relates to the field of optical technology, and in particular to a luminescent substrate and a manufacturing method thereof, a backlight source including the luminescent substrate, and a display device including the luminescent substrate.
  • Display devices are generally divided into two categories: liquid crystal display devices and organic light-emitting diode display devices.
  • Liquid crystal display devices are widely used due to their advantages of thinness, lightness, good shock resistance, wide viewing angle, and high contrast.
  • a liquid crystal display device generally includes a display panel and a backlight, and the backlight is usually disposed on a non-display side of the display panel to provide light for the display operation of the display panel.
  • Characteristics such as contrast ratio, brightness uniformity and stability of the liquid crystal display device are related to the structure and performance of the backlight source.
  • a light-emitting substrate including: a substrate including a plurality of light-emitting regions arranged in an array, each of the plurality of light-emitting regions includes a driving circuit and at least A light-emitting unit; a first conductive part located on the substrate and connected to the drive circuit in each light-emitting region and the at least one light-emitting unit; and a second conductive part located on the substrate and includes Multiple pads.
  • the first conductive part and the second conductive part are located at the same layer.
  • the plurality of light emitting regions are arranged in M rows along a first direction and N columns along a second direction intersecting with the first direction, and both M and N are positive integers greater than or equal to 1.
  • the first conductive portion includes N driving voltage signal lines and N common voltage signal lines extending along the first direction, each column of light-emitting areas includes a driving voltage signal line and a common voltage signal line, and emits light in each column In the area, the driving voltage signal line is connected to the first end of each light-emitting unit in the column of light-emitting areas, and the common voltage signal line is connected to each driving circuit in the column of light-emitting areas; in each column of light-emitting areas Inside, the driving voltage signal line, the light emitting unit, the driving circuit, and the common voltage signal line are arranged in sequence along the second direction.
  • the orthographic projections of the driving voltage signal line, the light emitting unit, the driving circuit, and the common voltage signal line on the substrate do not overlap each other.
  • each driving circuit includes a plurality of terminals arranged in an array, and the plurality of terminals are arranged in at least two columns along the second direction.
  • the plurality of terminals includes at least one output terminal and at least one common voltage terminal, the at least one output terminal and the at least one common voltage terminal being located in different columns of the plurality of terminals.
  • the at least one output terminal of each driving circuit is connected to the second end of the at least one light-emitting unit connected to the driving circuit in a one-to-one correspondence, and the at least one common output terminal of each driving circuit
  • the voltage terminal is connected to the common voltage signal line in the column of light-emitting areas.
  • the multiple terminals further include an address terminal, a relay terminal and a power supply terminal, each driving circuit in each row of light-emitting areas is cascaded in sequence, and the address terminal of the i-th level driving circuit is located in the A side of the i-level driving circuit close to the i-1th level driving circuit, the relay terminal of the i-level driving circuit is located on a side of the i-level driving circuit close to the i+1-th level driving circuit, 1 ⁇ i ⁇ M and i is a positive integer, the address terminal is configured to receive an address signal, the relay terminal is configured to output a relay signal, and the power supply terminal is configured to receive a power supply voltage signal.
  • the extending direction of the first conductive portion is parallel to the cascading direction of the driving circuits.
  • a plurality of terminals of the driving circuit are arranged in a first column and a second column along the second direction, and in each column of the light-emitting area, the terminals of the first column of the driving circuit are located in the driving A side of the circuit adjacent to the driving voltage signal line, the second column terminal of the driving circuit is located on a side of the driving circuit adjacent to the common voltage signal line.
  • the first conductive part further includes N power signal lines
  • each column of light-emitting areas includes a power signal line
  • each power signal line includes a main body part and a first connection part
  • the power signal lines The body portion extends along the first direction.
  • the power signal line is connected to the power terminal of each driving circuit in the column of the light-emitting area through the first connection part
  • the first column terminal is on the substrate
  • the orthographic projection of the terminal and the orthographic projection of the second row of terminals on the substrate are respectively located on both sides of the orthographic projection of the power signal line on the substrate.
  • the first conductive portion further includes N address signal lines extending along the first direction, and each column of light emitting regions includes one address signal line. In each column of the light-emitting area, the address selection signal line is connected to the address terminal of the first-level driving circuit.
  • the first conductive portion further includes a cascaded wiring extending along the first direction, and the cascaded wiring is located between two adjacent cascaded driving circuits in each row of light emitting regions. , and the relay terminal of the i-th level driving circuit is connected to the address terminal of the (i+1)-th level driving circuit via the cascade wiring.
  • the first conductive portion further includes N feedback signal lines extending along the first direction, and each row of light emitting regions includes a feedback signal line.
  • the feedback signal line is connected to the relay terminal of the last-stage drive circuit, and the feedback signal line is at least partially located in the common voltage signal line in the column of light-emitting areas away from all one side of the drive circuit.
  • the driving voltage signal line, the address selection signal line, the cascaded wiring, the power signal line, the common voltage signal line, and the feedback signal line are on the substrate
  • the orthographic projections on the base do not overlap each other.
  • the plurality of terminals of the driving circuit includes the address terminal, the power supply terminal, the common voltage terminal, and the output terminal.
  • the first column terminals include the output terminal and the address terminal, and the second column terminals include the common voltage terminal and the power supply terminal.
  • the output terminal of the drive circuit and the relay terminal are the same terminal, and the drive circuit is configured to output a relay signal through the output terminal within a first period of time as The address signal of the driving circuit at the next stage cascaded with the driving circuit provides a driving signal to the at least one light-emitting unit connected to the driving circuit through the output terminal in the second period.
  • the plurality of terminals of the driving circuit further includes data terminals, and the data terminals and the power supply terminals are located in different columns of the plurality of terminals.
  • the driving circuit has multiple output terminals and at least one common voltage terminal.
  • the first column of terminals includes the power supply terminal and the plurality of output terminals, and the second column of terminals includes the address terminal, the relay terminal, the data terminal, and the at least one common voltage terminal.
  • the first conductive portion further includes N data driving signal lines, each column of light emitting regions includes a data driving signal line, each data driving signal line includes a main body portion and a second connection portion, the data The main body portion of the driving signal line extends along the first direction.
  • the data driving signal line is connected to the data terminal of each driving circuit in the column of the light-emitting area through the second connection part, and the first column terminal is connected to the substrate
  • the orthographic projection on the substrate and the orthographic projection of the second column terminal on the substrate are respectively located on both sides of the orthographic projection of the data driving signal line on the substrate, and the data driving signal line is on the The orthographic projection on the substrate does not overlap with the orthographic projection of the power signal line on the substrate.
  • the plurality of output terminals of the driving circuit are connected to the second terminals of the plurality of light emitting units connected to the driving circuit in a one-to-one correspondence.
  • the drive circuit is configured to output a relay signal through the relay terminal as the address signal of a next-stage drive circuit cascaded with the drive circuit during a first period, and to output a relay signal through the relay terminal during a second period.
  • the plurality of output terminals respectively provide driving signals to the plurality of light emitting units.
  • the distance between the driving voltage signal line and other adjacent signal lines is greater than or equal to 0.2 mm.
  • the light-emitting substrate further includes a plurality of flexible circuit boards and a fan-out area.
  • Each signal line of the first conductive part includes a straight portion and a bent portion, the bent portion of each signal line is located in the fan-out area, and each signal line passes through the bent portion It is connected with the plurality of flexible circuit boards, and the width of the bent portion of each signal line along the second direction is smaller than the width of two adjacent columns of light emitting regions along the second direction.
  • the included angle between the straight portion and the bent portion of each signal line is 80° ⁇ 100°.
  • the material of the first conductive portion and the second conductive portion includes copper.
  • each light emitting unit includes a plurality of light emitting elements connected to each other, each of the plurality of light emitting elements includes a submillimeter light emitting diode or a micro light emitting diode.
  • the light-emitting substrate further includes a shielding ring, the shielding ring surrounds the periphery of the plurality of light-emitting regions, and the electrical signal received by the shielding ring is the same as the electrical signal received by the common voltage signal line. same.
  • the light-emitting substrate further includes a buffer layer and an insulating layer.
  • the buffer layer is located between the layer where the first conductive part and the second conductive part are located and the substrate, and the insulating layer is located in the layer where the first conductive part and the second conductive part are located side away from the substrate.
  • a backlight comprising the light-emitting substrate described in any one of the foregoing embodiments.
  • a display device which includes the light emitting substrate described in any one of the foregoing embodiments.
  • a method of manufacturing a light-emitting substrate comprising the steps of: providing a substrate; forming a conductive layer on the substrate, and simultaneously forming a first substrate by patterning the conductive layer. a conductive part and a second conductive part including a plurality of pads; and mounting a plurality of driving circuits and a plurality of light emitting units on the substrate to form a plurality of light emitting regions arranged in an array, and among the plurality of light emitting regions Each includes a driving circuit and at least one light emitting unit connected to the driving circuit. The first conductive portion is connected to the driving circuit and the at least one light emitting unit in each light emitting region.
  • FIG. 1 shows a schematic layout of a light-emitting substrate provided according to an embodiment of the present disclosure
  • Fig. 2 shows a schematic wiring diagram of a light-emitting substrate provided according to an embodiment of the present disclosure
  • FIG. 3 shows a schematic diagram of the arrangement of terminals of the drive circuit of the light-emitting substrate in FIG. 2;
  • FIG. 4 shows a schematic diagram of the arrangement of the first pads of the light-emitting substrate in FIG. 2;
  • Fig. 5 shows a partially enlarged schematic diagram of Fig. 2;
  • FIG. 6 shows a schematic wiring diagram of a light-emitting substrate provided according to an embodiment of the present disclosure
  • Fig. 7 shows a schematic wiring diagram of a light-emitting substrate provided according to another embodiment of the present disclosure.
  • FIG. 8 shows a schematic diagram of the arrangement of the first pads of the light-emitting substrate in FIG. 7;
  • Fig. 9 shows a partially enlarged schematic diagram of Fig. 7;
  • Fig. 10 shows a partially enlarged schematic diagram of Fig. 9
  • Fig. 11A shows a schematic layout of a flexible circuit board of a light-emitting substrate according to an embodiment of the present disclosure
  • Figure 11B shows a partial enlarged view of region I in Figure 11A;
  • Fig. 12 shows a schematic diagram of the arrangement of light emitting units of a light emitting substrate according to an embodiment of the present disclosure
  • Fig. 13 shows a schematic structural view of a light-emitting substrate provided according to an embodiment of the present disclosure
  • Fig. 14 shows a block diagram of a backlight provided according to yet another embodiment of the present disclosure.
  • Fig. 15 shows a block diagram of a display device provided according to yet another embodiment of the present disclosure.
  • Fig. 16 shows a flow chart of a method for manufacturing a light-emitting substrate according to yet another embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a light-emitting substrate, and FIG. 1 shows a schematic layout of the light-emitting substrate 100 .
  • the light-emitting substrate 100 includes a substrate 101 , a first conductive portion 105 and a second conductive portion 106 arranged on the substrate 101 .
  • the substrate 101 includes a plurality of light emitting regions 102 arranged in an array, and each light emitting region 102 includes a driving circuit 103 and at least one light emitting unit 104 connected to the driving circuit 103 .
  • the first conductive part 105 is connected to the driving circuit 103 and the light emitting unit 104 in each light emitting region 102 , for example, the first conductive part 105 may include a plurality of signal wires.
  • the dotted line box on the left side of FIG. 1 shows an enlarged schematic diagram of a light-emitting region 102.
  • the second conductive part 106 includes a plurality of pads, and the plurality of pads include, for example, a plurality of first pads 107. and a plurality of second pads 108 , the driving circuit 103 is mounted on the first pads 107 , and the light emitting unit 104 is mounted on the second pads 108 .
  • the first conductive portion 105 and the second conductive portion 106 are located on the same layer.
  • the term "A and B are located in the same layer” means that A and B are located on the surface of the same film layer and both are in direct contact with the surface.
  • a and B are formed from the same film layer by using the same process.
  • a and B are located on the surface of the same film layer and both are in direct contact with the surface, and A and B have substantially the same height or thickness.
  • FIG. 1 is only used to schematically show the connection relationship between the driving circuit 103, the light emitting unit 104 and the first conductive part 105 and the second conductive part 106.
  • the driving circuit 103, the light emitting unit 104, the first conductive part The dimensions of the portion 105 and the second conductive portion 106 are not drawn to scale, and their relative positional relationship does not necessarily completely correspond to the actual position. In the drawings, the scale of some regions and layers may be exaggerated for clarity.
  • the single-layer conductive layer can not only be used to make the first pad 107 and the second pad 108 of the second conductive part 106 and to connect the driving circuit 103 and light emitting
  • the wiring of the unit 104 can also be used to make a plurality of signal lines of the first conductive part 105 to transmit corresponding electrical signals to the driving circuit 103 and the light emitting unit 104 in each light emitting region 102 .
  • At least two conductive layers are usually used to realize the above-mentioned electrical connection relationship, that is, the first pad and the second pad are made through the first conductive layer, and the The second conductive layer of the first layer is used to make signal lines to transmit corresponding electrical signals. Since the first conductive layer and the second conductive layer inevitably overlap in the direction perpendicular to the substrate, and the overlapping area of the two is a weak performance area, the gap between the first conductive layer and the second conductive layer It is very easy to have a short circuit or an open circuit, thereby affecting the light-emitting performance of the light-emitting substrate.
  • the first conductive part 105 and the second conductive part 106 of the present application are located on the same layer.
  • the first conductive part can be completely avoided.
  • 105 and the second conductive portion 106 are short-circuited or disconnected due to overlapping in a direction perpendicular to the substrate 101 , thereby improving the light-emitting performance of the light-emitting substrate 100 and improving the light-emitting stability of the light-emitting substrate 100 .
  • the first conductive portion 105 and the second conductive portion 106 can be simultaneously formed from the same material through the same process, so the number of masks used can be reduced, the production cost can be reduced, and the manufacturing process can be simplified at the same time. ,Increase productivity.
  • a plurality of light emitting regions 102 are arranged in M rows along a first direction D1 and in N columns along a second direction D2 intersecting the first direction D1 , where M and N are both positive integers greater than or equal to 1.
  • the first direction D1 may be the vertical direction in the figure
  • the second direction D2 may be the horizontal direction in the figure
  • the first direction D1 and the second direction D2 may be perpendicular to each other.
  • the first conductive part 105 includes N driving voltage signal lines VLEDL and N common voltage signal lines GNDL extending along the first direction D1, so that each column of the light emitting region 001 includes one driving voltage signal line VLEDL and one common voltage signal line GNDL .
  • a driving voltage signal line VLEDL is connected to the first end of each light-emitting unit 104 in the column of light-emitting area 001, and a common voltage signal line GNDL is connected to the first end of each light-emitting unit 104 in the column of light-emitting area 001.
  • Circuit 103 is connected.
  • the driving voltage signal line VLEDL is configured to provide a driving voltage to the light emitting unit 104
  • the common voltage signal line GNDL is configured to provide a common voltage (such as a ground voltage) to the driving circuit 103, for example, when it is necessary to make the light emitting unit 104 in a certain light emitting area 102 emit light
  • a common voltage such as a ground voltage
  • the driving voltage signal line VLEDL, the light emitting unit 104 , the driving circuit 103 , and the common voltage signal line GNDL are sequentially arranged along the second direction D2.
  • the driving circuits 103 that is, the driving circuits 103 in rows 1 to M
  • the driving circuits 103 are arranged in driving circuit columns, along the direction from left to right in the figure in the second direction D2, according to the driving voltage signal line VLEDL, the light emitting unit column, the driving circuit
  • the order of the columns and the common voltage signal line GNDL is arranged in sequence.
  • the orthographic projections of the driving voltage signal line VLEDL, the light emitting unit column, the driving circuit column, and the common voltage signal line GNDL on the substrate 101 do not overlap each other.
  • short circuit or open circuit between the driving voltage signal line VLEDL and the common voltage signal line GNDL of the first conductive part 105 and the first pad 107 and the second pad 108 of the second conductive part 106 can be completely avoided. , so that the light emitting performance of the light emitting substrate 100 can be improved, and the light emitting stability of the light emitting substrate 100 can be improved.
  • the driving circuit 103 may be an integrated circuit, especially a packaged chip with multiple terminals.
  • the driving circuit 103 may include one output terminal, or may include at least two output terminals, such as two output terminals, three output terminals, four output terminals or more output terminals.
  • the layout of each terminal of the drive circuit 103 of the present application is optimized compared with the related art, so that it can better match the wiring of each signal line, so that no matter whether the signal lines are perpendicular to the substrate 101 There is no overlap in either direction or in a direction parallel to the substrate 101 .
  • each driving circuit 103 includes a plurality of terminals arranged in an array along the first direction D1 and the second direction D2, and the plurality of terminals are arranged in at least two columns along the second direction D2.
  • the plurality of terminals includes at least one output terminal Out and at least one common voltage terminal GND, the at least one output terminal Out and the at least one common voltage terminal GND are located in different columns of the plurality of terminals.
  • each driving circuit 103 is connected to the second end of at least one light-emitting unit 104 connected to the driving circuit 103 in a one-to-one correspondence, so as to transmit the driving signal to at least one light-emitting unit.
  • Unit 104; at least one common voltage terminal GND of each driving circuit 103 is connected to the common voltage signal line GNDL to receive the common voltage (eg, ground voltage) transmitted by the common voltage signal line GNDL.
  • the driving circuit 103 also includes address terminals Di/Di_in, relay terminals Out/Di_out, and power supply terminals Pwr/Vcc.
  • Each drive circuit 103 in each column of light-emitting area 001 is cascaded in sequence, and the address terminal Di/Di_in of the i-th drive circuit 103 is located on the side of the i-th drive circuit 103 close to the i-1th drive circuit 103, and the i-th drive circuit 103
  • the relay terminal Out/Di_out of the stage driving circuit 103 is located on the side of the i-th stage driving circuit 103 close to the (i+1)-th stage driving circuit 103 , 1 ⁇ i ⁇ M and i is a positive integer.
  • each driving circuit 103 in each column of light-emitting area 001 is cascaded sequentially from bottom to top along the first direction D1, and the i-th level of driving circuit 103 refers to the The i-th driving circuit 103 counts up from the M-th row driving circuit 103 .
  • the driving circuit 103 located in the first column and row M is the first-level driving circuit
  • the driving circuit 103 located in the first column and the M-1 row is the second-level driving circuit.
  • the driving circuit 103 located in the first column and the second row is the M-1th level driving circuit
  • the driving circuit 103 located in the first column and the first row is the Mth level driving circuit.
  • the address terminal is Di
  • the relay terminal is Out
  • the power terminal is Pwr.
  • the output terminal Out is multiplexed as a relay terminal, that is, the output terminal Out and the relay terminal are the same terminal, and the output terminal Out outputs different signals in different time periods, for example, as a relay terminal Output relay signal and drive signal as output terminal.
  • the address terminal is Di_in
  • the relay terminal is Di_out
  • the power supply terminal is Vcc.
  • the output terminal Out and the relay terminal Di_out are two different terminals.
  • the address terminals Di/Di_in are configured to receive address signals
  • the relay terminals Out/Di_out are configured to output relay signals
  • the power terminals Pwr/Vcc are configured to receive power voltage signals.
  • a plurality of terminals of the driving circuit 103 are arranged in a first column and a second column along the second direction D2, and in each column of the light-emitting area 001, the terminals of the first column of the driving circuit 103 are located adjacent to the driving voltage signal line VLEDL of the driving circuit 103.
  • the second column terminal of the driving circuit 103 is on the side of the driving circuit 103 adjacent to the common voltage signal line GNDL (ie on the right side of the driving circuit 103 ).
  • This arrangement of the terminals of the driving circuit 103 is beneficial to promote the regular arrangement of the signal traces, so that the signal traces do not overlap with each other, thereby avoiding the short circuit caused by the overlap between the signal traces / open circuit or signal crosstalk.
  • the first conductive portion 105 further includes N address signal lines ADDRL extending along the first direction D1, so that each column of light emitting regions 001 includes one address signal line ADDRL.
  • Fig. 2 and Fig. 7 only show that the light-emitting substrate includes four light-emitting regions 102, and the four light-emitting regions 102 are arranged in a manner of 2 rows*2 columns, this is only a partial screenshot of the light-emitting substrate.
  • the light-emitting substrate usually includes A plurality of light emitting regions 102, the plurality of light emitting regions 102 are arranged in M rows and N columns, where M and N are any positive integers greater than or equal to 1.
  • each column of light emitting regions 001 includes a plurality of driving circuits 103, and the driving circuits 103 are cascaded sequentially through the cascading wiring 111 extending along the first direction D1.
  • the address selection signal line ADDRL is connected to the address terminal Di/Di_in of the first-level drive circuit 103, and the relay terminal Out/Di_out of the upper-level drive circuit is connected to the address terminal of the next-level drive circuit 103 via the cascaded wiring 111 Di/Di_in.
  • each column of light emitting regions 001 is shown as including two driving circuits 103 , and the two driving circuits 103 are sequentially cascaded through the cascading wiring 111 extending along the first direction D1 .
  • the address selection signal line ADDRL is connected to the address terminal Di of the first-level driving circuit 103
  • the relay terminal Out of the first-level driving circuit is connected to the address terminal Di of the second-level driving circuit 103 via the cascaded wire 111 .
  • each column of light emitting regions 001 is shown as including two driving circuits 103 , and the two driving circuits 103 are sequentially cascaded through the cascading wiring 111 extending along the first direction D1 .
  • the address selection signal line ADDRL is connected to the address terminal Di_in of the first-level driving circuit 103 , and the relay terminal Di_out of the first-level driving circuit is connected to the address terminal Di_in of the second-level driving circuit 103 via the cascaded wire 111 .
  • the address selection signal line ADDRL is configured to transmit an address signal to the address terminal Di/Di_in of the first-level driving circuit 103 in each column of the light-emitting area 001. After receiving the address signal, the first-level driving circuit 103 can analyze, obtain and store the address signal.
  • the address information in the address signal is used as the address information of the first-level drive circuit 103, and the address information can be incremented by 1 or another fixed amount and the incremented address information (new address information) can be modulated into Relay signal, the relay terminal Out/Di_out of the first-level drive circuit 103 transmits the relay signal to the address terminal Di/Di_in of the second-level drive circuit 103 via the cascade wiring 111, as the second-level drive circuit 103 address information.
  • the first-level driving circuit 103 may also use any other appropriate function to transform its address information to generate a relay signal.
  • the second-level driving circuit 103 transmits a relay signal to the third-level driving circuit 103 in a similar manner as the address information of the third-level driving circuit 103 , and so on.
  • corresponding address information can be configured for each of the plurality of cascaded driving circuits 103 in each column of light emitting regions 001 . It can be seen that, for a row of light-emitting regions 001, only one address signal needs to be provided through one address selection signal line ADDRL, so that all the driving circuits 103 in the row of light-emitting regions 001 can obtain their respective address information. This greatly reduces the number of signal lines, saves wiring space, and simplifies the control method.
  • the first conductive portion 105 further includes N feedback signal lines FBL extending along the first direction D1, and each row of light emitting regions 001 includes a feedback signal line FBL.
  • the feedback signal line FBL is connected to the relay terminal Out/Di_out of the last-stage driving circuit 103 .
  • the feedback signal line FBL bypasses the common voltage signal line GNDL in the column light-emitting area 001 and is located on a side of the common voltage signal line GNDL away from the driving circuit 103 .
  • the first conductive portion 105 further includes N power signal lines PwrL/VccL, and each row of light emitting regions 001 includes one power signal line PwrL/VccL.
  • Each power signal line PwrL/VccL includes a main body portion and a first connection portion 118 , and the main body portion of the power signal line PwrL/VccL extends along the first direction D1.
  • a power signal line PwrL/VccL is connected to the power supply terminals Pwr/Vcc of all drive circuits 103 in the column of light-emitting area 001 through the first connection part 118, and the first column of each drive circuit 103
  • the orthographic projection of the terminal on the substrate 101 and the orthographic projection of the second row of terminals on the substrate 101 are respectively located on both sides of the orthographic projection of the power signal line PwrL/VccL on the substrate 101, that is, the power supply signal line PwrL/VccL
  • the signal line PwrL/VccL is arranged within the area occupied by each drive circuit 103 without overlapping the first column terminal and the second column terminal of each drive circuit 103 .
  • the wiring space can be saved, and the intersection between the power signal line PwrL/VccL and other signal lines can be avoided. stack.
  • the signal line generally includes a main body part and a connecting part, the main part defines the main extension direction of the signal line, and the connecting part is used to connect the signal line with required components connected.
  • the driving voltage signal line VLEDL is connected to the second end of the light emitting unit 104 through its connecting portion;
  • the power signal line PwrL/VccL is connected to the power terminal Pwr/Vcc of the driving circuit 103 through the first connecting portion 118;
  • the common voltage signal line GNDL It is connected to the common voltage terminal GND of the drive circuit 103 through its connecting portion.
  • the connection part of each signal line is very small in length or width compared with its main part.
  • phrases such as "the X signal line extending along the first direction D1" only define that the main part of the X signal line extends along the first direction D1, but do not limit the connection of the X signal line.
  • the portion extends along the first direction D1.
  • the main body portion of each power signal line PwrL/VccL extends along the first direction D1, and its first connecting portion 118 does not extend along the first direction D1, but along a direction intersecting the first direction D1 (such as the second The direction D2) extends.
  • the power signal line PwrL/VccL is configured to transmit a power voltage signal to the power terminal Pwr/Vcc of each driving circuit 103 , thereby providing power voltage for each driving circuit 103 .
  • the supply voltage signal is a power line carrier communication signal.
  • the power signal line PwrL/VccL can not only provide the power supply voltage to each driving circuit 103, but also provide communication data to each driving circuit 103, and the communication data can be used to control the The light-emitting duration of at least one light-emitting unit 104 controls its visual light-emitting brightness.
  • the power line carrier communication signal contains information corresponding to communication data.
  • the communication data is the data reflecting the duration of light emission, and further represents the required light emission brightness.
  • the embodiment of the present disclosure adopts the power line carrier communication (Power Line Carrier Communication, PLC) protocol to superimpose the communication data on the power signal line PwrL/VccL , thereby effectively reducing the number of signal lines.
  • PLC Power Line Carrier Communication
  • the terminals of the driving circuit 103 adopt the above-mentioned arrangement method, so that in each column of the light-emitting area 001, the driving voltage signal line VLEDL of the first conductive part 105, the address selection signal
  • the orthographic projections of the line ADDRL, the cascade wiring 111 , the power signal line PwrL/VccL, the common voltage signal line GNDL, and the feedback signal line FBL on the substrate 101 do not overlap each other.
  • the orthographic projections of the driving voltage signal line VLEDL, the common voltage signal line GNDL, and the feedback signal line FBL of the first conductive part 105 on the substrate 101 are consistent with the first pad 107 and the second pad 107 of the second conductive part 106.
  • the orthographic projections of the pads 108 on the substrate 101 also do not overlap.
  • the short circuit or open circuit caused by overlapping of the first conductive portion 105 and the second conductive portion 106 on the same layer can be completely avoided, thereby improving the luminous performance of the light-emitting substrate and improving the light-emitting stability of the light-emitting substrate.
  • Some common characteristics of the light-emitting substrate 200 and the light-emitting substrate 300 are described above. Below, two examples are used to describe the specific arrangement of the light-emitting substrate 200 and the specific arrangement of the light-emitting substrate 300 respectively.
  • FIG. 2 shows the arrangement of the light emitting substrate 200 .
  • FIG. 2 only shows four light emitting regions 102, and the four light emitting regions 102 are arranged in a manner of 2 rows*2 columns, this is only a partial screenshot of the light emitting substrate 200, and the light emitting substrate 200 may include any suitable number of light emitting regions. 102, any suitable number of light emitting regions 102 may be arranged in multiple rows and multiple columns. The embodiments of the present disclosure do not specifically limit the number of light emitting regions 102 included in the light emitting substrate 200 .
  • each light emitting region 102 includes a driving circuit 103 and a light emitting unit 104 connected to the driving circuit 103 .
  • FIG. 3 shows the layout of the terminals of the drive circuit 103 .
  • each driving circuit 103 includes four terminals, namely an address terminal Di, a power supply terminal Pwr, a common voltage terminal GND, and an output terminal Out.
  • the output terminal Out and the address terminal Di are the first column terminals of the drive circuit 103, which are located on the side of the drive circuit 103 adjacent to the drive voltage signal line VLEDL (that is, on the left side of the drive circuit 103);
  • the common voltage terminal GND and the power supply terminal Pwr is the second column terminal of the driving circuit 103 , which is located on a side of the driving circuit 103 adjacent to the common voltage signal line GNDL (ie, on the right side of the driving circuit 103 ).
  • the address terminal Di and the power terminal Pwr are located in the second row among the plurality of terminals, and the common voltage terminal GND and the output terminal Out are located in the first row among the plurality of terminals.
  • the output terminal Out is multiplexed as a relay terminal.
  • the output terminal Out of the first-stage drive circuit 103 that is, the drive circuit 103 located in the second row and the first column in FIG. 2
  • One end is connected to the light-emitting unit 104 corresponding to the driving circuit 103, and the other end is connected to the address of the second-level driving circuit 103 (that is, the driving circuit 103 located in the first row and the first column in FIG.
  • the output terminal Out of the second stage driving circuit 103 is connected to the light emitting unit 104 corresponding to the driving circuit 103, and the other end is connected to the feedback wiring FBL.
  • the output terminal Out can output different signals in different time periods.
  • the output terminal Out of the driving circuit 103 outputs a relay signal in a period of time as an address signal of the next-level driving circuit 103 cascaded with the driving circuit 103, and emits light to the device connected to the driving circuit 103 in another period of time.
  • the unit 104 provides a driving signal to make the light emitting unit 104 emit light.
  • the one period and the other period are two separate periods, eg the other period immediately follows the one period.
  • the driving signal may be, for example, a driving current for driving the light emitting unit 104 to emit light. It should be noted that, when the driving signal is a driving current, the driving current may flow from the output terminal Out to the light emitting unit 104, or may flow from the light emitting unit 104 to the output terminal Out, and the flow direction of the driving current may be determined according to actual needs. The embodiments are not limited to this.
  • the distance between the terminals of the driving circuit 103 of the light-emitting substrate 200 is generally determined according to many factors (such as process limit capability, line width requirements between two columns of terminals, electrical design requirements, etc.). Not specifically limited.
  • the distance between the terminals in the first row and the terminals in the second row may be 70-300um
  • the distance between the terminals in the first row and the terminals in the second row may be 70-300um.
  • the spacing S1 between the terminals in the first column and the terminals in the second column is 140 ⁇ m
  • the spacing S2 between the terminals in the first row and the terminals in the second row is 120 ⁇ m.
  • the distance between the output terminal Out and the common voltage terminal GND is 140 ⁇ m
  • the distance between the address terminal Di and the power terminal Pwr is 140 ⁇ m
  • the distance between the output terminal Out and the address terminal Di is 120 ⁇ m
  • the common voltage terminal The distance between GND and the power terminal Pwr is 120 ⁇ m.
  • the four terminals of the driving circuit 103 occupy substantially the same area, and have substantially the same length and width.
  • the width S3 of each terminal along the second direction D2 is 80 ⁇ m
  • the length S4 of each terminal along the first direction D1 is 100 ⁇ m.
  • the spacing S5 between the second row terminal and the first side of the driving circuit 103 is 25 ⁇ m, that is, the spacing S5 between the address terminal Di and the power supply terminal Pwr and the lower edge of the driving circuit 103 Both are 25 ⁇ m;
  • the spacing S5 between the first row terminal and the second side of the driving circuit 103 is 25 ⁇ m, that is, the output terminal Out and the common voltage terminal GND and the upper edge of the driving circuit 103
  • the intervals S5 between them are both 25 ⁇ m.
  • the spacing S6 between the first column terminal and the third side of the driving circuit 103 is 25 ⁇ m, that is, the spacing S6 between the output terminal Out and the address terminal Di and the left edge of the driving circuit 103 Both are 25 ⁇ m;
  • the spacing S6 between the second column terminal and the fourth side of the drive circuit 103 is 25 ⁇ m, that is, the common voltage terminal GND and the power supply terminal Pwr and the right edge of the drive circuit 103
  • the intervals S6 between them are both 25 ⁇ m.
  • the length L of the driving circuit 103 along the first direction D1 is 370 ⁇ m
  • the width W of the driving circuit 103 along the second direction D2 is 350 ⁇ m.
  • the distance between the power signal line PwrL and the terminals in the first column and the terminals in the second column may be 10-100 um, respectively.
  • the width of the power signal line PwrL between the first column terminal and the second column terminal along the second direction D2 is greater than or equal to 40 um.
  • each column of light-emitting area 001 includes a driving voltage signal line VLEDL, an address selection signal line ADDRL, a cascade wiring 111, a power signal line PwrL, a common voltage signal line GNDL, and a feedback signal line FBL.
  • the lines do not overlap each other neither in the direction perpendicular to the substrate 101 nor in the direction parallel to the substrate 101 .
  • the functions and arrangement of these signal lines are as described above, and for the sake of brevity, details are not repeated here.
  • the driving circuit 103 starts to work, firstly, the power supply terminal Pwr of each driving circuit 103 in each row of light-emitting area 001 is provided with a power supply voltage through the power signal line PwrL to complete initialization, so that the driving circuit 103 is in a power-on state.
  • the write address operation is performed in the first period, that is, the ADDRL signal line inputs the address signal to the first-level driving circuit 103 through the address terminal Di, so as to write the address.
  • the driving configuration is performed, and the first-level driving circuit 103 outputs a relay signal through the output terminal Out, and the relay signal is transmitted to the address terminal Di of the second-level driving circuit 103 through the cascaded wiring 111 , as an address signal for the second-level driving circuit 103.
  • the driving configuration is performed, and the first-level driving circuit 103 outputs a relay signal through the output terminal Out, and the relay signal is transmitted to the address terminal Di of the second-level driving circuit 103 through the cascaded wiring 111 , as an address signal for the second-level driving circuit 103.
  • the driving voltage is supplied to the driving voltage signal line VLEDL.
  • the third period enters after all the driving circuits 103 have acquired the corresponding address information. At this time, the driving voltage transmitted on the driving voltage signal line VLEDL becomes high level.
  • the output terminal Out of each driving circuit 103 provides a driving signal (for example, a driving current) according to the required lighting duration.
  • a driving signal for example, a driving current
  • the driving voltage signal line VLEDL, the light emitting unit 104, and the light emitting unit 104 are electrically
  • the connected output terminal Out and the common voltage signal line GNDL form a signal loop, and the light emitting unit 104 emits light according to the required light emitting time.
  • the system is shut down, that is, the driving circuit 103 is powered off, and the driving voltage provided by the driving voltage signal line VLEDL becomes low level, and the light emitting unit 104 stops emitting light.
  • the light-emitting substrate 200 shown in FIG. 2 can realize regional dimming.
  • the light-emitting substrate 200 includes a plurality of light-emitting regions 102, and each light-emitting region includes a drive circuit 103 and a light-emitting unit 104 connected to the drive circuit 103 and controlled by the drive circuit 103, so that the light-emitting brightness of each light-emitting unit 104 can be are controlled independently. For example, by setting the address signal and the power supply voltage signal provided to each driving circuit 103 , the light-emitting duration of the light-emitting unit 104 connected to each driving circuit 103 can be controlled respectively, thereby controlling the visual light-emitting brightness.
  • the light-emitting substrate 200 can realize independent control of light-emitting brightness by region, and has a wide range of applications. Moreover, the number of ports of each driving circuit 103 is small, and the required control signals are small, so the control method is simple, the power consumption is small, and the operation is convenient.
  • the light-emitting substrate 200 has a high degree of integration, and can cooperate with a liquid crystal display device to realize high-contrast display.
  • FIG. 4 shows the layout of the first pad 107 and its surrounding traces.
  • the drive circuit 103 shown in FIG. 2 is installed on the first pad 107 and is electrically connected to the drive circuit 103.
  • the first pad 107 is respectively provided with four sub-pads at positions corresponding to the four terminals of the drive circuit 103, respectively. It is the first sub-pad for mounting the address terminal Di, the second sub-pad for mounting the power terminal Pwr, the third sub-pad for mounting the common voltage terminal GND, and the first sub-pad for mounting the output terminal Out. Four sub pads.
  • the first sub-pad is connected to the address terminal Di of the drive circuit 103
  • the second sub-pad is connected to the power terminal Pwr of the drive circuit 103
  • the third sub-pad is connected to the common voltage terminal GND of the drive circuit 103
  • the fourth sub-pad The disk is connected to the output terminal Out of the drive circuit 103 .
  • the first sub-pad is connected to the address selection signal line ADDRL to transmit the address signal on the address selection signal line ADDRL to the address terminal Di.
  • the second sub-pad is connected to the power signal line PwrL to transmit the power voltage signal on the power signal line PwrL to the power terminal Pwr.
  • the third sub-pad is connected to the common voltage signal line GNDL to transmit the common voltage signal on the common voltage signal line GNDL to the common voltage terminal GND.
  • One end of the fourth sub-pad is connected to the cascade wiring 111, so as to output a relay signal within a period of time as an address signal of the next-level drive circuit 103 cascaded with the drive circuit 103;
  • the other end is connected to the wiring 109 to transmit the driving signal to the light emitting unit 104 connected to the driving circuit 103 via the wiring 109 in another period.
  • FIG. 5 is a partial schematic diagram of FIG. 2 , showing two rows of light emitting regions 001 . Within each column of light emitting regions 001 , four second pads 108 are sequentially connected in series and connected to the first pads 107 .
  • the address signal line ADDRL, the power signal line PwrL, the common voltage signal line GNDL, and the feedback signal line FBL are shown in each column of the light-emitting area 001, and the driving voltage signal line VLEDL is not shown, but as mentioned above, each column of the light-emitting area 001 includes a driving voltage signal line VLEDL, which is not shown in the figure.
  • one end of the address signal line ADDRL in the first row of light-emitting area 001 close to the first pad 107 and one end of the address signal line ADDRL in the second column of light-emitting area 001 close to the first pad 107 Basically flush, that is, the address selection signal line ADDRL in the light emitting area 001 of the first column has basically the same length as the address selection signal line ADDRL in the light emitting area 001 of the second column; the power signal line PwrL in the light emitting area 001 of the first column
  • the end close to the first pad 107 is substantially flush with the end of the power signal line PwrL in the light-emitting area 001 of the second column, which is close to the first pad 107, that is, the power signal line PwrL in the light-emitting area 001 of the first column is aligned with the end of the first pad 107.
  • the power signal lines PwrL in the 2-column light-emitting areas 001 have substantially the same length; the end of the common voltage signal line GNDL in the 1st-column light-emitting area 001 close to the first pad 107 is the same as the common voltage in the 2nd-column light-emitting area 001 One end of the signal line GNDL close to the first pad 107 is substantially flush, that is, the common voltage signal line GNDL in the first row of light emitting regions 001 has substantially the same length as the common voltage signal line GNDL in the second row of light emitting regions 001; One end of the feedback signal line FBL close to the first pad 107 in the light-emitting area 001 of the first column is substantially flush with the end of the feedback signal line FBL close to the first pad 107 in the light-emitting area 001 of the second column.
  • the feedback signal line FBL in the column light emitting region 001 has substantially the same length as the feedback signal line FBL in the second column light emitting region 001 .
  • one end of the driving voltage signal line VLEDL close to the first bonding pad 107 in the light emitting region 001 of the first row and the end of the driving voltage signal line VLEDL close to the first bonding pad in the light emitting region 001 of the second row One end of 107 is also substantially flush, that is, the driving voltage signal line VLEDL in the light emitting region 001 of the first column has substantially the same length as the driving voltage signal line VLEDL in the light emitting region 001 of the second column.
  • the same signal lines in each column of light-emitting regions 001 have substantially the same length, so as to maintain the uniformity of each column of light-emitting regions 001 .
  • the same signal line in each column of light emitting regions 001 refers to the signal lines having the same function in each column of light emitting regions 001, for example, the driving voltage signal lines in the first column of light emitting regions 001 to the Nth column of light emitting regions 001 VLEDL is the same signal line.
  • the same signal lines in each column of light-emitting areas 001 can have substantially the same length, so the signal lines in each column of light-emitting areas 001 have approximately the same resistance and voltage drop, so that each column of light-emitting areas 001 There is good brightness uniformity among them.
  • the light emitting substrate 200 may further include a shielding ring GND ESD Ring, which is shown in FIG. 6 .
  • the shielding ring GND ESD Ring surrounds the periphery of the plurality of light emitting regions 102 to provide electrostatic shielding.
  • the electrical signal received by the shielding ring GND ESD Ring is the same as the electrical signal received by the common voltage signal line GNDL.
  • both the shielding ring GND ESD Ring and the common voltage signal line GNDL are connected to the binding electrode of the binding area, and the binding electrode connected to the shielding ring GND ESD Ring has the same definition as the binding electrode connected to the common voltage signal line GNDL, Therefore, the electrical signal received by the shielding ring GND ESD Ring is the same as the electrical signal received by the common voltage signal line GNDL.
  • the shielding ring GND ESD Ring can be located on the same layer as the first conductive part 105 and the second conductive part 106.
  • the shape of the shielding ring GND ESD Ring is not limited to the shape shown in FIG. In an example, the width of the shielding ring GND ESD Ring is greater than or equal to 200um.
  • FIG. 7 shows a light emitting substrate 300
  • FIG. 8 shows the arrangement of terminals of the driving circuit 103 of the light emitting substrate 300
  • the light emitting substrate 300 shown in FIG. 7 has substantially the same configuration as the light emitting substrate 200 shown in FIG. 2 , and thus the same reference numerals are used to designate the same components. Therefore, the detailed actions and functions of the components with the same reference numerals as in FIG. 2 in FIG. 7 can refer to the description of FIG. 2, and will not be repeated here. For the sake of brevity, the different parts will be mainly discussed below.
  • the number of terminals GND is at least one.
  • FIG. 7 shows that the number of output terminals Out is four and the number of common voltage terminals GND is two, but this is only an example.
  • the number of output terminals Out may be more than four or less than four, and the number of common voltage terminals GND may be more than two or less than two.
  • the driving circuit 103 also includes a data terminal Data. As shown in Fig. 7 and Fig.
  • drive circuit 103 comprises two columns of terminals, and the first column terminal comprises power supply terminal Vcc and four output terminals Out1, Out2, Out3, Out4, and the first column terminal is located at the adjacent drive voltage of drive circuit 103 One side of the signal line VLEDL (that is, on the left side of the drive circuit 103); the second column terminal includes an address terminal Di_in, a relay terminal Di_out, a data terminal Data, and two common voltage terminals GND, and the second column terminal is located at the drive circuit 103 One side adjacent to the common voltage signal line GNDL (that is, on the right side of the driving circuit 103 ).
  • the terminals of the drive circuit 103 are arranged in five rows, the address terminal Di_in is located in the fifth row among the terminals, and the relay terminal Di_out is located in the first row among the terminals.
  • the power supply terminal Vcc is located in the third row of the first column of terminals, and the data terminal Data is located in the second row of the second column of terminals, this is only an example, and embodiments of the present disclosure do not limit the power supply terminals.
  • the power supply terminal Vcc may be located in any one of the first row to the fifth row
  • the data terminal Data may be located in any one of the second row to the fourth row.
  • the four output terminals Out1 , Out2 , Out3 , Out4 of the driving circuit 103 are connected to the second terminals of the four light emitting units 104 in one-to-one correspondence to provide driving signals for the light emitting units 104 .
  • the output terminal and the relay terminal of the drive circuit 103 are different terminals.
  • the drive circuit 103 is configured to output a relay signal through the relay terminal Di_out in one period as an address signal of the next-stage drive circuit 103 cascaded with the drive circuit 103, and to output a relay signal through four output terminals in another period.
  • Out1 , Out2 , Out3 , and Out4 respectively provide driving signals to the four light emitting units 104 .
  • the one period and the other period are two separate periods, eg the other period immediately follows the one period.
  • the driving signal may be, for example, a driving current for driving the light emitting unit 104 to emit light. It should be noted that when the driving signal is a driving current, the driving current may flow from the output terminals Out1, Out2, Out3, Out4 to the light emitting unit 104, or may flow from the light emitting unit 104 into the output terminals Out1, Out2, Out3, Out4, the driving current
  • the flow direction of can be determined according to actual requirements, which is not limited in the embodiments of the present disclosure.
  • FIG. 7 only shows four light emitting regions 102, and the four light emitting regions 102 are arranged in a manner of 2 rows*2 columns, this is only a partial screenshot of the light emitting substrate 300, and the light emitting substrate 300 may include any suitable number of light emitting regions. 102. Any appropriate number of light emitting regions 102 may be arranged in M rows and N columns, and M and N may be any positive integer greater than or equal to 1. The embodiments of the present disclosure do not specifically limit the number of light emitting regions 102 included in the light emitting substrate 300 .
  • each row of light-emitting regions 001 includes a driving voltage signal line VLEDL, an address signal line ADDRL, a cascade wiring 111, a power signal line VccL, a common voltage signal line GNDL, and a feedback signal extending along the first direction D1.
  • Lines FBL, their orthographic projections on the substrate 101 do not overlap each other. The functions and arrangement of these signal lines are as described above, and for the sake of brevity, details are not repeated here.
  • each row of light emitting regions 001 also includes a data driving signal line DataL.
  • Each data driving signal line DataL includes a main body portion and a second connection portion 119, and the main body portion of the data driving signal line DataL extends along the first direction D1.
  • each column of light-emitting area 001 one data driving signal line DataL is connected to the data terminals Data of all drive circuits 103 in the column of light-emitting area 001 through the second connection part 119, and the first column terminal of each drive circuit 103 is on the substrate.
  • the orthographic projection on the bottom 101 and the orthographic projection of the second column terminal on the substrate 101 are respectively located on both sides of the orthographic projection of the data driving signal line DataL on the substrate 101, that is, the data driving signal line DataL It is arranged in the area occupied by each driving circuit 103 and does not overlap with the first column terminal and the second column terminal of each driving circuit 103 .
  • the orthographic projection of the data driving signal line DataL on the substrate 101 does not overlap with the orthographic projection of the power signal line VccL in the row of light emitting regions 001 on the substrate 101 .
  • one data driving signal line DataL is configured to provide driving data to the data terminal Data of each driving circuit 103, and multiple different driving data can be loaded on this data driving signal line DataL, and each driving circuit 103
  • the corresponding driving data can be determined according to the address information thereof, and the respective connected light emitting units 104 can be driven according to the corresponding driving data.
  • the driving data is transmitted to the data terminal Data of the driving circuit 103 through the data driving signal line DataL, thus avoiding the use of SPI (Serial Peripheral interface, Serial Peripheral Interface) for data transmission and causing pads,
  • SPI Serial Peripheral interface, Serial Peripheral Interface
  • the problem of too many wires can further simplify the structures of the light-emitting substrate 300 , external circuits and the driving circuit 103 .
  • the distance between the terminals of the driving circuit 103 of the light-emitting substrate 300 is generally determined according to many factors (such as process limit capability, line width requirements between two columns of terminals, electrical design requirements, etc.). Not specifically limited.
  • the distance between the terminals in the first column and the terminals in the second column may be 70-500 um, and the distance between any two adjacent rows of terminals in the five rows of terminals may be 70-500 um.
  • the spacing S1 between the terminals in the first column and the terminals in the second column is 210 ⁇ m, and the spacing S2 between any two adjacent rows of terminals is 90 ⁇ m.
  • the distance between the first output terminal Out1 and the relay terminal Di_out, the distance between the second output terminal Out2 and the data terminal Data, the distance between the power supply terminal Vcc and the common voltage terminal GND, the distance between the third output terminal The distance between Out3 and the common voltage terminal GND, and the distance between the fourth output terminal Out4 and the address terminal Di_in are both S1, which is 210 ⁇ m; the distance between the first output terminal Out1 and the second output terminal Out2, the second The distance between the output terminal Out2 and the power terminal Vcc, the distance between the power terminal Vcc and the third output terminal Out3, the distance between the third output terminal Out3 and the fourth output terminal Out4, the distance between the relay terminal Di_out and the data terminal Data
  • the distance between, the distance between the data terminal Data and the common voltage terminal GND, the distance between the common voltage terminal GND and the adjacent common voltage terminal GND, and the distance between the common voltage terminal GND and the address terminal Di_in are all S2, is 90 ⁇ m.
  • the ten terminals of the drive circuit 103 occupy substantially the same area, and have substantially the same length and width.
  • the width S3 of each terminal along the second direction D2 is 110 ⁇ m, and the length S4 of each terminal along the first direction D1 is 100 ⁇ m.
  • the spacing S5 between the fifth row terminal and the first side of the driving circuit 103 is 35 ⁇ m, that is, the distance between the fourth output terminal Out4 and the address terminal Di_in and the lower edge of the driving circuit 103 S5 is 35 ⁇ m;
  • the spacing S5 between the first row of terminals and the second side of the drive circuit 103 is 35 ⁇ m, that is, the first output terminal Out1 and the relay terminal Di_out and the drive circuit 103
  • the spacing S5 between the upper edges of each is 35 ⁇ m.
  • the spacing S6 between the first column terminal and the third side of the driving circuit 103 is 25 ⁇ m
  • the second column terminal and the fourth side of the driving circuit 103 ie, the right side of the driving circuit 103.
  • the spacing S6 between the edges is 25 ⁇ m. Therefore, it can be known that the length L of the driving circuit 103 along the first direction D1 is 930 ⁇ m, and the width W of the driving circuit 103 along the second direction D2 is 480 ⁇ m.
  • the distance between the power signal line VccL and the first column terminal and the second column terminal can be 10-100um respectively, and the distance between the data driving signal line DataL and the first column terminal and the second column terminal The distance between them can be 10-100um respectively.
  • the width of the power signal line VccL and the data driving signal line DataL between the first column terminal and the second column terminal along the second direction D2 is greater than or equal to 40 um.
  • a driving circuit 103 shown in FIG. 7 includes four output terminals, so one driving circuit 103 can be connected to four light emitting units 104 at the same time, thereby greatly reducing the usage of the driving circuit 103 and reducing the cost of the light emitting substrate 300 . Not only that, because the amount of the driving circuit 103 is reduced, it can also reduce the manufacturing difficulty of the light-emitting substrate 300 , reduce the influence of the binding yield of the driving circuit 103 on the yield of the light-emitting substrate 300 , and further improve the yield of the light-emitting substrate 300 .
  • the terminals of the driving circuit 103 adopt the above-mentioned layout method, so that in each column of the light-emitting area 001, the driving voltage signal line VLEDL of the first conductive part 105, the address selection signal line ADDRL, the cascade wiring 111, the power supply Orthographic projections of the signal line VccL, the data driving signal line DataL, the common voltage signal line GNDL, and the feedback signal line FBL on the substrate 101 do not overlap each other.
  • the orthographic projections of the driving voltage signal line VLEDL, the common voltage signal line GNDL, and the feedback signal line FBL of the first conductive part 105 on the substrate 101 are consistent with the first pad 107 and the second pad 107 of the second conductive part 106.
  • the orthographic projections of the pads 108 on the substrate 101 also do not overlap.
  • the short circuit or open circuit caused by overlapping of the first conductive portion 105 and the second conductive portion 106 can be completely avoided, thereby improving the light emitting performance of the light emitting substrate 300 and improving the light emitting stability of the light emitting substrate 300 .
  • the driving circuit 103 starts to work, firstly, the power supply terminal Vcc of each driving circuit 103 in each row of light-emitting areas 001 is provided with a power supply voltage through the power signal line VccL to complete initialization, so that the driving circuit 103 is in a power-on state.
  • the write address operation is performed in the first period, that is, the ADDRL signal line inputs the address signal to the first-level driving circuit 103 through the address terminal Di_in, so as to write the address.
  • the first-level driving circuit 103 outputs a relay signal through the relay terminal Di_out, and the relay signal is transmitted to the address terminal Di_in of the second-level driving circuit 103 through the cascaded wiring 111, so as to serve as the address terminal Di_in of the second-level driving circuit 103. address signal.
  • each data driving signal line DataL transmits the driving data signal to the data terminal Data of each driving circuit 103 for initialization configuration.
  • the driving voltage is supplied to the driving voltage signal line VLEDL, and at this time, the driving voltage transmitted on the driving voltage signal line VLEDL becomes a high level.
  • each driving circuit 103 generates a driving control signal corresponding to each output terminal according to the received driving data, and the driving control signal is used to control the current flowing through the corresponding output terminal.
  • the driving circuit 103 can control the current flowing through the light emitting units 104 to achieve the purpose of driving each connected light emitting unit 104 according to the driving circuit 103 .
  • the system is shut down, that is, the driving circuit 103 is powered off, and the driving voltage provided by the driving voltage signal line VLEDL becomes low level, and the light emitting unit 104 stops emitting light.
  • Each drive circuit 103 includes four output terminals Out1, Out2, Out3, Out4.
  • the drive circuit 103 also includes a logic control module CTR and a control module CLM (not shown in the figure), the logic control module CTR includes four modulation modules, namely the first modulation module PWMM1, the second modulation module PWMM2, the third modulation module PWMM3, a fourth modulation module PWMM4.
  • the first output terminal Out1 to the fourth output terminal Out4 are connected to the first modulation module PWMM1 to the fourth modulation module PWMM4 in a one-to-one correspondence.
  • the control module CLM is used to generate the first drive control signal, the second drive control signal, the third drive control signal, and the fourth drive control signal according to the drive data provided by the data drive signal line DataL, and transmit them to the first modulation module PWMM1 respectively , the second modulation module PWMM2, the third modulation module PWMM3 and the fourth modulation module PWMM4.
  • the first modulation module PWMM1 is electrically connected to the first output terminal Out1, and can be turned on or off under the control of the first drive control signal, so that the first output terminal Out1 is connected to the common voltage signal line GNDL is turned on or off.
  • the first modulation module PWMM1 When the first modulation module PWMM1 is turned on, the common voltage signal line GNDL, the first output terminal Out1, the light emitting unit 104 electrically connected to the first output terminal Out1 and the driving voltage signal line VLEDL form a signal loop, and the light emitting unit 104 works; When the first modulation module PWMM1 is turned off, the signal loop is disconnected, and the light emitting unit 104 does not work. In this way, the first modulation module PWMM1 can modulate the current flowing through the light emitting unit 104 under the control of the first driving control signal, so that the current flowing through the light emitting unit 104 presents a pulse width modulation signal.
  • the first modulation module PWMM1 can modulate factors such as the duty cycle of the pulse width modulation signal flowing through the light emitting unit 104 according to the first driving control signal, and then control the working state of the light emitting unit 104 .
  • the light-emitting unit 104 includes an LED
  • the duty ratio of the pulse width modulation signal by increasing the duty ratio of the pulse width modulation signal, the total light-emitting time of the LED in a display frame can be increased, thereby increasing the total light-emitting brightness of the LED in the display frame, so that the light-emitting substrate 300 can The brightness of this area increases; on the contrary, by reducing the duty ratio of the pulse width modulation signal, the total light-emitting time of the LED in a display frame can be reduced, thereby reducing the total light-emitting brightness of the LED in the display frame, so that the light-emitting substrate 300 The brightness in this area is reduced, so that the brightness of the light emitting unit 104 electrically connected to the first output terminal Out1 is control
  • the brightness of the light-emitting units 104 that are electrically connected to the second output terminal Out2, the third output terminal Out3, and the fourth output terminal Out4 can be respectively controlled, thereby realizing the brightness of each light-emitting unit 104 in the light-emitting substrate 300. Brightness control.
  • FIG. 9 shows a partially enlarged view of a row of light emitting regions 001 of the light emitting substrate 300 in FIG. 7
  • FIG. 10 shows a further enlarged view within the dotted line frame in FIG. 9
  • the driving circuit 103 shown in FIG. 7 is mounted on the first pad 107 and is electrically connected to the driving circuit 103
  • the second pad 108 includes two sub-pads, for example, the two sub-pads are electrically connected to the anode and the cathode of the light emitting unit 104 respectively.
  • the first pad 107 is respectively provided with ten sub-pads at positions corresponding to the ten terminals of the drive circuit 103, which are respectively used to install the four output terminals Out1-Out4 and electrically connected to the four output terminals Out1-Out4.
  • One to the fourth sub-pad, the fifth sub-pad for installing the power terminal Vcc and electrically connected to the power terminal Vcc, the fifth sub-pad for installing two common voltage terminals GND and electrically connected to the two common voltage terminals GND respectively Sixth and seventh sub-pads, an eighth sub-pad for mounting the address terminal Di_in and electrically connected to the address terminal Di_in, a ninth sub-pad for mounting the relay terminal Di_out and electrically connecting with the relay terminal Di_out, and The tenth sub-pad is used for mounting the data terminal Data and is electrically connected to the data terminal Data.
  • the fourth sub-pad is connected to the two sub-pads of the second pad 108 via wires, so as to transmit the driving signal to the light emitting unit 104 electrically connected to the fourth terminal Out4.
  • the fifth sub-pad is connected to the power signal line VccL to transmit the power voltage signal on the power signal line VccL to the power terminal Vcc.
  • the sixth and seventh subpads are connected to the common voltage signal line GNDL to transmit the common voltage signal on the common voltage signal line GNDL to the two common voltage terminals GND.
  • the eighth subpad is connected to the address selection signal line ADDRL to transmit the address signal on the address selection signal line ADDRL to the address terminal Di_in.
  • the ninth sub-pad is connected to the cascaded wiring, so as to output a relay signal within a period of time as an address signal of the next-stage driving circuit 103 cascaded with the driving circuit 103 .
  • the tenth sub-pad is connected to the data driving signal line DataL, so as to transmit the data driving signal on the data driving signal line DataL to the data terminal Data.
  • the distance between each driving voltage signal line VLEDL and other adjacent signal lines needs to be greater than or equal to 0.2 mm. This is because the voltage on the driving voltage signal line VLEDL is relatively high (for example, about 10-50V), while the voltages of other signal lines adjacent to the driving voltage signal line VLEDL are usually relatively low. If the distance is too small, it is easy to cause line breakdown. and other bad phenomena.
  • the spacing between other signal lines on the light-emitting substrate can be designed according to technological limits, which is not specifically limited in the embodiments of the present disclosure. For example, if the process limit is 20um, the spacing between other signal lines on the light emitting substrate may be 20um.
  • the material of the first conductive part 105 and the second conductive part 106 may be any suitable conductive material, which is not specifically limited in this embodiment of the present disclosure.
  • the material of the first conductive part 105 and the second conductive part 106 includes copper.
  • the first conductive part 105 and the second conductive part 106 may be a stack of Cu and CuNi. The side of the stack close to the substrate 101 is a Cu layer, the thickness of which may be 2um, for example, and Cu is a preferred material for electrical signal transmission channels.
  • the side of the stack away from the substrate 101 is a CuNi layer, the thickness of which may be 0.6 um, for example, and the CuNi layer may be used to protect the Cu layer and prevent oxidation of the surface of the Cu layer with low resistivity being exposed.
  • the first conductive part 105 and the second conductive part 106 are, for example, a stack of MoNb/Cu/MoNb, and the side of the stack close to the substrate 101 is a MoNb layer with a thickness of about Left and right, mainly used to improve the adhesion between the stack and the substrate 101; the middle layer of the stack is a Cu layer, and Cu is the preferred material for the electrical signal transmission channel; the side away from the substrate 101 in the stack is a MoNb layer, The thickness is about On the left and right, the MoNb layer can be used to protect the middle Cu layer and prevent the surface of the middle Cu layer with low resistivity from being exposed and oxidized.
  • the light-emitting substrate described in any of the above embodiments may also include a plurality of flexible circuit boards 110.
  • FIG. 11A shows the connection relationship between the multiple flexible circuit boards 110 and signal lines.
  • FIG. 11B shows a part of the region I in FIG. The enlarged view shows the connection relationship between a flexible circuit board 110 and signal lines.
  • the flexible circuit board 110 is disposed in the binding area on the light-emitting substrate, and is electrically connected to each signal line of the first conductive part 105 through the binding electrode 120 of the binding area.
  • FIG. 11A shows the connection relationship between the multiple flexible circuit boards 110 and signal lines.
  • FIG. 11B shows a part of the region I in FIG.
  • the enlarged view shows the connection relationship between a flexible circuit board 110 and signal lines.
  • the flexible circuit board 110 is disposed in the binding area on the light-emitting substrate, and is electrically connected to each signal line of the first conductive part 105 through the binding electrode 120 of the binding area. In the example of FIG.
  • the flexible circuit board 110 and the driving voltage signal line VLEDL, the address selection signal line ADDRL, the power signal line PwrL, the common voltage signal line GNDL, the feedback signal line FBL, and the shielding ring GND of the first conductive part 105
  • the ESD Ring is electrically connected, and the flexible circuit board 110 provides the same signal for the common voltage signal line GNDL and the shielding ring GND ESD Ring.
  • the flexible circuit board 110 and the driving voltage signal line VLEDL, the address signal line ADDRL, the power signal line VccL, the driving data signal line DataL, the common voltage signal line GNDL, and the feedback signal line of the first conductive part 105 The FBL and the shielding ring GND ESD Ring are electrically connected, and the flexible circuit board 110 provides the same signal for the common voltage signal line GNDL and the shielding ring GND ESD Ring.
  • Figure 11B only shows the last row of light-emitting areas, that is, the M-th row of light-emitting areas, which shows four columns of light-emitting areas, the k-th column of light-emitting areas, the k+1th column of light-emitting areas, the k+2th column of light-emitting areas, the k+3 columns of light-emitting regions, and the areas occupied by each column of light-emitting regions are shown by dotted boxes.
  • the four columns of light emitting areas may be any adjacent four columns of light emitting areas in the N columns of light emitting areas.
  • Each row of light emitting regions includes a light emitting unit 104 .
  • Each signal line (for the sake of brevity, only the driving voltage signal line VLEDL and the common voltage signal line GNDL are marked in the figure) includes a straight line portion 116 extending along the first direction D1 and a bent portion 117, and the bent portion 117 is located at In the fan-out area 114 , each signal line is connected to the binding electrode 120 through its bent portion 117 , and the binding electrode 120 is connected to the flexible circuit board 110 , so as to realize the electrical connection between each signal line and the flexible circuit board 110 .
  • the width of the bent portion 117 of each signal line along the second direction D2 is smaller than the width of two adjacent rows of light emitting regions along the second direction D2. Taking the k-th column light-emitting area in FIG.
  • the width T1 of the bent portion 117 of the driving voltage signal line VLEDL along the second direction D2 is smaller than the light-emitting areas of two adjacent columns (for example, k-th column and k+1-th column). Width T2 along the second direction D2.
  • the included angle between the straight portion 116 and the bent portion 117 of each signal line is 80° ⁇ 100°. In one example, the included angle between the straight portion 116 and the bent portion 117 of each signal line is 90°.
  • each flexible circuit board corresponds to 5-15 columns of light-emitting areas, that is, each flexible circuit board is electrically connected to signal lines in 5-15 columns of light-emitting areas.
  • each flexible circuit board corresponds to 3 to 8 columns of light emitting regions 001, that is, each flexible circuit board 110 is connected to the signal wires in 3 to 8 columns of light emitting regions 001. connect.
  • each flexible circuit board 110 is electrically connected to the signal lines in the 4 columns of light-emitting areas 001 .
  • each signal line can basically extend to the bonding area in a straight line and be connected to the flexible circuit board 110 .
  • the fan-out region 114 of the light-emitting substrate provided by the embodiment of the present disclosure has a narrower width, so that the width of the lower frame of the light-emitting substrate can be reduced, which is beneficial to realize a narrow frame.
  • FIG. 12 shows several optional arrangements of each light emitting unit 104 as an example.
  • Each light emitting unit 104 includes a plurality of light emitting elements connected to each other, the first end of the plurality of light emitting elements is electrically connected to the driving voltage signal line VLEDL, and the second end of the plurality of light emitting elements is electrically connected to the output terminal Out of the driving circuit 103. connect.
  • Fig. 12 (a) shows that each light-emitting unit 104 includes four light-emitting elements connected in series with each other, and the four light-emitting elements are arranged in 1 column * 4 rows; Fig.
  • each light-emitting unit 104 includes each other Four light-emitting elements connected in series, the four light-emitting elements are arranged in 2 columns*2 rows; Column * 3 rows.
  • the multiple light emitting elements in each light emitting unit 104 are not limited to the above arrangement, and they can be arranged in any suitable manner.
  • multiple light emitting elements in each light emitting unit 104 can be connected in parallel with each other.
  • multiple light emitting elements in each light emitting unit 104 may be combined in series and in parallel. The number of light emitting elements included in each light emitting unit 104 may be determined according to actual requirements, for example, according to the size of the light emitting substrate and the required brightness.
  • Each light emitting element can be an organic light emitting diode or an inorganic light emitting diode.
  • each light emitting element may be a submillimeter light emitting diode (Mini LED) or a micro light emitting diode (Mirco LED).
  • the size of sub-millimeter LEDs is, for example, in the range of 100 microns to 500 microns; the size of micro LEDs is, for example, smaller than 100 microns.
  • Embodiments of the present disclosure do not limit the type and size of the light emitting elements of the light emitting unit 104 .
  • High-Dynamic Range (HDR) display can be realized by using submillimeter light-emitting diodes or miniature light-emitting diodes as the light-emitting elements of the light-emitting units 104, combined with independently controllable brightness of each light-emitting unit 104.
  • the contrast ratio of the display device can be significantly improved.
  • the light-emitting substrate may further include a buffer layer 112 and a first insulating layer 113 .
  • the buffer layer 112 is located between the layer where the first conductive portion 105 and the second conductive portion 106 are located and the substrate 101, and the first insulating layer 113 is located at a layer where the first conductive portion 105 and the second conductive portion 106 are located away from the substrate 101. side.
  • the buffer layer 112 can be used to reduce the stress on the substrate 101 during the preparation of the first conductive portion 105 and the second conductive portion 106, so as to avoid bending deformation of the substrate 101; The impurity has adverse effects on the conductivity of the first conductive portion 105 and the second conductive portion 106 .
  • the buffer layer 112 can be any suitable material, for example, it can be SiN.
  • the first insulating layer 113 can be used to protect the first conductive portion 105 and the second conductive portion 106 from being oxidized and corroded by water, oxygen, etc. in the environment.
  • the material of the first insulating layer 113 may be an organic material, an inorganic material, or a combination of an organic material and an inorganic material, and the first insulating layer 113 may be a single film layer, or may include multiple film layers.
  • the substrate 101 may be any suitable substrate such as a plastic substrate, a silicon substrate, a ceramic substrate, a glass substrate, a quartz substrate, and the embodiment of the present disclosure does not limit the material of the substrate 101 .
  • the light-emitting substrate may further include a second insulating layer 115 located on a side of the first insulating layer 113 away from the substrate 101 .
  • the material of the second insulating layer 115 may be an organic material, an inorganic material, or a combination of an organic material and an inorganic material, and the second insulating layer 115 may be a single film layer, or may include multiple film layers.
  • FIG. 14 shows a block diagram of a backlight 400 including the light-emitting substrate described in any one of the preceding embodiments.
  • the backlight source 400 can be used as a backlight source in a display device to provide a display light source for a display panel in the display device.
  • the backlight source 400 may also be used in any other device that requires a light source, and the embodiments of the present disclosure do not specifically limit the use of the backlight source 400 .
  • the backlight 400 can have basically the same technical effect as the light-emitting substrate described in the previous embodiments, for the sake of brevity, the technical effect of the backlight 400 will not be described here again.
  • FIG. 15 shows a block diagram of a display device 500 including the light-emitting substrate described in any one of the preceding embodiments.
  • the display device 500 may be a liquid crystal display device, which includes a liquid crystal panel and a backlight arranged on the non-display side of the liquid crystal panel, and the backlight includes the light-emitting substrate described in any of the previous embodiments, for example Can be used to implement HDR dimming for display operation.
  • the liquid crystal display device can have more uniform backlight brightness and better display contrast.
  • the display device 500 can be any suitable display device, including but not limited to mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, navigators, e-books, and any other products or components with display functions.
  • the display device 500 can basically have the same technical effect as the light-emitting substrate described in the previous embodiments, for the sake of brevity, the technical effect of the display device 500 will not be described here again.
  • FIG. 16 shows a flowchart of the method 600 , and the method 600 is applicable to the light-emitting substrate described in any one of the foregoing embodiments.
  • method 600 may comprise the following steps:
  • S602 forming a conductive layer on the substrate 101 , and simultaneously forming the first conductive portion 105 and the second conductive portion 106 including a plurality of pads 107 and 108 by patterning the conductive layer.
  • each light emitting region 102 includes a driving circuit 103 and at least one light emitting device connected to the driving circuit 103 Unit 104.
  • the first conductive part 105 is configured to transmit electrical signals to the driving circuit 103 and at least one light emitting unit 104 in each light emitting region 102 .
  • the substrate 101 may be any suitable substrate such as a plastic substrate, a silicon substrate, a ceramic substrate, a glass substrate, a quartz substrate, and the embodiment of the present disclosure does not limit the material of the substrate 101 .
  • a buffer layer 112 is formed on the substrate 101 by, for example, a magnetron sputtering method.
  • the buffer layer 112 can be used to reduce the stress on the substrate 101 during the subsequent preparation of the first conductive part 105 and the second conductive part 106, so as to avoid bending deformation of the substrate 101; the buffer layer 112 can also prevent the substrate 101 from The impurity in the impurity has an adverse effect on the conductivity of the subsequently formed first conductive portion 105 and second conductive portion 106 .
  • the buffer layer 112 can be any suitable material, for example, it can be SiN.
  • the first conductive part 105 may include the driving voltage signal line VLEDL, the address signal line ADDRL, the cascade wiring 111, the power signal line VccL, the data driving signal line DataL, the common voltage signal line GNDL, and the feedback signal line FBL as described above. And optional shielding ring GND ESD Ring.
  • the second conductive portion 106 includes a first pad 107 and a second pad 108 , the first pad 107 is used for mounting the driving circuit 103 , and the second pad 108 is used for mounting the light emitting unit 104 . Since the thickness of a single magnetron sputtering generally does not exceed 1 ⁇ m, multiple sputtering is usually required to form a conductive layer exceeding 1 ⁇ m. .
  • the formation process of the first conductive part 105 and the second conductive part 106 can be described as follows: firstly, a Cu layer with a thickness of 2um, for example, is formed on the buffer layer 112 to transmit various electrical signals; A CuNi layer with a thickness of, for example, 0.6 um is formed on the layer, and the CuNi layer can be used to protect the Cu layer and prevent the surface of the Cu layer with low resistivity from being exposed and oxidized.
  • the formation process of the first conductive portion 105 and the second conductive portion 106 can be described as follows: firstly, a layer with a thickness of about MoNb layer, the MoNb layer is used to improve the adhesion between the film layer and the substrate 101; then a Cu layer is formed on the MoNb layer to transmit various electrical signals; finally, a thickness of about The MoNb layer is used to protect the middle Cu layer and prevent the surface of the middle Cu layer with low resistivity from being exposed and oxidized.
  • MoNiTi can be used to form a seed layer first, so as to increase the nucleation density of the metal crystal grains in the subsequent electroplating process, and then through electroplating.
  • a Cu layer with low resistivity is used to make an anti-oxidation layer, and the material can be MoNiTi.
  • the first conductive part 105 and the second conductive part 106 can be formed after the conductive layer is cleaned, coated, baked, photolithography, developed, hard baked, etched, stripped and other processes.
  • the preparation of the first conductive part 105 and the second conductive part 106 on the same layer only needs to use two masks, compared with the related art that requires at least three masks to form conductive structures on different layers, which can reduce the The number of masks required is reduced, the process is simplified, and the production cost is reduced.
  • a first insulating layer 113 is formed on the side of the layer where the first conductive portion 105 and the second conductive portion 106 are located away from the substrate 101 by magnetron sputtering.
  • the first insulating layer 113 can be used to protect the first conductive portion 105 and the second conductive portion 106 from being oxidized and corroded by water, oxygen, etc. in the environment.
  • the material of the first insulating layer 113 may be an organic material, an inorganic material, or a combination of an organic material and an inorganic material, and the first insulating layer 113 may be a single film layer, or may include multiple film layers.
  • a second insulating film layer may also be coated on the side of the first insulating layer 113 away from the substrate 101, and the second insulating film layer may be cured, exposed, developed, etched, etc. to form the second insulating film layer.
  • Two insulating layers 115 The material of the second insulating layer 115 may be an organic material, an inorganic material, or a combination of an organic material and an inorganic material, and the second insulating layer 115 may be a single film layer, or may include multiple film layers.
  • the second insulating layer 115 and the first insulating layer 113 are etched to form a plurality of via holes.
  • the light-emitting substrate is cut into a specified shape, and the driving circuit 103 and the light-emitting unit 104 are respectively electrically connected to the first pad 107 and the second pad 108 of the second conductive part 103 through the above-mentioned multiple via holes, so as to drive the
  • the circuit 103 and the light emitting unit 104 are mounted on corresponding pads.
  • Each signal line of the first conductive part 105 is connected to the flexible circuit board 110 at the binding area, so as to realize the electrical connection between the driving circuit 103 and the flexible circuit board 110 , and finally obtain the required light-emitting substrate.

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Abstract

本公开提供了一种发光基板及其制造方法、背光源以及显示装置。该发光基板包括：衬底，包括阵列布置的多个发光区域，所述多个发光区域中的每一个包括驱动电路和与所述驱动电路连接的至少一个发光单元；第一导电部，位于所述衬底上且与每个发光区域内的所述驱动电路和所述至少一个发光单元连接；以及第二导电部，位于所述衬底上且包括多个焊盘。所述第一导电部和所述第二导电部位于同一层。

Description

发光基板及其制造方法、背光源、显示装置 技术领域
本公开涉及光学技术领域，尤其涉及一种发光基板及其制造方法、包括该发光基板的背光源以及包括该发光基板的显示装置。
背景技术
随着显示技术的不断发展，用户对显示装置的对比度、亮度均匀性以及稳定性提出了越来越高的要求。显示装置通常分为液晶显示装置和有机发光二极管显示装置两大类，液晶显示装置由于具有轻薄化、抗震性好、视角广、对比度高等优点而得到广泛应用。液晶显示装置通常包括显示面板和背光源，背光源通常设置在显示面板的非显示侧以为显示面板的显示操作提供光源。液晶显示装置的对比度、亮度均匀性以及稳定性等特性与背光源的结构和性能相关联。
发明内容
根据本公开的一方面，提供了一种发光基板，包括：衬底，包括阵列布置的多个发光区域，所述多个发光区域中的每一个包括驱动电路和与所述驱动电路连接的至少一个发光单元；第一导电部，位于所述衬底上且与每个发光区域内的所述驱动电路和所述至少一个发光单元连接；以及第二导电部，位于所述衬底上且包括多个焊盘。所述第一导电部和所述第二导电部位于同一层。
在一些实施例中，所述多个发光区域沿第一方向布置成M行且沿与所述第一方向交叉的第二方向布置成N列，M和N均为大于等于1的正整数。所述第一导电部包括沿所述第一方向延伸的N条驱动电压信号线和N条公共电压信号线，每列发光区域包括一条驱动电压信号线和一条公共电压信号线，在每列发光区域内，所述驱动电压信号线与该列发光区域内的每个发光单元的第一端连接，所述公共电压信号线与该列发光区域内的每个驱动电路连接；在每列发光区域内，所述驱动电压信号线、所述发光单元、所述驱动电路、以及所述公共电压信号线沿着所述第二方向依次排列。
在一些实施例中，所述驱动电压信号线、所述发光单元、所述驱 动电路、以及所述公共电压信号线在所述衬底上的正投影彼此不交叠。
在一些实施例中，每个驱动电路包括阵列布置的多个端子，所述多个端子沿所述第二方向排列成至少两列。所述多个端子包括至少一个输出端子和至少一个公共电压端子，所述至少一个输出端子和所述至少一个公共电压端子位于所述多个端子的不同列中。在每列发光区域内，每个驱动电路的所述至少一个输出端子与和该驱动电路连接的所述至少一个发光单元的第二端一一对应连接，每个驱动电路的所述至少一个公共电压端子与该列发光区域内的所述公共电压信号线连接。
在一些实施例中，所述多个端子还包括地址端子、中继端子以及电源端子，每列发光区域内的各个驱动电路依次级联，第i级驱动电路的所述地址端子位于所述第i级驱动电路的靠近第i-1级驱动电路的一侧，第i级驱动电路的所述中继端子位于所述第i级驱动电路的靠近第i+1级驱动电路的一侧，1＜i＜M且i为正整数，所述地址端子配置为接收地址信号，所述中继端子配置为输出中继信号，所述电源端子配置为接收电源电压信号。
在一些实施例中，所述第一导电部的延伸方向平行于所述驱动电路的级联方向。
在一些实施例中，所述驱动电路的多个端子沿所述第二方向布置成第一列和第二列，在每列发光区域内，所述驱动电路的第一列端子位于所述驱动电路的邻近所述驱动电压信号线的一侧，所述驱动电路的第二列端子位于所述驱动电路的邻近所述公共电压信号线的一侧。
在一些实施例中，所述第一导电部还包括N条电源信号线，每列发光区域包括一条电源信号线，每条电源信号线包括主体部分和第一连接部，所述电源信号线的主体部分沿所述第一方向延伸。在每列发光区域内，所述电源信号线通过所述第一连接部与该列发光区域内的每个驱动电路的所述电源端子连接，并且所述第一列端子在所述衬底上的正投影与所述第二列端子在所述衬底上的正投影分别位于所述电源信号线在所述衬底上的正投影的两侧。
在一些实施例中，所述第一导电部还包括沿所述第一方向延伸的N条选址信号线，每列发光区域包括一条选址信号线。在每列发光区域内，所述选址信号线与第一级驱动电路的所述地址端子连接。
在一些实施例中，所述第一导电部还包括沿所述第一方向延伸的级联走线，所述级联走线位于每列发光区域内的相邻两个级联的驱动电路之间，并且第i级驱动电路的所述中继端子经由所述级联走线与第i+1级驱动电路的所述地址端子连接。
在一些实施例中，所述第一导电部还包括沿所述第一方向延伸的N条反馈信号线，每列发光区域包括一条反馈信号线。在每列发光区域内，所述反馈信号线与最后一级驱动电路的所述中继端子连接，并且所述反馈信号线至少部分地位于该列发光区域内的所述公共电压信号线远离所述驱动电路的一侧。
在一些实施例中，所述驱动电压信号线、所述选址信号线、所述级联走线、所述电源信号线、所述公共电压信号线、以及所述反馈信号线在所述衬底上的正投影彼此不交叠。
在一些实施例中，所述驱动电路的所述多个端子包括所述地址端子、所述电源端子、所述公共电压端子、以及所述输出端子。所述第一列端子包括所述输出端子和所述地址端子，所述第二列端子包括所述公共电压端子和所述电源端子。
在一些实施例中，所述驱动电路的所述输出端子和所述中继端子为同一个端子，所述驱动电路配置为，在第一时段内通过所述输出端子输出中继信号以作为与该驱动电路级联的下一级驱动电路的所述地址信号，在第二时段内通过所述输出端子向与该驱动电路连接的所述至少一个发光单元提供驱动信号。
在一些实施例中，所述驱动电路的所述多个端子还包括数据端子，所述数据端子与所述电源端子位于所述多个端子的不同列中。
在一些实施例中，所述驱动电路的输出端子的数量为多个且所述公共电压端子的数量为至少一个。所述第一列端子包括所述电源端子和所述多个输出端子，所述第二列端子包括所述地址端子、所述中继端子、所述数据端子以及所述至少一个公共电压端子。
在一些实施例中，所述第一导电部还包括N条数据驱动信号线，每列发光区域包括一条数据驱动信号线，每条数据驱动信号线包括主体部分和第二连接部，所述数据驱动信号线的主体部分沿所述第一方向延伸。在每列发光区域内，所述数据驱动信号线通过所述第二连接部与该列发光区域内的每个驱动电路的所述数据端子连接，并且所述 第一列端子在所述衬底上的正投影与所述第二列端子在所述衬底上的正投影分别位于所述数据驱动信号线在所述衬底上的正投影的两侧，并且所述数据驱动信号线在所述衬底上的正投影与所述电源信号线在所述衬底上的正投影不交叠。
在一些实施例中，所述驱动电路的所述多个输出端子与和该驱动电路连接的多个发光单元的第二端一一对应连接。所述驱动电路配置为，在第一时段内通过所述中继端子输出中继信号以作为与该驱动电路级联的下一级驱动电路的所述地址信号，在第二时段内通过所述多个输出端子分别向所述多个发光单元提供驱动信号。
在一些实施例中，所述驱动电压信号线和相邻的其他信号线之间的间距大于等于0.2mm。
在一些实施例中，所述发光基板还包括多个柔性电路板和扇出区。所述第一导电部的各条信号线均包括直线部分和弯折部分，所述各条信号线的弯折部分位于所述扇出区内，并且所述各条信号线通过其弯折部分与所述多个柔性电路板连接，并且，每条信号线的弯折部分沿所述第二方向的宽度小于相邻两列发光区域沿所述第二方向的宽度。
在一些实施例中，每条信号线的所述直线部分和所述弯折部分之间的夹角为80°～100°。
在一些实施例中，所述第一导电部和所述第二导电部的材料包括铜。
在一些实施例中，每个发光单元包括彼此连接的多个发光元件，所述多个发光元件中的每一个包括次毫米发光二极管或微型发光二极管。
在一些实施例中，所述发光基板还包括屏蔽环，所述屏蔽环围绕在所述多个发光区域的外围，并且所述屏蔽环接收的电信号与所述公共电压信号线接收的电信号相同。
在一些实施例中，所述发光基板还包括缓冲层和绝缘层。所述缓冲层位于所述第一导电部和所述第二导电部所在的层与所述衬底之间，所述绝缘层位于所述第一导电部和所述第二导电部所在的层远离所述衬底的一侧。
根据本公开的另一方面，提供了一种背光源，该背光源包括在前面任一个实施例中描述的发光基板。
根据本公开的又一方面，提供了一种显示装置，该显示装置包括在前面任一个实施例中描述的发光基板。
根据本公开的再一方面，提供了一种制造发光基板的方法，该方法包括以下步骤：提供衬底；在所述衬底上形成导电层，通过对所述导电层进行构图以同时形成第一导电部和包括多个焊盘的第二导电部；以及在所述衬底上安装多个驱动电路和多个发光单元以形成阵列布置的多个发光区域，所述多个发光区域中的每一个包括驱动电路和与该驱动电路连接的至少一个发光单元。所述第一导电部与每个发光区域内的所述驱动电路和所述至少一个发光单元连接。
附图说明
为了更清楚地描述本公开实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了根据本公开实施例提供的发光基板的布置示意图；
图2示出了根据本公开实施例提供的发光基板的布线示意图；
图3示出了图2中的发光基板的驱动电路的端子的布置示意图；
图4示出了图2中的发光基板的第一焊盘的布置示意图；
图5示出了图2的局部放大示意图；
图6示出了根据本公开实施例提供的发光基板的布线示意图；
图7示出了根据本公开另一实施例提供的发光基板的布线示意图；
图8示出了图7中的发光基板的第一焊盘的布置示意图；
图9示出了图7的局部放大示意图；
图10示出了图9的局部放大示意图；
图11A示出了根据本公开实施例提供的发光基板的柔性电路板的布置示意图；
图11B示出了图11A中的区域I的局部放大图；
图12示出了根据本公开实施例提供的发光基板的发光单元的布置示意图；
图13示出了根据本公开实施例提供的发光基板的结构示意图；
图14示出了根据本公开又一实施例提供的背光源的框图；
图15示出了根据本公开再一实施例提供的显示装置的框图；以及
图16示出了根据本公开再一实施例提供的发光基板的制造方法的流程图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开的实施例提供了一种发光基板，图1示出了该发光基板100的布置示意图。如图1所示，该发光基板100包括衬底101、布置在衬底101上的第一导电部105以及第二导电部106。衬底101包括阵列布置的多个发光区域102，每个发光区域102包括驱动电路103和与该驱动电路103连接的至少一个发光单元104。第一导电部105与每个发光区域102内的驱动电路103和发光单元104连接，例如第一导电部105可以包括多条信号走线。图1的左侧虚线框示出了一个发光区域102的放大示意图，如该放大示意图所示，第二导电部106包括多个焊盘，该多个焊盘例如包括多个第一焊盘107和多个第二焊盘108，驱动电路103安装在第一焊盘107上，发光单元104安装在第二焊盘108上。第一导电部105和第二导电部106位于同一层。需要说明的是，在本申请中，术语“A与B位于同一层”是指A与B位于同一膜层的表面之上且均与该表面直接接触。在一些实施例中，A与B由同一膜层通过采用同一工艺形成。在一些实施例中，A与B位于同一膜层的表面之上且均与该表面直接接触，并且A与B具有基本相同的高度或厚度。
可以理解的是，图1仅用于示意性示出驱动电路103、发光单元104与第一导电部105和第二导电部106之间的连接关系，驱动电路103、发光单元104、第一导电部105以及第二导电部106的尺寸并不是按照比例进行绘制的，并且它们的相对位置关系也不一定与实际位置完全对应。在附图中，为了清晰起见，可能夸大了某些区域和层的比例。
通过使第一导电部105和第二导电部106位于同一层，单层导电 层不仅可以用来制作第二导电部106的第一焊盘107和第二焊盘108以及连接驱动电路103和发光单元104的走线，同时还可以用来制作第一导电部105的多条信号线以将相应的电信号传输至每个发光区域102内的驱动电路103和发光单元104。相比之下，相关技术中通常使用至少两个导电层来实现上述电连接关系，即，通过第一导电层来制作第一焊盘和第二焊盘，通过与该第一导电层位于不同层的第二导电层来制作信号线以传输相应的电信号。由于第一导电层和第二导电层在垂直于衬底的方向上往往不可避免地存在交叠，而二者的交叠区域为性能薄弱区域，因此第一导电层和第二导电层之间非常容易发生短路或断路，从而影响发光基板的发光性能。而且在制备位于不同层的第一导电层和第二导电层时，需要使用不同的掩膜板，这大大增加了生产成本。相比于相关技术，本申请第一导电部105和第二导电部106位于同一层，一方面，由于单层导电层不存在双层导电层的交叠问题，因此可以完全避免第一导电部105和第二导电部106由于在垂直于衬底101的方向上的交叠导致的短路或断路，从而可以改善发光基板100的发光性能，提高发光基板100的发光稳定性。另一方面，在制造过程中，可以由同一材料通过同一工艺来同时形成第一导电部105和第二导电部106，因此可以减少掩膜板的使用数量，降低生产成本，同时可以简化制程工艺，提高生产效率。
如图1所示，多个发光区域102沿第一方向D1布置成M行且沿与第一方向D1交叉的第二方向D2布置成N列，M和N均为大于等于1的正整数。第一方向D1可以是图中的竖直方向，第二方向D2可以是图中的水平方向，第一方向D1和第二方向D2可以相互垂直。第一导电部105包括沿第一方向D1延伸的N条驱动电压信号线VLEDL和N条公共电压信号线GNDL，从而使得每列发光区域001包括一条驱动电压信号线VLEDL和一条公共电压信号线GNDL。在每列发光区域001中，一条驱动电压信号线VLEDL与该列发光区域001内的每个发光单元104的第一端连接，一条公共电压信号线GNDL与该列发光区域001内的每个驱动电路103连接。驱动电压信号线VLEDL配置为向发光单元104提供驱动电压，公共电压信号线GNDL配置为向驱动电路103提供公共电压(例如接地电压)，例如在需要使某个发光区域102内的发光单元104发光时，通过使驱动电压为高电压且公共电压为 低电压，使得在发光单元104两侧产生电压差，从而驱动该发光单元104发光。在每列发光区域001中，驱动电压信号线VLEDL、发光单元104、驱动电路103、以及公共电压信号线GNDL沿着第二方向D2依次排列。以图1中的第1列发光区域001为例，该列发光区域001内的各个发光单元104(即第1～M行发光单元104)布置成发光单元列，该列发光区域001内的各个驱动电路103(即第1～M行驱动电路103)布置成驱动电路列，在第二方向D2上沿着图中从左至右的方向，按照驱动电压信号线VLEDL、发光单元列、驱动电路列、以及公共电压信号线GNDL的顺序依次排列。在一些实施例中，在每列发光区域001内，驱动电压信号线VLEDL、发光单元列、驱动电路列、以及公共电压信号线GNDL在衬底101上的正投影彼此不交叠。通过这样的布置方式，可以完全避免第一导电部105的驱动电压信号线VLEDL和公共电压信号线GNDL与第二导电部106的第一焊盘107和第二焊盘108之间出现短路或断路，从而可以改善发光基板100的发光性能，提高发光基板100的发光稳定性。
驱动电路103可以为集成电路，尤其是可以为一种具有多个端子的封装芯片。驱动电路103可以包含一个输出端子，也可以包含至少两个输出端子，例如两个输出端子、三个输出端子、四个输出端子或者更多个输出端子。本申请的驱动电路103的各个端子的布置方式相较于相关技术进行了优化，从而可以更好地配合各条信号线的布线，使得各条信号线之间无论是在垂直于衬底101的方向上还是在平行于衬底101的方向上，均没有交叠。
下面，参考图2和图7来描述发光基板200和发光基板300所具有的一些共同特性。
如图2和图7所示，每个驱动电路103包括沿第一方向D1和第二方向D2阵列布置的多个端子，多个端子沿第二方向D2排列成至少两列。多个端子包括至少一个输出端子Out和至少一个公共电压端子GND，至少一个输出端子Out和至少一个公共电压端子GND位于多个端子的不同列中。在每列发光区域001内，每个驱动电路103的至少一个输出端子Out与和该驱动电路103连接的至少一个发光单元104的第二端一一对应连接，以将驱动信号传输给至少一个发光单元104；每个驱动电路103的至少一个公共电压端子GND与公共电压信号线 GNDL连接，以接收公共电压信号线GNDL传输的公共电压(例如接地电压)。
驱动电路103还包括地址端子Di/Di_in、中继端子Out/Di_out以及电源端子Pwr/Vcc。每列发光区域001内的各个驱动电路103依次级联，第i级驱动电路103的地址端子Di/Di_in位于第i级驱动电路103的靠近第i-1级驱动电路103的一侧，第i级驱动电路103的中继端子Out/Di_out位于第i级驱动电路103的靠近第i+1级驱动电路103的一侧，1＜i＜M且i为正整数。在本公开的实施例中，每列发光区域001内的各个驱动电路103沿着第一方向D1以从下向上的方向依次级联，第i级驱动电路103指的是在每列发光区域001内从第M行驱动电路103开始往上数第i个驱动电路103。例如，以第1列发光区域001为例，位于第1列第M行的驱动电路103为第1级驱动电路，位于第1列第M-1行的驱动电路103为第2级驱动电路，以此类推，位于第1列第2行的驱动电路103为第M-1级驱动电路，位于第1列第1行的驱动电路103为第M级驱动电路。在如图2所示的驱动电路103中，地址端子为Di，中继端子为Out，电源端子为Pwr。在该驱动电路103中，输出端子Out复用作中继端子，即输出端子Out和中继端子为同一个端子，输出端子Out在不同的时段内分别输出不同的信号，例如分别作为中继端子输出中继信号和作为输出端子输出驱动信号。在如图7所示的驱动电路103中，地址端子为Di_in，中继端子为Di_out，电源端子为Vcc。在该驱动电路103中，输出端子Out和中继端子Di_out是两个不同的端子。地址端子Di/Di_in配置为接收地址信号，中继端子Out/Di_out配置为输出中继信号，电源端子Pwr/Vcc配置为接收电源电压信号。驱动电路103的多个端子沿第二方向D2布置成第一列和第二列，在每列发光区域001内，驱动电路103的第一列端子位于驱动电路103的邻近驱动电压信号线VLEDL的一侧(即位于驱动电路103的左侧)，驱动电路103的第二列端子位于驱动电路103的邻近公共电压信号线GNDL的一侧(即位于驱动电路103的右侧)。驱动电路103的端子的这种布置方式，有利于促进各条信号走线的规整布置，使得各条信号线之间彼此不交叠，从而避免各条信号走线之间由于交叠导致的短路/断路或信号串扰。
如图2和图7所示，第一导电部105还包括沿第一方向D1延伸的 N条选址信号线ADDRL，使得每列发光区域001包括一条选址信号线ADDRL。虽然图2和图7仅示出了发光基板包括四个发光区域102，四个发光区域102以2行*2列的方式布置，但是这仅是发光基板的部分截图，发光基板事实上通常包括多个发光区域102，多个发光区域102布置成M行和N列，M和N为大于等于1的任意正整数。因此，每列发光区域001包括多个驱动电路103，该多个驱动电路103之间通过沿第一方向D1延伸的级联走线111依次级联。选址信号线ADDRL与第一级驱动电路103的地址端子Di/Di_in连接，并且上一级驱动电路的中继端子Out/Di_out经由级联走线111连接到下一级驱动电路103的地址端子Di/Di_in。在图2的示例中，每列发光区域001示出为包括两个驱动电路103，该两个驱动电路103之间通过沿第一方向D1延伸的级联走线111依次级联。选址信号线ADDRL与第一级驱动电路103的地址端子Di连接，并且第一级驱动电路的中继端子Out经由级联走线111连接到第二级驱动电路103的地址端子Di。在图7的示例中，每列发光区域001示出为包括2个驱动电路103，该两个驱动电路103之间通过沿第一方向D1延伸的级联走线111依次级联。选址信号线ADDRL与第一级驱动电路103的地址端子Di_in连接，并且第一级驱动电路的中继端子Di_out经由级联走线111连接到第二级驱动电路103的地址端子Di_in。
选址信号线ADDRL配置为向每列发光区域001内的第一级驱动电路103的地址端子Di/Di_in传输地址信号，第一级驱动电路103接收该地址信号后，可以解析并获得、存储该地址信号中的地址信息以作为该第一级驱动电路103的地址信息，同时还可以使该地址信息递增1或递增另一固定量并将递增后的地址信息(新的地址信息)调制为中继信号，第一级驱动电路103的中继端子Out/Di_out经由级联走线111将该中继信号传输至第二级驱动电路103的地址端子Di/Di_in，以作为第二级驱动电路103的地址信息。当然，第一级驱动电路103还可以采用其他任意适当的函数对其地址信息进行变换以生成中继信号。第二级驱动电路103通过类似的方式向第三级驱动电路103传输中继信号以作为第三级驱动电路103的地址信息，以此类推。通过这样的方式，可以为每列发光区域001内的多个级联的驱动电路103中的每一个配置相应的地址信息。可以看出，对于一列发光区域001，只需要通 过一条选址信号线ADDRL提供一个地址信号，便可以使该列发光区域001内的所有驱动电路103均获得各自的地址信息。这样极大地减少了信号线的数量，节省了布线空间，并且简化了控制方式。
如图2和图7所示，第一导电部105还包括沿第一方向D1延伸的N条反馈信号线FBL，每列发光区域001包括一条反馈信号线FBL。在每列发光区域001内，反馈信号线FBL与最后一级驱动电路103的中继端子Out/Di_out连接。反馈信号线FBL绕过该列发光区域001内的公共电压信号线GNDL且位于该公共电压信号线GNDL远离驱动电路103的一侧。
第一导电部105还包括N条电源信号线PwrL/VccL，每列发光区域001包括一条电源信号线PwrL/VccL。每条电源信号线PwrL/VccL包括主体部分和第一连接部118，电源信号线PwrL/VccL的主体部分沿第一方向D1延伸。在每列发光区域001内，一条电源信号线PwrL/VccL通过第一连接部118与该列发光区域001内的所有驱动电路103的电源端子Pwr/Vcc连接，并且各个驱动电路103的第一列端子在衬底101上的正投影与第二列端子在衬底101上的正投影分别位于该条电源信号线PwrL/VccL在衬底101上的正投影的两侧，也即，该条电源信号线PwrL/VccL布置在各个驱动电路103所占用的区域内，且不与各个驱动电路103的第一列端子和第二列端子交叠。通过使每列发光区域001内的电源信号线PwrL/VccL布置在各个驱动电路103所占用的区域内，可以节省布线空间，并且避免该条电源信号线PwrL/VccL与其他信号线之间的交叠。
需要说明的是，在本公开的实施例中，信号线通常包括主体部分和连接部，主体部分限定该条信号线的主要延伸方向，而连接部用于将该条信号线与所需的部件相连。例如，驱动电压信号线VLEDL通过其连接部与发光单元104的第二端连接；电源信号线PwrL/VccL通过第一连接部118与驱动电路103的电源端子Pwr/Vcc连接；公共电压信号线GNDL通过其连接部与驱动电路103的公共电压端子GND相连。每条信号线的连接部相比于其主体部分在长度或宽度方面占比都很小。因此，在本申请的说明书中，诸如“沿第一方向D1延伸的X信号线”的短语仅限定该X信号线的主体部分沿第一方向D1延伸，但并不限定该X信号线的连接部沿第一方向D1延伸。例如，每条电 源信号线PwrL/VccL的主体部分沿第一方向D1延伸，其第一连接部118并没有沿第一方向D1延伸，而是沿与第一方向D1交叉的方向(例如第二方向D2)延伸。
在每列发光区域001中，电源信号线PwrL/VccL配置为向每个驱动电路103的电源端子Pwr/Vcc传输电源电压信号，从而为每个驱动电路103提供电源电压。在一个示例中，电源电压信号为电力线载波通信信号。在这种情况下，电源信号线PwrL/VccL不仅可以向每个驱动电路103提供电源电压，还可以向每个驱动电路103提供通信数据，该通信数据可以用于控制与该驱动电路103相连的至少一个发光单元104的发光时长，进而控制其视觉上的发光亮度。该电力线载波通信信号包含对应于通信数据的信息。例如，通信数据为反映发光时长的数据，进而代表了所需要的发光亮度。相比于通常的串行外设接口(Serial Peripheral Interface，SPI)协议，本公开实施例通过采用电力线载波通信(Power Line Carrier Communication，PLC)协议，将通信数据叠加在电源信号线PwrL/VccL上，从而有效减少信号线的数量。
通过图2和图7的示例可以看出，驱动电路103的端子采用如上所述的布置方式，可以使得在每列发光区域001内，第一导电部105的驱动电压信号线VLEDL、选址信号线ADDRL、级联走线111、电源信号线PwrL/VccL、公共电压信号线GNDL、以及反馈信号线FBL在衬底101上的正投影彼此不交叠。除此之外，第一导电部105的驱动电压信号线VLEDL、公共电压信号线GNDL、反馈信号线FBL在衬底101上的正投影与第二导电部106的第一焊盘107和第二焊盘108在衬底101上的正投影也不交叠。由此，可以完全避免位于同一层的第一导电部105和第二导电部106由于交叠导致的短路或断路，从而可以改善发光基板的发光性能，提高发光基板的发光稳定性。
以上描述了发光基板200和发光基板300的一些共同特性，下面，以两个示例来分别描述发光基板200的具体布置方式和发光基板300的具体布置方式。
图2示出了发光基板200的布置方式。虽然图2仅示出了四个发光区域102，四个发光区域102以2行*2列的方式布置，但是这仅是发光基板200的部分截图，发光基板200可以包括任意适当数量的发光区域102，该任意适当数量的发光区域102可以布置成多行和多列。 本公开实施例对发光基板200包括的发光区域102的数量不做具体限制。如图所示，每个发光区域102包括一个驱动电路103和与该驱动电路103连接的一个发光单元104。图3是该驱动电路103的端子的布置方式。
如图2和图3所示，每个驱动电路103包括四个端子，分别是地址端子Di、电源端子Pwr、公共电压端子GND、以及输出端子Out。输出端子Out和地址端子Di为驱动电路103的第一列端子，其位于驱动电路103的邻近驱动电压信号线VLEDL的一侧(即位于驱动电路103的左侧)；公共电压端子GND和电源端子Pwr为驱动电路103的第二列端子，其位于驱动电路103的邻近公共电压信号线GNDL的一侧(即位于驱动电路103的右侧)。地址端子Di和电源端子Pwr位于多个端子中的第二行，公共电压端子GND和输出端子Out位于多个端子中的第一行。如前所述，输出端子Out复用作中继端子，在每列发光区域001内，第一级驱动电路103(即图2中位于第2行第1列的驱动电路103)的输出端子Out的一端连接到对应于该驱动电路103的发光单元104，另一端经由级联走线111连接到第二级驱动电路103(即图2中位于第1行第1列的驱动电路103)的地址端子Di。第二级驱动电路103的输出端子Out的一端连接到对应于该驱动电路103的发光单元104，另一端连接到反馈走线FBL。输出端子Out可以在不同的时段分别输出不同的信号。例如，驱动电路103的输出端子Out在一个时段内输出中继信号以作为与该驱动电路103级联的下一级驱动电路103的地址信号，在另一个时段内向与该驱动电路103连接的发光单元104提供驱动信号以使该发光单元104发光。所述一个时段和另一个时段是两个独立的时段，例如另一个时段紧随在所述一个时段之后。驱动信号例如可以为驱动电流，用于驱动发光单元104发光。需要说明的是，当驱动信号为驱动电流时，驱动电流可以从输出端子Out流向发光单元104，也可以从发光单元104流入输出端子Out，驱动电流的流动方向可以根据实际需求而定，本公开的实施例对此不作限制。
发光基板200的驱动电路103的各个端子之间的间距通常根据诸多因素(诸如工艺极限能力、两列端子之间的线宽要求、电学设计要求等因素)来确定，本公开的实施例对此不做具体限定。例如，第一列端子和第二列端子之间的间距可以为70～300um，第一行端子和第二 行端子之间的间距可以为70～300um。如图3所示，在一个示例中，第一列端子与第二列端子之间的间距S1为140μm，第一行端子与第二行端子之间的间距S2为120μm。也就是说，输出端子Out与公共电压端子GND之间的间距为140μm，地址端子Di与电源端子Pwr之间的间距为140μm；输出端子Out与地址端子Di之间的间距为120μm，公共电压端子GND与电源端子Pwr之间的间距为120μm。驱动电路103的四个端子所占据的面积基本相同，并且具有基本相同的长度和宽度。每个端子沿第二方向D2的宽度S3为80μm，每个端子沿第一方向D1的长度S4为100μm。第二行端子与驱动电路103的第一侧边(即驱动电路103的下边缘)之间的间距S5为25μm，即地址端子Di和电源端子Pwr与驱动电路103的下边缘之间的间距S5均为25μm；第一行端子与驱动电路103的第二侧边(即驱动电路103的上边缘)之间的间距S5为25μm，即输出端子Out和公共电压端子GND与驱动电路103的上边缘之间的间距S5均为25μm。第一列端子与驱动电路103的第三侧边(即驱动电路103的左边缘)之间的间距S6为25μm，即输出端子Out和地址端子Di与驱动电路103的左边缘之间的间距S6均为25μm；第二列端子与驱动电路103的第四侧边(即驱动电路103的右边缘)之间的间距S6为25μm，即公共电压端子GND和电源端子Pwr与驱动电路103的右边缘之间的间距S6均为25μm。由此，可以得知，驱动电路103沿第一方向D1的长度L为370μm，驱动电路103沿第二方向D2的宽度W为350μm。在每列发光区域001内，电源信号线PwrL与第一列端子和第二列端子之间的间距可以分别为10～100um。在一个示例中，第一列端子和第二列端子之间的电源信号线PwrL沿第二方向D2的宽度大于等于40um。
在图2的示例中，每列发光区域001包括驱动电压信号线VLEDL、选址信号线ADDRL、级联走线111、电源信号线PwrL、公共电压信号线GNDL、以及反馈信号线FBL，这些信号线无论是在垂直于衬底101的方向上还是在平行于衬底101的方向上彼此均不交叠。这些信号线的作用及布置方式如前所述，为了简洁起见，此处不再赘述。
下面，简单介绍图2中的发光基板200的工作方式。
驱动电路103开始工作时，首先通过电源信号线PwrL为每列发光区域001内的各个驱动电路103的电源端子Pwr提供电源电压以完成 初始化，如此，驱动电路103处于上电状态。
接着，在第一时段内进行写地址操作，也即，ADDRL信号线将地址信号通过地址端子Di输入到第一级驱动电路103，从而写入地址。
接着，在第二时段，进行驱动配置，并且，第一级驱动电路103通过输出端子Out输出中继信号，该中继信号经由级联走线111传输至第二级驱动电路103的地址端子Di，以作第二级驱动电路103的地址信号。以此类推，直到所有的驱动电路103均完成地址信息配置。
然后，在第三时段，向驱动电压信号线VLEDL提供驱动电压。例如，当多个驱动电路103均获取到对应的地址信息之后进入该第三时段。此时，该驱动电压信号线VLEDL上传输的驱动电压变为高电平。
接着，在第四时段，每个驱动电路103的输出端子Out根据所需要的发光时长提供驱动信号(例如驱动电流)，此时，驱动电压信号线VLEDL、发光单元104、与该发光单元104电连接的输出端子Out以及公共电压信号线GNDL构成信号回路，发光单元104根据需要的发光时长发光。
最后，在第五时段，系统关闭，也即是，驱动电路103断电，且驱动电压信号线VLEDL提供的驱动电压变为低电平，发光单元104停止发光。
图2示出的发光基板200可以实现分区调光。发光基板200包括多个发光区域102，每个发光区域包括一个驱动电路103和与该驱动电路103连接且由该驱动电路103控制的一个发光单元104，从而使得每个发光单元104的发光亮度可以被分别独立控制。例如，通过设置提供给每个驱动电路103的地址信号和电源电压信号，可以分别控制与每个驱动电路103连接的发光单元104的发光时长，进而控制视觉上的发光亮度。该发光基板200可以实现发光亮度的分区域独立控制，适用范围广。并且，每个驱动电路103的端口数量少，所需要的控制信号少，因此控制方式简单，功耗小，便于操作。该发光基板200的集成度高，可与液晶显示器件配合实现高对比度显示。
图4示出了第一焊盘107及其周边走线的布置。第一焊盘107上安装有图2示出的驱动电路103且与驱动电路103电连接，第一焊盘107在对应驱动电路103的四个端子的位置处分别设置有四个子焊盘，分别是用于安装地址端子Di的第一子焊盘、用于安装电源端子Pwr的 第二子焊盘、用于安装公共电压端子GND的第三子焊盘、以及用于安装输出端子Out的第四子焊盘。第一子焊盘与驱动电路103的地址端子Di连接，第二子焊盘与驱动电路103的电源端子Pwr连接，第三子焊盘与驱动电路103的公共电压端子GND连接，第四子焊盘与驱动电路103的输出端子Out连接。第一子焊盘与选址信号线ADDRL连接，以将选址信号线ADDRL上的地址信号传输给地址端子Di。第二子焊盘与电源信号线PwrL连接，以将电源信号线PwrL上的电源电压信号传输给电源端子Pwr。第三子焊盘与公共电压信号线GNDL连接，以将公共电压信号线GNDL上的公共电压信号传输给公共电压端子GND。第四子焊盘的一端与级联走线111连接，以在一个时段内输出中继信号以作为与该驱动电路103级联的下一级驱动电路103的地址信号；第四子焊盘的另一端与走线109相连，以在另一个时段内经由该走线109将驱动信号传输至与该驱动电路103连接的发光单元104。
图5是图2的局部示意图，示出了两列发光区域001。在每列发光区域001内，四个第二焊盘108依次串联并连接到第一焊盘107。每列发光区域001内示出了选址信号线ADDRL、电源信号线PwrL、公共电压信号线GNDL、以及反馈信号线FBL，未示出驱动电压信号线VLEDL，但是如前所述，每列发光区域001包括驱动电压信号线VLEDL，只是图中未示出而已。如图所示，第1列发光区域001内的选址信号线ADDRL的靠近第一焊盘107的一端与第2列发光区域001内的选址信号线ADDRL的靠近第一焊盘107的一端基本齐平，即第1列发光区域001内的选址信号线ADDRL与第2列发光区域001内的选址信号线ADDRL具有基本相同的长度；第1列发光区域001内的电源信号线PwrL的靠近第一焊盘107的一端与第2列发光区域001内的电源信号线PwrL的靠近第一焊盘107的一端基本齐平，即第1列发光区域001内的电源信号线PwrL与第2列发光区域001内的电源信号线PwrL具有基本相同的长度；第1列发光区域001内的公共电压信号线GNDL的靠近第一焊盘107的一端与第2列发光区域001内的公共电压信号线GNDL的靠近第一焊盘107的一端基本齐平，即第1列发光区域001内的公共电压信号线GNDL与第2列发光区域001内的公共电压信号线GNDL具有基本相同的长度；第1列发光区域001内的反馈信号线FBL的靠近第一焊盘107的一端与第2列发光区域001内的 反馈信号线FBL的靠近第一焊盘107的一端基本齐平，即第1列发光区域001内的反馈信号线FBL与第2列发光区域001内的反馈信号线FBL具有基本相同的长度。虽然图中未示出，但是第1列发光区域001内的驱动电压信号线VLEDL的靠近第一焊盘107的一端与第2列发光区域001内的驱动电压信号线VLEDL的靠近第一焊盘107的一端也基本齐平，即第1列发光区域001内的驱动电压信号线VLEDL与第2列发光区域001内的驱动电压信号线VLEDL具有基本相同的长度。当发光基板200包括N列发光区域001时，各列发光区域001内的相同信号线具有基本相同的长度，以保持各列发光区域001的均一性。这里的“各列发光区域001内的相同信号线”指的是各列发光区域001内具有相同作用的信号线，例如第1列发光区域001～第N列发光区域001内的驱动电压信号线VLEDL为相同信号线。通过这样的布置方式，可以使各列发光区域001内的相同信号线具有基本相同的长度，因此各列发光区域001内的信号线具有大致相同的电阻以及电压降，从而使得各列发光区域001之间具有较好的亮度均一性。
发光基板200还可以包括屏蔽环GND ESD Ring，图6示出了该屏蔽环GND ESD Ring。屏蔽环GND ESD Ring围绕在多个发光区域102的外围，以提供静电屏蔽作用。屏蔽环GND ESD Ring接收的电信号与公共电压信号线GNDL接收的电信号相同。例如，屏蔽环GND ESD Ring和公共电压信号线GNDL均连接到绑定区的绑定电极，连接屏蔽环GND ESD Ring的绑定电极与连接公共电压信号线GNDL的绑定电极具有相同的定义，从而使得屏蔽环GND ESD Ring接收的电信号与公共电压信号线GNDL接收的电信号相同。屏蔽环GND ESD Ring可以和第一导电部105与第二导电部106位于同一层。屏蔽环GND ESD Ring的形状并不限于图6示出的形状，其可以具有任意适当的形状，只要其可以对发光区域102提供静电屏蔽作用即可。在一个示例中，屏蔽环GND ESD Ring的宽度大于等于200um。
图7示出了发光基板300，图8示出了该发光基板300的驱动电路103的各个端子的布置方式。在图7中示出的发光基板300具有与在图2中示出的发光基板200大体相同的构造，并且因此使用相同的附图标记来指代相同的部件。因此，图7中具有与图2相同附图标记的部件的详细作用及功能可以参考对图2的说明，此处不再赘述，为了简洁 起见，以下将主要讨论不同的部分。
参考图7和图8，与图2中的发光基板200不同的是，图7中的发光基板300的驱动电路103的端子的数量更多，其中，输出端子Out的数量为多个，公共电压端子GND的数量为至少一个。图7示出了输出端子Out的数量为四个且公共电压端子GND的数量为两个，但这仅是一个示例。输出端子Out的数量可以多于四个或少于四个，公共电压端子GND的数量可以多于两个或少于两个。在本公开的实施例中，输出端子Out的数量至少为两个，公共电压端子GND的数量至少为一个。此外，该驱动电路103还包括数据端子Data。如图7和图8所示，驱动电路103包括两列端子，第一列端子包括电源端子Vcc和四个输出端子Out1、Out2、Out3、Out4，第一列端子位于驱动电路103的邻近驱动电压信号线VLEDL的一侧(即位于驱动电路103的左侧)；第二列端子包括地址端子Di_in、中继端子Di_out、数据端子Data以及两个公共电压端子GND，第二列端子位于驱动电路103的邻近公共电压信号线GNDL的一侧(即位于驱动电路103的右侧)。驱动电路103的多个端子布置成五行，地址端子Di_in位于多个端子中的第5行，中继端子Di_out位于多个端子中的第1行。虽然图8中示出电源端子Vcc位于第一列端子中的第3行，数据端子Data位于第2列端子中的第2行，但这仅是一个示例，本公开实施例并不限制电源端子Vcc在第一列端子中的具体位置以及数据端子Data在第2列端子中的具体位置。例如，电源端子Vcc可以位于第一列端子中的第1行～第5行中的任意一个，数据端子Data可以位于第二列端子中的第2行～第4行中的任意一个。
如图所示，驱动电路103的四个输出端子Out1、Out2、Out3、Out4与四个发光单元104的第二端一一对应连接，以为发光单元104提供驱动信号。在图7的示例中，驱动电路103的输出端子与中继端子是不同的端子。该驱动电路103配置为，在一个时段内通过中继端子Di_out输出中继信号以作为与该驱动电路103级联的下一级驱动电路103的地址信号，在另一个时段内通过四个输出端子Out1、Out2、Out3、Out4分别向四个发光单元104提供驱动信号。所述一个时段和另一个时段是两个独立的时段，例如另一个时段紧随在所述一个时段之后。驱动信号例如可以为驱动电流，用于驱动发光单元104发光。需要说 明的是，当驱动信号为驱动电流时，驱动电流可以从输出端子Out1、Out2、Out3、Out4流向发光单元104，也可以从发光单元104流入输出端子Out1、Out2、Out3、Out4，驱动电流的流动方向可以根据实际需求而定，本公开的实施例对此不作限制。
虽然图7仅示出了四个发光区域102，四个发光区域102以2行*2列的方式布置，但是这仅是发光基板300的部分截图，发光基板300可以包括任意适当数量的发光区域102，该任意适当数量的发光区域102可以布置成M行和N列，M和N可以是大于等于1的任意正整数。本公开实施例对发光基板300包括的发光区域102的数量不做具体限制。
如前所述，每列发光区域001包括沿第一方向D1延伸的驱动电压信号线VLEDL、选址信号线ADDRL、级联走线111、电源信号线VccL、公共电压信号线GNDL、以及反馈信号线FBL，它们在衬底101上的正投影彼此不交叠。这些信号线的作用及布置方式如前所述，为了简洁起见，此处不再赘述。除此之外，每列发光区域001还包括一条数据驱动信号线DataL。每条数据驱动信号线DataL包括主体部分和第二连接部119，数据驱动信号线DataL的主体部分沿第一方向D1延伸。在每列发光区域001中，一条数据驱动信号线DataL通过第二连接部119与该列发光区域001内的所有驱动电路103的数据端子Data连接，并且各个驱动电路103的第一列端子在衬底101上的正投影与第二列端子在衬底101上的正投影分别位于该条数据驱动信号线DataL在衬底101上的正投影的两侧，也即，该条数据驱动信号线DataL布置在各个驱动电路103所占用的区域内，且不与各个驱动电路103的第一列端子和第二列端子交叠。该条数据驱动信号线DataL在衬底101上的正投影与该列发光区域001内的电源信号线VccL在衬底101上的正投影也不交叠。通过使每列发光区域001内的数据驱动信号线DataL布置在各个驱动电路103所占用的区域内，可以节省布线空间，并且避免该条数据驱动信号线DataL与其他信号线之间的交叠。
在每列发光区域001中，一条数据驱动信号线DataL配置为向各个驱动电路103的数据端子Data提供驱动数据，该条数据驱动信号线DataL上可以加载多个不同的驱动数据，各个驱动电路103可以根据其地址信息确定所对应的驱动数据，并根据各自对应的驱动数据来驱动 各自所连接的发光单元104。在本公开实施例中，通过数据驱动信号线DataL向驱动电路103的数据端子Data来传输驱动数据，因此避免了采用SPI(Serial Peripheral interface，串行外围设备接口)进行数据传输而导致焊盘、走线数量太多的问题，进而可以简化发光基板300、外部电路和驱动电路103的结构。
发光基板300的驱动电路103的各个端子之间的间距通常根据诸多因素(诸如工艺极限能力、两列端子之间的线宽要求、电学设计要求等因素)来确定，本公开的实施例对此不做具体限定。例如，第一列端子和第二列端子之间的间距可以为70～500um，五行端子中的任意相邻两行端子之间的间距可以为70～500um。如图8所示，在一个示例中，第一列端子与第二列端子之间的间距S1为210μm，任意相邻两行端子之间的间距S2为90μm。也就是说，第一输出端子Out1与中继端子Di_out之间的间距、第二输出端子Out2与数据端子Data之间的间距、电源端子Vcc与公共电压端子GND之间的间距、第三输出端子Out3与公共电压端子GND之间的间距、以及第四输出端子Out4与地址端子Di_in之间的间距均为S1，为210μm；第一输出端子Out1与第二输出端子Out2之间的间距、第二输出端子Out2与电源端子Vcc之间的间距、电源端子Vcc与第三输出端子Out3之间的间距、第三输出端子Out3与第四输出端子Out4之间的间距、中继端子Di_out与数据端子Data之间的间距、数据端子Data与公共电压端子GND之间的间距、公共电压端子GND与相邻的公共电压端子GND之间的间距、以及公共电压端子GND与地址端子Di_in之间的间距均为S2，为90μm。驱动电路103的十个端子所占据的面积基本相同，并且具有基本相同的长度和宽度。每个端子沿第二方向D2的宽度S3为110μm，每个端子沿第一方向D1的长度S4为100μm。第五行端子与驱动电路103的第一侧边(即驱动电路103的下边缘)之间的间距S5为35μm，即第四输出端子Out4和地址端子Di_in与驱动电路103的下边缘之间的间距S5均为35μm；第一行端子与驱动电路103的第二侧边(即驱动电路103的上边缘)之间的间距S5为35μm，即第一输出端子Out1和中继端子Di_out与驱动电路103的上边缘之间的间距S5均为35μm。第一列端子与驱动电路103的第三侧边(即驱动电路103的左边缘)之间的间距S6为25μm，第二列端子与驱动电路103的第四侧边(即 驱动电路103的右边缘)之间的间距S6为25μm。由此，可以得知，驱动电路103沿第一方向D1的长度L为930μm，驱动电路103沿第二方向D2的宽度W为480μm。在每列发光区域001内，电源信号线VccL与第一列端子和第二列端子之间的间距可以分别为10～100um，数据驱动信号线DataL与第一列端子和第二列端子之间的间距可以分别为10～100um。在一个示例中，第一列端子和第二列端子之间的电源信号线VccL和数据驱动信号线DataL沿第二方向D2的宽度均大于等于40um。
图7示出的一个驱动电路103包括四个输出端子，因此一个驱动电路103可以同时连接四个发光单元104，从而可以大幅度减小驱动电路103的用量，降低发光基板300的成本。不仅如此，由于驱动电路103的用量减少，还可以降低发光基板300的制备难度，减少驱动电路103绑定良率对发光基板300的良率的影响，进而提高发光基板300的良率。另外，驱动电路103的端子采用如上所述的布置方式，可以使得在每列发光区域001中，第一导电部105的驱动电压信号线VLEDL、选址信号线ADDRL、级联走线111、电源信号线VccL、数据驱动信号线DataL、公共电压信号线GNDL、以及反馈信号线FBL在衬底101上的正投影彼此不交叠。除此之外，第一导电部105的驱动电压信号线VLEDL、公共电压信号线GNDL、反馈信号线FBL在衬底101上的正投影与第二导电部106的第一焊盘107和第二焊盘108在衬底101上的正投影也不交叠。由此，可以完全避免第一导电部105和第二导电部106由于交叠导致的短路或断路，从而可以改善发光基板300的发光性能，提高发光基板300的发光稳定性。
下面，简单介绍图7中的发光基板300的工作流程。
驱动电路103开始工作时，首先通过电源信号线VccL为每列发光区域001内的各个驱动电路103的电源端子Vcc提供电源电压以完成初始化，如此，驱动电路103处于上电状态。
接着，在第一时段内进行写地址操作，也即，ADDRL信号线将地址信号通过地址端子Di_in输入到第一级驱动电路103，从而写入地址。并且，第一级驱动电路103通过中继端子Di_out输出中继信号，该中继信号经由级联走线111传输至第二级驱动电路103的地址端子Di_in，以作第二级驱动电路103的地址信号。以此类推，直到所有的驱动电 路103均完成地址信息配置。
接着，在第二时段内进行驱动配置，在每列发光区域001内，每条数据驱动信号线DataL将驱动数据信号传输至各个驱动电路103的数据端子Data，以进行初始化配置。
然后，在第三时段内，向驱动电压信号线VLEDL提供驱动电压，此时，该驱动电压信号线VLEDL上传输的驱动电压变为高电平。
接着，在第四时段内，每个驱动电路103根据接收到的驱动数据来生成与其各个输出端子一一对应的驱动控制信号，驱动控制信号用于控制流经对应的输出端子的电流。如此，在驱动电压信号线VLEDL上加载的驱动电压的作用下，驱动电路103可以控制流经发光单元104的电流，达成根据驱动电路103驱动所连接的各个发光单元104的目的。
最后，在第五时段内，系统关闭，也即是，驱动电路103断电，且驱动电压信号线VLEDL提供的驱动电压变为低电平，发光单元104停止发光。
图7示出的发光基板300可以实现分区调光。每个驱动电路103包括四个输出端子Out1、Out2、Out3、Out4。该驱动电路103还包括逻辑控制模块CTR和控制模块CLM(图中未示出)，该逻辑控制模块CTR包括四个调制模块，即第一调制模块PWMM1、第二调制模块PWMM2、第三调制模块PWMM3、第四调制模块PWMM4。第一输出端子Out1～第四输出端子Out4与第一调制模块PWMM1～第四调制模块PWMM4一一对应连接。控制模块CLM用于根据数据驱动信号线DataL提供的驱动数据来生成第一驱动控制信号、第二驱动控制信号、第三驱动控制信号、第四驱动控制信号，并分别传输至第一调制模块PWMM1、第二调制模块PWMM2、第三调制模块PWMM3和第四调制模块PWMM4。以第一输出端子Out1为例，第一调制模块PWMM1与第一输出端子Out1电连接，并能够在第一驱动控制信号的控制下导通或者截止，使得第一输出端子Out1与公共电压信号线GNDL之间导通或者断开。当第一调制模块PWMM1导通时，公共电压信号线GNDL、第一输出端子Out1、与第一输出端子Out1电连接的发光单元104和驱动电压信号线VLEDL构成信号回路，发光单元104工作；当第一调制模块PWMM1截止时，上述信号回路断开，发光单元104不工作。如 此，第一调制模块PWMM1可以在第一驱动控制信号的控制下对流经发光单元104的电流进行调制，使得流经发光单元104的电流呈现为一种脉冲宽度调制信号。第一调制模块PWMM1可以根据第一驱动控制信号对流经发光单元104的脉冲宽度调制信号的占空比等因素进行调制，进而控制发光单元104的工作状态。当发光单元104包括LED时，通过增加脉冲宽度调制信号的占空比，可以提高LED在一个显示帧内的发光总时长，进而提高LED在该显示帧内的总发光亮度，使得发光基板300在该区域的亮度增大；反之，通过降低脉冲宽度调制信号的占空比，可以降低LED在一个显示帧内的发光总时长，进而降低LED在该显示帧内的总发光亮度，使得发光基板300在该区域的亮度减小，从而实现了与第一输出端子Out1电连接的发光单元104的亮度可控。以类似的方式，可以分别控制与第二输出端子Out2、第三输出端子Out3、第四输出端子Out4分别电连接的发光单元104的亮度，从而实现对发光基板300内的每个发光单元104的亮度控制。
图9示出了图7的发光基板300的一列发光区域001的局部放大图，图10示出了图9中的虚线框内的进一步的放大图。如图9和图10所示，第一焊盘107上安装有图7示出的驱动电路103且第一焊盘107与该驱动电路103电连接。第二焊盘108包括两个子焊盘，两个子焊盘例如分别与发光单元104的阳极和阴极电连接。第一焊盘107在对应驱动电路103的十个端子的位置处分别设置有十个子焊盘，分别是用于安装四个输出端子Out1～Out4且与四个输出端子Out1～Out4电连接的第一～第四子焊盘、用于安装电源端子Vcc且与电源端子Vcc电连接的第五子焊盘、用于安装两个公共电压端子GND且与两个公共电压端子GND分别电连接的第六和第七子焊盘、用于安装地址端子Di_in且与地址端子Di_in电连接的第八子焊盘、用于安装中继端子Di_out且与中继端子Di_out电连接的第九子焊盘以及用于安装数据端子Data且与数据端子Data电连接的第十子焊盘。第四子焊盘经由走线与第二焊盘108的两个子焊盘连接，以将驱动信号传输给与第四端子Out4电连接的发光单元104。第五子焊盘与电源信号线VccL连接，以将电源信号线VccL上的电源电压信号传输给电源端子Vcc。第六和第七子焊盘与公共电压信号线GNDL连接，以将公共电压信号线GNDL上的公共电压信号传输给两个公共电压端子GND。第八子焊盘与选址信号线 ADDRL连接，以将选址信号线ADDRL上的地址信号传输给地址端子Di_in。第九子焊盘与级联走线连接，以在一个时段内输出中继信号以作为与该驱动电路103级联的下一级驱动电路103的地址信号。第十子焊盘与数据驱动信号线DataL连接，以将数据驱动信号线DataL上的数据驱动信号传输给数据端子Data。
在本公开多个实施例提供的发光基板中，例如发光基板100、发光基板200、发光基板300中，每条驱动电压信号线VLEDL和与其相邻的其他信号线之间的间距需要大于等于0.2mm。这是因为驱动电压信号线VLEDL上的电压较高(例如约为10～50V)，而与该驱动电压信号线VLEDL相邻的其他信号线电压通常比较低，如果间距太小容易产生线路击穿等不良现象。发光基板上的其他信号线之间的间距可以按照工艺极限来设计，本公开实施例对此不做具体限定。例如，如果工艺极限是20um，则发光基板上的其他信号线之间的间距可以为20um。
第一导电部105和第二导电部106的材料可以是任意适当的导电材料，本公开实施例对此不做具体限定。例如，第一导电部105和第二导电部106的材料包括铜。在一个示例中，第一导电部105和第二导电部106可以是Cu和CuNi的叠层。叠层的靠近衬底101的一侧是Cu层，其厚度例如可以是2um，Cu是作为电信号传递通道的优选材料。叠层的远离衬底101的一侧是CuNi层，其厚度例如可以是0.6um，CuNi层可以用于保护Cu层，防止电阻率低的Cu层表面暴露而发生氧化。在另一个示例中，第一导电部105和第二导电部106例如为MoNb/Cu/MoNb的叠层，叠层中靠近衬底101的一侧为MoNb层，厚度大约在
Figure PCTCN2021109837-appb-000001
左右，主要用于提高叠层与衬底101的粘附力；叠层的中间层为Cu层，Cu为电信号传递通道的优选材料；叠层中远离衬底101的一侧为MoNb层，厚度大约在
Figure PCTCN2021109837-appb-000002
左右，MoNb层可以用于保护中间Cu层，防止电阻率低的中间Cu层表面暴露而发生氧化。
上面任一实施例描述的发光基板还可以包括多个柔性电路板110，图11A示出了多个柔性电路板110与信号线的连接关系，图11B示出了图11A中的区域I的局部放大图，即一个柔性电路板110与信号线的连接关系。如图11A和11B所示，柔性电路板110设置在发光基板上的绑定区内，并通过绑定区的绑定电极120与第一导电部105的各条信号线电连接。在图2的示例中，柔性电路板110与第一导电部105 的驱动电压信号线VLEDL、选址信号线ADDRL、电源信号线PwrL、公共电压信号线GNDL、反馈信号线FBL、以及屏蔽环GND ESD Ring电连接，柔性电路板110为公共电压信号线GNDL和屏蔽环GND ESD Ring提供相同的信号。在图7的示例中，柔性电路板110与第一导电部105的驱动电压信号线VLEDL、选址信号线ADDRL、电源信号线VccL、驱动数据信号线DataL、公共电压信号线GNDL、反馈信号线FBL、以及屏蔽环GND ESD Ring电连接，柔性电路板110为公共电压信号线GNDL和屏蔽环GND ESD Ring提供相同的信号。图11B仅示出了最后一行发光区域，即第M行发光区域，其示出了四列发光区域，第k列发光区域、第k+1列发光区域、第k+2列发光区域、第k+3列发光区域，并分别用虚线框示出了每列发光区域所占据的区域。这四列发光区域可以是N列发光区域中任意相邻的四列发光区域。每列发光区域包括发光单元104。各条信号线(为了简洁起见，图中仅标出了驱动电压信号线VLEDL和公共电压信号线GNDL)均包括沿第一方向D1延伸的直线部分116和弯折部分117，弯折部分117位于扇出区114内，各条信号线通过其弯折部分117与绑定电极120连接，绑定电极120连接到柔性电路板110，从而实现各条信号线与柔性电路板110的电连接。每条信号线的弯折部分117沿第二方向D2的宽度小于相邻两列发光区域沿第二方向D2的宽度。以图11中的第k列发光区域为例，驱动电压信号线VLEDL的弯折部分117沿第二方向D2的宽度T1小于相邻两列(例如第k列和第k+1列)发光区域沿第二方向D2的宽度T2。在扇出区114内，每条信号线的直线部分116与弯折部分117的夹角在80°～100°。在一个示例中，每条信号线的直线部分116与弯折部分117的夹角为90°。在相关技术中，每个柔性电路板对应5～15列发光区域，即每个柔性电路板与5～15列发光区域内的信号线电连接。而在本申请中，通过增加柔性电路板110的数量，使得每个柔性电路板对应3～8列发光区域001，即每个柔性电路板110与3～8列发光区域001内的信号线电连接。例如，在图11B的示例中，每个柔性电路板110与4列发光区域001内的信号线电连接。通过增加柔性电路板110的数量并且配合信号线的近乎直角弯折设计，可以使每条信号线基本上以直线方式延伸至绑定区并与柔性电路板110连接。相比于相关技术，本公开实施例提供的发光基板的扇出区114具有较窄的宽度，从 而可以减少发光基板的下边框宽度，有利于实现窄边框。
图12作为示例示出了每个发光单元104的几种可选的布置方式。每个发光单元104包括彼此连接的多个发光元件，该多个发光元件的第一端与驱动电压信号线VLEDL电连接，该多个发光元件的第二端与驱动电路103的输出端子Out电连接。图12(a)示出了每个发光单元104包括彼此串联的四个发光元件，该四个发光元件布置为1列*4行；图12(b)示出了每个发光单元104包括彼此串联的四个发光元件，该四个发光元件布置为2列*2行；图12(c)示出了每个发光单元104包括彼此串联的九个发光元件，该九个发光元件布置为3列*3行。当然，每个发光单元104中的多个发光元件并不限于上述布置方式，它们可以以任意适当的方式布置。在一个示例中，每个发光单元104中的多个发光元件可以彼此并联。在另一个示例中，每个发光单元104中的多个发光元件可以串联和并联结合。每个发光单元104包括的发光元件的数量可以根据实际需求而定，例如根据发光基板的尺寸和所需要的亮度而定。每个发光元件可以为有机发光二级管或无机发光二级管。在一些实施例中，每个发光元件可以为次毫米发光二极管(Mini LED)或微型发光二极管(Mirco LED)。次毫米发光二极管的尺寸例如在100微米～500微米的范围内；微型发光二极管的尺寸例如小于100微米。本公开的实施例对于发光单元104的发光元件的类型和尺寸不作限制。利用次毫米发光二极管或微型发光二极管来作为发光单元104的发光元件，并结合各个发光单元104的亮度独立可控，可以实现高动态范围(High-Dynamic Range，HDR)显示。当这种发光基板应用于显示装置中时，可以显著提升显示装置的对比度。
如图13所示，本公开各个实施例提供的发光基板还可以包括缓冲层112和第一绝缘层113。缓冲层112位于第一导电部105和第二导电部106所在的层与衬底101之间，第一绝缘层113位于第一导电部105和第二导电部106所在的层远离衬底101的一侧。缓冲层112可以用来减小在制备第一导电部105和第二导电部106时对衬底101造成的应力，从而可以避免衬底101发生弯曲变形；缓冲层112还可以避免衬底101中的杂质对第一导电部105和第二导电部106的导电性能的不利影响。缓冲层112可以是任意适当的材料，例如，可以是SiN。第一绝缘层113可以用来保护第一导电部105和第二导电部106以防其 被环境中的水、氧等氧化腐蚀。第一绝缘层113的材料可以是有机材料、无机材料或者有机材料和无机材料的结合，第一绝缘层113可以是单个膜层，也可以包括多个膜层。衬底101可以为塑料基板、硅基板、陶瓷基板、玻璃基板、石英基板等任意适当的基板，本公开的实施例对衬底101的材料不作限制。可选地，发光基板还可以包括第二绝缘层115，第二绝缘层115位于第一绝缘层113远离衬底101的一侧。第二绝缘层115的材料可以是有机材料、无机材料或者有机材料和无机材料的结合，第二绝缘层115可以是单个膜层，也可以包括多个膜层。
根据本公开的另一方面，提供了一种背光源，图14示出了背光源400的框图，该背光源400包括在前面任一个实施例中描述的发光基板。该背光源400可以作为显示装置中的背光源，为显示装置中的显示面板提供显示光源。当然，背光源400也可以用于任何其他需要光源的设备，本公开的实施例对背光源400的用途不做具体限定。
由于背光源400可以与前面各个实施例描述的发光基板具有基本相同的技术效果，因此，出于简洁的目的，此处不再重复描述背光源400的技术效果。
根据本公开的又一方面，提供了一种显示装置，图15示出了显示装置500的框图，该显示装置500包括在前面任一个实施例中描述的发光基板。在一些实施例中，该显示装置500可以为液晶显示装置，其包括液晶面板和设置在该液晶面板的非显示侧的背光源，背光源包括在前面任一个实施例中描述的发光基板，例如可以用于实现HDR调光以用于显示操作。该液晶显示装置可以具有更均匀的背光亮度，具有更好的显示对比度。显示装置500可以为任意适当的显示装置，包括但不限于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、电子书等任何具有显示功能的产品或部件。
由于显示装置500可以与前面各个实施例描述的发光基板具有基本相同的技术效果，因此，出于简洁的目的，此处不再重复描述显示装置500的技术效果。
根据本公开的再一方面，提供了一种制造发光基板的方法，图16示出了该方法600的流程图，该方法600适用于在前面任一个实施例中描述的发光基板。参考图2、图7和图16，方法600可以包括以下 步骤：
S601：提供衬底101。
S602：在衬底101上形成导电层，通过对导电层进行构图以同时形成第一导电部105和包括多个焊盘107和108的第二导电部106。
S603：在衬底101上安装多个驱动电路103和多个发光单元104以形成阵列布置的多个发光区域102，每个发光区域102包括驱动电路103和与该驱动电路103连接的至少一个发光单元104。第一导电部105配置为将电信号传输到每个发光区域102内的驱动电路103和至少一个发光单元104。
下面以一个具体的示例来更详细地描述方法600的各个步骤。
首先，提供衬底101。衬底101可以为塑料基板、硅基板、陶瓷基板、玻璃基板、石英基板等任意适当的基板，本公开的实施例对衬底101的材料不作限制。
然后，在衬底101上例如通过磁控溅射方法形成缓冲层112。缓冲层112可以用来减小在后续制备第一导电部105和第二导电部106时对衬底101造成的应力，从而可以避免衬底101发生弯曲变形；缓冲层112还可以避免衬底101中的杂质对后续形成的第一导电部105和第二导电部106的导电性能的不利影响。缓冲层112可以是任意适当的材料，例如，可以是SiN。
接着，在衬底101上通过磁控溅射方法或电镀方法形成导电层，通过对导电层进行构图以同时形成第一导电部105和第二导电部106。第一导电部105可以包括如上所述的驱动电压信号线VLEDL、选址信号线ADDRL、级联走线111、电源信号线VccL、数据驱动信号线DataL、公共电压信号线GNDL、反馈信号线FBL以及可选的屏蔽环GND ESD Ring。第二导电部106包括第一焊盘107和第二焊盘108，第一焊盘107用于安装驱动电路103，第二焊盘108用于安装发光单元104。由于单次磁控溅射的厚度一般不超过1μm，因此在制作超过1μm的导电层时，通常需要多次溅射来形成。。在一个示例中，第一导电部105和第二导电部106的形成过程可以表述如下：首先在缓冲层112上形成厚度例如为2um的Cu层，以用来传递各种电信号；然后在Cu层上形成厚度例如为0.6um的CuNi层，该CuNi层可以用于保护Cu层，防止电阻率低的Cu层表面暴露而发生氧化。在另一个示例中，第一导电 部105和第二导电部106的形成过程可以表述如下：首先在缓冲层112上形成厚度大约为
Figure PCTCN2021109837-appb-000003
的MoNb层，该MoNb层用来提高膜层与衬底101的粘附力；然后在MoNb层上形成Cu层，以用来传递各种电信号；最后在Cu层上形成厚度大约为
Figure PCTCN2021109837-appb-000004
的MoNb层，以保护中间的Cu层，防止电阻率低的中间Cu层表面暴露而发生氧化。在利用电镀法在衬底101上形成第一导电部105和第二导电部106时，可以先利用MoNiTi形成种子层，以提高后续电镀工艺中金属晶粒的成核密度，之后再通过电镀制作电阻率低的Cu层，之后再制作防氧化层，材料可以为MoNiTi。导电层可以经过清洗、涂覆、烘烤、光刻、显影、硬烤、刻蚀、剥离等工艺后，形成第一导电部105和第二导电部106。制备位于同一层的第一导电部105和第二导电部106仅需要使用两张掩膜版，相比于相关技术中至少需要三张掩膜版来形成位于不同层的导电结构，可以减少所需掩膜版的数量，简化工艺制程，降低生产成本。
然后，在第一导电部105和第二导电部106所在的层远离衬底101的一侧通过磁控溅射方法形成第一绝缘层113。第一绝缘层113可以用来保护第一导电部105和第二导电部106以防止其被环境中的水、氧等氧化腐蚀。第一绝缘层113的材料可以是有机材料、无机材料或者有机材料和无机材料的结合，第一绝缘层113可以是单个膜层，也可以包括多个膜层。
可选地，还可以在第一绝缘层113远离衬底101的一侧涂覆第二绝缘膜层，通过对该第二绝缘膜层进行固化、曝光、显影、刻蚀等若干处理，形成第二绝缘层115。第二绝缘层115的材料可以是有机材料、无机材料或者有机材料和无机材料的结合，第二绝缘层115可以是单个膜层，也可以包括多个膜层。当发光基板上形成有第二绝缘层115时，对第二绝缘层115和第一绝缘层113进行刻蚀以形成多个过孔。
最后，将发光基板切割成规定的外形，使驱动电路103和发光单元104分别通过上述多个过孔与第二导电部103的第一焊盘107和第二焊盘108电连接，以将驱动电路103和发光单元104安装在相应的焊盘上。第一导电部105的各条信号线连接到绑定区处的柔性电路板110，从而实现驱动电路103与柔性电路板110的电连接，最终得到所需的发光基板。
该方法600实现的技术效果可以参考前面各个实施例描述的发光 基板的技术效果，因此，出于简洁的目的，此处不再重复描述方法600的技术效果。
在本公开的描述中，术语“上”、“下”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开而不是要求本公开必须以特定的方位构造和操作，因此不能理解为对本公开的限制。
在本说明书的描述中，参考术语“一个实施例”、“另一个实施例”等的描述意指结合该实施例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。另外，需要说明的是，本说明书中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
如本领域技术人员将理解的，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是这并非要求或者暗示必须按照该特定顺序来执行这些步骤，除非上下文另有明确说明。附加的或可替换的，可以将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行。此外，在步骤之间可以插入其他方法步骤。插入的步骤可以表示诸如本文所描述的方法的改进，或者可以与该方法无关。此外，在下一步骤开始之前，给定步骤可能尚未完全完成。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此。任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (28)

  1. 一种发光基板，包括：
    衬底，包括阵列布置的多个发光区域，所述多个发光区域中的每一个包括驱动电路和与所述驱动电路连接的至少一个发光单元；
    第一导电部，位于所述衬底上且与每个发光区域内的所述驱动电路和所述至少一个发光单元连接；以及
    第二导电部，位于所述衬底上且包括多个焊盘，
    其中，所述第一导电部和所述第二导电部位于同一层。
  2. 根据权利要求1所述的发光基板，其中，所述多个发光区域沿第一方向布置成M行且沿与所述第一方向交叉的第二方向布置成N列，M和N均为大于等于1的正整数，
    所述第一导电部包括沿所述第一方向延伸的N条驱动电压信号线和N条公共电压信号线，每列发光区域包括一条驱动电压信号线和一条公共电压信号线，
    在每列发光区域内，所述驱动电压信号线与该列发光区域内的每个发光单元的第一端连接，所述公共电压信号线与该列发光区域内的每个驱动电路连接，
    在每列发光区域内，所述驱动电压信号线、所述发光单元、所述驱动电路、以及所述公共电压信号线沿着所述第二方向依次排列。
  3. 根据权利要求2所述的发光基板，其中，所述驱动电压信号线、所述发光单元、所述驱动电路、以及所述公共电压信号线在所述衬底上的正投影彼此不交叠。
  4. 根据权利要求2或3所述的发光基板，其中，每个驱动电路包括阵列布置的多个端子，所述多个端子沿所述第二方向排列成至少两列，
    所述多个端子包括至少一个输出端子和至少一个公共电压端子，所述至少一个输出端子和所述至少一个公共电压端子位于所述多个端子的不同列中，
    在每列发光区域内，每个驱动电路的所述至少一个输出端子与和该驱动电路连接的所述至少一个发光单元的第二端一一对应连接，每个驱动电路的所述至少一个公共电压端子与该列发光区域内的所述公 共电压信号线连接。
  5. 根据权利要求4所述的发光基板，其中，
    所述多个端子还包括地址端子、中继端子以及电源端子，
    每列发光区域内的各个驱动电路依次级联，第i级驱动电路的所述地址端子位于所述第i级驱动电路的靠近第i-1级驱动电路的一侧，第i级驱动电路的所述中继端子位于所述第i级驱动电路的靠近第i+1级驱动电路的一侧，1＜i＜M且i为正整数，
    所述地址端子配置为接收地址信号，所述中继端子配置为输出中继信号，所述电源端子配置为接收电源电压信号。
  6. 根据权利要求5所述的发光基板，其中，所述第一导电部的延伸方向平行于所述驱动电路的级联方向。
  7. 根据权利要求5所述的发光基板，其中，所述驱动电路的多个端子沿所述第二方向布置成第一列和第二列，在每列发光区域内，所述驱动电路的第一列端子位于所述驱动电路的邻近所述驱动电压信号线的一侧，所述驱动电路的第二列端子位于所述驱动电路的邻近所述公共电压信号线的一侧。
  8. 根据权利要求7所述的发光基板，其中，所述第一导电部还包括N条电源信号线，每列发光区域包括一条电源信号线，每条电源信号线包括主体部分和第一连接部，所述电源信号线的主体部分沿所述第一方向延伸，
    在每列发光区域内，所述电源信号线通过所述第一连接部与该列发光区域内的每个驱动电路的所述电源端子连接，并且所述第一列端子在所述衬底上的正投影与所述第二列端子在所述衬底上的正投影分别位于所述电源信号线在所述衬底上的正投影的两侧。
  9. 根据权利要求8所述的发光基板，其中，所述第一导电部还包括沿所述第一方向延伸的N条选址信号线，每列发光区域包括一条选址信号线，在每列发光区域内，所述选址信号线与第一级驱动电路的所述地址端子连接。
  10. 根据权利要求9所述的发光基板，其中，所述第一导电部还包括沿所述第一方向延伸的级联走线，所述级联走线位于每列发光区域内的相邻两个级联的驱动电路之间，并且第i级驱动电路的所述中继端子经由所述级联走线与第i+1级驱动电路的所述地址端子连接。
  11. 根据权利要求10所述的发光基板，其中，所述第一导电部还包括沿所述第一方向延伸的N条反馈信号线，每列发光区域包括一条反馈信号线，在每列发光区域内，所述反馈信号线与最后一级驱动电路的所述中继端子连接，并且所述反馈信号线至少部分地位于该列发光区域内的所述公共电压信号线远离所述驱动电路的一侧。
  12. 根据权利要求11所述的发光基板，其中，所述驱动电压信号线、所述选址信号线、所述级联走线、所述电源信号线、所述公共电压信号线、以及所述反馈信号线在所述衬底上的正投影彼此不交叠。
  13. 根据权利要求8-12中任一项所述的发光基板，其中，所述驱动电路的所述多个端子包括所述地址端子、所述电源端子、所述公共电压端子、以及所述输出端子，
    所述第一列端子包括所述输出端子和所述地址端子，所述第二列端子包括所述公共电压端子和所述电源端子。
  14. 根据权利要求13所述的发光基板，其中，所述驱动电路的所述输出端子和所述中继端子为同一个端子，所述驱动电路配置为，在第一时段内通过所述输出端子输出中继信号以作为与该驱动电路级联的下一级驱动电路的所述地址信号，在第二时段内通过所述输出端子向与该驱动电路连接的所述至少一个发光单元提供驱动信号。
  15. 根据权利要求8-12中任一项所述的发光基板，其中，所述驱动电路的所述多个端子还包括数据端子，所述数据端子与所述电源端子位于所述多个端子的不同列中。
  16. 根据权利要求15所述的发光基板，其中，所述驱动电路的输出端子的数量为多个且所述公共电压端子的数量为至少一个，
    所述第一列端子包括所述电源端子和所述多个输出端子，所述第二列端子包括所述地址端子、所述中继端子、所述数据端子以及所述至少一个公共电压端子。
  17. 根据权利要求16所述的发光基板，其中，所述第一导电部还包括N条数据驱动信号线，每列发光区域包括一条数据驱动信号线，每条数据驱动信号线包括主体部分和第二连接部，所述数据驱动信号线的主体部分沿所述第一方向延伸，
    在每列发光区域内，所述数据驱动信号线通过所述第二连接部与该列发光区域内的每个驱动电路的所述数据端子连接，并且所述第一 列端子在所述衬底上的正投影与所述第二列端子在所述衬底上的正投影分别位于所述数据驱动信号线在所述衬底上的正投影的两侧，并且所述数据驱动信号线在所述衬底上的正投影与所述电源信号线在所述衬底上的正投影不交叠。
  18. 根据权利要求16所述的发光基板，其中，所述驱动电路的所述多个输出端子与和该驱动电路连接的多个发光单元的第二端一一对应连接，
    所述驱动电路配置为，在第一时段内通过所述中继端子输出中继信号以作为与该驱动电路级联的下一级驱动电路的所述地址信号，在第二时段内通过所述多个输出端子分别向所述多个发光单元提供驱动信号。
  19. 根据权利要求2-18中任一项所述的发光基板，其中，所述驱动电压信号线和相邻的其他信号线之间的间距大于等于0.2mm。
  20. 根据权利要求2-19中任一项所述的发光基板，还包括多个柔性电路板和扇出区，
    其中，所述第一导电部的各条信号线均包括直线部分和弯折部分，所述各条信号线的弯折部分位于所述扇出区内，并且所述各条信号线通过其弯折部分与所述多个柔性电路板连接，并且，
    其中，每条信号线的弯折部分沿所述第二方向的宽度小于相邻两列发光区域沿所述第二方向的宽度。
  21. 根据权利要求20所述的发光基板，其中，每条信号线的所述直线部分和所述弯折部分之间的夹角为80°～100°。
  22. 根据权利要求1-21中任一项所述的发光基板，其中，所述第一导电部和所述第二导电部的材料包括铜。
  23. 根据权利要求1-22中任一项所述的发光基板，其中，每个发光单元包括彼此连接的多个发光元件，所述多个发光元件中的每一个包括次毫米发光二极管或微型发光二极管。
  24. 根据权利要求2-23中任一项所述的发光基板，还包括屏蔽环，其中，所述屏蔽环围绕在所述多个发光区域的外围，并且所述屏蔽环接收的电信号与所述公共电压信号线接收的电信号相同。
  25. 根据权利要求1-24中任一项所述的发光基板，还包括缓冲层和绝缘层，其中，
    所述缓冲层位于所述第一导电部和所述第二导电部所在的层与所述衬底之间，
    所述绝缘层位于所述第一导电部和所述第二导电部所在的层远离所述衬底的一侧。
  26. 一种背光源，包括根据权利要求1-25中任一项所述的发光基板。
  27. 一种显示装置，包括根据权利要求1-25中任一项所述的发光基板。
  28. 一种制造发光基板的方法，包括：
    提供衬底；
    在所述衬底上形成导电层，通过对所述导电层进行构图以同时形成第一导电部和包括多个焊盘的第二导电部；以及
    在所述衬底上安装多个驱动电路和多个发光单元以形成阵列布置的多个发光区域，所述多个发光区域中的每一个包括驱动电路和与该驱动电路连接的至少一个发光单元，
    其中，所述第一导电部与每个发光区域内的所述驱动电路和所述至少一个发光单元连接。
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CN101038931A (zh) * 2006-03-14 2007-09-19 精工爱普生株式会社 有机场致发光装置及电子设备
CN110061035A (zh) * 2019-04-24 2019-07-26 合肥京东方卓印科技有限公司 阵列基板及显示装置
CN110265454A (zh) * 2019-06-25 2019-09-20 上海天马微电子有限公司 一种显示面板、其制作方法及显示装置
CN111968566A (zh) * 2020-08-27 2020-11-20 上海天马微电子有限公司 发光面板及其驱动方法、制作方法、显示装置
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CN101038931A (zh) * 2006-03-14 2007-09-19 精工爱普生株式会社 有机场致发光装置及电子设备
CN112868100A (zh) * 2018-10-12 2021-05-28 三星显示有限公司 光单元及包括该光单元的显示装置
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