WO2022266810A1 - 驱动器电路及其驱动方法、阵列基板和显示装置 - Google Patents

驱动器电路及其驱动方法、阵列基板和显示装置 Download PDF

Info

Publication number
WO2022266810A1
WO2022266810A1 PCT/CN2021/101304 CN2021101304W WO2022266810A1 WO 2022266810 A1 WO2022266810 A1 WO 2022266810A1 CN 2021101304 W CN2021101304 W CN 2021101304W WO 2022266810 A1 WO2022266810 A1 WO 2022266810A1
Authority
WO
WIPO (PCT)
Prior art keywords
driver circuit
pin
driving
address
wiring
Prior art date
Application number
PCT/CN2021/101304
Other languages
English (en)
French (fr)
Inventor
尹凯民
郝卫
时凌云
黄文杰
王飞飞
苏文刚
石蕊
商兴策
张峻玮
段涛涛
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP21946312.2A priority Critical patent/EP4224461A4/en
Priority to CN202180001566.4A priority patent/CN115968493A/zh
Priority to PCT/CN2021/101304 priority patent/WO2022266810A1/zh
Priority to US18/016,716 priority patent/US20230282172A1/en
Priority to JP2023524803A priority patent/JP2024525257A/ja
Priority to TW110136420A priority patent/TWI838650B/zh
Publication of WO2022266810A1 publication Critical patent/WO2022266810A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3283—Details of drivers for data electrodes in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G09G3/342—Control of illumination source using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines
    • G09G3/3426—Control of illumination source using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines the different display panel areas being distributed in two dimensions, e.g. matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/064—Adjustment of display parameters for control of overall brightness by time modulation of the brightness of the illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/0646—Modulation of illumination source brightness and image signal correlated to each other
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/026—Arrangements or methods related to booting a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/027—Arrangements or methods related to powering off a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G09G2330/045—Protection against panel overheating
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present disclosure relates to the field of display technology, in particular, to a driver circuit and its driving method, an array substrate and a display device.
  • an LED (Light Emitting Diode) array substrate with a local dimming function may be used as a backlight source.
  • the driver chip By integrating the driver chip on the LED array substrate, the problems of high control complexity and discontinuous and easy flickering of LED array light caused by the traditional passive row-column scanning control method can be overcome.
  • the purpose of the present disclosure is to overcome the shortcomings of the above-mentioned prior art, provide a driver circuit and its driving method, an array substrate and a display device, and reduce the usage of the driver circuit on the array substrate.
  • a driver circuit including a logic control module, a data pin and at least two output pins; the data pin is used to receive driving data; the logic control module is configured to The driving data generates a driving control signal corresponding to each of the output pins, and the driving control signal is used to control the current flowing through the corresponding output pin.
  • the driving data includes address information and driving information
  • the logic control module is further configured to, when the address information of the driving data matches the address information of the driver circuit, acquire the driving information of the driving data, and generate the driving information according to the driving information of the driving data. Drive control signal.
  • the driver circuit further includes an address pin and a relay pin
  • the address pin is capable of receiving an address signal
  • the logic control module is further configured to configure the address information of the driver circuit according to the address signal, and generate a relay signal; the relay signal can be used as an address signal of a subsequent driver circuit;
  • the relay pin is used to output the relay signal.
  • the number of the output pins is four; the driver circuit further includes a ground pin and a chip power pin; the ground pin is used to apply a ground voltage to the driver circuit ; The chip power supply pin is used to load the driver circuit with a chip power supply voltage for driving the driver circuit to work;
  • each pin of the driver circuit is arranged into two pin columns, and each pin column includes a plurality of pins arranged in a straight line; at least one of the pin columns includes five pins;
  • the four output pins are all located at the ends of the pin columns; the chip power pins and the data pins are located in different pin columns; the address pins and the relay Pins are in the same pin column as described.
  • a method for driving a driver circuit wherein the driver circuit includes at least two output pins; the method for driving the driver circuit includes:
  • drive data is received, and a drive control signal corresponding to each of the output pins is generated according to the drive data, and the drive control signal is used to control the current flowing through the corresponding output pin.
  • the driving data includes address information and driving information; the driving method of the driver circuit further includes:
  • an address signal is received, address information of the driver circuit is configured according to the address signal, and a relay signal is generated and output; the relay signal can be used as an address signal of a subsequent driver circuit;
  • Generating a drive control signal corresponding to each of the output pins according to the drive data includes:
  • the driving information of the driving data matches the address information of the driver circuit, the driving information of the driving data is obtained, and the driving control signal is generated according to the driving information of the driving data.
  • an array substrate including a plurality of device control regions arranged in an array; in any one of the device control regions, the array substrate is provided with the above-mentioned driver circuit, and is provided with a Each of the output pins of the driver circuit is connected to a device unit in one-to-one correspondence; any one of the device units includes a functional element or a plurality of electrically connected functional elements.
  • the device control regions are arranged into a plurality of device control region columns; any one of the device control region columns includes a plurality of device control regions arranged in sequence along the column direction;
  • the array substrate is provided with device power wiring and driving data wiring extending along the column direction; one end of the device unit is electrically connected to the device power wiring, and the other One end is electrically connected to the corresponding output pin; the data pin is electrically connected to the driving data wiring.
  • each of the driver circuits located in the same column of the device control area is cascaded in sequence; the driver circuit further includes an address pin and a relay pin;
  • the array substrate is provided with a plurality of address wirings corresponding to each of the driver circuits, and each of the address wirings extends along the column direction;
  • the address pins of the driver circuit are electrically connected to the corresponding address wires, and the relay pins of the upper-level driver circuit are electrically connected to the corresponding address wires of the lower-level driver circuit.
  • the array substrate is further provided with chip power traces and ground voltage traces extending along the column direction;
  • the driver circuit also includes a chip power supply pin and a ground pin, and the chip power supply pin is used to load the driver circuit with a chip power supply voltage for driving the driver circuit;
  • the chip power supply pin is electrically connected;
  • the ground pin is used to apply a ground voltage to the driver circuit, and the ground pin is electrically connected to the ground voltage wiring.
  • the device units are arranged into two device unit columns, and any one of the device unit columns includes a plurality of devices arranged in sequence along the column direction unit;
  • the number of the device power supply traces is two; the two device power supply traces are respectively located on both sides of the ground voltage trace, and are connected to the two devices One-to-one correspondence setting of cell columns;
  • Each of the device units in the device unit column is electrically connected to the corresponding device power supply wiring.
  • the address wiring, the driving data wiring and the chip power wiring are all located between the device power wiring and the between the ground voltage traces.
  • the array substrate in at least one of the device control area columns, is further provided with feedback wiring; in the device control area column, the relay of the last stage of the driver circuit A pin electrically connected to the feedback wiring; the feedback wiring is located between the device power supply wiring and the ground voltage wiring.
  • two adjacent device power supply lines are connected to each other to form one line.
  • the array substrate includes a base substrate, a driving circuit layer, and a device layer that are sequentially stacked;
  • the driving circuit layer includes a driving wiring layer, a first insulating layer, and a metal wiring layer sequentially stacked on the base substrate; the thickness of the driving wiring layer is greater than the thickness of the metal wiring layer;
  • the ground voltage wiring, the device power wiring, the chip power wiring, the driving data wiring and the address wiring are located in the driving wiring layer;
  • the metal wiring layer is provided with device pads, chip pads, and wiring lines; the functional element and the driver circuit are located on the device layer; the functional element is bound and connected to the device pad, and the The driver circuit is bound and connected to the chip pad, and the device pad, the chip pad and the driving wiring layer are electrically connected through the wiring.
  • a display device including the above-mentioned array substrate.
  • FIG. 1 is a principle schematic diagram of an array substrate at a local position in an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of pin arrangement of a driver circuit in an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a driver circuit in an embodiment of the present disclosure.
  • FIG. 4 is a timing diagram of a driver circuit in an embodiment of the present disclosure.
  • FIG. 5 is a timing diagram of cascaded driver circuits in an embodiment of the present disclosure.
  • FIG. 6 is a schematic flowchart of a driving method of a driver circuit in an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a driving process of an array substrate in an embodiment of the present disclosure.
  • Fig. 8 is a schematic structural diagram of a control area in an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of two control areas adjacent to the binding area in an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of an array substrate in an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of two control regions adjacent to the binding region in an embodiment of the present disclosure, and the device layer is not shown in FIG. 11 .
  • FIG. 12 is a schematic diagram of a driver circuit in an implementation manner of the present disclosure.
  • Fig. 13 is a schematic diagram of a control circuit in an embodiment of the present disclosure.
  • AA device control area
  • BB device control area column
  • MIC driver circuit
  • OUTP output pin
  • Out1 first output pin
  • Out4 Fourth output pin
  • DataP data pin
  • DataL drive data trace
  • VLEDL device power trace
  • Di_in address pin
  • Di_out relay pin
  • ADDRL address trace
  • FBL feedback trace
  • GNDP ground pin
  • GNDL ground voltage trace
  • VCCP chip power pin
  • VCCL chip power trace
  • CTR logic control module
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • a structure When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is “directly” placed on another structure, or that a structure is “indirectly” placed on another structure through another structure. other structures.
  • FIG. 1 is a schematic diagram of the principle of an array substrate at a local position.
  • the array substrate provided by the present disclosure includes a plurality of device control areas AA arranged in an array; in any device control area AA, the array substrate is provided with a driver circuit MIC and a device unit EC driven by the driver circuit MIC.
  • any device unit EC may include one functional element or multiple functional elements FE that are electrically connected.
  • FIG. 8 any device unit EC may include one functional element or multiple functional elements FE that are electrically connected.
  • the device control area AA is arranged into a plurality of device control area columns BB; any one device control area column BB includes a plurality of device control area AA arranged in sequence along the column direction. Further, in one column BB of the device control area, each driver circuit MIC may be linearly arranged along the column direction.
  • FIG. 1 is only used to illustrate the electrical connection relationship between the driver circuit MIC, the device unit EC and various wires.
  • the size of the driver circuit MIC, the device unit EC and each trace is not drawn to scale, and the driver circuit MIC, the device unit EC and each trace The distance between The relative positional relationship is not shown according to the actual position.
  • the driver circuit MIC may be an integrated circuit, especially a packaged chip with pins.
  • the functional element may be a current-driven electronic element, such as a heating element, a light emitting element, a sound emitting element, etc., or an electronic element that realizes a sensing function, such as a photosensitive element, a heat sensitive element, an acoustic electric element, etc. Transducer elements, etc.
  • Any device unit EC may include one type of functional element, or may include multiple different electronic elements. The quantity, type, relative position and electrical connection mode of the functional elements included in any two device units EC may be the same or different.
  • each device unit EC may be distributed in an array, so as to improve the uniformity of the distribution of the device units EC and the uniformity of the array substrate.
  • the functional elements in the device unit EC are the same functional element, for example, they are all light emitting elements.
  • various functional elements are distributed in an array, thereby ensuring the uniformity of distribution of the functional elements on the entire array substrate, and further improving the uniformity of the array substrate.
  • the number, type, relative position and electrical connection of the functional elements are exactly the same, for example, they are all light emitting elements; thus, each device unit EC is the same, which facilitates the driving and debugging of the array substrate.
  • the functional elements in the device unit EC can be light-emitting elements, such as LED (light-emitting diode), Micro LED (micro light-emitting diode), mini LED (mini light-emitting diode), OLED (organic electroluminescent diode) ), QD-OLED (quantum dot-organic electroluminescent diode), QLED (quantum dot light-emitting diode), PLED (organic polymer electroluminescent diode), etc.
  • the array substrate can emit light under the driving of the driver circuit MIC, and can be applied in display devices, lighting devices and other devices.
  • each functional element in the device unit EC is a light-emitting element, and each light-emitting element on the array substrate is distributed in an array;
  • the display device may be a liquid crystal display device, which includes a laminated liquid crystal display module and a backlight module , the array substrate can be used as a backlight source of a backlight module.
  • each device unit EC can work independently under the drive of the driver circuit MIC, so that each device unit EC can emit light independently; thus, the display device can realize local dimming (local dimming), and realize HDR (High -Dynamic Range) effect to improve the display quality of the display device.
  • the number of functional elements and the way of electrical connection are the same. In this way, the uniformity of distribution of the light-emitting elements on the array substrate can be ensured, which is conducive to improving the uniformity of light emission of the array substrate and reducing the difficulty of debugging the backlight module.
  • the display device may be a Micro LED display device.
  • light-emitting elements such as Micro LEDs, LEDs, etc.
  • the light emitting elements may be light emitting elements capable of emitting light of the same color, for example, all may be blue LEDs, red LEDs, green LEDs or yellow LEDs.
  • the display device may be a monochrome display device, which may be a display device such as an instrument dial, a signal indicating screen, or the like.
  • the light-emitting element may include a plurality of light-emitting elements of different colors, for example, may include at least two of red LEDs, green LEDs, blue LEDs, yellow LEDs, etc., and the light-emitting elements of different colors may be each independently controlled. In this way, the display device can perform color display by mixing light.
  • each functional element on the array substrate is arranged in an array at equal intervals in a row and column direction.
  • each functional element may be arranged in a plurality of element rows, each element row is arranged at equal intervals along the column direction, and each element row includes a plurality of functional elements arranged at equal intervals along the row direction.
  • Each functional element can also be arranged into a plurality of element columns, each element column is arranged at equal intervals along the row direction, and each element column includes a plurality of functional elements arranged at equal intervals along the column direction. In this way, the uniformity of distribution of functional elements on the array substrate can be further improved.
  • each driver circuit MIC is distributed in an array.
  • the difficulty of designing and manufacturing the array substrate can be reduced, the difficulty of debugging the array substrate can be reduced, and the cost of the array substrate and the display device can be reduced.
  • each driver circuit MIC is distributed in an array. Further, the relative position of each driver circuit MIC with respect to the device unit EC driven by it may be the same. In other embodiments, referring to FIG. 9 , the array substrate may include adjacent first regions C1 and second regions C2 .
  • the driver circuit MICs located in the first area are distributed in an array; the driver circuits MICs located in the second area are distributed in an array; the driver circuits MICs are not distributed in an array in the first area and the second area as a whole.
  • the relative position of the driver circuit MIC in the first area C1 with respect to the device unit EC it drives may be different from the relative position of the driver circuit MIC in the second area C2 with respect to the device unit EC it drives.
  • the array substrate has a bonding area, and a circuit board bonding pad for bonding connection with an external circuit (such as a circuit board, a flexible circuit board, a chip-on-chip, etc.) is arranged in the bonding area.
  • the second area may be located at an end of the array substrate close to the binding area, and the first area may be located at a side of the second area away from the binding area.
  • the driver circuit MIC has two output pins OUTP (such as Out1, Out2, etc.) to drive two device units EC.
  • the array substrate is provided with a fan-out area and a binding area, and the fan-out area has a fan-out line electrically connected to the bonding pad of the circuit board in the binding area, and the fan-out line is also connected to the driver circuit MIC and the device unit EC.
  • Drive traces are electrically connected.
  • each device control area AA closest to the binding area forms the second area C2, and the remaining control areas AA may form the first area C1.
  • the second area C2 may overlap with the fan-out area, especially each device unit EC in the second area C2 may overlap with the fan-out area.
  • the driver circuit MIC may be located on a side of the two device units EC away from the bonding area.
  • the driver circuit MIC may be located on a side of the two device units EC close to the bonding area.
  • the array substrate of the present disclosure is integrated with a driver circuit for driving device units, which can simplify the external circuit for driving the array substrate and its control method, and facilitate miniaturization of the external circuit.
  • this can reduce the volume of the integrated circuit in the external circuit and thus reduce the cost of the integrated circuit; on the other hand, it can reduce the area of the circuit board in the external circuit.
  • the driver circuit MIC includes a logic control module CTR, a data pin DataP and at least two output pins OUTP; the data pin DataP is used to receive the driving data Data; the logic control module CTR is configured to drive The data Data generates drive control signals corresponding to each output pin OUTP one by one, and the drive control signal is used to control the current flowing through the corresponding output pin OUTP.
  • the device units EC on the array substrate are arranged in one-to-one correspondence with each output pin OUTP of the driver circuit MIC. On the entire array substrate, each device unit EC is arranged in one-to-one correspondence with each output pin OUTP.
  • the driver circuit MIC can be driven by the following driving method: in the device control stage, the driving data Data is received, and the driving control signal corresponding to each output pin OUTP is generated according to the driving data Data, and the driving control signal is used to control the flow current through the corresponding output pin OUTP.
  • the logic control module CTR of the driver circuit MIC can control the current flowing through the output pin OUTP according to the driving data Data, and then control the driving current flowing through the device unit EC electrically connected to the output pin OUTP, so as to realize the control of the device Control and drive of the unit EC.
  • the driver circuit MIC of the present disclosure can simultaneously drive at least two device units EC, thereby reducing the number of driver circuits MIC in the array substrate and reducing the cost of the array substrate. Not only that, because the amount of MIC used in the driver circuit is reduced, it can also reduce the difficulty of preparing the array substrate, reduce the influence of the driver circuit bonding yield on the yield of the array substrate, and improve the yield of the array substrate.
  • the multiple driver MICs can simultaneously provide driving signals to multiple device units EC connected to them, that is, multiple device units EC driven by different driver MICs can work simultaneously. It can be understood that, in order to ensure the stability of the driver circuit MIC and prolong the service life of the driver circuit MIC, the "simultaneous driving" and “simultaneous operation” mentioned in this disclosure may have nanosecond order in time.
  • a driver circuit MIC is provided with four output pins OUTP, that is, a first output pin Out1, a second output pin Out2, and a third output pin Out3 are provided. , the fourth output pin Out4.
  • the driver circuit MIC of the present disclosure can simultaneously drive four device units EC; compared with the scheme in which one driver circuit MIC drives one device unit EC, the number of driver circuits MIC can be reduced to 1/4, greatly reducing the driver circuit MIC. usage, thereby reducing the cost of the array substrate.
  • the driver circuit MIC of the present disclosure has a slightly larger volume than the driver circuit with only one output pin, the present disclosure can greatly reduce the usage of the driver circuit MIC, and thus can be used in the driver circuit Significant improvements have been achieved in the reduction of the overall area ratio of the MIC, the improvement of the MIC binding efficiency of the driver circuit, and the improvement of the yield rate of the array substrate.
  • the driver circuit MIC of the present disclosure has four output pins OUTP, and its area is twice that of the driver circuit MIC with only one output pin OUTP; however, the present disclosure
  • the amount of the driver circuit MIC can be reduced to 1/4, thereby reducing the area ratio of the driver circuit MIC in the array substrate of the present disclosure to 1/2 (relative to an array substrate in which one driver circuit MIC drives one device unit EC) .
  • the array substrate is provided with device power supply traces VLEDL and drive data traces DataL extending along the column direction; one end of the device unit EC is electrically connected to the device power supply trace VLEDL, and the other end It is electrically connected to the corresponding output pin OUTP (for example, any one of Out1-Out4); the data pin DataP is electrically connected to the driving data line DataL.
  • the device cells EC are arranged into two device cell columns, and any device cell column includes a plurality of device units EC arranged in sequence along the column direction; in any device control area column BB Among them, the number of device power traces VLEDL is two; the two device power traces VLEDL are set in one-to-one correspondence with the two device cell columns; The line VLEDL (that is, the device power supply line VLEDL corresponding to the device unit EC) is connected.
  • two adjacent device power supply lines VLEDL in two adjacent control area columns, two adjacent device power supply lines VLEDL can be connected to each other to form one line, that is, two adjacent device power supply lines VLEDL Combined into one device supply trace VLEDL'.
  • the merged device power supply line VLEDL' can be arranged corresponding to the two device cell columns, and the device units EC on the two device cell columns are all connected to the merged device power supply line VLEDL'.
  • the width of the merged device power supply trace VLEDL' may be greater than that of the device power trace VLEDL connected to the device cell column closest to the edge of the array substrate, and the merged device power supply trace VLEDL' may include a hollow portion; of course, the merged The width of the device power supply trace VLEDL' may also be the same as that of the device power supply trace VLEDL connected to the device unit column closest to the edge of the array substrate.
  • the external circuit (such as a circuit board) can provide the driving data Data to the driving data line DataL, and then drive the data line DataL to transmit the driving data Data to the data pin DataP; the external circuit can also pass the device power line Line VLEDL supplies device cell EC with device supply voltage VLED.
  • the driver circuit MIC includes a ground pin GNDP, and the ground pin GNDP is used for applying a ground voltage GND to the driver circuit MIC.
  • the array substrate is provided with a ground voltage trace GNDL extending along the column direction, and the ground pin GNDP is electrically connected to the ground voltage trace GNDL; the external circuit can load the ground voltage GND to the ground voltage trace GNDL , and then load the ground voltage GND to the driver circuit MIC.
  • the device unit EC is equivalent to being connected between the device power supply line VLEDL and the ground voltage line GNDL; the logic control module CTR controls the conduction or cut-off of the current path of the device unit EC through the output pin OUTP, and then controls the current path through the device unit EC and the current at the output pin OUTP.
  • any device control area column BB there are two device power supply lines VLEDL; the two device power supply lines VLEDL are respectively located on both sides of the ground voltage line GNDL.
  • the driver circuit MIC may be arranged overlapping the ground voltage trace GNDL, so as to provide electromagnetic shielding for the driver circuit MIC by using the ground voltage GND applied on the ground voltage trace GNDL.
  • the logic control module CTR may include a control module CLM and a modulation module (such as PWMM1 ⁇ PWMM4 in FIG. 3 ) provided in one-to-one correspondence with each output pin OUTP.
  • Each modulation module is electrically connected to the corresponding output pin OUTP.
  • the control module CLM is configured to generate a drive control signal corresponding to each modulation module according to the drive data Data, and the drive control signal is used to control the on or off of the corresponding modulation module, and then control the output pin OUTP and the ground voltage wiring The electrical path or electrical disconnection before the GNDL realizes the control of the device unit EC.
  • the drive control signal can make the signal flowing through the modulation module (and the output pin OUTP connected to the modulation module, the device unit EC) be a pulse width modulation signal through the control of the modulation module; the drive control The signal can be used to modulate the pulse width modulation signal, such as adjusting the duty ratio of the pulse width modulation signal and other factors, thereby controlling the average current flowing through the output pin OUTP and the device unit EC.
  • the driver circuit MIC includes four output pins OUTP, which are respectively the first output pin Out1 to the fourth output pin Out4; the logic control
  • the module CTR includes four modulation modules, namely, the first modulation module PWMM1 , the second modulation module PWMM2 , the third modulation module PWMM3 and the fourth modulation module PWMM4 .
  • the first output pin Out1 to the fourth output pin Out4 are connected to the first modulation module PWMM1 to the fourth modulation module PWMM4 in a one-to-one correspondence.
  • the control module CLM is used to generate the first drive control signal, the second drive control signal, the third drive control signal, and the fourth drive control signal according to the drive data Data, and transmit them to the first modulation module PWMM1, the second modulation module PWMM2, The third modulation module PWMM3 and the fourth modulation module PWMM4.
  • the first modulation module PWMM1 is electrically connected to the first output pin Out1, and can be turned on or off under the control of the first drive control signal, so that the first output pin Out1 and the ground voltage line GNDL are turned on or off. open.
  • the first modulation module PWMM1 is turned on, the ground voltage trace GNDL, the first output pin Out1, the device unit EC electrically connected to the first output pin Out1, and the device power supply trace VLEDL form a signal loop, and the device unit EC works ;
  • the first modulation module PWMM1 is cut off, the above signal loop is disconnected, and the device unit EC does not work.
  • the first modulation module PWMM1 can modulate the current flowing through the device unit EC under the control of the first driving control signal, so that the current flowing through the device unit EC appears as a pulse width modulation signal.
  • the first modulation module PWMM1 can modulate factors such as the duty cycle of the pulse width modulation signal flowing through the device unit EC according to the first driving control signal, and then control the working state of the device unit EC.
  • the device unit EC contains LEDs
  • the duty ratio of the pulse width modulation signal the total light-emitting time of the LEDs in a display frame can be increased, thereby increasing the total light-emitting brightness of the LEDs in the display frame, so that the array substrate can be used in this display frame.
  • the brightness of the area increases; on the contrary, by reducing the duty cycle of the pulse width modulation signal, the total light-emitting time of the LED in a display frame can be reduced, and the total light-emitting brightness of the LED in the display frame can be reduced, so that the array substrate can be used in this display frame.
  • the brightness of the area is reduced.
  • the second modulation module PWMM2 is electrically connected to the second output pin Out2, and can be turned on or off under the control of the second drive control signal, so that the current flows through the device unit EC connected to the second output pin Out2 The current appears as a pulse width modulated signal.
  • the third modulation module PWMM3 is electrically connected to the third output pin Out3, and can be turned on or off under the control of the third drive control signal, so that the current flowing through the device unit EC connected to the third output pin Out3 presents It is a pulse width modulated signal.
  • the fourth modulation module PWMM4 is electrically connected to the fourth output pin Out4, and can be turned on or off under the control of the fourth drive control signal, so that the current flowing through the device unit EC connected to the fourth output pin Out4 presents It is a pulse width modulated signal.
  • the first modulation module PWMM1 to the fourth modulation module PWMM4 may be switching elements, such as transistors such as MOS (Metal-Oxide Semiconductor Field Effect Transistor) and TFT (Thin Film Transistor);
  • the first driving control signal to the fourth driving control signal may be pulse width modulation signals, and the switching elements are turned on or off under the control of the pulse width modulation signals.
  • the first modulation module PWMM1 to the fourth modulation module PWMM4 may be electrically connected to the control module CLM through the data bus DB, or may be electrically connected to the control module through data wiring respectively, or Or achieve electrical connection with the control module in other ways, which is not specifically limited in the present disclosure.
  • the control module CLM may include a data link (Data Link) circuit and a control logic module (Control Logic) circuit, and the data link circuit is used for electrically communicating with circuits/modules or structures other than the control module CLM. For example, it is used to electrically connect with the address pin Di_in, the data pin DataP and the data bus DB, and the control logic module circuit is used to receive external signals through the data link circuit (such as the address signal input by the data pin DataP, the data pin The driving data Data inputted by the pin DataP), and used to generate driving control signals (for example, outputting the first driving control signal to the fifth driving control signal) and outputting them through the data link circuit.
  • Data Link Data Link
  • Control Logic Control Logic
  • the driving data Data includes address information and driving information; the logic control module CTR is further configured to acquire the driving information of the driving data Data when the address information of the driving data Data matches the address information of the driver circuit MIC, And generate a driving control signal according to the driving information of the driving data Data.
  • the driving method of the driver circuit MIC may further include: in the address configuration stage, receiving an address signal, configuring the address information of the driver circuit MIC according to the address signal, and generating and outputting a relay signal; the relay signal can be used as the next driver circuit MIC address signal.
  • generating a drive control signal corresponding to each output pin OUTP according to the drive data Data can be achieved by the following method: when the address information of the drive data Data matches the address information of the driver circuit MIC, the drive data is obtained Data driving information, and generate a driving control signal according to the driving information of the driving data Data.
  • an encoder may be provided on an external circuit (such as a circuit board), and a decoder may be provided on the logic control module CTR.
  • the encoder can perform encoding according to the 4b/5b encoding protocol, the 8b/10b encoding protocol or other encoding protocols to generate the driving data Data and transmit it to the driving data line DataL.
  • the decoder of the logic control module CTR can decode the driving data Data, and then obtain the address information and driving information in the driving data Data.
  • the data pins DataP of multiple driver circuits MIC can be connected to the same driving data line DataL; multiple different driving data Data can be loaded on the driving data line DataL, and each driver circuit The MIC can determine the corresponding driving data Data according to the configured address information, and drive the respective connected device units EC according to the corresponding driving data Data.
  • the driver circuit MIC can receive the driving data Data through the data pin DataP, and the array substrate can transmit the driving data Data through the driving data line DataL, thus avoiding the use of the SPI (Serial Peripheral interface, serial peripheral device interface) ) for data transmission, resulting in too many pads and wires, which can simplify the structure of the array substrate, external circuit and driver circuit MIC, and reduce the cost of the array substrate and driver circuit MIC.
  • SPI Serial Peripheral interface, serial peripheral device interface
  • a driver data line DataL are arranged in a device control area column BB, and the data pin DataP of each driver circuit MIC is connected to the driver circuit MIC. Data trace DataL.
  • address information may be pre-configured in the driver circuit MIC, or may be configured after power-on.
  • address information may be allocated to each driver circuit MIC after power-on, and the address information may be a dynamic address.
  • the driver circuit MIC may further include an address pin Di_in and a relay pin Di_out.
  • the address pin Di_in can receive the address signal;
  • the logic control module CTR is also configured to configure the address information of the driver circuit MIC according to the address signal, and generate a relay signal;
  • the relay signal can be used as the address signal of the connected driver circuit MIC ;
  • the relay pin Di_out is used to output the relay signal.
  • the driver circuit MIC of the next stage is the next driver circuit MIC of the driver circuit MIC of the previous stage.
  • the upper driver circuit MIC can configure address information for the lower driver circuit MIC according to its own address information, thereby implementing dynamic allocation for the cascaded driver circuits MIC. address.
  • the address information may be a digital signal, which may be modulated into the address signal.
  • a driver circuit MIC receives the address signal, it can analyze and obtain and store the address information in the address signal, and can also increment the address information by 1 or another fixed amount and modulate the incremented address information (new address information) is a relay signal, and the relay signal is used as an address signal of the driver circuit MIC of the next stage.
  • the driver circuit MIC can also use other different functions to generate new address information.
  • the logic control module CTR may further include a fifth modulation module PWMM5 , and the fifth modulation module PWMM5 is electrically connected to the relay pin Di_out.
  • the control module CLM can receive an address signal from the address pin Di_in, and generate and transmit a relay control signal to the fifth modulation module PWMM5 according to the address signal; the fifth modulation module PWMM5 can generate a relay signal in response to the relay control signal and load To relay pin Di_out.
  • the fifth modulation module PWMM5 can be electrically connected to the control module CLM through the data bus DB, or can be electrically connected to the control module through a dedicated data wiring, or can also be electrically connected to the control module in other ways.
  • the present disclosure makes no special limitation on this.
  • the driver circuit MIC further includes a data bus DB; the first modulation module PWMM1 to the fifth modulation module PWMM5, and the control module CLM are all connected to the data bus DB, and then The control module DB is made to interact with the first modulation module PWMM1 to the fifth modulation module PWMM5.
  • the fifth modulation module PWMM5 may include switching elements, such as transistors such as MOS (Metal-Oxide Semiconductor Field Effect Transistor) and TFT (Thin Film Transistor); the relay control signal may be a pulse Width modulation signal, the switching element is turned on or off under the control of the pulse width modulation signal.
  • the fifth modulation module PWMM5 may output current or voltage; when the switch element is turned off, the fifth modulation module PWMM5 may not output current or voltage. In this way, the fifth modulation module PWMM5 can modulate a pulse width modulation signal as a relay signal.
  • each driver circuit MIC located in the same device control area column BB is cascaded in sequence; in any device control area column BB, the array substrate is provided with a plurality of addresses corresponding to each driver circuit MIC one-to-one.
  • ADDRL is traced, and each address trace ADDRL extends along the column direction; the address pin Di_in of the driver circuit MIC is electrically connected to the corresponding address trace ADDRL, and the relay pin Di_out of the upper-level driver circuit MIC is connected to the next-level driver
  • the address wire ADDRL corresponding to the circuit MIC is electrically connected.
  • the cascaded driver circuits MIC can be electrically connected through the address wire ADDRL, and the relay signal of the upper driver circuit MIC can be loaded to the corresponding
  • the address line ADDRL is used as the address signal of the next-level driver circuit MIC.
  • the external circuit can load the address signal to the address wire ADDRL corresponding to the first-level driver circuit MIC.
  • the extension directions of the address wires ADDRL are the same.
  • the extension lines of the address lines ADDRL can overlap.
  • each address line ADDRL can only occupy the width of one address line ADDRL, avoiding the address line ADDRL occupying too much wiring space in the row direction, which is beneficial to increase the device power supply line VLEDL, ground voltage line
  • each address wire ADDRL is located between the device power wire VLEDL and the ground voltage wire GNDL.
  • the array substrate is further provided with a feedback wiring FBL.
  • the relay pin Di_out of the driver circuit MIC of the last stage may be connected to the feedback wiring FBL.
  • the array substrate may include a plurality of signal channels, and each signal channel includes a device control region column BB or a plurality of sequentially adjacent device control region columns BB.
  • each driver circuit MIC is cascaded in sequence.
  • the array substrate may be provided with at least one feedback wiring FBL, so as to electrically connect the relay pin Di_out of the final driver circuit MIC in the signal channel to the feedback wiring FBL.
  • a signal channel includes a device control area column BB.
  • any device control area column BB has a feedback wiring FBL.
  • the feedback trace FBL is located between the ground voltage trace GNDL and the device power trace VLEDL.
  • the driver circuit MIC further includes a chip power supply pin VCCP; the chip power supply pin VCCP is used to load the driver circuit MIC with a chip power supply voltage VCC for driving the driver circuit MIC to work.
  • the driver circuit MIC can also include a power module PWRM, the chip power supply pin VCCP can load the chip power supply voltage VCC to the power module PWRM, and the power module is configured to distribute power to each circuit of the driver circuit MIC, so as to ensure that the driver circuit MIC power supply.
  • the array substrate in column BB of the device control area, can be provided with chip power traces VCCL extending along the column direction, and external circuits can apply chip power supply voltage VCC to the driver circuit MIC through the chip power traces VCCL. Further, referring to FIG. 1 , the chip power trace VCCL is located between the device power trace VLEDL and the ground voltage trace GNDL.
  • the array substrate uses different routings to load the chip power supply voltage VCC and the driving data Data respectively, which can simplify the circuit structure inside the driver circuit, and there is no need to set a power regulation circuit in the driver circuit (the power regulation circuit is used for The direct current component in the power signal generates the chip power supply voltage and generates the drive data based on the modulation component in the power signal), which in turn helps to reduce the area of the driver circuit.
  • this setting method can also simplify the external circuit structure, avoid setting the modulation circuit that modulates the chip power supply voltage and driving data into power line carrier communication, and can also reduce the quality requirements for the chip power supply voltage. Therefore, the arrangement of the driver circuit and the array substrate of the present disclosure can simplify the structure and reduce the cost of the driver circuit and the external circuit.
  • the array substrate uses different traces to load the chip power supply voltage VCC and the driving data Data respectively, which can also ensure the signal quality of the chip power supply voltage VCC and the driving data Data, which in turn helps to improve the stability of the array substrate and the local dimming effect. precision.
  • the data pin DataP of the driver circuit MIC and the chip power pin VCCP can also be combined into one power pin; the array substrate can be provided with a power trace, and the power pin and the power trace Wire connection.
  • the external circuit (such as a circuit board) can modulate the chip power supply voltage VCC and the driving data Data into a power line carrier communication signal, and transmit it to the power line; the power line transmits the power line carrier communication signal to the driver circuit MIC.
  • the driver circuit MIC is configured to generate chip power supply voltage VCC and driving data Data according to the power line carrier communication signal, and generate driving control signals corresponding to each of the output pins according to the driving data.
  • a power regulating circuit is provided in the driver circuit, and the power regulating circuit is used to generate the chip power supply voltage VCC based on the DC component in the power line carrier communication signal, and is used to generate the driving data Data based on the modulation component in the power line carrier communication signal PWR.
  • the driver circuit MIC includes at least two output pins OUTP, a data pin DataP, an address pin Di_in, a relay pin Di_out, a ground pin GNDP and Chip power supply pin VCCP.
  • the driver circuit MIC can drive the connected device unit EC through the driving method shown in the following steps S110 to S140 , and then drive the array substrate.
  • Step S110 receiving the chip power supply voltage VCC in the power-on phase T1.
  • the external circuit can load the chip power supply voltage VCC to the chip power supply line VCCL, and the chip power supply voltage VCC can be loaded to the driver circuit MIC through the chip power supply pin VCCP, so as to supply power to the driver circuit MIC.
  • the driver circuit MIC is in a power-on state.
  • the external circuit can simultaneously apply the chip power supply voltage VCC to each chip power supply line VCCL, so that each driver circuit MIC of the array substrate is powered on at the same time.
  • the external circuit for example, a circuit board driving the array substrate
  • the external circuit can apply the chip power supply voltage VCC to the chip power supply line VCCL, thereby enabling the driver circuit MIC to be powered on and display Device power-on remains synchronized.
  • step S120 in the address configuration stage T2, an address signal is received, address information of the driver circuit MIC is configured according to the address signal, and a relay signal is generated and output.
  • the relay signal can be used as an address signal of the driver circuit MIC of the next stage (ie, the next driver circuit MIC).
  • the driver circuit MIC can receive the address signal on the connected address line ADDRL through the address pin Di_in.
  • the address signal can be an address signal loaded by the external circuit on the address wiring ADDRL; when the address wiring ADDRL is electrically connected to the upper driver circuit MIC, the address The address signal on the line ADDRL may be a relay signal output by the upper driver circuit MIC.
  • the driver circuit MIC can output the relay signal through the relay pin Di_out.
  • Di_out(n-1) is the relay pin Di_out of the n-1th driver circuit MIC
  • Di_in(n) is the nth driver circuit MIC
  • Di_in is the address pin Di_in
  • Di_out(n) is the relay pin Di_out of the driver circuit MIC of the nth level
  • Di_in(n+1) is the address pin Di_in of the driver circuit MIC of the n+1st level.
  • Di_out(n-1) and Di_in(n) are loaded with the same signal, that is, the relay signal output by the n-1th driver circuit MIC is used as the address of the nth driver circuit MIC Signal; Di_out(n) and Di_in(n+1) are loaded with the same signal, that is, the relay signal output by the nth driver circuit MIC is used as the address signal of the n+1th driver circuit MIC.
  • 2 ⁇ n ⁇ N-1 wherein, n is a positive integer, and N is the total number of multiple driver circuits MIC in a cascaded relationship.
  • step S120 among multiple cascaded driver circuits MIC in sequence, the external circuit can load address signals to the first-level driver circuit MIC, so that the first-level driver circuit MIC configures address information; then, the upper-level driver circuit MIC Output a relay signal as an address signal to the next-level driver circuit MIC, so that the next-level driver circuit MIC configures address information until the last driver circuit MIC configures address information, so that address information is configured for each driver circuit MIC.
  • Step S130 in the driving configuration phase T3, receiving a driving configuration signal, and performing initial configuration on the driver circuit MIC according to the driving configuration signal.
  • the external circuit can load the driving configuration signal to the driving data line DataL
  • the driver circuit MIC can load the driving configuration signal through the data pin DataP.
  • each driver circuit MIC connected to the same driving data line DataL can simultaneously receive the driving configuration signal and perform initialization configuration.
  • the external circuit can load the driving configuration signal to each driving data line DataL at the same time, so that each driver circuit MIC can receive the driving configuration signal and complete the initialization configuration at the same time, reducing the time for the array substrate to initialize the configuration of the driver circuit MIC.
  • Step S140 in the device control stage T4, receiving the driving data Data, generating a driving control signal corresponding to each output pin OUTP according to the driving data Data, and the driving control signal is used to control the current flowing through the corresponding output pin OUTP.
  • the driver circuit MIC can control the current flowing through the device units EC to achieve the purpose of driving each connected device unit EC according to the driving data Data.
  • the external circuit may load the driving data Data to the driving data line DataL, and the driver circuit MIC receives the driving data Data through the data pin DataP.
  • the driving data Data includes address information and driving information.
  • the address information of the driving data Data matches the address information of the driver circuit MIC
  • the driving information of the driving data Data is acquired, and a driving control signal is generated according to the driving information of the driving data Data.
  • the driving method of the driver circuit MIC may further include step S150, in the power-off phase T5, the driver circuit MIC is in a power-off state and does not work.
  • the chip power supply voltage VCC may not be applied to the chip power supply line VCCL, so that the driver circuit MIC is in a power-off state.
  • the driver circuit IC is powered off. In other words, when the display device is turned off, the driver circuit IC can be powered off and is in the power-off stage.
  • FIG. 7 is a schematic diagram of the driving process of the array substrate.
  • the array substrate when the array substrate is working, it may further include, before the device control phase T4 , applying the device power supply voltage VLED to the device power supply line VLEDL.
  • the device unit EC can work under the control of the driver circuit MIC, for example, the light emitting element can emit light under the control of the driver circuit MIC.
  • the number of output pins OUTP is four; the driver circuit MIC also includes a data pin DataP, an address pin Di_in, a relay pin Di_out, a ground pin GNDP and a chip power pin VCCP .
  • the array substrate in the device control area column BB, can be provided with a driving data line DataL electrically connected to the data pin DataP, an address line ADDRL electrically connected to the address pin Di_in or a relay pin Di_out, and a ground pin
  • the ground voltage trace GNDL electrically connected to the pin GNDP, the chip power trace VCCL electrically connected to the chip power pin VCCP, and the device power trace VLEDL for applying the device power voltage VLED to the device unit EC.
  • each pin of the driver circuit MIC can be arranged in multiple columns to facilitate the preparation of the driver circuit MIC.
  • the individual pins of the driver circuit MIC may be arranged in three columns (three pins per column) or in two columns.
  • each pin of the driver circuit MIC (such as including the ground pin GNDP, the chip power pin VCCP, the data pin DataP, the address pin Di_in, the relay pin Di_out and the output pin OUTP, etc.) are arranged into two pin columns, each pin column includes a plurality of pins arranged in a straight line; at least one pin column includes five pins. In other words, one of the pin columns includes five pins, and the other pin column can include the remaining pins.
  • the four output pins OUTP are all located at the end of the pin row; so as to facilitate the four output pins OUTP to be electrically connected to the four device units EC respectively.
  • the driver circuit MIC has two ground pins GNDP.
  • the driver circuit MIC includes ten pins, and each pin row includes five pins, which is beneficial to the uniformity of each pin and facilitates the preparation of the driver circuit MIC.
  • the two ground pins GNDP are located in the same pin column to facilitate wiring.
  • two ground pins GNDP are adjacently arranged. It can be understood that the driver circuit MIC may also have one ground pin GNDP, and the driver circuit MIC has nine pins. Further, the pin column with the ground pin GNDP has four pins.
  • the chip power pin VCCP and the data pin DataP are located in different pin columns; thus, the chip power pin VCCP and the data pin DataP can be respectively located on both sides of the ground voltage line GNDL.
  • the chip power supply pin VCCP and the data pin DataP can also be located in the same pin column; in this way, the chip power supply trace VCCL and the driving data trace DataL can be located on the same side of the ground voltage trace GNDL.
  • the address pin Di_in and relay pin Di_out are located in the same pin column.
  • the wiring of the array substrate is simpler and more convenient, and the number of wires can be reduced.
  • the overlapping area between them improves the yield of the array substrate.
  • one pin column may include an address pin Di_in, a chip power supply pin VCCP, and a relay pin Di_out arranged in sequence; another pin column A data pin DataP and a ground pin GNDP may be included.
  • this example is only one way to arrange the pins of the driver circuit MIC, and the pins of the driver circuit MIC can also be arranged in other ways, for example, the address pin Di_in, the data pin The pin DataP and the relay pin Di_out, and the chip power pin VCCP and the ground pin GNDP are set in another pin column.
  • the distance between the pins of the driver circuit MIC and the edge of the driver circuit MIC may be 25-40 microns to facilitate the preparation of the driver circuit and avoid increasing the area of the driver circuit if the distance is too large.
  • an arrangement direction of pins in a pin row may be defined as a first direction, and an arrangement direction of two pin rows may be defined as a second direction.
  • the distance between two adjacent pins may be 0.8-1.2 times the size of the pins in the first direction.
  • the bonding process window between pins and chip pads can be enlarged, and bad bonding caused by misalignment can be reduced; Larger, thereby reducing the area of the driver circuit to reduce the cost of the array substrate.
  • the size of the pins of the driver circuit in the first direction may be in the range of 80-120 microns, and the distance between two adjacent pins in the first direction may be in the range of 80-100 microns.
  • the distance between two adjacent pin rows may be 0.8-1.2 times the size of the pins in the second direction.
  • the bonding process window between pins and chip pads can be enlarged, and bad bonding caused by misalignment can be reduced; Larger, thereby reducing the area of the driver circuit to reduce the cost of the array substrate.
  • the size of the pins of the driver circuit in the second direction may be in the range of 120-150 microns, and the distance between two adjacent pins in the second direction may be in the range of 130-170 microns.
  • FIG. 12 is an example of a driver circuit MIC of the present disclosure.
  • the driver circuit MIC may include a voltage regulation circuit C310, a low dropout regulator C330, an oscillator C340, a control logic module CLM, an address driver C360, a dimming circuit C370, a transistor C375 and a brightness control circuit C380.
  • the driver circuit MIC may include additional, fewer or different components.
  • the voltage regulating circuit C310 receives the chip power supply voltage VCC at the chip power supply pin VCCP for regulation to obtain a DC component in the chip power supply voltage VCC to generate a supply voltage.
  • the voltage regulation circuit C310 includes a first-order RC filter followed by an active follower.
  • the supply voltage is provided to a low dropout voltage regulator C330.
  • the low dropout regulator C330 converts the supply voltage to a regulated DC voltage (which can step down the voltage) for powering the oscillator C340, the control logic module CLM and other components (not shown).
  • the regulated DC voltage may be 1.8 volts.
  • the oscillator C340 provides a clock signal, and the maximum frequency of the clock signal may be about 10 MHz, for example.
  • the control logic module CLM receives the driving data Data from the data pin DataP, the DC voltage from the low dropout voltage regulator C330 and the clock signal from the oscillator C340. Depending on the working stage of the array substrate, the control logic module CLM can also receive digital data from the address signal received at the address pin Di_in; the control logic module CLM can output the enable signal C352, the incremented data signal C354, PWM clock selection Signal C356 and maximum current signal C358. During the address configuration phase, the control logic module CLM activates the enable signal C352 to enable the address driver C360. The control logic module CLM receives the address signal via the address pin Di_in, stores the address, and provides the incremented data signal C354 representing the outgoing address to the address driver C360.
  • the address driver C360 buffers the incremented data signal C354 to the relay pin Di_out.
  • the control logic module CLM can control the dimming circuit C370 to turn off the transistor C375 during the address configuration phase to effectively block the current path from the device cell.
  • the control logic module CLM deactivates the enable signal C352 and the output of the address driver C360 is tri-stated to effectively decouple it from the relay pin Di_out.
  • PWM clock select signal C356 specifies the duty cycle for controlling PWM dimming by PWM dimming circuit C370. Based on the selected duty cycle, PWM dimming circuit C370 controls the timing of the on-state and off-state of transistor C375. During the on-state of transistor C375, a current path is established through transistor C375 from output pin OUTP (coupled to the device unit, Out1 in FIG.
  • brightness control circuit C380 sinks driver current for the functional elements of the unit.
  • the brightness control circuit C380 receives the maximum current signal C358 from the control logic module CLM and controls the current level flowing through the functional element (from the output pin OUTP to the ground pin GNDP) when the transistor C375 is in the on state.
  • the control logic module CLM controls the duty cycle of the PWM dimming circuit C370 and the maximum current C358 of the brightness control circuit C380 to set the LEDs in the device cells to a desired brightness.
  • the driver circuit MIC may also include a voltage-controlled constant-current circuit (not shown in the figure), and the input reference voltage and input reference current of the voltage-controlled constant-current circuit may receive chip power from the chip power pin VCCP voltage VCC is generated.
  • the voltage-controlled constant current circuit can be electrically connected with the brightness control circuit C380.
  • a short circuit detector and an open circuit detector are provided in the modulating module, wherein the open circuit detector is composed of an operational amplifier connected in a virtual open mode, and is used to detect whether an open circuit occurs between the device unit and the driver circuit MIC, wherein, The Vopen terminal may be a floating signal terminal.
  • the short circuit detector is composed of an operational amplifier connected in a virtual short mode to detect whether a short circuit occurs between the device unit and the driver circuit MIC, wherein the potential of Vshort can be the same as the potential of the power supply voltage VLED transmitted by the device power supply line VLEDL.
  • any signal channel information such as short circuit and open circuit between each device unit and the driver circuit MIC will be collected into the control logic module CLM of the corresponding driver circuit MIC, and then passed through the relay pin Di_out of the driver circuit MIC (For example, the information is sequentially appended to the back of the data signal C354 according to the coding rules), transmitted step by step until it is output by the relay pin Di_out of the driver circuit MIC of the last stage, and connected to the external circuit through the feedback line FBL.
  • the external circuit can respond to the feedback information, and detect the abnormality of the driver circuit MIC or the device unit EC in time.
  • the CRC (cyclic redundancy check code) check information in the signal channel can also be controlled by the driver circuit MIC of the last stage in the same way.
  • Relay pin Di_out output and connect to external circuit through feedback trace FBL.
  • the external circuit can respond to the feedback information, and detect the abnormality of the driver circuit MIC or the device unit EC in time.
  • the driver circuit MIC further includes a data selector MUX and an analog-to-digital converter ADC.
  • the driver circuit MIC forms a signal loop with the corresponding connected device unit EC and the device power supply wiring VLEDL through multiple output pins OutP, it can transmit the electrical signals of multiple signal loops to the data selector MUX, and time-sharing sequentially through the module After being processed by the digital converter ADC, it is transmitted to the control logic module CLM, and then through the relay pin Di_out of the driver circuit MIC (for example, the electrical signals of multiple signal loops are appended to the back of the data signal C354 in sequence and according to the coding rules), one by one Stage transmission, until it is output by the relay pin Di_out of the driver circuit MIC of the last stage, and connected to the external circuit through the feedback trace FBL.
  • the external circuit can respond to the feedback information and adjust the output signal level (for example, the level of the device power supply voltage VLED), thereby reducing the power consumption
  • the driver circuit MIC can also be provided with a thermal shutdown delay sensor TSD and a thermal shutdown delay (Thermal Shutdown) controller TS.
  • the thermal shutdown delay sensor TSD is used to detect the internal temperature of the driver circuit MIC.
  • the thermal shutdown delay controller TS works to turn off the output of the driver circuit MIC to reduce the power consumption of the driver circuit MIC , thereby reducing the internal temperature of the driver circuit MIC.
  • the restart temperature protection temperature ⁇ delay temperature
  • the delay temperature is generally set within a range of 15° to 30°.
  • the thermal shutdown delay (Thermal Shutdown) controller TS can be connected to the data selector MUX, and then the abnormal information can be fed back to the control logic module CLM through the data selector MUX, so as to control the working state of the driver circuit MIC.
  • the external circuit may further include a control circuit D110 for driving the array substrate.
  • the control circuit D110 generates address signals ADDR and driving data Data for controlling the array substrate, and provides these signals to the driver circuit MIC via driving wires (VLEDL/ADDRL/GNDL/DataL, etc.).
  • the control circuit D110 may include a timing controller D210 and a bridge D220.
  • the control circuit D110 may include additional, fewer or different components.
  • control circuit D110 may be implemented using a Field Programmable Gate Array (FPGA) and/or a PHY block.
  • the control circuit D110 is powered by an input voltage (VP) and is connected to ground (GND).
  • the control circuit D110 may control the display device using an active matrix (AM) driving method or a passive matrix (PM) driving method.
  • AM active matrix
  • PM passive matrix
  • the timing controller D210 generates an image control signal D215 indicating a value for driving a pixel of the array substrate and a timing for driving the pixel.
  • the timing controller D210 controls the timing of image frames or video frames, and controls the timing of driving each device unit in the image frame or video frame (for example, LEDs located in the LED lamp area).
  • the timing controller D210 controls the brightness for driving each of the LED lamp areas during a given image frame or video frame.
  • the image control signal D215 is provided to the bridge D220 by the timing controller D210.
  • the bridge D220 converts the image control signal D215 into an address signal ADDR and a driver control signal for driving data Data.
  • the bridge D220 may generate the address signal ADDR for the first driver circuit MIC in the group of driver circuits MIC during the address mode according to the control scheme described above.
  • the array substrate may include a substrate base 11, a driving circuit layer 200, and a device layer 300 stacked in sequence.
  • the driving circuit layer may be provided with bonding pads, for example, provided with bonding pads for bonding Device pads for functional components, chip pads for bonding driver circuit MIC, and circuit board pads for bonding external circuits, etc.
  • the device layer includes each functional element and each driver circuit MIC, each functional element is bonded to the device pad, and each driver circuit MIC is bonded to the chip pad.
  • chip pads for bonding connection with respective pins of the same driver circuit MIC may form a chip pad group.
  • the driving circuit layer of the array substrate may include a plurality of chip pad groups, and each chip pad group is bonded and connected to each driver circuit MIC in a one-to-one correspondence.
  • the driver circuit MIC may include at least two output pins OUTP, an address pin Di_in, a relay pin Di_out, a chip power pin VCCP, a data pin DataP, and a ground pin GNDP.
  • a chip pad group may include an output pad for bonding connection with each output pin OUTP, an address pad for bonding connection with the address pin Di_in, and an intermediate pad for bonding connection with the relay pin Di_out.
  • the number of ground pins GNDP is two and arranged adjacently; correspondingly, the number of ground pins is two and arranged adjacently.
  • a sufficient electrical connection between the ground pin GNDP and the ground voltage trace GNDL can be ensured (for example, with a larger connection area and smaller contact resistance, lower impedance, etc.), and the load on the driver circuit MIC can be improved. Stability of ground voltage GND.
  • providing two ground pins GNDP can also avoid setting the ground pin GNDP with too large area, thereby avoiding the problem of insufficient bonding force between the ground pin GNDP and the ground pin due to the large area of the ground pin GNDP.
  • the setting method of the chip pads in the chip pad group can be set according to the pin arrangement of the driver circuit MIC, whichever satisfies the binding between the driver circuit MIC and the chip pad group. There are no special restrictions on this publicly.
  • the base substrate 11 may be a base substrate of an inorganic material, may also be a base substrate of an organic material, or may be a base substrate formed by laminating and compounding an organic material and an inorganic material.
  • the material of the base substrate can be glass materials such as soda-lime glass, quartz glass, sapphire glass, or metals such as stainless steel, aluminum, nickel, etc. Material.
  • the material of the base substrate can be polymethyl methacrylate (Polymethyl methacrylate, PMMA), polyvinyl alcohol (Polyvinyl alcohol, PVA), polyvinyl phenol (Polyvinyl phenol, PVP ), polyethersulfone (Polyether sulfone, PES), polyimide, polyamide, polyacetal, polycarbonate (Polycarbonate, PC), polyethylene terephthalate (Polyethylene terephthalate, PET), poly Polyethylene naphthalate (PEN) or combinations thereof.
  • the driving circuit layer 200 may include a driving wiring layer 102 , a first insulating layer 117 and a metal wiring layer 105 sequentially stacked on one side of the base substrate 11 .
  • the driving wiring layer 102 can be formed with driving wirings for loading signals (such as ground voltage wiring GNDL, device power supply wiring VLEDL, address wiring ADDRL, driving data wiring DataL, chip power supply wiring VCCL, feedback wiring line FBL, etc.); the metal wiring layer 105 can form bonding pads (such as 101/107) and wiring lines WW.
  • the wiring traces WW can be used between bonding pads (such as between device pads corresponding to each functional element of the device unit EC), between bonding pads and driving traces (such as chip pads and driving wires). Electrical connections between traces, between device pads and drive traces).
  • the driving trace and the wiring trace may be electrically connected through a via hole penetrating the first insulating layer 117 .
  • the thickness of the driving wiring layer may be greater than that of the metal wiring layer, so as to reduce the square resistance of the driving wiring and reduce the voltage drop of the signal on the driving wiring.
  • the thickness of the driving wiring layer 102 is about 1.5 ⁇ m to 7 ⁇ m, and its material may include copper.
  • a stacked material such as MoNb/Cu/MoNb can be formed by sputtering, and the stacked layer is close to the substrate
  • MoNb the thickness is about Left and right, mainly used to improve the adhesion between the film layer and the substrate.
  • the material of the middle layer of the stack is Cu, which is the preferred material for the electrical signal transmission channel.
  • the material on the side away from the substrate is MoNb, with a thickness of about Left and right, it can be used to protect the intermediate layer and prevent the surface of the intermediate layer with low resistivity from being exposed to oxidation.
  • the driving wiring layer can also be formed by electroplating.
  • MoNiTi can be used to form a seed layer to increase the nucleation density of metal grains in the subsequent electroplating process, and then copper with low resistivity can be produced by electroplating. Then make the anti-oxidation layer, the material can be MoNiTi.
  • the surface of the driving wiring layer on the side away from the base substrate may be covered by the first insulating layer, so as to ensure the reliability and stability of the electrical path.
  • the metal wiring layer 105 is provided with pads (such as device pads for binding functional elements, device pads for binding driver circuits, etc.) MIC chip pads and circuit board pads for bonding external circuits).
  • the film thickness of the metal wiring layer is about about.
  • an anti-oxidation material layer can be provided only on the exposed surface area of the pad, that is, the pad The surface of the area will have one more layer of structure than the area where the wiring traces are located; or the overall metal wiring layer is set as a laminated structure of at least two layers, and the film layer material away from the substrate is an anti-oxidation metal or alloy material , specifically can be composed of a stacked structure such as MoNb/Cu/CuNi, the bottom layer material MoNb in the stack is mainly used to improve the adhesion, and the middle layer Cu in the stack is mainly used to transmit electrical signals due to its low resistivity
  • the top layer of CuNi in the stack can not only prevent the oxidation of the middle layer, but also ensure the firmness of the connection with the electronic components.
  • the surface of the wiring trace away from the base substrate will be covered by the second insulating layer 108 to ensure the reliability and stability of the electrical path.
  • the driving wiring may include a device power supply wiring VLEDL, a ground voltage wiring GNDL, an address wiring ADDRL, a chip power wiring VCCL, a driving data wiring DataL, and the like.
  • a device power supply wiring VLEDL a ground voltage wiring GNDL
  • an address wiring ADDRL a chip power wiring VCCL
  • a driving data wiring DataL a driving data wiring DataL, and the like.
  • between the output pin OUTP and the device pad of the device unit EC, between the address pad and the address line ADDRL, between the chip power pad and the chip power line VCCL, between the data pad and the driving data line DataL between the device pads of the device unit EC and the device power supply trace VLEDL, and between some address pads and the address trace ADDRL are all electrically connected through wiring traces.
  • the ground pad and the ground voltage trace GNDL may be electrically connected through wiring traces.
  • the ground pad and the ground voltage trace GNDL may also be directly connected through a via hole.
  • the array substrate may further include a buffer layer 109 located between the base substrate 11 and the driving wiring layer 102, and a first planar layer 110 located between the first insulating layer 117 and the metal wiring layer 105, sequentially The second planar layer 111 and reflective layer 112 located on the side of the second insulating layer 108 away from the metal wiring layer, the transparent electrode 113 located on the bonding pad 107 in the peripheral area, and the connection between the transparent electrode 113 and the external circuit (such as a flexible circuit) Anisotropic conductive glue 114 between boards FPC).
  • a buffer layer 109 located between the base substrate 11 and the driving wiring layer 102
  • a first planar layer 110 located between the first insulating layer 117 and the metal wiring layer 105, sequentially The second planar layer 111 and reflective layer 112 located on the side of the second insulating layer 108 away from the metal wiring layer, the transparent electrode 113 located on the bonding pad 107 in the peripheral area, and the connection between the transparent electrode 113 and the external circuit (such
  • the buffer layer 109 can avoid the impact of impurities in the base substrate on the conductivity of the driving wiring layer
  • the first flat layer 110 can provide a flat surface for the fabrication of the second conductive layer 104
  • the second flat layer 110 can be Subsequent binding of the functional element FE and the driver circuit MIC provides a flat surface
  • the material of the reflective layer 112 can be white ink, which is used to improve the reflectivity of the array substrate to reduce light loss
  • the transparent electrode 113 and the anisotropic conductive glue 114 It is used to realize the electrical connection between the bonding pads 107 (such as circuit board bonding pads) of the peripheral area and the flexible circuit board FPC.
  • the material of the base substrate can be glass, quartz, plastic, polyimide, PET, PMMA and other materials.
  • FIG. 11 is a schematic structural view of other embodiments of the array substrate of the present disclosure.
  • the array substrate may include: a base substrate 11; a buffer layer 109 located on the base substrate 11; a driving wiring layer 102 located on the side of the buffer layer 109 away from the base substrate; a driving wiring layer 102 located away from the substrate
  • the second insulating layer 116 on the side of the second conductive layer 105 away from the base substrate; and the second planar layer 111 on the side of the second insulating layer 116 away from the base substrate.
  • the second insulating layer 116 is located between the first planar layer 110 and the second planar layer 111 .
  • the material of the second planar layer 111 is an organic insulating material
  • a plurality of vent holes 1160 may be provided in the second insulating layer 116 .
  • the plurality of vent holes 1160 respectively expose a portion of the underlying first planar layer 110 .
  • the gas accumulated in the first flat layer 110 can be released through the vent hole 1160, so that problems such as warping and peeling of the film layer of the array substrate can be avoided, thereby improving product quality. Rate.
  • vent holes 1160 are provided, however, this is only for illustration, rather than limiting the embodiments of the present disclosure. In other embodiments, more or less vent holes may be provided.
  • the array substrate may further include an encapsulation layer 13 located on a side of the device layer away from the base substrate.
  • the encapsulation layer 13 includes a layered structure for encapsulating the functional element FE on the base substrate.
  • the encapsulation glue is coated on the surface of the functional element FE in the array substrate, and the encapsulation layer 13 is formed after drying.
  • the material of the encapsulation glue may include transparent light-curing or heat-curing resin, that is, the material of the encapsulation layer 13 may be a transparent protective glue.
  • the encapsulation layer 13 may include a plurality of transparent protective structures 30 .
  • the pins of the functional element FE are respectively connected to the device pads 101 through solder paste T, and each device pad 101 is connected according to the position of the functional element in the electrical circuit.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of El Displays (AREA)
  • Planar Illumination Modules (AREA)
  • Circuit Arrangement For Electric Light Sources In General (AREA)

Abstract

提供了一种驱动器电路(MIC)及其驱动方法、阵列基板和显示装置，属于显示技术领域。驱动器电路(MIC)包括逻辑控制模块(CTR)、数据引脚(DataP)和至少两个输出引脚(OUTP)；数据引脚(DataP)用于接收驱动数据(Data)；逻辑控制模块(CTR)被配置为根据驱动数据(Data)生成与各个输出引脚(OUTP)一一对应的驱动控制信号，驱动控制信号用于控制流经对应的输出引脚(OUTP)的电流。提供的驱动器电路(MIC)可以减少阵列基板中驱动器电路(MIC)的数量。

Description

驱动器电路及其驱动方法、阵列基板和显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种驱动器电路及其驱动方法、阵列基板和显示装置。
背景技术
在液晶显示装置中，可以采用具有局域调光功能的LED(发光二极管)阵列基板作为背光源。通过将驱动芯片集成在LED阵列基板上，可以克服传统的被动式行列扫描的控制方式所导致的控制复杂度较高和LED阵列发光不连续易闪烁的问题。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于克服上述现有技术的不足，提供一种驱动器电路及其驱动方法、阵列基板和显示装置，减少阵列基板上驱动器电路的用量。
根据本公开的一个方面，提供一种驱动器电路，包括逻辑控制模块、数据引脚和至少两个输出引脚；所述数据引脚用于接收驱动数据；所述逻辑控制模块被配置为根据所述驱动数据生成与各个所述输出引脚一一对应的驱动控制信号，所述驱动控制信号用于控制流经对应的所述输出引脚的电流。
根据本公开的一种实施方式，所述驱动数据包括地址信息和驱动信息；
所述逻辑控制模块还被配置为，当所述驱动数据的地址信息与所述驱动器电路的地址信息匹配时，获取所述驱动数据的驱动信息，并根据所述驱动数据的驱动信息生成所述驱动控制信号。
根据本公开的一种实施方式，所述驱动器电路还包括地址引脚和中继引脚；
所述地址引脚能够接收地址信号；
所述逻辑控制模块还被配置为，根据所述地址信号配置所述驱动器电路的地址信息，并生成中继信号；所述中继信号能够作为接续的驱动器电路的地址信号；
所述中继引脚用于输出所述中继信号。
根据本公开的一种实施方式，所述输出引脚的数量为四个；所述驱动器电路还包括接地引脚和芯片电源引脚；所述接地引脚用于向所述驱动器电路加载接地电压；所述芯片电源引脚用于向所述驱动器电路加载用于驱动所述驱动器电路工作的芯片电源电压；
其中，所述驱动器电路的各个引脚排列成两个引脚列，每个所述引脚列包括直线排列的多个引脚；至少一个所述引脚列包括五个引脚；
四个所述输出引脚均位于所述引脚列的端部；所述芯片电源引脚和所述数据引脚位于不同的所述引脚列中；所述地址引脚和所述中继引脚位于同一所述引脚列中。
根据本公开的另一个方面，提供一种驱动器电路的驱动方法，其中，所述驱动器电路包括至少两个输出引脚；所述驱动器电路的驱动方法包括：
在器件控制阶段，接收驱动数据，根据所述驱动数据生成与各个所述输出引脚一一对应的驱动控制信号，所述驱动控制信号用于控制流经对应的所述输出引脚的电流。
根据本公开的一种实施方式，所述驱动数据包括地址信息和驱动信息；所述驱动器电路的驱动方法还包括：
在地址配置阶段，接收地址信号，根据所述地址信号配置所述驱动器电路的地址信息，并生成和输出中继信号；所述中继信号能够作为接续的驱动器电路的地址信号；
根据所述驱动数据生成与各个所述输出引脚一一对应的驱动控制信号包括：
当所述驱动数据的地址信息与所述驱动器电路的地址信息匹配时，获取所述驱动数据的驱动信息，并根据所述驱动数据的驱动信息生成所述驱动控制信号。
根据本公开的另一个方面，提供一种阵列基板，包括阵列设置的多个器件控制区域；在任意一个所述器件控制区域内，所述阵列基板设置有上述的驱动器电路，以及设置有与所述驱动器电路的各个所述输出引脚一一对应连接的器件单元；任意一个所述器件单元包括一个功能元件或者多个电连接的功能元件。
根据本公开的一种实施方式，所述器件控制区域排列成多个器件控制区域列；任意一个所述器件控制区域列包括沿列方向依次排列的多个器件控制区域；
在任意一个所述器件控制区域列，所述阵列基板设置有沿所述列方向延伸的器件电源走线和驱动数据走线；所述器件单元的一端与所述器件电源走线电连接，另一端与对应的所述输出引脚电连接；所述数据引脚与所述驱动数据走线电连接。
根据本公开的一种实施方式，位于同一所述器件控制区域列中的各个所述驱动器电路依次级联；所述驱动器电路还包括地址引脚和中继引脚；
在任意一个所述器件控制区域列，所述阵列基板设置有与各个所述驱动器电路一一对应的多个地址走线，且各个所述地址走线沿所述列方向延伸；
所述驱动器电路的地址引脚与对应的所述地址走线电连接，上一级所述驱动器电路的中继引脚与下一级所述驱动器电路对应的所述地址走线电连接。
根据本公开的一种实施方式，在任意一个所述器件控制区域列，所述阵列基板还设置有沿所述列方向延伸的芯片电源走线和接地电压走线；
所述驱动器电路还包括芯片电源引脚和接地引脚，所述芯片电源引脚用于向所述驱动器电路加载用于驱动所述驱动器电路工作的芯片电源电压；所述芯片电源走线与所述芯片电源引脚电连接；所述接地引脚用于向所述驱动器电路加载接地电压，所述接地引脚与所述接地电压走线电连接。
根据本公开的一种实施方式，在任意一个所述器件控制区域列，所述器件单元排 列成两个器件单元列，任意一个所述器件单元列包括沿所述列方向依次排列的多个器件单元；
在任意一个所述器件控制区域列中，所述器件电源走线的数量为两个；两个所述器件电源走线分别位于所述接地电压走线的两侧，且与两个所述器件单元列一一对应设置；
所述器件单元列中的各个所述器件单元，均电连接至对应的所述器件电源走线。
根据本公开的一种实施方式，在任意一个所述器件控制区域列中，所述地址走线、所述驱动数据走线和所述芯片电源走线均位于所述器件电源走线与所述接地电压走线之间。
根据本公开的一种实施方式，在至少一个所述器件控制区域列中，所述阵列基板还设置有反馈走线；在所述器件控制区域列中，最后一级所述驱动器电路的中继引脚，与所述反馈走线电连接；所述反馈走线位于所述器件电源走线和所述接地电压走线之间。
根据本公开的一种实施方式，相邻两个所述器件控制区域列中，相邻的两个所述器件电源走线相互连接成一个走线。
根据本公开的一种实施方式，所述阵列基板包括依次层叠设置的衬底基板、驱动电路层和器件层；
其中，所述驱动电路层包括依次层叠于所述衬底基板的驱动走线层、第一绝缘层和金属布线层；所述驱动走线层的厚度大于所述金属布线层的厚度；
所述接地电压走线、所述器件电源走线、所述芯片电源走线、所述驱动数据走线和所述地址走线位于所述驱动走线层；
所述金属布线层设置有器件焊盘、芯片焊盘和布线走线；所述功能元件和所述驱动器电路位于所述器件层；所述功能元件与所述器件焊盘绑定连接，所述驱动器电路与所述芯片焊盘绑定连接，所述器件焊盘和所述芯片焊盘与所述驱动走线层之间，通过所述布线走线电连接。
根据本公开的另一个方面，提供一种显示装置，包括上述的阵列基板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一种实施方式中阵列基板在局部位置的原理示意图。
图2为本公开一种实施方式中驱动器电路的引脚排布示意图。
图3为本公开一种实施方式中驱动器电路的原理示意图。
图4为本公开一种实施方式中驱动器电路的时序示意图。
图5为本公开一种实施方式中级联的驱动器电路的时序示意图。
图6为本公开一种实施方式中驱动器电路的驱动方法的流程示意图。
图7为本公开一种实施方式中阵列基板的驱动过程示意图。
图8为本公开一种实施方式中，一个控制区域的结构示意图。
图9为本公开一种实施方式中，临近绑定区的两个控制区域的结构示意图。
图10为本公开一种实施方式中，阵列基板的结构示意图。
图11为本公开一种实施方式中，临近绑定区的两个控制区域的结构示意图，图11中未示出器件层。
图12为本公开一种实施方式中，驱动器电路的原理示意图。
图13为本公开一种实施方式中，控制电路的原理示意图。
附图标记说明：
AA、器件控制区域；BB、器件控制区域列；MIC、驱动器电路；OUTP、输出引脚；Out1、第一输出引脚；Out2、第二输出引脚；Out3、第三输出引脚；Out4、第四输出引脚；DataP、数据引脚；DataL、驱动数据走线；VLEDL、器件电源走线；Di_in、地址引脚；Di_out、中继引脚；ADDRL、地址走线；FBL、反馈走线；GNDP、接地引脚；GNDL、接地电压走线；VCCP、芯片电源引脚；VCCL、芯片电源走线；CTR、逻辑控制模块；PWMM1、第一调制模块；PWMM2、第二调制模块；PWMM3、第三调制模块；PWMM4、第四调制模块；PWMM5、第五调制模块。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料等。在其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本公开的主要技术创意。
当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
本公开提供一种驱动器电路以及应用该驱动器电路的阵列基板和显示装置。图1为阵列基板在局部位置的原理示意图。参见图1，本公开提供的阵列基板包括阵列设置的多个器件控制区域AA；在任意一个器件控制区域AA内，阵列基板设置有驱动器电路MIC和驱动器电路MIC所驱动的器件单元EC。参见图8，任意一个器件单元EC可以包括一个功能元件或者存在电连接关系的多个功能元件FE。可选地，参见图1，器件控制区域AA排列成多个器件控制区域列BB；任意一个器件控制区域列BB包括沿列方向依次排列的多个器件控制区域AA。进一步地，在一个器件控制区域列BB中，各个驱动器电路MIC可以沿列方向直线排列。
可以理解的是，图1仅仅用于示意出驱动器电路MIC、器件单元EC和各个走线之间的电连接关系。在图1中，为了更为清晰的展示电连接关系，驱动器电路MIC、器件单元EC和各个走线的尺寸并不是按照比例进行绘制的，驱动器电路MIC、器件单元EC和各个走线之间的相对位置关系也不是按照实际位置进行示出的。
可选地，在本公开中，驱动器电路MIC可以为一种集成电路，尤其是可以为一种具有引脚的封装芯片。
在本公开中，功能元件可以为电流驱动型的电子元件，例如可以为发热元件、发光元件、发声元件等，也可以为实现感测功能的电子元件，例如光敏元件、热敏元件、声电换能元件等。任意一个器件单元EC可以包括一种功能元件，也可以包括多种不同的电子元件。任意两个器件单元EC所包含的功能元件的数量、种类、相对位置和电连接方式，可以相同，也可以不相同。
可选地，参见图1，各个器件单元EC可以阵列分布，以便提高器件单元EC分布的均一性，提高阵列基板的均一性。在本公开的一些实施方式中，器件单元EC中的功能元件为同一种功能元件，例如均是发光元件。在阵列基板上，各个功能元件阵列分布，进而保证功能元件在整个阵列基板上分布的均一性，进一步提高阵列基板的均一性。进一步地，各个器件单元EC中，功能元件的数量、种类、相对位置和电连接方式完全相同，例如均为发光元件；如此，各个器件单元EC相同，利于阵列基板的驱动和调试。
可选地，器件单元EC中的至少部分功能元件可以为发光元件，例如可以为LED(发光二极管)、Micro LED(微发光二极管)、mini LED(迷你发光二极管)、OLED (有机电致发光二极管)、QD-OLED(量子点-有机电致发光二极管)、QLED(量子点发光二极管)、PLED(有机高分子电致发光二极管)等。在该实施方式中，该阵列基板可以在驱动器电路MIC的驱动下发光，进而可以应用于显示装置、照明装置等设备中。
在一些实施方式中，器件单元EC中的各个功能元件均为发光元件，且阵列基板上的各个发光元件阵列分布；显示装置可以为液晶显示装置，其包括层叠的液晶显示模组和背光模组，该阵列基板可以作为背光模组的背光源。在该实施方式中，各个器件单元EC可以在驱动器电路MIC的驱动下独立工作，使得各个器件单元EC可以独立发光；如此，该显示装置可以实现局域调光(local dimming)，实现HDR(High-Dynamic Range)效果，提高显示装置的显示质量。在任意一个器件单元EC中，功能元件的数量和电连接方式均相同。如此，可以保证发光元件在阵列基板上分布的均一性，利于提高阵列基板发光的均一性，降低背光模组调试的难度。
在另外的一些实施方式中，显示装置可以为Micro LED显示装置。其中，作为功能元件的发光元件(例如Micro LED、LED等)可以发光以直接显示图案。在一种实施方式中，发光元件可以为能够发出相同颜色光线的发光元件，例如可以均为蓝色LED、红色LED、绿色LED或者黄色LED。如此，该显示装置可以为单色的显示装置，其可以为仪器表盘、信号指示屏等显示装置。在另外的一些实施方式中，发光元件可以包括多种不同颜色的发光元件，例如可以包括红色LED、绿色LED、蓝色LED、黄色LED等中的至少两种，且不同颜色的发光元件可以被各自独立控制。如此，该显示装置可以通过混光而进行彩色显示。
进一步地，在本公开的一种实施方式中，阵列基板上的各个功能元件按照行列方向等间距阵列分布。具体的，各个功能元件可以排列成多个元件行，各个元件行沿列方向等间距排列，且每个元件行包括沿行方向等间距排列的多个功能元件。各个功能元件还可以排列成多个元件列，各个元件列沿行方向等间距排列，且每个元件列包括沿列方向等间距排列的多个功能元件。如此，可以进一步提高功能元件在阵列基板上分布的均一性。
可选地，在阵列基板的至少部分区域，各个驱动器电路MIC阵列分布。如此，可以降低阵列基板的设计和制备的难度，并降低阵列基板的调试难度，降低阵列基板及显示装置的成本。在一些实施方式中，在阵列基板上，各个驱动器电路MIC阵列分布。进一步地，各个驱动器电路MIC相对于其所驱动的器件单元EC的相对位置，可以相同。在另外一些实施方式中，参见图9，阵列基板可以包括相邻的第一区域C1和第二区域C2。其中，位于第一区域中的各个驱动器电路MIC阵列分布；位于第二区域中的驱动器电路MIC阵列分布；驱动器电路MIC在第一区域和第二区域整体上不呈阵列分布。进一步地，第一区域C1中的驱动器电路MIC相对于其所驱动的器件单元EC的相对位置，与第二区域C2中的驱动器电路MIC相对于其所驱动的器件单元EC的 相对位置，可以不同。进一步地，阵列基板具有绑定区，绑定区内设置有用于与外部电路(例如电路板、柔性电路板、覆晶薄膜等)绑定连接的电路板绑定焊盘。第二区域可以位于阵列基板靠近绑定区的一端，第一区域可以位于第二区域远离绑定区的一侧。
示例性地，在本公开的一种实施方式中，如图9所示，驱动器电路MIC具有两个输出引脚OUTP(例如Out1、Out2等)，以驱动两个器件单元EC。阵列基板设置有扇出区和绑定区，扇出区内具有与绑定区中的电路板绑定焊盘电连接的扇出走线，扇出走线还与驱动驱动器电路MIC和器件单元EC的驱动走线电连接。其中，阵列基板中，最靠近绑定区的各个器件控制区域AA组成第二区域C2，其余控制区域AA可以组成第一区域C1。如此，第二区域C2可以与扇出区交叠，尤其是第二区域C2中的各个器件单元EC可以与扇出区交叠。第二区域C2中的控制区域AA中，驱动器电路MIC可以位于两个器件单元EC远离绑定区的一侧。第一区域C2中的控制区域AA中，驱动器电路MIC可以位于两个器件单元EC靠近绑定区的一侧。
可以理解的是，本公开的阵列基板集成有驱动器件单元的驱动器电路，这可以简化驱动阵列基板的外部电路并简化其控制方法，利于外部电路的小型化。尤其是，这一方面可以减小外部电路中的集成电路的体积进而降低集成电路的成本，另一方面可以减小外部电路中电路板的面积。
参见图3，本公开提供的驱动器电路MIC包括逻辑控制模块CTR、数据引脚DataP和至少两个输出引脚OUTP；数据引脚DataP用于接收驱动数据Data；逻辑控制模块CTR被配置为根据驱动数据Data生成与各个输出引脚OUTP一一对应的驱动控制信号，驱动控制信号用于控制流经对应的输出引脚OUTP的电流。参见图1和图3，在任意一个器件控制区域AA中，阵列基板上的器件单元EC与驱动器电路MIC的各个输出引脚OUTP一一对应设置。在整个阵列基板上，各个器件单元EC与各个输出引脚OUTP一一对应设置。
如此，驱动器电路MIC可以通过如下的驱动方法进行驱动：在器件控制阶段，接收驱动数据Data，根据驱动数据Data生成与各个输出引脚OUTP一一对应的驱动控制信号，驱动控制信号用于控制流经对应的输出引脚OUTP的电流。
根据该驱动方法，驱动器电路MIC的逻辑控制模块CTR可以根据驱动数据Data控制流经输出引脚OUTP的电流，进而控制流经与输出引脚OUTP电连接的器件单元EC的驱动电流，实现对器件单元EC的控制和驱动。本公开的驱动器电路MIC可以同时驱动至少两个器件单元EC，进而可以减少阵列基板中驱动器电路MIC的数量，降低阵列基板的成本。不仅如此，由于驱动器电路MIC的用量减少，还可以降低阵列基板的制备难度，减少驱动器电路绑定良率对阵列基板的良率的影响，进而提高阵列基板的良率。当存在多个阵列排布的驱动器电路MIC时，多个驱动器MIC可以同时向其所连接的多个器件单元EC提供驱动信号，即让多个受不同驱动器MIC驱动的器 件单元EC同时工作。可以理解的是，为了保证驱动器电路MIC的稳定性并延长驱动器电路MIC的使用寿命，本公开所说的“同时驱动”和“同时工作”，可以在时间上存在纳秒量级的先后顺序。
在本公开的一种实施方式中，参见图3，一个驱动器电路MIC设置有四个输出引脚OUTP，即设置有第一输出引脚Out1、第二输出引脚Out2、第三输出引脚Out3、第四输出引脚Out4。如此，本公开的驱动器电路MIC可以同时驱动四个器件单元EC；相较于一个驱动器电路MIC驱动一个器件单元EC的方案，可以使得驱动器电路MIC的数量减少至1/4，大大降驱动器电路MIC的用量，进而降低阵列基板的成本。
可以理解的是，尽管本公开的驱动器电路MIC相较于仅设置一个输出引脚的驱动器电路具有略大的体积，但是由于本公开可以大幅度减小驱动器电路MIC的用量，进而可以在驱动器电路MIC整体面积占比的降低、驱动器电路MIC绑定效率的提升和阵列基板良率的提升方面获得显著的改善。示例性地，在本公开的一种实施方式中，本公开的驱动器电路MIC具有四个输出引脚OUTP，其面积为仅具有一个输出引脚OUTP的驱动器电路MIC的两倍；然而，本公开的驱动器电路MIC的用量可以减少至1/4，进而使得本公开的阵列基板中驱动器电路MIC的面积占比降低至1/2(相对于1个驱动器电路MIC驱动一个器件单元EC的阵列基板)。
参见图1，在任意一个器件控制区域列BB，阵列基板设置有沿列方向延伸的器件电源走线VLEDL和驱动数据走线DataL；器件单元EC的一端与器件电源走线VLEDL电连接，另一端与对应的输出引脚OUTP(例如Out1～Out4中的任意一个)电连接；数据引脚DataP与驱动数据走线DataL电连接。
可选地，在任意一个器件控制区域列BB，器件单元EC排列成两个器件单元列，任意一个器件单元列包括沿列方向依次排列的多个器件单元EC；在任意一个器件控制区域列BB中，器件电源走线VLEDL的数量为两个；两个器件电源走线VLEDL与两个器件单元列一一对应设置；器件单元列中的各个器件单元EC，分别与距离自己最近的器件电源走线VLEDL(即该器件单元EC对应的器件电源走线VLEDL)相连接。
进一步地，在本公开的一种实施方式中，相邻两个控制区域列中，相邻的两个器件电源走线VLEDL可以相互连接成一个走线，即相邻两个器件电源走线VLEDL合并为一个器件电源走线VLEDL’。如此，该合并的器件电源走线VLEDL’可以与两个器件单元列对应设置，两个器件单元列上的器件单元EC均连接至该合并的器件电源走线VLEDL’。该合并的器件电源走线VLEDL’的宽度可以大于与位于最靠近阵列基板边缘的器件单元列连接的器件电源走线VLEDL，合并的器件电源走线VLEDL’可以包括镂空部；当然的，该合并的器件电源走线VLEDL’的宽度也可以与位于最靠近阵列基板边缘的器件单元列连接的器件电源走线VLEDL的宽度相同。
在该实施方式中，外部电路(例如电路板)可以向驱动数据走线DataL提供驱动数据Data，进而驱动数据走线DataL将驱动数据Data传输至数据引脚DataP；外部电 路还可以通过器件电源走线VLEDL向器件单元EC提供器件电源电压VLED。进一步地，驱动器电路MIC包括接地引脚GNDP，接地引脚GNDP用于向驱动器电路MIC加载接地电压GND。在任意一个器件控制区域列BB，阵列基板设置有沿列方向延伸的接地电压走线GNDL，接地引脚GNDP与接地电压走线GNDL电连接；外部电路可以向接地电压走线GNDL加载接地电压GND，进而将接地电压GND加载至驱动器电路MIC。如此，器件单元EC相当于连接于器件电源走线VLEDL和接地电压走线GNDL之间；逻辑控制模块CTR通过输出引脚OUTP控制器件单元EC的电流路径的导通或者截止，进而控制通过器件单元EC和输出引脚OUTP的电流。
可选地，在任意一个器件控制区域列BB中，器件电源走线VLEDL的数量为两个；两个器件电源走线VLEDL分别位于接地电压走线GNDL的两侧。
可选地，在任意一个器件控制区域列BB中，驱动器电路MIC可以与接地电压走线GNDL交叠设置，以利用接地电压走线GNDL上加载的接地电压GND为驱动器电路MIC提供电磁屏蔽。
可选地，参见图3，逻辑控制模块CTR可以包括控制模块CLM和与各个输出引脚OUTP一一对应设置的调制模块(例如图3中的PWMM1～PWMM4)。各个调制模块与对应的输出引脚OUTP电连接。控制模块CLM被配置为根据驱动数据Data生成与各个调制模块一一对应的驱动控制信号，驱动控制信号用于控制对应的调制模块的导通或者截止，进而控制输出引脚OUTP与接地电压走线GNDL之前的电通路或者电断路，进而实现对器件单元EC的控制。在一些实施方式中，驱动控制信号通过对调制模块的控制，可以使得流经调制模块(以及与调制模块连接的输出引脚OUTP、器件单元EC)的信号为一种脉冲宽度调制信号；驱动控制信号可以用于对该脉冲宽度调制信号的调制，例如调整该脉冲宽度调制信号的占空比等因素，进而控制流经输出引脚OUTP和器件单元EC的平均电流。
示例性地，在本公开的一种实施方式中，参见图1～图3，驱动器电路MIC包括四个输出引脚OUTP，分别为第一输出引脚Out1～第四输出引脚Out4；逻辑控制模块CTR包括四个调制模块，即第一调制模块PWMM1、第二调制模块PWMM2、第三调制模块PWMM3、第四调制模块PWMM4。第一输出引脚Out1～第四输出引脚Out4与第一调制模块PWMM1～第四调制模块PWMM4一一对应地连接。控制模块CLM用于根据驱动数据Data生成第一驱动控制信号、第二驱动控制信号、第三驱动控制信号、第四驱动控制信号，并分别传输至第一调制模块PWMM1、第二调制模块PWMM2、第三调制模块PWMM3和第四调制模块PWMM4。
第一调制模块PWMM1与第一输出引脚Out1电连接，并能够在第一驱动控制信号的控制下导通或者截止，使得第一输出引脚Out1与接地电压走线GNDL之间导通或者断开。当第一调制模块PWMM1导通时，接地电压走线GNDL、第一输出引脚Out1、与第一输出引脚Out1电连接的器件单元EC和器件电源走线VLEDL构成信号 回路，器件单元EC工作；当第一调制模块PWMM1截止时，上述信号回路断开，器件单元EC不工作。如此，第一调制模块PWMM1可以在第一驱动控制信号的控制下对流经器件单元EC的电流进行调制，使得流经器件单元EC的电流呈现为一种脉冲宽度调制信号。第一调制模块PWMM1可以根据第一驱动控制信号对流经器件单元EC的脉冲宽度调制信号的占空比等因素进行调制，进而控制器件单元EC的工作状态。当器件单元EC含有LED时，通过增加脉冲宽度调制信号的占空比，可以提高LED在一个显示帧内的发光总时长，进而提高LED在该显示帧内的总发光亮度，使得阵列基板在该区域的亮度增大；反之，通过降低脉冲宽度调制信号的占空比，可以降低LED在一个显示帧内的发光总时长，进而降低LED在该显示帧内的总发光亮度，使得阵列基板在该区域的亮度减小。
相应的，第二调制模块PWMM2与第二输出引脚Out2电连接，并能够在第二驱动控制信号的控制下导通或者截止，进而使得流经与第二输出引脚Out2连接的器件单元EC的电流呈现为一种脉冲宽度调制信号。第三调制模块PWMM3与第三输出引脚Out3电连接，并能够在第三驱动控制信号的控制下导通或者截止，进而使得流经与第三输出引脚Out3连接的器件单元EC的电流呈现为一种脉冲宽度调制信号。第四调制模块PWMM4与第四输出引脚Out4电连接，并能够在第四驱动控制信号的控制下导通或者截止，进而使得流经与第四输出引脚Out4连接的器件单元EC的电流呈现为一种脉冲宽度调制信号。
在本公开的一种实施方式中，第一调制模块PWMM1～第四调制模块PWMM4可以为开关元件，例如可以为MOS(金属-氧化物半导体场效应晶体管)、TFT(薄膜晶体管)等晶体管；第一驱动控制信号～第四驱动控制信号可以为脉冲宽度调制信号，开关元件在脉冲宽度调制信号的控制下导通或者截止。
可选地，在本公开中，参见图3，第一调制模块PWMM1～第四调制模块PWMM4可以通过数据总线DB与控制模块CLM电连接，也可以分别通过数据走线与控制模块电连接，亦或通过其他方式与控制模块实现电连接，本公开对此不做特殊的限制。
在本公开的一种实施方式中，控制模块CLM可以包括数据链接(Data Link)电路和控制逻辑模块(Control Logic)电路，数据链接电路用于与控制模块CLM以外的电路/模块或者结构进行电连接，例如用于与地址引脚Di_in、数据引脚DataP和数据总线DB进行电连接，控制逻辑模块电路用于通过数据链接电路接收外部的信号(例如数据引脚DataP输入的地址信号、数据引脚DataP输入的驱动数据Data)，以及用于生成驱动控制信号(例如输出第一驱动控制信号～第五驱动控制信号)并通过数据链接电路输出。
在一些实施方式中，驱动数据Data包括地址信息和驱动信息；逻辑控制模块CTR还被配置为，当驱动数据Data的地址信息与驱动器电路MIC的地址信息匹配时，获取驱动数据Data的驱动信息，并根据驱动数据Data的驱动信息生成驱动控制信号。
如此，驱动器电路MIC的驱动方法还可以包括：在地址配置阶段，接收地址信号，根据地址信号配置驱动器电路MIC的地址信息，并生成和输出中继信号；中继信号能够作为接续的驱动器电路MIC的地址信号。在在器件控制阶段，根据驱动数据Data生成与各个输出引脚OUTP一一对应的驱动控制信号可以通过如下方法实现：当驱动数据Data的地址信息与驱动器电路MIC的地址信息匹配时，获取驱动数据Data的驱动信息，并根据驱动数据Data的驱动信息生成驱动控制信号。
可选地，外部电路(例如电路板)上可以设置有编码器，逻辑控制模块CTR可以设置有解码器。编码器可以按照4b/5b编码协议、8b/10b编码协议或者其他编码协议进行编码，以生成驱动数据Data并传输至驱动数据走线DataL。逻辑控制模块CTR的解码器可以对驱动数据Data进行解码，进而获得驱动数据Data中的地址信息和驱动信息。
如此，在阵列基板上，参见图1，多个驱动器电路MIC的数据引脚DataP可以连接至同一驱动数据走线DataL；驱动数据走线DataL上可以加载多个不同的驱动数据Data，各个驱动器电路MIC可以根据配置的地址信息确定所对应的驱动数据Data，并根据各自对应的驱动数据Data来驱动各自所连接的器件单元EC。在本公开中，驱动器电路MIC可以通过数据引脚DataP来接收驱动数据Data，阵列基板可以通过驱动数据走线DataL来传输驱动数据Data，因此避免了采用SPI(Serial Peripheral interface，串行外围设备接口)进行数据传输而导致焊盘、走线数量太多的问题，进而可以简化阵列基板、外部电路和驱动器电路MIC的结构，降低阵列基板和驱动器电路MIC的成本。在本公开的一种实施方式中，参见图1，在一个器件控制区域列BB设置有一列驱动器电路MIC和一根驱动数据走线DataL，各个驱动器电路MIC的数据引脚DataP均连接至该驱动数据走线DataL。
可选地，在本公开中，驱动器电路MIC中可以预先配置有地址信息，也可以在上电后配置地址信息。在本公开的一种实施方式中，在上电后，可以为各个驱动器电路MIC分配地址信息，且该地址信息可以为一种动态地址。
示例性地，参见图1和图3，驱动器电路MIC还可以包括地址引脚Di_in和中继引脚Di_out。其中，地址引脚Di_in能够接收地址信号；逻辑控制模块CTR还被配置为，根据地址信号配置驱动器电路MIC的地址信息，并生成中继信号；中继信号能够作为接续的驱动器电路MIC的地址信号；中继引脚Di_out用于输出中继信号。在本公开中，当驱动器电路MIC级联时，下一级驱动器电路MIC为上一级驱动器电路MIC的接续的驱动器电路MIC。如此，当阵列基板上多个驱动器电路MIC依次级联时，上一级驱动器电路MIC可以根据自身的地址信息为下一级驱动器电路MIC配置地址信息，进而实现为级联的驱动器电路MIC分配动态地址。
在本公开的一种实施方式中，地址信息可以为一种数字信号，其可以被调制入地址信号中。当一个驱动器电路MIC接收地址信号后，可以解析并获得、存储该地址信 号中的地址信息，还可以使地址信息递增1或另一固定量并将递增后的地址信息(新的地址信息)调制为中继信号，该中继信号作为下一级驱动器电路MIC的地址信号。当然地，驱动器电路MIC还可以采用其他不同的函数以生成新的地址信息。
在本公开的一种实施方式中，参见图3，逻辑控制模块CTR还可以包括第五调制模块PWMM5，第五调制模块PWMM5与中继引脚Di_out电连接。控制模块CLM可以从地址引脚Di_in接收地址信号，并根据地址信号生成并传输中继控制信号至第五调制模块PWMM5；第五调制模块PWMM5可以响应中继控制信号而生成一中继信号并加载至中继引脚Di_out。
在本公开中，第五调制模块PWMM5可以通过数据总线DB与控制模块CLM电连接，也可以通过专用的数据走线与控制模块电连接，亦或还可以通过其他方式与控制模块实现电连接，本公开对此不做特殊的限制。
示例性地，参见图3，在本公开的一种实施方式中，驱动器电路MIC还包括数据总线DB；第一调制模块PWMM1～第五调制模块PWMM5、控制模块CLM均与数据总线DB连接，进而使得控制模块DB与第一调制模块PWMM1～第五调制模块PWMM5进行交互。
在本公开的一种实施方式中，第五调制模块PWMM5可以包括开关元件，例如可以包括MOS(金属-氧化物半导体场效应晶体管)、TFT(薄膜晶体管)等晶体管；中继控制信号可以为脉冲宽度调制信号，开关元件在脉冲宽度调制信号的控制下导通或者截止。当开关元件导通时，第五调制模块PWMM5可以输出电流或者电压；当开关元件截止时，第五调制模块PWMM5可以不输出电流或者电压。如此，第五调制模块PWMM5可以调制出一个脉冲宽度调制信号作为中继信号。
可选地，参见图1，位于同一器件控制区域列BB中的各个驱动器电路MIC依次级联；在任意一个器件控制区域列BB，阵列基板设置有与各个驱动器电路MIC一一对应的多个地址走线ADDRL，且各个地址走线ADDRL沿列方向延伸；驱动器电路MIC的地址引脚Di_in与对应的地址走线ADDRL电连接，上一级驱动器电路MIC的中继引脚Di_out与下一级驱动器电路MIC对应的地址走线ADDRL电连接。如此，在该器件控制区域列BB中，级联的驱动器电路MIC之间可以通过地址走线ADDRL进行电连接，上一级驱动器电路MIC的中继信号可以加载至下一级驱动器电路MIC对应的地址走线ADDRL上，并作为下一级驱动器电路MIC的地址信号。进一步地，外部电路可以向第一级驱动器电路MIC对应的地址走线ADDRL加载地址信号。
参见图1，在本公开的一种实施方式中，在任意一个器件控制区域列BB中，各个地址走线ADDRL的延伸方向相同。换言之，各个地址走线ADDRL的延伸线可以重合。如此，在行方向上，各个地址走线ADDRL可以仅占用一个地址走线ADDRL的宽度，避免了地址走线ADDRL在行方向上占用太大的布线空间，利于增大器件电源走线VLEDL、接地电压走线GNDL等走线的宽度以降低这些走线的方阻。
参见图1，在本公开的一种实施方式中，在任意一个器件控制区域列BB中，各个地址走线ADDRL位于器件电源走线VLEDL和接地电压走线GNDL之间。
在本公开的一种实施方式中，参见图1，在至少一个器件控制区域列BB中，阵列基板还设置有反馈走线FBL。在依次级联的多个驱动器电路MIC中，最后一级的驱动器电路MIC的中继引脚Di_out可以连接至反馈走线FBL。
进一步地，阵列基板可以包括多个信号通道，每个信号通道包括一个器件控制区域列BB或者依次相邻的多个器件控制区域列BB。在一个信号通道内，各个驱动器电路MIC依次级联。在任意一个信号通道内，阵列基板可以设置有至少一个反馈走线FBL，以便使得该信号通道内的最后一级驱动器电路MIC的中继引脚Di_out与反馈走线FBL电连接。示例性地，参见图1，一个信号通道包括一个器件控制区域列BB。再示例性地，参见图1，任意一个器件控制区域列BB具有一个反馈走线FBL。可选地，在器件控制区域列BB中，反馈走线FBL位于接地电压走线GNDL和器件电源走线VLEDL之间。
可选地，参见图1和图3，驱动器电路MIC还包括芯片电源引脚VCCP；芯片电源引脚VCCP用于向驱动器电路MIC加载用于驱动驱动器电路MIC工作的芯片电源电压VCC。进一步地，驱动器电路MIC还可以包括电源模块PWRM，芯片电源引脚VCCP可以将芯片电源电压VCC加载至电源模块PWRM，电源模块被配置将电力分配至驱动器电路MIC的各个电路中，以保障驱动器电路MIC的电力供应。
参见图1，在器件控制区域列BB，阵列基板可以设置有沿列方向延伸的芯片电源走线VCCL，外部电路可以通过芯片电源走线VCCL向驱动器电路MIC加载芯片电源电压VCC。进一步地，参见图1，芯片电源走线VCCL位于器件电源走线VLEDL和接地电压走线GNDL之间。
在该实施方式中，阵列基板采用不同的走线分别加载芯片电源电压VCC和驱动数据Data，可以简化驱动器电路内部的电路结构，无需在驱动器电路内设置电力调节电路(该电力调节电路用于基于电源信号中的直流分量生成芯片电源电压并基于电源信号中的调制分量生成驱动数据)，进而利于减小驱动器电路的面积。另外，这种设置方式还可以简化外部电路结构，既可以避免设置将芯片电源电压和驱动数据调制成电力线载波通信的调制电路，还可以降低对所芯片电源电压的品质要求。因此，本公开的驱动器电路和阵列基板的设置方式，可以简化驱动器电路和外部电路的结构并降低其成本。不仅如此，阵列基板采用不同的走线分别加载芯片电源电压VCC和驱动数据Data，还可以保证芯片电源电压VCC和驱动数据Data的信号质量，进而利于提高阵列基板的稳定性和局域调光的精准性。
当然的，在本公开的其他实施方式中，驱动器电路MIC的数据引脚DataP和芯片电源引脚VCCP也可以合并为一个电源引脚；阵列基板可以设置有电源走线，电源引脚与电源走线电连接。其中，外部电路(例如电路板)可以将芯片电源电压VCC和驱 动数据Data调制成电力线载波通信信号，并传输至电源走线；电源走线将电力线载波通信信号传输至驱动器电路MIC。驱动器电路MIC被配置为，根据电力线载波通信信号，生成芯片电源电压VCC和驱动数据Data，并根据所述驱动数据生成与各个所述输出引脚一一对应的驱动控制信号。进一步地，驱动器电路内设置电力调节电路，该电力调节电路用于基于电力线载波通信信号中的直流分量生成芯片电源电压VCC，且用于基于电力线载波通信信号PWR中的调制分量生成驱动数据Data。
在一种示例性地实施方式中，参见图2和图3，驱动器电路MIC包括至少两个输出引脚OUTP、数据引脚DataP、地址引脚Di_in、中继引脚Di_out、接地引脚GNDP和芯片电源引脚VCCP。参见图4～图6，驱动器电路MIC可以通过如下步骤S110～步骤S140所示的驱动方法来驱动所连接的器件单元EC，进而驱动阵列基板。
步骤S110，在上电阶段T1，接收芯片电源电压VCC。在该步骤中，外部电路可以向芯片电源走线VCCL加载芯片电源电压VCC，芯片电源电压VCC可以通过芯片电源引脚VCCP加载至驱动器电路MIC，以便为驱动器电路MIC供电。如此，驱动器电路MIC处于上电状态。
可选地，本公开的显示装置在工作时，外部电路可以同时向各个芯片电源走线VCCL加载芯片电源电压VCC，进而使得阵列基板的各个驱动器电路MIC同时上电。
可选地，当显示装置开机并使得外部电路(例如驱动阵列基板的电路板)上电后，该外部电路可以向芯片电源走线VCCL加载芯片电源电压VCC，进而使得驱动器电路MIC上电和显示装置开机保持同步。
步骤S120，在地址配置阶段T2，接收地址信号，根据地址信号配置驱动器电路MIC的地址信息，并生成和输出中继信号。中继信号能够作为下一级驱动器电路MIC(即接续的驱动器电路MIC)的地址信号。其中，驱动器电路MIC可以通过地址引脚Di_in接收所连接的地址走线ADDRL上的地址信号。当该地址走线ADDRL与外部电路电连接时，该地址信号可以为外部电路加载至地址走线ADDRL上的地址信号；当该地址走线ADDRL与上一级驱动器电路MIC电连接时，该地址走线ADDRL上的地址信号可以为上一级驱动器电路MIC所输出的中继信号。其中，驱动器电路MIC可以通过中继引脚Di_out输出中继信号。
示例性地，参见图5，在级联的驱动器电路MIC中，Di_out(n-1)为第n-1级驱动器电路MIC的中继引脚Di_out；Di_in(n)为第n级驱动器电路MIC的地址引脚Di_in；Di_out(n)为第n级驱动器电路MIC的中继引脚Di_out；Di_in(n+1)为第n+1级驱动器电路MIC的地址引脚Di_in。参见图5，在地址配置阶段T2，Di_out(n-1)和Di_in(n)上加载相同的信号，即第n-1级驱动器电路MIC输出的中继信号作为第n级驱动器电路MIC的地址信号；Di_out(n)和Di_in(n+1)上加载相同的信号，即第n级驱动器电路MIC输出的中继信号作为第n+1级驱动器电路MIC的地址信号。在该示例中，2≤n≤N-1；其中，n为正整数，N为具有级联关系的多个驱动器电路 MIC的总数。
在步骤S120中，在依次级联的多个驱动器电路MIC中，外部电路可以向第一级驱动器电路MIC加载地址信号，使得第一级驱动器电路MIC配置地址信息；然后，上一级驱动器电路MIC向下一级驱动器电路MIC输出作为地址信号的中继信号，以使得下一级驱动器电路MIC配置地址信息，直至最后一个驱动器电路MIC配置地址信息，如此实现对各个驱动器电路MIC配置地址信息。
步骤S130，在驱动配置阶段T3，接收驱动配置信号，并根据驱动配置信号对驱动器电路MIC进行初始化配置。其中，外部电路可以向驱动数据走线DataL加载驱动配置信号，驱动器电路MIC可以通过数据引脚DataP加载该驱动配置信号。
可选地，连接于同一驱动数据走线DataL上的各个驱动器电路MIC，可以同时接收驱动配置信号并进行初始化配置。
可选地，外部电路可以同时向各个驱动数据走线DataL加载驱动配置信号，以便使得各个驱动器电路MIC可以同时接收驱动配置信号并完成初始化配置，减少阵列基板对驱动器电路MIC进行初始化配置的时间。
步骤S140，在器件控制阶段T4，接收驱动数据Data，根据驱动数据Data生成与各个输出引脚OUTP一一对应的驱动控制信号，驱动控制信号用于控制流经对应的输出引脚OUTP的电流。如此，在器件电源走线VLEDL上加载的器件电源电压VLED的作用下，驱动器电路MIC可以控制流经器件单元EC的电流，达成根据驱动数据Data驱动所连接的各个器件单元EC的目的。在步骤S140中，外部电路可以向驱动数据走线DataL加载驱动数据Data，驱动器电路MIC通过数据引脚DataP接收驱动数据Data。
在本公开的一种实施方式中，驱动数据Data包括地址信息和驱动信息。当驱动数据Data的地址信息与驱动器电路MIC的地址信息匹配时，获取驱动数据Data的驱动信息，并根据驱动数据Data的驱动信息生成驱动控制信号。
可选地，驱动器电路MIC的驱动方法还可以包括步骤S150，在下电阶段T5，驱动器电路MIC处于下电状态，不工作。可选地，可以不向芯片电源走线VCCL加载芯片电源电压VCC，进而使得驱动器电路MIC处于下电状态。进一步可选地，当驱动阵列基板的外部电路下电时，驱动器电路IC下电。换言之，当显示装置关机时，驱动器电路IC可以下电而处于下电阶段。
可选地，图7为阵列基板在驱动过程示意图。参见图7，阵列基板在工作时，还可以包括，在器件控制阶段T4之前，向器件电源走线VLEDL加载器件电源电压VLED。如此，器件单元EC可以在驱动器电路MIC的控制下工作，例如发光元件可以在驱动器电路MIC的控制下发光。
在本公开的一些实施方式中，输出引脚OUTP的数量为四个；驱动器电路MIC还包括数据引脚DataP、地址引脚Di_in、中继引脚Di_out、接地引脚GNDP和芯片电源 引脚VCCP。如此，在器件控制区域列BB中，阵列基板可以设置有与数据引脚DataP电连接的驱动数据走线DataL、地址引脚Di_in或者中继引脚Di_out电连接的地址走线ADDRL、与接地引脚GNDP电连接的接地电压走线GNDL、与芯片电源引脚VCCP电连接的芯片电源走线VCCL，以及包括用于向器件单元EC加载器件电源电压VLED的器件电源走线VLEDL。
在该实施方式中，驱动器电路MIC的各个引脚可以排列成多列，以利于驱动器电路MIC的制备。例如，驱动器电路MIC的各个引脚可以排列成三列(每列三个引脚)或者排列成两列。
在本公开的一种实施方式中，驱动器电路MIC的各个引脚(例如包括接地引脚GNDP、芯片电源引脚VCCP、数据引脚DataP、地址引脚Di_in、中继引脚Di_out和输出引脚OUTP等)排列成两个引脚列，每个引脚列包括直线排列的多个引脚；至少一个引脚列包括五个引脚。换言之，其中一个引脚列包括五个引脚，另一个引脚列可以包括其余引脚。其中，四个输出引脚OUTP均位于引脚列的端部；以利于四个输出引脚OUTP分别与四个器件单元EC电连接。
可选地，驱动器电路MIC具有两个接地引脚GNDP。这样，驱动器电路MIC包括十个引脚，每个引脚列包括五个引脚，这利于各个引脚的均一性，便于驱动器电路MIC的制备。进一步地，两个接地引脚GNDP位于同一引脚列以利于布线。更进一步地，两个接地引脚GNDP相邻设置。可以理解的是，驱动器电路MIC也可以具有一个接地引脚GNDP，驱动器电路MIC具有九个引脚。进一步地，具有接地引脚GNDP的引脚列，具有四个引脚。
可选地，芯片电源引脚VCCP和数据引脚DataP位于不同的引脚列中；如此，芯片电源引脚VCCP和数据引脚DataP可以分别位于接地电压走线GNDL的两侧。当然的，芯片电源引脚VCCP和数据引脚DataP也可以位于同一引脚列中；这样，芯片电源走线VCCL和驱动数据走线DataL可以位于接地电压走线GNDL的同一侧。
可选地，地址引脚Di_in和中继引脚Di_out位于同一引脚列中。如此，上一级驱动器电路MIC的中继引脚Di_out与下一级驱动器电路MIC的地址引脚Di_in均连接至同一地址走线ADDRL时，阵列基板的布线更为简单方便，可以减少走线之间的交叠面积，提高阵列基板的良率。
示例性地的，在本公开的一种实施方式中，参见图2，一个引脚列可以包括依次排列的地址引脚Di_in、芯片电源引脚VCCP和中继引脚Di_out；另一个引脚列可以包括数据引脚DataP和接地引脚GNDP。可以理解的是，该示例仅为驱动器电路MIC的引脚排列的一种方式，该驱动器电路MIC的引脚还可以通过其他方式进行排列，例如一个引脚列中设置地址引脚Di_in、数据引脚DataP和中继引脚Di_out，而另一个引脚列中设置芯片电源引脚VCCP和接地引脚GNDP等。
可选地，驱动器电路MIC的引脚与驱动器电路MIC的边缘之间的距离可以为 25～40微米，以利于驱动器电路的制备并避免该距离太大而增大驱动器电路的面积。
在本公开中，可以将引脚列中引脚的排列方向定义为第一方向，将两个引脚列的排列方向定义为第二方向。可选地，在同一引脚列中，相邻两个引脚之间的距离，可以为引脚在第一方向上的尺寸的0.8～1.2倍。如此，一方面可以扩大引脚与芯片焊盘在绑定时的工艺窗口，减少对准偏差引起的绑定不良；另一方面避免两个引脚之间的间距太大而导致驱动器电路面积增大，进而减小驱动器电路面积以降低阵列基板的成本。示例性地，驱动器电路的引脚在第一方向上的尺寸可以在80～120微米范围内，相邻两个引脚在第一方向上的间距可以在80～100微米范围内。
可选地，相邻两个引脚列之间的距离，可以为引脚在第二方向上的尺寸的0.8～1.2倍。如此，一方面可以扩大引脚与芯片焊盘在绑定时的工艺窗口，减少对准偏差引起的绑定不良；另一方面避免两个引脚之间的间距太大而导致驱动器电路面积增大，进而减小驱动器电路面积以降低阵列基板的成本。示例性地，驱动器电路的引脚在第二方向上的尺寸可以在120～150微米范围内，相邻两个引脚在第二方向上的间距可以在130～170微米范围内。
图12为本公开一种驱动器电路MIC的示例。在该示例中，仅仅示出了第一调制模块PWMM1而未示出其他的调制模块。参见图12，在该示例中，驱动器电路MIC可以包括电压调节电路C310、低压差稳压器C330、振荡器C340、控制逻辑模块CLM、地址驱动器C360、调光电路C370、晶体管C375和亮度控制电路C380。在各种实施方式中，驱动器电路MIC可以包括附加的、更少的或不同的部件。
电压调节电路C310将在芯片电源引脚VCCP处接收芯片电源电压VCC进行调节，以获得芯片电源电压VCC中的直流分量，以生成供电电压。在示例实施方式中，电压调节电路C310包括跟随有源跟随器的一阶RC滤波器。供电电压被提供给低压差稳压器C330。低压差稳压器C330将供电电压转换为用于为振荡器C340、控制逻辑模块CLM和其他部件(未示出)供电的稳定的直流电压(其可以逐步降低电压)。在示例实施方式中，稳定直流电压可以是1.8伏。振荡器C340提供时钟信号，时钟信号的最大频率例如可以为10MHz左右。
控制逻辑模块CLM接收来自数据引脚DataP的驱动数据Data、来自低压差稳压器C330的直流电压和来自振荡器C340的时钟信号。取决于阵列基板的工作阶段，控制逻辑模块CLM还可以从在地址引脚Di_in处接收的地址信号中接收数字数据；控制逻辑模块CLM可以输出使能信号C352、递增的数据信号C354、PWM时钟选择信号C356和最大电流信号C358。在地址配置阶段，控制逻辑模块CLM激活使能信号C352以启用地址驱动器C360。控制逻辑模块CLM经由地址引脚Di_in接收地址信号，储存该地址，并且将表示传出地址的递增后的数据信号C354提供到地址驱动器C360。当在地址配置阶段使能信号C352被激活的情况下，地址驱动器C360将递增后的数据信号C354缓存到中继引脚Di_out。控制逻辑模块CLM可以控制调光电路C370以在 地址配置阶段关断晶体管C375以有效地阻断来自器件单元的电流路径。
在器件控制阶段和驱动配置阶段期间，控制逻辑模块CLM将使能信号C352去激活并且地址驱动器C360的输出是三态以有效地将其从中继引脚Di_out解耦。在器件控制阶段期间，PWM时钟选择信号C356指定用于由PWM调光电路C370控制PWM调光的占空比。基于所选择的占空比，PWM调光电路C370控制晶体管C375的导通状态和截止状态的定时。在晶体管C375的导通状态期间，建立通过晶体管C375从输出引脚OUTP(耦接至器件单元，图12中以Out1为示例)到接地引脚GNDP的电流路径，并且亮度控制电路C380汇集经过器件单元的功能元件的驱动器电流。在晶体管C375的截止状态期间，电流路径被中断以阻止电流流过器件单元。当晶体管C375处于导通状态时，亮度控制电路C380从控制逻辑模块CLM接收最大电流信号C358并且控制流过功能元件(从输出引脚OUTP至接地引脚GNDP)的电流电平。在器件控制阶段期间，控制逻辑模块CLM控制PWM调光电路C370的占空比和亮度控制电路C380的最大电流C358以将器件单元中的LED设置为期望亮度。
可以理解的是，驱动器电路MIC中还可以包括压控恒流电路(图中未示出)，压控恒流电路的输入参考电压和输入参考电流，可以由芯片电源引脚VCCP处接收芯片电源电压VCC生成。压控恒流电路可以与亮度控制电路C380电连接。
参见图12，在调制模块中设置有短路检测器和断路检测器，其中，断路检测器由虚断方式连接的运算放大器构成，用于检测器件单元与驱动器电路MIC之间是否发生断路，其中，Vopen端可以为悬空信号端。短路检测器由虚短方式连接的运算放大器构成，来检测器件单元与驱动器电路MIC之间是否发生短路，其中，Vshort的电位可以与器件电源走线VLEDL传输的电源电压VLED的电位相同。
任意一个信号通道内，各器件单元与驱动器电路MIC之间发生短路和断路等信息，会汇集至其对应的驱动器电路MIC的控制逻辑模块CLM中，再通过该驱动器电路MIC的中继引脚Di_out(例如将信息按照编码规则依次附加在数据信号C354的后面)，逐级传输，直至由最后一级的驱动器电路MIC的中继引脚Di_out输出，并通过反馈走线FBL连接到外部电路。外部电路可以对反馈信息进行响应，及时发现驱动器电路MIC或者器件单元EC的异常。
在一些实施例中，在上电阶段和/或地址配置阶段，信号通道内的CRC(循环冗余校验码)校验信息，也可以通过同样的方式，由最后一级的驱动器电路MIC的中继引脚Di_out输出，并通过反馈走线FBL连接到外部电路。外部电路可以对反馈信息进行响应，及时发现驱动器电路MIC或者器件单元EC的异常。
在一些实施例中，如图12所示，驱动器电路MIC还包括数据选择器MUX和模数转换器ADC。驱动器电路MIC通过多个输出引脚OutP在与对应连接器件单元EC和器件电源走线VLEDL构成信号回路时，可以将多个信号回路的电信号传输给数据选择器MUX，并分时依次经由模数转换器ADC处理后传递给控制逻辑模块CLM， 再通过该驱动器电路MIC的中继引脚Di_out(例如将多个信号回路的电信号按照顺序以及编码规则附加在数据信号C354的后面)，逐级传输，直至由最后一级的驱动器电路MIC的中继引脚Di_out输出，并通过反馈走线FBL连接到外部电路。外部电路可以对反馈信息进行响应，调节其所输出的信号电平(例如器件电源电压VLED的电平)，进而降低阵列基板的功耗。
参见图12，驱动器电路MIC还可以设置有热关断延迟传感器TSD和热关断延迟(Thermal Shutdown)控制器TS。热关断延迟传感器TSD用于检测驱动器电路MIC的内部温度。当驱动器电路MIC的内部温度达到预设的保护温度(一般设置在150℃～170℃之间)时，热关断延迟控制器TS工作以关闭驱动器电路MIC的输出，降低驱动器电路MIC的功耗，进而降低驱动器电路MIC的内部温度。当驱动器电路MIC的内部温度降低至预设的重启温度(重启温度＝保护温度-延迟温度)时，驱动器电路MIC将重新输出。其中，延迟温度一般设置在15～30°范围内。热关断延迟(Thermal Shutdown)控制器TS可以与数据选择器MUX相连接，进而可以通过数据选择器MUX将异常信息反馈给控制逻辑模块CLM，以控制驱动器电路MIC的工作状态。
在一些实施方式中，在显示装置中，外部电路还可以包括用于驱动阵列基板的控制电路D110。参见图13，控制电路D110生成用以控制阵列基板的地址信号ADDR和驱动数据Data，并且经由驱动走线(VLEDL/ADDRL/GNDL/DataL等)将这些信号提供给驱动器电路MIC。控制电路D110可以包括定时控制器D210和桥接器D220。在各种实施方式中，控制电路D110可以包括附加的、更少的或不同的部件。例如，在一些实施方式中，可以使用现场可编程门阵列(FPGA)和/或PHY块来实现控制电路D110。控制电路D110由输入电压(VP)供电，并且连接至地(GND)。控制电路D110可以使用有源矩阵(AM)驱动方法或无源矩阵(PM)驱动方法来控制显示装置。
定时控制器D210生成指示用于驱动阵列基板的的像素的值和用于驱动像素的定时的图像控制信号D215。例如，定时控制器D210控制图像帧或视频帧的定时，并且控制驱动图像帧或视频帧内的器件单元(例如可以为位于LED灯区内的LED)中的每个器件单元的定时。此外，定时控制器D210控制在给定图像帧或视频帧期间用于驱动LED灯区中每个LED灯区的亮度。图像控制信号D215被定时控制器D210提供给桥接器D220。
桥接器D220将图像控制信号D215转换为地址信号ADDR和驱动数据Data的驱动器控制信号。例如，桥接器D220可以根据上述控制方案在寻址模式期间生成用于驱动器电路MIC组中的第一驱动器电路MIC的地址信号ADDR。
在膜层结构的角度上，参见图10，阵列基板可以包括依次层叠的衬底基11、驱动电路层200和器件层300，驱动电路层可以设置有绑定焊盘，例如设置有用于绑定功能元件的器件焊盘、用于绑定驱动器电路MIC的芯片焊盘和用于绑定外部电路的电路板焊盘等。器件层包括各个功能元件和各个驱动器电路MIC，各个功能元件与器件焊 盘绑定连接，各个驱动器电路MIC与芯片焊盘绑定连接。在本公开中，用于与同一驱动器电路MIC的各个引脚绑定连接的芯片焊盘可以组成一个芯片焊盘组。如此，阵列基板的驱动电路层可以包括多个芯片焊盘组，各个芯片焊盘组与各个驱动器电路MIC一一对应地绑定连接。
在本公开的一些实施方式中，驱动器电路MIC可以包括至少两个输出引脚OUTP、地址引脚Di_in、中继引脚Di_out、芯片电源引脚VCCP、数据引脚DataP、接地引脚GNDP。相应的，一个芯片焊盘组可以包括用于与各个输出引脚OUTP绑定连接的输出焊盘、与地址引脚Di_in绑定连接的地址焊盘、与中继引脚Di_out绑定连接的中继焊盘、与芯片电源引脚VCCP绑定连接的芯片电源焊盘、与数据引脚DataP绑定连接的数据焊盘、与接地引脚GNDP绑定连接的接地引脚等。进一步地，在驱动器电路MIC中，接地引脚GNDP的数量为两个且相邻设置；相应地，接地引脚的数量为两个且相邻设置。如此，可以保证接地引脚GNDP与接地电压走线GNDL之间的充分电连接(例如具有较大的连接面积和较小的接触电阻、较小的阻抗等)，提高加载至驱动器电路MIC上的接地电压GND的稳定性。另外，设置两个接地引脚GNDP还可以避免设置面积太大的接地引脚GNDP，进而避免接地引脚GNDP面积太大而导致与接地引脚之间容易出现结合力不足的不良。
在阵列基板上，芯片焊盘组中的芯片焊盘的设置方式，可以根据驱动器电路MIC的引脚排布方式进行设置，以能够满足驱动器电路MIC与芯片焊盘组的绑定为准，本公开对此不做特殊的限制。
在本公开中，衬底基板11可以为无机材料的衬底基板，也可以为有机材料的衬底基板，或者可以为有机材料和无机材料层叠复合而成的衬底基板。举例而言，在本公开的一种实施方式中，衬底基板的材料可以为钠钙玻璃(soda-lime glass)、石英玻璃、蓝宝石玻璃等玻璃材料，或者可以为不锈钢、铝、镍等金属材料。在本公开的另一种实施方式中，衬底基板的材料可以为聚甲基丙烯酸甲酯(Polymethyl methacrylate，PMMA)、聚乙烯醇(Polyvinyl alcohol，PVA)、聚乙烯基苯酚(Polyvinyl phenol，PVP)、聚醚砜(Polyether sulfone，PES)、聚酰亚胺、聚酰胺、聚缩醛、聚碳酸酯(Poly carbonate，PC)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，PET)、聚萘二甲酸乙二酯(Polyethylene naphthalate，PEN)或其组合。
可选地，参见图10和图11，驱动电路层200可以包括依次层叠于衬底基板11一侧的驱动走线层102、第一绝缘层117和金属布线层105。其中，驱动走线层102可以形成有用于加载信号的驱动走线(例如接地电压走线GNDL、器件电源走线VLEDL、地址走线ADDRL、驱动数据走线DataL、芯片电源走线VCCL、反馈走线FBL等)；金属布线层105可以形成绑定焊盘(例如101/107)和布线走线WW。其中，布线走线WW可以用于绑定焊盘之间(例如器件单元EC的各个功能元件对应的器件焊盘之间)、绑定焊盘与驱动走线之间(例如芯片焊盘与驱动走线之间、器件焊盘与驱动走线 之间)的电连接。其中，驱动走线与布线走线之间，可以通过贯穿第一绝缘层117的过孔电连接。在本公开的一种实施方式中，驱动走线层的厚度可以大于金属布线层，以便降低驱动走线的方阻，降低信号在驱动走线上的压降。
可选的，驱动走线层102的厚度约为1.5μm～7μm，其材料可以包括铜，例如可以通过溅射的方式形成例如MoNb/Cu/MoNb的叠层材料，叠层中靠近衬底基板的一侧材料为MoNb，厚度大约在
Figure PCTCN2021101304-appb-000001
左右，主要用于提高膜层与衬底基板的粘附力，叠层的中间层材料为Cu，为电信号传递通道的优选材料，远离衬底基板一侧的材料为MoNb，厚度大约在
Figure PCTCN2021101304-appb-000002
左右，可以用于保护中间层，防止电阻率低的中间层表面暴露发生氧化。由于单次溅射的厚度一般不超过1μm，因此在制作超过1μm的驱动走线层时，需要多次溅射来形成。此外，驱动走线层还可以通过电镀的方式形成，具体地，可以先利用MoNiTi形成种子层，以提高后续电镀工艺中金属晶粒的成核密度，之后再通过电镀制作电阻率低的铜，之后再制作防氧化层，材料可以为MoNiTi。可选地，驱动走线层远离衬底基板一侧的表面可以被第一绝缘层覆盖，以保证电气通路的可靠性和稳定性。
可选的，金属布线层105设置有用于与电子元件(例如功能元件、驱动器电路MIC和外部电路)绑定的焊盘(例如用于绑定功能元件的器件焊盘、用于绑定驱动器电路MIC的芯片焊盘和用于绑定外部电路的电路板焊盘)。金属布线层的膜层厚度大约在
Figure PCTCN2021101304-appb-000003
左右。为了防止从阵列基板制程到将电子元件设置在基板上的制程过程中，焊盘暴露在空气中可能会产生氧化的问题，可以只在焊盘暴露的表面区域设置防氧化材料层，即焊盘区域的表面会比布线走线所在区域多出一层结构；或者将金属布线层整体设置为至少两层结构的叠层结构，其远离衬底基板的膜层材料为防氧化的金属或者合金材料，具体地可以由例如MoNb/Cu/CuNi的叠层结构构成，叠层中的底层材料MoNb主要用于提高粘附力，叠层中的中间层Cu由于电阻率低主要用于传递电信号，叠层中的顶层CuNi既可以防止中间层氧化，又可以保证与电子元件连接的牢固性。布线走线远离衬底基板一侧的表面会被第二绝缘层108覆盖，以保证电气通路的可靠性和稳定性。
示例性地，驱动布线层中，驱动走线可以包括器件电源走线VLEDL、接地电压走线GNDL、地址走线ADDRL、芯片电源走线VCCL、驱动数据走线DataL等。其中，输出引脚OUTP与器件单元EC的器件焊盘之间、地址焊盘与地址走线ADDRL之间、芯片电源焊盘与芯片电源走线VCCL之间、数据焊盘与驱动数据走线DataL之间、器件单元EC的器件焊盘与器件电源走线VLEDL之间、部分地址焊盘与地址走线ADDRL之间均通过布线走线电连接。
在一些实施方式中，接地焊盘与接地电压走线GNDL之间可以通过布线走线电连接。当然的，在本公开的其他实施方式中，接地焊盘与接地电压走线GNDL之间也可以通过过孔直接连接。
可选地，阵列基板还可以包括位于衬底基板11与驱动走线层102之间的缓冲层109，以及包括位于第一绝缘层117与金属布线层105之间的第一平坦层110，依次位于第二绝缘层108背离金属布线层一侧的第二平坦层111和反射层112，位于周边区的绑定焊盘107上的透明电极113，以及位于透明电极113与外部电路(例如柔性电路板FPC)之间的异方性导电胶114。其中，缓冲层109可以避免衬底基板中的杂质对驱动走线层导电性能的影响，第一平坦层110可以为第二导电层104的制作提供一个平坦的表面，第二平坦层110可以为后续绑定功能元件FE和驱动器电路MIC提供一个平坦的表面，反射层112的材料可以为白色油墨，用于提高阵列基板的反射率以减小光损耗，透明电极113和异方性导电胶114用于实现周边区的绑定焊盘107(例如电路板绑定焊盘)与柔性电路板FPC的电连接。衬底基板的材料可以为玻璃、石英、塑料、聚酰亚胺、PET、PMMA等材质。
图11为本公开的阵列基板的另外一些实施方式中的结构示意图。在图11中，并未示出各个功能元件和驱动器电路。参见图11，阵列基板可以包括：衬底基板11；位于衬底基板11上的缓冲层109；位于缓冲层109远离衬底基板一侧的驱动走线层102；位于驱动走线层102远离衬底基板一侧的第一绝缘层117；位于第一绝缘层117远离衬底基板一侧的第一平坦层110；位于第一平坦层110远离衬底基板一侧的第二导电层105；位于第二导电层105远离衬底基板一侧的第二绝缘层116；和位于第二绝缘层116远离衬底基板一侧的第二平坦层111。
如图11所示，第二绝缘层116位于第一平坦层110与第二平坦层111之间。在第二平坦层111的材质为有机绝缘材料的情况下，可以在第二绝缘层116中设置有多个放气孔1160。该多个放气孔1160分别暴露位于下方的第一平坦层110的一部分。在制造所述阵列基板的过程中，通过放气孔1160，聚集于第一平坦层110中的气体可以得到释放，从而可以避免阵列基板的膜层出现翘曲、剥离等问题，从而能够提高产品良率。
例如，在图11所示的实施例中，设置有多个放气孔1160，但是，这仅是示意性的，而不是对本公开实施例的限制。在其他实施例中，可以设置更多数量或更少数量的放气孔。
在本公开的一些实施方式中，参见图10，阵列基板还可以包括位于器件层远离衬底基板一侧的封装层13。封装层13包括用于将功能元件FE封装在衬底基板上的层状结构。在一些示例性实施例中，将封装胶涂覆在阵列基板中功能元件FE的表面，干燥后形成所述封装层13。所述封装胶的材料可以包括透明的光固化或热固化树脂，即，所述封装层13的材料可以为透明保护胶。在一些实施例中，封装层13可以包括多个透明保护结构30。
参见图10，功能元件FE的引脚分别通过焊锡膏T与器件焊盘101连接，各个器 件焊盘101再根据功能元件所在电气回路中的位置进行连接。
需要说明的是，尽管在附图中以特定顺序描述了本公开中驱动器电路的驱动方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (16)

  1. 一种驱动器电路，包括逻辑控制模块、数据引脚和至少两个输出引脚；所述数据引脚用于接收驱动数据；所述逻辑控制模块被配置为根据所述驱动数据生成与各个所述输出引脚一一对应的驱动控制信号，所述驱动控制信号用于控制流经对应的所述输出引脚的电流。
  2. 根据权利要求1所述的驱动器电路，其中，所述驱动数据包括地址信息和驱动信息；
    所述逻辑控制模块还被配置为，当所述驱动数据的地址信息与所述驱动器电路的地址信息匹配时，获取所述驱动数据的驱动信息，并根据所述驱动数据的驱动信息生成所述驱动控制信号。
  3. 根据权利要求2所述的驱动器电路，其中，所述驱动器电路还包括地址引脚和中继引脚；
    所述地址引脚能够接收地址信号；
    所述逻辑控制模块还被配置为，根据所述地址信号配置所述驱动器电路的地址信息，并生成中继信号；所述中继信号能够作为接续的驱动器电路的地址信号；
    所述中继引脚用于输出所述中继信号。
  4. 根据权利要求3所述的驱动器电路，其中，所述输出引脚的数量为四个；所述驱动器电路还包括接地引脚和芯片电源引脚；所述接地引脚用于向所述驱动器电路加载接地电压；所述芯片电源引脚用于向所述驱动器电路加载用于驱动所述驱动器电路工作的芯片电源电压；
    其中，所述驱动器电路的各个引脚排列成两个引脚列，每个所述引脚列包括直线排列的多个引脚；至少一个所述引脚列包括五个引脚；
    四个所述输出引脚均位于所述引脚列的端部；所述芯片电源引脚和所述数据引脚位于不同的所述引脚列中；所述地址引脚和所述中继引脚位于同一所述引脚列中。
  5. 一种驱动器电路的驱动方法，其中，所述驱动器电路包括至少两个输出引脚；所述驱动器电路的驱动方法包括：
    在器件控制阶段，接收驱动数据，根据所述驱动数据生成与各个所述输出引脚一一对应的驱动控制信号，所述驱动控制信号用于控制流经对应的所述输出引脚的电流。
  6. 根据权利要求5所述的驱动器电路的驱动方法，其中，所述驱动数据包括地址信息和驱动信息；所述驱动器电路的驱动方法还包括：
    在地址配置阶段，接收地址信号，根据所述地址信号配置所述驱动器电路的地址信息，并生成和输出中继信号；所述中继信号能够作为接续的驱动器电路的地址信号；
    根据所述驱动数据生成与各个所述输出引脚一一对应的驱动控制信号包括：
    当所述驱动数据的地址信息与所述驱动器电路的地址信息匹配时，获取所述驱动数据的驱动信息，并根据所述驱动数据的驱动信息生成所述驱动控制信号。
  7. 一种阵列基板，包括阵列设置的多个器件控制区域；在任意一个所述器件控制区域内，所述阵列基板设置有权利要求1～4任意一项所述的驱动器电路，以及设置有与所述驱动器电路的各个所述输出引脚一一对应连接的器件单元；任意一个所述器件单元包括一个功能元件或者多个电连接的功能元件。
  8. 根据权利要求7所述的阵列基板，其中，所述器件控制区域排列成多个器件控制区域列；任意一个所述器件控制区域列包括沿列方向依次排列的多个器件控制区域；
    在任意一个所述器件控制区域列，所述阵列基板设置有沿所述列方向延伸的器件电源走线和驱动数据走线；所述器件单元的一端与所述器件电源走线电连接，另一端与对应的所述输出引脚电连接；所述数据引脚与所述驱动数据走线电连接。
  9. 根据权利要求8所述的阵列基板，其中，位于同一所述器件控制区域列中的各个所述驱动器电路依次级联；所述驱动器电路还包括地址引脚和中继引脚；
    在任意一个所述器件控制区域列，所述阵列基板设置有与各个所述驱动器电路一一对应的多个地址走线，且各个所述地址走线沿所述列方向延伸；
    所述驱动器电路的地址引脚与对应的所述地址走线电连接，上一级所述驱动器电路的中继引脚与下一级所述驱动器电路对应的所述地址走线电连接。
  10. 根据权利要求9所述的阵列基板，其中，在任意一个所述器件控制区域列，所述阵列基板还设置有沿所述列方向延伸的芯片电源走线和接地电压走线；
    所述驱动器电路还包括芯片电源引脚和接地引脚，所述芯片电源引脚用于向所述驱动器电路加载用于驱动所述驱动器电路工作的芯片电源电压；所述芯片电源走线与所述芯片电源引脚电连接；所述接地引脚用于向所述驱动器电路加载接地电压，所述接地引脚与所述接地电压走线电连接。
  11. 根据权利要求10所述的阵列基板，其中，在任意一个所述器件控制区域列，所述器件单元排列成两个器件单元列，任意一个所述器件单元列包括沿所述列方向依次排列的多个器件单元；
    在任意一个所述器件控制区域列中，所述器件电源走线的数量为两个；两个所述器件电源走线分别位于所述接地电压走线的两侧，且与两个所述器件单元列一一对应设置；
    所述器件单元列中的各个所述器件单元，均电连接至对应的所述器件电源走线。
  12. 根据权利要求11所述的阵列基板，其中，在任意一个所述器件控制区域列中，所述地址走线、所述驱动数据走线和所述芯片电源走线均位于所述器件电源走线与所述接地电压走线之间。
  13. 根据权利要求11所述的阵列基板，其中，在至少一个所述器件控制区域列中，所述阵列基板还设置有反馈走线；在所述器件控制区域列中，最后一级所述驱动器电路的中继引脚，与所述反馈走线电连接；所述反馈走线位于所述器件电源走线和所述接地电压走线之间。
  14. 根据权利要求11所述的阵列基板，其中，相邻两个所述器件控制区域列中，相邻的两个所述器件电源走线相互连接成一个走线。
  15. 根据权利要求11所述的阵列基板，其中，所述阵列基板包括依次层叠设置的衬底基板、驱动电路层和器件层；
    其中，所述驱动电路层包括依次层叠于所述衬底基板的驱动走线层、第一绝缘层和金属布线层；所述驱动走线层的厚度大于所述金属布线层的厚度；
    所述接地电压走线、所述器件电源走线、所述芯片电源走线、所述驱动数据走线和所述地址走线位于所述驱动走线层；
    所述金属布线层设置有器件焊盘、芯片焊盘和布线走线；所述功能元件和所述驱动器电路位于所述器件层；所述功能元件与所述器件焊盘绑定连接，所述驱动器电路与所述芯片焊盘绑定连接，所述器件焊盘和所述芯片焊盘与所述驱动走线层之间，通过所述布线走线电连接。
  16. 一种显示装置，包括权利要求7～15任意一项所述的阵列基板。
PCT/CN2021/101304 2021-06-21 2021-06-21 驱动器电路及其驱动方法、阵列基板和显示装置 WO2022266810A1 (zh)

Priority Applications (6)

Application Number Priority Date Filing Date Title
EP21946312.2A EP4224461A4 (en) 2021-06-21 2021-06-21 DRIVING CIRCUIT AND ASSOCIATED DRIVING METHOD, MATRIX SUBSTRATE AND DISPLAY DEVICE
CN202180001566.4A CN115968493A (zh) 2021-06-21 2021-06-21 驱动器电路及其驱动方法、阵列基板和显示装置
PCT/CN2021/101304 WO2022266810A1 (zh) 2021-06-21 2021-06-21 驱动器电路及其驱动方法、阵列基板和显示装置
US18/016,716 US20230282172A1 (en) 2021-06-21 2021-06-21 Driver circuit, driving method of the driver circuit, array substrate, and display device
JP2023524803A JP2024525257A (ja) 2021-06-21 2021-06-21 ドライバ回路及びその駆動方法、アレイ基板、並びに表示装置
TW110136420A TWI838650B (zh) 2021-06-21 2021-09-30 驅動器電路及其驅動方法、陣列基板和顯示裝置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/101304 WO2022266810A1 (zh) 2021-06-21 2021-06-21 驱动器电路及其驱动方法、阵列基板和显示装置

Publications (1)

Publication Number Publication Date
WO2022266810A1 true WO2022266810A1 (zh) 2022-12-29

Family

ID=84543859

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/101304 WO2022266810A1 (zh) 2021-06-21 2021-06-21 驱动器电路及其驱动方法、阵列基板和显示装置

Country Status (6)

Country Link
US (1) US20230282172A1 (zh)
EP (1) EP4224461A4 (zh)
JP (1) JP2024525257A (zh)
CN (1) CN115968493A (zh)
TW (1) TWI838650B (zh)
WO (1) WO2022266810A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024152287A1 (zh) * 2023-01-19 2024-07-25 京东方科技集团股份有限公司 驱动芯片及装置、配置方法、背光模组、显示设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070139316A1 (en) * 2005-12-21 2007-06-21 Sony Ericsson Mobile Communications Ab Led module with integrated controller
CN101336026A (zh) * 2008-07-11 2008-12-31 北京巨数数字技术开发有限公司 一种集成单线控制装置的led发光元件
WO2010004871A1 (ja) * 2008-07-11 2010-01-14 シャープ株式会社 バックライト駆動装置、それを備える表示装置、およびバックライト駆動方法
CN109323135A (zh) * 2018-10-24 2019-02-12 浙江鼎鑫工艺品有限公司 一种集成控制芯片和led晶片的灯丝
CN112489588A (zh) * 2019-08-24 2021-03-12 华源智信半导体(深圳)有限公司 对显示装置中驱动器的动态的地址分配

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DK0725939T3 (da) * 1992-03-13 1999-11-15 Kopin Corp Skærmsystem til anbringelse på hovedet
TWI254899B (en) * 2002-06-21 2006-05-11 Himax Tech Inc Method and related apparatus for driving an LCD monitor
CN102472906B (zh) * 2009-08-31 2014-09-24 夏普株式会社 驱动装置、背光源单元和图像显示装置
US9153171B2 (en) * 2012-12-17 2015-10-06 LuxVue Technology Corporation Smart pixel lighting and display microcontroller
CN106302072A (zh) * 2015-06-10 2017-01-04 晶门科技（深圳）有限公司 与串联连接装置通信的系统和方法
US10950194B1 (en) * 2019-10-04 2021-03-16 Solomon Systech (Shenzhen) Limited Display panel with distributed driver network
CN212628502U (zh) * 2020-05-22 2021-02-26 昂宝电子（上海）有限公司 Led背光驱动电路及用于该电路的控制芯片
EP4033476A4 (en) * 2020-11-30 2023-01-25 Samsung Electronics Co., Ltd. DISPLAY MODULE AND DISPLAY DEVICE COMPRISING IT

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070139316A1 (en) * 2005-12-21 2007-06-21 Sony Ericsson Mobile Communications Ab Led module with integrated controller
CN101336026A (zh) * 2008-07-11 2008-12-31 北京巨数数字技术开发有限公司 一种集成单线控制装置的led发光元件
WO2010004871A1 (ja) * 2008-07-11 2010-01-14 シャープ株式会社 バックライト駆動装置、それを備える表示装置、およびバックライト駆動方法
CN109323135A (zh) * 2018-10-24 2019-02-12 浙江鼎鑫工艺品有限公司 一种集成控制芯片和led晶片的灯丝
CN112489588A (zh) * 2019-08-24 2021-03-12 华源智信半导体(深圳)有限公司 对显示装置中驱动器的动态的地址分配

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4224461A4 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024152287A1 (zh) * 2023-01-19 2024-07-25 京东方科技集团股份有限公司 驱动芯片及装置、配置方法、背光模组、显示设备

Also Published As

Publication number Publication date
EP4224461A1 (en) 2023-08-09
EP4224461A4 (en) 2023-12-27
CN115968493A (zh) 2023-04-14
TW202301311A (zh) 2023-01-01
US20230282172A1 (en) 2023-09-07
TWI838650B (zh) 2024-04-11
JP2024525257A (ja) 2024-07-12

Similar Documents

Publication Publication Date Title
EP3333906B1 (en) Led component, led panel and led display screen
EP3128504B1 (en) Mounting substrate and electronic device
US8094102B2 (en) Single full-color LED with driving mechanism
KR20210023762A (ko) 단일 패키지 발광 다이오드 및 드라이버 회로를 갖는 디스플레이 디바이스
CN114023248A (zh) 用于控制分布式驱动电路的具有二维共享线的显示装置
CN114283740A (zh) 显示装置和用于显示装置的驱动器电路
CN105304016B (zh) 智能全彩玻璃显示屏
WO2022170672A1 (zh) 阵列基板、背光模组及显示面板
WO2022266810A1 (zh) 驱动器电路及其驱动方法、阵列基板和显示装置
KR102287177B1 (ko) 투명 발광 장치
JP2023527096A (ja) 発光基板及びその駆動方法、表示装置
WO2022120605A1 (zh) 阵列基板、发光基板和显示装置
TW202429431A (zh) 驅動器電路及其驅動方法、陣列基板和顯示裝置
US20230387140A1 (en) Light-emitting substrate and display device
TWI705579B (zh) 主動式rgb發光二極體顯示器載板
WO2023087155A1 (zh) 驱动器电路及其驱动方法、阵列基板、显示装置
GB2467797A (en) Single full-colour LED with driving mechanism
WO2023004798A1 (zh) 发光基板及其制造方法、背光源、显示装置
WO2024130716A1 (zh) 发光模组和显示装置
TWI736982B (zh) 主動式rgb發光二極體像素元件
WO2023077281A1 (zh) 发光基板和显示装置
WO2024016332A1 (zh) 布线基板及电子装置
CN219040506U (zh) 一种led发光器件及led发光模组
WO2022147791A1 (zh) 阵列基板、其驱动方法及显示装置
CN118038816A (zh) 一种驱动背板及其驱动方法、发光装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21946312

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2023524803

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2021946312

Country of ref document: EP

Effective date: 20230502

NENP Non-entry into the national phase

Ref country code: DE