WO2023004797A1 - 发光基板、背光源、显示装置 - Google Patents

发光基板、背光源、显示装置 Download PDF

Info

Publication number
WO2023004797A1
WO2023004797A1 PCT/CN2021/109826 CN2021109826W WO2023004797A1 WO 2023004797 A1 WO2023004797 A1 WO 2023004797A1 CN 2021109826 W CN2021109826 W CN 2021109826W WO 2023004797 A1 WO2023004797 A1 WO 2023004797A1
Authority
WO
WIPO (PCT)
Prior art keywords
light
signal line
emitting
sub
column
Prior art date
Application number
PCT/CN2021/109826
Other languages
English (en)
French (fr)
Inventor
刘纯建
许邹明
田�健
吴信涛
雷杰
王杰
张建英
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/109826 priority Critical patent/WO2023004797A1/zh
Priority to US17/757,792 priority patent/US20230034742A1/en
Priority to CN202180002034.2A priority patent/CN116324601A/zh
Publication of WO2023004797A1 publication Critical patent/WO2023004797A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present disclosure relates to the field of optical technology, and in particular to a luminescent substrate, a backlight source including the luminescent substrate, and a display device including the luminescent substrate.
  • Display devices are generally divided into two categories: liquid crystal display devices and organic light-emitting diode display devices.
  • Liquid crystal display devices are widely used due to their advantages of thinness, lightness, good shock resistance, wide viewing angle, and high contrast.
  • a liquid crystal display device generally includes a display panel and a backlight, and the backlight is usually arranged on a non-display side of the display panel to provide a light source for the display operation of the display panel. Characteristics such as contrast ratio, brightness uniformity and stability of the liquid crystal display device are related to the structure and performance of the backlight source.
  • a light emitting substrate including: a light emitting area and a peripheral area surrounding the light emitting area.
  • the peripheral area includes a first area, the first area is located between the first side of the light-emitting substrate and the light-emitting area, and the light-emitting substrate further includes a first signal line, the first signal line comprising a first part and/or a second part, the first part of the first signal line extends along a first direction in the first region, the second part of the first signal line extends into the light emitting region, When the first signal line includes a first portion and a second portion, the first portion of the first signal line is connected to the second portion.
  • the peripheral region further includes a second region located between a second side of the light-emitting substrate opposite to the first side and the light-emitting region, and the The light-emitting substrate further includes a second signal line, a first part of the second signal line extends along the first direction in the second region, and a second part of the second signal line extends to the light-emitting region inside, and the first part of the second signal line is connected to the second part.
  • the second portion of the first signal line includes at least one strip structure extending along the first direction, the first portion and the second portion of the first signal line pass through the first signal line
  • the third part of the line is connected; and/or the second part of the second signal line includes at least one strip structure extending along the first direction, and the first part and the second part of the second signal line pass through the The third part of the second signal line is connected.
  • the light emitting region includes a plurality of sub-light emitting regions arranged in an array, and the plurality of sub-light emitting regions are arranged in M rows along the first direction and arranged in M rows along a second direction crossing the first direction.
  • N columns, M and N are both positive integers greater than or equal to 1.
  • the first part of the first signal line is arranged between the first row of sub-light-emitting regions and the first side of the light-emitting substrate, and each of the at least one strip-like structure of the second part of the first signal line is arranged In the corresponding column of sub-light-emitting regions of columns 1 to X.
  • Each of the at least one strip structure of the second part of the second signal line is arranged in a corresponding column of sub-light-emitting areas in the Y-Nth column, and the first part of the second signal line is arranged in the sub-light-emitting area of the N-th column. Between the region and the second side of the light-emitting substrate, 1 ⁇ X ⁇ Y ⁇ N.
  • the light-emitting substrate further includes a first conductive part located on the same layer as the first signal line, and the first conductive part includes N-1 driving voltage signal lines extending along the first direction.
  • Each of the 2nd to N columns of sub-light-emitting regions includes a driving voltage signal line, and each of the plurality of sub-light-emitting regions includes at least one light-emitting unit, and in each of the 2nd to N columns of sub-light-emitting regions,
  • the driving voltage signal line is connected to the first end of each light-emitting unit in the column of sub-light-emitting areas, and the first part of the first signal line is connected to the first end of each light-emitting unit in the first column of sub-light-emitting areas. connect.
  • the width of the first portion of the first signal line along the second direction is smaller than the width of each driving voltage signal line along the second direction.
  • the light-emitting substrate further includes a second conductive portion, wherein the second conductive portion includes a plurality of pads.
  • the first conductive portion and the second conductive portion are located at the same layer.
  • the first conductive portion further includes N ⁇ 1 common voltage signal lines extending along the first direction, and the first conductive portion and the second signal line are located on the same layer.
  • Each of the 1st to N-1 sub-light emitting regions includes a common voltage signal line, and each of the plurality of sub-light emitting regions further includes a driving circuit connected to the second end of the at least one light emitting unit.
  • the common voltage signal line is connected to each driving circuit in the column of sub-light emitting regions, and the first part of the second signal line is connected to the first part of the Nth column of sub-light emitting regions. of each drive circuit connection.
  • the width of the first portion of the second signal line along the second direction is smaller than the width of each common voltage signal line along the second direction.
  • the driving voltage signal line, the light emitting unit, the driving circuit, and the common voltage signal line are along the The second direction is arranged sequentially.
  • the first conductive portion further includes N feedback signal lines extending along the first direction, and each column of sub-light emitting regions includes a feedback signal line.
  • each driving circuit is cascaded in sequence, and the feedback signal line is connected to the last-level driving circuit.
  • the feedback signal line is located on a side away from the driving circuit from the common voltage signal line in the same column of sub-light emitting regions as the feedback signal line.
  • the feedback signal line in each of the first to X columns of sub-light emitting regions, is located in the same column of the sub-light emitting region as the feedback signal line, and the common voltage signal line is far away from the driving circuit.
  • the feedback signal line In each column of the sub-light-emitting regions of the Y-Nth columns, the feedback signal line is located in the sub-light-emitting region of the same column as the feedback signal line, and the drive voltage signal line is far away from the driving circuit. side.
  • the light-emitting substrate further includes a substrate, a buffer layer, and an insulating layer.
  • the buffer layer is located between the layer where the first conductive part and the second conductive part are located and the substrate, and the insulating layer is located in the layer where the first conductive part and the second conductive part are located side away from the substrate.
  • the light-emitting substrate further includes a binding electrode located in the peripheral region.
  • the binding electrode includes an effective terminal and a vacant terminal, the first part and the second part of the first signal line, the first part and the second part of the second signal line, and the first conductive part are all connected to the Valid terminal connections for bonded electrodes described above.
  • the common voltage signal line includes a first connection portion
  • the driving voltage signal line includes a second connection portion
  • the common voltage signal line passes through the connection between the first connection portion and the binding electrode.
  • the effective terminal is connected
  • the driving voltage signal line is connected to the effective terminal of the binding electrode through the second connection part;
  • the connection part is only located in the sub-light-emitting area of the column;
  • the second connection part of the driving voltage signal line in each column of the sub-light-emitting areas of the 2nd to N columns is only located in the sub-light-emitting area of the column.
  • the light emitting substrate further includes a substrate.
  • the first conductive part and the second conductive part are located in different layers, the first conductive part is located on the substrate, and the second conductive part is located on a side of the first conductive part away from the substrate. side.
  • the light emitting region includes a plurality of sub-light emitting regions arranged in an array, and the plurality of sub-light emitting regions are arranged in M rows along the first direction and arranged in M rows along a second direction crossing the first direction.
  • N columns, M and N are both positive integers greater than or equal to 1.
  • the first signal line includes a second portion, the second portion of the first signal line includes N sub-signal lines extending along the first direction, and each of the N columns of sub-light emitting regions includes a sub-signal line.
  • each of the plurality of sub-light-emitting regions includes at least one light-emitting unit, each of the at least one light-emitting unit includes a plurality of light-emitting elements connected to each other, and the sub-light-emitting regions in the first row
  • the sub-signal line is located at least part of the light-emitting elements among the plurality of light-emitting elements of each light-emitting unit in the row of sub-light-emitting regions, away from the first side of the light-emitting substrate, and the N-th column of sub-light-emitting regions.
  • the sub-signal lines are located at least part of the light-emitting elements among the plurality of light-emitting elements of each light-emitting unit in the row of sub-light-emitting regions, on the side away from the second side of the light-emitting substrate, and the second side is connected to the first side of the light-emitting substrate. Opposite sides.
  • the material of the first conductive portion and the second conductive portion includes copper.
  • the light-emitting substrate further includes a shielding ring.
  • the shielding ring at least partially surrounds the periphery of the light emitting area, and the signal received by the shielding ring is the same as that received by the common voltage signal line.
  • each of the at least one light emitting unit includes a plurality of light emitting elements connected to each other, and each of the plurality of light emitting elements includes a submillimeter light emitting diode or a micro light emitting diode.
  • a backlight comprising the light-emitting substrate described in any one of the preceding embodiments.
  • a display device which includes the light emitting substrate described in any one of the foregoing embodiments.
  • Fig. 1 shows a schematic diagram of arrangement of first signal lines and second signal lines of a light-emitting substrate according to an embodiment of the present disclosure
  • FIG. 2 shows a schematic layout of a light-emitting substrate provided according to an embodiment of the present disclosure
  • FIG. 3 shows a schematic layout of a light-emitting substrate provided according to an embodiment of the present disclosure
  • FIG. 4 shows a schematic diagram of the arrangement of terminals of the drive circuit of the light-emitting substrate in FIG. 3;
  • FIG. 5 shows a schematic layout of a light-emitting substrate provided according to an embodiment of the present disclosure
  • FIG. 6 shows a schematic diagram of the arrangement of terminals of the drive circuit of the light-emitting substrate in FIG. 5;
  • Fig. 7A shows the connection mode of the signal line of the light-emitting substrate and the binding electrode in the related art
  • Fig. 7B shows the connection mode of the signal line and the binding electrode of the light-emitting substrate according to an embodiment of the present disclosure
  • FIG. 8 shows a schematic structural view of a light-emitting substrate provided according to an embodiment of the present disclosure
  • FIG. 9 shows a schematic layout of light emitting units of a light emitting substrate according to an embodiment of the present disclosure.
  • FIG. 10 shows a schematic layout of a light-emitting substrate according to an embodiment of the present disclosure
  • Fig. 11A shows a schematic layout of the central area of the light-emitting substrate provided according to an embodiment of the present disclosure
  • FIG. 11B shows a schematic layout of the left area of the light-emitting substrate according to an embodiment of the present disclosure
  • Fig. 11C shows a schematic layout of the right area of the light-emitting substrate according to an embodiment of the present disclosure
  • Figure 12 shows a block diagram of a backlight provided according to an embodiment of the present disclosure.
  • FIG. 13 shows a block diagram of a display device provided according to an embodiment of the present disclosure.
  • Signal lines are generally arranged near both side edges of the substrate of the display device (eg, left and right edges of the display device when a user faces the display device).
  • the signal lines near the two sides of the substrate are usually designed to have a narrower width.
  • a signal line with a smaller width will cause the signal line to have a larger resistance and a larger voltage drop, thereby affecting the luminous efficiency of the display device, and making the luminous brightness of the central area and the edge areas on both sides of the display device uneven.
  • the resistance and voltage drop of the signal line are usually reduced by increasing the thickness of the signal line, but this greatly increases the material consumption and process of the signal line, thus Increased production costs and reduced production efficiency.
  • FIG. 1 shows a schematic layout of the light-emitting substrate 100 .
  • the light emitting substrate 100 includes a light emitting region 101 and a peripheral region 102 surrounding the light emitting region 101 .
  • the peripheral area 102 includes a first area 1021 located between the first side 001 of the light emitting substrate 100 and the light emitting area 101 .
  • the light-emitting substrate 100 further includes a first signal line 103, the first signal line 103 includes a first portion 1031 and/or a second portion 1032, the first portion 1031 of the first signal line 103 extends along the first direction D1 in the first region 1021, The second portion 1032 of the first signal line 103 extends into the light emitting area 101 , and when the first signal line 103 includes the first portion 1031 and the second portion 1032 , the first portion 1031 of the first signal line 103 is connected to the second portion 1032 .
  • FIG. 1 shows that the first signal line 103 includes a first portion 1031 and a second portion 1032, as expressed in “the first signal line 103 includes a first portion 1031 and/or a second portion 1032”,
  • the first signal line 103 may include only the first portion 1031 , or only the second portion 1032 , or both the first portion 1031 and the second portion 1032 .
  • the first portion 1031 of the first signal line 103 is located between the first side 001 of the light-emitting substrate 100 and the light-emitting region 101, in other words, the first portion 1031 of the first signal line 103 is located in the frame area of the light-emitting substrate 100, that is, FIG. 1 The left frame area of the light-emitting substrate 100 in .
  • the first signal line 103 can be various appropriate types of signal lines, such as a signal line for transmitting voltage, a signal line for transmitting driving data, and a wiring for connecting two components or multiple components.
  • the type of the wire 103 is not specifically limited.
  • the first signal line 103 When the first signal line 103 includes a first portion 1031 and a second portion 1032, the first portion 1031 of the first signal line 103 is located in the first region 1021 of the peripheral area 102, and the first portion 1031 of the first signal line 103
  • the second part 1032 of the connection extends into the light emitting region 101, and the first part 1031 of the first signal line 103 can be designed to have a narrower width in the second direction D2, so as to facilitate the reduction of the first region 1021 along the second direction.
  • the width of D2 is beneficial to reduce the width of the left frame of the light-emitting substrate 100 .
  • the second part 1032 connected to the first part 1031 extends into the light emitting region 101, it is equivalent to "dividing" the width of the first signal line 103 along the second direction D2 into two parts, and a part of the width is located in the first region of the peripheral region 102 1021 (i.e. the width of the first portion 1031 of the first signal line 103), a part of the width is located in the light emitting region 101 (i.e.
  • the width of the second portion 1032 of the first signal line 103 the width of the second portion 1032 of the first signal line 103), so that even if the width of the first signal line 103 is reduced
  • the width of the first part 1031 due to the existence of the second part 1032, will not increase the resistance and voltage drop of the first signal line 103, thus will not affect the luminous efficiency of the light emitting substrate 100, and make the central area and the edge of the light emitting substrate 100
  • the area has a uniform luminous brightness.
  • there is no need to increase the thickness of the first signal line 103 so the production cost can be reduced and the production efficiency can be improved.
  • the peripheral region 102 further includes a second region 1022 located between the second side 002 of the light emitting substrate 100 opposite to the first side 001 and the light emitting region 101 .
  • the light-emitting substrate 100 may further include a second signal line 104, the first portion 1041 of the second signal line 104 extends along the first direction D1 in the second region 1022, and the second portion 1042 of the second signal line 104 extends to In the light emitting area 101 , and the first part 1041 of the second signal line 104 is connected to the second part 1042 .
  • the first part 1041 of the second signal line 104 is located between the second side 002 of the light-emitting substrate 100 and the light-emitting area 101, in other words, the first part 1041 of the second signal line 104 is located in the frame area of the light-emitting substrate 100, that is, FIG. 1 The right frame area of the light-emitting substrate 100 in .
  • the second signal line 104 can be various appropriate types of signal lines, such as a signal line for transmitting voltage, a signal line for transmitting driving data, a wiring for connecting two components or multiple components, etc. The embodiment of the present disclosure does not specifically limit the type of the second signal line 104 .
  • the second portion 1032 of the first signal line 103 includes at least one strip structure 1034 extending along the first direction D1, the first portion 1031 and the second portion 1032 of the first signal line 103 pass through the first signal line
  • the third part 1033 of 103 is connected.
  • the first portion 1031 , the second portion 1032 and the third portion 1033 of the first signal line 103 make the first signal line 103 present a “comb” shape.
  • the second portion 1042 of the second signal line 104 includes at least one strip structure 1044 extending along the first direction D1, the first portion 1041 and the second portion 1042 of the second signal line 104 pass through the second signal line
  • the third part 1043 of 104 is connected.
  • the first portion 1041 , the second portion 1042 and the third portion 1043 of the second signal line 104 make the second signal line 104 present a “comb” shape.
  • the shape of the first signal line 103 and the second signal line 104 is not limited to the "comb” shape, and may be any other appropriate shape.
  • the shape of the first signal line 103 is "U”.
  • the shape of the second signal line 104 is "U”.
  • the embodiments of the present disclosure do not specifically limit the shapes of the first signal line 103 and the second signal line 104 .
  • the first portion 1041 of the second signal line 104 can be designed to have a narrower width in the second direction D2, thereby facilitating reducing the width of the second region 1022 along the second direction D2, that is, facilitating reducing The width of the right border of the light-emitting substrate 100 is small.
  • the second portion 1042 connected to the first portion 1041 extends into the light emitting region 101, even if the width of the first portion 1041 of the second signal line 104 is reduced, the second portion 1042 does not increase the width of the second signal line.
  • the resistance and the voltage drop of 104 will not affect the luminous efficiency of the light-emitting substrate 100, and make the central area and the edge area of the light-emitting substrate 100 have uniform luminous brightness.
  • there is no need to increase the thickness of the second signal line 104 so the production cost can be reduced and the production efficiency can be improved.
  • the arrangement of the first signal line 103 and the second signal line 104 is beneficial to reduce the width of the first area 1021 and the second area 1022 , thereby facilitating the realization of a narrow left frame and a narrow right frame of the light-emitting substrate 100 .
  • the existing large-sized light-emitting substrates are usually spliced by several small-sized light-emitting substrates. If the light-emitting substrate has a wider frame, the optical effect will be poor due to the large seam when multiple light-emitting substrates are spliced together. It cannot be matched with various institutions.
  • the light-emitting substrate 100 of the present application has a narrower frame, so when splicing multiple light-emitting substrates 100 to form a larger-sized light-emitting substrate, the multiple light-emitting substrates 100 can be spliced perfectly without being stuck between each other. An excessively large seam is generated, so that the optical effect of the large-size light-emitting substrate and the matching of various mechanisms can be improved.
  • FIG. 2 shows a more detailed wiring scheme of the light emitting substrate 100 .
  • the light-emitting region 101 includes a plurality of sub-light-emitting regions 105 arranged in an array, and the plurality of sub-light-emitting regions 105 are arranged in M rows along the first direction D1 and arranged in N columns along the second direction D2 crossing the first direction D1.
  • M and N are both positive integers greater than or equal to 1.
  • the first direction D1 may be a column direction
  • the second direction D2 may be a row direction
  • the first direction D1 and the second direction D2 may be perpendicular to each other.
  • the first part 1031 of the first signal line 103 is arranged between the sub-light emitting area of the first row and the first side 001 of the light emitting substrate 100, that is to say, the first part 1031 of the first signal line 103 is located in the first area of the peripheral area 102 1021, and outside the sub-light-emitting area of the first column.
  • Each strip structure 1034 of the second portion 1032 of the first signal line 103 is arranged in a corresponding column of the first to X columns of sub-light emitting regions, where 1 ⁇ X ⁇ N.
  • X the strip structure 1034
  • the strip structure 1034 is arranged in the first row of sub-light emitting regions.
  • the second portion 1032 of the first signal line 103 includes X strip structures 1034
  • the X strip structures 1034 are respectively arranged in the first to X columns of sub-light emitting regions.
  • each strip structure 1034 is located at the far right in the sub-light emitting region of the corresponding column, for example, the strip structure 1034 in the sub-light emitting region of the first column is located at the far right in the sub-light emitting region of the first column.
  • Each strip structure 1044 of the second part 1042 of the second signal line 104 is arranged in a corresponding column in the sub-light emitting regions of the Y-N columns, and the first part 1041 of the second signal line 104 is arranged in the sub-light emitting regions of the Nth column and the light emitting region. Between the second side 002 of the substrate 100, that is to say, the first part 1041 of the second signal line 104 is located in the second region 1022 of the peripheral region 102 and outside the Nth column of sub-light emitting regions, where 1 ⁇ X ⁇ Y ⁇ N.
  • the second portion 1042 of the second signal line 104 includes a strip structure 1044
  • each strip structure 1044 is located at the leftmost in the sub-light emitting region of the corresponding column, for example, the strip structure 1044 in the Y-th column of the sub-light-emitting region is located at the leftmost in the Y-th column of the sub-light-emitting region. It should be noted that the difference between Y and X may be greater than or equal to 1.
  • the sub-light-emitting area of the Y-th column is immediately behind the sub-light-emitting area of the X-th column, that is, the sub-light-emitting area of the X-th column is adjacent to the sub-light-emitting area of the Y-th column.
  • Y-X>1 there is at least one sub-light emitting region between the X-row sub-light-emitting region and the Y-row sub-light-emitting region, that is, the X-row sub-light-emitting region and the Y-row sub-light-emitting region are not adjacent.
  • the light-emitting substrate 100 further includes a first conductive portion 108 located on the same layer as the first signal line 103 .
  • the term "A and B are located in the same layer” means that A and B are located on the surface of the same film layer and both are in direct contact with the surface.
  • a and B are formed from the same film layer by using the same process.
  • a and B are located on the surface of the same film layer and both are in direct contact with the surface, and A and B have substantially the same height or thickness.
  • the first conductive portion 108 includes N ⁇ 1 driving voltage signal lines VLEDL extending along the first direction D1, and each of the second to N columns of sub-light emitting regions includes a driving voltage signal line VLEDL.
  • Each sub-light-emitting area 105 includes at least one light-emitting unit 106, and in each column of the second to N columns of sub-light-emitting areas, each driving voltage signal line VLEDL is connected to the first end of each light-emitting unit 106 in the column of sub-light-emitting areas. , so as to provide the driving voltage for the light emitting unit 106 at a desired period.
  • the first portion 1031 of the first signal line 103 is connected to the first end of each light emitting unit 106 in the first row of sub light emitting regions.
  • the width of the first portion 1031 of the first signal line 103 along the second direction D2 is smaller than the width of each driving voltage signal line VLEDL along the second direction D2.
  • the first signal line 103 and multiple driving voltage signal lines VLEDL are simultaneously formed by patterning the conductive layer, and the first part 1031 of the first signal line 103 corresponds to the sub-light emission of the first column.
  • the driving voltage signal line VLEDL of the region is used to provide the driving voltage for the light emitting units 106 in the first column of the sub light emitting region at a desired time period.
  • the width of the first part 1031 of the first signal line 103 along the second direction D2 is smaller than the width of each driving voltage signal line VLEDL along the second direction D2, that is, it is located in the left frame area of the light-emitting substrate 100 (that is, the first area 1021 , which is the distance from the center of the light-emitting unit 106 in the sub-light-emitting region of the first column to the first side 001 of the light-emitting substrate 100) within the line width of the driving voltage signal line VLEDL (that is, the first part 1031 of the first signal line 103) It is smaller than the line width of the driving voltage signal line VLEDL located in the light-emitting region 101 , which is beneficial to reduce the width of the left frame of the light-emitting substrate 100 and facilitates the realization of a narrow frame.
  • the width of the driving voltage signal line VLEDL along the second direction D2 is generally 2-15 mm, for example, 4.0 mm in one example.
  • the width of the left frame area of the light-emitting substrate 100 along the second direction D2 is required to be within 3.8 mm. If the driving voltage signal line VLEDL with a line width of 4.0 mm is arranged in the left frame area, the narrow frame requirements of the product cannot be met. .
  • the width of the first portion 1031 of the first signal line 103 along the second direction D2 smaller than the width of the driving voltage signal line VLEDL along the second direction D2, for example, the first portion 1031 of the first signal line 103 along the second
  • the width of the direction D2 can be realized to be 0.05-0.5 mm, which can greatly reduce the width of the left frame area of the light-emitting substrate 100 and fully meet the narrow frame requirements of the product. If such light-emitting substrates 100 need to be spliced to form a large-sized light-emitting substrate, the light-emitting substrate 100 with an extremely narrow border can also fully meet the splicing requirements without affecting optical and mechanical matching.
  • the second portion 1032 of the first signal line 103 due to the existence of the second portion 1032 of the first signal line 103, it is equivalent to extending a part of the width of the first signal line 103 into the light-emitting area 101. Therefore, even if the line width of the first portion 1031 of the first signal line 103 is reduced To 0.05-0.5 mm, it can also meet the resistance and voltage drop requirements of the first signal line 103 , without affecting the luminous efficiency and luminous uniformity of the light-emitting substrate 100 .
  • the first conductive portion 108 may further include N ⁇ 1 common voltage signal lines GNDL extending along the first direction D1, and the first conductive portion 108 and the second signal line 104 are located on the same layer, that is, the first The first signal line 103 , the second signal line 104 and the first conductive portion 108 are located on the same layer.
  • Each of the 1st to N ⁇ 1 sub-light emitting regions includes a common voltage signal line GNDL, and each sub-light emitting region 105 further includes a driving circuit 107 connected to the second end of at least one light emitting unit 106 .
  • each common voltage signal line GNDL is connected to each driving circuit 107 in the sub-light emitting region of the column, so as to provide a common voltage (such as a ground voltage) during a required period.
  • the first portion 1041 of the second signal line 104 is connected to each driving circuit 107 in the Nth column of sub-light emitting regions.
  • the width of the first portion 1041 of the second signal line 104 along the second direction D2 is smaller than the width of each common voltage signal line GNDL along the second direction D2.
  • the first signal line 103, the second signal line 104, the driving voltage signal line VLEDL and the common voltage signal line GNDL are simultaneously formed by patterning the conductive layer, the second signal line 104
  • the first part 1041 is equivalent to the common voltage signal line GNDL corresponding to the Nth column of sub-light emitting regions, so as to provide a common voltage during a required period.
  • the width of the first portion 1041 of the second signal line 104 along the second direction D2 is smaller than the width of each common voltage signal line GNDL along the second direction D2, that is, it is located in the right frame area of the light emitting substrate 100 (ie, the second area 1022 , which is the distance from the center of the light-emitting unit 106 in the Nth column of sub-light-emitting regions to the second side 002 of the light-emitting substrate 100) within the common voltage signal line GNDL (that is, the first part 1041 of the second signal line 104) line width It is smaller than the line width of the common voltage signal line GNDL located in the light-emitting region 101, which is beneficial to reduce the width of the right frame of the light-emitting substrate 100, and is beneficial to realize a narrow frame.
  • the width of the common voltage signal line GNDL along the second direction D2 is generally 2-15 mm, for example, 4.0 mm in one example.
  • the width of the right frame area of the light-emitting substrate 100 along the second direction D2 is required to be within 3.8 mm. If the common voltage signal line GNDL with a line width of 4.0 mm and other necessary signal traces are arranged in the right frame area, It cannot meet the narrow frame requirements of the product.
  • the width of the first portion 1041 of the second signal line 104 along the second direction D2 smaller than the width of the common voltage signal line GNDL along the second direction D2, for example, the first portion 1041 of the second signal line 104 along the second
  • the width of the direction D2 can be realized to be 0.05-0.5 mm, which can greatly reduce the width of the right frame area of the light-emitting substrate 100 and fully meet the narrow frame requirements of the product. If such light-emitting substrates 100 need to be spliced to form a large-sized light-emitting substrate, the light-emitting substrate 100 with an extremely narrow border can also fully meet the splicing requirements without affecting optical and mechanical matching.
  • the second portion 1042 of the second signal line 104 due to the existence of the second portion 1042 of the second signal line 104, it is equivalent to extending a part of the width of the second signal line 104 into the light-emitting region 101, therefore, even if the line width of the first portion 1041 of the second signal line 104 is reduced To 0.05-0.5 mm, it can also meet the resistance and voltage drop requirements of the second signal line 104 , without affecting the luminous efficiency and luminous uniformity of the light-emitting substrate 100 .
  • the light-emitting substrate 100 can have a very narrow left frame and a right frame.
  • the left and right bezels can even be omitted so that the light emitting substrate 100 can be realized as a bezel-less product.
  • the driving voltage signal line VLEDL, the light-emitting unit 106, the driving circuit 107, and the common voltage signal line GNDL are sequentially arranged along the second direction D2 , and their orthographic projections on the light-emitting substrate 100 do not overlap each other.
  • the first conductive portion 108 may further include N feedback signal lines FBL extending along the first direction D1, and each row of sub-light emitting regions includes a feedback signal line FBL.
  • each driving circuit 107 is cascaded in sequence, and each feedback signal line FBL is connected to the last-stage driving circuit 107 .
  • each feedback signal line FBL is located on a side away from the driving circuit 107 from the common voltage signal line GNDL in the same column of sub-light emitting regions as the feedback signal line FBL.
  • each feedback signal line FBL bypasses the common voltage signal line GNDL and is located on the side of the common voltage signal line GNDL away from the driving circuit 107 in each column of the 1st to N-1 sub-light emitting regions;
  • the feedback signal line FBL bypasses the signal line adjacent to it and on the right side thereof (such as the power signal line PwL) and is located on a side of the signal line away from the driving circuit 107 .
  • each feedback signal line FBL bypasses the common voltage signal line GNDL and is located on the side of the common voltage signal line GNDL away from the driving circuit 107; in each column of the sub-light-emitting regions of the Y-Nth columns, that is, when the second In each column of the strip structure 1044 of the second portion 1042 of the signal line 104 , the feedback signal line FBL bypasses the driving voltage signal line VLEDL and is located on a side of the driving voltage signal line VLEDL away from the driving circuit 107 .
  • FIG. 3 shows the layout of the light emitting substrate 200
  • FIG. 4 shows the layout of each terminal of the driving circuit 107 of the light emitting substrate 200 .
  • FIG. 3 only shows four columns of sub-light emitting regions, that is, the first column of sub-light emitting regions, the second column of sub-light emitting regions, the N ⁇ 1th column of sub-light emitting regions, and the Nth column of sub-light emitting regions.
  • the light emitting substrate 200 shown in FIG. 3 has substantially the same configuration as the light emitting substrate 100 shown in FIG. 2 , and thus the same reference numerals are used to designate the same components. Therefore, the detailed actions and functions of the components in FIG. 3 with the same reference numerals as those in FIG. 2 can refer to the description of FIG. 2 , and will not be repeated here.
  • the dotted line box on the left side of FIG. 3 shows an enlarged view of a sub-light-emitting region 105.
  • the light-emitting substrate 200 also includes a second conductive portion 109, and the second conductive portion 109 includes a plurality of first pads 1091. and a plurality of second pads 1092 , the light emitting unit 106 is mounted on the first pad 1091 , and the driving circuit 107 is mounted on the second pad 1092 .
  • the first conductive portion 108 and the second conductive portion 109 are located on the same layer, and the same conductive layer can be patterned to simultaneously form the first conductive portion 108 and the second conductive portion 109 during the manufacturing process.
  • each driving circuit 107 includes four terminals, namely an address terminal Di, a power supply terminal Pwr, a common voltage terminal GND, and an output terminal Out.
  • the output terminal Out and the address terminal Di are the first column terminals of the drive circuit 107, which are located on the side of the drive circuit 107 adjacent to the drive voltage signal line VLEDL (the first column terminal of the drive circuit 107 in the first column sub-light-emitting area is located in the drive circuit 107).
  • the side of the first part 1031 of the circuit 107 adjacent to the first signal line 103); the common voltage terminal GND and the power supply terminal Pwr are the second column terminals of the driving circuit 107, which are located on one side of the driving circuit 107 adjacent to the common voltage signal line GNDL side (the second column terminal of the driving circuit 107 in the Nth column of sub-light emitting regions is located on the side of the driving circuit 107 adjacent to the first portion 1041 of the second signal line 104 ).
  • the common voltage terminal GND and the output terminal Out are located in the first row among the terminals, and the address terminal Di and the power terminal Pwr are located in the second row among the terminals.
  • the first conductive portion 108 further includes N address signal lines ADDRL extending along the first direction D1, so that each column of sub-light emitting regions includes one address signal line ADDRL.
  • the address selection signal line ADDRL is connected to the address terminal Di of the first-level driving circuit 107 .
  • the output terminal Out can be multiplexed as a relay terminal of the driving circuit 107 .
  • the address selection signal line ADDRL is configured to transmit an address signal to the address terminal Di of the first-level driving circuit 107 in each sub-light-emitting area. After receiving the address signal, the first-level driving circuit 107 can analyze, obtain, and store the address signal.
  • the address information of the first-level driving circuit 107 is used as the address information of the first-level driving circuit 107, and the address information can be incremented by 1 or another fixed amount and the incremented address information (new address information) can be modulated into a relay signal,
  • the relay terminal Out of the first-level driving circuit 107 transmits the relay signal to the address terminal Di of the second-level driving circuit 107 via the cascaded wiring, as address information of the second-level driving circuit 107 .
  • corresponding address information can be configured for each driving circuit 107 in each sub-light emitting area.
  • the output terminal Out of the last-stage drive circuit 107 is connected to the feedback signal line FBL.
  • the output terminal Out can output different signals in different periods, for example, the output terminal Out of the drive circuit 107 outputs a relay signal within a period as an address signal of the next-stage drive circuit 107 cascaded with the drive circuit 107 , to provide a driving signal to the light emitting unit 106 connected to the driving circuit 107 in another period of time to make the light emitting unit 106 emit light.
  • the first conductive portion 108 further includes N power signal lines PwrL extending along the first direction D1, and each row of sub-light emitting regions includes a power signal line PwrL.
  • a power signal line PwrL is connected to the power terminals Pwr of all driving circuits 107 in the column of sub-light-emitting areas, and the orthographic projection of the first column terminals of each driving circuit 107 on the light-emitting substrate 200 is consistent with the second
  • the orthographic projections of the column terminals on the light-emitting substrate 200 are respectively located on both sides of the orthographic projection of the power signal line PwrL on the light-emitting substrate 200, that is, the power signal line PwrL is arranged in the area occupied by each driving circuit 107 , and does not overlap with the first column terminal and the second column terminal of each driving circuit 107 .
  • the lines are located on the same layer, and their orthographic projections on the light-emitting substrate 200 do not overlap with each other. In an example, the distance between any two adjacent signal lines among these signal lines is greater than or equal to 200um, so that signal interference between signal lines can be avoided.
  • FIG. 5 shows the layout of the light emitting substrate 300
  • FIG. 6 shows the layout of each terminal of the driving circuit 107 of the light emitting substrate 300 .
  • FIG. 5 only shows four columns of sub-light emitting regions, that is, the first column of sub-light emitting regions, the second column of sub-light emitting regions, the N ⁇ 1th column of sub-light emitting regions, and the Nth column of sub-light emitting regions.
  • the light emitting substrate 300 shown in FIG. 5 has substantially the same configuration as the light emitting substrate 200 shown in FIG. 3 , and thus the same reference numerals are used to designate the same components. Therefore, for the detailed functions and functions of the components with the same reference numerals in FIG. 5 as in FIG. 3 , reference may be made to the description of FIG. 3 , which will not be repeated here.
  • FIG. 3 Only the differences between the light emitting substrate 300 in FIG. 5 and the light emitting substrate 200 in FIG. 3 will be introduced below.
  • the number of terminals of the drive circuit 107 of the light-emitting substrate 300 in FIG. is at least one.
  • FIG. 6 shows that the number of output terminals Out is four and the number of common voltage terminals GND is two, but this is only an example.
  • the number of output terminals Out may be more than four or less than four, and the number of common voltage terminals GND may be more than two or less than two.
  • the driving circuit 107 also includes a data terminal Data. As shown in Fig. 5 and Fig.
  • the drive circuit 107 includes two columns of terminals, the first column terminal includes a power supply terminal Vcc and four output terminals Out1, Out2, Out3, Out4, and the first column terminal is located at the adjacent drive voltage of the drive circuit 107.
  • One side of the signal line VLEDL (the first column terminal of the driver circuit 107 in the first column sub-light-emitting area is located on the side of the first part 1031 of the driver circuit 107 adjacent to the first signal line 103);
  • the second column terminal includes the address terminal Di_in , a relay terminal Di_out, a data terminal Data, and two common voltage terminals GND, the second column terminal is located on one side of the drive circuit 107 adjacent to the common voltage signal line GNDL (the second column of the drive circuit 107 in the Nth column sub-light emitting area The terminal is located on a side of the driving circuit 107 adjacent to the first portion 1041 of the second signal line 104 ).
  • the terminals of the drive circuit 107 are arranged in five rows, the address terminal Di_in is located in the fifth row among the terminals, and the relay terminal Di_out is located in the first row among the terminals.
  • the power supply terminal Vcc is located in the third row of the first column of terminals, and the data terminal Data is located in the second row of the second column of terminals, this is only an example, and embodiments of the present disclosure do not limit the power supply terminals.
  • the power supply terminal Vcc may be located in any one of the first row to the fifth row
  • the data terminal Data may be located in any one of the second row to the fourth row.
  • the four output terminals Out1 , Out2 , Out3 , Out4 of the driving circuit 107 are connected to the second ends of the four light emitting units 106 in one-to-one correspondence to provide driving signals for the light emitting units 106 .
  • the output terminal and the relay terminal of the drive circuit 107 are different terminals.
  • the drive circuit 107 is configured to output a relay signal through the relay terminal Di_out in one period as an address signal of the next-stage drive circuit 107 cascaded with the drive circuit 107, and to output a relay signal through four output terminals in another period.
  • Out1 , Out2 , Out3 , and Out4 respectively provide driving signals to the four light emitting units 106 .
  • the first conductive line of the light emitting substrate 300 Section 108 also includes N power signal lines VccL and N data drive signal lines DataL extending along the first direction D1, so that each column of sub-light emitting regions includes one power signal line VccL and one data drive signal line DataL.
  • a power signal line VccL is connected to the power supply terminals Vcc of all driving circuits 107 in the column sub-light emitting area, and a data driving signal line DataL is connected to the data terminals Data of all driving circuits 107 in the column sub-light emitting area. connect.
  • the orthographic projections of the terminals in the first column and the orthographic projections of the terminals in the second column on the luminescent substrate 300 of each driving circuit 107 are located on the power signal line VccL and the data driving signal line DataL respectively.
  • the two sides of the orthographic projection on the light-emitting substrate 300 that is, the power signal line VccL and the data driving signal line DataL are arranged in the area occupied by each driving circuit 107, and are not connected to the first column terminal and the second column terminal of each driving circuit 107. Two rows of terminals overlap. Moreover, in each sub-light-emitting area, the orthographic projection of the data driving signal line DataL on the light-emitting substrate 300 and the orthographic projection of the power signal line VccL on the light-emitting substrate 300 do not overlap.
  • the wiring space can be saved, and the data driving signal line DataL and the power signal line VccL can be avoided from interfering with other signals. overlap between lines.
  • the first conductive part 108 and the second conductive part 109 of the light emitting substrate 300 are located on the same layer. That is, the first signal line 103, the driving voltage signal line VLEDL, the address selection signal line ADDRL, the power signal line VccL, the data driving signal line DataL, the common voltage signal line GNDL, the feedback signal line FBL, and the second signal line 104, These signal lines are located on the same layer, and their orthographic projections projected on the light-emitting substrate 300 do not overlap with each other.
  • the light emitting substrate includes a binding electrode 110'.
  • Figure 7A shows four columns of sub-light emitting regions, namely the i-th column of sub-light-emitting regions, the i+1-th column of sub-light-emitting regions, the i+2-th column of sub-light-emitting regions, and the i+3-th column of light-emitting regions, and they are shown in dotted line boxes respectively. The area occupied by each sub-luminous area.
  • Each row of sub-light emitting regions includes a light emitting unit 106', a common voltage signal line GNDL' and a driving voltage signal line VLEDL', and both the common voltage signal line GNDL' and the driving voltage signal line VLEDL' are electrically connected to the binding electrode 106'.
  • a part of the common voltage signal line GNDL' of the i-th column of sub-light emitting regions extends to the adjacent (i+1)th column of sub-light-emitting regions and is electrically connected to the binding electrode 106' in the (i+1)th column of sub-light-emitting regions.
  • a part of the driving voltage signal line VLEDL' of the (i+3)th sub-light emitting region extends to the adjacent (i+2)th column of sub-light emitting region and is electrically connected to the binding electrode 106' in the (i+2)th column of sub-light emitting region.
  • the common voltage signal line GNDL' of the ith column of sub-light emitting regions and the driving voltage signal line VLEDL' of the i+3th column of sub-light emitting regions respectively occupy the part of the binding electrode 106' located in the i+1th column of sub-light emitting regions and the The part in the sub-light-emitting area of the i+2 column, therefore, the common voltage signal line GNDL' and the driving voltage signal line VLEDL' in the i+1-th column of the sub-light-emitting area, and the common voltage signal line GNDL' in the i+2-th column of the sub-light-emitting area
  • these signal lines need to be further toward the binding electrode 106 than the signal lines in the i-th column of sub-light emitting regions and the i+3th column of sub-light-emitting regions.
  • the width T' of the lower frame of the light-emitting substrate (that is, the area from the center of the light-emitting unit 106' in the sub-light-emitting region of the last row (row M) to the binding electrode 110') is significantly increased, so that the light-emitting substrate has a very
  • the wide bottom frame cannot meet the design requirements of a narrow frame.
  • the embodiments of the present disclosure provide a solution to reduce the width of the lower frame of the light-emitting substrate, and this solution can be applied to the light-emitting substrates described in any of the previous embodiments, such as the light-emitting substrates 100, 200 , 300.
  • the light-emitting substrate may further include a binding electrode 110 located in the peripheral region 102, the binding electrode 110 includes an effective terminal 1101 and a vacant terminal 1102, the first part 1031 and the second part 1032 of the first signal line 103, The first part 1041 and the second part 1042 of the second signal line 104 and all the signal lines of the first conductive part 108 are only electrically connected to the effective terminal 1101 of the binding electrode 110 .
  • the plurality of strip structures 1034 of the first part 1031 and the second part 1032 of the first signal line 103 are all connected to the effective terminal 1101 of the binding electrode 110, and the effective terminal 1101 of the binding electrode 110 is the first part of the first signal line 103 1031 and the plurality of strip structures 1034 of the second portion 1032 provide the same signal.
  • the plurality of strip structures 1044 of the first part 1041 and the second part 1042 of the second signal line 104 are all connected to the effective terminal 1101 of the binding electrode 110, and the effective terminal 1101 of the binding electrode 110 is the first part of the second signal line 104 1041 and the plurality of strip structures 1044 of the second portion 1042 provide the same signal.
  • the signal received by the first signal line 103 is different from the signal received by the second signal line 104 .
  • the driving voltage signal line VLEDL, the address selection signal line ADDRL, the power signal line VccL, the common voltage signal line GNDL, the feedback signal line FBL and optionally the data driving signal line DataL of the first conductive part 108 are all connected to the bonding electrode 110. Effective terminal 1101.
  • FIG. 7B only shows the last row of sub-light-emitting regions, that is, the M-th row of sub-light-emitting regions, which shows four columns of sub-light-emitting regions, the i-th column of sub-light-emitting regions, the i+1-th column of sub-light-emitting regions, the i+th row of sub-light-emitting regions, the i+th row of sub-light-emitting regions, 2 columns of sub-light-emitting regions, the i+3th column of sub-light-emitting regions, and the area occupied by each column of sub-light-emitting regions are shown by dotted line boxes.
  • the four columns of sub-light emitting regions may be any adjacent four columns of sub-light emitting regions in the N columns of sub-light emitting regions. It should be noted that although it is shown in FIG. 7B that the binding electrodes 110 are connected to the signal lines in the adjacent four columns of sub-light emitting regions, this is only an example. In an alternative example, the binding electrode 110 can be connected to the signal lines in more than four columns of sub-light emitting regions or the signal lines in less than four columns of sub-light emitting regions. The number of columns in the region is not specifically limited. For clarity, each column of sub-light emitting regions only shows the light emitting unit 106 , the common voltage signal line GNDL and the driving voltage signal line VLEDL, and other signal lines are omitted.
  • the common voltage signal line GNDL includes a first connection portion 115
  • the driving voltage signal line VLEDL includes a second connection portion 116
  • each common voltage signal line GNDL is electrically connected to the effective terminal 1101 of the binding electrode 110 through its first connection portion 115
  • Each driving voltage signal line VLEDL is electrically connected to the active terminal 1101 of the binding electrode 110 through its second connection portion 116 .
  • the first connection portion 115 of the common voltage signal line GNDL is only located in the sub-light-emitting region of the column and does not extend to the sub-light-emitting regions of the adjacent column;
  • the second connection portion 116 of the driving voltage signal line VLEDL is only located in the sub-light emitting regions of the column and does not extend to the sub-light emitting regions of adjacent columns. As shown in FIG.
  • the first connecting portion 115 of the common voltage signal line GNDL and the second connecting portion 116 of the driving voltage signal line VLEDL in the i-th column of sub-light emitting regions are completely located in the i-th column of sub-light-emitting regions without extending to the corresponding In the adjacent i+1th column light-emitting area, and in the i-th column sub-light-emitting area, it is electrically connected to the effective terminal 1101 of the binding electrode 110;
  • the first connection part of the common voltage signal line GNDL in the i+1-th column sub-light-emitting area 115 and the second connecting portion 116 of the driving voltage signal line VLEDL are completely located in the i+1th column light-emitting area and will not extend to the adjacent i-th column light-emitting area and i+2-th column light-emitting area, and the i-th column
  • the effective terminal 1101 of the binding electrode 110 in the sub-light-emitting area of the +1 column is electrically
  • the common voltage signal line GNDL in the i-th column of the sub-light-emitting area and the driving voltage signal line VLEDL in the i+3-th column of the sub-light-emitting area are respectively electrically connected to the effective terminal 1101 of the binding electrode 110 in the column area where they are located, there is no need
  • the common voltage signal line GNDL and the driving voltage signal line VLEDL in the (i+1) sub-light-emitting region and the common voltage signal line GNDL and the driving voltage signal line VLEDL in the (i+2)-th sub-light-emitting region further extend toward the binding electrode 106 .
  • the width T of the lower frame of the light-emitting substrate (that is, the area from the center of the light-emitting unit 106 to the binding electrode 110 in the M-th row of sub-light-emitting regions) is greatly reduced, so that the light-emitting substrate has a very narrow lower frame, so that it can Meet the design requirements of narrow bezels.
  • the width T of the lower frame of the light-emitting substrate is 4.15 mm, which is 3.35 mm smaller than the width T′ of the lower frame in the related art which is 7.5 mm.
  • FIG. 7B can be combined with the design of the first signal line 103 and/or the second signal line 104 described in any of the previous embodiments, so as to realize the narrow border on the left side of the light-emitting substrate and / or the narrow frame on the right side and the narrow frame below; it may not be combined with the design of the first signal line 103 and the second signal line 104 described in any of the previous embodiments, that is, only the driving electrodes 110 of the light-emitting substrate may be used.
  • a design as shown in FIG. 7B is designed to separately realize the lower narrow frame of the light-emitting substrate.
  • the light-emitting substrate provided in the above embodiments may further include a substrate 111 , a buffer layer 112 and a first insulating layer 113 .
  • the buffer layer 112 is located between the layer where the first conductive portion 108 and the second conductive portion 109 are located and the substrate 111
  • the first insulating layer 113 is located at a layer where the first conductive portion 108 and the second conductive portion 109 are located away from the substrate 111. side.
  • the substrate 111 may be any suitable substrate such as a plastic substrate, a silicon substrate, a ceramic substrate, a glass substrate, a quartz substrate, and the embodiment of the present disclosure does not limit the material of the substrate 111 .
  • the buffer layer 112 can be used to reduce the stress on the substrate 111 during the preparation of the first conductive portion 108 and the second conductive portion 109, so that the substrate 111 can be prevented from being bent and deformed; the buffer layer 112 can also prevent the substrate 111 from The impurity has adverse effects on the conductivity of the first conductive portion 108 and the second conductive portion 109 .
  • the buffer layer 112 can be any suitable material, for example, it can be SiN.
  • the first insulating layer 113 can be used to protect the first conductive portion 108 and the second conductive portion 109 from being oxidized and corroded by water, oxygen, etc. in the environment.
  • the material of the first insulating layer 113 may be organic material, inorganic material or a combination of organic material and inorganic material.
  • the first insulating layer 113 may be a single film layer, or may include multiple film layers.
  • the light-emitting substrate may further include a second insulating layer 114 located on a side of the first insulating layer 113 away from the substrate 111 .
  • the material of the second insulating layer 114 may be organic material, inorganic material or a combination of organic material and inorganic material.
  • the second insulating layer 114 may be a single film layer, or may include multiple film layers.
  • first conductive portion 108 and the second conductive portion 109 located on the same layer may be any suitable conductive material, which is not specifically limited in this embodiment of the present disclosure.
  • the material of the first conductive part 108 and the second conductive part 109 includes copper.
  • the first conductive portion 108 and the second conductive portion 109 may be a stack of Cu and CuNi. The side of the stack close to the substrate 111 is a Cu layer, the thickness of which may be 2um, for example, and Cu is a preferred material for electrical signal transmission channels.
  • the side of the stack away from the substrate 111 is a CuNi layer, the thickness of which may be 0.6 um, for example, and the CuNi layer may be used to protect the Cu layer and prevent the surface of the Cu layer with low resistivity from being exposed and oxidized.
  • the first conductive part 108 and the second conductive part 109 are, for example, a stack of MoNb/Cu/MoNb, and the side of the stack close to the substrate 111 is a MoNb layer with a thickness of about Left and right, mainly used to improve the adhesion between the stack and the substrate 111; the middle layer of the stack is a Cu layer, and Cu is the preferred material for the electrical signal transmission channel; the side of the stack far away from the substrate 111 is a MoNb layer, The thickness is about On the left and right, the MoNb layer can be used to protect the middle Cu layer and prevent the surface of the middle Cu layer with low resistivity from being exposed and oxidized.
  • FIG. 9 shows several optional arrangements of each light emitting unit 106 as an example.
  • Each light-emitting unit 106 includes a plurality of light-emitting elements connected to each other, and the first ends of the plurality of light-emitting elements are electrically connected to the driving voltage signal line VLEDL (the first end of the plurality of light-emitting elements in the light-emitting unit 106 in the first row of sub-light-emitting regions terminals are electrically connected to the first part 1031 of the first signal line 103 ), and the second terminals of the plurality of light emitting elements are electrically connected to the output terminal Out of the driving circuit 107 .
  • VLEDL the driving voltage signal line
  • each light-emitting unit 106 includes four light-emitting elements connected in series with each other, and the four light-emitting elements are arranged in 1 column * 4 rows;
  • Fig. 9 (b) shows that each light-emitting unit 106 includes each other Four light-emitting elements connected in series, the four light-emitting elements are arranged in 2 columns*2 rows; FIG. Column * 3 rows.
  • the multiple light emitting elements in each light emitting unit 106 are not limited to the above arrangement, and they can be arranged in any suitable manner. In one example, multiple light emitting elements in each light emitting unit 106 can be connected in parallel with each other.
  • each light emitting element in each light emitting unit 106 may be combined in series and in parallel.
  • the number of light emitting elements included in each light emitting unit 106 may be determined according to actual requirements, for example, according to the size of the light emitting substrate and the required brightness.
  • Each light emitting element can be an organic light emitting diode or an inorganic light emitting diode.
  • each light emitting element may be a submillimeter light emitting diode (Mini LED) or a micro light emitting diode (Mirco LED).
  • the size of sub-millimeter LEDs is, for example, in the range of 100 microns to 500 microns; the size of micro LEDs is, for example, smaller than 100 microns.
  • Embodiments of the present disclosure do not limit the type and size of the light emitting elements of the light emitting unit 106 .
  • Using submillimeter light emitting diodes or micro light emitting diodes as the light emitting elements of the light emitting unit 106 can realize high dynamic range (High-Dynamic Range, HDR) display.
  • HDR High-Dynamic Range
  • the contrast ratio of the display device can be significantly improved.
  • the above describes how the light-emitting substrate 100, the light-emitting substrate 200, and the light-emitting substrate 300 realize the left narrow frame, the right narrow frame, and the lower narrow frame.
  • the first conductive part 108 and the second conductive part Section 109 is located on the same floor.
  • the first conductive part 108 and the second conductive part 109 are located in different layers, how the light-emitting substrate realizes a narrow frame will be described.
  • FIG. 10 shows a light-emitting substrate 400 .
  • the detailed actions and functions of components having the same reference numerals as in FIG. 3 in FIG. 10 can refer to the description of FIG. 3 , which will not be repeated here.
  • FIG. 3 shows a light-emitting substrate 400 .
  • FIG. 10 shows N columns of sub-light emitting regions, and the first conductive portion 108 and the second conductive portion 109 are located in different layers.
  • the first conductive part 108 includes a driving voltage signal line VLEDL, an address selection signal line ADDRL, a power signal line PwrL, a common voltage signal line GNDL, and a feedback signal line FBL, and the light emitting unit 106 and the driving circuit 107 are connected to the binding through these signal lines.
  • the bound electrodes of the region receive corresponding electrical signals.
  • the second conductive portion 109 includes a first pad 1091 and a second pad 1092 , the first pad 1091 is used for mounting the light emitting unit 106 , and the second pad 1092 is used for mounting the driving circuit 107 .
  • the first conductive part 108 is located between the substrate of the light-emitting substrate 400 and the second conductive part 109 , and the second conductive part 109 is located on a side of the first conductive part 108 away from the substrate.
  • a buffer layer is usually provided between the substrate and the first conductive portion 108 , which can be used to reduce the stress on the substrate during the preparation of the first conductive portion 108 , so as to avoid bending deformation of the substrate.
  • a first insulating layer is generally disposed between the first conductive portion 108 and the second conductive portion 109 , and the first conductive portion 108 is electrically connected to the second conductive portion 109 through a via hole in the first insulating layer.
  • the first insulating layer may be an inorganic layer or an organic layer or a laminate of an inorganic layer and an organic layer.
  • a second insulating layer is generally disposed on the side of the second conductive portion 109 away from the first conductive portion 108 to protect the first conductive portion 108 and the second conductive portion 109 from being oxidized and corroded.
  • the second insulating layer may be an inorganic layer or an organic layer or a laminate of an inorganic layer and an organic layer.
  • each column of sub-light-emitting regions includes a driving voltage signal line VLEDL, a common voltage signal line GNDL, a power signal line PwrL, And the address signal line ADDRL, and along the second direction D2 from left to right, in order of the driving voltage signal line VLEDL, the common voltage signal line GNDL, the power signal line PwrL, and the address signal line ADDRL.
  • each column of sub-light-emitting regions includes a driving voltage signal line VLEDL, a common voltage signal line GNDL, a power signal line PwrL, and a feedback signal line FBL, and along the second direction D2 from the left To the right, the driving voltage signal line VLEDL, the common voltage signal line GNDL, the power signal line PwrL, and the feedback signal line FBL are arranged in sequence.
  • the common voltage signal line GNDL is arranged in the central region of each column of sub-light emitting regions instead of the edge region, which can make the common voltage signal line GNDL have a larger width along the second direction D2, Therefore, the voltage drop on the common voltage signal line GNDL can be reduced (for example, reduced to less than 0.5V) without increasing the thickness of the common voltage signal line GNDL.
  • the driving circuits 107 of two adjacent columns of sub-light emitting regions are connected in series, so two adjacent columns of sub-light emitting regions can share one address selection signal line ADDRL and one feedback signal line FBL.
  • the address selection signal line ADDRL is connected to the first-stage driving circuit 107 in the sub-light emitting regions of the first column.
  • Each drive circuit 107 in the sub-light-emitting area of the first column is cascaded in sequence, and the last-level drive circuit 107 in the sub-light-emitting area of the first column is connected with the first-level drive circuit 107 in the sub-light-emitting area of the second column, and the sub-light-emitting area of the second column
  • Each drive circuit 107 in the circuit is also cascaded in sequence. Therefore, one address selection signal line ADDRL can provide address information for each driving circuit 107 in the sub-light emitting region of the first column and the sub-light emitting region of the second column.
  • a feedback signal line FBL is connected to the last-level drive circuit 107 in the second row of sub-light emitting regions, so as to feed back the information of each driver circuit 107 in the first row of sub-light emitting regions and the second row of sub-light emitting regions to an external circuit (such as a flexible circuit board).
  • the light emitting substrate 400 also includes a first signal line 103 .
  • the first part 1031 of the first signal line 103 is located in the first area 1021 of the peripheral area 102 of the light emitting substrate 400 , further, the first part 1031 of the first signal line 103 is arranged in the first column of the sub light emitting area and the first part of the light emitting substrate 400 . Between side 001.
  • Each strip structure 1034 of the second portion 1032 of the first signal line 103 may be respectively arranged in a corresponding column of the first to X columns of sub-light emitting regions, where 1 ⁇ X ⁇ N.
  • the second portion 1032 of the first signal line 103 includes a strip structure 1034
  • the second portion 1032 of the first signal line 103 includes N strip structures 1034
  • the N strip structures 1034 are respectively arranged in the first to N sub-light emitting regions.
  • each strip structure 1034 is located at the far right in the sub-light emitting area of the corresponding column, for example, the strip structure 1034 in the sub-light emitting area of the first column is located at the far right in the sub-light emitting area of the first column.
  • the first portion 1031 of the first signal line 103 is designed to have a narrower width in the second direction D2, for example, the width is 0.05-0.5 mm, so as to facilitate reducing the width of the first region 1021 along the second direction D2, that is, to facilitate narrowing The width of the left frame of the light emitting substrate 400 .
  • the second portion 1032 connected to the first portion 1031 extends into the light-emitting area 101, even if the width of the first portion 1031 of the first signal line 103 is reduced, the presence of the second portion 1032 will not increase the width of the first signal line.
  • the resistance and voltage drop of 103 will not affect the luminous efficiency of the light-emitting substrate 400, and make the central area and edge area of the light-emitting substrate 400 have uniform luminous brightness.
  • there is no need to increase the thickness of the first signal line 103 so the production cost can be reduced and the production efficiency can be improved.
  • the light-emitting substrate 500 has basically the same structure as the light-emitting substrate 400 , that is, the first conductive part 108 and the second conductive part 109 are also located in different layers.
  • the first signal line 103 only includes the second portion 1032 and does not include the first portion 1031 .
  • the second portion 1032 is located in the light emitting area 101 .
  • the second portion 1032 of the first signal line 103 includes N sub-signal lines extending along the first direction D1, and each column of sub-light emitting regions includes a sub-signal line. It should be noted that the function of the second portion 1032 of the first signal line 103 here is different from that of the second portion 1032 of the first signal line 103 described in the previous embodiments.
  • the second part 1032 is a tooth-shaped structure, together with the first part 1031 and the third part 1033 constitute a "comb" structure, and the second part 1032 is used to widen the width of the first part 1031 .
  • the first signal line 103 only includes the second part 1032 and does not include the first part 1031 and the third part 1033
  • the second part 1032 located in the light emitting area 101 includes N sub-signal lines , each column of sub-light-emitting areas includes a sub-signal line.
  • the N sub-signal lines are independent and insulated signal lines for transmitting corresponding electrical signals.
  • the sub-signal line may be a driving voltage signal line VLEDL, a power signal line PwrL, and a feedback signal line FBL. The specific types of sub-signal lines will be described in more detail below.
  • two adjacent columns of sub-light-emitting areas follow the driving voltage signal line VLEDL, the common voltage signal line GNDL, the power signal line PwrL, the address selection signal line ADDRL, the driving voltage signal line VLEDL, the common voltage signal line GNDL,
  • the order of the power signal line PwrL and the feedback signal line FBL is arranged from left to right.
  • the driving voltage signal line VLEDL is located on the left side of the light emitting unit 106 .
  • the power signal line PwrL and the address selection signal line ADDRL are located on the right side of the light-emitting unit 106; If the N columns of sub-light-emitting areas are all wired in the above-mentioned manner, then between the center of the light-emitting unit 106 in the first column of sub-light-emitting areas and the first side 001 of the light-emitting substrate 500 (that is, the left frame area of the light-emitting substrate 500) is provided with A wider drive voltage signal line VLEDL, a power signal line PwrL is provided between the center of the light-emitting unit 106 in the Nth column of sub-light-emitting regions and the second side 002 of the light-emitting substrate 500 (that is, the right frame area of the light-emitting substrate 500). and the feedback signal line FBL, which is not conducive to realizing a narrow frame of the light-emitting substrate 500, and cannot meet the specification
  • the central area of the light-emitting substrate 500 maintains the above-mentioned wiring scheme, that is, two adjacent columns of sub-light-emitting areas follow the driving voltage signal line VLEDL, the common voltage signal line GNDL, and the power signal line PwrL. , address selection signal line ADDRL, driving voltage signal line VLEDL, common voltage signal line GNDL, power signal line PwrL, and feedback signal line FBL are arranged in order from left to right.
  • the central area of the light-emitting substrate 500 may refer to the area occupied by the j-k sub-light-emitting regions of the light-emitting substrate 500 , for example, 3 ⁇ j ⁇ k ⁇ N ⁇ 2.
  • the sub signal line may refer to a driving voltage signal line VLEDL.
  • the driving voltage signal line VLEDL is located on a side of the light emitting unit 106 in each column of sub light emitting regions that is close to the first side 001 of the light emitting substrate 500 .
  • the driving voltage signal line VLEDL is located on the side of the light emitting elements E1 and E2 of the light emitting unit 106 in the column of sub light emitting regions away from the first side 001 of the light emitting substrate 500 . As shown in FIG.
  • the driving voltage signal line VLEDL in the sub-light-emitting region of the first column is arranged between the light-emitting element E1 and the light-emitting element E1 closest to the first side 001 of the light-emitting substrate 500 of the light-emitting unit 106
  • the right side of E2 that is, the driving voltage signal line VLEDL in the sub-light-emitting area of the first column is located on the side away from the peripheral area of the light-emitting elements E1 and E2 in the sub-light-emitting area of this column, and the position of the power signal line PwrL is adjusted so that it is in the drive Between the voltage signal line VLEDL and the common voltage signal line GNDL.
  • the driving voltage in the first column of sub-light-emitting regions in the embodiments of the present disclosure is adjusted from the peripheral area to the light-emitting area, so that the light-emitting units 106 in the sub-light-emitting areas of the first column move toward the first side 001 of the light-emitting substrate 500, so that the light-emitting units 106 in the sub-light-emitting areas of the first column are more Close to the first side 001 of the light-emitting substrate 500, the distance between the center of the light-emitting unit 106 in the sub-light-emitting area of the first column and the first side 001 of the light-emitting substrate 500 is reduced, thereby reducing the left side of the light-emitting substrate 500.
  • the sub-signal lines may also refer to the power signal line PwrL and the feedback signal line FBL.
  • the power signal lines PwrL and feedback signal lines FBL are located near the light-emitting substrate of the light-emitting unit 106 One side of the second side 002 of 500.
  • the power signal line PwrL and the feedback signal line FBL are located on the side away from the second side 002 of the light emitting substrate 500 from the light emitting elements E3 and E4 of the light emitting unit 106 in the sub light emitting region.
  • the power signal line PwrL and the feedback signal line FBL in the Nth column of sub-light-emitting regions are arranged on the second side 002 of the light-emitting unit 106 closest to the light-emitting substrate 500 Left side of light emitting elements E3 and E4.
  • the N-th column of sub-light-emitting areas in the embodiments of the present disclosure are adjusted from the peripheral area to the light-emitting area, so that the light-emitting units 106 in the Nth column of sub-light-emitting areas move toward the second side 002 of the light-emitting substrate 500, so that the N-th column of sub-light-emitting areas
  • the light-emitting unit 106 in the sub-light emitting region is closer to the second side 002 of the light-emitting substrate 500, thereby reducing the distance between the center of the light-emitting unit 106 in the Nth column of sub-light emitting regions and the second side 002
  • the light-emitting substrate 400 in FIG. 10 and the light-emitting substrate 500 in FIGS. 11A-11C can also use the drive electrode 110 as described above, so that all signal lines are connected to the effective terminal 1101 of the drive electrode 110, thereby reducing the size of the light-emitting substrate 400. and the lower frame of the light-emitting substrate 500.
  • the drive electrode 110 as described above, so that all signal lines are connected to the effective terminal 1101 of the drive electrode 110, thereby reducing the size of the light-emitting substrate 400. and the lower frame of the light-emitting substrate 500.
  • the shielding ring GND ESD Ring is also shown in FIG. 11B and FIG. 11C , and the shielding ring GND ESD Ring at least partially surrounds the periphery of the light emitting region 101 to provide electrostatic shielding.
  • the light emitting substrate 100, the light emitting substrate 200, the light emitting substrate 300, and the light emitting substrate 400 may also include shielding rings GND ESD Ring.
  • the shielding ring GND ESD Ring is connected to the effective terminal 1101 of the flexible circuit board 110, and the flexible circuit board 110 provides the same signal for the common voltage signal line GNDL and the shielding ring GND ESD Ring.
  • FIG. 12 shows a block diagram of a backlight 600 including the light-emitting substrate described in any one of the preceding embodiments.
  • the backlight source 600 can be used as a backlight source in a display device to provide a display light source for a display panel in the display device.
  • the backlight source 600 may also be used in any other device that requires a light source, and the embodiment of the present disclosure does not specifically limit the application of the backlight source 600 .
  • the backlight source 600 can basically have the same technical effect as the light-emitting substrate described in the previous embodiments, for the sake of brevity, the technical effect of the backlight source 600 will not be described here again.
  • FIG. 13 shows a block diagram of a display device 700, which includes the light-emitting substrate described in any one of the preceding embodiments.
  • the display device 700 may be a liquid crystal display device, which includes a liquid crystal panel and a backlight arranged on the non-display side of the liquid crystal panel, and the backlight includes the light-emitting substrate described in any of the previous embodiments, for example Can be used to implement HDR dimming for display operation.
  • the liquid crystal display device can have more uniform backlight brightness and better display contrast.
  • the display device 700 may be any suitable display device, including but not limited to mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, navigators, e-books, and any other products or components with display functions.
  • the display device 700 can have substantially the same technical effect as the light-emitting substrate described in the previous embodiments, for the sake of brevity, the technical effect of the display device 700 will not be described here again.
  • a method for manufacturing a light-emitting substrate is provided, which is applicable to the above-described light-emitting substrate 200 and light-emitting substrate 300 , that is, the first conductive portion 108 and the second conductive portion 109 are located on the same layer.
  • the method may include the following steps.
  • the substrate 111 may be any suitable substrate such as a plastic substrate, a silicon substrate, a ceramic substrate, a glass substrate, a quartz substrate, and the embodiment of the present disclosure does not limit the material of the substrate 111 .
  • a buffer layer 112 is formed on the substrate 111 by, for example, a magnetron sputtering method.
  • the buffer layer 112 can be used to reduce the stress on the substrate 111 during the subsequent preparation of the first conductive portion 108 and the second conductive portion 109, so as to avoid bending deformation of the substrate 111; the buffer layer 112 can also prevent the substrate 111 from The impurity in the impurity has an adverse effect on the conductivity of the subsequently formed first conductive portion 108 and second conductive portion 109 .
  • the buffer layer 112 can be any suitable material, for example, it can be SiN.
  • the first conductive part 108 may include the driving voltage signal line VLEDL, the address selection signal line ADDRL, the cascade wiring, the power signal line VccL, the data driving signal line DataL, the common voltage signal line GNDL, the feedback signal line FBL and Optional shielding ring GND ESD Ring.
  • the second conductive portion 109 includes a first pad 1091 and a second pad 1092 , the first pad 1091 is used for mounting the light emitting unit 106 , and the second pad 1092 is used for mounting the driving circuit 107 .
  • the first signal line 103 includes a first portion 1031 , a second portion 1032 and a third portion 1033 .
  • the second signal line 104 includes a first portion 1041 , a second portion 1042 and a third portion 1043 . Since the thickness of a single magnetron sputtering generally does not exceed 1 ⁇ m, multiple sputtering is usually required to form a conductive layer exceeding 1 ⁇ m.
  • the first conductive portion 108, the second conductive portion 109, the first signal line 103, and the second signal line 104 can be formed by the following process: firstly, a Cu layer with a thickness of, for example, 2um is formed on the buffer layer 112, used to transmit various electrical signals; then a CuNi layer with a thickness of, for example, 0.6um is formed on the Cu layer, and the CuNi layer can be used to protect the Cu layer and prevent the surface of the Cu layer with low resistivity from being exposed to oxidation.
  • the first conductive portion 108 , the second conductive portion 109 , the first signal line 103 and the second signal line 104 can be formed by the following process: firstly, on the buffer layer 112 , a layer with a thickness of about MoNb layer, the MoNb layer is used to improve the adhesion between the film layer and the substrate 111; then a Cu layer is formed on the MoNb layer to transmit various electrical signals; finally, a thickness of about The MoNb layer is used to protect the middle Cu layer and prevent the surface of the middle Cu layer with low resistivity from being exposed and oxidized.
  • the seed layer can be formed by using MoNiTi first to improve the metal density in the subsequent electroplating process.
  • the nucleation density of the crystal grains, and then a Cu layer with low resistivity is made by electroplating, and then an anti-oxidation layer is made, and the material can be MoNiTi.
  • the conductive layer can be cleaned, coated, baked, photolithographic, developed, hard baked, etched, stripped and other processes to form the first conductive part 108, the second conductive part 109, the first signal line 103 and the second signal line. Line 104.
  • the preparation of the first conductive portion 108, the second conductive portion 109, the first signal line 103, and the second signal line 104 on the same layer only requires the use of two masks, compared to at least three masks required to form the
  • the conductive structure of different layers can reduce the number of required masks, simplify the process and reduce the production cost.
  • the first insulating layer 113 is formed on the side of the layer where the first conductive portion 108 and the second conductive portion 109 are located away from the substrate 111 by magnetron sputtering.
  • the first insulating layer 113 can be used to protect the first conductive portion 108 and the second conductive portion 109 from being oxidized and corroded by water, oxygen, etc. in the environment.
  • the material of the first insulating layer 113 may be an organic material, an inorganic material, or a combination of an organic material and an inorganic material, and the first insulating layer 113 may be a single film layer, or may include multiple film layers.
  • a second insulating film layer can also be coated on the side of the first insulating layer 113 away from the substrate 111, and the second insulating film layer can be cured, exposed, developed, etched, etc. to form the second insulating film layer.
  • Two insulating layers 114 The material of the second insulating layer 114 may be an organic material, an inorganic material, or a combination of an organic material and an inorganic material, and the second insulating layer 114 may be a single film layer, or may include multiple film layers.
  • the second insulating layer 114 and the first insulating layer 113 are etched to form a plurality of via holes.
  • the light-emitting substrate is cut into a specified shape, and the light-emitting unit 106 and the driving circuit 107 are respectively electrically connected to the first pad 1091 and the second pad 1092 of the second conductive part 109 through the above-mentioned multiple via holes, so as to emit light
  • the unit 106 and the driving circuit 107 are mounted on corresponding pads.
  • Each signal line of the first conductive part 108 is connected to the flexible circuit board 110 at the binding area, so as to realize the electrical connection between the driving circuit 107 and the flexible circuit board 110 , and finally obtain the required light-emitting substrate.
  • the exemplary term “below” can encompass both “above” and “beneath” orientations, and the exemplary term “to the left of” can encompass Both “on the left” and “on the right” orientations.
  • the device may be oriented otherwise (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种发光基板（100,200,300,400,500）、背光源（600）以及显示装置（700）。发光基板（100,200,300,400,500）包括发光区（101）和围绕发光区（101）的周边区（102）。周边区（102）包括第一区域（1021），第一区域（1021）位于发光基板（100,200,300,400,500）的第一侧边（001）和发光区（101）之间，发光基板（100,200,300,400,500）还包括第一信号线（103），第一信号线（103）包括第一部分（1031）和/或第二部分（1032），第一信号线（103）的第一部分（1031）在第一区域（1021）内沿第一方向（D1）延伸，第一信号线（103）的第二部分（1032）延伸至发光区（101）内，当第一信号线（103）包括第一部分（1031）和第二部分（1032）时，第一信号线（103）的第一部分（1031）与第二部分（1032）连接。

Description

发光基板、背光源、显示装置 技术领域
本公开涉及光学技术领域，尤其涉及一种发光基板、包括该发光基板的背光源以及包括该发光基板的显示装置。
背景技术
随着显示技术的不断发展，用户对显示装置的对比度、亮度均匀性以及稳定性提出了越来越高的要求。显示装置通常分为液晶显示装置和有机发光二极管显示装置两大类，液晶显示装置由于具有轻薄化、抗震性好、视角广、对比度高等优点而得到广泛应用。液晶显示装置通常包括显示面板和背光源，背光源通常布置在显示面板的非显示侧以为显示面板的显示操作提供光源。液晶显示装置的对比度、亮度均匀性以及稳定性等特性与背光源的结构和性能相关联。
发明内容
根据本公开的一方面，提供了一种发光基板，包括：发光区和围绕所述发光区的周边区。所述周边区包括第一区域，所述第一区域位于所述发光基板的第一侧边和所述发光区之间，并且所述发光基板还包括第一信号线，所述第一信号线包括第一部分和/或第二部分，所述第一信号线的第一部分在所述第一区域内沿第一方向延伸，所述第一信号线的第二部分延伸至所述发光区内，当所述第一信号线包括第一部分和第二部分时，所述第一信号线的第一部分与第二部分连接。
在一些实施例中，所述周边区还包括第二区域，所述第二区域位于所述发光基板的与所述第一侧边相对的第二侧边和所述发光区之间，并且所述发光基板还包括第二信号线，所述第二信号线的第一部分在所述第二区域内沿所述第一方向延伸，所述第二信号线的第二部分延伸至所述发光区内，并且所述第二信号线的第一部分与第二部分连接。
在一些实施例中，所述第一信号线的第二部分包括沿所述第一方向延伸的至少一个条状结构，所述第一信号线的第一部分和第二部分通过所述第一信号线的第三部分连接；和/或所述第二信号线的第二部 分包括沿所述第一方向延伸的至少一个条状结构，所述第二信号线的第一部分和第二部分通过所述第二信号线的第三部分连接。
在一些实施例中，所述发光区包括阵列布置的多个子发光区，所述多个子发光区沿所述第一方向布置成M行且沿与所述第一方向交叉的第二方向布置成N列，M和N均为大于等于1的正整数。所述第一信号线的第一部分布置在第1列子发光区与所述发光基板的第一侧边之间，所述第一信号线的第二部分的至少一个条状结构中的每一个布置在第1～X列子发光区中的相应一列内。所述第二信号线的第二部分的至少一个条状结构中的每一个布置在第Y～N列子发光区中的相应一列内，所述第二信号线的第一部分布置在第N列子发光区与所述发光基板的第二侧边之间，1≤X＜Y≤N。
在一些实施例中，所述发光基板还包括与所述第一信号线位于同一层的第一导电部，所述第一导电部包括沿所述第一方向延伸的N-1条驱动电压信号线，第2～N列子发光区中的每一列包括一条驱动电压信号线，所述多个子发光区中的每一个包括至少一个发光单元，在第2～N列子发光区中的每一列内，所述驱动电压信号线与该列子发光区内的每个发光单元的第一端连接，并且，所述第一信号线的第一部分与第一列子发光区内的每个发光单元的第一端连接。
在一些实施例中，所述第一信号线的第一部分沿所述第二方向的宽度小于每条驱动电压信号线沿所述第二方向的宽度。
在一些实施例中，所述发光基板还包括第二导电部，其中，所述第二导电部包括多个焊盘。
在一些实施例中，所述第一导电部与所述第二导电部位于同一层。
在一些实施例中，所述第一导电部还包括沿所述第一方向延伸的N-1条公共电压信号线，且所述第一导电部与所述第二信号线位于同一层。第1～N-1列子发光区中的每一列包括一条公共电压信号线，所述多个子发光区中的每一个还包括与所述至少一个发光单元的第二端连接的驱动电路，在第1～N-1列子发光区中的每一列内，所述公共电压信号线与该列子发光区内的每个驱动电路连接，并且所述第二信号线的第一部分与第N列子发光区内的每个驱动电路连接。
在一些实施例中，所述第二信号线的第一部分沿所述第二方向的宽度小于每条公共电压信号线沿所述第二方向的宽度。
在一些实施例中，在第2～N-1列子发光区中的每一列内，所述驱动电压信号线、所述发光单元、所述驱动电路、以及所述公共电压信号线沿着所述第二方向依次排列。
在一些实施例中，所述第一导电部还包括沿所述第一方向延伸的N条反馈信号线，每列子发光区包括一条反馈信号线。在每列子发光区内，各个驱动电路依次级联，所述反馈信号线与最后一级驱动电路连接。在N列子发光区中的至少部分列内，所述反馈信号线位于与所述反馈信号线位于同一列子发光区内的所述公共电压信号线远离所述驱动电路的一侧。
在一些实施例中，在第1～X列子发光区中的每一列内，所述反馈信号线位于与所述反馈信号线位于同一列子发光区内的所述公共电压信号线远离所述驱动电路的一侧，在第Y～N列子发光区中的每一列内，所述反馈信号线位于与所述反馈信号线位于同一列子发光区内的所述驱动电压信号线远离所述驱动电路的一侧。
在一些实施例中，所述发光基板还包括衬底、缓冲层和绝缘层。所述缓冲层位于所述第一导电部和所述第二导电部所在的层与所述衬底之间，所述绝缘层位于所述第一导电部和所述第二导电部所在的层远离所述衬底的一侧。
在一些实施例中，所述发光基板还包括位于所述周边区内的绑定电极。所述绑定电极包括有效端子和空置端子，所述第一信号线的第一部分和第二部分、所述第二信号线的第一部分和第二部分、以及所述第一导电部均与所述绑定电极的有效端子连接。
在一些实施例中，所述公共电压信号线包括第一连接部，所述驱动电压信号线包括第二连接部，所述公共电压信号线通过所述第一连接部与所述绑定电极的有效端子连接，所述驱动电压信号线通过所述第二连接部与所述绑定电极的有效端子连接；第1～N-1列子发光区中的每一列内的公共电压信号线的第一连接部仅位于该列子发光区内；第2～N列子发光区中的每一列内的驱动电压信号线的第二连接部仅位于该列子发光区内。
在一些实施例中，所述发光基板还包括衬底。所述第一导电部和所述第二导电部位于不同层，所述第一导电部位于所述衬底上，所述第二导电部位于所述第一导电部远离所述衬底的一侧。
在一些实施例中，所述发光区包括阵列布置的多个子发光区，所述多个子发光区沿所述第一方向布置成M行且沿与所述第一方向交叉的第二方向布置成N列，M和N均为大于等于1的正整数。所述第一信号线包括第二部分，所述第一信号线的第二部分包括沿所述第一方向延伸的N条子信号线，N列子发光区中的每一列包括一条子信号线。
在一些实施例中，所述多个子发光区中的每一个包括至少一个发光单元，所述至少一个发光单元中的每一个包括彼此连接的多个发光元件，第一列子发光区内的所述子信号线位于该列子发光区内的每个发光单元的多个发光元件中的至少部分发光元件远离所述发光基板的所述第一侧边的一侧，第N列子发光区内的所述子信号线位于该列子发光区内的每个发光单元的多个发光元件中的至少部分发光元件远离所述发光基板的第二侧边的一侧，所述第二侧边与所述第一侧边相对。
在一些实施例中，所述第一导电部和所述第二导电部的材料包括铜。
在一些实施例中，所述发光基板还包括屏蔽环。所述屏蔽环至少部分地围绕所述发光区的外围，并且所述屏蔽环接收的信号与所述公共电压信号线接收的信号相同。
在一些实施例中，所述至少一个发光单元中的每一个包括彼此连接的多个发光元件，所述多个发光元件中的每一个包括次毫米发光二极管或微型发光二极管。
根据本公开的另一方面，提供了一种背光源，该背光源包括在前面任一个实施例中描述的发光基板。
根据本公开的又一方面，提供了一种显示装置，该显示装置包括在前面任一个实施例中描述的发光基板。
附图说明
为了更清楚地描述本公开实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了根据本公开实施例提供的发光基板的第一信号线和第二信号线的布置示意图；
图2示出了根据本公开实施例提供的发光基板的布置示意图；
图3示出了根据本公开实施例提供的发光基板的布置示意图；
图4示出了图3中的发光基板的驱动电路的端子的布置示意图；
图5示出了根据本公开实施例提供的发光基板的布置示意图；
图6示出了图5中的发光基板的驱动电路的端子的布置示意图；
图7A示出了相关技术中发光基板的信号线与绑定电极的连接方式；
图7B示出了根据本公开实施例提供的发光基板的信号线与绑定电极的连接方式；
图8示出了根据本公开实施例提供的发光基板的结构示意图；
图9示出了根据本公开实施例提供的发光基板的发光单元的布置示意图；
图10示出了根据本公开实施例提供的发光基板的布置示意图；
图11A示出了根据本公开实施例提供的发光基板的中心区域的布置示意图；
图11B示出了根据本公开实施例提供的发光基板的左侧区域的布置示意图；
图11C示出了根据本公开实施例提供的发光基板的右侧区域的布置示意图；
图12示出了根据本公开实施例提供的背光源的框图；以及
图13示出了根据本公开实施例提供的显示装置的框图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
可以理解的是，本公开实施例中的各个附图仅仅用于示意性示出各个部件之间的连接关系，附图中各个部件的尺寸并不是按照比例进行绘制的，并且它们的相对位置关系也不一定与实际位置完全对应。在附图中，为了清晰起见，可能夸大了某些区域和层的比例。
随着显示技术的不断发展，为了使用户获得更佳的视觉体验，对显示装置的屏占比提出了更高的要求，这就要求显示装置具有较窄的边框。显示装置的基板的两侧边缘(例如当用户面向显示装置时显示装置的左侧边缘和右侧边缘)附近通常布置有信号线。在相关技术中，为了实现窄边框，通常将基板两侧边缘附近的信号线设计成具有较窄的宽度。但是，宽度较小的信号线会使得信号线具有较大的电阻以及较大的电压降，从而会影响显示装置的发光效率，并且使得显示装置的中心区域和两侧边缘区域的发光亮度不均匀。为了解决因信号线宽度窄而导致的电阻大和电压降大，通常会通过增加信号线厚度的方式来降低信号线的电阻和电压降，但是这大大增加了信号线的材料用量以及工艺制程，从而增加了生产成本，降低了生产效率。
为了解决相关技术中存在的技术问题，本公开的实施例提供了一种发光基板，图1示出了该发光基板100的布置示意图。需要注意的是，为了清楚地示出第一信号线103(以及第二信号线104)的布置，图1省略了发光基板100的其他部件。如图1所示，该发光基板100包括发光区101和围绕发光区101的周边区102。周边区102包括第一区域1021，该第一区域1021位于发光基板100的第一侧边001和发光区101之间。发光基板100还包括第一信号线103，第一信号线103包括第一部分1031和/或第二部分1032，第一信号线103的第一部分1031在第一区域1021内沿第一方向D1延伸，第一信号线103的第二部分1032延伸至发光区101内，当第一信号线103包括第一部分1031和第二部分1032时，第一信号线103的第一部分1031与第二部分1032连接。
需要说明的是，虽然图1示出了第一信号线103包括第一部分1031和第二部分1032，但是如“第一信号线103包括第一部分1031和/或第二部分1032”所表述的，第一信号线103可以仅包括第一部分1031，或者仅包括第二部分1032，或者包括第一部分1031和第二部分1032两者。
第一信号线103的第一部分1031位于发光基板100的第一侧边001和发光区101之间，换句话说，第一信号线103的第一部分1031位于发光基板100的边框区域，即图1中的发光基板100的左侧边框区域。第一信号线103可以是各种适当类型的信号线，例如传输电压的信号 线、传输驱动数据的信号线、连接两个部件或多个部件的走线等，本公开实施例对第一信号线103的类型不做具体限定。
当第一信号线103包括第一部分1031和第二部分1032时，通过使第一信号线103的第一部分1031位于周边区102的第一区域1021内，而与第一信号线103的第一部分1031连接的第二部分1032延伸至发光区101内，可以将第一信号线103的第一部分1031设计成在第二方向D2上具有较窄的宽度，从而有利于缩减第一区域1021沿第二方向D2的宽度，即有利于减少发光基板100的左侧边框的宽度。由于与第一部分1031连接的第二部分1032延伸至发光区101内，相当于将第一信号线103沿第二方向D2的宽度“分成”了两部分，一部分宽度位于周边区102的第一区域1021内(即第一信号线103的第一部分1031的宽度)，一部分宽度位于发光区101内(即第一信号线103的第二部分1032的宽度)，这样，即使减少第一信号线103的第一部分1031的宽度，由于第二部分1032的存在，也不会增加第一信号线103的电阻以及电压降，从而不会影响发光基板100的发光效率，并且使得发光基板100的中心区域和边缘区域具有均匀的发光亮度。另外，通过这种布置方式，无需增加第一信号线103的厚度，因此可以降低生产成本，提高生产效率。
如图1所示，周边区102还包括第二区域1022，第二区域1022位于发光基板100的与第一侧边001相对的第二侧边002和发光区101之间。可选地，发光基板100还可以包括第二信号线104，第二信号线104的第一部分1041在第二区域1022内沿第一方向D1延伸，第二信号线104的第二部分1042延伸至发光区101内，并且第二信号线104的第一部分1041与第二部分1042连接。
第二信号线104的第一部分1041位于发光基板100的第二侧边002和发光区101之间，换句话说，第二信号线104的第一部分1041位于发光基板100的边框区域，即图1中的发光基板100的右侧边框区域。与第一信号线103类似，第二信号线104可以是各种适当类型的信号线，例如传输电压的信号线、传输驱动数据的信号线、连接两个部件或多个部件的走线等，本公开实施例对第二信号线104的类型不做具体限定。
在一些实施例中，第一信号线103的第二部分1032包括沿第一方 向D1延伸的至少一个条状结构1034，第一信号线103的第一部分1031和第二部分1032通过第一信号线103的第三部分1033连接。第一信号线103的第一部分1031、第二部分1032以及第三部分1033使得第一信号线103呈现“梳子”形状。在一些实施例中，第二信号线104的第二部分1042包括沿第一方向D1延伸的至少一个条状结构1044，第二信号线104的第一部分1041和第二部分1042通过第二信号线104的第三部分1043连接。第二信号线104的第一部分1041、第二部分1042以及第三部分1043使得第二信号线104呈现“梳子”形状。当然，第一信号线103和第二信号线104的形状并不仅限于“梳子”形状，其还可以是任意适当的其他形状。例如，当第一信号线103的第二部分1032包括一个条状结构1034时，第一信号线103的形状为“U”形。当第二信号线104的第二部分1042包括一个条状结构1044时，第二信号线104的形状为“U”形。本公开的实施例对第一信号线103和第二信号线104的形状不作具体限定。
与第一信号线103类似，通过使第二信号线104的第一部分1041位于周边区102的第二区域1022内，而与第二信号线104的第一部分1041连接的第二部分1042延伸至发光区101内，可以将第二信号线104的第一部分1041设计成在第二方向D2上具有较窄的宽度，从而有利于减小第二区域1022沿第二方向D2的宽度，即有利于减小发光基板100的右侧边框的宽度。由于与第一部分1041连接的第二部分1042延伸至发光区101内，因此，即使减少第二信号线104的第一部分1041的宽度，由于第二部分1042的存在，也不会增加第二信号线104的电阻以及电压降，从而不会影响发光基板100的发光效率，并且使得发光基板100的中心区域和边缘区域具有均匀的发光亮度。另外，通过这种布置方式，无需增加第二信号线104的厚度，因此可以降低生产成本，提高生产效率。
第一信号线103和第二信号线104这样的布置方式，有利于减少第一区域1021和第二区域1022的宽度，从而有利于实现发光基板100的左侧窄边框和右侧窄边框。此外，现有的大尺寸发光基板通常由若干个小尺寸的发光基板拼接而成，如果发光基板具有较宽的边框，则在多个发光基板拼接时由于拼缝过大容易导致光学效果较差和各个机构无法匹配。相比之下，本申请的发光基板100具有较窄的边框，因 此当拼接多个发光基板100形成更大尺寸的发光基板时，多个发光基板100可以完美地拼接而不会在彼此之间产生过大的拼缝，从而可以改善大尺寸发光基板的光学效果以及各个机构的匹配性。
图2示出了发光基板100更为详细的布线方案。如图2所示，发光区101包括阵列布置的多个子发光区105，多个子发光区105沿第一方向D1布置成M行且沿与第一方向D1交叉的第二方向D2布置成N列，M和N均为大于等于1的正整数。第一方向D1可以是列方向，第二方向D2可以是行方向，第一方向D1和第二方向D2可以互相垂直。第一信号线103的第一部分1031布置在第1列子发光区与发光基板100的第一侧边001之间，也就是说，第一信号线103的第一部分1031位于周边区102的第一区域1021内，且在第1列子发光区的外侧。第一信号线103的第二部分1032的每一个条状结构1034布置在第1～X列子发光区中的相应一列内，其中1≤X＜N。举例来说，当第一信号线103的第二部分1032包括一个条状结构1034时，此时，X＝1，该一个条状结构1034布置在第1列子发光区内。当第一信号线103的第二部分1032包括两个条状结构1034时，此时，X＝2，这两个条状结构1034分别布置在第1列子发光区内和第2列子发光区内。当第一信号线103的第二部分1032包括三个条状结构1034时，此时，X＝3，这三个条状结构1034分别布置在第1列子发光区内、第2列子发光区内和第3列子发光区内。以此类推，当第一信号线103的第二部分1032包括X个条状结构1034时，X个条状结构1034分别布置在第1～X列子发光区内。如图所示，每个条状结构1034位于对应列子发光区内的最右侧，例如，第1列子发光区内的条状结构1034位于第1列子发光区内的最右侧。
第二信号线104的第二部分1042的每一个条状结构1044布置在第Y～N列子发光区中的相应一列内，第二信号线104的第一部分1041布置在第N列子发光区与发光基板100的第二侧边002之间，也就是说，第二信号线104的第一部分1041位于周边区102的第二区域1022内，且在第N列子发光区的外侧，其中1≤X＜Y≤N。举例来说，当第二信号线104的第二部分1042包括一个条状结构1044时，此时，X＝1，该一个条状结构1044布置在第N列子发光区内。当第二信号线104的第二部分1042包括两个条状结构1044时，此时，X＝2，这两个 条状结构1044分别布置在第N列子发光区内和第N-1列子发光区内。当第二信号线104的第二部分1042包括三个条状结构1044时，此时，X＝3，这三个条状结构1044分别布置在第N列子发光区内、第N-1列子发光区内和第N-2列子发光区内。以此类推，当第二信号线104的第二部分1042包括N-Y+1个条状结构1044时，N-Y+1个条状结构1044分别布置在第Y～N列子发光区内。如图所示，每个条状结构1044位于对应列子发光区内的最左侧，例如，第Y列子发光区内的条状结构1044位于第Y列子发光区内的最左侧。需要说明的是，Y与X的差值可以大于等于1。当Y-X＝1时，此时第Y列子发光区紧随在第X列子发光区后面，即第X列子发光区与第Y列子发光区相邻。当Y-X＞1时，此时第X列子发光区与第Y列子发光区之间相隔至少一列子发光区，即第X列子发光区与第Y列子发光区不相邻。
如图2所示，发光基板100还包括与第一信号线103位于同一层的第一导电部108。在本申请中，术语“A与B位于同一层”是指A与B位于同一膜层的表面之上且均与该表面直接接触。在一些实施例中，A与B由同一膜层通过采用同一工艺形成。在一些实施例中，A与B位于同一膜层的表面之上且均与该表面直接接触，并且A与B具有基本相同的高度或厚度。第一导电部108包括沿第一方向D1延伸的N-1条驱动电压信号线VLEDL，第2～N列子发光区中的每一列包括一条驱动电压信号线VLEDL。每个子发光区105包括至少一个发光单元106，在第2～N列子发光区中的每一列内，每条驱动电压信号线VLEDL与该列子发光区内的每个发光单元106的第一端连接，以在所需时段为发光单元106提供驱动电压。并且，第一信号线103的第一部分1031与第1列子发光区内的每个发光单元106的第一端连接。第一信号线103的第一部分1031沿第二方向D2的宽度小于每条驱动电压信号线VLEDL沿第二方向D2的宽度。事实上，可以理解为，在制备过程中，通过对导电层进行构图同时形成第一信号线103和多条驱动电压信号线VLEDL，第一信号线103的第一部分1031相当于对应第1列子发光区的驱动电压信号线VLEDL，以在所需时段为第1列子发光区内的发光单元106提供驱动电压。
第一信号线103的第一部分1031沿第二方向D2的宽度小于每条驱动电压信号线VLEDL沿第二方向D2的宽度，也即，位于发光基板 100的左侧边框区域(即第一区域1021，其为第1列子发光区内的发光单元106的中心至发光基板100的第一侧边001的距离)内的驱动电压信号线VLEDL(即第一信号线103的第一部分1031)的线宽小于位于发光区101内的驱动电压信号线VLEDL的线宽，从而有利于减少发光基板100的左侧边框的宽度，有利于实现窄边框。为了满足电阻和压降需求，驱动电压信号线VLEDL沿第二方向D2的宽度一般在2～15mm，例如在一个示例中为4.0mm。但是发光基板100的左侧边框区域沿第二方向D2的宽度要求在3.8mm以内，如果将线宽为4.0mm的驱动电压信号线VLEDL布置在左侧边框区域，则无法满足产品的窄边框需求。在本申请中，通过使第一信号线103的第一部分1031沿第二方向D2的宽度小于驱动电压信号线VLEDL沿第二方向D2的宽度，例如第一信号线103的第一部分1031沿第二方向D2的宽度可以实现为0.05～0.5mm，可以大大减小发光基板100的左侧边框区域的宽度，完全可以满足产品的窄边框需求。如果需要将这样的发光基板100进行拼接形成大尺寸的发光基板，具有极窄边框的发光基板100也可以完全满足拼接需求，不会影响光学和机构匹配。而且由于第一信号线103的第二部分1032的存在，相当于将第一信号线103的一部分宽度延伸至发光区101内，因此，即使将第一信号线103的第一部分1031的线宽减少至0.05～0.5mm，也可以满足对第一信号线103的电阻和压降需求，不会影响发光基板100的发光效率和发光均匀性。
继续参考图2，第一导电部108还可以包括沿第一方向D1延伸的N-1条公共电压信号线GNDL，且第一导电部108与第二信号线104位于同一层，也即，第一信号线103、第二信号线104以及第一导电部108位于同一层。第1～N-1列子发光区中的每一列包括一条公共电压信号线GNDL，每个子发光区105还包括与至少一个发光单元106的第二端连接的驱动电路107。在第1～N-1列子发光区中的每一列内，每条公共电压信号线GNDL与该列子发光区内的每个驱动电路107连接，以在所需时段提供公共电压(例如接地电压)。第二信号线104的第一部分1041与第N列子发光区内的每个驱动电路107连接。第二信号线104的第一部分1041沿第二方向D2的宽度小于每条公共电压信号线GNDL沿第二方向D2的宽度。事实上，可以理解为，在制备过程中，通过对导电层进行构图同时形成第一信号线103、第二信号线104、驱 动电压信号线VLEDL和公共电压信号线GNDL，第二信号线104的第一部分1041相当于对应第N列子发光区的公共电压信号线GNDL，以在所需时段提供公共电压。
第二信号线104的第一部分1041沿第二方向D2的宽度小于每条公共电压信号线GNDL沿第二方向D2的宽度，也即，位于发光基板100的右侧边框区域(即第二区域1022，其为第N列子发光区内的发光单元106的中心至发光基板100的第二侧边002的距离)内的公共电压信号线GNDL(即第二信号线104的第一部分1041)的线宽小于位于发光区101内的公共电压信号线GNDL的线宽，从而有利于减少发光基板100的右侧边框的宽度，有利于实现窄边框。为了满足电阻和压降需求，公共电压信号线GNDL沿第二方向D2的宽度一般在2～15mm，例如在一个示例中为4.0mm。但是发光基板100的右侧边框区域沿第二方向D2的宽度要求在3.8mm以内，如果将线宽为4.0mm的公共电压信号线GNDL以及其他一些必要的信号走线布置在右侧边框区域，则无法满足产品的窄边框需求。在本申请中，通过使第二信号线104的第一部分1041沿第二方向D2的宽度小于公共电压信号线GNDL沿第二方向D2的宽度，例如第二信号线104的第一部分1041沿第二方向D2的宽度可以实现为0.05～0.5mm，这可以大大减小发光基板100的右侧边框区域的宽度，完全可以满足产品的窄边框需求。如果需要将这样的发光基板100进行拼接形成大尺寸的发光基板，具有极窄边框的发光基板100也可以完全满足拼接需求，不会影响光学和机构匹配。而且由于第二信号线104的第二部分1042的存在，相当于将第二信号线104的一部分宽度延伸至发光区101内，因此，即使将第二信号线104的第一部分1041的线宽减少至0.05～0.5mm，也可以满足对第二信号线104的电阻和压降需求，不会影响发光基板100的发光效率和发光均匀性。
通过使第一信号线103的第一部分1031和第二信号线104的第一部分1041具有非常窄的线宽，可以使发光基板100具有非常窄的左侧边框和右侧边框，这种极窄的左侧边框和右侧边框甚至可以被忽略从而使发光基板100实现为无边框产品。
如图2所示，在第2～N-1列子发光区中的每一列内，驱动电压信号线VLEDL、发光单元106、驱动电路107、以及公共电压信号线GNDL 沿着第二方向D2依次排列，且它们在发光基板100上的正投影彼此不交叠。第一导电部108还可以包括沿第一方向D1延伸的N条反馈信号线FBL，每列子发光区包括一条反馈信号线FBL。在每列子发光区内，各个驱动电路107依次级联，每条反馈信号线FBL与最后一级驱动电路107连接。在N列子发光区中的至少部分列内，每条反馈信号线FBL位于与该条反馈信号线FBL位于同一列子发光区内的公共电压信号线GNDL远离驱动电路107的一侧。在一个示例中，在第1～N-1列子发光区中的每一列内，每条反馈信号线FBL绕过公共电压信号线GNDL且位于公共电压信号线GNDL远离驱动电路107的一侧；在第N列子发光区内，反馈信号线FBL绕过与其相邻且在其右侧的信号线(例如电源信号线PwL)且位于该信号线远离驱动电路107的一侧。也就是说，在第1～N列子发光区内，所有的反馈信号线FBL都按照相同的方式进行布线，这样可简化布线工艺，提高生产效率。在另一个示例中，如图2所示，在第1～X列子发光区中的每一列内，也即在布置有第一信号线103的第二部分1032的条状结构1034的每一列内，每条反馈信号线FBL绕过公共电压信号线GNDL且位于公共电压信号线GNDL远离驱动电路107的一侧；在第Y～N列子发光区中的每一列内，也即在布置有第二信号线104的第二部分1042的条状结构1044的每一列内，反馈信号线FBL绕过驱动电压信号线VLEDL且位于驱动电压信号线VLEDL远离驱动电路107的一侧。通过这种布置方式，可以避免第N列子发光区内的反馈信号线FBL与第二信号线104的第一部分1041交叠。
图3示出了发光基板200的布置方式，图4示出了该发光基板200的驱动电路107的各个端子的布置方式。为了清楚起见，图3仅示出了四列子发光区，即第1列子发光区、第2列子发光区、第N-1列子发光区、以及第N列子发光区。在图3中示出的发光基板200具有与在图2中示出的发光基板100大体相同的构造，并且因此使用相同的附图标记来指代相同的部件。因此，图3中具有与图2相同附图标记的部件的详细作用及功能可以参考对图2的说明，此处不再赘述。
图3的左侧虚线框示出了一个子发光区105的放大图，如该放大图所示，发光基板200还包括第二导电部109，第二导电部109包括多个第一焊盘1091和多个第二焊盘1092，发光单元106安装在第一焊盘 1091上，驱动电路107安装在第二焊盘1092上。在图3的示例中，第一导电部108和第二导电部109位于同一层，在制备过程中，可以对同一导电层进行构图来同时形成第一导电部108和第二导电部109。
如图3和图4所示，每个驱动电路107包括四个端子，分别是地址端子Di、电源端子Pwr、公共电压端子GND、以及输出端子Out。输出端子Out和地址端子Di为驱动电路107的第一列端子，其位于驱动电路107的邻近驱动电压信号线VLEDL的一侧(第1列子发光区内的驱动电路107的第一列端子位于驱动电路107的邻近第一信号线103的第一部分1031的一侧)；公共电压端子GND和电源端子Pwr为驱动电路107的第二列端子，其位于驱动电路107的邻近公共电压信号线GNDL的一侧(第N列子发光区内的驱动电路107的第二列端子位于驱动电路107的邻近第二信号线104的第一部分1041的一侧)。公共电压端子GND和输出端子Out位于多个端子中的第一行，地址端子Di和电源端子Pwr位于多个端子中的第二行。第一导电部108还包括沿第一方向D1延伸的N条选址信号线ADDRL，使得每列子发光区包括一条选址信号线ADDRL。在每列子发光区内，选址信号线ADDRL与第一级驱动电路107的地址端子Di连接。输出端子Out可以复用作驱动电路107的中继端子。选址信号线ADDRL配置为向每列子发光区内的第一级驱动电路107的地址端子Di传输地址信号，第一级驱动电路107接收该地址信号后，可以解析并获得、存储该地址信号中的地址信息以作为该第一级驱动电路107的地址信息，同时还可以使该地址信息递增1或递增另一固定量并将递增后的地址信息(新的地址信息)调制为中继信号，第一级驱动电路107的中继端子Out经由级联走线将该中继信号传输至第二级驱动电路107的地址端子Di，以作为第二级驱动电路107的地址信息。以此类推，最终可以为每列子发光区内的每个驱动电路107配置相应的地址信息。最后一级驱动电路107的输出端子Out连接到反馈信号线FBL。输出端子Out的一端连接至级联走线(最后一级驱动电路107的输出端子Out连接到反馈信号线FBL)，输出端子Out的另一端连接至与该驱动电路107连接的一个发光单元106的第二端。输出端子Out可以在不同的时段分别输出不同的信号，例如，驱动电路107的输出端子Out在一个时段内输出中继信号以作为与该驱动电路107级联的下一级驱动电路107的地址信号， 在另一个时段内向与该驱动电路107连接的发光单元106提供驱动信号以使该发光单元106发光。
第一导电部108还包括沿第一方向D1延伸的N条电源信号线PwrL，每列子发光区包括一条电源信号线PwrL。在每列子发光区内，一条电源信号线PwrL与该列子发光区内的所有驱动电路107的电源端子Pwr连接，并且各个驱动电路107的第一列端子在发光基板200上的正投影与第二列端子在发光基板200上的正投影分别位于该条电源信号线PwrL在发光基板200上的正投影的两侧，也即，该条电源信号线PwrL布置在各个驱动电路107所占用的区域内，且不与各个驱动电路107的第一列端子和第二列端子交叠。通过使每列子发光区内的电源信号线PwrL布置在各个驱动电路107所占用的区域内，可以节省布线空间，并且避免该条电源信号线PwrL与其他信号线之间的交叠。
在图3的示例中，第一信号线103、驱动电压信号线VLEDL、选址信号线ADDRL、电源信号线PwrL、公共电压信号线GNDL、反馈信号线FBL、以及第二信号线104，这些信号线位于同一层，而且它们的投影在发光基板200上的正投影彼此不交叠。在一个示例中，这些信号线中任意相邻两条信号线之间的间距大于等于200um，从而可以避免信号线与信号线之间的信号干扰现象。
图5示出了发光基板300的布置方式，图6示出了该发光基板300的驱动电路107的各个端子的布置方式。为了清楚起见，图5仅示出了四列子发光区，即第1列子发光区、第2列子发光区、第N-1列子发光区、以及第N列子发光区。在图5中示出的发光基板300具有与在图3中示出的发光基板200基本相同的构造，并且因此使用相同的附图标记来指代相同的部件。因此，图5中具有与图3相同附图标记的部件的详细作用及功能可以参考对图3的说明，此处不再赘述。为了简洁起见，下面仅介绍图5中的发光基板300与图3中的发光基板200的不同之处。
参考图5和图6，与图3中的发光基板200不同的是，图5中的发光基板300的驱动电路107的端子的数量为多个，其中，输出端子Out的数量为多个，公共电压端子GND的数量为至少一个。图6示出了输出端子Out的数量为四个且公共电压端子GND的数量为两个，但这仅是一个示例。输出端子Out的数量可以多于四个或少于四个，公共电 压端子GND的数量可以多于两个或少于两个。在本公开的实施例中，输出端子Out的数量至少为两个，公共电压端子GND的数量至少为一个。此外，该驱动电路107还包括数据端子Data。如图5和图6所示，驱动电路107包括两列端子，第一列端子包括电源端子Vcc和四个输出端子Out1、Out2、Out3、Out4，第一列端子位于驱动电路107的邻近驱动电压信号线VLEDL的一侧(第1列子发光区内的驱动电路107的第一列端子位于驱动电路107的邻近第一信号线103的第一部分1031的一侧)；第二列端子包括地址端子Di_in、中继端子Di_out、数据端子Data以及两个公共电压端子GND，第二列端子位于驱动电路107的邻近公共电压信号线GNDL的一侧(第N列子发光区内的驱动电路107的第二列端子位于驱动电路107的邻近第二信号线104的第一部分1041的一侧)。驱动电路107的多个端子布置成五行，地址端子Di_in位于多个端子中的第5行，中继端子Di_out位于多个端子中的第1行。虽然图6中示出电源端子Vcc位于第一列端子中的第3行，数据端子Data位于第2列端子中的第2行，但这仅是一个示例，本公开实施例并不限制电源端子Vcc在第一列端子中的具体位置以及数据端子Data在第2列端子中的具体位置。例如，电源端子Vcc可以位于第一列端子中的第1行～第5行中的任意一个，数据端子Data可以位于第二列端子中的第2行～第4行中的任意一个。
如图所示，驱动电路107的四个输出端子Out1、Out2、Out3、Out4与四个发光单元106的第二端一一对应连接，以为发光单元106提供驱动信号。在图5的示例中，驱动电路107的输出端子与中继端子是不同的端子。该驱动电路107配置为，在一个时段内通过中继端子Di_out输出中继信号以作为与该驱动电路107级联的下一级驱动电路107的地址信号，在另一个时段内通过四个输出端子Out1、Out2、Out3、Out4分别向四个发光单元106提供驱动信号。
如前所述，除了第一信号线103、驱动电压信号线VLEDL、选址信号线ADDRL、公共电压信号线GNDL、反馈信号线FBL以及第二信号线104之外，发光基板300的第一导电部108还包括沿第一方向D1延伸的N条电源信号线VccL和N条数据驱动信号线DataL，使得每列子发光区包括一条电源信号线VccL和一条数据驱动信号线DataL。在每列子发光区内，一条电源信号线VccL与该列子发光区内 的所有驱动电路107的电源端子Vcc连接，一条数据驱动信号线DataL与该列子发光区内的所有驱动电路107的数据端子Data连接。在每列子发光区内，各个驱动电路107的第一列端子在发光基板300上的正投影与第二列端子在发光基板300上的正投影分别位于电源信号线VccL和数据驱动信号线DataL在发光基板300上的正投影的两侧，也即，电源信号线VccL和数据驱动信号线DataL布置在各个驱动电路107所占用的区域内，且不与各个驱动电路107的第一列端子和第二列端子交叠。而且，在每列子发光区内，数据驱动信号线DataL在发光基板300上的正投影与电源信号线VccL在发光基板300上的正投影也不交叠。通过使每列子发光区内的数据驱动信号线DataL和电源信号线VccL布置在各个驱动电路107所占用的区域内，可以节省布线空间，并且避免数据驱动信号线DataL和电源信号线VccL与其他信号线之间的交叠。
发光基板300的第一导电部108和第二导电部109位于同一层。也即，第一信号线103、驱动电压信号线VLEDL、选址信号线ADDRL、电源信号线VccL、数据驱动信号线DataL、公共电压信号线GNDL、反馈信号线FBL、以及第二信号线104，这些信号线位于同一层，而且它们的投影在发光基板300上的正投影彼此不交叠。
除了需要将发光基板的左右侧边框设计成窄边框之外，还迫切需求缩窄发光基板的下侧边框的宽度。在相关技术中，如图7A所示，发光基板包括绑定电极110′。图7A中示出了四列子发光区，即第i列子发光区、第i+1列子发光区、第i+2列子发光区、第i+3列子发光区，并分别用虚线框示出了每列子发光区所占据的区域。每列子发光区包括发光单元106′、公共电压信号线GNDL′和驱动电压信号线VLEDL′，并且公共电压信号线GNDL′和驱动电压信号线VLEDL′均与绑定电极106′电连接。如图所示，第i列子发光区的公共电压信号线GNDL′的一部分延伸至相邻的第i+1列子发光区内并在第i+1列子发光区内与绑定电极106′电连接，第i+3列子发光区的驱动电压信号线VLEDL′的一部分延伸至相邻的第i+2列子发光区内并在第i+2列子发光区内与绑定电极106′电连接。由于第i列子发光区的公共电压信号线GNDL′和第i+3列子发光区的驱动电压信号线VLEDL′分别占据了绑定电极106′位于第i+1列子发光区内的部分和位于第i+2列子发光区内的部分，因此，第 i+1列子发光区内的公共电压信号线GNDL′和驱动电压信号线VLEDL′以及第i+2列子发光区内的公共电压信号线GNDL′和驱动电压信号线VLEDL′为了实现与绑定电极106′的电连接，这些信号线相比于第i列子发光区内和第i+3列子发光区内的信号线需要进一步朝向绑定电极106′的方向延伸(即朝向发光基板的下方延伸)，从而与绑定电极106′电连接。这样，显著增大了发光基板的下边框(即最后一行(第M行)子发光区内的发光单元106′的中心至绑定电极110′的区域)的宽度T′，使得发光基板具有非常宽的下边框，无法满足窄边框的设计需求。
有鉴于此，本公开的实施例提供了一种解决方案，来减小发光基板的下边框的宽度，该方案可以适用于在前面任一个实施例中描述的发光基板，例如发光基板100、200、300。如图7B所示，发光基板还可以包括位于周边区102内的绑定电极110，绑定电极110包括有效端子1101和空置端子1102，第一信号线103的第一部分1031和第二部分1032、第二信号线104的第一部分1041和第二部分1042、以及第一导电部108的所有信号线均只与绑定电极110的有效端子1101电连接。第一信号线103的第一部分1031和第二部分1032的多个条状结构1034均连接到绑定电极110的有效端子1101，绑定电极110的有效端子1101为第一信号线103的第一部分1031和第二部分1032的多个条状结构1034提供相同的信号。第二信号线104的第一部分1041和第二部分1042的多个条状结构1044均连接到绑定电极110的有效端子1101，绑定电极110的有效端子1101为第二信号线104的第一部分1041和第二部分1042的多个条状结构1044提供相同的信号。第一信号线103接收的信号与第二信号线104接收的信号不同。第一导电部108的驱动电压信号线VLEDL、选址信号线ADDRL、电源信号线VccL、公共电压信号线GNDL、反馈信号线FBL以及可选地数据驱动信号线DataL均连接到绑定电极110的有效端子1101。
为了清楚起见，图7B仅示出了最后一行子发光区，即第M行子发光区，其示出了四列子发光区，第i列子发光区、第i+1列子发光区、第i+2列子发光区、第i+3列子发光区，并分别用虚线框示出了每列子发光区所占据的区域。这四列子发光区可以是N列子发光区中任意相邻的四列子发光区。需要说明的是，虽然图7B中示出了绑定电极110与相邻四列子发光区内的信号线相连，但这仅是一个示例。在替代的 示例中，绑定电极110可以与多于四列子发光区内的信号线或少于四列子发光区内的信号线相连，本公开的实施例对绑定电极110所连接的子发光区的列数不做具体限定。为了清楚起见，每列子发光区仅示出了发光单元106、公共电压信号线GNDL和驱动电压信号线VLEDL，省略了其他信号线。公共电压信号线GNDL包括第一连接部115，驱动电压信号线VLEDL包括第二连接部116，每条公共电压信号线GNDL通过其第一连接部115与绑定电极110的有效端子1101电连接，每条驱动电压信号线VLEDL通过其第二连接部116与绑定电极110的有效端子1101电连接。在第1～N-1列子发光区中的每一列内，公共电压信号线GNDL的第一连接部115仅位于该列子发光区内而不延伸至相邻列的子发光区内；在第2～N列子发光区中的每一列内，驱动电压信号线VLEDL的第二连接部116仅位于该列子发光区内而不延伸至相邻列的子发光区内。如图7B所示，第i列子发光区内的公共电压信号线GNDL的第一连接部115和驱动电压信号线VLEDL的第二连接部116完全位于第i列子发光区内而不会延伸至相邻的第i+1列子发光区内，并且在第i列子发光区内与绑定电极110的有效端子1101电连接；第i+1列子发光区内的公共电压信号线GNDL的第一连接部115和驱动电压信号线VLEDL的第二连接部116完全位于第i+1列子发光区内而不会延伸至相邻的第i列子发光区和第i+2列子发光区内，并且在第i+1列子发光区内与绑定电极110的有效端子1101电连接；第i+2列子发光区内的公共电压信号线GNDL的第一连接部115和驱动电压信号线VLEDL的第二连接部116完全位于第i+2列子发光区内而不会延伸至相邻的第i+1列子发光区和第i+3列子发光区内，并且在第i+2列子发光区内与绑定电极110的有效端子1101电连接；第i+3列子发光区内的公共电压信号线GNDL的第一连接部115和驱动电压信号线VLEDL的第二连接部116完全位于第i+3列子发光区内而不会延伸至相邻的第i+2列子发光区内，并且在第i+3列子发光区内与绑定电极110的有效端子1101电连接。由于第i列子发光区内的公共电压信号线GNDL和第i+3列子发光区内的驱动电压信号线VLEDL分别在自身所在列区域内与绑定电极110的有效端子1101电连接，因此，无需第i+1列子发光区内的公共电压信号线GNDL和驱动电压信号线VLEDL以及第i+2列子发光区内的公共电压信号线GNDL和驱动电压信号线 VLEDL进一步朝向绑定电极106的方向延伸。这样，大大减小了发光基板的下边框(即第M行子发光区内的发光单元106的中心至绑定电极110的区域)的宽度T，使得发光基板具有非常窄的下边框，从而可以满足窄边框的设计需求。在一个示例中，发光基板的下边框的宽度T为4.15mm，相较于相关技术中的下边框宽度T′为7.5mm，减小了3.35mm。
需要说明的是，图7B示出的技术方案可以与前面任一实施例中描述的第一信号线103和/或第二信号线104的设计相结合，以实现发光基板的左侧窄边框和/或右侧窄边框以及下方窄边框；也可以不与前面任一实施例中描述的第一信号线103和第二信号线104的设计相结合，即可以仅对发光基板的驱动电极110做出如图7B所示的设计，来单独实现发光基板的下方窄边框。
如图8所示，以上实施例提供的发光基板还可以包括衬底111、缓冲层112和第一绝缘层113。缓冲层112位于第一导电部108和第二导电部109所在的层与衬底111之间，第一绝缘层113位于第一导电部108和第二导电部109所在的层远离衬底111的一侧。衬底111可以为塑料基板、硅基板、陶瓷基板、玻璃基板、石英基板等任意适当的基板，本公开的实施例对衬底111的材料不作限制。缓冲层112可以用来减小在制备第一导电部108和第二导电部109时对衬底111造成的应力，从而可以避免衬底111发生弯曲变形；缓冲层112还可以避免衬底111中的杂质对第一导电部108和第二导电部109的导电性能的不利影响。缓冲层112可以是任意适当的材料，例如，可以是SiN。第一绝缘层113可以用来保护第一导电部108和第二导电部109以防其被环境中的水、氧等氧化腐蚀。第一绝缘层113的材料可以是有机材料、无机材料或者有机材料和无机材料的结合。第一绝缘层113可以是单个膜层，也可以包括多个膜层。可选地，发光基板还可以包括第二绝缘层114，第二绝缘层114位于第一绝缘层113远离衬底111的一侧。第二绝缘层114的材料可以是有机材料、无机材料或者有机材料和无机材料的结合。第二绝缘层114可以是单个膜层，也可以包括多个膜层。
位于同一层的第一导电部108和第二导电部109的材料可以是任意适当的导电材料，本公开实施例对此不做具体限定。例如，第一导 电部108和第二导电部109的材料包括铜。在一个示例中，第一导电部108和第二导电部109可以是Cu和CuNi的叠层。叠层的靠近衬底111的一侧是Cu层，其厚度例如可以是2um，Cu是作为电信号传递通道的优选材料。叠层的远离衬底111的一侧是CuNi层，其厚度例如可以是0.6um，CuNi层可以用于保护Cu层，防止电阻率低的Cu层表面暴露而发生氧化。在另一个示例中，第一导电部108和第二导电部109例如为MoNb/Cu/MoNb的叠层，叠层中靠近衬底111的一侧为MoNb层，厚度大约在
Figure PCTCN2021109826-appb-000001
左右，主要用于提高叠层与衬底111的粘附力；叠层的中间层为Cu层，Cu为电信号传递通道的优选材料；叠层中远离衬底111的一侧为MoNb层，厚度大约在
Figure PCTCN2021109826-appb-000002
左右，MoNb层可以用于保护中间Cu层，防止电阻率低的中间Cu层表面暴露而发生氧化。
图9作为示例示出了每个发光单元106的几种可选的布置方式。每个发光单元106包括彼此连接的多个发光元件，该多个发光元件的第一端与驱动电压信号线VLEDL电连接(第一列子发光区内的发光单元106的多个发光元件的第一端与第一信号线103的第一部分1031电连接)，该多个发光元件的第二端与驱动电路107的输出端子Out电连接。图9(a)示出了每个发光单元106包括彼此串联的四个发光元件，该四个发光元件布置为1列*4行；图9(b)示出了每个发光单元106包括彼此串联的四个发光元件，该四个发光元件布置为2列*2行；图9(c)示出了每个发光单元106包括彼此串联的九个发光元件，该九个发光元件布置为3列*3行。当然，每个发光单元106中的多个发光元件并不限于上述布置方式，它们可以以任意适当的方式布置。在一个示例中，每个发光单元106中的多个发光元件可以彼此并联。在另一个示例中，每个发光单元106中的多个发光元件可以串联和并联结合。每个发光单元106包括的发光元件的数量可以根据实际需求而定，例如根据发光基板的尺寸和所需要的亮度而定。每个发光元件可以为有机发光二级管或无机发光二级管。在一些实施例中，每个发光元件可以为次毫米发光二极管(Mini LED)或微型发光二极管(Mirco LED)。次毫米发光二极管的尺寸例如在100微米～500微米的范围内；微型发光二极管的尺寸例如小于100微米。本公开的实施例对于发光单元106的发光元件的类型和尺寸不作限制。利用次毫米发光二极管或微型发光二极管来作为发光单元106的发光元件，可以实现高动态范围 (High-Dynamic Range，HDR)显示。当这种发光基板应用于显示装置中时，可以显著提升显示装置的对比度。
以上描述了发光基板100、发光基板200以及发光基板300如何实现左侧窄边框、右侧窄边框、以及下方窄边框，在发光基板200和发光基板300中，第一导电部108和第二导电部109位于同一层。下面，描述当第一导电部108和第二导电部109位于不同层时，发光基板如何实现窄边框。
图10示出了发光基板400，在图10中具有与图3相同附图标记的部件的详细作用及功能可以参考对图3的说明，此处不再赘述。为了简洁起见，下面仅介绍图10中的发光基板400与图3中的发光基板200的不同之处。
图10示出了N列子发光区，第一导电部108和第二导电部109位于不同层。第一导电部108包括驱动电压信号线VLEDL、选址信号线ADDRL、电源信号线PwrL、公共电压信号线GNDL、以及反馈信号线FBL，发光单元106和驱动电路107通过这些信号线连接至绑定区的绑定电极，从而接收相应的电信号。第二导电部109包括第一焊盘1091和第二焊盘1092，第一焊盘1091用于安装发光单元106，第二焊盘1092用于安装驱动电路107。第一导电部108位于发光基板400的衬底和第二导电部109之间，第二导电部109位于第一导电部108远离衬底的一侧。在衬底和第一导电部108之间通常会设置有缓冲层，可以用来减小在制备第一导电部108时对衬底造成的应力，从而可以避免衬底发生弯曲变形。第一导电部108和第二导电部109之间通常设置有第一绝缘层，第一导电部108通过第一绝缘层中的过孔与第二导电部109电连接。第一绝缘层可以是无机层或有机层或无机层和有机层的叠层。在第二导电部109远离第一导电部108的一侧上方通常设置有第二绝缘层，用来保护第一导电部108和第二导电部109，防止其被氧化腐蚀。第二绝缘层可以是无机层或有机层或无机层和有机层的叠层。
如图所示，在N列子发光区中的奇数列子发光区内(除了第一列子发光区之外)，每列子发光区包括驱动电压信号线VLEDL、公共电压信号线GNDL、电源信号线PwrL、以及选址信号线ADDRL，并且沿着第二方向D2从左至右，按照驱动电压信号线VLEDL、公共电压信号线GNDL、电源信号线PwrL、以及选址信号线ADDRL的顺序依 次排列。在N列子发光区中的偶数列子发光区内，每列子发光区包括驱动电压信号线VLEDL、公共电压信号线GNDL、电源信号线PwrL、以及反馈信号线FBL，并且沿着第二方向D2从左至右，按照驱动电压信号线VLEDL、公共电压信号线GNDL、电源信号线PwrL、以及反馈信号线FBL的顺序依次排列。可以看出，在每列子发光区内，公共电压信号线GNDL布置在每列子发光区的中心区域而不是边缘区域，这可以使得公共电压信号线GNDL沿第二方向D2可以具有较大的宽度，从而可以在不增加公共电压信号线GNDL的厚度的情况下减小公共电压信号线GNDL上的电压降(例如减小至低于0.5V)。
相邻两列子发光区的驱动电路107串联连接，因此相邻两列子发光区可以共用一条选址信号线ADDRL和一条反馈信号线FBL。以相邻的第1列子发光区和第2列子发光区为例，选址信号线ADDRL与第1列子发光区内的第一级驱动电路107连接。第1列子发光区内的各个驱动电路107依次级联，并且第1列子发光区内的最后一级驱动电路107与第2列子发光区内的第一级驱动电路107连接，第2列子发光区内的各个驱动电路107也依次级联。因此，一条选址信号线ADDRL可以为第1列子发光区和第2列子发光区内的每个驱动电路107提供地址信息。一条反馈信号线FBL与第2列子发光区内的最后一级驱动电路107连接，以将第1列子发光区和第2列子发光区内的每个驱动电路107的信息反馈至外部电路(例如柔性电路板)。
如图所示，发光基板400还包括第一信号线103。第一信号线103的第一部分1031位于发光基板400的周边区102的第一区域1021内，进一步地，第一信号线103的第一部分1031布置在第1列子发光区与发光基板400的第一侧边001之间。第一信号线103的第二部分1032的每一个条状结构1034可以分别布置在第1～X列子发光区中的相应一列内，其中1≤X≤N。举例来说，当第一信号线103的第二部分1032包括一个条状结构1034时，此时，X＝1，该一个条状结构1034布置在第1列子发光区内。当第一信号线103的第二部分1032包括三个条状结构1034时，此时，X＝3，这三个条状结构1034分别布置在第1列子发光区内、第2列子发光区内和第3列子发光区内。当第一信号线103的第二部分1032包括N个条状结构1034时，N个条状结构1034分别布置在第1～N列子发光区内。如图所示，每个条状结构1034位于对应 列子发光区内的最右侧，例如，第1列子发光区内的条状结构1034位于第1列子发光区内的最右侧。
通过使第一信号线103的第一部分1031位于周边区102的第一区域1021内，而与第一信号线103的第一部分1031连接的第二部分1032延伸至发光区101内，可以将第一信号线103的第一部分1031设计成在第二方向D2上具有较窄的宽度，例如宽度为0.05～0.5mm，从而有利于缩减第一区域1021沿第二方向D2的宽度，即有利于缩窄发光基板400的左侧边框的宽度。由于与第一部分1031连接的第二部分1032延伸至发光区101内，因此，即使减少第一信号线103的第一部分1031的宽度，由于第二部分1032的存在，也不会增加第一信号线103的电阻以及电压降，从而不会影响发光基板400的发光效率，并且使得发光基板400的中心区域和边缘区域具有均匀的发光亮度。另外，通过这种布置方式，无需增加第一信号线103的厚度，因此可以降低生产成本，提高生产效率。
图11A-11C示出了减小发光基板500的左侧边框宽度和右侧边框宽度的另一种方案。发光基板500具有与发光基板400基本相同的结构，即第一导电部108和第二导电部109也位于不同层。
在图11A-11C示出的实施例中，第一信号线103仅包括第二部分1032而不包括第一部分1031。第二部分1032位于发光区101内。第一信号线103的第二部分1032包括沿第一方向D1延伸的N条子信号线，每列子发光区包括一条子信号线。需要说明的是，这里的第一信号线103的第二部分1032与前面实施例中描述的第一信号线103的第二部分1032所起的作用不同。在前面的实施例中，第二部分1032作为齿状结构，与第一部分1031和第三部分1033共同构成“梳状”结构，第二部分1032被用来拓宽第一部分1031的宽度。而在关于图11A-11C的实施例中，第一信号线103仅包括第二部分1032而不包括第一部分1031和第三部分1033，位于发光区101内的第二部分1032包括N条子信号线，每列子发光区包括一条子信号线。N条子信号线为彼此独立且彼此绝缘的信号线，其用来传输相应的电学信号。该子信号线可以是驱动电压信号线VLEDL、电源信号线PwrL、反馈信号线FBL。关于子信号线的具体类型，下文将有更详细的介绍。
如关于图10所描述的，相邻两列子发光区按照驱动电压信号线 VLEDL、公共电压信号线GNDL、电源信号线PwrL、选址信号线ADDRL、驱动电压信号线VLEDL、公共电压信号线GNDL、电源信号线PwrL、以及反馈信号线FBL的顺序从左至右依次排列。在每列子发光区内，驱动电压信号线VLEDL位于发光单元106的左侧。在奇数列子发光区内，电源信号线PwrL和选址信号线ADDRL位于发光单元106的右侧；在偶数列子发光区内，电源信号线PwrL和反馈信号线FBL位于发光单元106的右侧。如果N列子发光区均按照上述方式进行布线，则第1列子发光区内的发光单元106的中心至发光基板500的第一侧边001之间(即发光基板500的左侧边框区域)设置有较宽的驱动电压信号线VLEDL，第N列子发光区内的发光单元106的中心至发光基板500的第二侧边002之间(即发光基板500的右侧边框区域)设置有电源信号线PwrL和反馈信号线FBL，这不利于发光基板500实现窄边框，也无法满足基板拼接时对光学和机构匹配的规格要求。
在图11A-11C的示例中，如图11A所示，发光基板500的中心区域保持上述布线方案，即相邻两列子发光区按照驱动电压信号线VLEDL、公共电压信号线GNDL、电源信号线PwrL、选址信号线ADDRL、驱动电压信号线VLEDL、公共电压信号线GNDL、电源信号线PwrL、以及反馈信号线FBL的顺序从左至右依次排列。发光基板500的中心区域可以是指发光基板500第j～k列子发光区所占据的区域，例如3≤j＜k≤N-2。
子信号线可以指驱动电压信号线VLEDL。在第2～N列子发光区内，驱动电压信号线VLEDL位于每列子发光区内的发光单元106的靠近发光基板500的第一侧边001的一侧。而在第1列子发光区内，驱动电压信号线VLEDL位于该列子发光区内的发光单元106的发光元件E1和E2远离发光基板500的第一侧边001的一侧。如图11B所示，在发光基板500的左侧区域，将第1列子发光区内的驱动电压信号线VLEDL布置在发光单元106的最靠近发光基板500的第一侧边001的发光元件E1和E2的右侧，也即第1列子发光区内的驱动电压信号线VLEDL位于该列子发光区内的发光元件E1和E2远离周边区的一侧，并且调整电源信号线PwrL的位置使其位于驱动电压信号线VLEDL和公共电压信号线GNDL之间。这样，相比于相关技术中对应第1列子发光区的驱动电压信号线VLEDL位于发光基板的左侧边框区域(即位于周边 区)，本公开实施例中的第1列子发光区内的驱动电压信号线VLEDL从周边区调整到发光区内，而使第1列子发光区内的发光单元106朝向发光基板500的第一侧边001移动，这样使得第1列子发光区内的发光单元106更为靠近发光基板500的第一侧边001，减小了第1列子发光区内的发光单元106的中心至发光基板500的第一侧边001之间的距离，从而减小了发光基板500的左侧边框宽度。
子信号线也可以指电源信号线PwrL和反馈信号线FBL。在1～N-1列子发光区中的需要设置电源信号线PwrL和反馈信号线FBL的列(例如偶数列子发光区)内，电源信号线PwrL和反馈信号线FBL位于发光单元106的靠近发光基板500的第二侧边002的一侧。而在第N列子发光区内，电源信号线PwrL和反馈信号线FBL位于该列子发光区内的发光单元106的发光元件E3和E4远离发光基板500的第二侧边002的一侧。如图11C所示，在发光基板500的右侧区域，将第N列子发光区内的电源信号线PwrL和反馈信号线FBL布置在发光单元106的最靠近发光基板500的第二侧边002的发光元件E3和E4的左侧。这样，相比于相关技术中对应第N列子发光区的电源信号线PwrL和反馈信号线FBL位于发光基板的右侧边框区域(即位于周边区)，本公开实施例中的第N列子发光区内的电源信号线PwrL和反馈信号线FBL从周边区调整到发光区内，使得第N列子发光区内的发光单元106朝向发光基板500的第二侧边002移动，这样使得第N列子发光区内的发光单元106更为靠近发光基板500的第二侧边002，从而减小了第N列子发光区内的发光单元106的中心至发光基板500的第二侧边002之间的距离，减小了发光基板500的右侧边框宽度。
通过优化发光基板500的第1列子发光区内的驱动电压信号线VLEDL和电源信号线PwrL的布线方式，以及优化第N列子发光区内的电源信号线PwrL和反馈信号线FBL的布线方式，可以减小发光基板500的左侧边框宽度和右侧边框宽度，使得发光基板500实现为窄边框，并且可以满足基板拼接时对光学和机构匹配的规格要求。
需要说明的是，虽然发光基板500的第1列子发光区内的某些信号线(驱动电压信号线VLEDL和电源信号线PwrL)调整了位置，且发光基板500的第N列子发光区内的某些信号线(电源信号线PwrL和反馈信号线FBL)调整了位置，而发光基板500的中心区域的多列 子发光区内的信号线没有调整位置，但是可以通过相应的技术手段(比如调整各条信号线之间的线间距)来保持发光基板500的各列子发光区之间具有基本相同的间距。
图10中的发光基板400和图11A-11C中的发光基板500也可以采用如前所述的驱动电极110，使得所有信号线均连接至驱动电极110的有效端子1101，从而减小发光基板400和发光基板500的下方边框。具体的布置方式可参考前面关于图7B的描述，为了简洁起见，此处不再赘述。
图11B和图11C中还示出了屏蔽环GND ESD Ring，屏蔽环GND ESD Ring至少部分地围绕发光区101的外围，以提供静电屏蔽。虽然未示出，发光基板100、发光基板200、发光基板300、发光基板400也可以包括屏蔽环GND ESD Ring。屏蔽环GND ESD Ring连接至柔性电路板110的有效端子1101，柔性电路板110为公共电压信号线GNDL和屏蔽环GND ESD Ring提供相同的信号。
根据本公开的另一方面，提供了一种背光源，图12示出了背光源600的框图，该背光源600包括在前面任一个实施例中描述的发光基板。该背光源600可以作为显示装置中的背光源，为显示装置中的显示面板提供显示光源。当然，背光源600也可以用于任何其他需要光源的设备，本公开的实施例对背光源600的用途不做具体限定。
由于背光源600可以与前面各个实施例描述的发光基板具有基本相同的技术效果，因此，出于简洁的目的，此处不再重复描述背光源600的技术效果。
根据本公开的又一方面，提供了一种显示装置，图13示出了显示装置700的框图，该显示装置700包括在前面任一个实施例中描述的发光基板。在一些实施例中，该显示装置700可以为液晶显示装置，其包括液晶面板和设置在该液晶面板的非显示侧的背光源，背光源包括在前面任一个实施例中描述的发光基板，例如可以用于实现HDR调光以用于显示操作。该液晶显示装置可以具有更均匀的背光亮度，具有更好的显示对比度。显示装置700可以为任意适当的显示装置，包括但不限于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、电子书等任何具有显示功能的产品或部件。
由于显示装置700可以与前面各个实施例描述的发光基板具有基 本相同的技术效果，因此，出于简洁的目的，此处不再重复描述显示装置700的技术效果。
根据本公开的再一方面，提供了一种制造发光基板的方法，该方法可以适用于前面描述的发光基板200和发光基板300，即第一导电部108和第二导电部109位于同一层。该方法可以包括以下步骤。
首先，提供衬底111。衬底111可以为塑料基板、硅基板、陶瓷基板、玻璃基板、石英基板等任意适当的基板，本公开的实施例对衬底111的材料不作限制。
然后，在衬底111上例如通过磁控溅射方法形成缓冲层112。缓冲层112可以用来减小在后续制备第一导电部108和第二导电部109时对衬底111造成的应力，从而可以避免衬底111发生弯曲变形；缓冲层112还可以避免衬底111中的杂质对后续形成的第一导电部108和第二导电部109的导电性能的不利影响。缓冲层112可以是任意适当的材料，例如，可以是SiN。
接着，在缓冲层112上通过磁控溅射方法或电镀方法形成导电层，通过对导电层进行构图以同时形成第一导电部108、第二导电部109、第一信号线103以及第二信号线104。第一导电部108可以包括如上所述的驱动电压信号线VLEDL、选址信号线ADDRL、级联走线、电源信号线VccL、数据驱动信号线DataL、公共电压信号线GNDL、反馈信号线FBL以及可选的屏蔽环GND ESD Ring。第二导电部109包括第一焊盘1091和第二焊盘1092，第一焊盘1091用于安装发光单元106，第二焊盘1092用于安装驱动电路107。第一信号线103包括第一部分1031、第二部分1032以及第三部分1033。第二信号线104包括第一部分1041、第二部分1042以及第三部分1043。由于单次磁控溅射的厚度一般不超过1μm，因此在制作超过1μm的导电层时，通常需要多次溅射来形成。在一个示例中，第一导电部108、第二导电部109、第一信号线103以及第二信号线104可以通过如下工艺来形成：首先在缓冲层112上形成厚度例如为2um的Cu层，以用来传递各种电信号；然后在Cu层上形成厚度例如为0.6um的CuNi层，该CuNi层可以用于保护Cu层，防止电阻率低的Cu层表面暴露而发生氧化。在另一个示例中，第一导电部108、第二导电部109、第一信号线103以及第二信号线104可以通过如下工艺来形成：首先在缓冲层112上形成厚度大 约为
Figure PCTCN2021109826-appb-000003
的MoNb层，该MoNb层用来提高膜层与衬底111的粘附力；然后在MoNb层上形成Cu层，以用来传递各种电信号；最后在Cu层上形成厚度大约为
Figure PCTCN2021109826-appb-000004
的MoNb层，以保护中间的Cu层，防止电阻率低的中间Cu层表面暴露而发生氧化。在利用电镀法在衬底111上形成第一导电部108、第二导电部109、第一信号线103以及第二信号线104时，可以先利用MoNiTi形成种子层，以提高后续电镀工艺中金属晶粒的成核密度，之后再通过电镀制作电阻率低的Cu层，之后再制作防氧化层，材料可以为MoNiTi。导电层可以经过清洗、涂覆、烘烤、光刻、显影、硬烤、刻蚀、剥离等工艺后，形成第一导电部108、第二导电部109、第一信号线103以及第二信号线104。制备位于同一层的第一导电部108、第二导电部109、第一信号线103以及第二信号线104仅需要使用两张掩膜版，相比于至少需要三张掩膜版来形成位于不同层的导电结构，可以减少所需掩膜版的数量，简化工艺制程，降低生产成本。
然后，在第一导电部108和第二导电部109所在的层远离衬底111的一侧通过磁控溅射方法形成第一绝缘层113。第一绝缘层113可以用来保护第一导电部108和第二导电部109以防止其被环境中的水、氧等氧化腐蚀。第一绝缘层113的材料可以是有机材料、无机材料或者有机材料和无机材料的结合，第一绝缘层113可以是单个膜层，也可以包括多个膜层。
可选地，还可以在第一绝缘层113远离衬底111的一侧涂覆第二绝缘膜层，通过对该第二绝缘膜层进行固化、曝光、显影、刻蚀等若干处理，形成第二绝缘层114。第二绝缘层114的材料可以是有机材料、无机材料或者有机材料和无机材料的结合，第二绝缘层114可以是单个膜层，也可以包括多个膜层。当发光基板上形成有第二绝缘层114时，对第二绝缘层114和第一绝缘层113进行刻蚀以形成多个过孔。
最后，将发光基板切割成规定的外形，使发光单元106和驱动电路107分别通过上述多个过孔与第二导电部109的第一焊盘1091和第二焊盘1092电连接，以将发光单元106和驱动电路107安装在相应的焊盘上。第一导电部108的各条信号线连接到绑定区处的柔性电路板110，从而实现驱动电路107与柔性电路板110的电连接，最终得到所需的发光基板。
该方法实现的其他技术效果可以参考前面各个实施例描述的发光基板的技术效果，因此，出于简洁的目的，此处不再重复描述方法的技术效果。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料等。在其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本公开的主要技术创意。
诸如“行”、“列”、“上”、“下”、“左”、“右”等等之类的空间相对术语在本文中可以为了便于描述而用来描述如图中所图示的一个元件或特征与另一个(些)元件或特征的关系。将理解的是，这些空间相对术语意图涵盖除了图中描绘的取向之外在使用或操作中的器件的不同取向。例如，如果翻转图中的器件，那么被描述为“在其他元件或特征之下”或“在其他元件或特征下面”或“在其他元件或特征下方”的元件将取向为“在其他元件或特征之上”，被描述为“在其他元件的左侧”的元件将取向为“在其他元件的右侧”。因此，示例性术语“在...之下”可以涵盖“在...之上″和″在...之下″的取向两者，示例性术语“在...左侧”可以涵盖“在...左侧″和″在...右侧″的取向两者。器件可以取向为其他方式(旋转90度或以其他取向)并且相应地解释本文中使用的空间相对描述符。另外，还将理解的是，当层被称为“在两个层之间”时，其可以是在该两个层之间的唯一的层，或者也可以存在一个或多个中间层。
在本说明书的描述中，参考术语“一个实施例”、“另一个实施例”等的描述意指结合该实施例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特 征进行结合和组合。另外，需要说明的是，本说明书中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
如本领域技术人员将理解的，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是这并非要求或者暗示必须按照该特定顺序来执行这些步骤，除非上下文另有明确说明。附加的或可替换的，可以将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行。此外，在步骤之间可以插入其他方法步骤。插入的步骤可以表示诸如本文所描述的方法的改进，或者可以与该方法无关。此外，在下一步骤开始之前，给定步骤可能尚未完全完成。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此。任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (24)

  1. 一种发光基板，包括发光区和围绕所述发光区的周边区，其中，
    所述周边区包括第一区域，所述第一区域位于所述发光基板的第一侧边和所述发光区之间，并且
    所述发光基板还包括第一信号线，所述第一信号线包括第一部分和/或第二部分，所述第一信号线的第一部分在所述第一区域内沿第一方向延伸，所述第一信号线的第二部分延伸至所述发光区内，当所述第一信号线包括第一部分和第二部分时，所述第一信号线的第一部分与第二部分连接。
  2. 根据权利要求1所述的发光基板，其中，
    所述周边区还包括第二区域，所述第二区域位于所述发光基板的与所述第一侧边相对的第二侧边和所述发光区之间，并且
    所述发光基板还包括第二信号线，所述第二信号线的第一部分在所述第二区域内沿所述第一方向延伸，所述第二信号线的第二部分延伸至所述发光区内，并且所述第二信号线的第一部分与第二部分连接。
  3. 根据权利要求2所述的发光基板，其中，
    所述第一信号线的第二部分包括沿所述第一方向延伸的至少一个条状结构，所述第一信号线的第一部分和第二部分通过所述第一信号线的第三部分连接；和/或
    所述第二信号线的第二部分包括沿所述第一方向延伸的至少一个条状结构，所述第二信号线的第一部分和第二部分通过所述第二信号线的第三部分连接。
  4. 根据权利要求3所述的发光基板，其中，所述发光区包括阵列布置的多个子发光区，所述多个子发光区沿所述第一方向布置成M行且沿与所述第一方向交叉的第二方向布置成N列，M和N均为大于等于1的正整数，
    所述第一信号线的第一部分布置在第1列子发光区与所述发光基板的第一侧边之间，所述第一信号线的第二部分的至少一个条状结构中的每一个布置在第1～X列子发光区中的相应一列内，
    所述第二信号线的第二部分的至少一个条状结构中的每一个布置在第Y～N列子发光区中的相应一列内，所述第二信号线的第一部分布 置在第N列子发光区与所述发光基板的第二侧边之间，1≤X＜Y≤N。
  5. 根据权利要求4所述的发光基板，还包括与所述第一信号线位于同一层的第一导电部，其中，
    所述第一导电部包括沿所述第一方向延伸的N-1条驱动电压信号线，第2～N列子发光区中的每一列包括一条驱动电压信号线，所述多个子发光区中的每一个包括至少一个发光单元，在第2～N列子发光区中的每一列内，所述驱动电压信号线与该列子发光区内的每个发光单元的第一端连接，并且，
    所述第一信号线的第一部分与第一列子发光区内的每个发光单元的第一端连接。
  6. 根据权利要求5所述的发光基板，其中，所述第一信号线的第一部分沿所述第二方向的宽度小于每条驱动电压信号线沿所述第二方向的宽度。
  7. 根据权利要求5或6所述的发光基板，还包括第二导电部，其中，所述第二导电部包括多个焊盘。
  8. 根据权利要求7所述的发光基板，其中，所述第一导电部与所述第二导电部位于同一层。
  9. 根据权利要求8所述的发光基板，其中，所述第一导电部还包括沿所述第一方向延伸的N-1条公共电压信号线，且所述第一导电部与所述第二信号线位于同一层，
    第1～N-1列子发光区中的每一列包括一条公共电压信号线，所述多个子发光区中的每一个还包括与所述至少一个发光单元的第二端连接的驱动电路，在第1～N-1列子发光区中的每一列内，所述公共电压信号线与该列子发光区内的每个驱动电路连接，并且
    所述第二信号线的第一部分与第N列子发光区内的每个驱动电路连接。
  10. 根据权利要求9所述的发光基板，其中，所述第二信号线的第一部分沿所述第二方向的宽度小于每条公共电压信号线沿所述第二方向的宽度。
  11. 根据权利要求9或10所述的发光基板，其中，在第2～N-1列子发光区中的每一列内，所述驱动电压信号线、所述发光单元、所述驱动电路、以及所述公共电压信号线沿着所述第二方向依次排列。
  12. 根据权利要求11所述的发光基板，其中，所述第一导电部还包括沿所述第一方向延伸的N条反馈信号线，每列子发光区包括一条反馈信号线，
    在每列子发光区内，各个驱动电路依次级联，所述反馈信号线与最后一级驱动电路连接，
    在N列子发光区中的至少部分列内，所述反馈信号线位于与所述反馈信号线位于同一列子发光区内的所述公共电压信号线远离所述驱动电路的一侧。
  13. 根据权利要求12所述的发光基板，其中，
    在第1～X列子发光区中的每一列内，所述反馈信号线位于与所述反馈信号线位于同一列子发光区内的所述公共电压信号线远离所述驱动电路的一侧，
    在第Y～N列子发光区中的每一列内，所述反馈信号线位于与所述反馈信号线位于同一列子发光区内的所述驱动电压信号线远离所述驱动电路的一侧。
  14. 根据权利要求8-13中任一项所述的发光基板，还包括衬底、缓冲层和绝缘层，
    其中，所述缓冲层位于所述第一导电部和所述第二导电部所在的层与所述衬底之间，所述绝缘层位于所述第一导电部和所述第二导电部所在的层远离所述衬底的一侧。
  15. 根据权利要求9-14中任一项所述的发光基板，还包括位于所述周边区内的绑定电极，
    其中，所述绑定电极包括有效端子和空置端子，所述第一信号线的第一部分和第二部分、所述第二信号线的第一部分和第二部分、以及所述第一导电部均与所述绑定电极的有效端子连接。
  16. 根据权利要求15所述的发光基板，其中，
    所述公共电压信号线包括第一连接部，所述驱动电压信号线包括第二连接部，所述公共电压信号线通过所述第一连接部与所述绑定电极的有效端子连接，所述驱动电压信号线通过所述第二连接部与所述绑定电极的有效端子连接；
    第1～N-1列子发光区中的每一列内的公共电压信号线的第一连接部仅位于该列子发光区内；
    第2～N列子发光区中的每一列内的驱动电压信号线的第二连接部仅位于该列子发光区内。
  17. 根据权利要求7所述的发光基板，还包括衬底，
    其中，所述第一导电部和所述第二导电部位于不同层，所述第一导电部位于所述衬底上，所述第二导电部位于所述第一导电部远离所述衬底的一侧。
  18. 根据权利要求1所述的发光基板，其中，
    所述发光区包括阵列布置的多个子发光区，所述多个子发光区沿所述第一方向布置成M行且沿与所述第一方向交叉的第二方向布置成N列，M和N均为大于等于1的正整数，
    所述第一信号线包括第二部分，所述第一信号线的第二部分包括沿所述第一方向延伸的多条子信号线，N列子发光区中的每一列包括所述子信号线。
  19. 根据权利要求18所述的发光基板，其中，所述多个子发光区中的每一个包括至少一个发光单元，所述至少一个发光单元中的每一个包括彼此连接的多个发光元件，第一列子发光区内的所述子信号线位于该列子发光区内的每个发光单元的多个发光元件中的至少部分发光元件远离所述发光基板的所述第一侧边的一侧，第N列子发光区内的所述子信号线位于该列子发光区内的每个发光单元的多个发光元件中的至少部分发光元件远离所述发光基板的第二侧边的一侧，所述第二侧边与所述第一侧边相对。
  20. 根据权利要求7-17中任一项所述的发光基板，其中，所述第一导电部和所述第二导电部的材料包括铜。
  21. 根据权利要求9-16中任一项所述的发光基板，还包括屏蔽环，其中，所述屏蔽环至少部分地围绕所述发光区的外围，并且所述屏蔽环接收的信号与所述公共电压信号线接收的信号相同。
  22. 根据权利要求5-18中任一项所述的发光基板，其中，所述至少一个发光单元中的每一个包括彼此连接的多个发光元件，所述多个发光元件中的每一个包括次毫米发光二极管或微型发光二极管。
  23. 一种背光源，包括根据权利要求1-22中任一项所述的发光基板。
  24. 一种显示装置，包括根据权利要求1-22中任一项所述的发光基板。
PCT/CN2021/109826 2021-07-30 2021-07-30 发光基板、背光源、显示装置 WO2023004797A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/CN2021/109826 WO2023004797A1 (zh) 2021-07-30 2021-07-30 发光基板、背光源、显示装置
US17/757,792 US20230034742A1 (en) 2021-07-30 2021-07-30 Light-emitting substrate, backlight, display device
CN202180002034.2A CN116324601A (zh) 2021-07-30 2021-07-30 发光基板、背光源、显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/109826 WO2023004797A1 (zh) 2021-07-30 2021-07-30 发光基板、背光源、显示装置

Publications (1)

Publication Number Publication Date
WO2023004797A1 true WO2023004797A1 (zh) 2023-02-02

Family

ID=85037422

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/109826 WO2023004797A1 (zh) 2021-07-30 2021-07-30 发光基板、背光源、显示装置

Country Status (3)

Country Link
US (1) US20230034742A1 (zh)
CN (1) CN116324601A (zh)
WO (1) WO2023004797A1 (zh)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1551062A (zh) * 2003-05-12 2004-12-01 ������������ʽ���� 数据驱动器及电子光学装置
US20140239823A1 (en) * 2013-02-26 2014-08-28 Samsung Display Co., Ltd. Organic light emitting display device
CN110767731A (zh) * 2019-10-31 2020-02-07 京东方科技集团股份有限公司 显示面板及显示装置
CN110796980A (zh) * 2019-11-29 2020-02-14 上海天马有机发光显示技术有限公司 一种显示面板及显示装置
CN111462687A (zh) * 2020-06-09 2020-07-28 上海天马有机发光显示技术有限公司 显示面板及其驱动方法、显示装置
CN111952343A (zh) * 2020-08-21 2020-11-17 昆山国显光电有限公司 阵列基板及显示面板
WO2021092875A1 (zh) * 2019-11-15 2021-05-20 京东方科技集团股份有限公司 阵列基板及显示装置
CN113160745A (zh) * 2021-03-31 2021-07-23 合肥维信诺科技有限公司 显示面板及显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1551062A (zh) * 2003-05-12 2004-12-01 ������������ʽ���� 数据驱动器及电子光学装置
US20140239823A1 (en) * 2013-02-26 2014-08-28 Samsung Display Co., Ltd. Organic light emitting display device
CN110767731A (zh) * 2019-10-31 2020-02-07 京东方科技集团股份有限公司 显示面板及显示装置
WO2021092875A1 (zh) * 2019-11-15 2021-05-20 京东方科技集团股份有限公司 阵列基板及显示装置
CN110796980A (zh) * 2019-11-29 2020-02-14 上海天马有机发光显示技术有限公司 一种显示面板及显示装置
CN111462687A (zh) * 2020-06-09 2020-07-28 上海天马有机发光显示技术有限公司 显示面板及其驱动方法、显示装置
CN111952343A (zh) * 2020-08-21 2020-11-17 昆山国显光电有限公司 阵列基板及显示面板
CN113160745A (zh) * 2021-03-31 2021-07-23 合肥维信诺科技有限公司 显示面板及显示装置

Also Published As

Publication number Publication date
CN116324601A (zh) 2023-06-23
US20230034742A1 (en) 2023-02-02

Similar Documents

Publication Publication Date Title
GB2373623A (en) Liquid crystal display panel and method for manufacturing the same
CN113223420B (zh) 一种显示面板及显示装置
TW201626352A (zh) 顯示裝置
TW200521917A (en) Pixel element substrate, display device, electronic device, and method for manufacturing the pixel element substrate
WO2020168634A1 (zh) 阵列基板、显示面板及显示装置
TWI751857B (zh) 發光基板及顯示裝置
WO2021087726A1 (zh) 一种阵列基板及其制作方法、显示装置
CN110632795A (zh) 背光源及其背板、制作方法
WO2023004797A1 (zh) 发光基板、背光源、显示装置
US20230280855A1 (en) Touch detection device, display device including the same, and method for manufacturing the same
JP2005252226A (ja) 表示パネル用のリードパッド構造とその製造方法およびリードパッドアレイ構造
WO2022266795A1 (zh) 驱动背板及其制作方法、显示装置
WO2022134019A1 (zh) 驱动背板及显示装置
WO2023004798A1 (zh) 发光基板及其制造方法、背光源、显示装置
WO2022160203A1 (zh) 驱动背板、显示面板及显示装置
WO2023050209A1 (zh) 发光基板及显示装置
WO2024130716A1 (zh) 发光模组和显示装置
WO2023109233A1 (zh) 发光二极管驱动背板及显示装置
WO2022205343A1 (zh) 发光基板及显示装置
US20240234657A1 (en) Array substrate, backlight, display device
TWI851156B (zh) 顯示裝置
WO2024031372A1 (zh) 基板和电子装置
WO2024031371A1 (zh) 基板和电子装置
WO2022227031A1 (zh) 阵列基板和显示装置
US20240274763A1 (en) Backlight module and manufacturing method therefor, and display apparatus

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21951387

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 27/05/2024)