WO2022027726A1 - Led灯板、拼接式led灯板及显示装置 - Google Patents

Led灯板、拼接式led灯板及显示装置 Download PDF

Info

Publication number
WO2022027726A1
WO2022027726A1 PCT/CN2020/109614 CN2020109614W WO2022027726A1 WO 2022027726 A1 WO2022027726 A1 WO 2022027726A1 CN 2020109614 W CN2020109614 W CN 2020109614W WO 2022027726 A1 WO2022027726 A1 WO 2022027726A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate driving
led
signal
led chips
signal wiring
Prior art date
Application number
PCT/CN2020/109614
Other languages
English (en)
French (fr)
Inventor
刘凡成
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/981,351 priority Critical patent/US11563051B2/en
Priority to EP20842541.3A priority patent/EP4198622A1/en
Publication of WO2022027726A1 publication Critical patent/WO2022027726A1/zh

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133603—Direct backlight with LEDs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G09G3/342—Control of illumination source using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines
    • G09G3/3426—Control of illumination source using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines the different display panel areas being distributed in two dimensions, e.g. matrix

Definitions

  • the present application relates to the field of display technology, in particular to an LED light panel, a spliced LED light panel and a display device.
  • Mini LED Mini Light Emitting Diode, Mini Light Emitting Diode
  • Mini Light Emitting Diode backlight module has attracted more and more attention due to its advantages of high brightness, ultra-narrow frame, special shape and the ability to achieve partial partition design.
  • higher partitions generally mean better displays, but currently Mini
  • the driving method of LED is generally passive driving. When more partitions are realized, more driver chips are usually required, which will bring about a substantial increase in cost and is not conducive to realizing narrow borders and integrated display.
  • the present application provides an LED light panel, a spliced LED light panel and a display device to solve the technical problem that the current active Mini LED driving structure design cannot meet the requirement of free splicing.
  • the application provides an LED light panel, which includes:
  • the LED chip array is disposed on the substrate;
  • the gate driving module is disposed on the substrate and used for providing gate driving signals to the LED chips, the gate driving module includes a plurality of gate driving units;
  • the LED chips are disposed on both sides of the gate driving module, and each of the gate driving units is electrically connected to the corresponding LED chips on both sides.
  • a plurality of the gate driving units and the plurality of the LED chips are arranged in an array;
  • a plurality of the gate driving units are arranged in a row, and each of the gate driving units is electrically connected to the LED chips on both sides arranged in the same row respectively.
  • the number of the LED chips electrically connected to both sides of each gate driving unit is the same.
  • the plurality of the LED chips include a plurality of first LED chips and a plurality of second LED chips arranged in parallel, and the first LED chips are arranged on the side of the gate driving module. On one side, the second LED chip is arranged on the other side of the gate driving module;
  • the plurality of gate driving units include a first gate driving unit and a second gate driving unit arranged in parallel, and the first gate driving unit is arranged at a position of the gate driving module close to the first LED chip.
  • the second gate driving unit is disposed on the side of the gate driving module close to the second LED chip;
  • Each of the first gate driving units is electrically connected to the first LED chips arranged in the same row, and each of the second gate driving units is electrically connected to the second LED chips arranged in the same row.
  • the first gate driving unit and the second gate driving unit are disposed adjacent to each other, and the number of the first LED chips and the second LED chips is the same.
  • the LED light board further includes a plurality of first signal lines and a plurality of second signal lines, the first signal lines and the second signal lines are the same
  • the gate drive unit, the LED chip, the first signal trace and the third Two signal lines form a display module
  • the gate driving unit is connected to the LED chip on one side thereof through the first signal wiring, and the gate driving unit is connected by the second signal wiring on the LED chip on the other side thereof.
  • the extending directions of the first signal wiring and the second signal wiring are coincident.
  • the first signal wiring and the second signal wiring are arranged in a staggered manner.
  • the present application provides a spliced LED lamp panel, which includes at least two LED lamp panels spliced in parallel, the LED lamp panel including:
  • the LED chip array is disposed on the substrate;
  • the gate driving module is disposed on the substrate and used for providing gate driving signals to the LED chips, the gate driving module includes a plurality of gate driving units; the LED chips disposed on both sides of the gate driving module, and each of the gate driving units is electrically connected to the LED chips corresponding to the two sides;
  • a plurality of first signal wirings and a plurality of second signal wirings, the first signal wirings and the second signal wirings are arranged in the same layer, and are arranged in the same layer as part of the film layer of the gate driving unit ;
  • the gate drive unit, the LED chip and the first signal wiring and the second signal wiring connected to each row form a display module;
  • the gate driving unit is connected to the LED chip on one side thereof through the first signal wiring, and the gate driving unit is connected by the second signal wiring on the LED chip on the other side thereof;
  • the ends of the first signal traces and the ends of the second signal traces are staggered.
  • the LED light panel includes a display area and a frame area arranged on both sides of the display area, and a plurality of the LED chips are arranged in the display area;
  • the first signal wiring includes a first part and a second part connected to the first part, the first part is located in the display area, and the second part is located in the frame area;
  • the orthographic projection of the first part on the plane where the substrate is located passes through the orthographic projection of the LED chip on the plane where the substrate is located;
  • the second part includes a first horizontal segment, a vertical segment and a second horizontal segment connected in sequence, the first horizontal segment is connected to the first part, and in the row direction of the LED chips, the second horizontal segment is The segments are located outside the LED chips.
  • the first signal wiring is arranged on the outer side of the LED chips.
  • the LED light board further includes a plurality of first connection wires, and the first connection wires are electrically connected to one of the LED chips in a one-to-one correspondence.
  • the first signal wiring is electrically connected to the LED chip through the first connection wiring;
  • the first connection wiring and the first signal wiring are arranged in different layers.
  • the second signal wiring is located outside the LED chip, and is arranged on a different side from the first signal wiring ;
  • the LED light board further includes a plurality of second connection lines, the second connection lines are electrically connected to the LED chips in a one-to-one correspondence, and the second signal lines pass through the second connection lines is electrically connected to the LED chip.
  • the line width of the first signal wiring and the line width of the second signal wiring are both smaller than those of the adjacent 1/2 of the distance between LED chips.
  • the first signal wiring and the second signal wiring are both high-level signal wirings or low-level signal wirings.
  • the present application also provides a display device, the display device includes a liquid crystal display panel and a backlight module, the backlight module includes an LED lamp panel, and the LED lamp panel includes:
  • the LED chip array is disposed on the substrate;
  • the gate driving module is disposed on the substrate and used for providing gate driving signals to the LED chips, the gate driving module includes a plurality of gate driving units;
  • the LED chips are disposed on both sides of the gate driving module, and each of the gate driving units is electrically connected to the corresponding LED chips on both sides.
  • a plurality of the gate driving units and a plurality of the LED chips are arranged in an array;
  • a plurality of the gate driving units are arranged in a row, and each of the gate driving units is electrically connected to the LED chips on both sides arranged in the same row respectively.
  • the number of the LED chips electrically connected to both sides of each gate driving unit is the same.
  • the LED light board further includes a plurality of first signal lines and a plurality of second signal lines, and the first signal lines and the second signal lines are in the same layer
  • the gate drive unit, the LED chip, and the first signal trace and the second signal line connected to each row of the gate drive unit, the LED chip, and the second The signal traces form a display module
  • the gate driving unit is connected to the LED chip on one side thereof through the first signal wiring, and the gate driving unit is connected by the second signal wiring on the LED chip on the other side thereof.
  • the first signal wiring and the second signal wiring are arranged in a staggered manner.
  • the LED light board provided by the present application is provided with a gate driving module on the substrate, the gate driving module includes a plurality of gate driving units, and the LED chip is arranged on the gate Both sides of the drive module, and each gate drive unit is electrically connected to the corresponding LED chips on both sides, so that when cutting the LED light board, different sizes of light boards can be cut, so as to meet the requirements of different sizes of LED lights. Board splicing requirements.
  • FIG. 1 is a schematic diagram of a first structure of an LED lamp panel provided by a first embodiment of the present application
  • FIG. 2 is a schematic diagram of a second structure of the LED lamp panel provided by the first embodiment of the present application.
  • FIG. 3 is a schematic diagram of a first structure of an LED lamp panel provided by a second embodiment of the present application.
  • FIG. 4 is a schematic diagram of a second structure of an LED light panel provided by a second embodiment of the present application.
  • FIG. 5 is a first structural schematic diagram of a spliced LED light panel provided by an embodiment of the present application.
  • Fig. 6 is the enlarged structural representation of OO' in Fig. 5;
  • FIG. 7 is a second structural schematic diagram of a spliced LED light panel provided by an embodiment of the present application.
  • FIG. 8 is a third structural schematic diagram of a spliced LED light panel provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as “first”, “second” may expressly or implicitly include one or more of said features. In the description of the present application, “plurality” means two or more, unless otherwise expressly and specifically defined.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection, electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • installed should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection, electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • a first feature "on” or “under” a second feature may include direct contact between the first and second features, or may include the first and second features Not directly but through additional features between them.
  • the first feature being “above”, “over” and “above” the second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is level higher than the second feature.
  • the first feature is “below”, “below” and “below” the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature has a lower level than the second feature.
  • the LED light board in this application also includes a driving module, which includes a driving chip, a TCON chip, etc. (not marked in the figure), and the driving module can be bound to the LED light board through a flexible circuit board or a printed circuit board. connection, which will not be repeated here.
  • a driving module which includes a driving chip, a TCON chip, etc. (not marked in the figure)
  • the driving module can be bound to the LED light board through a flexible circuit board or a printed circuit board. connection, which will not be repeated here.
  • FIG. 1 is a schematic diagram of the first structure of the LED lamp panel provided by the first embodiment of the present application
  • FIG. 2 is a schematic diagram of the second structure of the LED lamp panel provided by the first embodiment of the present application.
  • the first embodiment of the present application provides an LED lamp panel 100 , which includes a substrate 10 , a plurality of LED chips 20 and a gate driving module 30 .
  • the array of LED chips 20 is disposed on the substrate 10 .
  • the gate driving module 30 is disposed on the substrate 10 and is used for providing gate driving signals to the LED chips 20 .
  • the gate driving module 30 includes a plurality of gate driving units 301 .
  • the LED chips 20 are disposed on both sides of the gate driving module 30 , and each gate driving unit 301 is electrically connected to the corresponding LED chips 20 on both sides.
  • a gate driving module 30 is provided on the substrate 10 , and the gate driving module 30 includes a plurality of gate driving units 301 , and the LED chips 20 are arranged on the gate
  • the two sides of the pole drive module 30 are connected to each other, and each gate drive unit 301 is electrically connected to the corresponding LED chips 20 on both sides, so that when the LED lamp panel 100 is cut, lamp panels of different sizes can be cut to meet the It meets the splicing requirements of LED light panels of different sizes.
  • the substrate 10 in the embodiment of the present application includes gate scan lines, data lines, thin film transistors, and various insulating film layers (not shown in the figure).
  • the specific structure of the substrate 10 may refer to the prior art. It is not repeated here.
  • the plurality of gate driving units 301 and the plurality of LED chips 20 are arranged in an array.
  • a plurality of gate driving units 301 are arranged in a row.
  • Each gate driving unit 301 is electrically connected to the LED chips 20 on both sides arranged in the same row.
  • each gate driving unit 301 the number of LED chips 20 on both sides of each gate driving unit 301 is the same.
  • the edge of the LED light board is usually used as the starting point for cutting, and according to the required size of the light board, the cutting is carried out to the center of the LED light board.
  • the position of the gate driving unit 301 is cut along the axis of symmetry to meet the splicing requirements of LED light panels of different sizes.
  • the above arrangement can ensure the uniformity of the current on the LED chips 20 on both sides of the gate driving unit 301 on the lamp board after cutting, which is beneficial to improve the uniformity of the brightness of the LED lamp board after splicing.
  • lamp boards of different sizes can be obtained with the gate driving unit 301 as the axis of symmetry. Therefore, according to the required size of the LED light board, different cutting lines can be selected, thereby obtaining light boards with different sizes and better current uniformity, and then after splicing the light boards cut from the LED light board 100 , which improves the uniformity of the overall brightness of the light panel after splicing.
  • each gate driving unit 301 may also be different, and details are not described herein again.
  • the plurality of LED chips 20 include a plurality of first LED chips 201 and a plurality of second LED chips 202 arranged in parallel.
  • the first LED chip 201 is disposed on one side of the gate driving module 30 .
  • the second LED chip 202 is disposed on the other side of the gate driving module 30 .
  • the plurality of gate driving units 301 include a first gate driving unit 3011 and a second gate driving unit 3012 arranged in parallel.
  • the first gate driving unit 3011 is disposed on the side of the gate driving module 30 close to the first LED chip 201 .
  • the second gate driving unit 3012 is disposed on the side of the gate driving module 30 close to the second LED chip 202 .
  • Each of the first gate driving units 3011 is electrically connected to the first LED chips 201 disposed in the same row.
  • Each second gate driving unit 3012 is electrically connected to the second LED chip 202 disposed in the same row.
  • the first gate driving unit 3011 and the second gate driving unit 3012 by setting the first gate driving unit 3011 and the second gate driving unit 3012, and making the first gate driving unit 3011 provide the gate driving signal to the first LED chip 201 on the side of the gate driving module 30,
  • the second gate driving unit 3012 provides a gate driving signal to the second LED chip 202 located on the other side of the gate driving module 30 , so that when cutting the LED lamp panel 100 , lamp panels of different sizes can be cut out, thereby Meet the splicing needs of LED light panels of different sizes.
  • first gate driving unit 3011 and the second gate driving unit 3012 are disposed adjacent to each other, and the number of the first LED chips 201 and the second LED chips 202 is the same.
  • the edge of the LED light board is usually used as the starting point for cutting, and the cutting is carried out toward the center of the LED light board according to the required size of the light board.
  • the above arrangement enables cutting with the position of the gate driving module 30 as the axis of symmetry during cutting, so as to meet the splicing requirements of LED light panels of different sizes.
  • the above arrangement can also avoid the problem of wasting the lamp board caused by asymmetric cutting.
  • the first gate driving unit 3011 and the second gate driving unit 3012 may also be disposed at the edge of the LED lamp panel 100, and the positions of the first gate driving unit 3011 and the second gate driving unit 3012 may be The selection is made according to the actual situation, which is not limited in this application.
  • FIG. 3 is a schematic diagram of the first structure of the LED lamp panel provided by the second embodiment of the present application
  • FIG. 4 is a schematic diagram of the second structure of the LED lamp panel provided by the second embodiment of the present application.
  • the LED lamp panel 100 in the second embodiment of the present application further includes a plurality of first signal wirings 401 and a plurality of second signal wirings 402 .
  • the first signal wiring 401 and the second signal wiring 402 are arranged in the same layer, and are arranged in the same layer as part of the film layer of the gate driving unit 301 .
  • the gate driving unit 301 , the LED chips 20 in each row, and the first signal wiring 401 and the second signal wiring 402 connected to them form a display module 40 .
  • the gate driving unit 301 is connected to the LED chip 20 on one side thereof through the first signal wiring 401 .
  • the gate driving unit 301 is connected to the LED chip 20 on the other side thereof through the second signal wiring 402 .
  • the first signal wiring 401 and the second signal wiring 402 may be provided in the same layer as the metal layer in the gate driving unit 301 , and the metal layer may be a gate metal layer or The source-drain metal layer and other film layers, the specific film layer of the metal layer can be selected according to the actual situation, which is not limited in this application.
  • the number of LED chips 20 on both sides of the gate driving module 30 is the same as an example for description, but it is not limited thereto.
  • the first signal trace 401 and the second signal trace 402 may be both high-level signal traces, low-level signal traces or other signal traces.
  • the types of the first signal trace 401 and the second signal trace 402 are not specifically limited.
  • each display module 40 the extending directions of the first signal traces 401 and the second signal traces 402 are coincident.
  • the above arrangement simplifies the circuit design by arranging the extension directions of the first signal trace 401 and the second signal trace 402 to overlap, and avoids voltage drop caused by the extension of the circuit.
  • the increase of which is beneficial to improve the uniformity of the brightness of the lamp panel.
  • the second structure of the LED lamp panel 100 provided by the second embodiment of the present application as shown in FIG. 4 .
  • the difference between the second structure and the first structure is that in each display module 40 , the first signal wiring 401 and the second signal wiring 402 are arranged in a staggered manner.
  • the first signal traces 401 and the second signal traces 402 are both disposed outside the LED chips 20 .
  • the first signal wiring 401 and the second signal wiring 402 are symmetrical and arranged on opposite sides.
  • the LED light panels are first cut according to the required size of the LED light panels, and then the light panels cut from different LED light panels are spliced to obtain a spliced LED light panel.
  • LED light panel structure In the prior art, when the lamp panels cut from different LED lamp panels are spliced, the corresponding traces of the LED lamp panels to be spliced at the splicing position are prone to signal crosstalk and short-circuits, thus greatly reducing the Affects the luminous brightness at the splicing position. Therefore, in the prior art, spacers are usually filled between the spliced LED light panels to prevent the occurrence of a short circuit.
  • the spacers have a certain thickness and there are operating tolerances in the filling process, the spliced LEDs are There is a certain gap between the light boards, so that the spliced LED light boards form dark lines at the splicing position, which seriously affects the optical quality of the LED light boards at the splicing position.
  • the splicing requirements of LED lamp boards of different sizes are satisfied.
  • the splicing position is The staggered setting between the corresponding traces of the signal traces effectively reduces the risk of crosstalk between the signal traces.
  • the above arrangement can also save the filling of the insulator, which not only avoids the occurrence of dark lines at the splicing position, but also simplifies the process, which is beneficial to saving the process cost.
  • the embodiment of the present application further provides a spliced LED lamp panel 200, which includes at least two LED lamp panels 201 that are spliced and arranged side by side.
  • the LED lamp board 201 includes a substrate 20 , a plurality of LED chips 30 , a gate driving module 40 , a plurality of first signal wires 501 and a plurality of second signal wires 502 .
  • the array of LED chips 30 is disposed on the substrate 20 .
  • the gate driving module 40 is disposed on the substrate 20 and is used for providing gate driving signals to the LED chips 30 .
  • the gate driving module 40 includes a plurality of gate driving units 401 .
  • the LED chips 30 are disposed on both sides of the gate driving module 40 , and each gate driving unit 301 is electrically connected to the corresponding LED chips 20 on both sides.
  • the first signal wiring 501 and the second signal wiring 502 are arranged in the same layer, and are arranged in the same layer as part of the film layer of the gate driving unit 401 .
  • the gate driving units 401 , the LED chips 30 in each row, and the first signal traces 501 and the second signal traces 502 connected to them form a display module 50 .
  • the gate driving unit 401 is connected to the LED chip 30 on one side thereof through the first signal wiring 501 .
  • the gate driving unit 401 is connected to the LED chip 30 on the other side thereof through the second signal wiring 502 .
  • the first signal wiring 501 and the second signal wiring 502 are arranged staggered. Wherein, the end of the first signal trace 501 and the end of the second signal trace 502 are staggered.
  • the end of the first signal wiring 501 and the end of the second signal wiring 502 in the LED light board 201 are arranged in a staggered manner, and then the different LED light boards
  • the problem of signal crosstalk between the first signal trace 501 and the second signal trace 502 at the splicing position can be effectively avoided, thereby reducing the interference between the first signal trace 501 and the second signal trace 502.
  • the risk of short circuit improves the luminous performance of the spliced LED light panel.
  • the end of the first signal wire 501 and the end of the second signal wire 502 in the LED light board 201 are arranged in a staggered manner, thereby effectively avoiding the first signal wire 501 and the second signal wire 502 at the splicing position.
  • the occurrence of the problem of signal crosstalk between them greatly reduces the short-circuit risk of the corresponding signal lines between the spliced LED light panels, thereby improving the luminous performance of the spliced LED light panels.
  • the use of an insulator when the LED light boards are spliced can be directly omitted, and the splicing position can be avoided.
  • the occurrence of the dark pattern further improves the optical taste of the spliced LED light panel at the splicing position.
  • the above arrangement can also simplify the process, which is beneficial to save the process cost.
  • the LED light panel 201 includes a display area 20A and a frame area disposed on both sides of the display area 20A 20B.
  • a plurality of LED chips 30 are arranged in the display area 20A.
  • the first signal trace 501 includes a first portion 501A and a second portion 501B connected to the first portion 501A.
  • the first portion 501A is located in the display area 20A.
  • the second portion 501B is located in the border region 20B.
  • the orthographic projection of the first portion 501A on the plane where the substrate 20 is located passes through the orthographic projection of the LED chip 30 on the plane where the substrate 20 is located.
  • the second portion 501B includes a first horizontal segment 5011, a vertical segment 5012, and a second horizontal segment 5013 connected in sequence.
  • the first horizontal section 5011 is connected to the first portion 501A.
  • the second horizontal segment 5013 is located outside the LED chips 30 .
  • the second signal trace 502 includes a third portion 502A and a fourth portion 502B connected to the third portion 502A.
  • the third portion 502A is located in the display area 20A.
  • the fourth portion 502B is located in the border region 20B.
  • the orthographic projection of the third portion 502A on the plane where the substrate 20 is located passes through the orthographic projection of the LED chip 30 on the plane where the substrate 20 is located.
  • the fourth portion 502B includes a third horizontal segment 5021 , another vertical segment 5022 and a fourth horizontal segment 5023 connected in sequence.
  • the third horizontal segment 5021 is connected to the third portion 502A. In the row direction of the LED chips 30 , the fourth horizontal segment 5023 is located outside the LED chips 30 .
  • the above arrangement makes the part of the first signal trace 501 located in the frame area 20B and the part of the second signal trace 502 located in the frame area 20B staggered.
  • the part of the first signal trace 501 in the 201 at the splicing position and the part of the second signal trace 502 in the other LED light board 201 at the splicing position are arranged in a staggered manner, effectively avoiding the first signal at the splicing position.
  • the phenomenon of signal crosstalk occurs between the line 501 and the second signal line 502, thereby reducing the risk of short circuit of the corresponding signal lines between the spliced LED light panels.
  • the above arrangement can simplify the process by making the first signal wiring 501 and the second signal wiring 502 staggered only in the part located in the frame region 20B, which is beneficial to save the process cost.
  • the orthographic projection of the second signal trace 502 on the plane where the substrate 20 is located passes through the orthographic projection of the LED chip 30 on the plane where the substrate 20 is located, that is, only the first signal trace 501 is located in the frame area 20B position for structural design.
  • This arrangement can still make the first signal wiring 501 and the second signal wiring 502 corresponding to different LED lamp boards staggered during splicing, thereby avoiding the short-circuit problem, which will not be repeated here.
  • the difference between the second structure and the first structure is that in the column direction of the LED chips 30 , the first signal traces 501 are disposed outside the LED chips 30 .
  • the LED light board 201 further includes a plurality of first connection wires 503 .
  • the first connection wires 503 are electrically connected to an LED chip 30 in a one-to-one correspondence.
  • the first signal wiring 501 is electrically connected to the LED chip 30 through the first connecting wiring 503 .
  • the first connection traces 503 and the first signal traces 501 are disposed in different layers.
  • the orthographic projection of the second signal trace 502 on the plane where the substrate 20 is located passes through the orthographic projection of the LED chip 30 on the plane where the substrate 20 is located.
  • the part of the first signal trace 501 located in the frame area 20B directly extends to the splicing position in the horizontal direction, so as to avoid the need for the first signal trace.
  • the 501 is designed to be bent to occupy the space of the frame area 20B, thereby saving the space of the frame area 20B, which is beneficial to realize the narrow frame design of the LED light panel 201 .
  • this arrangement shortens the distance between the LED chips 30 adjacent to the frame area 20B between the different LED light panels 201 , thereby helping to improve the luminous brightness at the splicing position and reducing the frame of the spliced LED light panels 200 .
  • the difference between the brightness of the area 20B and the brightness difference of the display area 20A greatly improves the overall brightness uniformity of the spliced LED light panel.
  • the space between adjacent LED chips is saved, and the first signal wiring is
  • the line width of the first signal wiring 501 can be appropriately increased, which is beneficial to reduce the voltage drop on the first signal wiring 501, thereby further improving the overall brightness uniformity of the spliced LED light panel.
  • the difference between the third structure and the second structure is that in the column direction of the LED chips 30 , the second structure is different from the second structure.
  • the signal wiring 502 is located outside the LED chip 30 and is disposed on the opposite side of the first signal wiring 501 .
  • the LED light board further includes a plurality of second connection wires 504 .
  • the second connection wires 504 are electrically connected to an LED chip 30 in a one-to-one correspondence.
  • the second signal trace 502 is electrically connected to the LED chip 30 through the second connection trace 504 .
  • the line width of the first signal wiring 501 and the line width of the second signal wiring 502 are both smaller than those between adjacent LED chips 30 . half the distance.
  • the corresponding signal traces at the splicing positions may be shifted during the alignment process.
  • the above arrangement makes the first signal trace 501 and the second signal trace 502 corresponding to the splicing position have a certain offset distance when aligning, which is beneficial to reduce the difficulty of splicing and assembling different LED light panels 201 .
  • the second connection wiring 504 and the second signal wiring 502 are arranged in different layers, so that when the wiring design of the second signal wiring 502 is performed, the first On the premise that the first signal trace 501 and the second signal trace 502 are arranged in a staggered manner, the line width of the second signal trace 502 can be appropriately increased, which is beneficial to reduce the voltage drop on the second signal trace 502, thereby further reducing the voltage drop on the second signal trace 502. Improve the uniformity of the overall brightness of the spliced LED light panel.
  • the substrate 20 in the embodiment of the present application includes gate scan lines, data lines, thin film transistors, and various insulating film layers (not shown in the figure).
  • the specific structure of the substrate 20 may refer to the prior art. It is not repeated here.
  • via holes may be provided on the insulating layer in the substrate 20 to realize the connection between the first signal trace 501 and the plurality of first connection traces 503, and the second signal trace 502 and the plurality of connection traces.
  • the specific film layer structure can be selected according to the actual situation, which is not limited in this application.
  • the LED light board provided by the present application is provided with a gate driving module on the substrate, the gate driving module includes a plurality of gate driving units, and the LED chip is arranged on the gate Both sides of the drive module, and each gate drive unit is electrically connected to the corresponding LED chips on both sides, so that when cutting the LED light board, different sizes of light boards can be cut, so as to meet the requirements of different sizes of LED lights. Board splicing requirements.
  • FIG. 9 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • An embodiment of the present application further provides a display device 1000, the display device 1000 includes a liquid crystal display panel 1, an optical film layer 2 and a backlight module 3 arranged in sequence, and the backlight module 3 may include the LED lamp described in any of the above embodiments
  • the specific structure of the board 100 or the spliced LED light board 200, and the specific structure of the LED light board 100 or the spliced LED light board 200 can be referred to the descriptions of the above embodiments, which will not be repeated here.
  • the liquid crystal display panel 1 includes a lower polarizer 11 , an array substrate 12 , a liquid crystal 13 , a color filter substrate 14 , an upper polarizer 15 and a cover plate 16 sequentially arranged on the optical film layer 2 .
  • the optical film layer 2 includes a fluorescent film 21 , a diffusion film 22 and a shell extension film 23 which are sequentially arranged on the backlight module 3 .
  • the optical film layer 2 may also include other film layer structures, and this embodiment should not be construed as a limitation on the present application.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种LED灯板(201)、拼接式LED灯板(200)及显示装置(1000)，LED灯板(201)包括衬底(20)、多个LED芯片(30)以及栅极驱动模块(40)；LED芯片(30)阵列设置于衬底(20)上；栅极驱动模块(40)设置于衬底(20)上，并用于向LED芯片(30)提供栅极驱动信号，栅极驱动模块(40)包括多个栅极驱动单元(401)；LED芯片(30)设置于栅极驱动模块(40)的两侧，且每个栅极驱动单元(401)电性连接于两侧对应的LED芯片(30)。

Description

LED灯板、拼接式LED灯板及显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种LED灯板、拼接式LED灯板及显示装置。
 背景技术
Mini LED（Mini Light Emitting Diode, 迷你发光二极管）背光模组因其高亮度、超窄边框、异形以及能够实现局部分区设计等优点而受到越来越多的关注。通常，越高的分区一般意味着更好的显示效果，但目前Mini LED的驱动方式一般为被动式驱动，当实现更多分区的时候，通常需要更多驱动芯片，这样会带来成本的大幅度上升，且不利于实现窄边框及集成化显示。
因此，各大厂家均在开发主动式驱动的Mini LED，也即，通过在玻璃基板上设计驱动器件来驱动Mini LED，利用薄膜晶体管实现主动式驱动，进而大幅度减少驱动芯片的数量，降低驱动成本，以此实现更多的分区及更好的显示效果。
 技术问题
然而，由于中大尺寸的Mini LED背板通常采用拼接方式形成，目前的主动式Mini LED驱动结构设计无法满足自由拼接的需求，因此，如何实现Mini LED背板的自由拼接成为亟待解决的技术问题。
 技术解决方案
本申请提供一种LED灯板、拼接式LED灯板及显示装置，以解决目前的主动式Mini LED驱动结构设计无法满足自由拼接的需求的技术问题。
本申请提供一种LED灯板，其包括：
衬底；
多个LED芯片，所述LED芯片阵列设置于所述衬底上；以及
栅极驱动模块，所述栅极驱动模块设置于所述衬底上，并用于向所述LED芯片提供栅极驱动信号，所述栅极驱动模块包括多个栅极驱动单元；
所述LED芯片设置于所述栅极驱动模块的两侧，且每个所述栅极驱动单元电性连接于两侧对应的所述LED芯片。
在本申请所述的LED灯板中，多个所述栅极驱动单元与多个所述LED芯片呈阵列排布；
多个所述栅极驱动单元排成一列，每一所述栅极驱动单元分别电性连接于与其同行设置的两侧所述LED芯片。
在本申请所述的LED灯板中，每一所述栅极驱动单元两侧并与其电性连接的所述LED芯片的数量相同。
在本申请所述的LED灯板中，多个所述LED芯片包括并列设置的多个第一LED芯片和多个第二LED芯片，所述第一LED芯片设置在所述栅极驱动模块的一侧，所述第二LED芯片设置在所述栅极驱动模块的另一侧；
多个所述栅极驱动单元包括并列设置的第一栅极驱动单元和第二栅极驱动单元，所述第一栅极驱动单元设置在所述栅极驱动模块靠近所述第一LED芯片的一侧，所述第二栅极驱动单元设置在所述栅极驱动模块靠近所述第二LED芯片的一侧；
每一所述第一栅极驱动单元电性连接于与其同行设置的所述第一LED芯片，每一所述第二栅极驱动单元电性连接于与其同行设置的所述第二LED芯片。
在本申请所述的LED灯板中，所述第一栅极驱动单元和所述第二栅极驱动单元相邻设置，且所述第一LED芯片和所述第二LED芯片的数量相同。
在本申请所述的LED灯板中，所述LED灯板还包括多条第一信号走线和多条第二信号走线，所述第一信号走线和所述第二信号走线同层设置，且与所述栅极驱动单元的部分膜层同层设置；每行的所述栅极驱动单元、所述LED芯片以及连接于二者的所述第一信号走线和所述第二信号走线形成一显示模块；
在每一所述显示模块中，所述栅极驱动单元通过所述第一信号走线连接于位于其一侧的所述LED芯片，所述栅极驱动单元通过所述第二信号走线连接于位于其另一侧的所述LED芯片。
在本申请所述的LED灯板中，在每一所述显示模块中，所述第一信号走线和所述第二信号走线的延伸方向重合。
在本申请所述的LED灯板中，在每一所述显示模块中，所述第一信号走线和所述第二信号走线相错设置。
本申请提供一种拼接式LED灯板，其包括至少并列拼接设置的两个LED灯板，所述LED灯板包括：
衬底；
多个LED芯片，所述LED芯片阵列设置于所述衬底上；
栅极驱动模块，所述栅极驱动模块设置于所述衬底上，并用于向所述LED芯片提供栅极驱动信号，所述栅极驱动模块包括多个栅极驱动单元；所述LED芯片设置于所述栅极驱动模块的两侧，且每个所述栅极驱动单元电性连接于两侧对应的所述LED芯片；
多条第一信号走线和多条第二信号走线，所述第一信号走线和所述第二信号走线同层设置，且与所述栅极驱动单元的部分膜层同层设置；每行的所述栅极驱动单元、所述LED芯片以及连接于二者的所述第一信号走线和所述第二信号走线形成一显示模块；
在每一所述显示模块中，所述栅极驱动单元通过所述第一信号走线连接于位于其一侧的所述LED芯片，所述栅极驱动单元通过所述第二信号走线连接于位于其另一侧的所述LED芯片；
所述第一信号走线的末端和所述第二信号走线的末端相错设置。
在本申请所述的拼接式LED灯板中，所述LED灯板包括显示区和设置在所述显示区两侧的边框区，多个所述LED芯片设置在所述显示区；
所述第一信号走线包括第一部分和连接于所述第一部分的第二部分，所述第一部分位于所述显示区，所述第二部分位于所述边框区；
在所述显示模块中，所述第一部分于所述衬底所在平面的正投影贯穿所述LED芯片于所述衬底所在平面的正投影；
所述第二部分包括依次连接的第一水平段、竖直段和第二水平段，所述第一水平段连接于所述第一部分，在所述LED芯片的行方向上，所述第二水平段位于所述LED芯片的外侧。
在本申请所述的拼接式LED灯板中，在所述LED芯片的列方向上，所述第一信号走线设置于所述LED芯片的外侧。
在本申请所述的拼接式LED灯板中，所述LED灯板还包括多条第一连接走线，所述第一连接走线一一对应电性连接于一所述LED芯片，所述第一信号走线通过所述第一连接走线与所述LED芯片电性连接；
所述第一连接走线与所述第一信号走线异层设置。
在本申请所述的拼接式LED灯板中，在所述LED芯片的列方向上，所述第二信号走线位于所述LED芯片的外侧，且与所述第一信号走线异侧设置；
所述LED灯板还包括多条第二连接走线，所述第二连接走线一一对应电性连接于一所述LED芯片，所述第二信号走线通过所述第二连接走线与所述LED芯片电性连接。
在本申请所述的拼接式LED灯板中，在所述LED芯片的列方向上，所述第一信号走线的线宽和所述第二信号走线的线宽均小于相邻所述LED芯片之间距离的二分之一。
在本申请所述的拼接式LED灯板中，所述第一信号走线和所述第二信号走线均为高电平信号走线或低电平信号走线。
本申请还提供一种显示装置，所述显示装置包括液晶显示面板和背光模组，所述背光模组包括LED灯板，所述LED灯板包括：
衬底；
多个LED芯片，所述LED芯片阵列设置于所述衬底上；以及
栅极驱动模块，所述栅极驱动模块设置于所述衬底上，并用于向所述LED芯片提供栅极驱动信号，所述栅极驱动模块包括多个栅极驱动单元；
所述LED芯片设置于所述栅极驱动模块的两侧，且每个所述栅极驱动单元电性连接于两侧对应的所述LED芯片。
在本申请所述的显示装置中，多个所述栅极驱动单元与多个所述LED芯片呈阵列排布；
多个所述栅极驱动单元排成一列，每一所述栅极驱动单元分别电性连接于与其同行设置的两侧所述LED芯片。
在本申请所述的显示装置中，每一所述栅极驱动单元两侧并与其电性连接的所述LED芯片的数量相同。
在本申请所述的显示装置中，所述LED灯板还包括多条第一信号走线和多条第二信号走线，所述第一信号走线和所述第二信号走线同层设置，且与所述栅极驱动单元的部分膜层同层设置；每行的所述栅极驱动单元、所述LED芯片以及连接于二者的所述第一信号走线和所述第二信号走线形成一显示模块；
在每一所述显示模块中，所述栅极驱动单元通过所述第一信号走线连接于位于其一侧的所述LED芯片，所述栅极驱动单元通过所述第二信号走线连接于位于其另一侧的所述LED芯片。
在本申请所述的显示装置中，在每一所述显示模块中，所述第一信号走线和所述第二信号走线相错设置。
 有益效果
相较于现有技术中的LED灯板，本申请提供的LED灯板通过在衬底上设置一栅极驱动模块，该栅极驱动模块包括多个栅极驱动单元，LED芯片设置于栅极驱动模块的两侧，且每个栅极驱动单元电性连接于两侧对应的LED芯片，进而在对LED灯板进行切割时，可以切割出不同尺寸的灯板，从而满足了不同尺寸LED灯板的拼接需求。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请第一实施例提供的LED灯板的第一结构示意图；
图2是本申请第一实施例提供的LED灯板的第二结构示意图；
图3是本申请第二实施例提供的LED灯板的第一结构示意图；
图4是本申请第二实施例提供的LED灯板的第二结构示意图；
图5是本申请实施例提供的拼接式LED灯板的第一结构示意图；
图6是图5中OO’的放大结构示意图；
图7是本申请实施例提供的拼接式LED灯板的第二结构示意图；
图8是本申请实施例提供的拼接式LED灯板的第三结构示意图；
图9是本申请实施例提供的显示装置的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
需要说明的是，本申请LED灯板中LED芯片的数量仅为示意，用以方便描述本申请以下各实施例，但不能理解为对本申请的限制。
需要说明的是，本申请中的LED灯板还包括驱动模块，驱动模块包括驱动芯片、TCON芯片等（图中未标识），驱动模块可以通过柔性电路板或印刷电路板与LED灯板绑定连接，在此不再赘述。
请参阅图1和图2，图1是本申请第一实施例提供的LED灯板的第一结构示意图；图2是本申请第一实施例提供的LED灯板的第二结构示意图。
本申请第一实施例提供一种LED灯板100，其包括衬底10、多个LED芯片20和栅极驱动模块30。LED芯片20阵列设置于衬底10上。栅极驱动模块30设置于衬底10上，并用于向LED芯片20提供栅极驱动信号。栅极驱动模块30包括多个栅极驱动单元301。其中，LED芯片20设置于栅极驱动模块30的两侧，且每个栅极驱动单元301电性连接于两侧对应的LED芯片20。
由此，本申请第一实施例提供的LED灯板100通过在衬底10上设置一栅极驱动模块30，该栅极驱动模块30包括多个栅极驱动单元301，LED芯片20设置于栅极驱动模块30的两侧，且每个栅极驱动单元301电性连接于两侧对应的LED芯片20，进而在对LED灯板100进行切割时，可以切割出不同尺寸的灯板，从而满足了不同尺寸LED灯板的拼接需求。
需要说明的是，本申请实施例中的衬底10包括栅极扫描线、数据线、薄膜晶体管以及各绝缘膜层（图中未示出），衬底10的具体结构可以参照现有技术，在此不再赘述。
在本申请第一实施例提供的LED灯板100的第一种结构中，如图1所示。多个栅极驱动单元301与多个LED芯片20呈阵列排布。多个栅极驱动单元301排成一列。每一栅极驱动单元301分别电性连接于与其同行设置的两侧LED芯片20。
进一步的，每一栅极驱动单元301两侧的LED芯片20的数量相同。
可以理解的是，在LED灯板的切割过程中，通常以LED灯板的边缘为切割起点，并根据所需灯板的尺寸向LED灯板的中心进行切割，上述设置使得在切割时能够以栅极驱动单元301所在位置为对称轴进行切割，以满足不同尺寸LED灯板的拼接需求。
进一步的，在采用对称式切割而得到的灯板中，由于每一栅极驱动单元301到与其同行设置的两侧LED芯片20的距离相等，进而能够避免不对称切割时造成的灯板浪费问题。此外，上述设置能够保证切割后灯板上栅极驱动单元301两侧的LED芯片20上电流的均一性，有利于提高LED灯板拼接后亮度的均一性。
具体的，如图1所示，当在第一切割线101处或第二切割线102处进行切割时，可以得到以栅极驱动单元301为对称轴的不同尺寸的灯板。因此，根据所需LED灯板的尺寸，可以选择不同的切割线，由此得到不同尺寸且电流均一性较佳的灯板，进而在将从LED灯板100上切割出的灯板进行拼接后，提高了拼接后灯板整体亮度的均一性。
在一些实施例中，每一栅极驱动单元301两侧的LED芯片20的数量也可以不同，在此不再赘述。
另外，在本申请第一实施例提供的LED灯板100的第二种结构中，如图2所示。该第二种结构与第一种结构的不同之处在于：多个LED芯片20包括并列设置的多个第一LED芯片201和多个第二LED芯片202。第一LED芯片201设置在栅极驱动模块30的一侧。第二LED芯片202设置在栅极驱动模块30的另一侧。多个栅极驱动单元301包括并列设置的第一栅极驱动单元3011和第二栅极驱动单元3012。第一栅极驱动单元3011设置在栅极驱动模块30靠近第一LED芯片201的一侧。第二栅极驱动单元3012设置在栅极驱动模块30靠近第二LED芯片202的一侧。每一第一栅极驱动单元3011电性连接于与其同行设置的第一LED芯片201。每一第二栅极驱动单元3012电性连接于与其同行设置的第二LED芯片202。
上述设置通过设置第一栅极驱动单元3011和第二栅极驱动单元3012，并使第一栅极驱动单元3011对位于栅极驱动模块30一侧的第一LED芯片201提供栅极驱动信号，第二栅极驱动单元3012对位于栅极驱动模块30另一侧的第二LED芯片202提供栅极驱动信号，进而在对LED灯板100进行切割时，能够切割出不同尺寸的灯板，从而满足不同尺寸LED灯板的拼接需求。
进一步的，第一栅极驱动单元3011和第二栅极驱动单元3012相邻设置，且第一LED芯片201和第二LED芯片202的数量相同。
可以理解的是，在LED灯板的切割过程中，通常以LED灯板的边缘为切割起点，并根据所需灯板的尺寸向LED灯板的中心进行切割。上述设置使得在切割时能够以栅极驱动模块30所在位置为对称轴进行切割，以满足不同尺寸LED灯板的拼接需求。此外，上述设置还能够避免不对称切割时造成的灯板浪费问题。
在一些实施例中，第一栅极驱动单元3011和第二栅极驱动单元3012还可以设置在LED灯板100的边缘，第一栅极驱动单元3011和第二栅极驱动单元3012的位置可以根据实际情况进行选择，本申请对此不作限定。
请参阅图3和图4，图3是本申请第二实施例提供的LED灯板的第一结构示意图；图4是本申请第二实施例提供的LED灯板的第二结构示意图。
在第一实施例的结构的基础上，本申请第二实施例中的LED灯板100还包括多条第一信号走线401和多条第二信号走线402。第一信号走线401和第二信号走线402同层设置，且与栅极驱动单元301的部分膜层同层设置。每行的栅极驱动单元301、LED芯片20以及连接于二者的第一信号走线401和第二信号走线402形成一显示模块40。在每一显示模块40中，栅极驱动单元301通过第一信号走线401连接于位于其一侧的LED芯片20。栅极驱动单元301通过第二信号走线402连接于位于其另一侧的LED芯片20。
具体的，在本申请第二实施例中，第一信号走线401和第二信号走线402可以与栅极驱动单元301中的金属层同层设置，该金属层可以为栅极金属层或源漏金属层等膜层，金属层的具体膜层可以根据实际情况进行选择，本申请对此不作限定。
需要说明的是，本申请第二实施例仅以栅极驱动模块30两侧的LED芯片20数量相同为例进行说明，但并不限于此。
另外，在本申请第二实施例中，第一信号走线401和第二信号走线402可以均为高电平信号走线、低电平信号走线或其他信号走线，本申请对第一信号走线401及第二信号走线402的类型均不作具体限定。
具体的，在本申请第二实施例提供的LED灯板100的第一种结构中，如图3所示。在每一显示模块40中，第一信号走线401和第二信号走线402的延伸方向重合。
上述设置在满足不同尺寸LED灯板拼接需求的同时，通过将第一信号走线401和第二信号走线402的延伸方向重合设置，简化了线路设计，避免随着线路的延长而造成压降的增加，进而有利于提高灯板亮度的均匀性。
另外，在本申请第二实施例提供的LED灯板100的第二种结构中，如图4所示。该第二种结构与第一种结构的不同之处在于：在每一显示模块40中，第一信号走线401和第二信号走线402相错设置。
具体的，在LED芯片20的列方向上，第一信号走线401和第二信号走线402均设置于LED芯片20的外侧。其中，第一信号走线401和第二信号走线402对称且异侧设置。
可以理解的是，对于拼接式的LED灯板，首先根据所需要的LED灯板的尺寸对LED灯板进行切割，然后将从不同LED灯板中切割出的灯板进行拼接，以得到拼接式的LED灯板结构。在现有技术中，由于将从不同LED灯板中切割出的灯板进行拼接时，待拼接的LED灯板位于拼接位置处的对应走线之间易产生信号串扰而发生短接，进而大大影响了拼接位置处的发光亮度。因而，在现有技术中，通常在拼接的LED灯板之间填充隔绝物来防止短路现象的发生，然而，由于隔绝物具有一定的厚度，且在填充过程中存在作业公差，导致拼接的LED灯板之间存在一定的间隙，从而使得拼接后的LED灯板在拼接位置处形成暗纹，进而严重影响了LED灯板在拼接位置处的光学品味。
上述设置通过将第一信号走线401和第二信号走线402对称且异侧设置，一方面，满足了不同尺寸LED灯板的拼接需求。另一方面，由于将第一信号走线401和第二信号走线402设置在LED芯片20的两侧，进而在将从LED灯板100上切割出的灯板进行拼接时，使得拼接位置处的对应走线之间错开设置，有效降低了信号走线之间的串扰风险。此外，上述设置还可以省去隔绝物的填充，不仅避免了拼接位置处暗纹现象的产生，而且还简化了工艺，有利于节约工艺成本。
请参阅图5至图8。本申请实施例还提供一种拼接式LED灯板200，其包括至少并列拼接设置的两个LED灯板201。LED灯板201包括衬底20、多个LED芯片30、栅极驱动模块40、多条第一信号走线501和多条第二信号走线502。LED芯片30阵列设置于衬底20上。栅极驱动模块40设置于衬底20上，并用于向LED芯片30提供栅极驱动信号。栅极驱动模块40包括多个栅极驱动单元401。LED芯片30设置于栅极驱动模块40的两侧，且每个栅极驱动单元301电性连接于两侧对应的LED芯片20。第一信号走线501和第二信号走线502同层设置，且与栅极驱动单元401的部分膜层同层设置。每行的栅极驱动单元401、LED芯片30以及连接于二者的第一信号走线501和第二信号走线502形成一显示模块50。在每一显示模块50中，栅极驱动单元401通过第一信号走线501连接于位于其一侧的LED芯片30。栅极驱动单元401通过第二信号走线502连接于位于其另一侧的LED芯片30。在每一显示模块50中，第一信号走线501和第二信号走线502相错设置。其中，第一信号走线501的末端和第二信号走线502的末端相错设置。
由此，本申请实施例提供的拼接式LED灯板200通过使LED灯板201中第一信号走线501的末端和第二信号走线502的末端相错设置，进而在将不同LED灯板201进行拼接时，能够有效避免拼接位置处第一信号走线501和第二信号走线502之间发生信号串扰问题，从而降低了第一信号走线501和第二信号走线502之间的短接风险，提高了拼接式LED灯板的发光性能。
可以理解的是，在现有技术中，将不同LED灯板进行拼接时，待拼接的LED灯板位于拼接位置处的对应走线之间易产生信号串扰而发生短接，进而降低了拼接式LED灯板的发光性能。因而，通常在待拼接的LED灯板之间填充隔绝物来防止短路现象的发生，但由于隔绝物具有一定的厚度，且在填充过程中存在作业公差，导致拼接的LED灯板之间存在一定的间隙，从而使得LED灯板在拼接位置处产生暗纹，大大降低了拼接式LED灯板在拼接位置处的光学品味。
本实施例通过使LED灯板201中第一信号走线501的末端和第二信号走线502的末端相错设置，有效避免了拼接位置处第一信号走线501和第二信号走线502之间信号串扰问题的发生，大大降低了拼接式LED灯板之间对应信号走线的短接风险，从而提高了拼接式LED灯板的发光性能。
进一步的，本实施例通过LED灯板201中第一信号走线501和第二信号走线502的相错设置，还可以直接省去LED灯板拼接时隔绝物的使用，避免了拼接位置处暗纹现象的发生，进一步提高了拼接式LED灯板在拼接位置处的光学品味。此外，上述设置还可以简化工艺，有利于节约工艺成本。
需要说明的是，本申请实施例仅以栅极驱动模块40两侧的LED芯片30数量相同为例进行说明，但并不限于此。
具体的，在本申请实施例提供的拼接式LED灯板的第一种结构中，如图5和图6所示，LED灯板201包括显示区20A和设置在显示区20A两侧的边框区20B。多个LED芯片30设置在显示区20A。第一信号走线501包括第一部分501A和连接于第一部分501A的第二部分501B。第一部分501A位于显示区20A。第二部分501B位于边框区20B。在显示模块50中，第一部分501A于衬底20所在平面的正投影贯穿LED芯片30于衬底20所在平面的正投影。第二部分501B包括依次连接的第一水平段5011、竖直段5012和第二水平段5013。第一水平段5011连接于第一部分501A。在LED芯片30的行方向上，第二水平段5013位于LED芯片30的外侧。
在本实施例的第一结构中，第二信号走线502包括第三部分502A和连接于第三部分502A的第四部分502B。第三部分502A位于显示区20A。第四部分502B位于边框区20B。在显示模块50中，第三部分502A于衬底20所在平面的正投影贯穿LED芯片30于衬底20所在平面的正投影。第四部分502B包括依次连接的第三水平段5021、另一竖直段5022和第四水平段5023。第三水平段5021连接于第三部分502A。在LED芯片30的行方向上，第四水平段5023位于LED芯片30的外侧。
上述设置通过使第一信号走线501位于边框区20B的部分和第二信号走线502位于边框区20B的部分相错设置，进而在对不同LED灯板201进行拼接时，使得一LED灯板201中的第一信号走线501位于拼接位置处的部分和另一LED灯板201中的第二信号走线502位于拼接位置处的部分相错设置，有效避免了拼接位置处第一信号走线501和第二信号走线502之间发生信号串扰现象，从而降低了拼接式LED灯板之间对应信号走线的短接风险。此外，上述设置通过使第一信号走线501和第二信号走线502仅在位于边框区20B的部分相错设置，还可以简化工艺，有利于节约工艺成本。
在一些实施例中，第二信号走线502于衬底20所在平面的正投影贯穿LED芯片30于衬底20所在平面的正投影，也即，仅对第一信号走线501位于边框区20B的位置进行结构上的设计。该设置仍然能够使得不同LED灯板在拼接时对应的第一信号走线501和第二信号走线502之间相错开来，进而避免发生短接问题，在此不再赘述。
在本申请实施例提供的拼接式LED灯板的第二种结构中，如图7所示。该第二种结构与第一种结构的不同之处在于：在LED芯片30的列方向上，第一信号走线501设置于LED芯片30的外侧。LED灯板201还包括多条第一连接走线503。第一连接走线503一一对应电性连接于一LED芯片30。第一信号走线501通过第一连接走线503与LED芯片30电性连接。第一连接走线503与第一信号走线501异层设置。第二信号走线502于衬底20所在平面的正投影贯穿LED芯片30于衬底20所在平面的正投影。
上述设置通过将第一信号走线501设置在LED芯片30的外侧，使得第一信号走线501位于边框区20B的部分直接沿水平方向延伸至拼接位置处，避免因需对第一信号走线501做弯折设计而占用边框区20B的空间，进而可以节省边框区20B的空间，有利于实现LED灯板201的窄边框设计。进一步的，该设置缩短了不同LED灯板201之间与边框区20B相邻的LED芯片30之间的距离，进而有利于提高拼接位置处的发光亮度，减小了拼接式LED灯板200边框区20B的亮度与显示区20A亮度差异之间的差异，从而大大提高了拼接式LED灯板整体亮度的均匀性。
另外，在本申请实施例的第二种结构中，通过将第一连接走线503与第一信号走线501异层设置，节省了相邻LED芯片之间的空间，进而在对第一信号走线501进行布线设计时，可以适当增加第一信号走线501的线宽，有利于减小第一信号走线501上的压降，从而可以进一步提高拼接式LED灯板整体亮度的均匀性。
在本申请实施例提供的拼接式LED灯板的第三种结构中，如图8所示，该第三结构与第二结构的不同之处在于：在LED芯片30的列方向上，第二信号走线502位于LED芯片30的外侧，且与第一信号走线501异侧设置。LED灯板还包括多条第二连接走线504。第二连接走线504一一对应电性连接于一LED芯片30。第二信号走线502通过第二连接走线504与LED芯片30电性连接。
具体的，在本实施例的第三结构中，在LED芯片30的列方向上，第一信号走线501的线宽和第二信号走线502的线宽均小于相邻LED芯片30之间距离的二分之一。
可以理解的是，不同LED灯板201在对位拼接时，拼接位置处对应的信号走线在对位过程中可能会发生偏移。上述设置使得拼接位置处对应的第一信号走线501和第二信号走线502在对位时存在一定的偏移距离，进而有利于降低不同LED灯板201拼接式的对位组装难度。
进一步的，在本申请实施例的第三结构中，第二连接走线504与第二信号走线502异层设置，该设置使得在对第二信号走线502进行布线设计时，在保证第一信号走线501和第二信号走线502相错设置的前提下，可以适当增加第二信号走线502的线宽，有利于减小第二信号走线502上的压降，从而可以进一步提高拼接式LED灯板整体亮度的均匀性。
需要说明的是，本申请实施例中的衬底20包括栅极扫描线、数据线、薄膜晶体管以及各绝缘膜层（图中未示出），衬底20的具体结构可以参照现有技术，在此不再赘述。
另外，在实际工艺中，可以通过在衬底20中的绝缘层上设置过孔来实现第一信号走线501和多条第一连接走线503之间、以及第二信号走线502和多条第二连接走线504之间的电性连接，具体膜层结构可以根据实际情况进行选择，本申请对此不作限定。
相较于现有技术中的LED灯板，本申请提供的LED灯板通过在衬底上设置一栅极驱动模块，该栅极驱动模块包括多个栅极驱动单元，LED芯片设置于栅极驱动模块的两侧，且每个栅极驱动单元电性连接于两侧对应的LED芯片，进而在对LED灯板进行切割时，可以切割出不同尺寸的灯板，从而满足了不同尺寸LED灯板的拼接需求。
请参阅图9，图9为本申请实施例提供的显示装置的结构示意图。
本申请实施例还提供一种显示装置1000，显示装置1000包括依次设置的液晶显示面板1、光学膜层2和背光模组3，背光模组3可以包括上述任一实施例所述的LED灯板100或拼接式LED灯板200，LED灯板100或者拼接式LED灯板200的具体结构可以参照上述实施例的描述，在此不再赘述。
其中，液晶显示面板1包括依次设置在光学膜层2上的下偏光片11、阵列基板12、液晶13、彩膜基板14、上偏光片15以及盖板16。
光学膜层2包括依次设置在背光模组3上的荧光膜21、扩散膜22和增壳膜23。在一些实施例中，光学膜层2还可以包括其他膜层结构，本实施例不能理解为对本申请的限制。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种LED灯板，其包括：
    衬底；
    多个LED芯片，所述LED芯片阵列设置于所述衬底上；以及
    栅极驱动模块，所述栅极驱动模块设置于所述衬底上，并用于向所述LED芯片提供栅极驱动信号，所述栅极驱动模块包括多个栅极驱动单元；
    所述LED芯片设置于所述栅极驱动模块的两侧，且每个所述栅极驱动单元电性连接于两侧对应的所述LED芯片。
  2. 根据权利要求1所述的LED灯板，其中，多个所述栅极驱动单元与多个所述LED芯片呈阵列排布；
    多个所述栅极驱动单元排成一列，每一所述栅极驱动单元分别电性连接于与其同行设置的两侧所述LED芯片。
  3. 根据权利要求2所述的LED灯板，其中，每一所述栅极驱动单元两侧并与其电性连接的所述LED芯片的数量相同。
  4. 根据权利要求1所述的LED灯板，其中，多个所述LED芯片包括并列设置的多个第一LED芯片和多个第二LED芯片，所述第一LED芯片设置在所述栅极驱动模块的一侧，所述第二LED芯片设置在所述栅极驱动模块的另一侧；
    多个所述栅极驱动单元包括并列设置的第一栅极驱动单元和第二栅极驱动单元，所述第一栅极驱动单元设置在所述栅极驱动模块靠近所述第一LED芯片的一侧，所述第二栅极驱动单元设置在所述栅极驱动模块靠近所述第二LED芯片的一侧；
    每一所述第一栅极驱动单元电性连接于与其同行设置的所述第一LED芯片，每一所述第二栅极驱动单元电性连接于与其同行设置的所述第二LED芯片。
  5. 根据权利要求4所述的LED灯板，其中，所述第一栅极驱动单元和所述第二栅极驱动单元相邻设置，且所述第一LED芯片和所述第二LED芯片的数量相同。
  6. 根据权利要求1所述的LED灯板，其中，所述LED灯板还包括多条第一信号走线和多条第二信号走线，所述第一信号走线和所述第二信号走线同层设置，且与所述栅极驱动单元的部分膜层同层设置；每行的所述栅极驱动单元、所述LED芯片以及连接于二者的所述第一信号走线和所述第二信号走线形成一显示模块；
    在每一所述显示模块中，所述栅极驱动单元通过所述第一信号走线连接于位于其一侧的所述LED芯片，所述栅极驱动单元通过所述第二信号走线连接于位于其另一侧的所述LED芯片。
  7. 根据权利要求6所述的LED灯板，其中，在每一所述显示模块中，所述第一信号走线和所述第二信号走线的延伸方向重合。
  8. 根据权利要求6所述的LED灯板，其中，在每一所述显示模块中，所述第一信号走线和所述第二信号走线相错设置。
  9. 一种拼接式LED灯板，其包括至少并列拼接设置的两个LED灯板，其中，所述LED灯板包括；
    衬底；
    多个LED芯片，所述LED芯片阵列设置于所述衬底上；
    栅极驱动模块，所述栅极驱动模块设置于所述衬底上，并用于向所述LED芯片提供栅极驱动信号，所述栅极驱动模块包括多个栅极驱动单元；所述LED芯片设置于所述栅极驱动模块的两侧，且每个所述栅极驱动单元电性连接于两侧对应的所述LED芯片；以及
    多条第一信号走线和多条第二信号走线，所述第一信号走线和所述第二信号走线同层设置，且与所述栅极驱动单元的部分膜层同层设置；每行的所述栅极驱动单元、所述LED芯片以及连接于二者的所述第一信号走线和所述第二信号走线形成一显示模块；
    在每一所述显示模块中，所述栅极驱动单元通过所述第一信号走线连接于位于其一侧的所述LED芯片，所述栅极驱动单元通过所述第二信号走线连接于位于其另一侧的所述LED芯片；
    所述第一信号走线的末端和所述第二信号走线的末端相错设置。
  10. 根据权利要求9所述的拼接式LED灯板，其中，所述LED灯板包括显示区和设置在所述显示区两侧的边框区，多个所述LED芯片设置在所述显示区；
    所述第一信号走线包括第一部分和连接于所述第一部分的第二部分，所述第一部分位于所述显示区，所述第二部分位于所述边框区；
    在所述显示模块中，所述第一部分于所述衬底所在平面的正投影贯穿所述LED芯片于所述衬底所在平面的正投影；
    所述第二部分包括依次连接的第一水平段、竖直段和第二水平段，所述第一水平段连接于所述第一部分，在所述LED芯片的行方向上，所述第二水平段位于所述LED芯片的外侧。
  11. 根据权利要求9所述的拼接式LED灯板，其中，在所述LED芯片的列方向上，所述第一信号走线设置于所述LED芯片的外侧。
  12. 根据权利要求11所述的拼接式LED灯板，其中，所述LED灯板还包括多条第一连接走线，所述第一连接走线一一对应电性连接于一所述LED芯片，所述第一信号走线通过所述第一连接走线与所述LED芯片电性连接；
    所述第一连接走线与所述第一信号走线异层设置。
  13. 根据权利要求12所述的拼接式LED灯板，其中，在所述LED芯片的列方向上，所述第二信号走线位于所述LED芯片的外侧，且与所述第一信号走线异侧设置；
    所述LED灯板还包括多条第二连接走线，所述第二连接走线一一对应电性连接于一所述LED芯片，所述第二信号走线通过所述第二连接走线与所述LED芯片电性连接。
  14. 根据权利要求13所述的拼接式LED灯板，其中，在所述LED芯片的列方向上，所述第一信号走线的线宽和所述第二信号走线的线宽均小于相邻所述LED芯片之间距离的二分之一。
  15. 根据权利要求9所述的拼接式LED灯板，其中，所述第一信号走线和所述第二信号走线均为高电平信号走线或低电平信号走线。
  16. 一种显示装置，其包括液晶显示面板和背光模组，所述背光模组包括LED灯板，所述LED灯板包括：
    衬底；
    多个LED芯片，所述LED芯片阵列设置于所述衬底上；以及
    栅极驱动模块，所述栅极驱动模块设置于所述衬底上，并用于向所述LED芯片提供栅极驱动信号，所述栅极驱动模块包括多个栅极驱动单元；
    所述LED芯片设置于所述栅极驱动模块的两侧，且每个所述栅极驱动单元电性连接于两侧对应的所述LED芯片。
  17. 根据权利要求16所述的显示装置，其中，多个所述栅极驱动单元与多个所述LED芯片呈阵列排布；
    多个所述栅极驱动单元排成一列，每一所述栅极驱动单元分别电性连接于与其同行设置的两侧所述LED芯片。
  18. 根据权利要求17所述的显示装置，其中，每一所述栅极驱动单元两侧并与其电性连接的所述LED芯片的数量相同。
  19. 根据权利要求16所述的显示装置，其中，所述LED灯板还包括多条第一信号走线和多条第二信号走线，所述第一信号走线和所述第二信号走线同层设置，且与所述栅极驱动单元的部分膜层同层设置；每行的所述栅极驱动单元、所述LED芯片以及连接于二者的所述第一信号走线和所述第二信号走线形成一显示模块；
    在每一所述显示模块中，所述栅极驱动单元通过所述第一信号走线连接于位于其一侧的所述LED芯片，所述栅极驱动单元通过所述第二信号走线连接于位于其另一侧的所述LED芯片。
  20. 根据权利要求19所述的显示装置，其中，在每一所述显示模块中，所述第一信号走线和所述第二信号走线相错设置。
PCT/CN2020/109614 2020-08-05 2020-08-17 Led灯板、拼接式led灯板及显示装置 WO2022027726A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US16/981,351 US11563051B2 (en) 2020-08-05 2020-08-17 Light-emitting diode (LED) light board, spliced led light board and display device having the ends of the first and second signal wires being staggered
EP20842541.3A EP4198622A1 (en) 2020-08-05 2020-08-17 Led lamp panel, spliced led lamp panel, and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010776988.6A CN111965891B (zh) 2020-08-05 2020-08-05 Led灯板、拼接式led灯板及显示装置
CN202010776988.6 2020-08-05

Publications (1)

Publication Number Publication Date
WO2022027726A1 true WO2022027726A1 (zh) 2022-02-10

Family

ID=73363766

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/109614 WO2022027726A1 (zh) 2020-08-05 2020-08-17 Led灯板、拼接式led灯板及显示装置

Country Status (2)

Country Link
CN (1) CN111965891B (zh)
WO (1) WO2022027726A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113077724B (zh) * 2021-03-22 2022-05-03 Tcl华星光电技术有限公司 拼接式灯板及显示装置
CN113140175B (zh) * 2021-04-07 2023-04-07 武汉华星光电技术有限公司 一种显示面板及显示装置
CN114185200B (zh) * 2021-12-13 2022-11-08 Tcl华星光电技术有限公司 光源模块及显示装置
CN114648965A (zh) * 2022-04-21 2022-06-21 惠科股份有限公司 屏幕暗影补偿方法及背光模组

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201866691U (zh) * 2010-09-21 2011-06-15 丰铁流 拼接式led网格矩阵板背光源
US20150161928A1 (en) * 2013-12-06 2015-06-11 Samsung Display Co., Ltd. Display device and multi-panel display device
CN109521603A (zh) * 2018-12-10 2019-03-26 厦门天马微电子有限公司 背光模组和显示装置
CN110930953A (zh) * 2019-11-22 2020-03-27 深圳市华星光电半导体显示技术有限公司 mini-LED背光模组及液晶显示面板
CN111402754A (zh) * 2020-05-20 2020-07-10 上海天马有机发光显示技术有限公司 一种显示面板和显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009145874A (ja) * 2007-12-11 2009-07-02 Lg Display Co Ltd 液晶表示装置
TWI416221B (zh) * 2009-12-30 2013-11-21 Au Optronics Corp 具局部光源控制功能之背光模組
CN201780729U (zh) * 2010-02-01 2011-03-30 深圳市丽晶光电科技有限公司 网格式彩色发光二极管显示屏
CN102147074A (zh) * 2010-02-10 2011-08-10 深圳帝光电子有限公司 直下式超薄led背光模组
CN107065353A (zh) * 2017-04-26 2017-08-18 上海天马有机发光显示技术有限公司 显示面板以及显示面板的测试方法
CN107390413B (zh) * 2017-08-09 2020-07-28 深圳市华星光电技术有限公司 拼接式显示装置及其拼接方法
CN108777118A (zh) * 2018-07-06 2018-11-09 深圳市艾森视讯科技有限公司 一种led显示模组及拼接显示屏
CN208922016U (zh) * 2018-09-10 2019-05-31 惠州市隆利科技发展有限公司 一种可拼接直下式背光源
CN108873485A (zh) * 2018-09-10 2018-11-23 惠州市隆利科技发展有限公司 一种可拼接直下式背光源
CN209087294U (zh) * 2018-11-08 2019-07-09 中山市宏晟祥光电照明科技有限公司 一种适用于拼接级联的led光源板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201866691U (zh) * 2010-09-21 2011-06-15 丰铁流 拼接式led网格矩阵板背光源
US20150161928A1 (en) * 2013-12-06 2015-06-11 Samsung Display Co., Ltd. Display device and multi-panel display device
CN109521603A (zh) * 2018-12-10 2019-03-26 厦门天马微电子有限公司 背光模组和显示装置
CN110930953A (zh) * 2019-11-22 2020-03-27 深圳市华星光电半导体显示技术有限公司 mini-LED背光模组及液晶显示面板
CN111402754A (zh) * 2020-05-20 2020-07-10 上海天马有机发光显示技术有限公司 一种显示面板和显示装置

Also Published As

Publication number Publication date
CN111965891A (zh) 2020-11-20
CN111965891B (zh) 2021-04-27

Similar Documents

Publication Publication Date Title
WO2022027726A1 (zh) Led灯板、拼接式led灯板及显示装置
KR101648714B1 (ko) 액정 표시 장치 및 이를 포함하는 표시 장치 세트
CN101144919A (zh) 液晶显示器
WO2023065488A1 (zh) 一种显示模组及无缝拼接显示装置
WO2021223268A1 (zh) 背光模组、显示面板及电子装置
US20220130747A1 (en) Light-emitting substrate and display apparatus
WO2020062369A1 (zh) 一种阵列基板和显示面板
CN113376883A (zh) 拼接lcd显示屏
KR101644055B1 (ko) 외곽영역이 최소화된 액정표시장치
WO2022116304A1 (zh) 显示面板、显示面板的制作方法和显示屏
WO2020057020A1 (zh) 显示面板及显示装置
KR101218132B1 (ko) 액정표시장치 모듈
CN114397781A (zh) 背光模组及其制备方法和显示装置
US11563051B2 (en) Light-emitting diode (LED) light board, spliced led light board and display device having the ends of the first and second signal wires being staggered
JPS59210419A (ja) 液晶表示体装置
WO2023108745A1 (zh) 双面显示面板及双面显示拼接屏
WO2023221154A1 (zh) 显示面板、显示装置以及拼接显示装置
US8179685B2 (en) Printed circuit board and display apparatus having the same
WO2022082980A1 (zh) 显示装置及发光面板
KR101290600B1 (ko) 액정표시장치 모듈
US20220216265A1 (en) Light-emitting module and display apparatus
WO2023206615A1 (zh) 显示面板及显示装置
CN114913779B (zh) 显示模组和终端设备
CN210465935U (zh) 一种液晶显示面板及电子设备
WO2024011597A1 (zh) 显示面板和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20842541

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2020842541

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE