WO2024011597A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2024011597A1
WO2024011597A1 PCT/CN2022/106017 CN2022106017W WO2024011597A1 WO 2024011597 A1 WO2024011597 A1 WO 2024011597A1 CN 2022106017 W CN2022106017 W CN 2022106017W WO 2024011597 A1 WO2024011597 A1 WO 2024011597A1
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WO
WIPO (PCT)
Prior art keywords
common electrode
via hole
base substrate
electrode bus
hole structure
Prior art date
Application number
PCT/CN2022/106017
Other languages
English (en)
French (fr)
Inventor
王骁
尹晓峰
刘玉清
闫岩
马禹
陈维涛
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280002217.9A priority Critical patent/CN117716283A/zh
Priority to PCT/CN2022/106017 priority patent/WO2024011597A1/zh
Publication of WO2024011597A1 publication Critical patent/WO2024011597A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells

Definitions

  • Embodiments of the present disclosure relate to a display panel and a display device.
  • the liquid crystal display panel is one of the non-luminescent image display devices.
  • the liquid crystal display panel includes a color filter substrate, an array substrate with thin film transistors disposed thereon, and a liquid crystal layer formed by injecting between the color filter substrate and the array substrate. Since the liquid crystal molecules in the liquid crystal layer are anisotropic, the liquid crystal display panel can utilize differences in light transmittance to display images.
  • the liquid crystal display panel includes a liquid crystal panel and a drive circuit for driving the liquid crystal panel.
  • the pixel units on the liquid crystal panel are arranged in a matrix, and the gate lines and data lines on the liquid crystal panel intersect to define a pixel area.
  • the liquid crystal cell is arranged in the pixel area.
  • the liquid crystal panel is also provided with a common electrode and a pixel electrode that provide electric fields to each liquid crystal cell.
  • Each pixel electrode is connected to the data line through the source or drain lead line of the thin film transistor that functions as a switching element, and the gate lead line of the switching transistor is connected to the gate line.
  • the driving circuit includes a gate driver that drives a gate line, a data driver that drives a data line, and a common voltage generator that drives a common electrode.
  • the gate driver delivers gate signals to the gate lines in order to sequentially drive the liquid crystal cells on the liquid crystal panel. Therefore, the liquid crystal display panel can adjust the light transmittance of each liquid crystal cell according to the electric field applied between the pixel electrode and the common electrode in response to the data voltage signal, and then display the image.
  • At least one embodiment of the present disclosure provides a display panel and a display device.
  • the conductive connection layer is connected to the branch portion of the first common electrode bus through a first via hole structure in the peripheral area, and the conductive connection layer is connected through a second common electrode bus.
  • the via hole structure is electrically connected to the first end of the second common electrode bus.
  • the structural design of the display panel can increase the number of the first via hole structure and the second via hole structure and reduce the resistance in the circuit structure to avoid There is a problem that the first via hole structure and the second via hole structure are burned, resulting in a reduction in the product yield of the display panel and a shortened life of the display panel.
  • the display panel is a liquid crystal display panel
  • arranging the first via hole structure and the second via hole structure away from the display area can also avoid the heat dissipated from the first via hole structure and the second via hole structure causing the liquid crystal to
  • the problem is that the temperature of the liquid crystal layer in the display area of the display panel increases to reach the clearing point of the liquid crystal.
  • At least one embodiment of the present disclosure provides a display panel, which includes: a base substrate, including a display area and a peripheral area surrounding the display area; a first common electrode bus stacked on the base substrate, A second common electrode bus and a conductive connection layer, wherein the first common electrode bus includes a main body part and a branch part extending from an end of the main body part to a side away from the display area, the main body part Extending along the first direction, at least the portion of the branch portion connected to the main body portion extends along the second direction, and the first direction and the second direction intersect; the second common electrode bus line extends along The second direction extends to a side away from the display area, and the first end of the second common electrode bus is directly opposite to the end of the main body part and the branch part; in the peripheral area,
  • the conductive connection layer is electrically connected to the branch portion of the first common electrode bus through a first via hole structure, and the conductive connection layer is electrically connected to the branch portion of the second common electrode bus through a second via hole
  • the branch portion on a plane parallel to the main surface of the base substrate, the branch portion at least includes a first bending portion away from the display area, and the The orthographic projection of the first via hole structure on the base substrate and the orthographic projection of the first bending portion on the base substrate at least partially overlap.
  • the first end portion extends into the opening area defined by the first bending portion.
  • the orthographic projection of the second via hole structure on the base substrate and the orthographic projection of the first end portion on the base substrate at least partially overlap.
  • the first bending portion includes a first sub-bending portion extending along the second direction and a first sub-bending portion extending toward the second direction along the first direction.
  • a second sub-bent portion extends from one side of the common electrode bus, the extension direction of the second common electrode bus is parallel to the second direction, and the first sub-bent portion is on the front side of the base substrate.
  • the projection and the orthographic projection of the first via structure on the base substrate have overlapping portions
  • the orthographic projection of the second sub-bending portion on the base substrate and the first via hole Orthographic projections of the structures onto the base substrate have overlapping portions.
  • the first bending portion includes a first sub-bending portion extending along the second direction and a first sub-bending portion extending toward the second direction along the first direction.
  • a second sub-bent portion extends from one side of the common electrode bus, the extension direction of the second common electrode bus is parallel to the second direction, and the first sub-bent portion is on the front side of the base substrate.
  • the projection and the orthographic projection of the first via structure on the base substrate have overlapping portions
  • the orthographic projection of the second sub-bending portion on the base substrate and the first via hole Orthographic projections of the structures onto the base substrate have no overlapping portions.
  • the first bending portion includes a first sub-bending portion extending along the second direction and a first sub-bending portion extending toward the second direction along the first direction.
  • a second sub-bent portion extends from one side of the common electrode bus, the extension direction of the second common electrode bus is parallel to the second direction, and the first sub-bent portion is on the front side of the base substrate.
  • the projection and the orthographic projection of the first via structure on the base substrate do not have an overlapping portion, and the orthographic projection of the second sub-bending portion on the base substrate and the first through hole structure have no overlapping portion. Orthographic projections of the hole structures on the base substrate have overlapping portions.
  • the branch portion further includes a second bending portion away from the display area, and the The second bending portion includes a third sub-bending portion extending along the second direction and a fourth sub-bending portion extending along the first direction.
  • the second sub-bending portion and the fourth sub-bending portion The bending parts are connected so that the overall shape of the first bending part and the second bending part is "U"-shaped, and the second common electrode bus extends into the "U"-shaped opening.
  • the orthographic projection of the third sub-bent portion on the base substrate and the orthogonal projection of the first via hole structure on the base substrate are The projection has an overlapping portion, and the orthographic projection of the fourth sub-bent portion on the base substrate and the orthographic projection of the first via structure on the base substrate have an overlapping portion.
  • the orthographic projection of the third sub-bent portion on the base substrate and the orthogonal projection of the first via hole structure on the base substrate are The projection has an overlapping portion, and the orthographic projection of the fourth sub-bending portion on the base substrate and the orthographic projection of the first via structure on the base substrate do not have an overlapping portion.
  • the main body portion of the first common electrode bus is parallel to the first direction.
  • the main body part is provided with a third via hole structure, and the main body part is electrically connected to the conductive connection layer through the third via hole structure.
  • the minimum distance between the first via hole structure and the second via hole structure and the display area is greater than 500 microns.
  • the first via hole structure is configured as multiple
  • the second via hole structure is configured as multiple
  • the first via hole structure and the The total number of second via structures is greater than or equal to 150.
  • the first via structure and the second via structure are arranged in a matrix, the first direction is the row direction, and the second direction is the column direction. direction, the sum of the number of the first via structure and the second via structure in a row along the first direction is greater than 15, and the first via hole in a column along the second direction.
  • the sum of the number of the first via structure and the second via structure is greater than 10
  • the sum of the number of the first via structure and the second via structure in a row along the first direction is greater than the sum of the number of the first via structure and the second via structure along the first direction.
  • the second direction is the sum of the number of the first via hole structure and the second via hole structure in a column.
  • the first via structure and the second via structure are arranged in a matrix, the first direction is the row direction, and the second direction is the column direction. direction, the sum of the number of the first via structure and the second via structure in a row along the first direction is greater than 10, and the first via hole in a column along the second direction.
  • the sum of the number of the first via structure and the second via structure is greater than 15, and the sum of the number of the first via structure and the second via structure in a row along the first direction is smaller than the sum of the number of the first via structure and the second via structure along the first direction.
  • the second direction is the sum of the number of the first via hole structure and the second via hole structure in a column.
  • the maximum size of the first via hole structure and the second via hole structure on the main board surface parallel to the base substrate ranges from 4 microns. ⁇ 6 microns.
  • the display panel provided by at least one embodiment of the present disclosure further includes: a thin film transistor and a first electrode provided on the base substrate and in the display area, wherein the thin film transistor includes a stacked gate electrode, An active layer and a source-drain electrode layer.
  • the source-drain electrode layer includes a source electrode and a drain electrode arranged oppositely.
  • the first common electrode bus line and the gate electrode are arranged in the same layer.
  • the second common electrode bus line and the gate electrode are arranged in the same layer.
  • the source electrode and the drain electrode are arranged in the same layer, the conductive connection layer and the first electrode are arranged in the same layer and are spaced apart from each other, and the first electrode is electrically connected to the drain electrode through a fourth via hole structure.
  • a gate insulating layer is provided on a side of the gate electrode away from the base substrate, and a gate insulation layer is provided on a side of the source and drain electrode layer away from the base substrate.
  • a passivation layer is provided on one side of the layer.
  • the second common electrode bus lines are configured as two , and the two second common electrode bus lines are arranged oppositely along the first direction on both sides of the main body of the first common electrode bus line; the display panel also includes the first common electrode bus line and the first common electrode bus line.
  • a third common electrode bus with buses arranged oppositely in the second direction, the third common electrode bus and the main body part of the first common electrode bus are parallel, and the third common electrode bus and the The first common electrode bus is arranged on the same layer, and the two second common electrode buses, the first common electrode bus and the third common electrode bus are arranged around the display area; two second common electrode buses
  • the common electrode bus respectively includes a second end and a third end far away from the first common electrode bus in the first direction, and the conductive connection layer passes through the fifth via structure and the second end and The third end is electrically connected;
  • the third common electrode bus includes a fourth end opposite to the second end and a fifth end opposite to the third end, and the conductive connection layer
  • the sixth via structure is electrically connected to the fourth end and the fifth end.
  • a portion of the third common electrode bus between the fourth end and the fifth end passes through a seventh via structure and the The conductive connection layer is electrically connected.
  • At least one embodiment of the present disclosure further provides a display device, which includes the display panel in any of the above examples.
  • Figure 1 is a schematic diagram of the planar structure of a display panel
  • Figure 2 is a schematic plan view of a display panel provided by at least one embodiment of the present disclosure
  • Figure 3 is an enlarged planar structural schematic diagram of a first bending portion provided by at least one embodiment of the present disclosure
  • Figure 4 is an enlarged planar structural schematic diagram of yet another first bending portion provided by at least one embodiment of the present disclosure
  • Figure 5 is an enlarged schematic plan view of another first bending portion provided by at least one embodiment of the present disclosure.
  • Figure 6 is an enlarged schematic plan view of a branch portion provided by at least one embodiment of the present disclosure.
  • Figure 7 is an enlarged schematic plan view of yet another branch portion provided by at least one embodiment of the present disclosure.
  • Figure 8 is an enlarged schematic plan view of another branch portion provided by at least one embodiment of the present disclosure.
  • Figure 9 is a circuit diagram of a first via structure and a second via structure provided by at least one embodiment of the present disclosure.
  • FIG. 10 is a schematic cross-sectional structural diagram of a display panel provided by at least one embodiment of the present disclosure.
  • Thin film transistor display is a type of display. Each pixel on the thin film transistor display is driven by a field effect thin film transistor integrated behind it, so that information on the high-brightness and high-contrast display screen can be obtained. Due to GOA The drive circuit can replace the gate drive chip on film (Gate COF). The manufacturing cost of the GOA drive circuit is lower than the manufacturing cost of the gate drive chip on film. Therefore, the use of GOA drive circuit can save production costs and make it possible On the basis of reducing production costs, the display device can be mass-produced and used in the display field.
  • a display panel usually includes a plurality of electronic components, including thin film transistors, signal lines, electrode patterns, and the like.
  • the structures of these electronic components are distributed in different layer structures.
  • conductive patterns located on different layers pass through multiple via structures and electrical connection layers.
  • Connection means that two conductive patterns located on different layers are electrically connected to the electrical connection layer through corresponding via structures, thereby achieving electrical connection between the conductive patterns located on different layers.
  • Display panels are also widely used in small-size display panels such as e-sports monitors. As the e-sports market continues to expand, similar to large-size display panels, the two conductive patterns located on different layers in small-size display panels also pass through corresponding The through-hole structure is electrically connected to the electrical connection layer.
  • the refresh frequency has developed from 60Hz to high refresh frequencies such as 120Hz, 144Hz, 165Hz, 240Hz or 480Hz. , the higher the frequency, the greater the heat generated.
  • the inventor of the present disclosure noticed that in current medium and large size display panels and small size display panels, the resistance values at the junctions of the electrical connection layer and the conductive pattern are both large, that is, the resistance at the via structure is large, and the resistance is high. The smaller the current value, the more heat dissipated from the via structure when the same current passes through, and the higher the heat generated.
  • the via hole structure is also close to the display area, which will increase the temperature of the liquid crystal layer located in the display area. When the temperature of the liquid crystal layer exceeds the temperature of the liquid crystal molecules, When clearing the dots, the liquid crystal layer will become transparent, which will affect the display of the display area and result in a poor display image.
  • the above display area refers to the area corresponding to the effective pixels.
  • the pixels of the display panel include effective pixels and dummy pixels (dummy pixels).
  • the display area is the area corresponding to the effective pixels.
  • the via structure is the same as the area corresponding to the effective pixels.
  • the distance of the display area refers to the minimum distance between the via structure and the effective pixels. In some cases, it is easy for the via structure to be burned, resulting in a reduction in the product yield of the LCD panel and a short life of the LCD panel.
  • Figure 1 is a schematic plan view of a display panel.
  • a vertical common electrode bus 012 is provided on the right side of the display area 011, and a horizontal common electrode bus 013 is provided below the display area 011.
  • a first via hole 014 is provided above the horizontal common electrode bus 013, a second via hole 015 is provided above the vertical common electrode bus 012, and a conductive via hole 014 is provided above the first via hole 014 and the second via hole 015.
  • Connection layer 016 is electrically connected to the lateral common electrode bus 013 through the first via hole 014, and the conductive connection layer 016 is electrically connected to the vertical common electrode bus 012 through the second via hole 015, so that the lateral common electrode bus 013 and the vertical common electrode bus 012 are electrically connected.
  • the area where the vertical common electrode bus 012 and the lateral common electrode bus 013 face each other is smaller, so that the first via 014 and the second via 014 can be laid out.
  • the area of the via hole 015 is smaller, so that the number of the first via hole 014 and the second via hole 015 is smaller, so that there are fewer circuits connected in parallel, and the resistance in the entire circuit is larger, so that the first via hole 014 and the second via hole 015 are smaller.
  • the second via hole 015 releases a lot of heat, which causes the first via hole 014 and the second via hole 015 to be easily burned, which reduces the product yield of the display panel and shortens the life of the display panel.
  • the first via hole 014 and the second via hole 015 are relatively close to the display area 011, and it is easy for the heat dissipated from the first via hole 014 and the second via hole 015 to cause the liquid crystal display
  • the temperature of the liquid crystal layer in the display area 011 of the panel increases to reach the clearing point of the liquid crystal. Therefore, it can be considered to set the number of the first via hole 014 and the second via hole 015 to be larger.
  • the second via hole 015 and the second via hole 015 are arranged away from the display area 011 to reduce the impact of the heat dissipated by the first via hole 014 and the second via hole 015 on the display area 011 .
  • At least one embodiment of the present disclosure provides a display panel, which includes a base substrate, a first common electrode bus, a second common electrode bus, and a conductive connection layer stacked on the base substrate.
  • the base substrate includes a display area and a peripheral area surrounding the display area.
  • the first common electrode bus includes a main body part and a branch part extending from an end of the main body part to a side away from the display area.
  • the main body part extends along The first direction extends, at least the portion of the branch portion connected to the main body portion extends along the second direction, and the first direction and the second direction intersect.
  • the second common electrode bus extends along the second direction to a side away from the display area, and the first end of the second common electrode bus directly faces the end of the main body and the branch part.
  • the conductive connection layer is connected to the branch portion of the first common electrode bus through the first via hole structure, and the conductive connection layer is electrically connected to the first end of the second common electrode bus through the second via hole structure.
  • the display panel The structural design can increase the number of the first via hole structure and the second via hole structure and reduce the resistance in the circuit structure to avoid the first via hole structure and the second via hole structure being burned, resulting in the display panel product The yield rate is reduced and the life of the display panel is shortened.
  • the display panel is a liquid crystal display panel
  • arranging the first via hole structure and the second via hole structure away from the display area can also avoid the heat dissipated from the first via hole structure and the second via hole structure causing the liquid crystal to
  • the problem is that the temperature of the liquid crystal layer in the display area of the display panel increases to reach the clearing point of the liquid crystal.
  • FIG. 2 is a schematic plan view of a display panel according to at least one embodiment of the present disclosure.
  • the display panel 100 includes: a base substrate 101 and a first common electrode bus 102 stacked on the base substrate 101. Two common electrode bus lines 103 and conductive connection layers 104.
  • the base substrate 101 includes a display area 105 and a peripheral area 106 surrounding the display area 105.
  • the first common electrode bus 102 includes a main body part 102a and extends from an end part 102a' of the main body part to a side away from the display area 105. branch part 102b.
  • the main body part 102a extends along the first direction The second direction Y intersects.
  • the branch portion 102 b includes two parts, the two parts form a step shape, and the first end 103 a of the second common electrode bus 103 extends to the lateral platform of the step.
  • the portion of the branch portion 102b connected to the main body portion 102a extends along the second direction Y to form a stepped vertical portion.
  • the branch portion 102b may also include only a long strip portion connected to the main body 102a and extending along the second direction Y, or the branch portion 102b may also include multiple a stepped part.
  • the second common electrode bus 103 extends along the second direction Y to a side away from the display area 105 , and the first end 103 a and the main body of the second common electrode bus 103 The end portion 102a' and the branch portion 102b are both facing each other.
  • the conductive connection layer 104 is connected to the branch portion 102 b of the first common electrode bus 102 through the first via hole structure 107 , and the conductive connection layer 104 is connected through the second via hole structure 108 and the first branch portion 102 b of the second common electrode bus 103 .
  • the end 103a is electrically connected.
  • the second via hole structure 108 is only provided at the position of the first end portion 103a corresponding to the branch portion 102b. It should be noted that the first end portion 103a is also provided with a via structure at a position corresponding to the end portion 102a' of the main body portion. The size, shape, distribution density, etc. of the via hole structure at this position may be the same as those of the second via hole structure.
  • the pore structure 108 is different.
  • the maximum size of the via hole structure at the position corresponding to the end portion 102a' of the main body portion of the first end portion 103a and parallel to the main surface of the base substrate 101 is greater than the maximum size of the second via hole structure 108.
  • the distribution The density is smaller than the distribution density of the second via structure 108 .
  • the display panel 100 further includes a third common electrode bus 126 disposed opposite to the first common electrode bus 102 in the second direction Y.
  • the third common electrode bus 126 is connected to the first common electrode bus 102 .
  • the main body part 102a of the common electrode bus 102 is parallel, and the third common electrode bus 126 and the first common electrode bus 102 are arranged on the same layer.
  • a second common electrode bus 103 is provided on the left and right sides of the first common electrode bus 102 and the third common electrode bus 126.
  • the first common electrode bus 102, the third common electrode bus 126 and the two second common electrode bus lines 103 They are all located in the peripheral area 106 .
  • the two second common electrode bus lines 103 , the first common electrode bus line 102 and the third common electrode bus line 126 are arranged around the display area 105 to form a structure surrounding the display area 105 .
  • An anti-static structure 110 and an electrostatic lead-out line 111 are provided on a side of the third common electrode bus 126 away from the display area 105 and in a direction from a position close to the display area 105 to a position away from the display area 105 .
  • anti-static structures 110 are provided on a side of the first common electrode bus 102 away from the display area 105 and in a direction from a position close to the display area 105 to a position away from the display area 105 . and a fan-out area 109 configured to apply touch signals and/or display signals, etc., to the display area.
  • branch portions 107 extending to the side away from the display area 105 are provided only at the two end portions 102a' of the main body of the first common electrode bus 102.
  • the branch portions 107 are the gathering places for currents. The heat generated there is very large, so the branch part 107 needs to be arranged away from the display area 105 .
  • No branch portion 107 is provided at any end of the third common electrode bus 126 .
  • a gate driving circuit 114 is provided on the side of the second common electrode bus 103 on the left away from the display area 105 , and on the side of the second common electrode bus 103 on the right away from the display area 105 .
  • a gate driving circuit 114 is also provided on one side, and the gate driving circuit 114 can apply scanning signals to the gate lines.
  • the display panel 100 also includes a common electrode line 115 extending from the display area 105, and the common electrode line 115 is electrically connected to the second common electrode bus line 103 and the conductive connection layer 104.
  • the structural design of the display panel 100 can set the branch portion 107 further away from the display area 105, so that there is a larger area on the branch portion 107 to provide more via structures, so that the first via structure 107 and The number of the second via hole structure 108 is increased to reduce the resistance in the circuit structure to prevent the first via hole structure 107 and the second via hole structure 108 from being burned, resulting in a reduction in the product yield of the display panel 100 and the display panel The problem of shorter life span.
  • the display panel is a liquid crystal display panel
  • arranging the first via hole structure 107 and the second via hole structure 108 away from the display area 105 can also avoid the appearance of the first via hole structure 107 and the second via hole structure 108
  • the dissipated heat causes the temperature of the liquid crystal layer in the display area of the liquid crystal display panel to rise to reach the clearing point of the liquid crystal.
  • the minimum distance between the first via hole structure 107 and the second via hole structure 108 and the display area 105 is both greater than 500 microns.
  • the minimum distance between the first via hole structure 107 and the display area 105 may be equal to the minimum distance between the second via hole structure 108 and the display area 105 , or the first via hole structure 107 may be The minimum distance between the first via hole structure 107 and the display area 105 is greater than the minimum distance between the second via hole structure 108 and the display area 105 , or the minimum distance between the first via hole structure 107 and the display area 105 is smaller than the second via hole structure.
  • the minimum distance between 108 and the display area 105 is not limited by the embodiments of the present disclosure.
  • the minimum distance D between the first via hole structure 107 and the display area 105 is smaller than the minimum distance between the second via hole structure 108 and the display area 105 , and the first via hole structure 107
  • the minimum distance D from the display area 105 is greater than 500 microns. The setting of this distance can prevent the heat dissipated from the first via structure 107 and the second via structure 108 from causing damage to the liquid crystal layer in the display area of the liquid crystal display panel. The problem of display quality deteriorating as the temperature rises to reach the clearing point of the liquid crystal.
  • the branch portion 107 at least includes a first bending portion 112 away from the display area 105 , and the first via structure 107 is on the base substrate 101 .
  • the orthographic projection on the substrate 101 at least partially overlaps with the orthographic projection of the first bending portion 112 on the base substrate 101 .
  • the entire structure of the branch part 107 is the first bending part 112 and does not include other structures.
  • the branch part 107 may also include other structures, for example, the branch part 107 It may also include more bending portions or long strip portions extending from the first bending portion 112 to a side away from the display area 105 , and embodiments of the present disclosure are not limited thereto.
  • the first end portion 103 a extends into the opening area 113 defined by the first bending portion 112 , and the second via hole structure
  • the orthographic projection of 108 on the base substrate 101 and the orthographic projection of the first end 103a on the base substrate 101 at least partially overlap, that is, the orthographic projection of the first end 103a on the base substrate 101 can overlap with all
  • the orthographic projection of the second via hole structure 108 on the base substrate 101 may overlap with the orthographic projection of part of the second via hole structure 108 on the base substrate 101 .
  • the main body portion 102 a of the first common electrode bus 102 is disposed in a direction parallel to the first direction X, that is, in FIG. 2
  • the main body portion 102a of the first common electrode bus 102 extends laterally.
  • a plurality of third via hole structures 116 are provided on the main body part 102a, and the main body part 102a is electrically connected to the conductive connection layer 104 through the plurality of third via hole structures 116.
  • the main body 102a has a plurality of parallel branches.
  • the plurality of third via hole structures 116 are relatively close to the display area 105, the resistance of the multiple parallel branches is very small, and The current does not pool here, thus generating very little heat and not affecting the display of the display area.
  • FIG. 3 is an enlarged planar structural diagram of a first bending part provided by at least one embodiment of the present disclosure.
  • the first bending part 112 includes a first sub-section extending along the second direction Y.
  • the bent portion 112a and the second sub-bent portion 112b extending along the first direction
  • the plane shape is "L" shaped.
  • the extension direction of the second common electrode bus 103 is parallel to the second direction Y.
  • the orthographic projection of the first sub-bent portion 112a on the base substrate 101 and the orthographic projection of the first via hole structure 107 on the base substrate 101 have The overlapping portion, and the orthographic projection of the second sub-bent portion 112b on the base substrate 101 and the orthographic projection of the first via structure 107 on the base substrate 101 have an overlapping portion, and the first via structure 107 row
  • the overall shape of the cloth is also "L" shaped.
  • the orthographic projection of a part of the first sub-bent portion 112 a on the substrate 101 overlaps with the orthographic projection of the first via structure 107 on the substrate 101
  • the second The orthographic projection of a part of the sub-bent portion 112b on the base substrate 101 and the orthographic projection of the first via structure 107 on the base substrate 101 overlap.
  • the orthographic projection of a portion of the first end portion 103 a on the base substrate 101 and the orthographic projection of the second via structure 108 on the base substrate 101 overlap.
  • the first bending portion 112 has a simple structure and can meet the number requirements of the plurality of first via structures 107 and the plurality of second via structures 108, making the process simple.
  • this design can also allow the first via hole structure 107 to be provided on both the first sub-bent portion 112a and the second sub-bent portion 112b, so that the first via hole structure 107 corresponds to the second via hole structure 108. Distribute them as evenly as possible to make the connection between the second common electrode bus 103 and the first common electrode bus 102 more stable.
  • the orthographic projection of the conductive connection layer 104 on the base substrate 101 overlaps with the orthographic projection of part of the second common electrode bus 103 on the base substrate 101
  • the conductive connection layer 104 is arranged around the display area 105, that is, the orthographic projection of the conductive connection layer 104 on the base substrate 101 covers the orthographic projection of the first common electrode bus 102 on the base substrate 101.
  • the orthographic projection of the third common electrode bus 126 on the base substrate 101 and the orthographic projection of the two second common electrode bus lines 103 on the base substrate 101 are examples of the orthographic projection of the conductive connection layer 104 on the base substrate 101 .
  • FIG. 4 is an enlarged plan structural diagram of yet another first bending part provided by at least one embodiment of the present disclosure.
  • the first bending part 112 includes a first bending part 112 extending along the second direction Y.
  • the overall planar shape is "L" shaped.
  • the extension direction of the second common electrode bus 103 is parallel to the second direction Y.
  • the orthographic projection of the first sub-bent portion 112a on the base substrate 101 and the orthographic projection of the first via hole structure 107 on the base substrate 101 have The overlapping portion, and the orthographic projection of the second sub-bent portion 112b on the base substrate 101 and the orthographic projection of the first via hole structure 107 on the base substrate 101 do not have an overlapping portion, the first via hole structure 107
  • the overall shape of the arrangement is also linear, and the linear arrangement of the first via structure 107 is directly opposite to the linear arrangement of the second via structure 108 .
  • the linear arrangement of the first via structure 107 and the linear arrangement of the second via structure 108 are based on meeting the number requirements of the plurality of first via structures 107 and the plurality of second via structures 108 , it can also make the process of forming the first via structure 107 simple, and the width of the second sub-bent portion 112b in the second direction Y can be set as small as possible, so that the width of the lower frame can be reduced, so that The width of the bottom border is narrower.
  • the orthographic projection of the conductive connection layer 104 on the base substrate 101 overlaps with the orthographic projection of part of the second common electrode bus 103 on the base substrate 101
  • the conductive connection layer 104 is arranged around the display area 105, that is, the orthographic projection of the conductive connection layer 104 on the base substrate 101 covers the orthographic projection of the first common electrode bus 102 on the base substrate 101.
  • the orthographic projection of the third common electrode bus 126 on the base substrate 101 and the orthographic projection of the two second common electrode bus lines 103 on the base substrate 101 are examples of the orthographic projection of the conductive connection layer 104 on the base substrate 101 .
  • FIG. 5 is an enlarged schematic plan view of another first bending part provided by at least one embodiment of the present disclosure.
  • the first bending part 112 includes a first bending part 112 extending along the second direction Y.
  • the overall planar shape is "L" shaped.
  • the extension direction of the second common electrode bus 103 is parallel to the second direction Y, the orthographic projection of the first sub-bent portion 112a on the base substrate 101 and the orthographic projection of the first via hole structure 107 on the base substrate 101 There is no overlapping portion, and the orthographic projection of the second sub-bent portion 112b on the base substrate 101 and the orthographic projection of the first via structure 107 on the base substrate 101 have overlapping portions.
  • the first bending portion 112 has a simple structure and can satisfy the number requirements of the plurality of first via structures 107 and the plurality of second via structures 108, thereby simplifying the process.
  • this design can also allow the first via structure 107 to be provided only on the second sub-bent portion 112b, thereby increasing the distance between the first via structure 107 and the display area 105, thereby reducing the distance from the first via structure 107 to the display area 105.
  • the influence of the heat dissipated by the first via structure 107 on the display area 105 can also allow the first via structure 107 to be provided only on the second sub-bent portion 112b, thereby increasing the distance between the first via structure 107 and the display area 105, thereby reducing the distance from the first via structure 107 to the display area 105. The influence of the heat dissipated by the first via structure 107 on the display area 105 .
  • the orthographic projection of the conductive connection layer 104 on the base substrate 101 overlaps with the orthographic projection of part of the second common electrode bus 103 on the base substrate 101
  • the conductive connection layer 104 is arranged around the display area 105, that is, the orthographic projection of the conductive connection layer 104 on the base substrate 101 covers the orthographic projection of the first common electrode bus 102 on the base substrate 101.
  • the orthographic projection of the third common electrode bus 126 on the base substrate 101 and the orthographic projection of the two second common electrode bus lines 103 on the base substrate 101 are examples of the orthographic projection of the conductive connection layer 104 on the base substrate 101 .
  • FIG. 6 is an enlarged plan view of a branch portion provided by at least one embodiment of the present disclosure.
  • the branch portion 107 includes a structure far away from the display.
  • the first bending part 112 includes a first sub-bending part 112a extending along the second direction Y and a first bending part 112a extending along the first direction X.
  • the second sub-bent portion 112b extends toward the side close to the second common electrode bus 103.
  • the first sub-bent portion 112a and the second sub-bent portion 112b have an overall planar shape of "L" shape.
  • the second bending portion 113 includes a third sub-bending portion 113a extending along the second direction Y and a fourth sub-bending portion 113b extending along the first direction X.
  • the second sub-bending portion 112b and the fourth sub-bending portion 113b extend along the first direction X.
  • the bending portion 113b is connected so that the overall shape of the first bending portion 112 and the second bending portion 113 is a "U" shape.
  • the extending direction of the second common electrode bus 103 is parallel to the second direction Y, and the second common electrode bus 103 extends in a U-shaped manner.
  • the electrode bus 103 extends into the "U"-shaped opening.
  • the edges of the second sub-bent portion 112b and the fourth sub-bent portion 113b shown in Figure 6 are right-angled edges, although the final formed
  • the shape of the branch part is not strictly "U"-shaped, but can also be equivalent to a "U"-shaped one.
  • the edges of the second sub-bent part 112b and the fourth sub-bent part 113b are also It may be an arc-shaped edge, so that the cross-sectional shape of the finally formed branch part is a "U" shape.
  • the orthographic projection of a part of the first sub-bent portion 112 a on the substrate 101 overlaps with the orthographic projection of the first via structure 107 on the substrate 101
  • the second sub-bent portion 112 a overlaps with the orthographic projection of the first via structure 107 on the substrate 101
  • the orthographic projection of a part of the bent portion 112b on the base substrate 101 overlaps with the orthographic projection of the first via hole structure 107 on the base substrate 101.
  • the orthogonal projection of the third sub-bent portion 113a on the base substrate 101 overlaps.
  • the projection and the orthographic projection of the first via hole structure 107 on the base substrate 101 have overlapping portions, and the orthographic projection of the fourth sub-bent portion 113b on the base substrate 101 and the first via hole structure 107 have an overlapping portion on the base substrate 101
  • the orthographic projection on 101 has an overlapping portion, so that the arrangement shape of the first via structure 107 is also a "U" shape, so that the first end 103a of the second common electrode bus 103 and the first common electrode bus 102 Connect as many locations as possible.
  • This structure allows the first via structure 107 to be provided at the corresponding positions of the first sub-bent part 112a and the third sub-bent part 113a of the "U"-shaped branch part.
  • the first sub-bent portion 112a is electrically connected to the first end 103a of the second common electrode bus 103 through the first via structure 107 and the conductive connection layer 104, and the third sub-bent portion 113a passes through the first via structure 107 and the conductive connection layer 104.
  • the conductive connection layer 104 is electrically connected to the first end 103a of the second common electrode bus 103, so that the first end 103a of the second common electrode bus 103 can be electrically connected to the first sub-bent portion 112a. It is electrically connected to the third sub-bent portion 113a, so that more parallel circuits are formed, and the resistance can be further reduced to reduce the heat dissipation.
  • This structure allows the first via structure 107 to be provided at the corresponding positions of the second sub-bent portion 112b and the fourth sub-bent portion 113b of the "U"-shaped bottom.
  • the second sub-bent portion 112b is electrically connected to the first end 103a of the second common electrode bus 103 through the first via structure 107 and the conductive connection layer 104, and the fourth sub-bent portion 113b passes through the first via structure 107 and the conductive connection layer 104.
  • the conductive connection layer 104 is electrically connected to the first end 103a of the second common electrode bus 103, so that the first end 103a of the second common electrode bus 103 can also be connected to the second sub-bent portion 112b and the fourth sub-bend.
  • the folded portions 113b are electrically connected, thereby forming more parallel circuits, further reducing resistance and further reducing dissipated heat.
  • FIG. 7 is an enlarged schematic plan view of yet another branch portion provided by at least one embodiment of the present disclosure. As shown in FIG.
  • the orthographic projection of a part of the first sub-bending portion 112a on the base substrate 101 Overlapping with the orthographic projection of the first via hole structure 107 on the base substrate 101 , the orthographic projection of a part of the second sub-bent portion 112 b on the base substrate 101 overlaps with the orthographic projection of the first via hole structure 107 on the base substrate 101
  • the orthographic projection of the third sub-bent portion 113a on the base substrate 101 overlaps with the orthographic projection of the first via structure 107 on the base substrate 101, and the fourth sub-bent portion 113a has an overlapping portion.
  • the orthographic projection of the folded portion 113b on the base substrate 101 and the orthographic projection of the first via structure 107 on the base substrate 101 do not have an overlapping portion.
  • the first sub-bent portion 112a is electrically connected to the first end 103a of the second common electrode bus 103 through the first via structure 107 and the conductive connection layer 104, and the third sub-bent portion 113a passes through the first via structure 107 and the conductive connection layer 104.
  • the conductive connection layer 104 is electrically connected to the first end 103a of the second common electrode bus 103, so that the first end 103a of the second common electrode bus 103 can be electrically connected to the first sub-bent portion 112a. It is electrically connected to the third sub-bent portion 113a, so that more parallel circuits are formed, and the resistance can be further reduced to reduce the heat dissipation.
  • This structure allows the first via structure 107 to be provided at a position corresponding to the second sub-bent portion 112b of the bottom of the “U” shape.
  • the second sub-bent portion 112b is electrically connected to the first end 103a of the second common electrode bus 103 through the first via structure 107 and the conductive connection layer 104.
  • the fourth sub-bent portion 113b is not provided with a first via. hole structure 107, so that the first via hole structure 107 can be provided at the position of the "U"-shaped structure directly opposite the first end 103a of the second common electrode bus 103, and the first via hole structure can also be satisfied.
  • the orthographic projection of the conductive connection layer 104 on the base substrate 101 overlaps with the orthographic projection of part of the second common electrode bus 103 on the base substrate 101
  • the conductive connection layer 104 is arranged around the display area 105, that is, the orthographic projection of the conductive connection layer 104 on the base substrate 101 covers the orthographic projection of the first common electrode bus 102 on the base substrate 101.
  • the orthographic projection of the third common electrode bus 126 on the base substrate 101 and the orthographic projection of the two second common electrode bus lines 103 on the base substrate 101 are examples of the orthographic projection of the conductive connection layer 104 on the base substrate 101 .
  • FIG. 8 is an enlarged schematic plan view of another branch portion provided by at least one embodiment of the present disclosure.
  • the orthographic projection of a part of the first sub-bent portion 112a on the substrate 101 There is no overlapping portion with the orthographic projection of the first via hole structure 107 on the base substrate 101.
  • the orthographic projection of the second sub-bent portion 112b on the base substrate 101 and the first through hole structure 107 have no overlapping portion on the base substrate 101.
  • the orthographic projection on 101 does not have an overlapping portion
  • the orthographic projection of the third sub-bent portion 113a on the base substrate 101 and the orthographic projection of the first via structure 107 on the base substrate 101 have an overlapping portion
  • the orthographic projection of the fourth sub-bent portion 113b on the base substrate 101 and the orthographic projection of the first via structure 107 on the base substrate 101 have overlapping portions.
  • the third sub-bent portion 113a is electrically connected to the first end 103a of the second common electrode bus 103 through the first via structure 107 and the conductive connection layer 104
  • the fourth sub-bent portion 113b passes through the first via structure 107 and the conductive connection layer 104.
  • the conductive connection layer 104 is electrically connected to the first end 103a of the second common electrode bus 103, so that the first end 103a of the second common electrode bus 103 can be electrically connected to the third sub-bent portion 113a. It is electrically connected to the fourth sub-bent part 113b, so that more parallel circuits are formed, the resistance can be further reduced to reduce the dissipated heat, and the distance between the third sub-bent part 113a and the fourth sub-bent part 113b is shown
  • the area 105 is further away, and the first via hole structure 107 is disposed on the third sub-bent portion 113a and the fourth sub-bent portion 113b, which can further reduce the impact of heat dissipated from the first via hole structure 107 on the display area 105.
  • the orthographic projection of the conductive connection layer 104 on the base substrate 101 overlaps with the orthographic projection of part of the second common electrode bus 103 on the base substrate 101
  • the conductive connection layer 104 is arranged around the display area 105, that is, the orthographic projection of the conductive connection layer 104 on the base substrate 101 covers the orthographic projection of the first common electrode bus 102 on the base substrate 101.
  • the orthographic projection of the third common electrode bus 126 on the base substrate 101 and the orthographic projection of the two second common electrode bus lines 103 on the base substrate 101 are examples of the orthographic projection of the conductive connection layer 104 on the base substrate 101 .
  • the orthographic projection of a part of the first sub-bent portion 112a on the base substrate 101 and the orthographic projection of the first via structure 107 on the base substrate 101 may have The overlapping portion, the orthographic projection of a part of the second sub-bent portion 112b on the base substrate 101 and the orthographic projection of the first via structure 107 on the base substrate 101 do not have an overlapping portion, and the third sub-bending portion does not have an overlapping portion.
  • the orthographic projection of the folded portion 113a on the base substrate 101 and the orthographic projection of the first via hole structure 107 on the base substrate 101 have overlapping portions, and the orthographic projection of the fourth sub-bent portion 113b on the base substrate 101 There is no overlap with the orthographic projection of the first via hole structure 107 on the base substrate 101; it can also be the orthographic projection of a part of the first sub-bent portion 112a on the base substrate 101 and the first via hole structure.
  • the orthographic projection of 107 on the base substrate 101 does not have an overlapping portion.
  • the orthographic projection of a part of the second sub-bent portion 112b on the base substrate 101 and the orthographic projection of the first via hole structure 107 on the base substrate 101 has an overlapping portion
  • the orthographic projection of the third sub-bending portion 113a on the base substrate 101 and the orthographic projection of the first via structure 107 on the base substrate 101 have an overlapping portion
  • the fourth sub-bending portion has an overlapping portion.
  • the orthographic projection of the portion 113b on the base substrate 101 and the orthographic projection of the first via structure 107 on the base substrate 101 do not have an overlapping portion, and the embodiments of the present disclosure do not limit this.
  • the first via hole structure 107 is configured as multiple
  • the second via hole structure 108 is configured as multiple
  • the total number of the first via hole structure 107 and the second via hole structure 108 is The number is greater than or equal to 150.
  • the first via hole structure 107 and the second via hole structure 108 designed with this number can ensure that the heat generated by the professional gaming monitor at high refresh frequencies such as 240Hz or 480Hz will not affect the normal performance of the display panel. show.
  • the first via structure 107 and the second via structure 108 are arranged in a matrix.
  • the first direction X is the row direction
  • the second direction Y is the column direction.
  • the sum of the numbers of the first via structures 107 and the second via structures 108 in each row is greater than or equal to the sum of the numbers of the first via structures 107 and the second via structures 108 in each column. 1.5 times, this can make the sum of the number of the first via hole structure 107 and the second via hole structure 108 reach 150, and the first via hole structure 107 and the second via hole structure 108 are evenly arranged, so that the parallel circuit Resistance is minimal, resulting in minimal heat dissipation.
  • this design can also make the width of the conductive connection layer 104 narrower in the second direction Y, so that the distance between the lower side of the conductive connection layer 104 that is farthest from the display area 105 and the display area 105 is reduced. As a result, the width of the lower border can be reduced, making the width of the lower border narrower.
  • the first via structure 107 and the second via structure 108 are arranged in a matrix.
  • the first direction X is the row direction
  • the second direction Y is the column direction.
  • the sum of the numbers of the first via structures 107 and the second via structures 108 in each column is greater than or equal to the sum of the numbers of the first via structures 107 and the second via structures 108 in each row. 1.5 times, this can make the sum of the number of the first via hole structure 107 and the second via hole structure 108 reach 150, and the first via hole structure 107 and the second via hole structure 108 are evenly arranged, so that the parallel circuit Resistance is minimal, resulting in minimal heat dissipation.
  • this design can also make the width of the conductive connection layer 104 narrower in the first direction The distance is reduced, so that the width of the left and right borders can be reduced, making the width of the left and right borders narrower.
  • Figure 9 is a circuit diagram of a display panel with a first via hole structure and a second via hole structure provided by at least one embodiment of the present disclosure.
  • R0 corresponds to the resistance of the conductive connection layer 104
  • R1 corresponds to For the resistance of the first via structure 107 connecting the conductive connection layer 104 and the first common electrode bus 102
  • R2 corresponds to the resistance of the second via structure 108 connecting the conductive connection layer 104 and the second common electrode bus 103
  • C1 corresponds to C0 corresponds to the coupling capacitance between the conductive connection layer 104 and the source-drain electrode layer (shown in FIG.
  • C0 corresponds to the coupling capacitance between the conductive connection layer 104 and the gate electrode (shown in FIG. 10).
  • resistors R0, R1 and R2 and three capacitors C0, C1 and C2 are shown, the number of resistors and the number of capacitors in the embodiment of the present disclosure can be The more circuits connected in parallel, the smaller the resulting resistance and the less heat the entire circuit dissipates.
  • the current is I at a frequency of 60Hz
  • the heat at a frequency of 480Hz is 8 times that at 60Hz
  • R1 is equal to R2
  • the resistance is 30 ohms, which is the resistance value of resistor R0.
  • the simulated value of the 6 ⁇ m*6 ⁇ m via resistance is about 80 ohms.
  • the three capacitors C0, C1 and C2 can be ignored, and 10*10 of the same size
  • the simulated value of the comprehensive resistance of the 6 ⁇ m*6 ⁇ m via hole is about 40 ohms; in the arrangement diagram of the 10*30 first via hole structure and the second via hole structure, at this time, the three capacitors C0, C1 and C2 can be ignored.
  • the simulated value of the comprehensive resistance of 10*30 6 ⁇ m*6 ⁇ m via holes of the same size is about 16 ohms, which is a 2.5 times reduction in resistance.
  • the three capacitors C0, C1 and C2 can be ignored, and 10*10 of the same size
  • the simulated value of the comprehensive resistance of the 6 ⁇ m*6 ⁇ m via hole is about 320 ohms; in the arrangement diagram of the 10*30 first via hole structure and the second via hole structure, at this time, the three capacitors C0, C1 and C2 can be ignored, and the simulated value of the comprehensive resistance of 10*30 6 ⁇ m*6 ⁇ m via holes of the same size is about 128 ohms.
  • the current is I at a frequency of 60Hz
  • the heat at a frequency of 165Hz is 2.75 times that at 60Hz
  • R1 is equal to R2
  • the magnitudes of R1 and R2 Under the condition that both are 400 ohms, between the adjacent first via structure and the first via structure, between the adjacent first via structure and the second via structure, or between the adjacent first via structure
  • the resistance of the conductive connection layer 104 between the second via hole structure and the second via hole structure is 30 ohms, which is the resistance value of the resistor R0.
  • the simulated value of the via hole resistance of 24 ⁇ m*24 ⁇ m is about 400 ohms.
  • the three capacitors C0, C1 and C2 can be ignored, and 2*2 of the same size
  • the simulated value of the comprehensive resistance of the 24 ⁇ m*24 ⁇ m via is about 130 ohms.
  • the three capacitors C0, C1 and C2 can be ignored, and 2*2 of the same size
  • the simulated value of the comprehensive resistance of the 24 ⁇ m*24 ⁇ m via is about 357.5 ohms.
  • the resistance R1 of the first via hole structure with a size of 24 ⁇ m*24 ⁇ m is 5 times the resistance R1 of the first via hole structure with a size of 6 ⁇ m*6 ⁇ m
  • the second via hole with a size of 24 ⁇ m*24 ⁇ m The resistance R2 of the structure is 5 times the resistance R2 of the second via structure with a size of 6 ⁇ m*6 ⁇ m.
  • the via size of 6 ⁇ m*6 ⁇ m is the smallest size that the current in-factory equipment can achieve. In some embodiments of the present disclosure, 6 ⁇ m is selected. *6 ⁇ m via hole, and the smaller the size of the first via hole structure 107 and the second via hole structure 108, the smaller the corresponding resistors R1 and R2 are.
  • the maximum size of the first via hole structure 107 and the second via hole structure 108 on the main board surface parallel to the base substrate 101 ranges from 4 microns to 6 microns.
  • the first via hole structure 107 and the second via hole structure 108 have the same planar shape, and the planar shapes of the first via hole structure 107 and the second via hole structure 108 are both rectangles with the same size, The size of the long side of the rectangle is 4 to 6 microns.
  • the first via hole structure 107 and the second via hole structure 108 have the same planar shape, which is rectangular, but the dimensions of the planar shapes of the first via hole structure 107 and the second via hole structure 108 are different.
  • the size of the long side of the rectangle with the larger long side corresponding to the first via hole structure 107 and the second via hole structure 108 is 4 microns to 6 microns.
  • the first via hole structure 107 and the second via hole structure 108 have the same planar shape, which is circular, but the dimensions of the planar shapes of the first via hole structure 107 and the second via hole structure 108 Differently, the first via hole structure 107 and the second via hole structure 108 correspond to a larger diameter circle with a diameter of 4 to 6 microns.
  • first via hole structure 107 and the second via hole structure 108 have the same planar shape, which is elliptical, but the dimensions of the planar shapes of the first via hole structure 107 and the second via hole structure 108 are Differently, the major diameter of the ellipse corresponding to the first via hole structure 107 and the second via hole structure 108 has a larger major diameter of 4 to 6 microns.
  • the planar shapes of the first via hole structure 107 and the second via hole structure 108 can also be other shapes. For other shapes, comparisons are made according to similar rules, and the embodiments of the present disclosure are not limited thereto.
  • the planar shape of the third via hole structure 116 may be the same as or different from the planar shapes of the first via hole structure 107 and the second via hole structure 108 .
  • the maximum dimension of the planar shape of the third via hole structure 116 is larger than the maximum dimension of the planar shape of the first via hole structure 107 and is also larger than the maximum dimension of the planar shape of the second via hole structure 108 .
  • FIG. 10 is a schematic cross-sectional structural diagram of a display panel provided by at least one embodiment of the present disclosure.
  • the display panel 100 also includes a thin film transistor 117 disposed on the base substrate 101 and in the display area 105 and a first electrode 118.
  • the thin film transistor 117 includes a stacked gate electrode 119, an active layer 120 and a source-drain electrode layer 121.
  • the source-drain electrode layer 121 includes an oppositely arranged source electrode 121a and a drain electrode 121b.
  • the first common The electrode bus 102 and the gate electrode 119 are arranged on the same layer, the second common electrode bus 103 is arranged on the same layer as the source electrode 121a and the drain electrode 121b, the conductive connection layer 104 and the first electrode 118 are arranged on the same layer and are spaced apart from each other. 118 is electrically connected to the drain electrode 121b through the fourth via structure 122.
  • the thin film transistor 117 may be a top gate thin film transistor, a bottom gate thin film transistor, or a double gate thin film transistor, which is not limited in the embodiments of the present disclosure.
  • “same layer” refers to a layer structure formed by using the same film formation process to form a film layer for forming a specific pattern, and then using the same mask to form a patterning process.
  • the sequential patterning process may include multiple exposure, development or etching processes, and the specific graphics formed on the same layer may be continuous or discontinuous. These specific graphics may also be at different heights or have Different thicknesses.
  • a gate insulating layer 123 is provided on the side of the gate electrode 119 away from the base substrate 101
  • a passivation layer 124 is provided on the side of the source and drain electrode layer 121 away from the base substrate 101 .
  • the first via hole structure 107 penetrates the passivation layer 124 and the gate insulation layer 123 in sequence, and the second via hole structure 108 and the fourth via hole structure 122 both penetrate the passivation layer 124 .
  • the second common electrode bus lines 103 are configured as two, and the two second common electrode bus lines 103 are arranged along The first direction
  • the main part of the fourth common electrode bus 125 is parallel to the main part 102a of the first common electrode bus 102, and the fourth common electrode bus 125 and the first common electrode bus 102 are arranged on the same layer.
  • the two second common electrode buses 103 respectively include a second end 103b and a third end 103c away from the first common electrode bus 102 in the first direction X.
  • the conductive connection layer 104 passes through the fifth via structure 127 and the third The two ends 103b and the third end 103c are electrically connected.
  • the fourth common electrode bus 125 includes a fourth end 125a opposite the second end 103b and a fifth end 125b opposite the third end 103c. It is electrically conductive.
  • the connection layer 104 is electrically connected to the fourth end portion 125a and the fifth end portion 125b through the sixth via structure 128.
  • the fourth common electrode bus 125 is disposed on a side of the static electricity lead-out line 111 away from the display area 105 .
  • the fourth common electrode bus 125 , the third common electrode bus 126 and the second common electrode bus 103 are electrically connected through a conductive connection layer 104 .
  • the middle portion of the third common electrode bus 126 at its two ends is electrically connected to the conductive connection layer 104 through the seventh via structure 129 .
  • the arrangement density of the seventh via structure 129 , The planar shape and size may be the same as the third via hole structure 116 and will not be described again here.
  • At least one embodiment of the present disclosure further provides a display device, which includes the display panel in any of the above embodiments. Since the display device includes the display panel in any of the above embodiments, the structural design of the display device can also enable the branch portion to be arranged further away from the display area, so that there is a larger area on the branch portion to provide more via holes. structure, so that the number of the first via hole structure and the second via hole structure is increased to reduce the resistance in the circuit structure to avoid the first via hole structure and the second via hole structure being burned, resulting in poor product quality of the display device. The problem is that the efficiency is reduced and the life of the display device is shorter.
  • the display device is a liquid crystal display device
  • arranging the first via hole structure and the second via hole structure away from the display area can also avoid the heat dissipated from the first via hole structure and the second via hole structure causing the liquid crystal to
  • the problem is that the temperature of the liquid crystal layer in the display area of the display panel increases to reach the clearing point of the liquid crystal. That is, the resistance of the conductive connection layer crossover in the display device is small and the heat generation is small, so it has better product performance and better display effect.
  • the display device may be a liquid crystal display device, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function, which is not limited in the embodiments of the present disclosure.
  • a liquid crystal display device such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function, which is not limited in the embodiments of the present disclosure.
  • the conductive connection layer in the peripheral area, is connected to the branch portion of the first common electrode bus through the first via hole structure, and the conductive connection layer is connected to the branch portion of the first common electrode bus through the second via hole structure and the second via hole structure.
  • the first end of the common electrode bus is electrically connected, which can increase the number of the first via hole structure and the second via hole structure, reduce the resistance in the circuit structure, and avoid the occurrence of the first via hole structure and the second via hole structure. Burned out, resulting in reduced product yield of the display panel and shorter service life of the display panel.
  • the first via hole structure and the second via hole structure are arranged away from the display area, which can also avoid the occurrence of leaks from the first via hole structure.
  • the heat dissipated by the hole structure and the second via hole structure increases the temperature of the liquid crystal layer in the display area of the liquid crystal display panel to reach the clearing point of the liquid crystal.

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Abstract

一种显示面板和显示装置，该显示面板(100)包括:衬底基板(101),包括显示区域(105)和围绕显示区域(105)的周边区域(106)；层叠设置在衬底基板(101)上的第一公共电极总线(102)、第二公共电极总线(103)和导电连接层(104)，其中，第一公共电极总线(102)包括主体部(102a)和从主体部的端部(102a)向远离显示区域(105)的一侧延伸出的分支部(102b),主体部(102a)沿着第一方向(X)延伸，分支部(102b)的至少和主体部(102a)连接的部分沿着第二方向(Y)延伸，第一方向(X)和第二方向(Y)相交；第二公共电极总线(103)沿着第二方向(Y)向远离显示区域(105)的一侧延伸，第二公共电极总线(103)的第一端部(103a)和主体部的端部(102a')、分支部(102b)正对；在周边区域(106)，导电连接层(104)通过第一过孔结构(107)和第一公共电极总线(102)的分支部(102b)电连接，导电连接层(104)通过第二过孔结构(108)和第二公共电极总线(103)的第一端部(103a)电连接，该显示面板(100)可以使得第一过孔结构和第二过孔结构的数量增加，减小电路结构中的电阻，以避免出现第一过孔结构和第二过孔结构被烧毁，导致显示面板的产品良率降低，显示面板的寿命缩短的问题。

Description

显示面板和显示装置 技术领域
本公开的实施例涉及一种显示面板和显示装置。
背景技术
液晶显示器(Liquid Crystal Display，简称LCD)是最广泛使用的平板显示器之一，它具有轻薄、色域高、功耗低和便携性强等优点，目前已被广泛应用于电视机、显示器、笔记本电脑等显示产品中。液晶显示面板是非发光图像显示器件之一，液晶显示面板包括彩膜基板、其上设置有薄膜晶体管的阵列基板和通过在彩膜基板和阵列基板之间注入形成的液晶层。由于液晶层中的液晶分子具有各向异性，所以液晶显示面板可以利用透光率的差异来显示图像。
液晶显示面板包括液晶板和驱动液晶板的驱动电路，液晶板上的像素单元成矩阵排列，且液晶板上的栅线与数据线交叉限定像素区域，该液晶盒设置在像素区域中。该液晶板中还设置有向各个液晶盒提供电场的公共电极和像素电极。每个像素电极通过起开关元件作用的薄膜晶体管的源极或者漏极引出线与数据线相连，开关晶体管的栅极引出线与栅线相连。驱动电路包括驱动栅线的栅极驱动器和驱动数据线的数据驱动器，和驱动公共电极的公共电压发生器。栅极驱动器依次向栅线输送栅极信号，以便依次驱动液晶板上的液晶盒。从而液晶显示面板可以根据响应数据电压信号后施加在像素电极和公共电极之间的电场来调整每个液晶盒的透光率，进而进行图像显示。
发明内容
本公开至少一实施例提供一种显示面板和显示装置，在该显示面板中，在周边区域导电连接层通过第一过孔结构和第一公共电极总线的分支部连接，导电连接层通过第二过孔结构和第二公共电极总线的第一端部电连接，该显示面板的结构设计可以使得第一过孔结构和第二过孔结构的数量增加，减小电路结构中的电阻，以避免出现第一过孔结构和第二过孔结构被烧毁，导致显示面板的产品良率降低，显示面板的寿命较短的问题。而且当该显示面板为液晶显示面板时，将第一过孔结构和第二过孔结构设 置得远离显示区域，还可以避免出现从第一过孔结构和第二过孔结构散发的热量使得液晶显示面板的显示区域中的液晶层的温度升高以达到液晶的清亮点的问题。
本公开至少一实施例提供一种显示面板，该显示面板包括：衬底基板，包括显示区域和围绕所述显示区域的周边区域；层叠设置在所述衬底基板上的第一公共电极总线、第二公共电极总线和导电连接层，其中，所述第一公共电极总线包括主体部和从所述主体部的端部向远离所述显示区域的一侧延伸出的分支部，所述主体部沿着第一方向延伸，所述分支部的至少和所述主体部连接的部分沿着第二方向延伸，所述第一方向和所述第二方向相交；所述第二公共电极总线沿着所述第二方向向远离所述显示区域的一侧延伸，所述第二公共电极总线的第一端部和所述主体部的端部、所述分支部正对；在所述周边区域，所述导电连接层通过第一过孔结构和所述第一公共电极总线的所述分支部电连接，所述导电连接层通过第二过孔结构和所述第二公共电极总线的所述第一端部电连接。
例如，在本公开至少一实施例提供的显示面板中，在平行于所述衬底基板的主表面的平面上，所述分支部至少包括远离所述显示区域的第一弯折部，所述第一过孔结构在所述衬底基板上的正投影和所述第一弯折部在所述衬底基板上的正投影至少部分交叠。
例如，在本公开至少一实施例提供的显示面板中，在平行于所述衬底基板的主表面的平面上，所述第一端部延伸至所述第一弯折部限定的开口区域中，且所述第二过孔结构在所述衬底基板上的正投影和所述第一端部在所述衬底基板上的正投影至少部分交叠。
例如，在本公开至少一实施例提供的显示面板中，所述第一弯折部包括沿所述第二方向延伸的第一子弯折部分和沿所述第一方向向靠近所述第二公共电极总线的一侧延伸的第二子弯折部分，所述第二公共电极总线的延伸方向平行于所述第二方向，所述第一子弯折部分在所述衬底基板上的正投影和所述第一过孔结构在所述衬底基板上的正投影具有交叠部分，且所述第二子弯折部分在所述衬底基板上的正投影和所述第一过孔结构在所述衬底基板上的正投影具有交叠部分。
例如，在本公开至少一实施例提供的显示面板中，所述第一弯折部包括沿所述第二方向延伸的第一子弯折部分和沿所述第一方向向靠近所述第 二公共电极总线的一侧延伸的第二子弯折部分，所述第二公共电极总线的延伸方向平行于所述第二方向，所述第一子弯折部分在所述衬底基板上的正投影和所述第一过孔结构在所述衬底基板上的正投影具有交叠部分，且所述第二子弯折部分在所述衬底基板上的正投影和所述第一过孔结构在所述衬底基板上的正投影不具有交叠部分。
例如，在本公开至少一实施例提供的显示面板中，所述第一弯折部包括沿所述第二方向延伸的第一子弯折部分和沿所述第一方向向靠近所述第二公共电极总线的一侧延伸的第二子弯折部分，所述第二公共电极总线的延伸方向平行于所述第二方向，所述第一子弯折部分在所述衬底基板上的正投影和所述第一过孔结构在所述衬底基板上的正投影不具有交叠部分，且所述第二子弯折部分在所述衬底基板上的正投影和所述第一过孔结构在所述衬底基板上的正投影具有交叠部分。
例如，在本公开至少一实施例提供的显示面板中，在平行于所述衬底基板的主表面的平面上，所述分支部还包括远离所述显示区域的第二弯折部，所述第二弯折部包括沿所述第二方向延伸的第三子弯折部分和沿所述第一方向延伸的第四子弯折部分，所述第二子弯折部分和所述第四子弯折部分连接以使所述第一弯折部和所述第二弯折部的整体形状为“U”型，且所述第二公共电极总线延伸至所述“U”型的开口中。
例如，在本公开至少一实施例提供的显示面板中，所述第三子弯折部分在所述衬底基板上的正投影和所述第一过孔结构在所述衬底基板上的正投影具有交叠部分，且所述第四子弯折部分在所述衬底基板上的正投影和所述第一过孔结构在所述衬底基板上的正投影具有交叠部分。
例如，在本公开至少一实施例提供的显示面板中，所述第三子弯折部分在所述衬底基板上的正投影和所述第一过孔结构在所述衬底基板上的正投影具有交叠部分，且所述第四子弯折部分在所述衬底基板上的正投影和所述第一过孔结构在所述衬底基板上的正投影不具有交叠部分。
例如，在本公开至少一实施例提供的显示面板中，在平行于所述衬底基板的主表面的平面上，所述第一公共电极总线的所述主体部在平行于所述第一方向的方向上设置，所述主体部上设置有第三过孔结构，且所述主体部通过所述第三过孔结构和所述导电连接层电连接。
例如，在本公开至少一实施例提供的显示面板中，所述第一过孔结构 和所述第二过孔结构与所述显示区域的最小距离均大于500微米。
例如，在本公开至少一实施例提供的显示面板中，所述第一过孔结构配置为多个，所述第二过孔结构配置为多个，且所述第一过孔结构和所述第二过孔结构的总个数大于或者等于150。
例如，在本公开至少一实施例提供的显示面板中，所述第一过孔结构和所述第二过孔结构呈矩阵排列，所述第一方向为行方向，所述第二方向为列方向，沿着所述第一方向在一行中所述第一过孔结构和所述第二过孔结构的数量之和大于15，沿着所述第二方向在一列中所述第一过孔结构和所述第二过孔结构的数量之和大于10，且沿着所述第一方向在一行中所述第一过孔结构和所述第二过孔结构的数量之和大于沿着所述第二方向在一列中所述第一过孔结构和所述第二过孔结构的数量之和。
例如，在本公开至少一实施例提供的显示面板中，所述第一过孔结构和所述第二过孔结构呈矩阵排列，所述第一方向为行方向，所述第二方向为列方向，沿着所述第一方向在一行中所述第一过孔结构和所述第二过孔结构的数量之和大于10，沿着所述第二方向在一列中所述第一过孔结构和所述第二过孔结构的数量之和大于15，且沿着所述第一方向在一行中所述第一过孔结构和所述第二过孔结构的数量之和小于沿着所述第二方向在一列中所述第一过孔结构和所述第二过孔结构的数量之和。
例如，在本公开至少一实施例提供的显示面板中，所述第一过孔结构和所述第二过孔结构在平行于所述衬底基板的主板面上的最大尺寸的范围为4微米～6微米。
例如，本公开至少一实施例提供的显示面板还包括：设置在所述衬底基板上且在所述显示区域的薄膜晶体管和第一电极，其中，所述薄膜晶体管包括层叠设置的栅极、有源层和源漏电极层，所述源漏电极层包括相对设置的源极和漏极，所述第一公共电极总线和所述栅极同层设置，所述第二公共电极总线和所述源极、所述漏极同层设置，所述导电连接层和所述第一电极同层设置且相互间隔，所述第一电极通过第四过孔结构和所述漏极电连接。
例如，在本公开至少一实施例提供的显示面板中，在所述栅极的远离所述衬底基板的一侧设置有栅绝缘层，在所述源漏电极层的远离所述衬底基板的一侧设置有钝化层，所述第一过孔结构依次贯穿所述钝化层和所述 栅绝缘层，所述第二过孔结构和所述第四过孔结构均贯穿所述钝化层。
例如，在本公开至少一实施例提供的显示面板中，在平行于所述衬底基板的主表面的平面上，且在一个所述显示面板中，所述第二公共电极总线配置为两条，且两条所述第二公共电极总线沿着所述第一方向相对设置在所述第一公共电极总线的所述主体部的两侧；所述显示面板还包括和所述第一公共电极总线在所述第二方向上相对设置的第三公共电极总线，所述第三公共电极总线和所述第一公共电极总线的所述主体部平行，且所述第三公共电极总线和所述第一公共电极总线同层设置，两条所述第二公共电极总线、所述第一公共电极总线和所述第三公共电极总线围设在所述显示区域的四周；两条所述第二公共电极总线分别包括在所述第一方向上远离所述第一公共电极总线的第二端部和第三端部，所述导电连接层通过第五过孔结构和所述第二端部以及所述第三端部电连接；所述第三公共电极总线包括和所述第二端部相对的第四端部以及和所述第三端部相对的第五端部，所述导电连接层通过第六过孔结构和所述第四端部以及所述第五端部电连接。
例如，在本公开至少一实施例提供的显示面板中，所述第三公共电极总线的在所述第四端部和所述第五端部之间的部分通过第七过孔结构和所述导电连接层电连接。
本公开至少一实施例还提供一种显示装置，该显示装置包括上述任一示例中的显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示面板的平面结构示意图；
图2为本公开至少一实施例提供的一种显示面板的平面结构示意图；
图3为本公开至少一实施例提供的一种第一弯折部放大后的平面结构示意图；
图4为本公开至少一实施例提供的再一种第一弯折部放大后的平面结构示意图；
图5为本公开至少一实施例提供的又一种第一弯折部放大后的平面结构示意图；
图6为本公开至少一实施例提供的一种分支部放大后的平面结构示意图；
图7为本公开至少一实施例提供的再一种分支部放大后的平面结构示意图；
图8为本公开至少一实施例提供的又一种分支部放大后的平面结构示意图；
图9为本公开至少一实施例提供的一种第一过孔结构和第二过孔结构处的电路图；以及
图10为本公开至少一实施例提供的一种显示面板的截面结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
随着平板显示技术的不断发展，显示器件已经成功应用于笔记本电脑、监控仪、电视、广告屏等显示设备中。薄膜晶体管显示器是多种显示器的一种，薄膜晶体管显示器上的每一个像素点都是由集成在其后的场效应薄膜晶体管来驱动的，从而可以获取高亮度高对比度显示屏幕的信息，由于GOA 驱动电路可以代替栅驱动覆晶薄膜(Gate Chip On Film，Gate COF)，GOA驱动电路的制造成本比栅驱动覆晶薄膜的制造成本更低，从而使得采用GOA驱动电路可以节约生产成本，使得可以在降低生产成本的基础上该显示器件在显示领域可以被大量生产和使用。
例如，显示面板通常包括多个电子元器件，该电子元器件包括薄膜晶体管、信号线、电极图案等。这些电子元器件的结构又会分布在不同的层结构中。在显示面板的实际制备过程中，基于走线设计、版图排布等需求，常常需要将位于不同层的导电图案进行电连接，以满足产品的需求。
例如，在显示面板的设计方案中，例如，在电视机、笔记本电脑、监控仪、广告屏等大尺寸显示面板中，通常是位于不同层的导电图案分别通过多个过孔结构与电连接层连接，即位于不同层的两个导电图案分别通过对应的过孔结构与电连接层进行电连接，从而实现位于不同层的导电图案之间的电连接。显示面板也广泛应用于电竞显示器等小尺寸显示面板中，随着电竞市场的不断扩大，和大尺寸显示面板类似，小尺寸显示面板中位于不同层的两个导电图案也是分别通过对应的过孔结构与电连接层进行电连接的，专业电竞显示器对超高刷新频率的游戏产品的需求越来越高，刷新频率从60Hz发展到120Hz、144Hz、165Hz、240Hz或者480Hz等高刷频率，频率越高产生的热量越大。
本公开的发明人注意到，在目前的中大尺寸显示面板和小尺寸显示面板中，电连接层和导电图案连接处的电阻值均较大，即在过孔结构处的电阻较大，耐电流值较小，在经过相同电流的情况下过孔结构处散发的热量越多，产生的热量越高。尤其在液晶显示面板中，不仅过孔结构处的电阻大，过孔结构距离显示区域也较近，从而会使得位于显示区域中的液晶层的温度升高，当液晶层的温度超过液晶分子的清亮点时，就会使得液晶层变成透明的状态，从而会影响显示区域的显示，以使得形成的显示画面不良。需要说明的是，上述显示区域是指对应有效像素的区域，在一些实施例中，显示面板的像素包括有效像素和虚拟像素(dummy pixel)，显示区域是对应有效像素的区域，过孔结构与显示区域的距离是指过孔结构与有效像素的最小距离。在一些情况下还容易出现过孔结构被烧毁，导致液晶显示面板的产品良率降低，液晶显示面板的寿命较短的问题。例如，图1为一种显示面板的平面结构示意图，如图1所示，在显示区域011的右侧设置有竖向公共电极总线012， 在显示区域011的下方设置有横向公共电极总线013。在横向公共电极总线013的上方设置有第一过孔014，在竖向公共电极总线012的上方设置有第二过孔015，在第一过孔014和第二过孔015的上方设置有导电连接层016。该导电连接层016通过第一过孔014和横向公共电极总线013电连接，该导电连接层016通过第二过孔015和竖向公共电极总线012电连接，从而使得横向公共电极总线013和竖向公共电极总线012电连接，但是，在图1所示的结构中，竖向公共电极总线012和横向公共电极总线013正对的区域较小，从而使得可以布局第一过孔014和第二过孔015的区域较小，以使得第一过孔014和第二过孔015的数量较少，从而使得并联的电路较少，整个电路中的电阻较大，进而使得第一过孔014和第二过孔015处释放的热量较多，导致容易出现第一过孔014和第二过孔015被烧毁，显示面板的产品良率降低，显示面板的寿命较短的问题。当该显示面板为液晶显示面板时，该第一过孔014和第二过孔015距离显示区域011较近，还容易出现从第一过孔014和第二过孔015散发的热量使得液晶显示面板的显示区域011中的液晶层的温度升高以达到液晶的清亮点的问题，因此，可以考虑将第一过孔014和第二过孔015的数量设置的更多，第一过孔014和第二过孔015设置得远离显示区域011，以减少第一过孔014和第二过孔015散发的热量对显示区域011的影响。
本公开至少一实施例提供一种显示面板，该显示面板包括：衬底基板和层叠设置在衬底基板上的第一公共电极总线、第二公共电极总线和导电连接层。该衬底基板包括显示区域和围绕该显示区域的周边区域，该第一公共电极总线包括主体部和从主体部的端部向远离显示区域的一侧延伸出的分支部，该主体部沿着第一方向延伸，分支部的至少和主体部连接的部分沿着第二方向延伸，且第一方向和第二方向相交。第二公共电极总线沿着第二方向向远离显示区域的一侧延伸，第二公共电极总线的第一端部和主体部的端部、分支部正对。在周边区域，导电连接层通过第一过孔结构和第一公共电极总线的分支部连接，导电连接层通过第二过孔结构和第二公共电极总线的第一端部电连接，该显示面板的结构设计可以使得第一过孔结构和第二过孔结构的数量增加，减小电路结构中的电阻，以避免出现第一过孔结构和第二过孔结构被烧毁，导致显示面板的产品良率降低，显示面板的寿命较短的问题。而且当该显示面板为液晶显示面板时，将第一过孔结构和第二过孔结构 设置得远离显示区域，还可以避免出现从第一过孔结构和第二过孔结构散发的热量使得液晶显示面板的显示区域中的液晶层的温度升高以达到液晶的清亮点的问题。
例如，图2为本公开至少一实施例提供的一种显示面板的平面结构示意图，该显示面板100包括：衬底基板101和层叠设置在衬底基板101上的第一公共电极总线102、第二公共电极总线103和导电连接层104。该衬底基板101包括显示区域105和围绕该显示区域105的周边区域106，该第一公共电极总线102包括主体部102a和从主体部的端部102a’向远离显示区域105的一侧延伸出的分支部102b。例如，该主体部102a沿着第一方向X延伸，分支部102b至少包括长条形部分，分支部102b的至少和主体部102a连接的部分沿着第二方向Y延伸，且第一方向X和第二方向Y相交。
例如，在一个示例中，如图2所示，该分支部102b包括两个部分，该两个部分形成一个台阶状，第二公共电极总线103的第一端部103a延伸至和台阶的横向平台正对，该分支部102b的和主体部102a连接的部分沿着第二方向Y延伸以形成台阶状的竖向部分。当然，本公开的实施例不限于此，还可以是该分支部102b仅包括和主体部102a连接的且沿着第二方向Y延伸的长条形部分，或者，该分支部102b还可以包括多个台阶状的部分。
例如，在一个示例中，如图2所示，该第二公共电极总线103沿着第二方向Y向远离显示区域105的一侧延伸，第二公共电极总线103的第一端部103a和主体部的端部102a’、分支部102b均正对。在周边区域106，导电连接层104通过第一过孔结构107和第一公共电极总线102的分支部102b连接，导电连接层104通过第二过孔结构108和第二公共电极总线103的第一端部103a电连接。例如，该第二过孔结构108仅设置在第一端部103a的和分支部102b对应的位置处。需要说明的是，该第一端部103a的和主体部的端部102a’对应的位置也设置有过孔结构，该位置处的过孔结构的尺寸、形状、分布密度等可以和第二过孔结构108不同。例如，该第一端部103a的和主体部的端部102a’对应的位置的过孔结构在平行于衬底基板101的主表面上的最大尺寸大于第二过孔结构108的最大尺寸，分布密度小于第二过孔结构108的分布密度。
例如，在图2所示的结构中，该显示面板100还包括和第一公共电极总线102在第二方向Y上相对设置的第三公共电极总线126，该第三公共电极 总线126和第一公共电极总线102的主体部102a平行，且第三公共电极总线126和第一公共电极总线102同层设置。在第一公共电极总线102和第三公共电极总线126的左右两侧设置有第二公共电极总线103，该第一公共电极总线102、第三公共电极总线126和两条第二公共电极总线103均位于周边区域106，两条第二公共电极总线103、第一公共电极总线102和第三公共电极总线126围设在显示区域105的四周形成环绕显示区域105的结构。在第三公共电极总线126的远离显示区域105的一侧，且沿着从靠近显示区域105的位置向远离显示区域105的位置的方向依次设置有防静电结构110和静电导出线111。
例如，如图2所示，在第一公共电极总线102的远离显示区域105的一侧，且沿着从靠近显示区域105的位置向远离显示区域105的位置的方向依次设置有防静电结构110和扇出区109，该扇出区109配置为向显示区域施加触控信号和/或显示信号等。例如，仅在第一公共电极总线102的主体部的两个端部102a’的位置处设置有向远离显示区域105的一侧延伸的分支部107，该分支部107是电流的汇集处，该处产生的热量很大，所以需要将分支部107设置成远离显示区域105。在第三公共电极总线126的端部均未设置分支部107。
例如，如图2所示，在左侧的第二公共电极总线103的远离显示区域105的一侧设置有栅极驱动电路114，在右侧的第二公共电极总线103的远离显示区域105的一侧也设置有栅极驱动电路114，该栅极驱动电路114可以给栅线施加扫描信号。该显示面板100还包括从显示区域105中延伸出的公共电极线115，该公共电极线115和第二公共电极总线103以及导电连接层104电连接。
例如，该显示面板100的结构设计可以将分支部107设置成更远离显示区域105，从而使得分支部107上有更大的区域可以设置更多的过孔结构，使得第一过孔结构107和第二过孔结构108的数量增加，以减小电路结构中的电阻，以避免出现第一过孔结构107和第二过孔结构108被烧毁，导致显示面板100的产品良率降低，显示面板的寿命较短的问题。而且当该显示面板为液晶显示面板时，将第一过孔结构107和第二过孔结构108设置得远离显示区域105，还可以避免出现从第一过孔结构107和第二过孔结构108散发的热量使得液晶显示面板的显示区域中的液晶层的温度升高以达到液晶 的清亮点的问题。
例如，如图2所示，该第一过孔结构107和第二过孔结构108与显示区域105的最小距离均大于500微米。在一些示例中，可以是该第一过孔结构107与显示区域105之间的最小距离和第二过孔结构108与显示区域105之间的最小距离相等，也可以是第一过孔结构107与显示区域105之间的最小距离大于第二过孔结构108与显示区域105之间的最小距离，还可以是第一过孔结构107与显示区域105之间的最小距离小于第二过孔结构108与显示区域105之间的最小距离，本公开的实施例对此不作限定。在图2所示的结构中，第一过孔结构107与显示区域105之间的最小距离D小于第二过孔结构108与显示区域105之间的最小距离，且该第一过孔结构107与显示区域105之间的最小距离D大于500微米，该距离的设置可以避免出现从第一过孔结构107和第二过孔结构108散发的热量使得液晶显示面板的显示区域中的液晶层的温度升高以达到液晶的清亮点导致显示质量下降的问题。
例如，如图2所示，在平行于衬底基板101的主表面的平面上，分支部107至少包括远离显示区域105的第一弯折部112，第一过孔结构107在衬底基板101上的正投影和第一弯折部112在衬底基板101上的正投影至少部分交叠。在图2所示的结构中，该分支部107整体的结构即为第一弯折部112，不包括其他的结构，当然，该分支部107也可以包括其他的结构，例如，该分支部107还可以包括从第一弯折部112向远离显示区域105的一侧延伸的更多的弯折部或者长条形部分，本公开的实施例不限于此。
例如，如图2所示，在平行于衬底基板101的主表面的平面上，该第一端部103a延伸至第一弯折部112限定的开口区域113中，且该第二过孔结构108在衬底基板101上的正投影和第一端部103a在衬底基板101上的正投影至少部分交叠，即该第一端部103a在衬底基板101上的正投影可以和全部的第二过孔结构108在衬底基板101上的正投影交叠，也可以和部分的第二过孔结构108在衬底基板101上的正投影交叠。
例如，如图2所示，在平行于衬底基板101的主表面的平面上，该第一公共电极总线102的主体部102a在平行于第一方向X的方向上设置，即在图2中该第一公共电极总线102的主体部102a横向延伸。主体部102a上设置有多个第三过孔结构116，且该主体部102a通过该多个第三过孔结构116和导电连接层104电连接。
需要说明的是，该主体部102a上具有多个并联的支路，尽管该多个第三过孔结构116距离显示区域105的距离较近，但是多个并联的支路的电阻很小，且电流不在此处汇集，从而产生的热量很少，不会对显示区域的显示造成影响。
例如，图3为本公开至少一实施例提供的一种第一弯折部放大后的平面结构示意图，如图3所示，第一弯折部112包括沿第二方向Y延伸的第一子弯折部分112a和沿第一方向X向靠近第二公共电极总线103的一侧延伸的第二子弯折部分112b，该第一子弯折部分112a和第二子弯折部分112b构成的整体的平面形状为“L”型。该第二公共电极总线103的延伸方向平行于第二方向Y，第一子弯折部分112a在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影具有交叠部分，且第二子弯折部分112b在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影具有交叠部分，该第一过孔结构107排布的整体形状也呈“L”型。在图3所示的结构中，该第一子弯折部分112a的一部分在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影相交叠，该第二子弯折部分112b的一部分在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影相交叠。第一端部103a的一部分在衬底基板101上的正投影和第二过孔结构108在衬底基板101上的正投影相交叠。该第一弯折部112的结构简单，且可以满足多个第一过孔结构107和多个第二过孔结构108数量的需求，使得工艺过程简单。此外，该种设计还可以使得在第一子弯折部分112a和第二子弯折部分112b上均具有第一过孔结构107，使得和第二过孔结构108对应的第一过孔结构107尽量均匀分布，以使得第二公共电极总线103和第一公共电极总线102的连接更加稳定。
例如，尽管在图3所示的结构中，该导电连接层104在衬底基板101上的正投影和部分第二公共电极总线103在衬底基板101上的正投影相交叠，但是在实际的产品中，该导电连接层104是围绕着显示区域105的四周设置的，即导电连接层104在衬底基板101上的正投影覆盖第一公共电极总线102在衬底基板101上的正投影、第三公共电极总线126在衬底基板101上的正投影和两条第二公共电极总线103在衬底基板101上的正投影。
例如，图4为本公开至少一实施例提供的再一种第一弯折部放大后的平面结构示意图，如图4所示，该第一弯折部112包括沿第二方向Y延伸的第 一子弯折部分112a和沿第一方向X向靠近第二公共电极总线103的一侧延伸的第二子弯折部分112b，该第一子弯折部分112a和第二子弯折部分112b构成的整体的平面形状为“L”型。该第二公共电极总线103的延伸方向平行于第二方向Y，第一子弯折部分112a在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影具有交叠部分，且第二子弯折部分112b在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影不具有交叠部分，该第一过孔结构107排布的整体形状也呈直线型，该第一过孔结构107排布的直线型和第二过孔结构108排布的直线型正对。该第一过孔结构107排布的直线型和第二过孔结构108排布的直线型，在满足多个第一过孔结构107和多个第二过孔结构108数量的需求的基础上，还可以使得形成第一过孔结构107的工艺过程变得简单，且使得第二子弯折部分112b在第二方向Y的宽度可以设置得尽量小，从而可以减小下边框的宽度，使得下边框的宽度更窄。
例如，尽管在图4所示的结构中，该导电连接层104在衬底基板101上的正投影和部分第二公共电极总线103在衬底基板101上的正投影相交叠，但是在实际的产品中，该导电连接层104是围绕着显示区域105的四周设置的，即导电连接层104在衬底基板101上的正投影覆盖第一公共电极总线102在衬底基板101上的正投影、第三公共电极总线126在衬底基板101上的正投影和两条第二公共电极总线103在衬底基板101上的正投影。
例如，图5为本公开至少一实施例提供的又一种第一弯折部放大后的平面结构示意图，如图5所示，该第一弯折部112包括沿第二方向Y延伸的第一子弯折部分112a和沿第一方向X向靠近第二公共电极总线103的一侧延伸的第二子弯折部分112b，该第一子弯折部分112a和第二子弯折部分112b构成的整体的平面形状为“L”型。该第二公共电极总线103的延伸方向平行于第二方向Y，该第一子弯折部分112a在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影不具有交叠部分，且第二子弯折部分112b在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影具有交叠部分。该第一弯折部112的结构简单，且可以满足多个第一过孔结构107和多个第二过孔结构108数量的需求的基础上，使得工艺过程变得简单。此外，该种设计还可以使得仅在第二子弯折部分112b上具有第一过孔结构107，从而可以增大第一过孔结构107与显示区域105之间的 距离，进而可以减小从第一过孔结构107散发的热量对显示区域105的影响。
例如，尽管在图5所示的结构中，该导电连接层104在衬底基板101上的正投影和部分第二公共电极总线103在衬底基板101上的正投影相交叠，但是在实际的产品中，该导电连接层104是围绕着显示区域105的四周设置的，即导电连接层104在衬底基板101上的正投影覆盖第一公共电极总线102在衬底基板101上的正投影、第三公共电极总线126在衬底基板101上的正投影和两条第二公共电极总线103在衬底基板101上的正投影。
例如，图6为本公开至少一实施例提供的一种分支部放大后的平面结构示意图，如图6所示，在平行于衬底基板101的主表面的平面上，分支部107包括远离显示区域105的第一弯折部112和远离显示区域105的第二弯折部113，该第一弯折部112包括沿第二方向Y延伸的第一子弯折部分112a和沿第一方向X向靠近第二公共电极总线103的一侧延伸的第二子弯折部分112b，该第一子弯折部分112a和第二子弯折部分112b构成的整体的平面形状为“L”型。该第二弯折部113包括沿第二方向Y延伸的第三子弯折部分113a和沿第一方向X延伸的第四子弯折部分113b，该第二子弯折部分112b和第四子弯折部分113b连接以使第一弯折部112和第二弯折部113的整体形状为“U”型，该第二公共电极总线103的延伸方向平行于第二方向Y，且第二公共电极总线103延伸至该“U”型的开口中，需要说明的是，图6中示出的第二子弯折部分112b和第四子弯折部分113b的边缘为直角边，尽管最终形成的分支部的形状不是严格意义上的“U”型，但也可以等效成“U”型，在另一个示例中，该第二子弯折部分112b和第四子弯折部分113b的边缘也可以为弧形边，以使得最终形成的分支部的截面形状为“U”型。
例如，如图6所示，该第一子弯折部分112a的一部分在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影相交叠，该第二子弯折部分112b的一部分在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影相交叠，该第三子弯折部分113a在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影具有交叠部分，且第四子弯折部分113b在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影具有交叠部分，从而使得第一过孔结构107的排布形状也为“U”型，以使得第二公共电极总线103的第一端部103a与第一公共电极总线102连接的位置尽量的多。
例如，如图6所示，第二公共电极总线103的第一端部103a的一部分在衬底基板101上的正投影和第二过孔结构108在衬底基板101上的正投影相交叠。该结构使得在“U”型分支部的第一子弯折部分112a和第三子弯折部分113a对应的位置处均设置有第一过孔结构107。第一子弯折部分112a通过第一过孔结构107和导电连接层104与第二公共电极总线103的第一端部103a电连接，第三子弯折部分113a通过第一过孔结构107和导电连接层104与第二公共电极总线103的第一端部103a电连接，这样可以使得第二公共电极总线103的第一端部103a既可以和第一子弯折部分112a电连接，又可以和第三子弯折部分113a电连接，从而使得形成的并联电路更多，可以进一步减小电阻，以减少发散的热量。该结构使得在“U”型的底部的第二子弯折部分112b和第四子弯折部分113b对应的位置处均设置有第一过孔结构107。第二子弯折部分112b通过第一过孔结构107和导电连接层104与第二公共电极总线103的第一端部103a电连接，第四子弯折部分113b通过第一过孔结构107和导电连接层104与第二公共电极总线103的第一端部103a电连接，这样可以使得第二公共电极总线103的第一端部103a还可以和第二子弯折部分112b和第四子弯折部分113b电连接，从而使得形成的并联电路更多，可以进一步减小电阻，以进一步减少发散的热量。
例如，尽管在图6所示的结构中，该导电连接层104在衬底基板101上的正投影和部分第二公共电极总线103在衬底基板101上的正投影相交叠，但是在实际的产品中，该导电连接层104是围绕着显示区域105的四周设置的，即导电连接层104在衬底基板101上的正投影覆盖第一公共电极总线102在衬底基板101上的正投影、第三公共电极总线126在衬底基板101上的正投影和两条第二公共电极总线103在衬底基板101上的正投影。例如，图7为本公开至少一实施例提供的再一种分支部放大后的平面结构示意图，如图7所示，该第一子弯折部分112a的一部分在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影相交叠，该第二子弯折部分112b的一部分在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影相交叠，该第三子弯折部分113a在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影具有交叠部分，且第四子弯折部分113b在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影不具有交叠部分。第一子弯折部分112a通过第一过孔结构107和导电连 接层104与第二公共电极总线103的第一端部103a电连接，第三子弯折部分113a通过第一过孔结构107和导电连接层104与第二公共电极总线103的第一端部103a电连接，这样可以使得第二公共电极总线103的第一端部103a既可以和第一子弯折部分112a电连接，又可以和第三子弯折部分113a电连接，从而使得形成的并联电路更多，可以进一步减小电阻，以减少发散的热量。该结构使得在“U”型的底部的第二子弯折部分112b对应的位置处也设置有第一过孔结构107。第二子弯折部分112b通过第一过孔结构107和导电连接层104与第二公共电极总线103的第一端部103a电连接，但是，第四子弯折部分113b上未设置第一过孔结构107，这样可以使得“U”型结构的与第二公共电极总线103的第一端部103a正对的位置处均设置有第一过孔结构107，还可以在满足第一过孔结构107数量的基础上，尽量在与第二公共电极总线103的第一端部103a非正对的位置处，即第四子弯折部分113b上不设置第一过孔结构107，以简化工艺过程。
例如，尽管在图7所示的结构中，该导电连接层104在衬底基板101上的正投影和部分第二公共电极总线103在衬底基板101上的正投影相交叠，但是在实际的产品中，该导电连接层104是围绕着显示区域105的四周设置的，即导电连接层104在衬底基板101上的正投影覆盖第一公共电极总线102在衬底基板101上的正投影、第三公共电极总线126在衬底基板101上的正投影和两条第二公共电极总线103在衬底基板101上的正投影。
例如，图8为本公开至少一实施例提供的又一种分支部放大后的平面结构示意图，如图8所示，该第一子弯折部分112a的一部分在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影不具有交叠部分，该第二子弯折部分112b在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影不具有交叠部分，该第三子弯折部分113a在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影具有交叠部分，且第四子弯折部分113b在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影具有交叠部分。第三子弯折部分113a通过第一过孔结构107和导电连接层104与第二公共电极总线103的第一端部103a电连接，第四子弯折部分113b通过第一过孔结构107和导电连接层104与第二公共电极总线103的第一端部103a电连接，这样可以使得第二公共电极总线103的第一端部103a既可以和第三子弯折部分113a电连接，又可 以和第四子弯折部分113b电连接，从而使得形成的并联电路更多，可以进一步减小电阻，以减少发散的热量，且第三子弯折部分113a和第四子弯折部分113b距离显示区域105更远，第一过孔结构107设置在第三子弯折部分113a和第四子弯折部分113b上可以进一步减小从第一过孔结构107散发的热量对显示区域105的影响。
例如，尽管在图8所示的结构中，该导电连接层104在衬底基板101上的正投影和部分第二公共电极总线103在衬底基板101上的正投影相交叠，但是在实际的产品中，该导电连接层104是围绕着显示区域105的四周设置的，即导电连接层104在衬底基板101上的正投影覆盖第一公共电极总线102在衬底基板101上的正投影、第三公共电极总线126在衬底基板101上的正投影和两条第二公共电极总线103在衬底基板101上的正投影。
需要说明的是，在其他的示例中，也可以是该第一子弯折部分112a的一部分在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影具有交叠部分，该第二子弯折部分112b的一部分在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影不具有交叠部分，该第三子弯折部分113a在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影具有交叠部分，且第四子弯折部分113b在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影不具有交叠部分；还可以是该第一子弯折部分112a的一部分在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影不具有交叠部分，该第二子弯折部分112b的一部分在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影具有交叠部分，该第三子弯折部分113a在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影具有交叠部分，且第四子弯折部分113b在衬底基板101上的正投影和第一过孔结构107在衬底基板101上的正投影不具有交叠部分，本公开的实施例对此不作限定。
例如，结合图2～8所示，该第一过孔结构107配置为多个，第二过孔结构108配置为多个，且第一过孔结构107和第二过孔结构108的总个数大于或者等于150，该种数量设计的第一过孔结构107和第二过孔结构108可以使得专业电竞显示器在240Hz或者480Hz等高刷频率时产生的热量也不会影响显示面板的正常显示。
需要说明的是，在图2～图8所示的结构中仅示出了一部分第一过孔结构 107和第二过孔结构108，有大量的第一过孔结构107和第二过孔结构108省略了。
例如，结合图2～图8所示，第一过孔结构107和第二过孔结构108呈矩阵排列，该第一方向X为行方向，第二方向Y为列方向，沿着第一方向X在一行中第一过孔结构107和第二过孔结构108的数量之和大于等于15，沿着第二方向Y在一列中第一过孔结构107和第二过孔结构108的数量之和大于等于10，且沿着第一方向X在一行中第一过孔结构107和第二过孔结构108的数量之和大于沿着第二方向Y在一列中第一过孔结构107和第二过孔结构108的数量之和。例如，在一个示例中，每一行中第一过孔结构107和第二过孔结构108的数量之和大于等于每一列中第一过孔结构107和第二过孔结构108的数量之和的1.5倍，这样可以使得第一过孔结构107和第二过孔结构108的数量之和达到150，且第一过孔结构107和第二过孔结构108均匀排布，使得并联的电路的的电阻最小，从而使得散发的热量最小。此外，该种设计还可以使得在第二方向Y上导电连接层104的宽度可以设计得更窄，使得导电连接层104的下部最远离显示区域105的边与显示区域105之间的距离缩小，从而可以减小下边框的宽度，使得下边框的宽度更窄。
例如，结合图2～图8所示，第一过孔结构107和第二过孔结构108呈矩阵排列，该第一方向X为行方向，第二方向Y为列方向，沿着第一方向X在一行中第一过孔结构107和第二过孔结构108的数量之和大于等于10，沿着第二方向Y在一列中第一过孔结构107和第二过孔结构108的数量之和大于等于15，且沿着第一方向X在一行中第一过孔结构107和第二过孔结构108的数量之和小于沿着第二方向Y在一列中第一过孔结构107和第二过孔结构108的数量之和。例如，在一个示例中，每一列中第一过孔结构107和第二过孔结构108的数量之和大于等于每一行中第一过孔结构107和第二过孔结构108的数量之和的1.5倍，这样可以使得第一过孔结构107和第二过孔结构108的数量之和达到150，且第一过孔结构107和第二过孔结构108均匀排布，使得并联的电路的的电阻最小，从而使得散发的热量最小。此外，该种设计还可以使得在第一方向X上导电连接层104的宽度可以设计得更窄，使得导电连接层104的左右两部分的最远离显示区域105的边与显示区域105之间的距离缩小，从而可以减小左边框和右边框的宽度，使得左边框和右边框的宽度更窄。
例如，图9为本公开至少一实施例提供的一种第一过孔结构和第二过孔结构处显示面板的电路图，如图9所示，R0对应于导电连接层104的电阻，R1对应于连接导电连接层104和第一公共电极总线102的第一过孔结构107的电阻，R2对应于连接导电连接层104和第二公共电极总线103的第二过孔结构108的电阻，C1对应于导电连接层104和栅极(图10中示出)之间的耦合电容，C2对应于导电连接层104和源漏电极层(图10中示出)之间的耦合电容，C0对应于栅极和源漏电极层之间的耦合电容，尽管只示出了3个电阻R0、R1和R2和三个电容C0、C1和C2，但是本公开的实施例中电阻的数量和电容的数量可以更多，并联的电路越多最终形成的电阻越小，整个电路散发的热量越少。
例如，在一个示例中，假定在频率为60Hz的条件下电流为I，频率为480Hz的条件下的热量为60Hz的条件下热量的8倍，在R1等于R2的条件下，相邻的第一过孔结构和第一过孔结构之间、相邻的第一过孔结构和第二过孔结构之间或者相邻的第二过孔结构和第二过孔结构之间的导电连接层104的电阻为30欧姆，即为电阻R0的阻值，6μm*6μm的过孔电阻的模拟值为80欧姆左右。在频率为60Hz的条件下在10*10的第一过孔结构和第二过孔结构的排布图中，此时，三个电容C0、C1和C2可以忽略，10*10个同样尺寸大小的6μm*6μm的过孔的综合电阻的模拟值为40欧姆左右；在10*30的第一过孔结构和第二过孔结构的排布图中，此时，三个电容C0、C1和C2可以忽略，10*30个同样尺寸大小的6μm*6μm的过孔的综合电阻的模拟值为16欧姆左右，阻值减小了2.5倍。在频率为480Hz的条件下在10*10的第一过孔结构和第二过孔结构的排布图中，此时，三个电容C0、C1和C2可以忽略，10*10个同样尺寸大小的6μm*6μm的过孔的综合电阻的模拟值为320欧姆左右；在10*30的第一过孔结构和第二过孔结构的排布图中，此时，三个电容C0、C1和C2可以忽略，10*30个同样尺寸大小的6μm*6μm的过孔的综合电阻的模拟值为128欧姆左右。
例如，在一个对比的示例中，假定在频率为60Hz的条件下电流为I，频率为165Hz的条件下的热量为60Hz的条件下热量的2.75倍，在R1等于R2，且R1和R2的大小均为400欧姆的条件下，相邻的第一过孔结构和第一过孔结构之间、相邻的第一过孔结构和第二过孔结构之间或者相邻的第一过孔结构和第二过孔结构之间的导电连接层104的电阻为30欧姆，即为电阻R0的 阻值，24μm*24μm的过孔电阻的模拟值为400欧姆左右。在频率为60Hz的条件下在2*2的第一过孔结构和第二过孔结构的排布图中，此时，三个电容C0、C1和C2可以忽略，2*2个同样尺寸大小的24μm*24μm的过孔的综合电阻的模拟值为130欧姆左右。在频率为165Hz的条件下在2*2的第一过孔结构和第二过孔结构的排布图中，此时，三个电容C0、C1和C2可以忽略，2*2个同样尺寸大小的24μm*24μm的过孔的综合电阻的模拟值为357.5欧姆左右。
通过上述示例可以看出，尺寸为24μm*24μm的第一过孔结构的电阻R1是尺寸为6μm*6μm的第一过孔结构的电阻R1的5倍，尺寸为24μm*24μm的第二过孔结构的电阻R2是尺寸为6μm*6μm的第二过孔结构的电阻R2的5倍，6μm*6μm过孔尺寸是目前厂内设备能够做到的最小尺寸，本公开的一些实施例中选择6μm*6μm的过孔，且第一过孔结构107和第二过孔结构108尺寸越小，对应的电阻R1和R2越小。
例如，结合图2～图8，该第一过孔结构107和第二过孔结构108在平行于衬底基板101的主板面上的最大尺寸的范围为4微米～6微米。例如，在一个示例中，该第一过孔结构107和第二过孔结构108的平面形状相同，该第一过孔结构107和第二过孔结构108的平面形状均为尺寸相同的矩形，该矩形的长边的尺寸为4微米～6微米。在另一个示例中，该第一过孔结构107和第二过孔结构108的平面形状相同，均为矩形，但是该第一过孔结构107和第二过孔结构108的平面形状的尺寸不同，该第一过孔结构107和第二过孔结构108对应的具有较大长边的矩形的长边的尺寸为4微米～6微米。在另一个示例中，该第一过孔结构107和第二过孔结构108的平面形状相同，均为圆形，但是该第一过孔结构107和第二过孔结构108的平面形状的尺寸不同，该第一过孔结构107和第二过孔结构108对应的具有较大直径的圆形的直径的尺寸为4微米～6微米。在又一个示例中，该第一过孔结构107和第二过孔结构108的平面形状相同，均为椭圆形，但是该第一过孔结构107和第二过孔结构108的平面形状的尺寸不同，该第一过孔结构107和第二过孔结构108对应的具有较大长径的椭圆形的长径的尺寸为4微米～6微米。该第一过孔结构107和第二过孔结构108的平面形状还可以是其他的形状，对于其他形状的情形，按照类似的规律进行比较，本公开的实施例对此不作限定。
例如，再结合图2，在平行于衬底基板101的主板面上，该第三过孔结 构116的平面形状可以和第一过孔结构107、第二过孔结构108的平面形状相同或者不同。该第三过孔结构116的平面形状的最大尺寸大于第一过孔结构107的平面形状的最大尺寸，也大于第二过孔结构108的平面形状的最大尺寸。
例如，图10为本公开至少一实施例提供的一种显示面板的截面结构示意图，如图10所示，该显示面板100还包括设置在衬底基板101上且在显示区域105的薄膜晶体管117和第一电极118，该薄膜晶体管117包括层叠设置的栅极119、有源层120和源漏电极层121，该源漏电极层121包括相对设置的源极121a和漏极121b，第一公共电极总线102和栅极119同层设置，第二公共电极总线103和源极121a、漏极121b同层设置，该导电连接层104和该第一电极118同层设置且相互间隔，第一电极118通过第四过孔结构122和漏极121b电连接。
例如，该薄膜晶体管117可以为顶栅型薄膜晶体管、底栅型薄膜晶体管或者双栅型薄膜晶体管，本公开的实施例对此不作限定。
例如，在本公开的实施例中，“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩膜版通过一次构图工艺形成的层结构。根据特定图形的不同，依次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的同层的特定图形是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
例如，如图10所示，在栅极119的远离衬底基板101的一侧设置有栅绝缘层123，在源漏电极层121的远离衬底基板101的一侧设置有钝化层124，第一过孔结构107依次贯穿钝化层124和栅绝缘层123，第二过孔结构108和第四过孔结构122均贯穿钝化层124。
例如，结合图2，在平行于衬底基板101的主表面的平面上，且在一个显示面板中，该第二公共电极总线103配置为两条，且两条第二公共电极总线103沿着第一方向X相对设置在第一公共电极总线102的主体部102a的两侧，该显示面板100还包括设置在第三公共电极总线126的远离显示区域105一侧的第四公共电极总线125，该第四公共电极总线125的主体部分和第一公共电极总线102的主体部102a平行，且第四公共电极总线125和第一公共电极总线102同层设置。两条第二公共电极总线103分别包括在第一方向X上远离第一公共电极总线102的第二端部103b和第三端部103c，该 导电连接层104通过第五过孔结构127和第二端部103b以及第三端部103c电连接，该第四公共电极总线125包括和第二端部103b相对的第四端部125a以及和第三端部103c相对的第五端部125b，导电连接层104通过第六过孔结构128和第四端部125a以及第五端部125b电连接。
例如，如图2所示，该第四公共电极总线125设置在静电导出线111的远离显示区域105的一侧，该第四公共电极总线125和第三公共电极总线126以及第二公共电极总线103通过导电连接层104电连接。
例如，结合图2，该第三公共电极总线126的位于其两个端部的中间部分通过第七过孔结构129和导电连接层104电连接，该第七过孔结构129的排布密度、平面形状和尺寸可以和第三过孔结构116相同，在此不再赘述。
本公开至少一实施例还提供一种显示装置，该显示装置包括上述任一实施例中的显示面板。由于显示装置包括上述任一实施例中的显示面板，该显示装置的结构设计也可以实现将分支部设置成更远离显示区域，从而使得分支部上有更大的区域可以设置更多的过孔结构，使得第一过孔结构和第二过孔结构的数量增加，以减小电路结构中的电阻，以避免出现第一过孔结构和第二过孔结构被烧毁，导致显示装置的产品良率降低，显示装置的寿命较短的问题。而且当该显示装置为液晶显示装置时，将第一过孔结构和第二过孔结构设置得远离显示区域，还可以避免出现从第一过孔结构和第二过孔结构散发的热量使得液晶显示面板的显示区域中的液晶层的温度升高以达到液晶的清亮点的问题。即显示装置中的导电连接层跨接处的电阻较小，发热量较小，故其具有较好的产品性能，且显示效果较好。
例如，该显示装置可以为液晶显示装置，例如手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不作限定。
本公开至少一实施例提供的显示面板和显示装置，具有以下至少一项有益技术效果：
(1)本公开至少一实施例提供的显示面板，在周边区域，导电连接层通过第一过孔结构和第一公共电极总线的分支部连接，导电连接层通过第二过孔结构和第二公共电极总线的第一端部电连接，可以使得第一过孔结构和第二过孔结构的数量增加，减小电路结构中的电阻，以避免出现第一过孔结构和第二过孔结构被烧毁，导致显示面板的产品良率 降低，显示面板的寿命较短的问题。
(2)本公开至少一实施例提供的显示面板，当该显示面板为液晶显示面板时，将第一过孔结构和第二过孔结构设置得远离显示区域，还可以避免出现从第一过孔结构和第二过孔结构散发的热量使得液晶显示面板的显示区域中的液晶层的温度升高以达到液晶的清亮点的问题。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种显示面板，包括：
    衬底基板，包括显示区域和围绕所述显示区域的周边区域；
    层叠设置在所述衬底基板上的第一公共电极总线、第二公共电极总线和导电连接层，其中，
    所述第一公共电极总线包括主体部和从所述主体部的端部向远离所述显示区域的一侧延伸出的分支部，所述主体部沿着第一方向延伸，所述分支部的至少和所述主体部连接的部分沿着第二方向延伸，所述第一方向和所述第二方向相交；
    所述第二公共电极总线沿着所述第二方向向远离所述显示区域的一侧延伸，所述第二公共电极总线的第一端部和所述主体部的端部、所述分支部正对；
    在所述周边区域，所述导电连接层通过第一过孔结构和所述第一公共电极总线的所述分支部电连接，所述导电连接层通过第二过孔结构和所述第二公共电极总线的所述第一端部电连接。
  2. 根据权利要求1所述的显示面板，其中，
    在平行于所述衬底基板的主表面的平面上，所述分支部至少包括远离所述显示区域的第一弯折部，所述第一过孔结构在所述衬底基板上的正投影和所述第一弯折部在所述衬底基板上的正投影至少部分交叠。
  3. 根据权利要求2所述的显示面板，其中，在平行于所述衬底基板的主表面的平面上，所述第一端部延伸至所述第一弯折部限定的开口区域中，且所述第二过孔结构在所述衬底基板上的正投影和所述第一端部在所述衬底基板上的正投影至少部分交叠。
  4. 根据权利要求2所述的显示面板，其中，
    所述第一弯折部包括沿所述第二方向延伸的第一子弯折部分和沿所述第一方向向靠近所述第二公共电极总线的一侧延伸的第二子弯折部分，所述第二公共电极总线的延伸方向平行于所述第二方向，所述第一子弯折部分在所述衬底基板上的正投影和所述第一过孔结构在所述衬底基板上的正投影具有交叠部分，且所述第二子弯折部分在所述衬底基板上的正投影和所述第一过孔结构在所述衬底基板上的正投影具有交叠部分。
  5. 根据权利要求2所述的显示面板，其中，
    所述第一弯折部包括沿所述第二方向延伸的第一子弯折部分和沿所述第一方向向靠近所述第二公共电极总线的一侧延伸的第二子弯折部分，所述第二公共电极总线的延伸方向平行于所述第二方向，所述第一子弯折部分在所述衬底基板上的正投影和所述第一过孔结构在所述衬底基板上的正投影具有交叠部分，且所述第二子弯折部分在所述衬底基板上的正投影和所述第一过孔结构在所述衬底基板上的正投影不具有交叠部分。
  6. 根据权利要求2所述的显示面板，其中，
    所述第一弯折部包括沿所述第二方向延伸的第一子弯折部分和沿所述第一方向向靠近所述第二公共电极总线的一侧延伸的第二子弯折部分，所述第二公共电极总线的延伸方向平行于所述第二方向，所述第一子弯折部分在所述衬底基板上的正投影和所述第一过孔结构在所述衬底基板上的正投影不具有交叠部分，且所述第二子弯折部分在所述衬底基板上的正投影和所述第一过孔结构在所述衬底基板上的正投影具有交叠部分。
  7. 根据权利要求4～6中任一项所述的显示面板，其中，在平行于所述衬底基板的主表面的平面上，所述分支部还包括远离所述显示区域的第二弯折部，所述第二弯折部包括沿所述第二方向延伸的第三子弯折部分和沿所述第一方向延伸的第四子弯折部分，所述第二子弯折部分和所述第四子弯折部分连接以使所述第一弯折部和所述第二弯折部的整体形状为“U”型，且所述第二公共电极总线延伸至所述“U”型的开口中。
  8. 根据权利要求7所述的显示面板，其中，所述第三子弯折部分在所述衬底基板上的正投影和所述第一过孔结构在所述衬底基板上的正投影具有交叠部分，且所述第四子弯折部分在所述衬底基板上的正投影和所述第一过孔结构在所述衬底基板上的正投影具有交叠部分。
  9. 根据权利要求7所述的显示面板，其中，所述第三子弯折部分在所述衬底基板上的正投影和所述第一过孔结构在所述衬底基板上的正投影具有交叠部分，且所述第四子弯折部分在所述衬底基板上的正投影和所述第一过孔结构在所述衬底基板上的正投影不具有交叠部分。
  10. 根据权利要求1～9中任一项所述的显示面板，其中，在平行于所述衬底基板的主表面的平面上，所述第一公共电极总线的所述主体部在平行于所述第一方向的方向上设置，所述主体部上设置有第三过孔结构，且所述主 体部通过所述第三过孔结构和所述导电连接层电连接。
  11. 根据权利要求1～10中任一项所述的显示面板，其中，所述第一过孔结构和所述第二过孔结构与所述显示区域的最小距离均大于500微米。
  12. 根据权利要求1～11中任一项所述的显示面板，其中，所述第一过孔结构配置为多个，所述第二过孔结构配置为多个，且所述第一过孔结构和所述第二过孔结构的总个数大于或者等于150。
  13. 根据权利要求12所述的显示面板，其中，所述第一过孔结构和所述第二过孔结构呈矩阵排列，所述第一方向为行方向，所述第二方向为列方向，沿着所述第一方向在一行中所述第一过孔结构和所述第二过孔结构的数量之和大于15，沿着所述第二方向在一列中所述第一过孔结构和所述第二过孔结构的数量之和大于10，且沿着所述第一方向在一行中所述第一过孔结构和所述第二过孔结构的数量之和大于沿着所述第二方向在一列中所述第一过孔结构和所述第二过孔结构的数量之和。
  14. 根据权利要求12所述的显示面板，其中，所述第一过孔结构和所述第二过孔结构呈矩阵排列，所述第一方向为行方向，所述第二方向为列方向，沿着所述第一方向在一行中所述第一过孔结构和所述第二过孔结构的数量之和大于10，沿着所述第二方向在一列中所述第一过孔结构和所述第二过孔结构的数量之和大于15，且沿着所述第一方向在一行中所述第一过孔结构和所述第二过孔结构的数量之和小于沿着所述第二方向在一列中所述第一过孔结构和所述第二过孔结构的数量之和。
  15. 根据权利要求1～14中任一项所述的显示面板，其中，所述第一过孔结构和所述第二过孔结构在平行于所述衬底基板的主板面上的最大尺寸的范围为4微米～6微米。
  16. 根据权利要求1～14中任一项的显示面板，还包括：设置在所述衬底基板上且在所述显示区域的薄膜晶体管和第一电极，其中，所述薄膜晶体管包括层叠设置的栅极、有源层和源漏电极层，所述源漏电极层包括相对设置的源极和漏极，所述第一公共电极总线和所述栅极同层设置，所述第二公共电极总线和所述源极、所述漏极同层设置，所述导电连接层和所述第一电极同层设置且相互间隔，所述第一电极通过第四过孔结构和所述漏极电连接。
  17. 根据权利要求16所述的显示面板，其中，在所述栅极的远离所述 衬底基板的一侧设置有栅绝缘层，在所述源漏电极层的远离所述衬底基板的一侧设置有钝化层，所述第一过孔结构依次贯穿所述钝化层和所述栅绝缘层，所述第二过孔结构和所述第四过孔结构均贯穿所述钝化层。
  18. 根据权利要求1～17中任一项所述的显示面板，其中，
    在平行于所述衬底基板的主表面的平面上，且在一个所述显示面板中，所述第二公共电极总线配置为两条，且两条所述第二公共电极总线沿着所述第一方向相对设置在所述第一公共电极总线的所述主体部的两侧；
    所述显示面板还包括和所述第一公共电极总线在所述第二方向上相对设置的第三公共电极总线，所述第三公共电极总线和所述第一公共电极总线的所述主体部平行，且所述第三公共电极总线和所述第一公共电极总线同层设置，两条所述第二公共电极总线、所述第一公共电极总线和所述第三公共电极总线围设在所述显示区域的四周；
    两条所述第二公共电极总线分别包括在所述第一方向上远离所述第一公共电极总线的第二端部和第三端部，所述导电连接层通过第五过孔结构和所述第二端部以及所述第三端部电连接；
    所述第三公共电极总线包括和所述第二端部相对的第四端部以及和所述第三端部相对的第五端部，所述导电连接层通过第六过孔结构和所述第四端部以及所述第五端部电连接。
  19. 根据权利要求18所述的显示面板，其中，所述第三公共电极总线的在所述第四端部和所述第五端部之间的部分通过第七过孔结构和所述导电连接层电连接。
  20. 一种显示装置，包括权利要求1～19中任一项所述的显示面板。
PCT/CN2022/106017 2022-07-15 2022-07-15 显示面板和显示装置 WO2024011597A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101082745A (zh) * 2006-05-31 2007-12-05 株式会社日立显示器 液晶显示装置
CN101872092A (zh) * 2009-04-24 2010-10-27 上海天马微电子有限公司 液晶显示面板
JP2013182127A (ja) * 2012-03-01 2013-09-12 Sharp Corp 液晶ディスプレイ
CN103946740A (zh) * 2011-11-25 2014-07-23 夏普株式会社 液晶显示装置
US20150219944A1 (en) * 2012-08-09 2015-08-06 Sharp Kabushiki Kaisha Display apparatus

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101082745A (zh) * 2006-05-31 2007-12-05 株式会社日立显示器 液晶显示装置
CN101872092A (zh) * 2009-04-24 2010-10-27 上海天马微电子有限公司 液晶显示面板
CN103946740A (zh) * 2011-11-25 2014-07-23 夏普株式会社 液晶显示装置
JP2013182127A (ja) * 2012-03-01 2013-09-12 Sharp Corp 液晶ディスプレイ
US20150219944A1 (en) * 2012-08-09 2015-08-06 Sharp Kabushiki Kaisha Display apparatus

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