WO2020181634A1 - Oled 显示装置及制备方法 - Google Patents

Oled 显示装置及制备方法 Download PDF

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Publication number
WO2020181634A1
WO2020181634A1 PCT/CN2019/084766 CN2019084766W WO2020181634A1 WO 2020181634 A1 WO2020181634 A1 WO 2020181634A1 CN 2019084766 W CN2019084766 W CN 2019084766W WO 2020181634 A1 WO2020181634 A1 WO 2020181634A1
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Prior art keywords
layer
insulating layer
interlayer insulating
gate
display device
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PCT/CN2019/084766
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English (en)
French (fr)
Inventor
白思航
郑园
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武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/492,133 priority Critical patent/US20200295111A1/en
Publication of WO2020181634A1 publication Critical patent/WO2020181634A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • This application relates to the field of display technology, in particular to an OLED display device and a manufacturing method.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • the line residue of the source and drain metal layer will occur at the edge, resulting in the short distance between the VDD signal wiring and the VSS signal wiring.
  • the short circuit further leads to abnormal signal.
  • the present application provides an OLED display device and a manufacturing method, which can increase the residual path of the source and drain metal layers at the edge of the organic film layer, so as to solve the problem of the existing OLED display device, because the organic film layer with less stress is used in the bending area At the same time, linear residues of the source and drain metal layers will occur at the edges, causing short circuits between the VDD signal traces and the VSS signal traces due to the short distance, which further leads to technical problems of abnormal signals.
  • the present application provides an OLED display device.
  • the OLED display device includes a display area and a non-display area located at one end of the display area; a plurality of signal traces, bending areas, and bindings are arranged in the non-display area Area, one end of each signal trace is connected to the display area, the opposite end of each signal trace extends through the bending area to the binding area, and the signal located in the bending area
  • the wiring includes at least a power line and a data signal line.
  • An organic interlayer insulating layer is also provided in the bending area. The power line and the adjacent signal wiring are arranged in parallel with each other and pass through the organic The edge of the interlayer insulation layer;
  • the edge length of the portion of the organic interlayer insulating layer between the power line and the adjacent signal wiring is greater than or equal to the width of the power line.
  • the power supply line includes a VDD signal line and a VSS signal line.
  • the VDD signal line is adjacent to the VSS signal line.
  • the signal wires or the data signal wires are arranged parallel to each other and pass through the edges of the organic interlayer insulating layer respectively.
  • the distance between the VDD signal wiring located in the bending area and the adjacent VSS signal wiring is 3000-5000 microns.
  • the portion of the organic interlayer insulating layer between the VDD signal wiring and the adjacent VSS signal wiring is The edge shape is set to a bow shape.
  • the portion of the OLED display device located in the bending area includes a flexible substrate, a barrier layer, a buffer layer, a first gate insulating layer, and a second gate insulating layer ,
  • the inorganic interlayer insulating layer, the organic interlayer insulating layer, the source and drain metal layer, the planarization layer, the pixel defining layer and the pixel support layer, the organic interlayer insulating layer penetrates the inorganic interlayer insulating layer, the The second gate insulating layer, the first gate insulating layer, the buffer layer and the barrier layer are connected to the flexible substrate.
  • the material of the flexible substrate is polyimide
  • the material of the buffer layer is one or two of silicon nitride or silicon oxide
  • the organic The material of the interlayer insulating layer is organic photoresist
  • the material of the first gate buffer layer is silicon nitride or silicon oxide
  • the material of the second gate buffer layer is the same as the material of the first gate buffer layer
  • the material of the source and drain metal layer is titanium or titanium aluminum alloy.
  • the application also provides a method for manufacturing an OLED display device, including:
  • a substrate is provided, a flexible substrate is prepared on the surface of the substrate, a barrier layer and a buffer layer are sequentially prepared on the surface of the flexible substrate, and then an active layer is prepared on the surface of the buffer layer, and then the buffer layer A first gate insulating layer is prepared on the surface of the layer, the first gate insulating layer completely covers the active layer, and then a first gate metal layer is prepared on the surface of the first gate insulating layer, and the second gate A polar insulating layer is formed on the first gate insulating layer and completely covers the first gate metal layer, a second gate metal layer is prepared on the second gate insulating layer, and then a second gate metal layer is formed on the second gate insulating layer.
  • a source and drain metal layer and a planarization layer are sequentially prepared on the surface of the inorganic interlayer insulating layer, the planarization layer completely covers the source and drain metal layer, and finally, a surface of the planarization layer is sequentially prepared An anode metal layer, a pixel defining layer and a pixel support layer, a part of the anode metal layer is directly connected with the source and drain metal layers, and finally the substrate is removed.
  • the power supply line includes a VDD signal wiring and a VSS signal wiring.
  • the VDD signal wiring In the bending area, the VDD signal wiring The VSS signal traces or the data signal lines adjacent to the VSS signal traces are arranged in parallel with each other and respectively pass through the edges of the organic interlayer insulating layer.
  • the distance between the VDD signal wiring located in the bending area and the adjacent VSS signal wiring is 3000-5000 microns.
  • a portion of the organic layer between the VDD signal wiring and the adjacent VSS signal wiring is set to be arcuate.
  • the beneficial effects of the present application are: the OLED display device and manufacturing method provided by the present application adjust the edge length of one end of the organic interlayer insulating layer between the power line in the bending area and the adjacent signal wiring Setting it to be greater than or equal to the width of the power line increases the residual path of the source and drain metal layers at the edge of the organic film layer, and further reduces the risk of short circuits between adjacent signal traces.
  • FIG. 1 is a schematic diagram of the structure of the OLED display device of this application.
  • FIG. 2 is an enlarged schematic cross-sectional view of the OLED display device of the present application at A in FIG. 1.
  • FIG. 3A is an enlarged schematic plan view at B in FIG. 2 of Embodiment 1 of the OLED display device of the present application.
  • 3B is an enlarged schematic plan view at B in the second embodiment of the OLED display device of the present application in FIG. 2.
  • FIG. 4 is a flow chart of the manufacturing method of the OLED display device of this application.
  • 5A-5D are schematic diagrams of the manufacturing method of the OLED display device of this application.
  • This application is aimed at the existing OLED display device, because when the organic film layer with less stress is used in the bending area, the source and drain metal layer will have linear residues on the edge, resulting in the VDD signal wiring and the VSS signal wiring due to the spacing If the short circuit is too short, it will further cause the technical problem of abnormal signal.
  • This embodiment can solve the defect.
  • the present application provides an OLED display device 101.
  • the OLED display device 101 includes a display area 102 and a non-display area 108 located at one end of the display area 102; the non-display area 108 is provided with A plurality of signal traces, a bending area 104 and a binding area 107, one end 103 of each signal trace is connected to the display area 102, and the opposite end 106 of each signal trace passes through the bending
  • the area 104 extends to the binding area 107; the lower end of the bending area 104 is connected with a test circuit 105.
  • the multiple signal traces include array substrate row drive signal lines, power supply lines, and data signal lines connected from the backplane to the display area 102, and the signal traces are made of materials with good ductility. Ti/Al/Ti materials.
  • the power supply line includes a VDD signal line and a VSS signal line.
  • the VDD signal line is between the VSS signal line or the data signal line adjacent to it. Set up parallel to each other.
  • an enlarged cross-sectional schematic diagram of the OLED display device of this application at A (bending area 104).
  • the portion of the OLED display device located in the bending area 104 (at A) includes a flexible substrate 201, a barrier layer 202, a buffer layer 203, a first gate insulating layer 204, a second gate insulating layer 205,
  • the insulating layer 206, the second gate insulating layer 205, the first gate insulating layer 204, the buffer layer 203 and the barrier layer 202 are connected to the flexible substrate 201.
  • a plurality of signal traces are provided on the surface of the organic interlayer insulating layer 207, including array substrate row drive signal lines, power lines, and data signal lines.
  • the signal traces are made of materials with good ductility. Ti/Al/Ti material;
  • the power line and its adjacent signal traces are arranged parallel to each other and pass through the edges of the organic interlayer insulating layer 207, so The edge length of the portion of the organic interlayer insulating layer 207 between the power line and the adjacent signal wiring is greater than or equal to the width of the power line; wherein the line width of the power line is 700 ⁇ 800 microns.
  • the power supply line includes a VDD signal wiring 212 and a VSS signal wiring 213.
  • the VDD signal wiring 212 and the adjacent VSS signal wiring 213 or the VSS signal wiring are arranged parallel to each other and pass through the edges of the organic interlayer insulating layer 207 respectively.
  • the material of the organic interlayer insulating layer 207 is an organic photoresist.
  • the material of the flexible substrate 201 is polyimide
  • the material of the buffer layer 203 is one or two of silicon nitride or silicon oxide
  • the material of the first gate buffer layer 204 It is silicon nitride or silicon oxide
  • the material of the second gate buffer layer 205 is the same as the material of the first gate buffer layer 204
  • the material of the source and drain metal layer 208 is titanium or titanium aluminum alloy.
  • FIG. 3A it is an enlarged schematic plan view at B in the first embodiment of the OLED display device of the present application in FIG.
  • the VDD signal wiring 212 and the VSS signal wiring 213 are arranged in parallel with each other and pass through the edge of the organic interlayer insulating layer 2071 respectively; the VDD signal wiring 212 and the adjacent VSS signal wiring
  • the distance D1 of the line 213 ranges from 3000 to 5000 microns, that is, the edge length of the organic interlayer insulating layer 2071 between the VDD signal trace 212 and the adjacent VSS signal trace 213 is greater than The line width of the VDD signal wiring 212 or the VSS signal wiring 213.
  • the distance between the VDD signal wiring 212 and the adjacent VSS signal wiring 213 is increased to 3000 ⁇ 5000 microns, which is compared with the VDD signal wiring in the prior art
  • the distance between 212 and the VSS signal trace 213 is 100 to 200 microns, which increases the residual path of the source and drain metal layer 208 at the edge of the organic film layer 2071. As long as the path is at any position If the source and drain metal particles are disconnected, the signal short circuit will not be caused. This design is more helpful to reduce the risk of short circuit between the VDD signal wiring 212 and the VSS signal wiring 213.
  • FIG. 3B it is an enlarged schematic plan view at B in the second embodiment of the OLED display device of the present application in FIG.
  • the VDD signal wiring 212 and the VSS signal wiring 213 are arranged in parallel with each other and pass through the edge of the organic interlayer insulating layer 2072; the VDD signal wiring 212 and the adjacent VSS signal wiring
  • the distance between the lines 213 is D2; the edge shape of the part of the organic interlayer insulating layer 2072 located between the VDD signal wiring 212 and the VSS signal wiring 213 is set into an arcuate shape by etching.
  • the edge length of the portion of the organic interlayer insulating layer 2072 between the VDD signal wiring 212 and the adjacent VSS signal wiring 21 is greater than that of the VDD signal wiring 212 or the VSS signal wiring.
  • the edge shape of the organic interlayer insulating layer 2072 between the VDD signal wiring 212 and the adjacent VSS signal wiring 213 is set to a bow shape, which increases The residual path of the source and drain metal layer 208 at the edge of the organic film layer 2072. As long as the source and drain metal particles at any position in this path are disconnected, it will not cause a signal short circuit problem. This design is more helpful This reduces the risk of short circuit between the VDD signal wiring 212 and the VSS signal wiring 213.
  • the present application also provides a manufacturing method flow of an OLED display device, and the method includes:
  • a substrate is provided, a flexible substrate 501 is prepared on the surface of the substrate, a barrier layer 502 and a buffer layer 503 are sequentially prepared on the surface of the flexible substrate 501, and then an active layer 504 is prepared on the surface of the buffer layer.
  • a first gate insulating layer 505 is prepared on the surface of the buffer layer 503, and the first gate insulating layer 505 completely covers the active layer 504, and then is prepared on the surface of the first gate insulating layer 505
  • the first gate metal layer 506 and the second gate insulating layer 507 are formed on the first gate insulating layer 505 and completely cover the first gate metal layer 506, on the second gate insulating layer 507
  • a second gate metal layer 508 is prepared, and then an inorganic interlayer insulating layer 509 is formed on the second gate metal layer 508.
  • the S10 further includes:
  • an insulating substrate is provided, and a layer of flexible substrate 501 is deposited on the surface of the insulating substrate.
  • the material of the flexible substrate 501 is polyimide; then, physical weathering is used on the surface of the flexible substrate 501.
  • the barrier layer 502 and the buffer layer 503 are sequentially deposited by the deposition method.
  • the material of the barrier layer 502 is one or two of silicon nitride or silicon oxide; the material of the buffer layer 503 is silicon nitride or silicon oxide.
  • a semiconductor layer is formed on the surface of the buffer layer 503, and the semiconductor layer structure is defined by a photomask lithography process to form the active layer 504; then on the buffer layer 503 A first gate insulating layer 505 is deposited on the surface, the first gate insulating layer 505 completely covers the active layer 504, and the material of the first gate buffer layer 505 is silicon nitride or silicon oxide; The surface of the first gate buffer layer 505 uses a photomask lithography process to define the gate conductor structure to form a first gate metal layer 506. The material of the first gate metal layer 506 is metal molybdenum.
  • a second gate buffer layer 507 is deposited on the surface of the first gate buffer layer 505, the material of the second gate buffer layer 507 is the same as the material of the first gate buffer layer 505;
  • a photomask lithography process is used on the surface of the second gate buffer layer 507 to define a gate conductor structure to form a second gate metal layer 508; the material of the second gate metal layer 508 It is molybdenum, and finally an inorganic interlayer insulating layer 509 is deposited on the second gate metal layer 508, as shown in FIG. 5A.
  • the S20 further includes:
  • a trench is formed in a non-display area, and the trench exposes the flexible substrate 501; the trench penetrates the inorganic interlayer insulating layer 509, the second gate insulating layer 507, and the first The gate insulating layer 505, the buffer layer 503, and the barrier layer 502 stop at the flexible substrate 501; after that, an organic interlayer insulating layer 510 is filled in the trench, and the organic interlayer insulating
  • the material of 510 is an organic photoresist, as shown in FIG. 5B.
  • the S30 further includes:
  • a plurality of signal traces are provided on the surface of the organic interlayer insulating layer 510, including array substrate row driving signal lines, power lines, and data signal lines.
  • the signal traces are made of materials with good ductility. Ti/Al/Ti materials.
  • the power line and its adjacent signal traces are arranged in parallel with each other and pass through the edges of the organic interlayer insulating layer 510 respectively, and the power line and the adjacent signal traces
  • the edge length of the part of the organic interlayer insulating layer 510 between the signal traces is greater than or equal to the width of the power line; wherein the line width of the power line ranges from 700 to 800 microns.
  • the power supply line includes a VDD signal wiring 511 and a VSS signal wiring 512.
  • the VDD signal wiring 511 and the adjacent VSS signal wiring 512 or the The data signal lines are arranged parallel to each other and pass through the edges of the organic interlayer insulating layer 510 respectively.
  • the length of the distance D between the VDD signal wiring 511 and the adjacent VSS signal wiring 512 is set to 3000 ⁇ 5000 microns, that is, the VDD signal wiring 511 and the adjacent VSS signal
  • the edge length of the portion of the organic interlayer insulating layer 510 between the traces 512 is greater than the line width of the VDD signal trace 212 or the VSS signal trace 213.
  • the edge shape of the portion of the organic interlayer insulating layer 510 located between the VDD signal wiring 511 and the VSS signal wiring 512 is set into an arcuate shape by etching. At this time, the edge length of the organic interlayer insulating layer 510 between the VDD signal wiring 511 and the adjacent VSS signal wiring 512 is greater than that of the VDD signal wiring 511 or the VSS signal wiring.
  • the line width of line 512 is as shown in FIG. 5C.
  • a source and drain metal layer 513 and a planarization layer 514 are sequentially formed on the surface of the inorganic interlayer insulating layer 509, the planarization layer 514 completely covers the source and drain metal layer 513, and finally the planarization
  • An anode metal layer 515, a pixel defining layer 516, and a pixel support layer 517 are sequentially prepared on the surface of the layer 514. A part of the anode metal layer 515 is directly connected to the source and drain metal layer 513, and finally the substrate is removed.
  • the S40 further includes:
  • a metal layer is formed on the surface of the inorganic interlayer insulating layer 509, and a source and drain conductor layer structure is defined by a photomask lithography process to form a source and drain metal layer 513; then, on the inorganic layer A planarization layer 514 is deposited on the surface of the inter-insulating layer 509, and the planarization layer 514 completely covers the source and drain metal layers 513; then an anode metal layer 515 and pixels are sequentially deposited on the surface of the planarization layer 514 The defining layer 516 and the pixel supporting layer 517, wherein a part of the anode metal layer 515 is directly connected to the source and drain metal layer 513; finally, the substrate is removed, as shown in FIG. 5D.
  • the beneficial effects of the present application are: the OLED display device and manufacturing method provided by the present application adjust the edge length of one end of the organic interlayer insulating layer between the power line in the bending area and the adjacent signal wiring Setting it to be greater than or equal to the width of the power line increases the residual path of the source and drain metal layers at the edge of the organic film layer, and further reduces the risk of short circuits between adjacent signal traces.

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Abstract

一种OLED显示装置，包括显示区域及非显示区域；所述非显示区域内设置有多条信号走线、弯折区域及绑定区域，位于所述弯折区域的信号走线至少包括VDD信号走线以及VSS信号走线，所述弯折区域内还设置一有机层间绝缘层；位于所述VDD信号走线与所述VSS信号走线之间的部分所述有机层间绝缘层一端的边缘长度大于或等于3000微米。

Description

OLED显示装置及制备方法 技术领域
本申请涉及显示技术领域，尤其涉及一种OLED显示装置及制备方法。
 背景技术
目前AMOLED（有源矩阵有机发光二极体）以其轻薄，可弯折，不易碎，可穿戴等优点成为下一代显示技术的杰出代表，然而目前仍有很多技术问题需要攻克。首先弯折性能就是最关键的衡量标准，为了减少产品在弯折过程中应力过大所带来的风险，各企业对平板弯折区的材料的选择以及结构的优化正在积极研究中，目前主流产品在平板的弯折区域主要采用多步蚀刻的方式去除无机膜层，相应的采用应力较小的有机膜层取代，提高产品的弯折性能。但是在实验过程中，我们发现以下制程风险：在有机膜层边缘会发生源漏极金属层的线状残留，VDD信号走线(恒压高电平信号走线)与VSS信号走线(恒压低电平信号走线)之间的距离大概在100-200微米之间，在VDD信号走线与VSS信号走线之间的残留的源漏极金属层会导致VDD信号走线与VSS信号走线发生短路，从而导致信号异常。
综上所述，现有的OLED显示装置，由于在弯折区域采用应力较小的有机膜层时其边缘会发生源漏极金属层的线状残留，导致VDD信号走线与VSS信号走线因为间距过短发生短路，进一步导致信号异常。
 技术问题
现有的OLED显示装置，由于在弯折区域采用应力较小的有机膜层时其边缘会发生源漏极金属层的线状残留，导致VDD信号走线与VSS信号走线因为间距过短发生短路，进一步导致信号异常。
 技术解决方案
本申请提供一种OLED显示装置及制备方法，能够增加有机膜层边缘的源漏极金属层的残留路径，以解决现有的OLED显示装置，由于在弯折区域采用应力较小的有机膜层时其边缘会发生源漏极金属层的线状残留，导致VDD信号走线与VSS信号走线因为间距过短发生短路，进一步导致信号异常的技术问题。
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种OLED显示装置，所述OLED显示装置包括显示区域，以及位于所述显示区域一端的非显示区域；所述非显示区域内设置有多条信号走线、弯折区域以及绑定区域，每一所述信号走线的一端连接所述显示区域，每一所述信号走线的相对另一端经过所述弯折区域延伸至所述绑定区域，位于所述弯折区域的信号走线至少包括电源线以及数据信号线，所述弯折区域内还设置一有机层间绝缘层，所述电源线与其相邻的所述信号走线之间相互平行设置且分别经过所述有机层间绝缘层的边缘；
其中，在所述弯折区域内，所述电源线和与其相邻的所述信号走线之间的部分所述有机层间绝缘层的边缘长度大于或等于所述电源线的宽度。
在本申请实施例所提供的OLED显示装置中，所述电源线包括VDD信号走线以及VSS信号走线，在所述弯折区域内，所述VDD信号走线和与其相邻的所述VSS信号走线或所述数据信号线之间相互平行设置且分别经过所述有机层间绝缘层的边缘。
在本申请实施例所提供的OLED显示装置中，位于弯折区域内的所述VDD信号走线和与其相邻的所述VSS信号走线的间距范围为3000-5000微米。
在本申请实施例所提供的OLED显示装置中，在所述弯折区域内，所述VDD信号走线和与其相邻的所述VSS信号走线之间的部分所述有机层间绝缘层的边缘形状设置为弓形。
在本申请实施例所提供的OLED显示装置中，所述OLED显示装置位于所述弯折区域的部分包括柔性衬底、阻挡层、缓冲层、第一栅极绝缘层、第二栅极绝缘层、无机层间绝缘层、所述有机层间绝缘层、源漏极金属层、平坦化层、像素限定层以及像素支撑层，所述有机层间绝缘层贯穿所述无机层间绝缘层、所述第二栅极绝缘层、所述第一栅极绝缘层、所述缓冲层以及所述阻挡层并与所述柔性衬底相连。
在本申请实施例所提供的OLED显示装置中，所述柔性衬底的材料为聚酰亚胺，所述缓冲层的材料为氮化硅或氧化硅其中的一种或两种，所述有机层间绝缘层的材料为有机光阻，所述第一栅极缓冲层的材料为氮化硅或氧化硅，所述第二栅极缓冲层的材料与所述第一栅极缓冲层的材料相同，所述源漏极金属层的材料为钛或钛铝合金。
本申请还提供一种OLED显示装置的制备方法，包括：
S10，提供一基板，在所述基板表面制备柔性衬底，之后在所述柔性衬底表面依次制备阻挡层以及缓冲层，然后在所述缓冲层的表面制备有源层，之后在所述缓冲层的表面制备第一栅极绝缘层，所述第一栅极绝缘层完全覆盖所述有源层，然后在所述第一栅极绝缘层的表面制备第一栅极金属层，第二栅极绝缘层形成于所述第一栅极绝缘层并完全覆盖所述第一栅极金属层，在所述第二栅极绝缘层上制备第二栅极金属层，之后在所述第二栅极金属层上制备无机层间绝缘层；
S20，通过掩膜对所述阻挡层、所述缓冲层、所述第一栅极绝缘层、所述第二栅极绝缘层以及所述无机层间绝缘层进行干法刻蚀，在非显示区域形成沟槽，所述沟槽暴露出所述柔性衬底，在所述沟槽内填充形成有机层间绝缘层；
S30，将电源线在弯折区域内与其相邻的信号走线之间相互平行设置且分别经过所述有机层间绝缘层的边缘，使得所述电源线和与其相邻的所述信号走线之间的部分所述有机层间绝缘层一端的边缘长度大于或等于所述电源线的宽度；
S40，在所述无机层间绝缘层的表面依次制备源漏极金属层以及平坦化层，所述平坦化层完全覆盖所述源漏极金属层，最后在所述平坦化层的表面依次制备阳极金属层、像素限定层以及像素支撑层，所述阳极金属层的一部分与所述源漏极金属层直接相连，最后去除基板。
在本申请实施例所提供的OLED显示装置的制备方法中，所述S30中，所述电源线包括VDD信号走线以及VSS信号走线，在所述弯折区域内，所述VDD信号走线和与其相邻的所述VSS信号走线或所述数据信号线之间相互平行设置且分别经过所述有机层间绝缘层的边缘。
在本申请实施例所提供的OLED显示装置的制备方法中，位于弯折区域内的所述VDD信号走线和与其相邻的所述VSS信号走线的间距范围为3000-5000微米。
在本申请实施例所提供的OLED显示装置的制备方法中，在所述弯折区域内，所述VDD信号走线和与其相邻的所述VSS信号走线之间的部分所述有机层间绝缘层的边缘形状设置为弓形。
 有益效果
本申请的有益效果为：本申请所提供的OLED显示装置及制备方法，将位于弯折区域的电源线和与其相邻的信号走线之间的部分所述有机层间绝缘层一端的边缘长度设置为大于或等于所述电源线的宽度，增加了有机膜层边缘的源漏极金属层的残留路径，进一步减少了相邻信号走线之间的短路风险。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请OLED显示装置架构示意图。
图2为图1中本申请OLED显示装置在A处的放大截面示意图。
图3A为图2中本申请OLED显示装置实施例一在B处的放大平面示意图。
图3B为图2中本申请OLED显示装置实施例二在B处的放大平面示意图。
图4为本申请OLED显示装置的制造方法流程图。
图5A-图5D为本申请OLED显示装置的制造方法示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请针对现有的OLED显示装置，由于在弯折区域采用应力较小的有机膜层时其边缘会发生源漏极金属层的线状残留，导致VDD信号走线与VSS信号走线因为间距过短发生短路，进一步导致信号异常的技术问题，本实施例能够解决该缺陷。
如图1所示，本申请提供一种OLED显示装置101，所述OLED显示装置101包括显示区域102，以及位于所述显示区域102一端的非显示区域108；所述非显示区域108内设置有多条信号走线、弯折区域104以及绑定区域107，每一所述信号走线的一端103连接所述显示区域102，每一所述信号走线的相对另一端106经过所述弯折区域104延伸至所述绑定区域107；所述弯折区域104的下端连接有测试电路105。
具体的，多条所述信号走线包括从背板连接至所述显示区域102的阵列基板行驱动信号线、电源线以及数据信号线，所述信号走线的材料为会延展性能较好的Ti/Al/Ti材料。
其中，所述电源线包括VDD信号走线以及VSS信号走线，在所述弯折区域内，所述VDD信号走线和与其相邻的所述VSS信号走线或所述数据信号线之间相互平行设置。
如图2所示，为本申请OLED显示装置在A处（弯折区域104）的放大截面示意图。其中，所述OLED显示装置位于所述弯折区域104（A处）的部分包括柔性衬底201、阻挡层202、缓冲层203、第一栅极绝缘层204、第二栅极绝缘层205、无机层间绝缘层206、有机层间绝缘层207、源漏极金属层208、平坦化层209、像素限定层210以及像素支撑层211，所述有机层间绝缘层207贯穿所述无机层间绝缘层206、所述第二栅极绝缘层205、所述第一栅极绝缘层204、所述缓冲层203以及所述阻挡层202并与所述柔性衬底201相连。
具体的，所述有机层间绝缘层207的表面上设置有多条信号走线，包括阵列基板行驱动信号线、电源线以及数据信号线，所述信号走线的材料为会延展性能较好的Ti/Al/Ti材料；在所述弯折区域104内，所述电源线与其相邻的所述信号走线之间相互平行设置且分别经过所述有机层间绝缘层207的边缘，所述电源线和与其相邻的所述信号走线之间的部分所述有机层间绝缘层207的边缘长度大于或等于所述电源线的宽度；其中，所述电源线的线宽范围为700~800微米。
具体的，所述电源线包括VDD信号走线212以及VSS信号走线213，在所述弯折区域104内，所述VDD信号走线212和与其相邻的所述VSS信号走线213或所述数据信号线之间相互平行设置且分别经过所述有机层间绝缘层207的边缘。
具体的，所述有机层间绝缘层207的材料为有机光阻。
具体的，所述柔性衬底201的材料为聚酰亚胺，所述缓冲层203的材料为氮化硅或氧化硅其中的一种或两种；所述第一栅极缓冲层204的材料为氮化硅或氧化硅，所述第二栅极缓冲层205的材料与所述第一栅极缓冲层204的材料相同；所述源漏极金属层208的材料为钛或钛铝合金。
如图3A所示，为图2中本申请OLED显示装置实施例一在B处的放大平面示意图。其中，所述VDD信号走线212与所述VSS信号走线213之间相互平行设置且分别经过有机层间绝缘层2071的边缘；所述VDD信号走线212与其相邻的所述VSS信号走线213的距离D1的长度范围为3000~5000微米，即所述VDD信号走线212与其相邻的所述VSS信号走线213之间的部分所述有机层间绝缘层2071的边缘长度大于所述VDD信号走线212或所述VSS信号走线213的线宽。
本申请OLED显示装置实施例一将所述VDD信号走线212与其相邻的所述VSS信号走线213之间的距离增加到3000~5000微米，相比现有技术中所述VDD信号走线212与所述VSS信号走线213之间的距离为100~200微米，增加了所述有机膜层2071的边缘处的所述源漏极金属层208的残留路径，此路径内只要任意位置的源漏极金属颗粒断开，就不会造成信号的短路问题，此种设计更有助于降低所述VDD信号走线212与所述VSS信号走线213之间的短路风险。
如图3B所示，为图2中本申请OLED显示装置实施例二在B处的放大平面示意图。其中，所述VDD信号走线212与所述VSS信号走线213之间相互平行设置且分别经过有机层间绝缘层2072的边缘；所述VDD信号走线212与其相邻的所述VSS信号走线213之间的距离为D2；位于所述VDD信号走线212与所述VSS信号走线213之间的部分所述有机层间绝缘层2072的边缘形状通过蚀刻设置为弓形。此时，所述VDD信号走线212与其相邻的所述VSS信号走线21之间的部分所述有机层间绝缘层2072的边缘长度大于所述VDD信号走线212或所述VSS信号走线213的线宽。
本申请OLED显示装置实施例二将位于所述VDD信号走线212与其相邻的所述VSS信号走线213之间的部分所述有机层间绝缘层2072的边缘形状设置为弓形，增加了所述有机膜层2072边缘处的所述源漏极金属层208的残留路径，此路径内只要任意位置的源漏极金属颗粒断开，就不会造成信号的短路问题，此种设计更有助于降低所述VDD信号走线212与所述VSS信号走线213之间的短路风险。
如图4所示，本申请还提供一种OLED显示装置的制造方法流程，所述方法包括：
S10，提供一基板，在所述基板表面制备柔性衬底501，之后在所述柔性衬底501表面依次制备阻挡层502以及缓冲层503，然后在所述缓冲层的表面制备有源层504，之后在所述缓冲层503的表面制备第一栅极绝缘层505，所述第一栅极绝缘层505完全覆盖所述有源层504，然后在所述第一栅极绝缘层505的表面制备第一栅极金属层506，第二栅极绝缘层507形成于所述第一栅极绝缘层505并完全覆盖所述第一栅极金属层506，在所述第二栅极绝缘层上507制备第二栅极金属层508，之后在所述第二栅极金属层508上制备无机层间绝缘层509。
具体的，所述S10还包括：
首先，提供一个绝缘基板，在所述绝缘基板的表面沉积一层柔性衬底501，所述柔性衬底501的材料为聚酰亚胺；之后，在所述柔性衬底501的表面使用物理气象沉积法依次沉积出阻挡层502以及缓冲层503，所述阻挡层502的材料为氮化硅或氧化硅其中的一种或两种；所述缓冲层503的材料为氮化硅或氧化硅其中的一种或两种；之后，在所述缓冲层503的表面形成一半导体层，以一道光罩微影蚀刻制程来定义出半导体层结构，形成有源层504；接着在所述缓冲层503表面沉积出第一栅极绝缘层505，所述第一栅极绝缘层505完全覆盖所述有源层504，所述第一栅极缓冲层505的材料为氮化硅或氧化硅；接着在所述第一栅极缓冲层505的表面以一道光罩微影蚀刻制程来定义出栅极导体结构，形成第一栅极金属层506，所述第一栅极金属层506的材料为金属钼；接着在所述第一栅极缓冲层505的表面沉积出第二栅极缓冲层507，所述第二栅极缓冲层507的材料与所述第一栅极缓冲层505的材料相同；然后在所述第二栅极缓冲层507的表面以一道光罩微影蚀刻制程来定义出一层栅极导体结构，形成第二栅极金属层508；所述第二栅极金属层508的材料为钼，最后在所述第二栅极金属层508上沉积出无机层间绝缘层509，如图5A所示。
S20，通过掩膜对所述阻挡层502、所述缓冲层503、所述第一栅极绝缘层505、所述第二栅极绝缘层507以及所述无机层间绝缘层509进行干法刻蚀，在非显示区域形成沟槽，所述沟槽暴露出所述柔性衬底501，在所述沟槽内填充形成有机层间绝缘层510。
具体的，所述S20还包括：
首先通过掩膜对所述阻挡层502、所述缓冲层503、所述第二栅极绝缘层507、所述第一栅极绝缘层505以及所述无机层间绝缘层509进行干法刻蚀，在非显示区域形成沟槽，所述沟槽暴露出所述柔性衬底501；所述沟槽贯穿所述无机层间绝缘层509、所述第二栅极绝缘层507、所述第一栅极绝缘层505、所述缓冲层503以及所述阻挡层502并止于所述柔性衬底501；之后，在所述沟槽内填充形成有机层间绝缘层510，所述有机层间绝缘510的材料为有机光阻，如图5B所示。
S30，将电源线在弯折区域内与其相邻的信号走线之间相互平行设置且分别经过所述有机层间绝缘层510的边缘，使得所述电源线和与其相邻的所述信号走线之间的部分所述有机层间绝缘层510一端的边缘长度大于或等于所述电源线的宽度。
具体的，所述S30还包括：
首先，在所述有机层间绝缘层510的表面上设置有多条信号走线，包括阵列基板行驱动信号线、电源线以及数据信号线，所述信号走线的材料为会延展性能较好的Ti/Al/Ti材料。之后，在弯折区域内，将所述电源线与其相邻的所述信号走线之间相互平行设置且分别经过所述有机层间绝缘层510的边缘，所述电源线和与其相邻的所述信号走线之间的部分所述有机层间绝缘层510的边缘长度大于或等于所述电源线的宽度；其中，所述电源线的线宽范围为700~800微米。
具体的，所述电源线包括VDD信号走线511以及VSS信号走线512，在所述弯折区域内，所述VDD信号走线511和与其相邻的所述VSS信号走线512或所述数据信号线之间相互平行设置且分别经过所述有机层间绝缘层510的边缘。
优选地，所述VDD信号走线511与其相邻的所述VSS信号走线512的距离D的长度范围设置为3000~5000微米，即所述VDD信号走线511与其相邻的所述VSS信号走线512之间的部分所述有机层间绝缘层510的边缘长度大于所述VDD信号走线212或所述VSS信号走线213的线宽。
优选地，位于所述VDD信号走线511与所述VSS信号走线512之间的部分所述有机层间绝缘层510的边缘形状通过蚀刻设置为弓形。此时，所述VDD信号走线511与其相邻的所述VSS信号走线512之间的部分所述有机层间绝缘层510的边缘长度大于所述VDD信号走线511或所述VSS信号走线512的线宽，如图5C所示。
S40，在所述无机层间绝缘层509的表面依次制备源漏极金属层513以及平坦化层514，所述平坦化层514完全覆盖所述源漏极金属层513，最后在所述平坦化层514的表面依次制备阳极金属层515、像素限定层516以及像素支撑层517，所述阳极金属层515的一部分与所述源漏极金属层513直接相连，最后去除基板。
具体的，所述S40还包括：
在所述无机层间绝缘层509的表面上形成一金属层，以一道光罩微影蚀刻制程来定义出源漏极导体层结构，形成源漏极金属层513；之后，在所述无机层间绝缘层509的表面沉积出一平坦化层514，所述平坦化层514完全覆盖所述源漏极金属层513；接着在所述平坦化层514的表面依次沉积出阳极金属层515、像素限定层516以及像素支撑层517，其中，所述阳极金属层515的一部分直接与所述源漏金属层513相连；最后，去除所述基板，如图5D所示。
本申请的有益效果为：本申请所提供的OLED显示装置及制备方法，将位于弯折区域的电源线和与其相邻的信号走线之间的部分所述有机层间绝缘层一端的边缘长度设置为大于或等于所述电源线的宽度，增加了有机膜层边缘的源漏极金属层的残留路径，进一步减少了相邻信号走线之间的短路风险。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (10)

  1. 一种OLED显示装置，其中，所述OLED显示装置包括显示区域，以及位于所述显示区域一端的非显示区域；所述非显示区域内设置有多条信号走线、弯折区域以及绑定区域，每一所述信号走线的一端连接所述显示区域，每一所述信号走线的相对另一端经过所述弯折区域延伸至所述绑定区域，位于所述弯折区域的信号走线至少包括电源线以及数据信号线，所述弯折区域内还设置一有机层间绝缘层，所述电源线与其相邻的所述信号走线之间相互平行设置且分别经过所述有机层间绝缘层的边缘；
    其中，在所述弯折区域内，所述电源线和与其相邻的所述信号走线之间的部分所述有机层间绝缘层的边缘长度大于或等于所述电源线的宽度。
  2. 根据权利要求1所述的OLED显示装置，其中，所述电源线包括VDD信号走线以及VSS信号走线，在所述弯折区域内，所述VDD信号走线和与其相邻的所述VSS信号走线或所述数据信号线之间相互平行设置且分别经过所述有机层间绝缘层的边缘。
  3. 根据权利要求2所述的OLED显示装置，其中，位于弯折区域内的所述VDD信号走线和与其相邻的所述VSS信号走线的间距范围为3000-5000微米。
  4. 根据权利要求2所述的OLED显示装置，其中，在所述弯折区域内，所述VDD信号走线和与其相邻的所述VSS信号走线之间的部分所述有机层间绝缘层的边缘形状设置为弓形。
  5. 根据权利要求1所述的OLED显示装置，其中，所述OLED显示装置位于所述弯折区域的部分包括柔性衬底、阻挡层、缓冲层、第一栅极绝缘层、第二栅极绝缘层、无机层间绝缘层、所述有机层间绝缘层、源漏极金属层、平坦化层、像素限定层以及像素支撑层，所述有机层间绝缘层贯穿所述无机层间绝缘层、所述第二栅极绝缘层、所述第一栅极绝缘层、所述缓冲层以及所述阻挡层并与所述柔性衬底相连。
  6. 根据权利要求5所述的OLED显示装置，其中，所述柔性衬底的材料为聚酰亚胺，所述缓冲层的材料为氮化硅或氧化硅其中的一种或两种，所述有机层间绝缘层的材料为有机光阻，所述第一栅极缓冲层的材料为氮化硅或氧化硅，所述第二栅极缓冲层的材料与所述第一栅极缓冲层的材料相同，所述源漏极金属层的材料为钛或钛铝合金。
  7. 一种OLED显示装置的制备方法，其中，包括：
    S10，提供一基板，在所述基板表面制备柔性衬底，之后在所述柔性衬底表面依次制备阻挡层以及缓冲层，然后在所述缓冲层的表面制备有源层，之后在所述缓冲层的表面制备第一栅极绝缘层，所述第一栅极绝缘层完全覆盖所述有源层，然后在所述第一栅极绝缘层的表面制备第一栅极金属层，第二栅极绝缘层形成于所述第一栅极绝缘层并完全覆盖所述第一栅极金属层，在所述第二栅极绝缘层上制备第二栅极金属层，之后在所述第二栅极金属层上制备无机层间绝缘层；
    S20，通过掩膜对所述阻挡层、所述缓冲层、所述第一栅极绝缘层、所述第二栅极绝缘层以及所述无机层间绝缘层进行干法刻蚀，在非显示区域形成沟槽，所述沟槽暴露出所述柔性衬底，在所述沟槽内填充形成有机层间绝缘层；
    S30，将电源线在弯折区域内与其相邻的信号走线之间相互平行设置且分别经过所述有机层间绝缘层的边缘，使得所述电源线和与其相邻的所述信号走线之间的部分所述有机层间绝缘层一端的边缘长度大于或等于所述电源线的宽度；
    S40，在所述无机层间绝缘层的表面依次制备源漏极金属层以及平坦化层，所述平坦化层完全覆盖所述源漏极金属层，最后在所述平坦化层的表面依次制备阳极金属层、像素限定层以及像素支撑层，所述阳极金属层的一部分与所述源漏极金属层直接相连，最后去除基板。
  8. 根据权利要求7所述的OLED显示装置的制备方法，其中，所述S30中，所述电源线包括VDD信号走线以及VSS信号走线，在所述弯折区域内，所述VDD信号走线和与其相邻的所述VSS信号走线或所述数据信号线之间相互平行设置且分别经过所述有机层间绝缘层的边缘。
  9. 根据权利要求8柔性显示面板的制造方法，其中，位于弯折区域内的所述VDD信号走线和与其相邻的所述VSS信号走线的间距范围为3000-5000微米。
  10. 根据权利要求8所述的OLED显示装置的制备方法，其中，在所述弯折区域内，所述VDD信号走线和与其相邻的所述VSS信号走线之间的部分所述有机层间绝缘层的边缘形状设置为弓形。
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