WO2020114053A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2020114053A1
WO2020114053A1 PCT/CN2019/108660 CN2019108660W WO2020114053A1 WO 2020114053 A1 WO2020114053 A1 WO 2020114053A1 CN 2019108660 W CN2019108660 W CN 2019108660W WO 2020114053 A1 WO2020114053 A1 WO 2020114053A1
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Prior art keywords
fan
layer
line
out line
array substrate
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PCT/CN2019/108660
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English (en)
French (fr)
Inventor
曾超
黄炜赟
黄耀
高永益
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/651,411 priority Critical patent/US11257851B2/en
Priority to EP19858705.7A priority patent/EP3893278A4/en
Publication of WO2020114053A1 publication Critical patent/WO2020114053A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate, a manufacturing method thereof, and a display device.
  • the fanout area is the main constituent unit of the lower border of the display panel, accounting for 64% of the entire lower border of the display panel.
  • the pitch between Fanout traces is necessary to reduce the pitch between Fanout traces to compress the length of Fanout in the Y direction.
  • An embodiment of the present disclosure provides an array substrate including: a base substrate; and a display area and a fan-out area provided on the base substrate, a signal line is provided in the display area, and the fan-out area includes A first fan-out line layer, a second fan-out line layer, and one or more spacer layers between the first fan-out line layer and the second fan-out line layer, provided in the first fan-out line layer A first fan-out line, a second fan-out line is provided in the second fan-out line layer, the signal line is connected to the first fan-out line or the second fan-out line, and the spacer layer is made of an insulating material; wherein, The orthographic projection of the first fan-out line on the base substrate and the orthographic projection of the second fan-out line on the base substrate at least partially overlap.
  • the signal line includes a first signal line connected to the first fan-out line and a second signal line connected to the second fan-out line.
  • the array substrate includes a light shielding layer for blocking light incident from the base substrate into the array substrate, the second fan-out line layer and the light shielding layer of the array substrate Made of the same material and located on the same layer.
  • the array substrate includes at least one gate line layer, and the first fan-out line layer and one of the at least one gate line layer are made of the same material and are disposed on the same layer.
  • the signal line includes a data line
  • the array substrate further includes a data line layer and a patch cord layer
  • the data line is disposed in the data line layer
  • the patch cord layer is disposed on the Between the data line layer and the first fan-out line layer or the second fan-out line layer
  • the transfer line layer includes a transfer line, the data line is electrically connected to the transfer line and the transfer line is connected to the The first fan-out line or the second fan-out line is electrically connected.
  • the signal line further includes a gate line; the transfer line layer and the gate line are made of the same material and arranged on the same layer.
  • the array substrate includes a first gate line layer and a second gate line layer
  • the transfer line layer and the first gate line layer are made of the same material and arranged on the same layer
  • the fan The output area includes at least one buffer layer and a first gate insulating layer between the transfer line layer and the second fan-out line layer, and a second gate insulation between the data line layer and the transfer line layer Layer and at least one interlayer dielectric layer
  • the data line is electrically connected to the transfer line through a first conductive plug penetrating the second gate insulating layer and at least one interlayer dielectric layer
  • the transfer line passes through The at least one buffer layer and the second conductive plug of the first gate insulating layer are electrically connected to the second fan-out line.
  • the array substrate includes a first gate line layer and a second gate line layer
  • the transfer line layer and the second gate line layer are made of the same material and arranged on the same layer
  • the fan The output area includes at least one buffer layer, a first gate insulating layer and a second gate insulating layer between the transfer wiring layer and the second fan-out line layer, and between the data line layer and the transfer wiring layer
  • At least one interlayer dielectric layer the data line is electrically connected to the transfer line through a third conductive plug penetrating the at least one interlayer dielectric layer, and the transfer line passes through the at least one buffer layer, the first The fourth conductive plug of a gate insulating layer and the second gate insulating layer is electrically connected to the second fan-out line.
  • the signal line includes a data line
  • the array substrate further includes a data line layer
  • the data line is disposed in the data line layer
  • the data line passes through the fifth conductive plug and the first A fan-out line or a second fan-out line is electrically connected
  • the fifth conductive plug penetrates one or more insulating layers between the data line layer and the first fan-out line layer or the second fan-out line layer.
  • the orthographic projection of the first fan-out line on the base substrate completely overlaps the orthographic projection of the second fan-out line on the base substrate.
  • the spacer layer includes a buffer layer or at least one gate insulating layer or a combination of the buffer layer and at least one gate insulating layer.
  • the total thickness of the one or more spacer layers is greater than 500 nm.
  • the first fan-out line layer includes a plurality of the first fan-out lines
  • the second fan-out line layer includes a plurality of the second fan-out lines
  • the nodes of the plurality of first fan-out lines The pitch and the pitch of the plurality of second fan-out lines are between 1.5 and 3.0 microns.
  • the capacitance per unit area between the first fan-out line and the second fan-out line that at least partially overlap each other is less than 8 ⁇ 10 ⁇ 5 picofarads/square micrometer.
  • An embodiment of the present disclosure provides a display device including the array substrate described in any of the embodiments described above.
  • An embodiment of the present disclosure also provides a method of manufacturing an array substrate, including: forming a second fan-out line layer including a second fan-out line on a base substrate; and separating the second fan-out line layer from the base substrate on the second fan-out line layer One or more spacer layers are formed on one side; a first fan-out line layer including a first fan-out line is formed on the side of the spacer layer away from the base substrate, and the first fan-out line is on the base substrate There is at least partial overlap between the projection and the orthographic projection of the second fan-out line on the base substrate; a signal line layer including signal lines is formed on a side of the first fan-out line layer away from the base substrate, the signal line Connected to the first fan-out line or the second fan-out line; wherein, the spacer layer is made of an insulating material; the signal line is formed in the display area of the array substrate, and the first fan-out line and the second fan-out line It is formed in the fan-out area of the array substrate.
  • the forming the second fan-out line layer including the second fan-out line on the base substrate further includes: forming a first metal thin film on the base substrate; and patterning the first metal thin film Chemical treatment to form a light shielding layer and the second fan-out line layer; the light shielding layer is used to block light incident from the base substrate into the array substrate.
  • the signal line includes a gate line
  • the method further includes: Forming a second metal thin film on the top; patterning the second metal thin film, forming a gate line layer in the display area, and forming a transfer wiring layer at the boundary between the display area and the fan-out area.
  • the orthographic projection of the first fan-out line on the base substrate overlaps the orthographic projection of the second fan-out line on the base substrate.
  • the spacer layer includes a buffer layer or at least one gate insulating layer or a combination of the buffer layer and at least one gate insulating layer.
  • FIG. 1 is a schematic diagram of an array substrate according to some embodiments of the present disclosure.
  • FIG. 2 is a schematic cross-sectional structure diagram of the fan-out area of the array substrate along the AA' direction in FIG. 1 according to some embodiments of the present disclosure
  • FIG. 3 is a schematic diagram of the principle of compressing the pitch of the trace to narrow the lower border in the Y direction;
  • FIG. 4 is a schematic cross-sectional structure diagram of the fan-out area of the array substrate along the AA' direction in FIG. 1 according to other embodiments of the present disclosure
  • FIG. 5A is a schematic cross-sectional structural view of the fan-out area of the array substrate along the BB' direction in FIG. 1 according to other embodiments of the present disclosure
  • 5B is a schematic cross-sectional structural view of the fan-out area of the array substrate along the BB' direction in FIG. 1 according to still other embodiments of the present disclosure
  • 5C is a schematic cross-sectional structural view of the fan-out area of the array substrate along the BB' direction in FIG. 1 according to still other embodiments of the present disclosure
  • FIG. 6A is a schematic cross-sectional structure diagram of the fan-out area of the array substrate along the BB' direction in FIG. 1 according to other embodiments of the present disclosure
  • FIG. 6B is a schematic cross-sectional structural view of the fan-out area of the array substrate along the BB' direction in FIG. 1 according to still other embodiments of the present disclosure.
  • FIG. 7 is a schematic flowchart of a method of manufacturing an array substrate according to some embodiments of the present disclosure.
  • An embodiment of the present disclosure proposes an array substrate, which can reduce the width of the display panel frame to a certain extent.
  • FIG. 1 shows a schematic diagram of an array substrate.
  • the array substrate includes a display area 10 and a fan-out area 20.
  • a signal line is formed in the display area, the signal line includes a data line 11, a first gate line 12, and a second gate line 13, the data line 11 is used to input a driving signal, and the first gate line 12
  • the second gate line 13 is used to form a storage capacitor, for example, for connecting a gate of a thin film transistor (TFT) to provide a scan signal.
  • TFT thin film transistor
  • the signal lines in the display area 10 can realize signal transmission with external integrated circuits (ICs) through the fan-out lines in the fan-out area 20, for example.
  • ICs integrated circuits
  • the external integrated circuit is usually implemented by an independent circuit board 70, and there is a bending area 80 between the circuit board 70 and the fan-out area 20. By bending the bending area 80, the circuit board 70 can be folded in The display area and the fan-out area of the display panel are below, so as not to occupy the border width.
  • FIG. 2 is a cross-sectional view of the fan-out area 20 in FIG. 1 in the direction AA′. As shown in FIG. 2, in the fan-out area, a first fan-out line 41a and a second fan-out line 42a are provided.
  • the signal The line may include a first signal line connected to the first fan-out line 41a and a second signal line connected to the second fan-out line 42a); the first fan-out line layer where the first fan-out line 41a is located and the second Between the second fan-out line layer where the fan-out line 42a is located, one or more spacer layers 55 can be provided; the spacer layer 55 is made of an insulating material and can be used to make the first fan-out line layer and the second fan-out line layer Maintain a large interlayer spacing; the orthographic projection of the first fan-out line 41a on the base substrate 40 and the orthographic projection of the second fan-out line 42a on the base substrate 40 at least partially overlap.
  • the array panel shown in FIG. 2 further includes a first insulating layer 43' and a second insulating
  • the array substrate provided by the present disclosure increases the interlayer spacing between the first fan-out line layer and the second fan-out line layer by reducing the first fan
  • the capacitance formed between the outlet line and the second fan-out line thereby reducing crosstalk problems and reducing power consumption; at the same time, the reduction in the capacitance formed between the first fan-out line and the second fan-out line also makes the first fan
  • the fanout line (Fanout) in the fanout area usually has an inclined section and a vertical section.
  • the fanout line When the pitch of the fanout line is reduced, the fanout line will be compressed toward the middle, and the inclined section of the fanout line will The X and Y directions (refer to FIG. 1) are compressed, which compresses the length of the fan-out line in the Y direction, thereby narrowing the width of the lower frame of the array substrate.
  • the orthographic projection of the first fan-out line 41 b on the base substrate 40 and the orthographic projection of the corresponding second fan-out line 42 b on the base substrate 40 overlapping. Because the capacitance formed between the first fan-out line and the second fan-out line is reduced by increasing the interlayer spacing, thereby reducing the crosstalk problem, so that the first fan-out line and the second fan-out line can form a complete overlap , Further reducing the trace spacing, thereby further reducing the width of the lower border.
  • the pitch of the wiring can be reduced by about 17% compared with the existing design, and the length of the fan-out area in the Y direction can be compressed by about 20% compared with the existing design.
  • the spacer layer 55 may include a buffer layer (Buffer).
  • Buffer buffer layer
  • the material of the buffer layer is not limited, but it is usually an insulating material, such as SiNX or SiOX. Since the buffer layer is usually disposed close to the base substrate 40, when the second fan-out line 42e/42f/42g is below the buffer layer and the first fan-out line 41e/41f (refer to FIGS. 6A and 6B) is above the buffer layer At this time, it can be ensured that the interlayer spacing between the first fan-out line and the second fan-out line is sufficiently large to achieve the purpose of reducing the capacitance between the two.
  • a layer of light-shielding substance usually formed on the base substrate 40 is used to form a light-shielding layer, and the light-shielding layer LS is used to block the light Light incident on the back of the array substrate (e.g., incident into the array substrate from the base substrate) to prevent the light from adversely affecting the array substrate (e.g., preventing light from irradiating the thin film transistor (TFT) array of the array substrate) Active layer, thereby preventing the active layer from generating photo-generated carriers due to illumination).
  • TFT thin film transistor
  • the second fan-out line layer 42e, 42f or 42g is also provided on the base substrate 40, that is, the second fan-out line layer 42e, 42f or 42g and the light shielding layer of the array substrate may Made of the same material and located on the same layer.
  • the second fan-out line layer 42e, 42f or 42g itself can also be regarded as a part of the light-shielding layer LS and also has a light-shielding effect. Because the light-shielding layer LS is usually directly placed on the base substrate and belongs to the lowest layer structure, when one layer of the fan-out line layer is co-layered with the LS, it can make the fan-out line between this layer and another layer The interval between layers is large enough.
  • the second fan-out line 42e, 42f, or 42g is formed by patterning the shading layer LS in the fan-out region 20;
  • the interlayer spacing between it and the fan-out line of the other layer can be increased to further reduce the crosstalk problem; on the other hand, it can simultaneously exist in
  • the shading layer (metal material, usually Mo) in the fan-out area is more fully utilized.
  • the display area in the array substrate has a first gate line 12 for forming a gate of a thin film transistor (TFT) and a second for forming a storage capacitor
  • the gate line 13 can be used to form the fan-out lines in the fan-out area at the same time when the two kinds of gate lines are fabricated.
  • the first gate line used to form the gate of the TFT is used as the first fan-out line 41e in the fan-out area, together with the second fan-out line 42e, 42f, or 42g shown in FIG. 5A, 5B, or 5C. , Together forming the fan-out line in the fan-out area.
  • FIG. 6A the first gate line used to form the gate of the TFT is used as the first fan-out line 41e in the fan-out area, together with the second fan-out line 42e, 42f, or 42g shown in FIG. 5A, 5B, or 5C. , Together forming the fan-out line in the fan-out area.
  • the second gate line used to form the storage capacitor is used as the first fan-out line 41f in the fan-out area, together with the second fan-out line 42e, 42f, or 42g shown in FIG. 5A, 5B, or 5C.
  • the first gate line or the second gate line When the first gate line or the second gate line is formed as the first fan-out line, it can be used as the two fan-out lines in the fan-out area with the aforementioned second fan-out line formed by patterning the light-shielding layer LS, and Between the first fan-out line layer where the first fan-out line is located and the second fan-out line layer where the second fan-out line is located, it usually includes a first buffer layer 44, a second buffer layer 45, and a first gate insulating layer 46 and so on (as shown in FIG.
  • these hierarchical structures may belong to a part of the spacer layer, in this way, the use of buffer layer, gate insulating layer and other levels
  • the thickness of the structure reduces the capacitance between the first fan-out line and the second fan-out line to avoid crosstalk between signals between the first fan-out line and the second fan-out line. If it is necessary to further reduce the capacitance between the first fan-out line and the second fan-out line, the thickness of the hierarchical structure such as the buffer layer and the gate insulating layer can also be appropriately increased.
  • the total thickness of the one or more spacer layers may be greater than 500 nm.
  • the capacitance per unit area between the first fan-out line and the second fan-out line that at least partially overlap each other is less than 8 ⁇ 10 ⁇ 5 picofarads/square micrometer. The design of the total thickness of the spacer layer and the capacitance per unit area can effectively prevent signals between the first fan-out line and the second fan-out line from crosstalking with each other.
  • the first fan-out line layer includes multiple first fan-out lines
  • the second fan-out line layer includes multiple second fan-out lines
  • the pitch of the multiple first fan-out lines and the The pitch of the plurality of second fan-out lines may be between 1.5 and 3.0 microns.
  • the main function of the fan-out area is to connect the data line 11 or the first gate line 12 of the circuit of the display area to an external integrated circuit. Therefore, it is necessary to connect the data line 11 or the first gate line 12 to an external IC through a fan-out line.
  • the data lines and the fan-out lines may be directly connected through the vias.
  • the array substrate may further include a transfer wiring layer, the transfer wiring layer is disposed between the data line layer where the data line is located and the first fan-out line layer, or the transfer wiring The layer is provided between the data line layer where the data line is located and the second fan-out line layer; the transfer line layer includes transfer lines 60a/60b (as shown in FIGS. 5A and 5B), and the data line passes through the The patch cord is connected to the first fan-out line or the second fan-out line.
  • the transfer wiring layer includes transfer lines 60a/60b (as shown in FIGS. 5A and 5B), and the data line passes through the The patch cord is connected to the first fan-out line or the second fan-out line.
  • a gate line (which may be the first gate line 12 or the second gate line 13) is formed; the transfer line layer and the gate line where the gate line is located
  • the layers are the same layer. In this way, the transfer line is formed at the same time by the process when manufacturing the gate line, thereby saving process steps and improving production efficiency.
  • the transfer line 60a may be connected to the first gate line used to form the gate of the TFT Made of the same material and arranged in the same layer, the data line 50 is connected to the second fan-out line 42e through the transfer line 60a. While forming the gate in the display area, a corresponding transfer line 60a may be formed at the boundary of the display area 10 and the fan-out area 20 for electrically connecting the data line 50 and the second fan-out line 42e.
  • the array substrate may include a first gate line layer where a first gate line is located and a second gate line layer where a second gate line is located, and the transfer wiring layer may be in contact with the first gate line layer Made of the same material and arranged on the same layer.
  • the fan-out area 20 includes at least one buffer layer (eg, the first buffer layer 44 and the second buffer layer) between the transfer wiring layer where the patch cord 60a is located and the second fan out line layer where the second fan-out line 42e is located 45) and the first gate insulating layer 46 and the second gate insulating layer 47 and at least one interlayer dielectric layer between the data line layer and the transfer wiring layer.
  • the data line 50 is electrically connected to the transfer line 60a through the first conductive plug 61 penetrating the second gate insulating layer 47 and at least one interlayer dielectric layer, and the transfer line 60a passes through the at least one buffer layer and The second conductive plug 62 of the first gate insulating layer 46 is electrically connected to the second fan-out line 42e.
  • the transfer line 60b may be the same as the second gate line used to form the storage capacitor
  • the material is made of the same layer and is used to electrically connect the data line 50 and the second fan-out line 42f.
  • the patch cord 60b may be made of the same material and arranged in the same layer as the second gate line, and the fan-out area 20 may include the patch cord layer and the second layer where the patch cord 60b is located At least one buffer layer (eg, the first buffer layer 44 and the second buffer layer 45) between the second fan-out line layer where the fan-out line 42e is located, the first gate insulating layer 46 and the second gate insulating layer 47, and At least one interlayer dielectric layer between the data line layer and the transfer line layer, the data line 50 is electrically connected to the transfer line 60b through a third conductive plug 63 penetrating the at least one interlayer dielectric layer and The patch cord 60b is electrically connected to the second fan-out line 42f through a fourth conductive plug 64 penetrating the at least one buffer layer, the first gate insulating layer 46, and the second gate insulating layer 47.
  • the buffer layer eg, the first buffer layer 44 and the second buffer layer 45
  • the data line 50 is electrically connected to the transfer
  • the data line can be directly connected to the second fan-out line.
  • the data line 50 and the second fan-out line 42g are directly connected through vias.
  • the data line 50 is electrically connected to the first fan-out line or the second fan-out line through a fifth conductive plug 65, and the fifth conductive plug 65 penetrates the data line layer and the first One or more insulating layers between the fan-out line layer or the second fan-out line layer.
  • the external integrated circuit is usually implemented by an independent circuit board 70, and there is also a bending region 80 between the circuit board 70 and the fan-out region 20.
  • the bending by the bending region 80 So that the circuit board 70 can be received under the display area and the fan-out area of the display panel, so as not to occupy the width of the frame.
  • the fan-out area is used to provide a transition area for the connection between the display area and the external integrated circuit, the fan-out line of the fan-out area 20 needs to be connected to the data line of the bending area 80 in addition to the data line of the display area 10 In order to realize the signal transmission of the display area and the data line of the external circuit.
  • the connection method of the fan-out line of the fan-out area 20 and the data line of the bending area 80 can also be implemented by any one of the methods in FIGS. 5A to 5C.
  • FIGS. 5A, 5B, and 5C show the connection between the second fan-out line and the data line formed by the light-shielding layer LS.
  • 6A and 6B respectively show that the first fan-out line 41e and the first gate line are made of the same material and are arranged in the same layer and the first fan-out line 41f and the second gate line are made of the same material and are arranged in the same layer , The connection mode of the first fan-out line and the data line.
  • any structure shown in FIGS. 5A to 5C and the structure of FIG. 6A or 6B may be used.
  • FIGS. 5A to 5C mainly show the wiring of the boundary position between the display area 10 and the fan-out area 20 (the part between the two vertical dotted lines in the figure), and the data line and the fan-out line are completed.
  • the connection between, in the main part of the fan-out area there may be overlap or even complete between the orth projection of the first fan-out line on the base substrate and the orth projection of the second fan-out line on the base substrate Overlap, as shown in Figure 2 and Figure 4, this can be achieved through the patterning process.
  • the hierarchical structure in FIGS. 5A-5C, 6A, and 6B includes the base substrate 40.
  • the array substrate may further include the first buffer layer 44 and the second The buffer layer 45, the first gate insulating layer (GI) 46, the second gate insulating layer 47, the first interlayer dielectric layer (ILD) 43, and the second interlayer dielectric layer 48.
  • GI gate insulating layer
  • ILD interlayer dielectric layer
  • one of the buffer layers is used to isolate metal ions in the base substrate 40 made of glass to prevent the metal ions from diffusing into the TFT device, and the other buffer layer is used for heat preservation to It is favorable for silicon (Si) to form large crystalline grains.
  • the first gate insulating layer 46 is used to insulate the first gate line layer (eg, metal layer) where the first gate line 12 is located, and the second gate insulating layer 47 is used to implement the second gate line 13 where Insulation of the second gate line layer (eg metal layer).
  • first gate line layer eg, metal layer
  • second gate insulating layer 47 is used to implement the second gate line 13 where Insulation of the second gate line layer (eg metal layer).
  • the present disclosure aims to make the length of the display panel in the Y direction as small as possible by balancing the pitch of the trace and the capacitance between the traces, thereby achieving the purpose of achieving a narrow bezel As long as such an objective can be achieved, and the disclosed idea is basically consistent with the present disclosure, it can be considered as falling within the protection scope of the present disclosure.
  • the data line is used as an example for description, but it can be known that the gate line also needs to perform signal transmission with an external IC circuit through a fan-out line. Therefore, for the gate line, The connection with the fan-out line can be completed by referring to the foregoing data line embodiment, which will not be repeated here.
  • the array substrate includes two types of gate lines (ie, the first gate line 12 and the second gate line 13) as an example for description, but it can be known that there are only one type of array substrate
  • the structure of the gate line that is, only including the gate line for receiving the scan signal
  • the embodiments of the present disclosure also provide a display device, which can reduce the width of the display panel frame to a certain extent.
  • the display device includes any embodiment or combination of embodiments of the array substrate as described above.
  • the display device provided by the present disclosure increases the interlayer spacing between the first fan-out line layer and the second fan-out line layer by interposing a spacer layer between them, thereby reducing the first
  • the capacitance formed between the fan-out line and the second fan-out line reduces crosstalk problems and reduces power consumption; meanwhile, the reduction in the capacitance formed between the first fan-out line and the second fan-out line also makes the first There may be some overlap between the fan-out line and the second fan-out line, thereby reducing the routing pitch and compressing the length of the fan-out area in the Y direction, which helps to achieve a narrow border.
  • the display device in this embodiment may be any product or component with a display function such as electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, and navigator.
  • the embodiments of the present disclosure also provide a method for manufacturing an array substrate, which can reduce the frame width of the display panel to a certain extent.
  • the manufacturing method of the array substrate includes:
  • Step 91 forming a second fan-out line layer including a second fan-out line on the base substrate;
  • Step 92 Form one or more spacer layers on the side of the second fan-out line layer away from the base substrate;
  • Step 93 Form a first fan-out line layer including a first fan-out line on the side of the spacer layer away from the base substrate, an orthographic projection of the second fan-out line on the base substrate and the first fan-out line There is at least partial overlap in the orthographic projection on the base substrate;
  • Step 94 forming a signal line layer including a signal line on a side of the first fan-out line layer away from the base substrate, the signal line being connected to the first fan-out line or the second fan-out line;
  • the spacer layer is made of insulating material; the signal line is formed in the display area of the array substrate, and the first and second fan-out lines are formed in the fan-out area of the array substrate.
  • the method for manufacturing an array substrate increases the interlayer spacing between the first fan-out line layer and the second fan-out line layer by interposing a spacer layer, thereby reducing The capacitance formed between the first fan-out line and the second fan-out line, thereby reducing the crosstalk problem and reducing the power consumption; at the same time, the reduction in the capacitance formed between the first fan-out line and the second fan-out line also makes all There may be some overlap between the first fan-out line and the second fan-out line, thereby reducing the routing pitch, compressing the length of the fan-out area in the Y direction, and helping to achieve a narrow border.
  • step 91 in the method for manufacturing an array substrate may further include the following steps:
  • the light-shielding layer is used to block light incident from the base substrate into the array substrate, for example, to prevent all The light irradiates the active layer in the thin film transistor array of the array substrate.
  • the shading layer material By using the shading layer material to make one of the fan-out lines, the hierarchical structure between it and another fan-out line can be used as the spacer layer, so that the interlayer spacing can be increased (because the shading layer is directly placed on the base substrate On the bottom of the hierarchy) to further reduce crosstalk issues.
  • the light-shielding layer (metal material) present in the fan-out area can be more fully utilized.
  • the signal line further includes a gate line
  • the method for manufacturing the array substrate, after the step 92 may further include the following steps:
  • the gate line layer and the transfer line layer can be simultaneously formed through a patterning process, which simplifies the process and improves production efficiency.
  • the gate line includes a first gate line 12 for forming the gate of the TFT and a second gate line 13 for forming the storage capacitor in the display area of the array substrate.
  • the transfer wiring layer can be simultaneously manufactured.
  • the orthographic projection of the first fan-out line overlaps the orthographic projection of the second fan-out line. Because the crosstalk problem is reduced, the first fan-out line and the second fan-out line can form an overlap, thereby reducing the line spacing, thereby reducing the width of the lower frame.
  • the spacer layer may include a buffer layer or at least one gate insulating layer or a combination of the buffer layer and at least one gate insulating layer.
  • the buffer layer can isolate impurities on the base substrate into other layers, and the material of the buffer layer is not limited, for example, it can be SiN X or SiO X. Since the buffer layer is usually provided at a level close to the base substrate, when the second fan-out line is below the buffer layer and the first fan-out line is above the buffer layer, the gap between the first fan-out line and the second fan-out line can be ensured The interval between layers is large enough to reduce the capacitance between the two.
  • the interlayer spacing between the first fan-out line and the second fan-out line can be increased to further reduce Crosstalk issues.
  • layer forming operations include, but are not limited to, (chemical phase, physical phase) deposition film formation, (magnetron) sputtering film formation, and those skilled in the art can understand that after forming each layer, Corresponding patterns can be further formed on it as needed, which will not be repeated in this disclosure.
  • the array substrate, the manufacturing method thereof, and the display device provided by the embodiments of the present disclosure increase the interlayer spacing between the first fan-out line layer and the second fan-out line layer by interposing a spacer layer, thereby reducing the number of The capacitance formed between one fan-out line and the second fan-out line reduces crosstalk problems and reduces power consumption; meanwhile, the reduction in the capacitance formed between the first fan-out line and the second fan-out line also makes the first There may be some overlap between one fan-out line and the second fan-out line, thereby reducing the routing pitch, compressing the length of the fan-out area in the Y direction, and helping to achieve a narrow border.
  • the source and drain electrodes and the active layer are in different layers, the substrate thickness is large and the manufacturing process is complicated.
  • the source electrode, the drain electrode, the data line and the active layer can be prepared in the same layer by doping copper nitride, thereby reducing the thickness of the array substrate and simplifying the fabrication of the array substrate Craftsmanship.

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Abstract

一种阵列基板，包括：衬底基板(40)；以及设置在衬底基板上的显示区域(10)和扇出区域(20)，在所述显示区域(10)中设置有信号线，所述扇出区域(20)包括第一扇出线层、第二扇出线层和在所述第一扇出线层与所述第二扇出线层之间的一个或更多个间隔层(55)，在所述第一扇出线层中设置有第一扇出线(41a)，在所述第二扇出线层中设置有第二扇出线(42a)，所述信号线与所述第一扇出线(41a)或第二扇出线(42a)连接，所述间隔层(55)采用绝缘材料制作；其中，所述第一扇出线(41a)在衬底基板(40)上的正投影与所述第二扇出线(42a)在衬底基板(40)上的正投影至少存在部分重叠。还提供了一种阵列基板的制造方法和显示装置。

Description

阵列基板及其制造方法、显示装置
相关申请的交叉引用
本申请要求于2018年12月6日递交中国专利局的、申请号为201811486997.0的中国专利申请的权益，该申请的全部内容以引用方式并入本文。
技术领域
本公开涉及显示技术领域，特别是指一种阵列基板及其制造方法、显示装置。
背景技术
现如今，减小显示面板下边框，提高显示的屏占比是显示面板发展的方向之一。现有设计中，在模组工艺(MDL)中的弯折工艺(bending)之后，扇出区(Fanout)是显示面板下边框的主要构成单元，占显示面板整个下边框的64％。为了减小显示面板下边框的宽度，则需要减小Fanout走线之间的间距(pitch)，以压缩Fanout在Y方向的长度。
公开内容
本公开的实施例提供了一种阵列基板，包括：衬底基板；以及设置在衬底基板上的显示区域和扇出区域，在所述显示区域中设置有信号线，所述扇出区域包括第一扇出线层、第二扇出线层和在所述第一扇出线层与所述第二扇出线层之间的一个或更多个间隔层，在所述第一扇出线层中设置有第一扇出线，在所述第二扇出线层中设置有第二扇出线，所述信号线与所述第一扇出线或第二扇出线连接，所述间隔层采用绝缘材料制作；其中，所述第一扇出线在衬底基板上的正投影与所述第二扇出线在衬底基板上的正投影至少存在部分重叠。
在一些实施例中，所述信号线包括与第一扇出线连接的第一信号线和与第二扇出线连接的第二信号线。
在一些实施例中，所述阵列基板包括遮光层，所述遮光层用于遮挡从所述衬底基板入射到阵列基板中的光线，所述第二扇出线层与所述阵列基板的遮光层由相同材料制成且位于同一层。
在一些实施例中，所述阵列基板包括至少一个栅线层，所述第一扇出线层与所述 至少一个栅线层中的一个栅线层由相同材料制成且设置于同一层。
在一些实施例中，所述信号线包括数据线，所述阵列基板还包括数据线层和转接线层，所述数据线设置于所述数据线层中，所述转接线层设置在所述数据线层与所述第一扇出线层或所述第二扇出线层之间；所述转接线层包括转接线，所述数据线与所述转接线电连接且所述转接线与所述第一扇出线或第二扇出线电连接。
在一些实施例中，所述信号线还包括栅线；所述转接线层与所述栅线由相同材料制成且布置在同一层。
在一些实施例中，所述阵列基板包括第一栅线层和第二栅线层，所述转接线层与所述第一栅线层由相同材料制成且布置在同一层，所述扇出区域包括位于所述转接线层和第二扇出线层之间的至少一个缓冲层和第一栅极绝缘层以及位于所述数据线层和所述转接线层之间的第二栅极绝缘层和至少一个层间介质层，所述数据线通过贯穿所述第二栅极绝缘层和至少一个层间介质层的第一导电塞与所述转接线电连接且所述转接线通过贯穿所述至少一个缓冲层和第一栅极绝缘层的第二导电塞与所述第二扇出线电连接。
在一些实施例中，所述阵列基板包括第一栅线层和第二栅线层，所述转接线层与所述第二栅线层由相同材料制成且布置在同一层，所述扇出区域包括位于所述转接线层和第二扇出线层之间的至少一个缓冲层、第一栅极绝缘层和第二栅极绝缘层以及位于所述数据线层和所述转接线层之间的至少一个层间介质层，所述数据线通过贯穿所述至少一个层间介质层的第三导电塞与所述转接线电连接且所述转接线通过贯穿所述至少一个缓冲层、第一栅极绝缘层和第二栅极绝缘层的第四导电塞与所述第二扇出线电连接。
在一些实施例中，所述信号线包括数据线，所述阵列基板还包括数据线层，所述数据线设置于所述数据线层中，所述数据线通过第五导电塞与所述第一扇出线或第二扇出线电连接，所述第五导电塞贯穿所述数据线层与所述第一扇出线层或第二扇出线层之间的一个或多个绝缘层。
在一些实施例中，所述第一扇出线在衬底基板上的正投影与所述第二扇出线在衬底基板上的正投影完全重叠。
在一些实施例中，所述间隔层包括缓冲层或至少一个栅极绝缘层或缓冲层与至少一个栅极绝缘层的组合。
在一些实施例中，所述一个或多个间隔层的总厚度大于500nm。
在一些实施例中，所述第一扇出线层包括多个所述第一扇出线，所述第二扇出线层包括多个所述第二扇出线，所述多个第一扇出线的节距和所述多个第二扇出线的节距在1.5至3.0微米之间。
在一些实施例中，彼此至少部分交叠的所述第一扇出线和所述第二扇出线之间的单位面积电容小于8×10 -5皮法/平方微米。
本公开的实施例提供了一种显示装置，包括如上所述任一实施例所述的阵列基板。
本公开的实施例还提供了一种阵列基板的制造方法，包括：在衬底基板上形成包括第二扇出线的第二扇出线层；在所述第二扇出线层的远离衬底基板的一侧形成一个或更多个间隔层；在所述间隔层的远离衬底基板的一侧形成包括第一扇出线的第一扇出线层，所述第一扇出线在衬底基板上的正投影与所述第二扇出线在衬底基板上的正投影至少存在部分重叠；在所述第一扇出线层的远离衬底基板的一侧形成包括信号线的信号线层，所述信号线与所述第一扇出线或第二扇出线连接；其中，所述间隔层采用绝缘材料制作；所述信号线形成在所述阵列基板的显示区域，所述第一扇出线和第二扇出线形成在所述阵列基板的扇出区域。
在一些实施例中，所述在衬底基板上形成包括第二扇出线的第二扇出线层还包括：在所述衬底基板上形成第一金属薄膜；对所述第一金属薄膜进行图案化处理，形成遮光层和所述第二扇出线层；所述遮光层用于遮挡从所述衬底基板入射到阵列基板中的的光线。
在一些实施例中，所述信号线包括栅线，在所述第二扇出线层的远离衬底基板的一侧形成一个或多个间隔层之后，所述方法还包括：在所述间隔层上形成第二金属薄膜；对所述第二金属薄膜进行图案化处理，在所述显示区域形成栅线层，在所述显示区域和扇出区域的交界位置形成转接线层。
在一些实施例中，所述第一扇出线在衬底基板上的正投影与所述第二扇出线在衬底基板上的正投影重叠。
在一些实施例中，所述间隔层包括缓冲层或至少一个栅极绝缘层或缓冲层与至少一个栅极绝缘层的组合。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的 限制。
图1为根据本公开的一些实施例的一种阵列基板的示意图；
图2为根据本公开的一些实施例的阵列基板的扇出区沿图1中AA’方向的剖面结构示意图；
图3为压缩走线节距(pitch)实现下边框在Y方向上变窄的原理示意图；
图4为根据本公开的另一些实施例的阵列基板的扇出区沿图1中AA’方向的剖面结构示意图；
图5A为根据本公开的另一些实施例的阵列基板的扇出区沿图1中BB’方向的剖面结构示意图；
图5B为根据本公开的又一些实施例的阵列基板的扇出区沿图1中BB’方向的剖面结构示意图；
图5C为根据本公开的再一些实施例的阵列基板的扇出区沿图1中BB’方向的剖面结构示意图；
图6A为根据本公开的另一些实施例的阵列基板的扇出区沿图1中BB’方向的剖面结构示意图；
图6B为根据本公开的再一些实施例的阵列基板的扇出区沿图1中BB’方向的剖面结构示意图；以及
图7为根据本公开的一些实施例的阵列基板的制造方法的流程示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该 词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开实施例提出了一种阵列基板，能够在一定程度上减小显示面板边框宽度。
图1示出了一种阵列基板的示意图。所述阵列基板包括显示区域10和扇出区域20。在所述显示区域中形成有信号线，所述信号线包括数据线11、第一栅线12和第二栅线13，所述数据线11用于输入驱动信号，所述第一栅线12例如用于连接薄膜晶体管(TFT)的栅极以提供扫描信号，所述第二栅线13例如用于形成存储电容。所述显示区域10中的信号线例如可通过扇出区域20中的扇出线与外部集成电路(IC)实现信号传输。
外部集成电路通常采用独立的电路板70来实现，而电路板70与扇出区域20之间还具有弯折区域80，通过弯折区域80的弯折，使得所述电路板70可以折收于显示面板的显示区域和扇出区域的下方，从而不占用边框宽度。
图2为图1中扇出区域20在AA’方向的截面视图，如图2所示，在所述扇出区域，设置有第一扇出线41a和第二扇出线42a，所述信号线可以与所述第一扇出线41a连接或者所述信号线也可以与所述第二扇出线42a连接，以使信号线通过扇出线与外部集成电路实现信号传输(在一些实施例中，所述信号线可以包括与第一扇出线41a连接的第一信号线和与第二扇出线42a连接的第二信号线)；在所述第一扇出线41a所在的第一扇出线层与所述第二扇出线42a所在的第二扇出线层之间，可以设置有一个或多个间隔层55；所述间隔层55采用绝缘材料制作，可用于使所述第一扇出线层和第二扇出线层之间保持较大的层间间隔；所述第一扇出线41a在衬底基板40上的正投影与所述第二扇出线42a在衬底基板40上的正投影至少存在部分重叠。图2中所示的阵列面板，还包括第一绝缘层43’和第二绝缘层44’。其中，第二绝缘层44’也可以看成是间隔层之一。
从上述实施例可以看出，本公开提供的阵列基板，通过在第一扇出线层和第二扇出线层之间设置间隔层使二者的层间间隔增大，从而减小了第一扇出线和第二扇出线之间形成的电容，进而减少了串扰问题，降低了功耗；同时，第一扇出线和第二扇出线之间形成的电容的减小，也使得所述第一扇出线和第二扇出线之间可以存在一定重 叠，从而减小了走线pitch，压缩扇出区域在Y方向的长度，有助于实现窄边框。
下面结合图1和图3简要说明减小走线pitch与实现窄边框的关系。如图3所示，通常扇出区域的扇出线(Fanout)具有倾斜段和垂直段，当减小扇出线的走线pitch时，扇出线会向中间压缩，扇出线的倾斜段则会同时向X与Y两个方向(参考图1)压缩，这样便压缩了扇出线在Y方向的长度，从而使得阵列基板的下边框的宽度变窄。
作为本公开的一些实施例，如图4所示，所述第一扇出线41b在衬底基板40上的正投影与其相对应的所述第二扇出线42b在衬底基板40上的正投影重叠。因为通过增大层间间隔的方式减小了第一扇出线和第二扇出线之间形成的电容，进而减小了串扰问题，使得第一扇出线与第二扇出线间可形成完全交叠，进一步缩小了走线间距，从而进一步减小了下边框的宽度。采用这种重叠扇出线的方式，例如，走线pitch相比现有设计能够减小约17％，进而扇出区域在Y方向的长度相比现有设计能够压缩约20％。
作为本公开的一些实施例，参考图5A、5B和5C所示，所述间隔层55可以包括缓冲层(Buffer)。当衬底基板40为玻璃时，其上通常会设置有缓冲层，缓冲层可隔离衬底基板上的杂质进入其他层。缓冲层材质不限，但通常为绝缘材料，例如可以为SiNX或SiOX。因为缓冲层通常设置在靠近衬底基板40的位置，因此，当第二扇出线42e/42f/42g位于缓冲层以下而第一扇出线41e/41f(参考图6A和图6B)位于缓冲层以上时，能够保证第一扇出线和第二扇出线之间的层间间隔足够大，以达到减小二者间电容的目的。
作为本公开的一个实施例，参考图5A、5B或5C所示，所述衬底基板40上通常会形成的一层遮光物质，用于形成遮光层，所述遮光层LS用于遮挡从所述阵列基板背面入射(如从衬底基板入射到阵列基板中)的光线，以防止所述光线在阵列基板中产生不良影响(例如防止光线照射所述阵列基板的薄膜晶体管(TFT)阵列中的有源层，进而防止有源层因光照而产生光生载流子)。可以看出，所述第二扇出线层42e、42f或42g也设置在所述衬底基板40上，亦即所述第二扇出线层42e、42f或42g与所述阵列基板的遮光层可以由相同材料制成且位于同一层。或者说，所述第二扇出线层42e、42f或42g本身也可看成是遮光层LS的一部分，也具有遮光作用。因为遮光层LS通常直接置于衬底基板上，属于最底层的层级结构，因此，当其中一层扇出线层与LS共层时，可以使得该层扇出线与另一层扇出线之间的层间间隔足够大。
在一些实施例中，当所述遮光层采用金属材料制作时，所述第二扇出线42e、42f或42g，是通过对处于所述扇出区域20的遮光层LS进行图案化处理形成的；通过利 用遮光层LS制作其中一层扇出线，一方面，能够使得其与另一层扇出线之间的层间间隔能够增大，以进一步减小串扰问题；另一方面，能够同时把存在于扇出区域的遮光层(金属材料，通常为Mo)更充分地利用起来。
作为本公开的一些实施例，如图1所示，所述阵列基板中的显示区域内具有用于形成薄膜晶体管(TFT)的栅极的第一栅线12以及用于形成存储电容的第二栅线13，在制作这两种栅线的同时，可利用构图工艺一次性在扇出区域形成扇出线。如图6A所示，用于形成TFT的栅极的第一栅线，在扇出区域用作第一扇出线41e，搭配图5A、5B或5C所示的第二扇出线42e、42f或42g，共同形成为扇出区域的扇出线。如图6B所示，用于形成存储电容的第二栅线，在扇出区域用作第一扇出线41f，搭配图5A、5B或5C所示的第二扇出线42e、42f或42g，共同形成为扇出区域的扇出线。需要说明的是，虽然在扇出区域的第一扇出线是通过栅线制作的，但只是因为它们可以在同一层采用一次构图工艺同时制作而成，并不代表第一扇出线与栅线之间是电连接的，可以知道的，为了使栅线和扇出线分别实现相应的功能，二者通常情况下是不会相互电连接的。
当所述第一栅线或第二栅线形成为第一扇出线时，其可搭配前述的由遮光层LS图案化后形成的第二扇出线，来作为扇出区的两种扇出线，并且在第一扇出线所在的第一扇出线层与所述第二扇出线所在的第二扇出线层之间，通常会包括第一缓冲层44、第二缓冲层45、第一栅极绝缘层46等(如图5B所示，某些情况下还可包括第二栅极绝缘层47)，这些层级结构均可属于所述间隔层的一部分，这样，利用缓冲层、栅极绝缘层等层级结构的厚度去减小第一扇出线和第二扇出线之间的电容，避免第一扇出线和第二扇出线之间的信号相互串扰。若需进一步减小第一扇出线和第二扇出线之间的电容，还可以适当增大缓冲层、栅极绝缘层等层级结构的厚度。
在一些实施例中，所述一个或多个间隔层的总厚度可以大于500nm。在一些实施例中，彼此至少部分交叠的所述第一扇出线和所述第二扇出线之间的单位面积电容小于8×10 -5皮法/平方微米。上述间隔层的总厚度和单位面积电容的设计可以有效地防止第一扇出线和第二扇出线之间的信号相互串扰。
在一些实施例中，所述第一扇出线层包括多个第一扇出线，所述第二扇出线层包括多个第二扇出线，所述多个第一扇出线的节距和所述多个第二扇出线的节距可以在1.5至3.0微米之间。通常情况下，扇出区域所起的主要作用在于，将显示区域的电路的数据线11或第一栅线12连接到外部集成电路中。因此，需要将数据线11或第一栅 线12通过扇出线与外部IC进行连接。在本公开实施例中，当采用遮光层LS制作其中一层扇出线时，可以直接通过过孔来连接数据线和扇出线。
在一些实施例中，所述阵列基板还可包括转接线层，所述转接线层设置在所述数据线所在的数据线层与所述第一扇出线层之间，或者，所述转接线层设置在所述数据线所在的数据线层与所述第二扇出线层之间；所述转接线层包括转接线60a/60b(如图5A和5B所示)，所述数据线通过所述转接线连接所述第一扇出线或第二扇出线。这样，通过设置转接线层，能够减小过孔深度，提高电连接可靠性。这种方式对于遮光层LS和数据线所在的数据线层50之间的层间间隔较大、二者间层级结构较为复杂的情况，尤其有益。
根据本公开的一些实施例，在所述显示区域，形成有栅线(可以是第一栅线12也可以是第二栅线13)；所述转接线层与所述栅线所在的栅线层为同一层。这样，利用制作栅线时的工艺同时形成转接线，从而可以节省工艺步骤，提高生产效率。
如图5A所示，在显示区域10和扇出区域20的交界位置(图5A中两条竖直虚线之间的区域)，转接线60a可以与用于形成TFT的栅极的第一栅线由相同材料制成且同层设置，数据线50通过所述转接线60a连接第二扇出线42e。在显示区域形成栅极的同时，可以在显示区域10和扇出区域20的交界位置形成相应的转接线60a，用于将数据线50与第二扇出线42e进行电连接。在一些实施例中，所述阵列基板可以包括第一栅线所在的第一栅线层和第二栅线所在的第二栅线层，所述转接线层可以与所述第一栅线层由相同材料制成且布置在同一层。所述扇出区域20包括位于所述转接线60a所在的转接线层和第二扇出线42e所在的第二扇出线层之间的至少一个缓冲层(例如第一缓冲层44、第二缓冲层45)和第一栅极绝缘层46以及位于所述数据线层和所述转接线层之间的第二栅极绝缘层47和至少一个层间介质层。数据线50通过贯穿所述第二栅极绝缘层47和至少一个层间介质层的第一导电塞61与所述转接线60a电连接且所述转接线60a通过贯穿所述至少一个缓冲层和第一栅极绝缘层46的第二导电塞62与所述第二扇出线42e电连接。
如图5B所示，在显示区域10和扇出区域20的交界位置(图5B中两条竖直虚线之间的区域)，转接线60b可以与用于形成存储电容的第二栅线由相同材料制成且同层设置，用于将数据线50与第二扇出线42f进行电连接。在一些实施例中，转接线60b可以与所述第二栅线由相同材料制成且布置在同一层，所述扇出区域20可包括位于所述转接线60b所在的转接线层和第二扇出线42e所在的第二扇出线层之间的至少一个 缓冲层(例如第一缓冲层44、第二缓冲层45)、第一栅极绝缘层46和第二栅极绝缘层47以及位于所述数据线层和所述转接线层之间的至少一个层间介质层，所述数据线50通过贯穿所述至少一个层间介质层的第三导电塞63与所述转接线60b电连接且所述转接线60b通过贯穿所述至少一个缓冲层、第一栅极绝缘层46和第二栅极绝缘层47的第四导电塞64与所述第二扇出线42f电连接。
当然，若直接在数据线和第二扇出线之间直接通过过孔连接能够保证连接稳定性时，可以直接将数据线与第二扇出线进行连接。如图5C所示，数据线50与第二扇出线42g直接通过过孔进行连接。在一些实施例中，所述数据线50通过第五导电塞65与所述第一扇出线或第二扇出线电连接，所述第五导电塞65贯穿所述数据线层与所述第一扇出线层或第二扇出线层之间的一个或多个绝缘层。
需要说明的是，如图1所示，外部集成电路通常采用独立的电路板70来实现，而电路板70与扇出区域20之间还具有弯折区域80，通过弯折区域80的弯折，使得所述电路板70可以收于显示面板的显示区域和扇出区域的下方，从而不占用边框宽度。因为扇出区域用于为显示区域和外部集成电路的连接提供过渡区域，因此，扇出区域20的扇出线除了与显示区域10的数据线连接外，还需要与弯折区域80的数据线连接，以实现显示区域和外部电路的数据线的信号传递。而扇出区域20的扇出线与弯折区域80的数据线的连接方法，也可以采用图5A至5C之中的任意一种方法来实现。
图5A、5B、5C示出的是利用遮光层LS所形成的第二扇出线与数据线的连接方式。图6A和6B则分别示出了第一扇出线41e与第一栅线由同样材料制成且设置在同一层和第一扇出线41f与第二栅线由同样材料制成且设置在同一层时，第一扇出线与数据线的连接方式。在具体实现本公开的扇出区域的扇出线排布结构时，可以采用图5A～5C示出的任一结构以及图6A或图6B的结构来实现。
需要说明的是，图5A～5C示出的主要是显示区域10与扇出区域20的交界位置(图中两条竖直虚线之间的部分)的布线方式，而在完成数据线与扇出线之间的连接后，实际在扇出区域的主要部分中，第一扇出线在衬底基板上的正投影和第二扇出线在衬底基板上的正投影之间可以存在交叠甚至是完全重叠，即如图2、图4所示，这是完全可以通过构图工艺实现的。
还需要说明的是，图5A～5C、6A和6B中的层级结构中包括有衬底基板40，基于阵列基板的制作工艺的选择，所述阵列基板还可能包括第一缓冲层44、第二缓冲层45、第一栅极绝缘层(GI)46、第二栅极绝缘层47、第一层间介质层(ILD)43和第二层 间介质层48。其中，在这两层缓冲层中，其中一层缓冲层用于隔离玻璃制成的衬底基板40中的金属离子，防止金属离子扩散到TFT器件内，另一层缓冲层用于保温，以利于硅(Si)形成大的结晶晶粒。在两层层间介质层中，其中一层由SiOx制成，用于起到平坦和绝缘的作用，另一层由SiNx制成，用于起到修复Si的缺陷的作用。所述第一栅极绝缘层46用于实现第一栅线12所在的第一栅线层(例如金属层)的绝缘，所述第二栅极绝缘层47用于实现第二栅线13所在的第二栅线层(例如金属层)的绝缘。需要知道，这样的层级结构仅仅是示意性的，并不代表本公开仅保护含有所有这些层级结构的阵列基板，可以知道，在允许的情况下，所述层级结构中的各层可以有增减，这些变形也应该属于本公开的保护范围。
在前述各实施例的描述基础上，还需要指出的是，本公开旨在通过平衡走线pitch和走线间电容而使得显示面板在Y方向长度能够尽可能小，从而达到实现窄边框的目的，只要能够达到这样的目的，并且公开思路与本公开基本一致，即可认为属于本公开的保护范围。
需要说明的是，前述的部分实施例中以数据线为例进行了描述，但是可以知道的是，栅线也需要通过扇出线与外部IC电路进行信号传输，因此，对于栅线来说，也可以参考前述数据线的实施例来完成与扇出线的连接，在此不再赘述。
还需要说明的是，前述实施例中以阵列基板包括两种栅线(即第一栅线12和第二栅线13)为例进行描述，但是可以知道，阵列基板中还存在仅包括一种栅线的结构(即，仅包括用于接收扫描信号的栅线)，对于这种结构，也同样适用于前述实施例的公开思路，在此不再赘述。
本公开实施例还提供了一种显示装置，能够在一定程度上减小显示面板边框宽度。所述显示装置，包括如前所述的阵列基板的任一实施例或实施例的组合。
从上述实施例可以看出，本公开提供的显示装置，通过在第一扇出线层和第二扇出线层之间夹设间隔层使二者的层间间隔增大，从而减小了第一扇出线和第二扇出线之间形成的电容，进而减少了串扰问题，降低了功耗；同时，第一扇出线和第二扇出线之间形成的电容的减小，也使得所述第一扇出线和第二扇出线之间可以存在一定重叠，从而减小了走线pitch，压缩扇出区域在Y方向的长度，有助于实现窄边框。
需要说明的是，本实施例中的显示装置可以为：电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例还提供了一种阵列基板的制造方法，能够在一定程度上减小显示面板边框宽度。
如图7所示，所述阵列基板的制造方法，包括：
步骤91：在衬底基板上形成包括第二扇出线的第二扇出线层；
步骤92：在所述第二扇出线层的远离衬底基板的一侧形成一个或更多个间隔层；
步骤93：在所述间隔层的远离衬底基板的一侧形成包括第一扇出线的第一扇出线层，所述第二扇出线在衬底基板上的正投影与所述第一扇出线在衬底基板上的正投影至少存在部分重叠；
步骤94：在所述第一扇出线层远离衬底基板的一侧形成包括信号线的信号线层，所述信号线与所述第一扇出线或第二扇出线连接；
其中，所述间隔层采用绝缘材料制作；所述信号线形成在所述阵列基板的显示区域，所述第一扇出线和第二扇出线形成在所述阵列基板的扇出区域。
从上述实施例可以看出，本公开提供的阵列基板的制造方法，通过在第一扇出线层和第二扇出线层之间夹设间隔层使二者的层间间隔增大，从而减小了第一扇出线和第二扇出线之间形成的电容，进而减少了串扰问题，降低了功耗；同时，第一扇出线和第二扇出线之间形成的电容的减小，也使得所述第一扇出线和第二扇出线之间可以存在一定重叠，从而减小了走线pitch，压缩扇出区域在Y方向的长度，有助于实现窄边框。
在一些实施例中，所述阵列基板的制造方法中的步骤91还可包括以下步骤：
在所述衬底基板上形成第一金属薄膜；
对所述第一金属薄膜进行图案化处理，形成遮光层和所述第二扇出线层；所述遮光层用于遮挡从所述衬底基板入射到阵列基板中的的光线，例如以防止所述光线照射所述阵列基板的薄膜晶体管阵列中的有源层。
通过利用遮光层材料制作其中一层扇出线，使得其与另一层扇出线之间的层级结构均可作为所述间隔层，从而层间间隔能够增大(因遮光层直接置于衬底基板上，属于最底层的层级结构)，以进一步减小串扰问题。同时能够把存在于扇出区的遮光层(金属材料)更充分地利用起来。
在一些实施例中，所述信号线还包括栅线，所述阵列基板的制造方法，在所述步骤92之后，还可包括以下步骤：
在所述间隔层上形成第二金属薄膜；
对所述第二金属薄膜进行图案化处理，在所述显示区域形成栅线层，在所述显示区域和扇出区域的交界位置形成转接线层。
这样，通过一次构图工艺即可同时制作形成栅线层和转接线层，精简了工艺，提升了生产效率。
在一些实施例中，所述栅线包括所述阵列基板的显示区域内的用于形成TFT的栅极的第一栅线12以及用于形成存储电容的第二栅线13。在制作这两种栅线的同时，均可同时制作所述转接线层。
在一些实施例中，所述第一扇出线的正投影与所述第二扇出线的正投影重叠。因为减小了串扰问题，使得第一扇出线与第二扇出线间可形成交叠，进而减小线间距，从而减小下边框的宽度。
在一些实施例中，所述间隔层可包括缓冲层或至少一个栅极绝缘层或缓冲层与至少一个栅极绝缘层的组合。当衬底基板为玻璃时，缓冲层可隔离衬底基板上杂质进入其他层，缓冲层材质不限，例如可以为SiN X或SiO X。因为缓冲层通常设置在靠近衬底基板的层级位置，因此，当第二扇出线位于缓冲层以下而第一扇出线位于缓冲层以上时，能够保证第一扇出线和第二扇出线之间的层间间隔足够大，以达到减小二者间电容的目的。
在本公开的实施例中，通过在第一扇出线与第二扇出线之间增加设置至少一层绝缘层，可以以加大第一扇出线与第二扇出线的层间间隔，进一步减小串扰问题。
需要说明的是，上述形成层的操作，包括但不仅限于(化学相、物理相)沉积成膜、(磁控)溅射成膜，并且本领域技术人员可以理解，在形成每个层之后，可以根据需要在其上进一步形成相应的图案，本公开对此不再赘述。
本公开实施例提供的阵列基板及其制造方法、显示装置，通过在第一扇出线层和第二扇出线层之间夹设间隔层使二者的层间间隔增大，从而减小了第一扇出线和第二扇出线之间形成的电容，进而减少了串扰问题，降低了功耗；同时，第一扇出线和第二扇出线之间形成的电容的减小，也使得所述第一扇出线和第二扇出线之间可以存在一定重叠，从而减小了走线pitch，压缩扇出区域在Y方向的长度，有助于实现窄边框。
以上结合附图详细说明了本公开的技术方案，考虑到现有技术中，源漏极和有源层处于不同层，使得基板厚度较大，制作工艺复杂。通过本申请的技术方案，可以通 过对氮化铜进行掺杂处理，将源极、漏极、数据线和有源层制备在同一层中，从而减小阵列基板的厚度，简化阵列基板的制作工艺。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间惟一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
所属领域的普通技术人员应当理解：以上所述仅为本公开的具体实施例而已，并不用于限制本公开，凡在本公开的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种阵列基板，包括：
    衬底基板；以及
    设置在衬底基板上的显示区域和扇出区域，在所述显示区域中设置有信号线，所述扇出区域包括第一扇出线层、第二扇出线层和在所述第一扇出线层与所述第二扇出线层之间的一个或更多个间隔层，在所述第一扇出线层中设置有第一扇出线，在所述第二扇出线层中设置有第二扇出线，所述信号线与所述第一扇出线或第二扇出线连接，所述间隔层采用绝缘材料制作；
    其中，所述第一扇出线在衬底基板上的正投影与所述第二扇出线在衬底基板上的正投影至少存在部分重叠。
  2. 根据权利要求1所述的阵列基板，其中，所述信号线包括与第一扇出线连接的第一信号线和与第二扇出线连接的第二信号线。
  3. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括遮光层，所述遮光层用于遮挡从所述衬底基板入射到阵列基板中的光线，所述第二扇出线层与所述阵列基板的遮光层由相同材料制成且位于同一层。
  4. 根据权利要求3所述的阵列基板，其中，所述阵列基板包括至少一个栅线层，所述第一扇出线层与所述至少一个栅线层中的一个栅线层由相同材料制成且设置于同一层。
  5. 根据权利要求3所述的阵列基板，其中，所述信号线包括数据线，所述阵列基板还包括数据线层和转接线层，所述数据线设置于所述数据线层中，所述转接线层设置在所述数据线层与所述第一扇出线层或所述第二扇出线层之间；所述转接线层包括转接线，所述数据线与所述转接线电连接且所述转接线与所述第一扇出线或第二扇出线电连接。
  6. 根据权利要求5所述的阵列基板，其中，所述信号线还包括栅线；所述转接线层与所述栅线由相同材料制成且布置在同一层。
  7. 根据权利要求5所述的阵列基板，其中，所述阵列基板包括第一栅线层和第二栅线层，所述转接线层与所述第一栅线层由相同材料制成且布置在同一层，所述扇出区域包括位于所述转接线层和第二扇出线层之间的至少一个缓冲层和第一栅极绝缘层 以及位于所述数据线层和所述转接线层之间的第二栅极绝缘层和至少一个层间介质层，所述数据线通过贯穿所述第二栅极绝缘层和至少一个层间介质层的第一导电塞与所述转接线电连接且所述转接线通过贯穿所述至少一个缓冲层和第一栅极绝缘层的第二导电塞与所述第二扇出线电连接。
  8. 根据权利要求5所述的阵列基板，其中，所述阵列基板包括第一栅线层和第二栅线层，所述转接线层与所述第二栅线层由相同材料制成且布置在同一层，所述扇出区域包括位于所述转接线层和第二扇出线层之间的至少一个缓冲层、第一栅极绝缘层和第二栅极绝缘层以及位于所述数据线层和所述转接线层之间的至少一个层间介质层，所述数据线通过贯穿所述至少一个层间介质层的第三导电塞与所述转接线电连接且所述转接线通过贯穿所述至少一个缓冲层、第一栅极绝缘层和第二栅极绝缘层的第四导电塞与所述第二扇出线电连接。
  9. 根据权利要求3所述的阵列基板，其中，所述信号线包括数据线，所述阵列基板还包括数据线层，所述数据线设置于所述数据线层中，所述数据线通过第五导电塞与所述第一扇出线或第二扇出线电连接，所述第五导电塞贯穿所述数据线层与所述第一扇出线层或第二扇出线层之间的一个或多个绝缘层。
  10. 根据权利要求1至9中任一项所述的阵列基板，其中，所述第一扇出线在衬底基板上的正投影与所述第二扇出线在衬底基板上的正投影完全重叠。
  11. 根据权利要求1至9中任一项所述的阵列基板，其中，所述间隔层包括缓冲层或至少一个栅极绝缘层或缓冲层与至少一个栅极绝缘层的组合。
  12. 根据权利要求1至9中任一项所述的阵列基板，其中，所述一个或多个间隔层的总厚度大于500nm。
  13. 根据权利要求1至9中任一项所述的阵列基板，其中，所述第一扇出线层包括多个所述第一扇出线，所述第二扇出线层包括多个所述第二扇出线，所述多个第一扇出线的节距和所述多个第二扇出线的节距在1.5至3.0微米之间。
  14. 根据权利要求1至9中任一项所述的阵列基板，其中，彼此至少部分交叠的所述第一扇出线和所述第二扇出线之间的单位面积电容小于8×10 -5皮法/平方微米。
  15. 一种显示装置，包括如权利要求1-14中任一项所述的阵列基板。
  16. 一种阵列基板的制造方法，包括：
    在衬底基板上形成包括第二扇出线的第二扇出线层；
    在所述第二扇出线层的远离衬底基板的一侧形成一个或更多个间隔层；
    在所述间隔层的远离衬底基板的一侧形成包括第一扇出线的第一扇出线层，所述第一扇出线在衬底基板上的正投影与所述第二扇出线在衬底基板上的正投影至少存在部分重叠；
    在所述第一扇出线层的远离衬底基板的一侧形成包括信号线的信号线层，所述信号线与所述第一扇出线或第二扇出线连接；
    其中，所述间隔层采用绝缘材料制作；所述信号线形成在所述阵列基板的显示区域，所述第一扇出线和第二扇出线形成在所述阵列基板的扇出区域。
  17. 根据权利要求16所述的方法，其中，所述在衬底基板上形成包括第二扇出线的第二扇出线层还包括：
    在所述衬底基板上形成第一金属薄膜；
    对所述第一金属薄膜进行图案化处理，形成遮光层和所述第二扇出线层；所述遮光层用于遮挡从所述衬底基板入射到阵列基板中的光线。
  18. 根据权利要求16所述的方法，其中，所述信号线包括栅线，在所述第二扇出线层的远离衬底基板的一侧形成一个或多个间隔层之后，所述方法还包括：
    在所述间隔层上形成第二金属薄膜；
    对所述第二金属薄膜进行图案化处理，在所述显示区域形成栅线层，在所述显示区域和扇出区域的交界位置形成转接线层。
  19. 根据权利要求16所述的方法，其中，所述第一扇出线在衬底基板上的正投影与所述第二扇出线在衬底基板上的正投影重叠。
  20. 根据权利要求16所述的方法，其中，所述间隔层包括缓冲层或至少一个栅极绝缘层或缓冲层与至少一个栅极绝缘层的组合。
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