CN104992952A - 阵列基板及其制备方法 - Google Patents

阵列基板及其制备方法 Download PDF

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CN104992952A
CN104992952A CN201510374557.6A CN201510374557A CN104992952A CN 104992952 A CN104992952 A CN 104992952A CN 201510374557 A CN201510374557 A CN 201510374557A CN 104992952 A CN104992952 A CN 104992952A
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intermediate pattern
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photoresist layer
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杨丽娟
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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Priority to US15/107,808 priority patent/US10204932B2/en
Priority to PCT/CN2015/092204 priority patent/WO2017000431A1/zh
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Abstract

本发明公开了一种阵列基板及其制备方法，所述阵列基板包括显示区和位于所述显示区外围的布线区，所述制备方法包括制备位于所述布线区中的线路的步骤，该步骤包括：形成金属层；对所述金属层进行第一次构图工艺，形成中间图形；对所述中间图形进行第二次构图工艺，形成位于所述布线区中的线路。本发明将高密度的布线区线路分为两次构图工艺进行制作，两次构图工艺采用两套分立的、图形密度低的掩膜板进行曝光，降低了对曝光机分辨率的要求，使得曝光后形成的图形质量更高。并且，本发明能够实现布线区线路的细线化制作，与现有技术中采用一次曝光的方式相比，能够有效降低线路断路和短路的风险。

Description

阵列基板及其制备方法
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制备方法。
背景技术
液晶显示面板(TFT-LCD)具有亮度好、对比度高、功耗低、体积小、重量轻等优点。同时，液晶显示面板大规模生产性好、自动化生产程度高、原材料成本低廉、发展空间广阔，是21世纪全球经济增长的一个亮点。
液晶显示面板包括有效显示区(Active Area)以及周边电路区(Peripheral Circuit Area)。有效显示区内配置有多个像素以形成像素阵列，周边电路区则设有周边线路。每个像素都包括薄膜晶体管以及与该薄膜晶体管连接的像素电极，且每个像素都被两条相邻的扫描线以及两条相邻的数据线包围。通常，这些扫描线以及数据线会由有效显示区域延伸到周边电路区，并通过周边电路与驱动芯片电连接。一般而言，驱动芯片有特定的尺寸设计，周边电路会连接扫描线与数据线的一端向驱动芯片所在的区域形成布线区(Fanout区)。
随着显示技术的发展，显示产品需要以窄边框设计来实现完美的视觉效果，这就需要减小线宽和线距。然而，现有的排线设计已经达到了曝光机的分辨率极限，如果进一步减小线宽和线距，制程中会存在线路断路和短路的风险。
并且，生产过程中发现，掩膜版上同样的图案经光刻工艺后形成在像素区的线路比形成在布线区的线路要细。导致这种不良的原因有：从布局上看，像素区的走线比较稀疏，而布线区的走线比较稠密。对于正性光刻胶来说，在形成线路时，是对线路之间的光刻胶进行曝光，并显影去除。这样在显影时，由于布线区的走线十分稠密，所以线路之间的光刻胶较难被去除，使得布线区的走线较宽。
从光强分布的角度来看，布线区的走线十分稠密，以正性光刻胶为例，掩膜版上的透光区对应线路之间的间隙，当光照射到掩膜版上时，掩膜版的透光区相当于一道道狭缝，组成了一个透射式衍射光栅，走线越稠密，狭缝数越多，光栅常数越小，光栅衍射形成的明条纹越亮越细，从而使得曝光区变小，造成布线区的线路宽度变大。
从成像的角度来看，曝光机实际上就是一个成像光学系统，每个成像系统都有一个截止频率，高于截止频率的物(掩膜版上的图像)频谱，系统是没办法通过的。对于掩膜版上的图像，走线越稠密，高频成分越多，成像时被截止掉的信息就越多，光刻胶被曝光的区域和掩膜版上的图像差异就越大。
因此，针对目前曝光机分辨率达到极限、窄边框及高PPI产品布线区制程中出现瓶颈的现状，如何实现布线区线路的细线化制作是本领域亟待解决的技术问题。
发明内容
本发明的目的在于提供一种阵列基板及其制备方法，以实现布线区线路的细线化制作，从而降低线路断路和短路的风险。
为解决上述技术问题，作为本发明的第一个方面，提供了一种阵列基板的制备方法，所述阵列基板包括显示区和位于所述显示区外围的布线区，所述制备方法包括制备位于所述布线区中的线路的步骤，该步骤包括：
形成金属层；
对所述金属层进行第一次构图工艺，形成中间图形，所述中间图形包括形成的部分线路图形；
对所述中间图形进行第二次构图工艺，形成位于所述布线区中的线路。
优选地，对所述金属层进行第一次构图工艺，形成中间图形的步骤包括：
在所述金属层上形成第一光刻胶层；
采用第一掩膜板对所述第一光刻胶层进行曝光；
对曝光后的第一光刻胶层进行显影；
对所述金属层进行第一次刻蚀；
剥离残留的光刻胶，得到所述中间图形。
优选地，对所述中间图形进行第二次构图工艺，形成位于所述布线区中的线路的步骤包括：
在所述中间图形上形成第二光刻胶层；
采用第二掩膜板对所述第二光刻胶层进行曝光；
对曝光后的第二光刻胶层进行显影；
对所述中间图形进行第二次刻蚀；
剥离残留的光刻胶，得到位于所述布线区中的线路。
优选地，所述阵列基板还包括源漏极层，位于所述布线区中的线路与所述源漏极层中的源极和漏极同层形成。
优选地，所述阵列基板还包括栅极层，位于所述布线区中的线路与所述栅极层中的栅极同层形成。
优选地，所述第一光刻胶层为正性光刻胶层，所述第一掩膜板上对应于所述金属层上将形成所述中间图形的区域为遮光区，所述第一掩膜板上对应于所述金属层上将被去除部位的区域为透光区；
或者，所述第一光刻胶层为负性光刻胶层，所述第一掩膜板上对应于所述金属层上将形成所述中间图形的区域为透光区，所述第一掩膜板上对应于所述金属层上将被去除部位的区域为遮光区。
优选地，所述第二光刻胶层为正性光刻胶层，所述第二掩膜板上对应于所述中间图形上将形成所述线路的区域为遮光区，所述第二掩膜板上对应于所述中间图形上将被去除部位的区域为透光区；
或者，所述第二光刻胶层为负性光刻胶层，所述第二掩膜板上对应于所述中间图形上将形成所述线路的区域为透光区，所述第二掩膜板上对应于所述中间图形上将被去除部位的区域为遮光区。
优选地，对所述金属层进行第一次刻蚀的步骤中，刻蚀方法包括干刻或者湿刻。
优选地，对所述中间图形进行第二次刻蚀的步骤中，刻蚀方法包括干刻或者湿刻。
作为本发明的第二个方面，还提供一种阵列基板，所述阵列基板采用本发明所提供的上述制备方法制备形成。
本发明将高密度的布线区线路分为两次构图工艺进行制作，两次构图工艺采用两套分立的、图形密度低的掩膜板进行曝光，降低了对曝光机分辨率的要求，使得曝光后形成的图形质量更高。并且，本发明能够实现布线区线路的细线化制作，与现有技术中采用一次曝光的方式相比，能够有效降低线路断路和短路的风险。
附图说明
附图是用来提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。
图1是本发明方法中制备布线区线路的流程示意图；
图2a-图2b分别是本发明实施例中形成中间图形和最终线路的流程示意图；
图3a-图3i是本发明实施例中布线区线路在制作过程中的剖面示意图。
在附图中，200-衬底；210-金属层；220-第一光刻胶层；221-第一光刻胶保留部；230-第一掩膜板；211-中间图形；240-第二光刻胶层；241-第二光刻胶保留部；250-第二掩膜板；212-最终图形。
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
本发明提供了一种阵列基板的制备方法，所述阵列基板包括显示区和位于所述显示区外围的布线区(Fanout区)，所述制备方法包括制备位于所述布线区中的线路的步骤，如图1所示，该步骤包括：
形成金属层；
对所述金属层进行第一次构图工艺，形成中间图形，所述中间图形包括形成的部分线路图形；
对所述中间图形进行第二次构图工艺，形成位于所述布线区中的线路。
如上所述，受曝光机分辨率的限制，窄边框及高PPI产品在布线区的线路难以实现细线化制作，如果利用曝光机一次形成线宽和/或线距小于曝光机曝光精度极限的图形，制程中会存在线路断路和短路的风险。
本发明将高密度的布线区线路分为两次构图工艺进行制作，两次构图工艺采用两套分立的、图形密度低的掩膜板进行曝光，降低了对曝光机曝光精度的要求，使得曝光后形成的图形质量更高。并且，本发明能够实现布线区线路的细线化制作，与现有技术中采用一次曝光的方式相比，能够有效降低线路断路和短路的风险。
优选地，如图2a所示，对所述金属层进行第一次构图工艺，形成中间图形的步骤包括：
S11、在所述金属层上形成第一光刻胶层；
S12、采用第一掩膜板对所述第一光刻胶层进行曝光；
S13、对曝光后的第一光刻胶层进行显影；
S14、对所述金属层进行第一次刻蚀；
S15、剥离残留的光刻胶，得到所述中间图形。
优选地，如图2b所示，对所述中间图形进行第二次构图工艺，形成位于所述布线区中的线路的步骤包括：
S21、在所述中间图形上形成第二光刻胶层；
S22、采用第二掩膜板对所述第二光刻胶层进行曝光；
S23、对曝光后的第二光刻胶层进行显影；
S24、对所述中间图形进行第二次刻蚀；
S25、剥离残留的光刻胶，得到位于所述布线区中的线路。
在上述实施方式中，本发明采用光刻工艺逐步形成中间图形和最终线路。
进一步地，所述阵列基板还包括源漏极层，位于所述布线区中的线路与所述源漏极层中的源极和漏极同层形成。
通常，布线区中的线路主要是信号线，信号线的主要作用是连接源漏极金属和驱动芯片。因此，在本发明中，阵列基板中的源漏极与布线区线路可以设置在同一层。
或者，所述阵列基板还包括栅极层，位于所述布线区中的线路与所述栅极层中的栅极同层形成。
在目前的TFT-LCD工艺中，栅极材料一般也为金属，布线区线路也可以同栅极设置在同一层，然后通过过孔将布线区线路与源漏极金属进行电连接。
在本发明中，进行第一次构图工艺所使用的第一光刻胶层和进行第二次构图工艺所使用的第二光刻胶层可以是正性光刻胶层、也可以是负性光刻胶层。
当所述第一光刻胶层为正性光刻胶层时，所述第一掩膜板上对应于所述金属层上将形成所述中间图形的区域为遮光区，所述第一掩膜板上对应于所述金属层上将被去除部位的区域为透光区；
或者，当所述第一光刻胶层为负性光刻胶层时，所述第一掩膜板上对应于所述金属层上将形成所述中间图形的区域为透光区，所述第一掩膜板上对应于所述金属层上将被去除部位的区域为遮光区。
相应地，当所述第二光刻胶层为正性光刻胶层时，所述第二掩膜板上对应于所述中间图形上将形成所述线路的区域为遮光区，所述第二掩膜板上对应于所述中间图形上将被去除部位的区域为透光区；
或者，当所述第二光刻胶层为负性光刻胶层时，所述第二掩膜板上对应于所述中间图形上将形成所述线路的区域为透光区，所述第二掩膜板上对应于所述中间图形上将被去除部位的区域为遮光区。
进一步地，本发明对于第一次刻蚀工艺和第二次刻蚀工艺中所采用的具体刻蚀方法不做限定，只要能够完成膜层刻蚀并得到工艺所需的图形即可。
例如，对所述金属层进行第一次刻蚀的步骤中，刻蚀方法可以包括干刻或者湿刻；对所述中间图形进行第二次刻蚀的步骤中，刻蚀方法也可以包括干刻或者湿刻。
下面结合图3a-图3i，对本发明方法进行详细的阐述。本发明中位于布线区中的线路的制作过程如下：
首先，在衬底200表面依次形成金属层210(例如：用于形成TFT栅极或源漏极的金属层)和第一光刻胶层220，然后利用第一掩膜板230对第一光刻胶层220进行曝光，如图3a所示。
在本实施例中选用正性光刻胶，正性光刻胶被曝光后，感光部在曝光过程中发生光化学反应，遇水后生成羧类物质，能与碱性显影液发生化学反应而被溶解掉；未感光部中的树脂与感光剂之间发生建桥反应，能阻止树脂在显影液中溶解从而形成工艺上所需的光刻胶图案。
之后，对曝光后的第一光刻胶层220进行显影，使曝光后性质发生改变的光刻胶与显影液发生反应，而未被光照射区域的光刻胶保留下来，形成第一光刻胶保留部221。在接下来的刻蚀工艺中，第一光刻胶保留部221用于对它下方的金属进行保护，如图3b所示。
相对于未被拆分的掩膜板(这里指掩膜板上的图形和最终图形一致、能通过一次曝光形成最终图形的掩膜板)，第一掩膜板230上的图形密度降低，所以曝光后能形成质量较高的图形，从而避免了由于掩膜板上图形达到曝光极限而引起的线路断路或短路的风险。
之后，对金属层210进行第一次刻蚀，去除金属层210中未被光刻胶保护的区域，而第一光刻胶保留部221下方区域的金属被保留，形成中间图形211，如图3c所示。
布线区线路一般由金属层制作完成，对于金属层，一般采用湿法刻蚀，即用腐蚀性的酸液与金属层中未被光刻胶保护的区域反应，而有光刻胶保护的区域下方的金属被保留，从而形成工艺上所需的图案。然而，这里的刻蚀方法不只限于湿法刻蚀，对于一切能完成膜层刻蚀的刻蚀方法都属于本发明的保护范围。
之后，剥离残留的光刻胶，如图3d所示，这里的剥离液一般为碱性有机溶剂。
之后，在中间图形211上形成第二光刻胶层240，如图3e所示。
利用第二掩膜板250对第二光刻胶层240进行曝光，如图3f所示。因为最终图形是在中间图形211的基础上进一步形成的，所以在本次曝光时，需要对第二掩膜板250和中间图形211的对位精度进行严格管控，以保证最终图形的质量。
之后，对曝光后的第二光刻胶层240进行显影，使曝光后性质发生改变的光刻胶与显影液发生反应，而未被光照射区域的光刻胶保留下来，形成第二光刻胶保留部241，第二光刻胶保留部241在接下来的刻蚀工艺中对它下方的金属进行保护，如图3g所示。
对中间图形211进行第二次刻蚀，如图3h所示，然后剥离残留的光刻胶得到最终图形212(即位于布线区中的线路)，如图3i所示。
需要说明的是，本发明方法虽然主要是为了改善布线区的图形质量，但对于其它膜层图形的制作过程也是同样适用的，也能够有效改善曝光精度从而提高图形质量。
本发明还提供了一种阵列基板，所述阵列基板采用本发明所提供的上述制备方法制备形成。本发明所提供的阵列基板将高密度的布线区线路分为两次构图工艺进行制作，两次构图工艺采用两套分立的、图形密度低的掩膜板进行曝光，降低了对曝光机分辨率的要求，使得曝光后形成的图形质量更高。并且，本发明所提供的阵列基板能够实现布线区线路的细线化制作，与现有技术中采用一次曝光的方式形成的线路相比，本发明中的线路能够有效降低断路和短路的风险。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (10)

1.一种阵列基板的制备方法，所述阵列基板包括显示区和位于所述显示区外围的布线区，其特征在于，所述制备方法包括制备位于所述布线区中的线路的步骤，该步骤包括：
形成金属层；
对所述金属层进行第一次构图工艺，形成中间图形，所述中间图形包括形成的部分线路图形；
对所述中间图形进行第二次构图工艺，形成位于所述布线区中的线路。
2.根据权利要求1所述的制备方法，其特征在于，对所述金属层进行第一次构图工艺，形成中间图形的步骤包括：
在所述金属层上形成第一光刻胶层；
采用第一掩膜板对所述第一光刻胶层进行曝光；
对曝光后的第一光刻胶层进行显影；
对所述金属层进行第一次刻蚀；
剥离残留的光刻胶，得到所述中间图形。
3.根据权利要求2所述的制备方法，其特征在于，对所述中间图形进行第二次构图工艺，形成位于所述布线区中的线路的步骤包括：
在所述中间图形上形成第二光刻胶层；
采用第二掩膜板对所述第二光刻胶层进行曝光；
对曝光后的第二光刻胶层进行显影；
对所述中间图形进行第二次刻蚀；
剥离残留的光刻胶，得到位于所述布线区中的线路。
4.根据权利要求1至3中任意一项所述的制备方法，其特征在于，所述阵列基板还包括源漏极层，位于所述布线区中的线路与所述源漏极层中的源极和漏极同层形成。
5.根据权利要求1至3中任意一项所述的制备方法，其特征在于，所述阵列基板还包括栅极层，位于所述布线区中的线路与所述栅极层中的栅极同层形成。
6.根据权利要求2或3所述的制备方法，其特征在于，所述第一光刻胶层为正性光刻胶层，所述第一掩膜板上对应于所述金属层上将形成所述中间图形的区域为遮光区，所述第一掩膜板上对应于所述金属层上将被去除部位的区域为透光区；
或者，所述第一光刻胶层为负性光刻胶层，所述第一掩膜板上对应于所述金属层上将形成所述中间图形的区域为透光区，所述第一掩膜板上对应于所述金属层上将被去除部位的区域为遮光区。
7.根据权利要求3所述的制备方法，其特征在于，所述第二光刻胶层为正性光刻胶层，所述第二掩膜板上对应于所述中间图形上将形成所述线路的区域为遮光区，所述第二掩膜板上对应于所述中间图形上将被去除部位的区域为透光区；
或者，所述第二光刻胶层为负性光刻胶层，所述第二掩膜板上对应于所述中间图形上将形成所述线路的区域为透光区，所述第二掩膜板上对应于所述中间图形上将被去除部位的区域为遮光区。
8.根据权利要求2或3所述的制备方法，其特征在于，对所述金属层进行第一次刻蚀的步骤中，刻蚀方法包括干刻或者湿刻。
9.根据权利要求3所述的制备方法，其特征在于，对所述中间图形进行第二次刻蚀的步骤中，刻蚀方法包括干刻或者湿刻。
10.一种阵列基板，其特征在于，所述阵列基板采用权利要求1至9中任意一项所述的制备方法制备形成。
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