WO2019178904A1 - 一种阵列基板及制备方法 - Google Patents

一种阵列基板及制备方法 Download PDF

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Publication number
WO2019178904A1
WO2019178904A1 PCT/CN2018/082734 CN2018082734W WO2019178904A1 WO 2019178904 A1 WO2019178904 A1 WO 2019178904A1 CN 2018082734 W CN2018082734 W CN 2018082734W WO 2019178904 A1 WO2019178904 A1 WO 2019178904A1
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Prior art keywords
light shielding
metal light
layer
shielding layer
substrate
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PCT/CN2018/082734
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English (en)
French (fr)
Inventor
韩约白
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武汉华星光电技术有限公司
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Priority to US16/072,504 priority Critical patent/US20190296154A1/en
Publication of WO2019178904A1 publication Critical patent/WO2019178904A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • the present invention relates to the field of array substrate manufacturing technology, and in particular, to an array substrate and a method for fabricating the same.
  • Low-temperature polysilicon panels have become the star products in flat panel display products due to their high resolution, high mobility, low power consumption, etc., and are widely used in major mobile phones such as Apple, Samsung, Huawei, Huawei and Meizu. And on the tablet computer, but due to the complicated process of the low-temperature polysilicon device, the top gate structure is used at present, so it is necessary to first form a layer of LS (light-shielding metal film, hereinafter referred to as LS) on the glass surface, and the LS is in the low-temperature polysilicon panel process.
  • the first film is located at the bottom of all the layers of the array.
  • Poly polysilicon film, hereinafter referred to as Poly
  • Poly will cross the LS edge, and the Poly film layer will be thin or even broken at the edge of the LS, resulting in Poly. Electrical anomalies occur at the LS edge climbing position, causing group dark spots and other defects.
  • the invention provides an array substrate and a preparation method thereof, which can prevent the polysilicon film from passing through the edge of the metal light shielding layer, thereby avoiding the problem that the polysilicon film is thinner at the edge of the metal light shielding layer, thereby achieving the purpose of improving product performance and improving product yield.
  • the invention provides an array substrate comprising:
  • a metal light shielding layer disposed on the surface of the substrate
  • the area of the metal light shielding layer is greater than or equal to the area of the polysilicon layer, and the projection of the polysilicon layer on the metal light shielding layer falls within the range of the metal light shielding layer, and the edge of the metal light shielding layer Is a straight line, a broken line, or an arc.
  • the metal light shielding layer has a U shape.
  • the width of the metal light shielding layer is 0.5 ⁇ m to 2 ⁇ m wider than the width of the polysilicon layer.
  • the metal light shielding layer has a rectangular or trapezoidal shape.
  • the invention also provides a method for preparing an array substrate, the method comprising the following steps:
  • Step S1 providing a substrate, preparing a spaced-apart metal light-shielding layer on the substrate;
  • Step S2 preparing a buffer layer having the same thickness as the metal light shielding layer on the substrate, patterning, removing the buffer layer corresponding to the metal light shielding layer, and forming the same as the metal light shielding layer a planar buffer layer pattern;
  • Step S3 preparing a buffer layer of a predetermined thickness on the buffer layer pattern and the metal light shielding layer;
  • Step S4 preparing a polysilicon layer on the buffer layer corresponding to the corresponding position of the metal light shielding layer, wherein the formed polysilicon layer has a uniform film thickness.
  • the metal light shielding layer has a U shape or a rectangular shape or a trapezoidal shape.
  • the edge of the metal light shielding layer is a straight line, a broken line or an arc.
  • the projection of the polysilicon layer on the substrate falls within the range of projection of the metallic light shielding layer on the substrate.
  • the projection of the polysilicon layer on the substrate does not completely overlap the projection of the metallic light shielding layer on the substrate.
  • the invention also provides an array substrate comprising:
  • a metal light shielding layer disposed on the surface of the substrate
  • the area of the metal light shielding layer is greater than or equal to the area of the polysilicon layer, and the projection of the polysilicon layer on the metal light shielding layer falls within the range of the metal light shielding layer.
  • the metal light shielding layer has a U shape.
  • the width of the metal light shielding layer is 0.5 ⁇ m to 2 ⁇ m wider than the width of the polysilicon layer.
  • the metal light shielding layer has a rectangular or trapezoidal shape.
  • the invention has the beneficial effects that the array substrate of the present invention is designed to have a U-shaped or rectangular or trapezoidal shape, and the shape is slightly larger than that of the polysilicon layer (1 micron), so that the metal is shielded from the prior art.
  • the layer completely blocks the polysilicon layer pattern, ensuring that the polysilicon layer does not cross the edge of the metal light shielding layer, and the problem that the polysilicon layer is thinner at the edge of the metal light shielding layer is avoided.
  • the buffer layer is prepared in two portions, and a buffer layer having the same thickness as the metal light-shielding film layer is prepared for the first time, and then patterned to form a buffer layer pattern coplanar with the metal light-shielding layer, and then in the metal light-shielding layer and buffer A second buffer layer preparation is performed on the flat surface formed by the layer pattern, so that the polysilicon layer is formed on the flat substrate, so that the film thickness of the polysilicon layer is kept uniform, thereby improving the electrical properties of the polysilicon layer and improving the product yield.
  • FIG. 1 is a top plan view showing a structure of a prior art array substrate
  • FIG. 2 is a cross-sectional view showing the structure of a prior art array substrate
  • FIG. 3 is a top plan view showing a structure of a portion of an array substrate provided by the present invention.
  • FIG. 4 is a cross-sectional view of the array substrate provided along the line A-A of the present invention.
  • Figure 5 is a cross-sectional view of the array substrate provided along the line B-B of the present invention.
  • FIG. 6 is a schematic structural view of an array substrate provided by the present invention.
  • FIG. 7 is a flow chart of a method for preparing an array substrate provided by the present invention.
  • the present invention is directed to a polysilicon thin film transistor of the prior art.
  • the film layer When a polysilicon layer is disposed, the film layer will cross the edge of the metal light shielding layer, resulting in a thin or even broken layer of the polysilicon layer at the edge of the metal light shielding layer, thereby causing polysilicon.
  • the electrical defects of the layer are liable to cause technical problems such as abnormalities such as bright spots and dark spots, and this embodiment can solve the defect.
  • FIG. 1 it is a top view of a structure of a prior art array substrate.
  • the array substrate includes: a metal light shielding layer 11 having a rectangular shape; a polysilicon layer 12 disposed on the metal light shielding layer 11; and a gate electrode 13 electrically disposed on the polysilicon layer Above the 12th.
  • the projection of the polysilicon layer 12 on the metal light shielding layer 11 passes through the edge of the metal light shielding layer 11.
  • FIG. 2 is a structural cross-sectional view of a prior art array substrate.
  • a buffer layer 22 is further disposed between the metal light-shielding layer 21 and the polysilicon layer 23. Since the metal light-shielding layer 21 is disposed to cause a corresponding position of the substrate to form a bump, causing unevenness of the film layer, the buffering is performed subsequently.
  • the layer 22 also forms a certain protrusion at a corresponding position.
  • the polysilicon layer 23 is prepared, since the polysilicon layer 23 needs to cross the edge of the metal light shielding layer 21, the polysilicon layer 23 corresponds to the corresponding layer.
  • the film layer at the edge position of the metal light shielding layer 21 has a climbing phenomenon, that is, the film layer at the position has a certain inclination angle, so that the film layer corresponding to the position is thin or even broken, thereby causing the polysilicon layer 23 to be electrically Poor, it is easy to cause abnormalities such as bright spots and dark spots.
  • FIG. 3 is a top plan view showing a part of the array substrate provided by the present invention.
  • the array substrate includes: a substrate 30; a metal light shielding layer 31; a polysilicon layer 32 disposed on the metal light shielding layer 31; a source 33 disposed in a source region of the polysilicon layer 32; and a drain 34 disposed on a drain region of the polysilicon layer 32; a gate electrode 35 is disposed above the polysilicon layer 32; wherein an area of the metal light shielding layer 31 is greater than or equal to an area of the polysilicon layer 32, the metal light shielding layer With the polysilicon layer 32 being distributed, the polysilicon layer 32 and the source 33 and the drain 34 are distributed in a U shape.
  • the metal light shielding layer 31 has a U shape, and the polysilicon The projection of the layer 32 on the metal light shielding layer 31 falls within the range of the metal light shielding layer 31.
  • the width of the metal light shielding layer 31 is 0.5 ⁇ m to 2 ⁇ m wider than the width of the polysilicon layer 32.
  • the width of the metal light shielding layer 31 is 1 micrometer wider than the width of the polysilicon layer 32.
  • the edge of the metal light-shielding layer 31 is a straight line, a broken line, an arc, or the like.
  • the shape of the metal light-shielding layer 31 may be a rectangle or a trapezoid, etc., and is not limited herein, as long as the polysilicon layer 32 can be completely blocked. .
  • the cross-sectional view of the array substrate along the AA line is as shown in FIG. 4 , the metal light shielding layer 41 is insulated from the polysilicon layer 42 , and the width of the metal light shielding layer 41 in the AA direction is larger than the polysilicon layer 42 , so that the The projection of the polysilicon layer 42 on the substrate falls into the projection of the metal light shielding layer 41 on the substrate, thereby maintaining the film thickness of the polysilicon layer 42 uniform.
  • a cross-sectional view of the polysilicon thin film transistor along line BB is as shown in FIG. 5, a metal light shielding layer 51 is insulated from the polysilicon layer 52, and a width of the metal light shielding layer 51 in the BB direction is larger than the polysilicon layer 52, so that The projection of the polysilicon layer 52 on the substrate falls into the projection of the metal light shielding layer 51 on the substrate, so that the film thickness of the polysilicon layer 52 is kept uniform. Thereby, the electrical properties of the polysilicon layer 52 are improved, and the product yield is improved.
  • FIG. 6 is a schematic structural diagram of an array substrate provided by the present invention.
  • the array substrate includes: a substrate 61; a metal light shielding layer 62 disposed at intervals on a surface of the substrate 61; and a buffer layer 63 disposed on the metal shading a layer 62 and a surface of the substrate 61; a polysilicon layer 64 corresponding to the metal light shielding layer 62 disposed on the surface of the buffer layer 63; a source 65 disposed in a source region of the polysilicon layer 64; and a drain 66 disposed on a drain region of the polysilicon layer 64; a gate 67, an insulating layer disposed above the polysilicon layer 64; wherein an area of the metal light shielding layer 62 is greater than or equal to an area of the polysilicon layer 64, and the polysilicon layer 64
  • the projection on the metal light shielding layer 62 falls within the range of the metal light shielding layer 62.
  • the metal light shielding layer 62 has a U shape.
  • the shape of the metal light shielding layer 62 may also be a shape such as a rectangle or a trapezoid.
  • the width of the metal light shielding layer 62 is wider than the width of the polysilicon layer 64 by 0.5 micrometers to 2 micrometers, preferably 1 micrometer.
  • the thickness of the film layer of the polysilicon layer 64 of the array substrate of the embodiment is kept uniform, thereby improving the electrical properties of the polysilicon layer 64 and improving the product yield.
  • the present invention also provides a method for preparing an array substrate, as shown in FIG. 7 , which is a flowchart of a method for preparing an array substrate provided by the present invention, and the method includes the following steps:
  • Step S1 providing a substrate, preparing a spaced-apart metal light-shielding layer on the substrate;
  • Step S2 preparing a buffer layer having the same thickness as the metal light shielding layer on the substrate, patterning, removing the buffer layer corresponding to the metal light shielding layer, and forming the same as the metal light shielding layer a planar buffer layer pattern;
  • Step S3 preparing a buffer layer of a predetermined thickness on the buffer layer pattern and the metal light shielding layer;
  • Step S4 preparing a polysilicon layer on the buffer layer corresponding to the corresponding position of the metal light shielding layer, wherein the formed polysilicon layer has a uniform film thickness.
  • a substrate is first provided, and a metal light shielding layer disposed at intervals is formed on the substrate, and the metal light shielding layer has a U shape or a rectangular shape or a trapezoidal shape.
  • the edge of the metal light shielding layer has a shape such as a straight line, a broken line, or an arc.
  • the buffer layer is prepared twice on the substrate.
  • a buffer layer having the same thickness as the metal light shielding layer is prepared on the substrate, and the buffer layer is patterned and etched correspondingly.
  • the buffer layer above the metal light shielding layer forms a buffer layer pattern coplanar with the metal light shielding layer; then a second preparation of the buffer layer is performed, and the metal light shielding layer and the buffer layer pattern are formed
  • a buffer layer of a predetermined thickness is further prepared on the flat surface, whereby a buffer layer having a flat surface is formed on the substrate, and a polysilicon layer is prepared at a position corresponding to the metal light shielding layer. Since the buffer layer is flat as the substrate of the polysilicon layer, the film thickness of the polysilicon layer can be kept uniform, thereby improving the electrical properties of the polysilicon layer.
  • the projection of the polysilicon layer on the substrate may fall within a range of projection of the metal light shielding layer on the substrate; or the projection of the polysilicon layer on the substrate and the metal shading The projections of the layers on the substrate may also not completely overlap.
  • the array substrate prepared by the method does not limit the size and shape of the metal light shielding layer and the polysilicon layer.
  • the array substrate of the present invention is designed to have a U-shaped or rectangular or trapezoidal shape, and the shape is slightly larger than that of the polysilicon layer (1 micron), so that the metal light shielding layer completely blocks the polysilicon layer pattern. It is ensured that the polysilicon layer does not cross the edge of the metal light shielding layer, and the problem that the polysilicon layer is thinner at the edge of the metal light shielding layer is avoided.
  • the buffer layer is prepared in two portions, and a buffer layer having the same thickness as the metal light-shielding film layer is prepared for the first time, and then patterned to form a buffer layer pattern coplanar with the metal light-shielding layer, and then in the metal light-shielding layer and buffer A second buffer layer preparation is performed on the flat surface formed by the layer pattern, so that the polysilicon layer is formed on the flat substrate, so that the film thickness of the polysilicon layer is kept uniform, thereby improving the electrical properties of the polysilicon layer and improving the product yield.

Abstract

一种阵列基板及制备方法，阵列基板包括：基板(30)；金属遮光层(31)，设置于基板(30)表面；多晶硅层(32)，设置于金属遮光层(31)之上；其中，金属遮光层(31)的面积大于或等于多晶硅层(32)的面积，且多晶硅层(32)在金属遮光层(31)上的投影落入金属遮光层(31)的范围内，多晶硅层(32)的膜层厚度均一。

Description

一种阵列基板及制备方法 技术领域
本发明涉及阵列基板制造技术领域，尤其涉及一种阵列基板及制备方法。
 背景技术
低温多晶硅面板借着其高分辨率，高迁移率，低功耗等诸多优点已成为了目前平板显示产品中的明星产品，被广泛应用在例如苹果、三星、华为、小米、魅族等各大手机及平板电脑上，但由于低温多晶硅器件制程复杂，目前多采用顶栅结构，因此需要在玻璃表面首先成膜一层LS（遮光层金属膜，后面简称为LS），LS位于低温多晶硅面板制程的第一道成膜，位于阵列所有膜层的最下面，传统设计中Poly（多晶硅薄膜，后面简称Poly）都会跨过LS边缘，在LS边缘位置会造成Poly膜层偏薄甚至断掉，导致Poly在LS边缘爬坡位置会发生电性异常，从而引起群亮暗点等不良。
因此，有必要提供一种阵列基板及制备方法，以解决现有技术所存在的问题。
 技术问题
本发明提供一种阵列基板及制备方法，能够避免多晶硅薄膜经过金属遮光层边缘，从而避免多晶硅薄膜在金属遮光层边缘膜层偏薄的问题，进而实现改善产品性能，提高产品良率的目的。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种阵列基板，包括：
基板；
金属遮光层，设置于所述基板表面；
多晶硅层，设置于所述金属遮光层之上；
其中，所述金属遮光层的面积大于等于所述多晶硅层的面积，且所述多晶硅层在所述金属遮光层上的投影落入所述金属遮光层的范围内，所述金属遮光层的边缘为直线、折线或者弧线。
根据本发明一优选实施例，所述金属遮光层的形状为U形。
根据本发明一优选实施例，所述金属遮光层的宽度比所述多晶硅层的宽度宽0.5微米~2微米。
根据本发明一优选实施例，所述金属遮光层的形状为矩形或梯形。
本发明还提供一种阵列基板的制备方法，所述方法包括以下步骤：
步骤S1、提供一基板，在所述基板上制备间隔分布的金属遮光层；
步骤S2、在所述基板上制备一层与所述金属遮光层厚度相同的缓冲层，进行图案化，将对应所述金属遮光层上方的所述缓冲层去除，形成与所述金属遮光层同平面的缓冲层图案；
步骤S3、在所述缓冲层图案以及所述金属遮光层上再制备一层预设厚度的缓冲层；
步骤S4、在所述缓冲层上对应所述金属遮光层的相应位置制备多晶硅层，其中，形成的所述多晶硅层的膜层厚度均一。
根据本发明一优选实施例，所述金属遮光层的形状为U形或矩形，或者梯形。
根据本发明一优选实施例，所述金属遮光层的边缘为直线、折线或者弧线。
根据本发明一优选实施例，所述多晶硅层在所述基板上的投影落入所述金属遮光层在所述基板上的投影的范围内。
根据本发明一优选实施例，所述多晶硅层在所述基板上的投影与所述金属遮光层在所述基板上的投影不完全重叠。
本发明还提供一种阵列基板，包括：
基板；
金属遮光层，设置于所述基板表面；
多晶硅层，设置于所述金属遮光层之上；
其中，所述金属遮光层的面积大于等于所述多晶硅层的面积，且所述多晶硅层在所述金属遮光层上的投影落入所述金属遮光层的范围内。
根据本发明一优选实施例，所述金属遮光层的形状为U形。
根据本发明一优选实施例，所述金属遮光层的宽度比所述多晶硅层的宽度宽0.5微米~2微米。
根据本发明一优选实施例，所述金属遮光层的形状为矩形或梯形。
 有益效果
本发明的有益效果为：相较于现有的阵列基板，本发明的阵列基板通过将金属遮光层设计为U形或者矩形或梯形，形状略大于多晶硅层(1微米即可)，使金属遮光层完全遮挡多晶硅层图案，保证了多晶硅层不会跨过金属遮光层的边缘，避免了多晶硅层在金属遮光层边缘位置处的膜层偏薄的问题。或者，将缓冲层分两次制备，第一次制备一层与金属遮光层膜层厚度相同的缓冲层，然后图案化形成与金属遮光层共平面的缓冲层图案，之后在金属遮光层与缓冲层图案形成的平坦的表面上进行第二次缓冲层制备，使得多晶硅层形成在平坦的基底上，从而使多晶硅层的膜层厚度保持均一，进而改善多晶硅层的电性，提高产品良率。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术的阵列基板的结构俯视图；
图2为现有技术的阵列基板的结构截面图；
图3为本发明提供的阵列基板局部的结构俯视图；
图4为本发明提供的阵列基板沿A-A线的截面图；
图5为本发明提供的阵列基板沿B-B线的截面图；
图6为本发明提供的阵列基板结构示意图；
图7为本发明提供的阵列基板的制备方法流程图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有技术的多晶硅薄膜晶体管，存在多晶硅层在设置时膜层会跨过金属遮光层的边缘，导致多晶硅层在金属遮光层边缘位置处的膜层偏薄甚至断掉，从而导致多晶硅层的电性不良，容易引起群亮暗点等显示异常的技术问题，本实施例能够解决该缺陷。
如图1所示，为现有技术的阵列基板的结构俯视图。所述阵列基板包括：金属遮光层11，所述金属遮光层11为间隔设置的矩形；多晶硅层12，设置于所述金属遮光层11之上；栅极13，绝缘的设置于所述多晶硅层12的上方。其中，所述多晶硅层12在所述金属遮光层11上的投影会经过所述金属遮光层11的边缘。
具体请参照图2所示，为现有技术的阵列基板的结构截面图。其中，金属遮光层21与多晶硅层23之间还设置有缓冲层22，由于所述金属遮光层21的设置会使基板的相应位置形成凸起，造成膜层的不平整，所以后续所述缓冲层22也会在相应位置形成一定的凸起，在所述多晶硅层23制备的时候，由于所述多晶硅层23需要对应跨过所述金属遮光层21的边缘，导致所述多晶硅层23对应所述金属遮光层21的边缘位置处的膜层存在爬坡现象，即该位置的膜层存在一定的倾斜角，使得该位置对应的膜层偏薄甚至断线，造成所述多晶硅层23电性不良，容易引起群亮暗点等显示异常的现象。
如图3所示，为本发明提供的阵列基板局部的结构俯视图。所述阵列基板包括：基板30；金属遮光层31；多晶硅层32，设置于所述金属遮光层31之上；源极33，设置于所述多晶硅层32的源区；漏极34，设置于所述多晶硅层32的漏区；栅极35，绝缘的设置于所述多晶硅层32的上方；其中，所述金属遮光层31的面积大于等于所述多晶硅层32的面积，所述金属遮光层31随所述多晶硅层32分布，所述多晶硅层32与所述源极33以及所述漏极34分布呈U形，优选的，所述金属遮光层31的形状为U形，且所述多晶硅层32在所述金属遮光层31上的投影落入所述金属遮光层31的范围内。所述金属遮光层31的宽度比所述多晶硅层32的宽度宽0.5微米~2微米。优选的，所述金属遮光层31的宽度比所述多晶硅层32的宽度宽1微米。
所述金属遮光层31的边缘为直线、折线或者弧线等，所述金属遮光层31的形状还可以为矩形或梯形等，此处不做限制，只要能完全遮挡所述多晶硅层32即可。
所述阵列基板沿A-A线的截面图如图4所示，金属遮光层41与多晶硅层42绝缘设置，且所述金属遮光层41在A-A方向上的宽度大于所述多晶硅层42，使得所述多晶硅层42在基板上的投影落入所述金属遮光层41在所述基板上的投影，从而使所述多晶硅层42的膜层厚度保持均一。
所述多晶硅薄膜晶体管沿B-B线的截面图如图5所示，金属遮光层51与多晶硅层52绝缘设置，且所述金属遮光层51在B-B方向上的宽度大于所述多晶硅层52，使得所述多晶硅层52在基板上的投影落入所述金属遮光层51在所述基板上的投影，从而使所述多晶硅层52的膜层厚度保持均一。从而改善所述多晶硅层52的电性，提高产品良率。
如图6所示，为本发明提供的阵列基板结构示意图，所述阵列基板包括：基板61；金属遮光层62，间隔的设置于所述基板61表面；缓冲层63，设置于所述金属遮光层62与所述基板61表面；多晶硅层64，对应所述金属遮光层62设置于所述缓冲层63表面；源极65，设置于所述多晶硅层64的源区；漏极66，设置于所述多晶硅层64的漏区；栅极67，绝缘设置于所述多晶硅层64的上方；其中，所述金属遮光层62的面积大于等于所述多晶硅层64的面积，且所述多晶硅层64在所述金属遮光层62上的投影落入所述金属遮光层62的范围内。优选的，所述金属遮光层62的形状为U形。所述金属遮光层62的形状还可以为矩形或梯形等形状。其中，所述金属遮光层62的宽度比所述多晶硅层64的宽度宽0.5微米~2微米，优选为1微米。本实施例的所述阵列基板的所述多晶硅层64的膜层厚度保持均一，从而改善所述多晶硅层64的电性，提高产品良率。
本发明还提供一种阵列基板的制备方法，如图7所示，为本发明提供的阵列基板的制备方法流程图，所述方法包括以下步骤：
步骤S1、提供一基板，在所述基板上制备间隔分布的金属遮光层；
步骤S2、在所述基板上制备一层与所述金属遮光层厚度相同的缓冲层，进行图案化，将对应所述金属遮光层上方的所述缓冲层去除，形成与所述金属遮光层同平面的缓冲层图案；
步骤S3、在所述缓冲层图案以及所述金属遮光层上再制备一层预设厚度的缓冲层；
步骤S4、在所述缓冲层上对应所述金属遮光层的相应位置制备多晶硅层，其中，形成的所述多晶硅层的膜层厚度均一。
具体地，先提供一基板，在所述基板上形成间隔设置的金属遮光层，所述金属遮光层的形状为U形或矩形，或者梯形。所述金属遮光层的边缘为直线、折线或者弧线等形状。之后在所述基板上进行两次缓冲层的制备，首先在所述基板上制备一层与所述金属遮光层的膜层厚度相同的缓冲层，对该缓冲层进行图案化，刻蚀掉对应所述金属遮光层上方的所述缓冲层，形成与所述金属遮光层共平面的缓冲层图案；之后进行缓冲层的第二次制备，在所述金属遮光层与所述缓冲层图案形成的平坦的表面上再制备一层预设厚度的缓冲层，由此，在所述基板上就形成了表面平坦的缓冲层，在所述缓冲层对应所述金属遮光层的位置制备多晶硅层。因为是以平坦的所述缓冲层作为所述多晶硅层的基底，所以所述多晶硅层的膜层厚度能够保持均一，从而改善了所述多晶硅层的电性。因此，所述多晶硅层在所述基板上的投影可以落入所述金属遮光层在所述基板上的投影的范围内；或者，所述多晶硅层在所述基板上的投影与所述金属遮光层在所述基板上的投影也可以不完全重叠。采用该方法制备的所述阵列基板，对所述金属遮光层以及所述多晶硅层的大小形状不做限制。
相较于现有的阵列基板，本发明的阵列基板通过将金属遮光层设计为U形或者矩形或梯形，形状略大于多晶硅层(1微米即可)，使金属遮光层完全遮挡多晶硅层图案，保证了多晶硅层不会跨过金属遮光层的边缘，避免了多晶硅层在金属遮光层边缘位置处的膜层偏薄的问题。或者，将缓冲层分两次制备，第一次制备一层与金属遮光层膜层厚度相同的缓冲层，然后图案化形成与金属遮光层共平面的缓冲层图案，之后在金属遮光层与缓冲层图案形成的平坦的表面上进行第二次缓冲层制备，使得多晶硅层形成在平坦的基底上，从而使多晶硅层的膜层厚度保持均一，进而改善多晶硅层的电性，提高产品良率。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (13)

  1. 一种阵列基板，其包括：
    基板；
    金属遮光层，设置于所述基板表面；
    多晶硅层，设置于所述金属遮光层之上；
    其中，所述金属遮光层的面积大于等于所述多晶硅层的面积，且所述多晶硅层在所述金属遮光层上的投影落入所述金属遮光层的范围内，所述金属遮光层的边缘为直线、折线或者弧线。
  2. 根据权利要求1所述的阵列基板，其中，所述金属遮光层的形状为U形。
  3. 根据权利要求1所述的阵列基板，其中，所述金属遮光层的宽度比所述多晶硅层的宽度宽0.5微米~2微米。
  4. 根据权利要求1所述的阵列基板，其中，所述金属遮光层的形状为矩形或梯形。
  5. 一种阵列基板的制备方法，其中，所述方法包括以下步骤：
    步骤S1、提供一基板，在所述基板上制备间隔分布的金属遮光层；
    步骤S2、在所述基板上制备一层与所述金属遮光层厚度相同的缓冲层，进行图案化，将对应所述金属遮光层上方的所述缓冲层去除，形成与所述金属遮光层同平面的缓冲层图案；
    步骤S3、在所述缓冲层图案以及所述金属遮光层上再制备一层预设厚度的缓冲层；
    步骤S4、在所述缓冲层上对应所述金属遮光层的相应位置制备多晶硅层，其中，形成的所述多晶硅层的膜层厚度均一。
  6. 根据权利要求5所述的制备方法，其中，所述金属遮光层的形状为U形或矩形，或者梯形。
  7. 根据权利要求5所述的制备方法，其中，所述金属遮光层的边缘为直线、折线或者弧线。
  8. 根据权利要求5所述的制备方法，其中，所述多晶硅层在所述基板上的投影落入所述金属遮光层在所述基板上的投影的范围内。
  9. 根据权利要求5所述的制备方法，其中，所述多晶硅层在所述基板上的投影与所述金属遮光层在所述基板上的投影不完全重叠。
  10. 一种阵列基板，其包括：
    基板；
    金属遮光层，设置于所述基板表面；
    多晶硅层，设置于所述金属遮光层之上；
    其中，所述金属遮光层的面积大于等于所述多晶硅层的面积，且所述多晶硅层在所述金属遮光层上的投影落入所述金属遮光层的范围内。
  11. 根据权利要求10所述的阵列基板，其中，所述金属遮光层的形状为U形。
  12. 根据权利要求10所述的阵列基板，其中，所述金属遮光层的宽度比所述多晶硅层的宽度宽0.5微米~2微米。
  13. 根据权利要求10所述的阵列基板，其中，所述金属遮光层的形状为矩形或梯形。
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