WO2020228168A1 - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

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Publication number
WO2020228168A1
WO2020228168A1 PCT/CN2019/101962 CN2019101962W WO2020228168A1 WO 2020228168 A1 WO2020228168 A1 WO 2020228168A1 CN 2019101962 W CN2019101962 W CN 2019101962W WO 2020228168 A1 WO2020228168 A1 WO 2020228168A1
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WIPO (PCT)
Prior art keywords
edge
color resist
display area
spacer
resist pattern
Prior art date
Application number
PCT/CN2019/101962
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English (en)
French (fr)
Inventor
叶成亮
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深圳市华星光电技术有限公司
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Publication of WO2020228168A1 publication Critical patent/WO2020228168A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate

Definitions

  • the present invention relates to the field of display technology, in particular to an array substrate and a manufacturing method thereof.
  • Liquid Crystal Display has many advantages such as thin body, power saving, no radiation, etc., and has been widely used, such as: mobile phones, personal digital assistants (PDA), digital cameras, computer screens and notebook computers Screen etc.
  • PDA personal digital assistants
  • LCD Liquid Crystal Display
  • backlight liquid crystal display devices which include a housing, a liquid crystal display panel arranged in the housing, and a backlight module (Backlight module).
  • the structure of a traditional liquid crystal display panel is composed of a color filter substrate (Color Filter), a thin film transistor array substrate (Thin Film Transistor Array Substrate, TFT Array Substrate), and a liquid crystal layer (Liquid Array Substrate) arranged between the two substrates.
  • Crystal Layer its working principle is to control the rotation of the liquid crystal molecules of the liquid crystal layer by applying a driving voltage on two glass substrates, and refract the light from the backlight module to produce a picture.
  • COA Color Filter on Array
  • the existing COA technology liquid crystal display panel combines an array substrate with a color filter layer and a common electrode and spacers. (PS) opposing substrates are obtained by pairing, which has the advantages of higher aperture ratio and smaller coupling capacitance.
  • an existing POA technology refers to fabricating the spacers of the opposing substrate on the array substrate prepared with a color filter layer, which can improve the display caused by the shift of the spacers of the curved panel Uneven (mura).
  • FIG. 1 is a schematic structural diagram of an existing liquid crystal display panel adopting POA technology.
  • the liquid crystal display panel has a display area 901 and a peripheral area 902 located outside the display area 901, and includes an array substrate 800 and a counter substrate 700 disposed oppositely.
  • the array substrate 800 includes a first substrate 810, and is disposed on the first substrate.
  • the edge spacers on the layer 850 and above the edge color block 842 also called redundant spacers, dummy PS
  • the thin film transistor array layer 820 includes a gate 821, a capacitor plate 822, and peripheral wiring 823 arranged on the first substrate 810, and a gate 821, a capacitor plate 822, and peripheral wiring 823 on the first substrate 810.
  • the drain 827, the gate 821, the capacitor plate 822, the active layer 824, the source 825, and the drain 826 are all located in the display area 901, and the peripheral wiring 823 is located in the peripheral area 902.
  • the counter substrate 700 includes a second substrate 710 and a common electrode layer 720 provided on the second substrate 710.
  • the liquid crystal display panel further includes a sealant (not shown) located between the array substrate 700 and the counter substrate 800 and located in the peripheral area 902.
  • the edge color resist block 842 and the edge spacer 873 are both located inside the sealant. Please refer to FIG. 2, the cross-sectional shape of the edge color resist block 842 is square, and its length and width are both about 100 ⁇ m. It is used to heighten the edge spacer 873 so that it can support the thickness of the panel box of the peripheral area 902.
  • the main spacer 871, the auxiliary spacer 872 and the edge spacer 873 are usually produced by forming a spacer material film on the second passivation layer 850, and then using a half-tone mask (half-tone mask). mask)
  • the spacer material film is patterned to obtain the main spacer 871, the auxiliary spacer 872, and the edge spacer 873.
  • the height of the main spacer 871 and the edge spacer 873 are generally set to be the same.
  • the spacer material film is generally a photoresist material with leveling properties, the spacer material film is colored at the edge.
  • the part above the block 842 is thinner than the part above the color resist pattern 841 in the display area. As shown in FIG.
  • the thickness of the panel box of 902 is effectively supported, so that the LCD panel has peripheral display unevenness, which affects the display quality.
  • the object of the present invention is to provide an array substrate, which can reduce the height difference between the main spacer and the edge spacer, and is applied to a liquid crystal display panel to improve the display quality of the liquid crystal display panel.
  • Another object of the present invention is to provide a manufacturing method of an array substrate, which can reduce the height difference between the main spacer and the edge spacer, and the prepared array substrate can be used in a liquid crystal display panel to improve the display quality of the liquid crystal display panel .
  • the present invention first provides an array substrate having a display area and a peripheral area located outside the display area; the array substrate includes an edge color resist pattern provided in the peripheral area and an edge color resist pattern. An edge spacer above the pattern; the edge color resist pattern includes a block part and a retaining wall located outside the block part.
  • the array substrate further includes a base substrate, a thin film transistor array layer provided on the base substrate, a first passivation layer provided on the thin film transistor array layer, a first passivation layer provided on the first passivation layer and located in the display area
  • the color resist pattern in the display area, the second passivation layer covering the color resist pattern in the display area, the edge color resist pattern is provided on the first passivation layer, the second passivation layer covers the edge color resist pattern, and the edge
  • the spacer is arranged on the second passivation layer.
  • the array substrate further includes main spacers and auxiliary spacers arranged on the second passivation layer at intervals and located in the display area; the main spacers and auxiliary spacers are both located above the color resist patterns in the display area ; The height of the auxiliary spacer is smaller than the height of the main spacer and the edge spacer.
  • the materials of the block and the retaining wall are the same or different.
  • the peripheral area includes a plastic frame coating area located outside the display area and spaced from the display area and a transition area between the plastic frame coating area and the display area.
  • the edge color resist pattern and the edge spacers are both located in the transition area. Area.
  • the retaining wall is ring-shaped.
  • the cross-sectional shape of the block portion is a square, and the cross-sectional shape of the retaining wall is a rectangular frame.
  • the length and width of the block portion are 105 ⁇ m-110 ⁇ m; the distance between the inner edge and the outer edge of the retaining wall is 20 ⁇ m-50 ⁇ m; the distance between the inner edge of the retaining wall and the edge of the block portion It is 10 ⁇ m-20 ⁇ m.
  • the array substrate further includes a pixel electrode disposed on the second passivation layer and located in the display area; the first passivation layer, the color resist pattern in the display area, and the second passivation layer are provided with via holes, the pixel The electrode is in contact with the thin film transistor array layer through the hole.
  • the present invention also provides a manufacturing method of the array substrate, including the following steps:
  • Step S1 Provide a base substrate, and fabricate a thin film transistor array layer on the base substrate;
  • Step S2 A first passivation layer is formed on the thin film transistor array layer, and a color resist pattern in the display area and an edge color resist pattern located outside the color resist pattern in the display area are formed on the first passivation layer. On the first passivation layer, Forming a second passivation layer on the color resist pattern and the edge color resist pattern in the display area;
  • the edge color resist pattern includes a block portion and a retaining wall located outside the block portion;
  • Step S3 forming a spacer material layer on the second passivation layer; patterning the spacer material layer to form a main spacer above the color resist pattern in the display area and an edge spacer above the edge color resist pattern Cushion.
  • the array substrate of the present invention has a display area and a peripheral area located outside the display area.
  • the array substrate includes an edge color resist pattern arranged in the peripheral area and an edge spacer located above the edge color resist pattern.
  • the color resistance pattern includes a block part and a retaining wall located outside the block part, so that the spacer material layer for making the main spacer and the edge spacer is formed above the color resistance pattern and the edge color resistance pattern in the display area ,
  • the leveling of the spacer material layer above the edge color resist pattern is greatly reduced, so that the final formed main spacer above the color resist pattern in the display area and the edge spacer above the edge color resist pattern
  • the height difference is reduced, and the display quality of the liquid crystal display panel can be improved.
  • the liquid crystal display panel of the present invention can reduce the height difference between the main spacer and the edge spacer, and the display quality is good.
  • FIG. 1 is a schematic cross-sectional view of an existing liquid crystal display panel using POA technology
  • FIG. 2 is a schematic top view of an edge color resist block of the liquid crystal display panel shown in FIG. 1;
  • FIG. 3 is a schematic top view of the array substrate of the present invention.
  • FIG. 5 is a schematic top view of the edge color resist pattern of the array substrate of the present invention.
  • step S1 of the manufacturing method of the array substrate of the present invention is a schematic diagram of step S1 of the manufacturing method of the array substrate of the present invention.
  • step S2 is a schematic diagram of step S2 of the manufacturing method of the array substrate of the present invention.
  • step S3 is a schematic diagram of step S3 of the manufacturing method of the array substrate of the present invention.
  • FIG. 10 is a schematic structural diagram of a liquid crystal display panel formed by a pair of an array substrate and a counter substrate of the present invention.
  • the present invention provides an array substrate using POA technology. Please refer to FIG. 3.
  • the array substrate has a display area 91 and a peripheral area 92 located outside the display area 91.
  • the array substrate includes an edge color resist pattern 32 provided in the peripheral area 92 and an edge spacer 42 located above the edge color resist pattern 32.
  • the edge color resist pattern 32 includes a block 321 and a retaining wall 322 located outside the block 321.
  • the array substrate further includes a base substrate 10, a thin film transistor array layer 20 provided on the base substrate 10, and a first passivation layer 20 provided on the thin film transistor array layer 20.
  • the second passivation layer 60 is provided on the first passivation layer 60 and is located in the display area 91 in the display area color resist pattern, and the second passivation layer 70 covering the display area color resist pattern 91, the edge color resist pattern 32 is provided On the first passivation layer 60, the second passivation layer 70 covers the edge color resist pattern 32, and the edge spacer 42 is provided on the second passivation layer 70.
  • the thin film transistor array layer 20 includes a gate 21, a capacitor plate 22, and peripheral wires 23 arranged on the base substrate 10 at intervals, and a gate 21, a capacitor
  • the source 26 and the drain 27 connected at both ends of 25, the gate 21, the capacitor plate 22, the active layer 25, the source 26 and the drain 27 are all located in the display area 91, and the peripheral wiring 23 is located in the peripheral area 92 .
  • the array substrate further includes main spacers 41 and auxiliary spacers 43 that are spaced apart on the second passivation layer 70 and located in the display area 91.
  • the main spacer 41 and the auxiliary spacer 43 are both located above the color resist pattern 31 in the display area.
  • the height of the auxiliary spacer 43 is smaller than the height of the main spacer 41 and the edge spacer 42.
  • the array substrate further includes a pixel electrode 50 disposed on the second passivation layer 70 and located in the display area 91.
  • the first passivation layer 60, the color resist pattern 31 in the display area, and the second passivation layer 70 are provided with a via 71, the via 71 is located above the drain 27, the pixel electrode 50 passes through the hole 71 and the thin film transistor array
  • the drain 27 of the layer 20 is in contact.
  • the materials of the block 321 and the retaining wall 322 may be the same or different.
  • the retaining wall 322 is ring-shaped.
  • the cross-sectional shape of the block 321 is a square
  • the cross-sectional shape of the retaining wall 322 is a rectangular frame.
  • the length and width of the block portion 321 are both 105 ⁇ m-110 ⁇ m.
  • the distance between the inner edge and the outer edge of the retaining wall 322 is 20 ⁇ m-50 ⁇ m.
  • the distance between the inner edge of the retaining wall 322 and the edge of the block 321 is 10 ⁇ m-20 ⁇ m.
  • the peripheral area 92 includes a plastic frame coating area 921 located outside the display area 91 and spaced from the display area 91 and a transition area 922 between the plastic frame coating area 921 and the display area 91
  • the edge color resist pattern 32 and the edge spacer 42 are both located in the transition area 922.
  • the array substrate of the present invention designs the shape of the edge color resist pattern 32 supporting the edge spacer 42 so that the edge color resist pattern 32 includes a block portion 321 and a retaining wall located outside the block portion 321 322, please refer to FIG. 9, after forming a spacer material layer 49 on the second passivation layer 70 on the color resist pattern 31 and the edge color resist pattern 32 in the display area, the spacer material layer 49 is on the edge The leveling of the part above the color resist pattern 32 is greatly reduced, so that compared with the prior art using block-shaped edge color resist blocks, the present invention can reduce the portion of the spacer material layer 49 above the edge color resist pattern 32 The difference between the thickness of the spacer material layer 49 and the thickness of the part of the spacer material layer 49 on the color resist pattern 31 of the display area, so that a halftone mask is used to pattern the spacer material layer 49 to produce the main spacer 41 The height difference between the edge spacer 42 and the edge spacer 42 is greatly reduced and tends to be consistent, so that, referring to
  • the edge spacer 42 can effectively support the thickness of the panel box in the peripheral area 92, which eliminates the problem that the edge spacer cannot effectively support the thickness of the panel box in the peripheral area in the prior art.
  • the display is uneven, thereby improving the display quality of the LCD panel.
  • the present invention also provides a manufacturing method of the above-mentioned array substrate, which includes the following steps:
  • Step S1 referring to FIG. 7, a base substrate 10 is provided, and a thin film transistor array layer 20 is fabricated on the base substrate 10.
  • the thin film transistor array layer 20 includes a gate 21, a capacitor electrode plate 22, and peripheral wiring 23 arranged on the base substrate 10 at intervals, and a gate electrode 21, a capacitor electrode plate 22 and the periphery arranged on the base substrate 10
  • Step S2 referring to FIG. 8, a first passivation layer 60 is formed on the thin film transistor array layer 20, and a color resist pattern 31 in the display area and an edge color located outside the color resist pattern 31 in the display area are formed on the first passivation layer 60
  • the resist pattern 32 forms a second passivation layer 70 on the first passivation layer 60, the display area color resist pattern 31 and the edge color resist pattern 32.
  • the edge color resist pattern 32 includes a block portion 321 and a retaining wall 322 located outside the block portion 321.
  • the materials of the block 321 and the retaining wall 322 may be the same or different.
  • the retaining wall 322 is ring-shaped.
  • the cross-sectional shape of the block 321 is a square
  • the cross-sectional shape of the retaining wall 322 is a rectangular frame.
  • the length and width of the block portion 321 are both 105 ⁇ m-110 ⁇ m.
  • the distance between the inner edge and the outer edge of the retaining wall 322 is 20 ⁇ m-50 ⁇ m.
  • the distance between the inner edge of the retaining wall 322 and the edge of the block 321 is 10 ⁇ m-20 ⁇ m.
  • step S2 after the second passivation layer 70 is formed, the first passivation layer 60, the color resist pattern 31 in the display area, and the second passivation layer 70 are patterned to form the drain located in the thin film transistor array layer 20. Via 71 above pole 27.
  • Step S3 referring to FIG. 9, a spacer material layer 49 is formed on the second passivation layer 70.
  • the spacer material layer 49 is patterned to form a main spacer 41 located above the color resist pattern 31 in the display area and an edge spacer 42 located above the edge color resist pattern 32, thereby forming as shown in FIGS. 3 and 4 The array substrate shown.
  • a half-tone mask is used to pattern the spacer material layer 49 to form the main spacer 41 and the edge spacer 42.
  • the spacer material layer 49 is patterned to form the main spacer 41 and the edge spacer 42 while also forming the color resist pattern 31 above the display area and spaced from the main spacer 41. ⁇ auxiliary spacer 43.
  • the height of the auxiliary spacer 43 is smaller than the height of the main spacer 41 and the edge spacer 42.
  • step S3 before forming the spacer material layer 49 on the second passivation layer 70, a pixel electrode 50 located above the color resist pattern 31 in the display area is also formed on the second passivation layer 70.
  • the pixel electrode 50 is in contact with the drain 27 of the thin film transistor array layer 20 through the hole 71.
  • the manufacturing method of the array substrate of the present invention designs the shape of the edge color resist pattern 32 supporting the edge spacer 42 so that the edge color resist pattern 32 includes a block 321 and is located outside the block 321
  • the retaining wall 322 please refer to FIG. 9, after forming a spacer material layer 49 on the second passivation layer 70 on the color resist pattern 31 and the edge color resist pattern 32 in the display area, the spacer material layer 49.
  • the leveling of the part above the edge color resist pattern 32 is greatly reduced, so that compared with the prior art using block-shaped edge color resist blocks, the present invention can reduce the spacer material layer 49 on the edge color resist pattern 32.
  • the array substrate made by the present invention is compared with the one including the opposing substrate substrate 81 and the common electrode 82 arranged in sequence.
  • the edge spacers 42 can effectively support the thickness of the panel in the peripheral area 92, eliminating the inability of the edge spacers to affect the thickness of the panel in the peripheral area in the prior art.
  • the uneven display caused by effective support improves the display quality of the liquid crystal display panel.
  • the array substrate of the present invention has a display area and a peripheral area located outside the display area.
  • the array substrate includes an edge color resist pattern provided in the peripheral area and an edge spacer located above the edge color resist pattern.
  • the edge color resist pattern includes a block shape. Part and the retaining wall located outside the block part, so that when the spacer material layer for the main spacer and the edge spacer is formed above the color resist pattern and the edge color resist pattern in the display area, the spacer material layer The leveling of the part above the edge color resist pattern is greatly reduced, so that the final height difference between the main spacer above the color resist pattern in the display area and the edge spacer above the edge color resist pattern is reduced, which can be improved
  • the display quality of the LCD panel can reduce the height difference between the main spacer and the edge spacer, and the display quality is good.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)

Abstract

一种阵列基板及其制作方法。阵列基板具有显示区及位于显示区外侧的外围区，阵列基板包括设于外围区内的边缘色阻图案及位于边缘色阻图案上方的边缘隔垫物，边缘色阻图案包括块状部及位于块状部外侧的挡墙，从而在显示区色阻图案及边缘色阻图案上方形成用于制作主隔垫物及边缘隔垫物的隔垫物材料层时，隔垫物材料层在边缘色阻图案上方的部分的流平性大大降低，使得最终形成的位于显示区色阻图案上方的主隔垫物与位于边缘色阻图案上方的边缘隔垫物的高度差降低，能够提升液晶显示面板的显示品质。

Description

阵列基板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制作方法。
 背景技术
液晶显示装置（Liquid Crystal Display，LCD）具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：移动电话、个人数字助理（PDA）、数字相机、计算机屏幕和笔记本电脑屏幕等。
现有市场上的液晶显示装置大部分为背光型液晶显示装置，其包括壳体、设于壳体内的液晶显示面板及设于壳体内的背光模组（Backlight module）。传统的液晶显示面板的结构是由一彩色滤光片基板（Color Filter）、一薄膜晶体管阵列基板（Thin Film Transistor Array Substrate，TFT Array Substrate）以及一配置于两基板间的液晶层（Liquid Crystal Layer）所构成，其工作原理是通过在两片玻璃基板上施加驱动电压来控制液晶层的液晶分子的旋转，将背光模组的光线折射出来产生画面。
COA（Color Filter on Array）技术是将彩色滤光层制备在阵列基板上的技术，现有的COA技术的液晶显示面板通过将制备有彩色滤光层的阵列基板与具有公共电极及隔垫物（PS）的对置基板进行对组而得到，具有开口率较高且耦合电容较小的优点。在COA技术基础上，现有一种POA技术，是指将对置基板的隔垫物制作在制备有彩色滤光层的阵列基板上，可以改善曲面面板的隔垫物位移（shift）造成的显示不均（mura）。
请参阅图1，为现有的一种采用POA技术的液晶显示面板的结构示意图。该液晶显示面板具有显示区901及位于显示区901外侧的外围区902，包括相对设置的阵列基板800及对置基板700，所述阵列基板800包括第一衬底810、设于第一衬底810上的薄膜晶体管阵列层820、设于薄膜晶体管阵列层820上的第一钝化层830、设于第一钝化层830上且位于显示区901内的显示区色阻图案841、设于第一钝化层830上且位于外围区902内的边缘色阻块（又称为冗余色阻块）842、覆盖显示区色阻图案841及边缘色阻块842的第二钝化层850、设于第二钝化层850上且位于显示区色阻图案841上方的像素电极860、主隔垫物（Main PS）871及辅助隔垫物（Sub PS）872以及设于第二钝化层850上且位于边缘色阻块842上方的边缘隔垫物（又称为冗余隔垫物，dummy PS）873。薄膜晶体管阵列层820包括间隔设于第一衬底810上栅极821、电容极板822及外围走线823、设于第一衬底810、栅极821、电容极板822及外围走线823上的栅极绝缘层824、设于栅极绝缘层824上且位于栅极821上方的有源层825、设于栅极绝缘层824上且分别与有源层825两端连接的源极826及漏极827，栅极821、电容极板822、有源层824、源极825及漏极826均位于显示区901内，外围走线823位于外围区902内。所述对置基板700包括第二衬底710及设于第二衬底710上的公共电极层720，对置基板700设有公共电极720的一侧与阵列基板800设有像素电极860的一侧相对。所述液晶显示面板还包括位于阵列基板700及对置基板800之间且位于外围区902的框胶（未图示），边缘色阻块842及边缘隔垫物873均位于框胶内侧。请参阅图2，所述边缘色阻块842的横截面形状为正方形，其长宽均为100μm左右，用于垫高边缘隔垫物873使其能够对外围区902的面板盒厚进行支撑，主隔垫物871、辅助隔垫物872及边缘隔垫物873在制作时，通常是在第二钝化层850上形成隔垫物材料膜，而后利用一道半色调光罩（half-tone mask）对隔垫物材料膜进行图案化，从而得到主隔垫物871、辅助隔垫物872及边缘隔垫物873。标准设计中，一般是设置主隔垫物871与边缘隔垫物873的高度相同，但由于隔垫物材料膜一般为光阻材料，具有流平性，因此隔垫物材料膜在边缘色阻块842上方的部分较显示区色阻图案841上方的部分薄，使得请参阅图1，边缘隔垫物873的高度会小于主隔垫物871的高度，使得边缘隔垫物873无法对外围区902的面板盒厚进行有效支撑，使得该液晶显示面板存在周边显示不均，影响显示品质。
 技术问题
本发明的目的在于提供一种阵列基板，能够降低主隔垫物与边缘隔垫物的高度差，应用于液晶显示面板中能够提升液晶显示面板的显示品质。
本发明的另一目的在于提供一种阵列基板的制作方法，能够降低主隔垫物与边缘隔垫物的高度差，制得的阵列基板应用于液晶显示面板中能够提升液晶显示面板的显示品质。
 技术解决方案
为实现上述目的，本发明首先提供一种阵列基板，所述阵列基板具有显示区及位于显示区外侧的外围区；所述阵列基板包括设于外围区内的边缘色阻图案及位于边缘色阻图案上方的边缘隔垫物；所述边缘色阻图案包括块状部及位于块状部外侧的挡墙。
所述阵列基板还包括衬底基板、设于衬底基板上的薄膜晶体管阵列层、设于薄膜晶体管阵列层上的第一钝化层、设于第一钝化层上且位于显示区内的显示区色阻图案、覆盖显示区色阻图案的第二钝化层，所述边缘色阻图案设于第一钝化层上，所述第二钝化层覆盖边缘色阻图案，所述边缘隔垫物设于第二钝化层上。
所述阵列基板还包括间隔设于第二钝化层上且位于显示区内的主隔垫物及辅助隔垫物；所述主隔垫物及辅助隔垫物均位于显示区色阻图案上方；所述辅助隔垫物的高度小于主隔垫物及边缘隔垫物的高度。
所述块状部及挡墙的材料相同或不同。
所述外围区包括位于显示区外侧且与显示区间隔的胶框涂布区及位于胶框涂布区与显示区之间的过渡区，所述边缘色阻图案及边缘隔垫物均位于过渡区内。
所述挡墙为环状。
所述块状部的横截面形状为正方形，所述挡墙的横截面形状为矩形框。
所述块状部的长宽均为105μm-110μm；所述挡墙的内侧边缘与外侧边缘之间的距离为20μm-50μm；所述挡墙的内侧边缘与块状部的边缘之间的距离为10μm-20μm。
所述阵列基板还包括设于第二钝化层上且位于显示区内的像素电极；所述第一钝化层、显示区色阻图案及第二钝化层设有过孔，所述像素电极经过孔与薄膜晶体管阵列层接触。
本发明还提供一种阵列基板的制作方法，包括如下步骤：
步骤S1、提供衬底基板，在衬底基板上制作薄膜晶体管阵列层；
步骤S2、在薄膜晶体管阵列层上形成第一钝化层，在第一钝化层上制作显示区色阻图案及位于显示区色阻图案外侧的边缘色阻图案，在第一钝化层、显示区色阻图案及边缘色阻图案上形成第二钝化层；
所述边缘色阻图案包括块状部及位于块状部外侧的挡墙；
步骤S3、在第二钝化层上形成隔垫物材料层；对隔垫物材料层进行图案化，形成位于显示区色阻图案上方的主隔垫物以及位于边缘色阻图案上方的边缘隔垫物。
 有益效果
本发明的有益效果：本发明的阵列基板具有显示区及位于显示区外侧的外围区，阵列基板包括设于外围区内的边缘色阻图案及位于边缘色阻图案上方的边缘隔垫物，边缘色阻图案包括块状部及位于块状部外侧的挡墙，从而在显示区色阻图案及边缘色阻图案上方形成用于制作主隔垫物及边缘隔垫物的隔垫物材料层时，隔垫物材料层在边缘色阻图案上方的部分的流平性大大降低，使得最终形成的位于显示区色阻图案上方的主隔垫物与位于边缘色阻图案上方的边缘隔垫物的高度差降低，能够提升液晶显示面板的显示品质。本发明液晶显示面板能够降低主隔垫物与边缘隔垫物的高度差，显示品质好。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的一种采用POA技术的液晶显示面板的剖视示意图；
图2为图1所示的液晶显示面板的边缘色阻块的俯视示意图；
图3为本发明的阵列基板的俯视示意图；
图4为本发明的阵列基板的剖视示意图；
图5为本发明的阵列基板的边缘色阻图案的俯视示意图；
图6为本发明的阵列基板的制作方法的流程图；
图7为本发明的阵列基板的制作方法的步骤S1的示意图；
图8为本发明的阵列基板的制作方法的步骤S2的示意图；
图9为本发明的阵列基板的制作方法的步骤S3的示意图；
图10为本发明的阵列基板与对置基板对组形成的液晶显示面板的结构示意图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
本发明提供一种采用POA技术的阵列基板，请参阅图3，所述阵列基板具有显示区91及位于显示区91外侧的外围区92。请结合图3及图4，所述阵列基板包括设于外围区92内的边缘色阻图案32及位于边缘色阻图案32上方的边缘隔垫物42。请结合图4及图5，所述边缘色阻图案32包括块状部321及位于块状部321外侧的挡墙322。
具体地，在图4所示的实施例中，所述阵列基板还包括衬底基板10、设于衬底基板10上的薄膜晶体管阵列层20、设于薄膜晶体管阵列层20上的第一钝化层60、设于第一钝化层60上且位于显示区91内的显示区色阻图案31、覆盖显示区色阻图案91的第二钝化层70，所述边缘色阻图案32设于第一钝化层60上，所述第二钝化层70覆盖边缘色阻图案32，所述边缘隔垫物42设于第二钝化层70上。
进一步地，请参阅图4，所述薄膜晶体管阵列层20包括间隔设于衬底基板10上栅极21、电容极板22及外围走线23、设于衬底基板10、栅极21、电容极板22及外围走线23上的栅极绝缘层24、设于栅极绝缘层24上且位于栅极21上方的有源层25、设于栅极绝缘层24上且分别与有源层25两端连接的源极26及漏极27，栅极21、电容极板22、有源层25、源极26及漏极27均位于显示区91内，外围走线23位于外围区92内。
具体地，在图4所示的实施例中，所述阵列基板还包括间隔设于第二钝化层70上且位于显示区91内的主隔垫物41及辅助隔垫物43。所述主隔垫物41及辅助隔垫物43均位于显示区色阻图案31上方。所述辅助隔垫物43的高度小于主隔垫物41及边缘隔垫物42的高度。
具体地，在图4所示的实施例中，所述阵列基板还包括设于第二钝化层70上且位于显示区91内的像素电极50。所述第一钝化层60、显示区色阻图案31及第二钝化层70设有过孔71，该过孔71位于漏极27上方，所述像素电极50经过孔71与薄膜晶体管阵列层20的漏极27接触。
具体地，所述块状部321及挡墙322的材料可以相同，也可以不同。
具体地，请参阅图5，所述挡墙322为环状。
优选地，请参阅图5，所述块状部321的横截面形状为正方形，所述挡墙322的横截面形状为矩形框。
更优选地，所述块状部321的长宽均为105μm-110μm。所述挡墙322的内侧边缘与外侧边缘之间的距离为20μm-50μm。所述挡墙322的内侧边缘与块状部321的边缘之间的距离为10μm-20μm。
具体地，请参阅图3，所述外围区92包括位于显示区91外侧且与显示区91间隔的胶框涂布区921及位于胶框涂布区921与显示区91之间的过渡区922，所述边缘色阻图案32及边缘隔垫物42均位于过渡区922内。
需要说明的是，本发明的阵列基板通过对支撑边缘隔垫物42的边缘色阻图案32的形状进行设计，使得边缘色阻图案32包括块状部321及位于块状部321外侧的挡墙322，从而请结合图9，在显示区色阻图案31及边缘色阻图案32上的第二钝化层70上形成一层隔垫物材料层49后，该隔垫物材料层49在边缘色阻图案32上方的部分的流平性大大降低，从而相比于现有技术采用块状的边缘色阻块，本发明能够减小隔垫物材料层49在边缘色阻图案32上方的部分的厚度与隔垫物材料层49在显示区色阻图案31上的部分的厚度的差值，从而采用一道半色调光罩对隔垫物材料层49进行图案化制作得到的主隔垫物41与边缘隔垫物42的高度差异被大大减小并趋于一致，使得请参阅图10，本发明的阵列基板与包括依次设置的对置基板衬底81及公共电极82的对置基板8进行对组形成液晶显示面板后，边缘隔垫物42能够对外围区92的面板盒厚进行有效的支撑，消除现有技术中由于边缘隔垫物无法对外围区的面板盒厚进行有效支撑而产生的显示不均，从而提升液晶显示面板的显示品质。
请参阅图6，基于同一发明构思，本发明还提供一种上述阵列基板的制作方法，包括如下步骤：
步骤S1、请参阅图7，提供衬底基板10，在衬底基板10上制作薄膜晶体管阵列层20。
具体地，所述薄膜晶体管阵列层20包括间隔设于衬底基板10上栅极21、电容极板22及外围走线23、设于衬底基板10、栅极21、电容极板22及外围走线23上的栅极绝缘层24、设于栅极绝缘层24上且位于栅极21上方的有源层25、设于栅极绝缘层24上且分别与有源层25两端连接的源极26及漏极27。
步骤S2、请参阅图8，在薄膜晶体管阵列层20上形成第一钝化层60，在第一钝化层60上制作显示区色阻图案31及位于显示区色阻图案31外侧的边缘色阻图案32，在第一钝化层60、显示区色阻图案31及边缘色阻图案32上形成第二钝化层70。请结合图8及图5，所述边缘色阻图案32包括块状部321及位于块状部321外侧的挡墙322。
具体地，所述块状部321及挡墙322的材料可以相同，也可以不同。
具体地，请参阅图5，所述挡墙322为环状。
优选地，请参阅图5，所述块状部321的横截面形状为正方形，所述挡墙322的横截面形状为矩形框。
更优选地，所述块状部321的长宽均为105μm-110μm。所述挡墙322的内侧边缘与外侧边缘之间的距离为20μm-50μm。所述挡墙322的内侧边缘与块状部321的边缘之间的距离为10μm-20μm。
具体地，所述步骤S2在形成第二钝化层70后还对第一钝化层60、显示区色阻图案31及第二钝化层70进行图案化形成位于薄膜晶体管阵列层20的漏极27上方的过孔71。
步骤S3、请参阅图9，在第二钝化层70上形成隔垫物材料层49。对隔垫物材料层49进行图案化，形成位于显示区色阻图案31上方的主隔垫物41以及位于边缘色阻图案32上方的边缘隔垫物42，从而形成如图3及图4所示的阵列基板。
具体地，所述步骤S3中采用一道半色调光罩对隔垫物材料层49进行图案化形成主隔垫物41及边缘隔垫物42。
具体地，所述步骤S3中对隔垫物材料层49进行图案化形成主隔垫物41及边缘隔垫物42的同时还形成位于显示区色阻图案31上方且与主隔垫物41间隔的辅助隔垫物43。辅助隔垫物43的高度小于主隔垫物41及边缘隔垫物42的高度。
具体地，所述步骤S3在第二钝化层70上形成隔垫物材料层49之前还在第二钝化层70上制作位于显示区色阻图案31上方的像素电极50，所述像素电极50经过孔71与薄膜晶体管阵列层20的漏极27接触。
需要说明的是，本发明的阵列基板的制作方法通过对支撑边缘隔垫物42的边缘色阻图案32的形状进行设计，使得边缘色阻图案32包括块状部321及位于块状部321外侧的挡墙322，从而请结合图9，在显示区色阻图案31及边缘色阻图案32上的第二钝化层70上形成一层隔垫物材料层49后，该隔垫物材料层49在边缘色阻图案32上方的部分的流平性大大降低，从而相比于现有技术采用块状的边缘色阻块，本发明能够减小隔垫物材料层49在边缘色阻图案32上方的部分的厚度与隔垫物材料层49在显示区色阻图案31上的部分的厚度的差值，从而采用一道半色调光罩对隔垫物材料层49进行图案化制作得到的主隔垫物41与边缘隔垫物42的高度差异被大大减小并趋于一致，使得请参阅图10，本发明制得的阵列基板与包括依次设置的对置基板衬底81及公共电极82的对置基板8进行对组形成液晶显示面板后，边缘隔垫物42能够对外围区92的面板盒厚进行有效的支撑，消除现有技术中由于边缘隔垫物无法对外围区的面板盒厚进行有效支撑而产生的显示不均，从而提升液晶显示面板的显示品质。
综上所述，阵列基板及其制作方法。本发明的阵列基板具有显示区及位于显示区外侧的外围区，阵列基板包括设于外围区内的边缘色阻图案及位于边缘色阻图案上方的边缘隔垫物，边缘色阻图案包括块状部及位于块状部外侧的挡墙，从而在显示区色阻图案及边缘色阻图案上方形成用于制作主隔垫物及边缘隔垫物的隔垫物材料层时，隔垫物材料层在边缘色阻图案上方的部分的流平性大大降低，使得最终形成的位于显示区色阻图案上方的主隔垫物与位于边缘色阻图案上方的边缘隔垫物的高度差降低，能够提升液晶显示面板的显示品质。本发明液晶显示面板能够降低主隔垫物与边缘隔垫物的高度差，显示品质好。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种阵列基板，具有显示区及位于显示区外侧的外围区；所述阵列基板包括设于外围区内的边缘色阻图案及位于边缘色阻图案上方的边缘隔垫物；所述边缘色阻图案包括块状部及位于块状部外侧的挡墙。
  2. 如权利要求1所述的阵列基板，还包括衬底基板、设于衬底基板上的薄膜晶体管阵列层、设于薄膜晶体管阵列层上的第一钝化层、设于第一钝化层上且位于显示区内的显示区色阻图案、覆盖显示区色阻图案的第二钝化层，所述边缘色阻图案设于第一钝化层上，所述第二钝化层覆盖边缘色阻图案，所述边缘隔垫物设于第二钝化层上。
  3. 如权利要求2所述的阵列基板，还包括间隔设于第二钝化层上且位于显示区内的主隔垫物及辅助隔垫物；所述主隔垫物及辅助隔垫物均位于显示区色阻图案上方；所述辅助隔垫物的高度小于主隔垫物及边缘隔垫物的高度。
  4. 如权利要求1所述的阵列基板，其中，所述块状部及挡墙的材料相同或不同。
  5. 如权利要求1所述的阵列基板，其中，所述外围区包括位于显示区外侧且与显示区间隔的胶框涂布区及位于胶框涂布区与显示区之间的过渡区，所述边缘色阻图案及边缘隔垫物均位于过渡区内。
  6. 如权利要求1所述的阵列基板，其中，所述挡墙为环状。
  7. 如权利要求6所述的阵列基板，其中，所述块状部的横截面形状为正方形，所述挡墙的横截面形状为矩形框。
  8. 如权利要求7所述的阵列基板，其中，所述块状部的长宽均为105μm-110μm；所述挡墙的内侧边缘与外侧边缘之间的距离为20μm-50μm；所述挡墙的内侧边缘与块状部的边缘之间的距离为10μm-20μm。
  9. 如权利要求1所述的阵列基板，还包括设于第二钝化层上且位于显示区内的像素电极；所述第一钝化层、显示区色阻图案及第二钝化层设有过孔，所述像素电极经过孔与薄膜晶体管阵列层接触。
  10. 一种阵列基板的制作方法，包括如下步骤：
    步骤S1、提供衬底基板，在衬底基板上制作薄膜晶体管阵列层；
    步骤S2、在薄膜晶体管阵列层上形成第一钝化层，在第一钝化层上制作显示区色阻图案及位于显示区色阻图案外侧的边缘色阻图案，在第一钝化层、显示区色阻图案及边缘色阻图案上形成第二钝化层；
    所述边缘色阻图案包括块状部及位于块状部外侧的挡墙；
    步骤S3、在第二钝化层上形成隔垫物材料层；对隔垫物材料层进行图案化，形成位于显示区色阻图案上方的主隔垫物以及位于边缘色阻图案上方的边缘隔垫物。
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