WO2019128966A1 - 一种阵列基板及其制备方法 - Google Patents

一种阵列基板及其制备方法 Download PDF

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Publication number
WO2019128966A1
WO2019128966A1 PCT/CN2018/123388 CN2018123388W WO2019128966A1 WO 2019128966 A1 WO2019128966 A1 WO 2019128966A1 CN 2018123388 W CN2018123388 W CN 2018123388W WO 2019128966 A1 WO2019128966 A1 WO 2019128966A1
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layer
buffer layer
polysilicon
prepared
light shielding
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PCT/CN2018/123388
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English (en)
French (fr)
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高玲
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武汉华星光电技术有限公司
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Publication of WO2019128966A1 publication Critical patent/WO2019128966A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133302—Rigid substrates, e.g. inorganic substrates

Definitions

  • the present invention relates to the field of display panel manufacturing technology, and in particular, to an array substrate and a method for fabricating the same.
  • the TFT substrate is fabricated by 12 to 14 lithography processes, the film structure is complicated, the production process is cumbersome, and the process precision is required to be higher and higher.
  • the first photolithographic LS film layer forms a metal light shielding layer 601 arranged in a matrix, there is a significant taper at the edge of each rectangular metal light shielding layer 601, which may result in uneven film layers in subsequent film layer fabrication.
  • a polycrystalline silicon (poly) layer 602 is a channel.
  • the thin film itself is thin and critical, and the thin portion corresponding to the metal light shielding layer 601 is thin, which may cause undesirable phenomena such as dark spots.
  • Metal 1 is used as a gate electrode 603, and a gate insulating layer 604 (SiOx/SiNx or the like) is used as a dielectric to constitute a TFT device (see FIG. 6).
  • a current in the direction of the polysilicon layer can be formed, which is the main driving current displayed in the plane; however, since the gate insulating layer 604 is thin at the edge of the polysilicon layer 602, that is, a1> A2, which is equivalent to two parasitic TFTs connected in parallel with the main TFT, which causes the edge channel to open in advance, and the vertical edge current appears, causing a hump effect, which affects the normal display of the panel.
  • the invention provides an array substrate and a preparation method thereof, which can improve defects caused by uneven thickness of other film layers caused by edges of the metal light shielding layer; and reduce the influence of the protrusion of the polysilicon layer, thereby improving the electrical conductivity of the TFT.
  • the invention provides an array substrate comprising:
  • a polysilicon layer corresponding to the metal light shielding layer is prepared on the second buffer layer;
  • a gate electrode corresponding to the polysilicon layer is prepared on the gate insulating layer
  • the second buffer layer is provided with a preset groove corresponding to the position of the polysilicon layer, and the polysilicon layer is located in the groove and is in the same plane as the surface of the second buffer layer, the groove The depth is the same as the thickness of the polysilicon layer.
  • the groove conforms to the shape of the polysilicon layer.
  • the thickness of the gate insulating layer corresponding to the corresponding portion of the polysilicon layer remains uniform.
  • the material of the first buffer layer/the second buffer layer is at least one or more of SiOx and SiNx.
  • the invention also provides a method for preparing the above array substrate, the method comprising the following steps:
  • Step S1 providing a substrate on which a metal light shielding layer, a first buffer layer, and a second buffer layer are sequentially prepared;
  • Step S2 performing a photolithography process on the second buffer layer, so that the second buffer layer forms a preset recess at a position corresponding to the metal light shielding layer;
  • Step S3 preparing a polysilicon film on the second buffer layer, patterning to form a polysilicon layer corresponding to the groove, and the polysilicon layer and the surface of the second buffer layer are in the same plane.
  • the groove depth is the same as the thickness of the polysilicon film.
  • the groove shape is consistent with the shape of the polysilicon layer.
  • the step S1 includes:
  • Step S101 providing a substrate substrate on which a patterned metal light shielding layer is prepared, and first coating a first buffer layer having the same thickness as the metal light shielding layer on the substrate substrate;
  • Step S102 patterning the first buffer layer, and etching corresponding portions of the first buffer layer corresponding to the metal light shielding layer, so that the thickness of the patterned first buffer layer and the metal light shielding layer are located same plane;
  • Step S103 further coating a first thickness of the first buffer layer on the patterned first buffer layer and the metal light shielding layer;
  • Step S104 coating a second buffer layer on the first buffer layer.
  • the method further comprises the following steps:
  • Step S4 preparing a gate insulating layer on the second buffer layer and the polysilicon layer
  • Step S5 preparing a gate on the gate insulating layer, the gate facing the polysilicon layer.
  • the gate insulating layer maintains a uniform film thickness corresponding to the polysilicon layer.
  • an array substrate including:
  • a polysilicon layer corresponding to the metal light shielding layer is prepared on the second buffer layer;
  • a gate electrode corresponding to the polysilicon layer is prepared on the gate insulating layer
  • the second buffer layer is provided with a preset groove corresponding to the position of the polysilicon layer, and the polysilicon layer is located in the groove and is in the same plane as the surface of the second buffer layer.
  • the groove conforms to the shape of the polysilicon layer.
  • the thickness of the gate insulating layer corresponding to the corresponding portion of the polysilicon layer remains uniform.
  • the material of the first buffer layer/the second buffer layer is at least one or more of SiOx and SiNx.
  • the beneficial effects of the present invention are as follows: the array substrate of the present invention and the preparation method thereof are compared with the prior art TFT substrate process, and the first buffer layer prepared on the metal light shielding layer is completed by two coatings, first After the second coating, a first buffer layer pattern which is in the same layer as the metal light shielding layer and has the same film thickness is formed by the photomask, that is, there is no step, and then the second coating is performed according to the actual film thickness requirement.
  • the film layer is made on the flat film layer so as not to affect the thickness of the film layer. When the film layer is made, it will not be uneven due to unevenness of the film surface, which can effectively improve the thickness unevenness of the film layer. problem.
  • the second buffer layer after the film formation can be subjected to a mask process to form a groove conforming to the design value of the shape and thickness of the polysilicon layer pattern, and the polysilicon layer is patterned in the groove.
  • the polysilicon layer is flat with other regions of the second buffer layer, and there is no step, and the polysilicon layer bump is prevented from affecting the uneven film formation of the subsequent gate insulating layer.
  • the preparation method of the invention greatly improves the product yield, effectively improves the TFT hump effect, and improves the panel driving performance.
  • FIG. 1 is a schematic structural view of an array substrate provided by the present invention.
  • FIG. 2 is a flow chart of a method for preparing an array substrate according to Embodiment 1 of the present invention
  • 3a-3d are schematic flow charts of a method for preparing an array substrate provided in the first embodiment
  • 5a-5c are schematic flowcharts of a method for preparing an array substrate provided in the second embodiment
  • FIG. 6 is a schematic structural view of a TFT substrate of the prior art.
  • the invention is directed to the existing TFT substrate process, the phenomenon that the thickness of other film layers is uneven due to the edge of the metal light shielding layer, and the film formation of the gate insulating layer caused by the protrusion of the polysilicon layer is uneven, thereby causing the hump effect of the TFT and affecting the panel.
  • This embodiment can solve the drawback of the technical problem of electrical quality.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by the present invention.
  • the array substrate includes: a base substrate 101; a metal light shielding layer 102 is prepared on the base substrate 101; and a first buffer layer 103 is prepared on a second buffer layer 104 is formed on the first buffer layer 103; and a polysilicon layer 105 is formed on the second buffer layer 104 corresponding to the metal light shielding layer 102;
  • the layer 106 is prepared on the second buffer layer 104 and the polysilicon layer 105.
  • the gate 107 is formed on the gate insulating layer 106 corresponding to the polysilicon layer 105.
  • the second buffer layer 104 is disposed with a preset groove 108 corresponding to the position of the polysilicon layer 105.
  • the polysilicon layer 105 is located in the groove 108 and is in the same state as the surface of the second buffer layer 104. flat.
  • the groove 108 is in the same shape as the polysilicon layer 105.
  • the depth of the groove 108 is the same as the thickness of the polysilicon layer 105, that is, the polysilicon layer 105 is embedded on the surface of the second buffer layer 104.
  • the polysilicon layer 105 located within the recess 108 forms a coplanar with the non-groove of the second buffer layer 104.
  • the thickness of the gate insulating layer 106 corresponding to the corresponding portion of the polysilicon layer 105 is uniform. It can be understood that the thickness of the film of the gate insulating layer 106 is consistent.
  • the TFT device is driven by a voltage to form a current along the direction of the polysilicon layer 105 without a hump effect and a dark spot phenomenon.
  • the material of the first buffer layer 103 / the second buffer layer 104 is at least one or more of SiOx and SiNx.
  • the material of the first buffer layer 103 is SiNx
  • the material of the second buffer layer 104 is SiOx
  • the material of the gate insulating layer 106 is SiOx.
  • a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention includes the following steps:
  • Step S1 providing a substrate on which a metal light shielding layer, a first buffer layer, and a second buffer layer are sequentially prepared;
  • Step S2 performing a photolithography process on the second buffer layer, so that the second buffer layer forms a preset recess at a position corresponding to the metal light shielding layer;
  • Step S3 preparing a polysilicon film on the second buffer layer, patterning to form a polysilicon layer corresponding to the groove, and the polysilicon layer and the surface of the second buffer layer are in the same plane.
  • FIGS. 3a-3d a schematic flowchart of a method for fabricating an array substrate according to the first embodiment is shown.
  • a metal light shielding layer 302, a first buffer layer 303, and a second buffer layer 304 are sequentially formed on the substrate 301.
  • the second buffer layer 304 is patterned to form a recess 305 corresponding to the design value of the shape and thickness of the polysilicon layer at a position corresponding to the metal light shielding layer 302.
  • a polysilicon film 306 is prepared on the second buffer layer 304, and the polysilicon film 306 has the same thickness as the groove 305.
  • the polysilicon film 306 is patterned to form a polysilicon layer 307 located in the recess, and the polysilicon layer 307 is in the same plane as the non-groove of the second buffer layer 304.
  • the method also includes the following steps:
  • Step S4 preparing a gate insulating layer on the second buffer layer and the polysilicon layer
  • Step S5 preparing a gate on the gate insulating layer, the gate facing the polysilicon layer.
  • the array substrate prepared by the method provided by the embodiment has a uniform thickness of the gate insulating layer at a corresponding portion of the corresponding polysilicon layer, thereby ensuring electrical quality of the array substrate.
  • the second embodiment provides another method for preparing the array substrate of the present invention. This embodiment further improves the solution of the first embodiment. As shown in FIG. 4, the method includes the following steps:
  • Step S101 providing a substrate substrate on which a patterned metal light shielding layer is prepared, and first coating a first buffer layer having the same thickness as the metal light shielding layer on the substrate substrate;
  • Step S102 patterning the first buffer layer, and etching corresponding portions of the first buffer layer corresponding to the metal light shielding layer, so that the thickness of the patterned first buffer layer and the metal light shielding layer are located same plane;
  • Step S103 further coating a first thickness of the first buffer layer on the patterned first buffer layer and the metal light shielding layer;
  • Step S104 coating a second buffer layer on the first buffer layer.
  • a flow chart of a method for fabricating an array substrate provided in the second embodiment provides a substrate 501 on which a metal light shielding layer 502 is formed.
  • a first buffer layer 503 having the same thickness as the metal light shielding layer 502 is first coated on the substrate 501. Patterning the first buffer layer 503, etching a corresponding portion of the first buffer layer 503 overlapping the metal light shielding layer 502, forming a first buffer layer pattern 504, and patterning the first buffer layer
  • the layer 503 and the metal light shielding layer 502 have the same plane thickness, that is, the first buffer layer pattern 504 and the metal light shielding layer 502 have the same thickness and form the same plane.
  • the first buffer layer 503 of a predetermined thickness is further coated on the patterned first buffer layer 503 and the metal light shielding layer 502 according to the film thickness requirement. Applying a second buffer layer on the coated first buffer layer 503, wherein the second buffer layer, the polysilicon layer, the gate insulating layer and the gate are prepared in the same manner as in the first embodiment, I will not repeat them here.
  • the first buffer layer prepared on the metal light shielding layer is completed by two coatings, and the first coating is passed through the photomask.
  • a first buffer layer pattern in the same layer as the metal light-shielding layer and having the same film thickness is formed, that is, there is no step, and then a second coating is performed according to the actual film thickness requirement.
  • the film layer is made on the flat film layer so as not to affect the thickness of the film layer. When the film layer is made, it will not be uneven due to unevenness of the film surface, which can effectively improve the thickness unevenness of the film layer. problem.
  • the second buffer layer after the film formation can be subjected to a mask process to form a groove conforming to the design value of the shape and thickness of the polysilicon layer pattern, and the polysilicon layer is patterned in the groove.
  • the polysilicon layer is flat with other regions of the second buffer layer, and there is no step, and the polysilicon layer bump is prevented from affecting the uneven film formation of the subsequent gate insulating layer.
  • the preparation method of the invention greatly improves the product yield, effectively improves the TFT hump effect, and improves the panel driving performance.

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Abstract

本发明提供一种阵列基板及其制备方法，阵列基板包括：依次制备于衬底基板上的金属遮光层、第一缓冲层、第二缓冲层、多晶硅层、栅绝缘层及栅极。其中，第二缓冲层对应多晶硅层的位置设置有预设凹槽，多晶硅层位于凹槽内，且与第二缓冲层表面处于同平面，从而解决阵列基板膜层厚度不均问题。

Description

一种阵列基板及其制备方法 技术领域
本发明涉及显示面板制造技术领域，尤其涉及一种阵列基板及其制备方法。
 背景技术
在液晶面板制备过程中，TFT基板由12~14道光刻工艺制作而成，膜层结构复杂，生产流程繁琐，对制程精度要求越来越高。因第一道光刻LS膜层形成矩阵排布的金属遮光层601，在每个矩形金属遮光层601边缘会有明显凸起（taper），在后续膜层制作中会因此而膜层不均。尤其明显的是作为沟道的多晶硅（poly）层602，此膜层本身较薄，又很关键，在对应所述金属遮光层601凸起处偏薄，会导致群暗点等不良现象。一般将Metal 1作为Gate极603，栅绝缘层604（SiOx/SiNx等）作介质，构成TFT器件（如图6）。
在TFT器件中，通过电压驱动，可形成沿多晶硅层方向的电流，此为面内显示的主要驱动电流；但是，由于所述多晶硅层602边缘处所述栅绝缘层604偏薄，即a1>a2, 相当于两个寄生TFT与主TFT并联，这会导致边缘沟道提前开启，出现垂直方向的边缘电流，出现驼峰效应（Hump effect），影响面板正常显示。
综上所述，现有的TFT基板制程中，存在着金属遮光层边缘造成其他膜层厚度不均，以及多晶硅层凸起造成的栅绝缘层成膜不均的现象，从而引起TFT的驼峰效应，影响面板电性品质。
 技术问题
本发明提供一种阵列基板及其制备方法，能够改善由于金属遮光层边缘造成的其他膜层厚度不均而导致的不良；以及减小多晶硅层凸起的影响，从而改善TFT的电性曲线。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种阵列基板，包括：
衬底基板；
金属遮光层，制备于所述衬底基板上；
第一缓冲层，制备于所述衬底基板上；
第二缓冲层，制备于所述第一缓冲层上；以及
多晶硅层，对应所述金属遮光层制备于所述第二缓冲层上；
栅绝缘层，制备于所述第二缓冲层以及所述多晶硅层上；
栅极，对应所述多晶硅层制备于所述栅绝缘层上；
其中，所述第二缓冲层对应所述多晶硅层的位置设置有预设凹槽，所述多晶硅层位于所述凹槽内，且与所述第二缓冲层表面处于同平面，所述凹槽深度与所述多晶硅层厚度相同。
在本申请的阵列基板中，所述凹槽与所述多晶硅层的形状一致。
在本申请的阵列基板中，所述栅绝缘层对应所述多晶硅层的相应部分的厚度保持均一。
在本申请的阵列基板中，所述第一缓冲层/所述第二缓冲层的材料至少为SiOx、SiNx中的一种或一种以上。
本发明还提供一种上述阵列基板的制备方法，所述方法包括以下步骤：
步骤S1：提供一衬底基板，在所述衬底基板上依次制备金属遮光层、第一缓冲层以及第二缓冲层；
步骤S2：对所述第二缓冲层进行光刻制程，使所述第二缓冲层在对应所述金属遮光层的位置形成预设凹槽；
步骤S3：在所述第二缓冲层上制备一层多晶硅膜，图案化后形成对应所述凹槽的多晶硅层，且所述多晶硅层与所述第二缓冲层表面处于同平面。
在本申请的制备方法中，所述凹槽深度与所述多晶硅膜厚度相同。
在本申请的制备方法中，所述凹槽形状与所述多晶硅层形状一致。
在本申请的制备方法中，所述步骤S1包括：
步骤S101：提供一衬底基板，所述衬底基板上制备有图案化的金属遮光层，在所述衬底基板上先涂布一层与所述金属遮光层厚度相同的第一缓冲层；
步骤S102：图案化所述第一缓冲层，对所述第一缓冲层对应所述金属遮光层的相应部分进行蚀刻，使图案化的所述第一缓冲层与所述金属遮光层的厚度位于同一平面；
步骤S103：在图案化的所述第一缓冲层以及所述金属遮光层上再涂布一层预设厚度的所述第一缓冲层；
步骤S104：在所述第一缓冲层上涂布第二缓冲层。
在本申请的制备方法中，所述方法还包括以下步骤：
步骤S4：在所述第二缓冲层以及所述多晶硅层上制备栅绝缘层；
步骤S5：在所述栅绝缘层上制备栅极，所述栅极正对所述多晶硅层。
在本申请的制备方法中，所述栅绝缘层对应所述多晶硅层的部分膜厚保持均一。
为解决上述问题，本发明还提供一种阵列基板，包括：
衬底基板；
金属遮光层，制备于所述衬底基板上；
第一缓冲层，制备于所述衬底基板上；
第二缓冲层，制备于所述第一缓冲层上；以及
多晶硅层，对应所述金属遮光层制备于所述第二缓冲层上；
栅绝缘层，制备于所述第二缓冲层以及所述多晶硅层上；
栅极，对应所述多晶硅层制备于所述栅绝缘层上；
其中，所述第二缓冲层对应所述多晶硅层的位置设置有预设凹槽，所述多晶硅层位于所述凹槽内，且与所述第二缓冲层表面处于同平面。
在本申请的阵列基板中，所述凹槽与所述多晶硅层的形状一致。
在本申请的阵列基板中，所述栅绝缘层对应所述多晶硅层的相应部分的厚度保持均一。
在本申请的阵列基板中，所述第一缓冲层/所述第二缓冲层的材料至少为SiOx、SiNx中的一种或一种以上。
 有益效果
本发明的有益效果为：相较于现有技术的TFT基板制程，本发明的阵列基板及其制备方法，将制备于金属遮光层上的第一缓冲层通过两次涂布来完成，第一次涂布后通过光罩形成与金属遮光层同层且同样膜厚的第一缓冲层图案，即无段差，然后再根据实际膜厚需求进行第二次涂布。后面膜层制作均是在平坦膜层上制作，从而不会对后面膜层厚度造成影响，较薄膜层制作时不会因表面不平而膜厚不均，可有效改善较薄膜层的厚度不均问题。本发明还可通过对成膜后的第二缓冲层进行光罩制程，形成与多晶硅层图案的形状及厚度的设计值一致的凹槽，将多晶硅层图案化于所述凹槽内。这样多晶硅层与第二缓冲层其他区域持平，无段差，避免多晶硅层凸起对后续栅绝缘层成膜不均造成影响。本发明的制备方法大大提升产品良率，有效改善TFT驼峰效应，提高面板驱动性能。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明提供的阵列基板结构示意图；
图2为本发明实施例一提供的阵列基板的制备方法流程图；
图3a-3d为实施例一提供的阵列基板制备方法流程示意图；
图4为本发明实施例二提供的阵列基板的制备方法流程图；
图5a-5c为实施例二提供的阵列基板制备方法流程示意图；
图6为现有技术TFT基板结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有TFT基板制程中，存在着金属遮光层边缘造成其他膜层厚度不均，以及多晶硅层凸起造成的栅绝缘层成膜不均的现象，从而引起TFT的驼峰效应，影响面板电性品质的技术问题，本实施例能够解决该缺陷。
下面结合附图详细介绍本发明具体实施例提供的阵列基板及其制备方法。
如图1所示，为本发明提供的阵列基板结构示意图，所述阵列基板包括：衬底基板101；金属遮光层102，制备于所述衬底基板101上；第一缓冲层103，制备于所述衬底基板101上；第二缓冲层104，制备于所述第一缓冲层103上；以及多晶硅层105，对应所述金属遮光层102制备于所述第二缓冲层104上；栅绝缘层106，制备于所述第二缓冲层104以及所述多晶硅层105上；栅极107，对应所述多晶硅层105制备于所述栅绝缘层106上。其中，所述第二缓冲层104对应所述多晶硅层105的位置设置有预设凹槽108，所述多晶硅层105位于所述凹槽108内，且与所述第二缓冲层104表面处于同平面。所述凹槽108与所述多晶硅层105的形状一致，所述凹槽108的深度与所述多晶硅层105的厚度相同，即所述多晶硅层105嵌设于所述第二缓冲层104表面，位于所述凹槽108内的所述多晶硅层105与所述第二缓冲层104的非凹槽处形成共平面。所述栅绝缘层106对应所述多晶硅层105的相应部分的厚度保持均一，可以理解的是，所述栅绝缘层106的膜层厚度保持一致。
本实施例提供的阵列基板，TFT器件通过电压驱动，可形成沿所述多晶硅层105方向的电流，不会出现驼峰效应以及群暗点现象。所述第一缓冲层103/所述第二缓冲层104的材料至少为SiOx、SiNx中的一种或一种以上。优选的，所述第一缓冲层103的材料为SiNx，所述第二缓冲层104的材料为SiOx，所述栅绝缘层106的材料为SiOx。
如图2所示，为本发明实施例提供的阵列基板的制备方法流程图，上述阵列基板的制备方法包括以下步骤：
步骤S1：提供一衬底基板，在所述衬底基板上依次制备金属遮光层、第一缓冲层以及第二缓冲层；
步骤S2：对所述第二缓冲层进行光刻制程，使所述第二缓冲层在对应所述金属遮光层的位置形成预设凹槽；
步骤S3：在所述第二缓冲层上制备一层多晶硅膜，图案化后形成对应所述凹槽的多晶硅层，且所述多晶硅层与所述第二缓冲层表面处于同平面。
具体地，参照图3a-3d所示，为实施例一提供的阵列基板制备方法流程示意图，在衬底基板301上依次制备金属遮光层302、第一缓冲层303以及第二缓冲层304。图案化所述第二缓冲层304，在对应所述金属遮光层302的位置形成与多晶硅层形状及厚度的设计值一致的凹槽305。在所述第二缓冲层304上制备一层多晶硅膜306，所述多晶硅膜306厚度与所述凹槽305深度相同。图案化所述多晶硅膜306，形成位于所述凹槽内的多晶硅层307，且所述多晶硅层307与所述第二缓冲层304的非凹槽处处于同平面。
所述方法还包括以下步骤：
步骤S4：在所述第二缓冲层以及所述多晶硅层上制备栅绝缘层；
步骤S5：在所述栅绝缘层上制备栅极，所述栅极正对所述多晶硅层。
通过本实施例提供的方法制备的阵列基板，其中栅绝缘层在对应多晶硅层的相应部分的厚度均一，保证了阵列基板的电性品质。
实施例二提供了另一种制备本发明阵列基板的方法，本实施例在实施例一的方案上做了进一步的改进，如图4所示，所述方法包括以下步骤：
步骤S101：提供一衬底基板，所述衬底基板上制备有图案化的金属遮光层，在所述衬底基板上先涂布一层与所述金属遮光层厚度相同的第一缓冲层；
步骤S102：图案化所述第一缓冲层，对所述第一缓冲层对应所述金属遮光层的相应部分进行蚀刻，使图案化的所述第一缓冲层与所述金属遮光层的厚度位于同一平面；
步骤S103：在图案化的所述第一缓冲层以及所述金属遮光层上再涂布一层预设厚度的所述第一缓冲层；
步骤S104：在所述第一缓冲层上涂布第二缓冲层。
具体地，参照图5a-5c所示，为实施例二提供的阵列基板制备方法流程示意图，提供一衬底基板501，所述衬底基板501上制备有金属遮光层502，在所述衬底基板501上先涂布一层与所述金属遮光层502厚度相同的第一缓冲层503。图案化所述第一缓冲层503，将与所述金属遮光层502重叠的所述第一缓冲层503的相应部分蚀刻掉，形成第一缓冲层图案504，使图案化的所述第一缓冲层503与所述金属遮光层502的厚度位于同一平面，即所述第一缓冲层图案504与所述金属遮光层502的厚度相同，形成同一平面。根据膜厚需求，在图案化后的所述第一缓冲层503以及所述金属遮光层502上再涂布预设厚度的所述第一缓冲层503。在涂布完成的所述第一缓冲层503上涂布第二缓冲层，其中，所述第二缓冲层、多晶硅层、栅绝缘层以及栅极的制备方法与实施例一的制备方法相同，此处不再赘述。
相较于现有技术的TFT基板制程，本发明的阵列基板及其制备方法，将制备于金属遮光层上的第一缓冲层通过两次涂布来完成，第一次涂布后通过光罩形成与金属遮光层同层且同样膜厚的第一缓冲层图案，即无段差，然后再根据实际膜厚需求进行第二次涂布。后面膜层制作均是在平坦膜层上制作，从而不会对后面膜层厚度造成影响，较薄膜层制作时不会因表面不平而膜厚不均，可有效改善较薄膜层的厚度不均问题。本发明还可通过对成膜后的第二缓冲层进行光罩制程，形成与多晶硅层图案的形状及厚度的设计值一致的凹槽，将多晶硅层图案化于所述凹槽内。这样多晶硅层与第二缓冲层其他区域持平，无段差，避免多晶硅层凸起对后续栅绝缘层成膜不均造成影响。本发明的制备方法大大提升产品良率，有效改善TFT驼峰效应，提高面板驱动性能。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (14)

  1. 一种阵列基板，其包括：
    衬底基板；
    金属遮光层，制备于所述衬底基板上；
    第一缓冲层，制备于所述衬底基板上；
    第二缓冲层，制备于所述第一缓冲层上；以及
    多晶硅层，对应所述金属遮光层制备于所述第二缓冲层上；
    栅绝缘层，制备于所述第二缓冲层以及所述多晶硅层上；
    栅极，对应所述多晶硅层制备于所述栅绝缘层上；
    其中，所述第二缓冲层对应所述多晶硅层的位置设置有预设凹槽，所述多晶硅层位于所述凹槽内，且与所述第二缓冲层表面处于同平面，所述凹槽深度与所述多晶硅层厚度相同。
  2. 根据权利要求1所述的阵列基板，其中，所述凹槽与所述多晶硅层的形状一致。
  3. 根据权利要求1所述的阵列基板，其中，所述栅绝缘层对应所述多晶硅层的相应部分的厚度保持均一。
  4. 根据权利要求1所述的阵列基板，其中，所述第一缓冲层/所述第二缓冲层的材料至少为SiOx、SiNx中的一种或一种以上。
  5. 一种如权利要求1所述阵列基板的制备方法，其中，所述方法包括以下步骤：
    步骤S1：提供一衬底基板，在所述衬底基板上依次制备金属遮光层、第一缓冲层以及第二缓冲层；
    步骤S2：对所述第二缓冲层进行光刻制程，使所述第二缓冲层在对应所述金属遮光层的位置形成预设凹槽；
    步骤S3：在所述第二缓冲层上制备一层多晶硅膜，图案化后形成对应所述凹槽的多晶硅层，且所述多晶硅层与所述第二缓冲层表面处于同平面。
  6. 根据权利要求5所述的制备方法，其中，所述凹槽深度与所述多晶硅膜厚度相同。
  7. 根据权利要求6所述的制备方法，其中，所述凹槽形状与所述多晶硅层形状一致。
  8. 根据权利要求5所述的制备方法，其中，所述步骤S1包括：
    步骤S101：提供一衬底基板，所述衬底基板上制备有图案化的金属遮光层，在所述衬底基板上先涂布一层与所述金属遮光层厚度相同的第一缓冲层；
    步骤S102：图案化所述第一缓冲层，对所述第一缓冲层对应所述金属遮光层的相应部分进行蚀刻，使图案化的所述第一缓冲层与所述金属遮光层的厚度位于同一平面；
    步骤S103：在图案化的所述第一缓冲层以及所述金属遮光层上再涂布一层预设厚度的所述第一缓冲层；
    步骤S104：在所述第一缓冲层上涂布第二缓冲层。
  9. 根据权利要求5所述的制备方法，其中，所述方法还包括以下步骤：
    步骤S4：在所述第二缓冲层以及所述多晶硅层上制备栅绝缘层；
    步骤S5：在所述栅绝缘层上制备栅极，所述栅极正对所述多晶硅层。
  10. 根据权利要求9所述的制备方法，其中，所述栅绝缘层对应所述多晶硅层的部分膜厚保持均一。
  11. 一种阵列基板，其包括：
    衬底基板；
    金属遮光层，制备于所述衬底基板上；
    第一缓冲层，制备于所述衬底基板上；
    第二缓冲层，制备于所述第一缓冲层上；以及
    多晶硅层，对应所述金属遮光层制备于所述第二缓冲层上；
    栅绝缘层，制备于所述第二缓冲层以及所述多晶硅层上；
    栅极，对应所述多晶硅层制备于所述栅绝缘层上；
    其中，所述第二缓冲层对应所述多晶硅层的位置设置有预设凹槽，所述多晶硅层位于所述凹槽内，且与所述第二缓冲层表面处于同平面。
  12. 根据权利要求11所述的阵列基板，其中，所述凹槽与所述多晶硅层的形状一致。
  13. 根据权利要求11所述的阵列基板，其中，所述栅绝缘层对应所述多晶硅层的相应部分的厚度保持均一。
  14. 根据权利要求11所述的阵列基板，其中，所述第一缓冲层/所述第二缓冲层的材料至少为SiOx、SiNx中的一种或一种以上。
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