WO2019095493A1 - Tft阵列基板及其制作方法以及液晶显示面板 - Google Patents

Tft阵列基板及其制作方法以及液晶显示面板 Download PDF

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WO2019095493A1
WO2019095493A1 PCT/CN2017/117148 CN2017117148W WO2019095493A1 WO 2019095493 A1 WO2019095493 A1 WO 2019095493A1 CN 2017117148 W CN2017117148 W CN 2017117148W WO 2019095493 A1 WO2019095493 A1 WO 2019095493A1
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silicon
layer
gate
drain
source
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PCT/CN2017/117148
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English (en)
French (fr)
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徐洪远
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/743,976 priority Critical patent/US10877340B2/en
Publication of WO2019095493A1 publication Critical patent/WO2019095493A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2203/00—Function characteristic
    • G02F2203/01—Function characteristic transmissive

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a TFT array substrate, a method for fabricating the same, and a liquid crystal display panel.
  • LCDs liquid crystal displays
  • Flat panel displays are mainly divided into two types: active light-emitting type and non-active light-emitting type: active light-emitting flat panel displays use voltage signals to modulate the brightness and color of each light-emitting point, that is, sub-pixels, for direct display; non-active light-emitting flat panel displays themselves Instead of emitting light, the voltage signal is used to control the transmission brightness of the dedicated light source on each of the light-emitting points, that is, the sub-pixels, for display purposes.
  • the LCD is a widely used non-active light-emitting flat panel display, which includes a liquid crystal display panel and a backlight module.
  • the liquid crystal display panel further includes a thin film transistor array substrate (TFT array substrate).
  • TFT array substrate A color filter (CF) substrate and a liquid crystal layer disposed between the two substrates.
  • the LCD realizes the screen display by modulating the light field intensity of the backlight through the liquid crystal switch.
  • the TFT array substrate is provided with a plurality of thin film transistors TFT arranged in a matrix, and one TFT is correspondingly located in one sub-pixel region. In the prior art, the TFT is usually opaque and affects the aperture ratio of the pixel.
  • liquid crystal display panels are required to have a high pixel density (Pixels Per Inch, PPI).
  • PPI Pixel Per Inch
  • the ratio of the area occupied by the TFT in a single sub-pixel region to the area of a single sub-pixel is increasing; in other words, in a liquid crystal display panel with a high PPI.
  • a relatively large portion of the pixel aperture ratio is sacrificed by the TFT, resulting in a low transmittance of the high PPI liquid crystal display panel and a poor display effect.
  • An object of the present invention is to provide a TFT array substrate capable of transmitting light of a portion of a pixel region occupied by a TFT, increasing a pixel aperture ratio, improving transmittance of a high PPI liquid crystal display panel, and improving display performance of a high PPI liquid crystal display panel. .
  • Another object of the present invention is to provide a method for fabricating a TFT array substrate by using the method.
  • the TFT array substrate fabricated by the method can increase the pixel aperture ratio, improve the transmittance of the high PPI liquid crystal display panel, and improve the display effect of the high PPI liquid crystal display panel.
  • Another object of the present invention is to provide a liquid crystal display panel capable of having a high pixel aperture ratio and a superior display effect under the premise of high PPI.
  • the present invention first provides a TFT array substrate, including:
  • the gate Provided on the substrate and connected to the gate of the scan line, the gate adopts a transparent conductive material;
  • a data line disposed on the gate insulating layer and insulated from the scan line;
  • a passivation layer covering the gate insulating layer, silicon-based nanowires, data lines, source and drain electrodes;
  • a pixel electrode disposed on the passivation layer, the pixel electrode contacting the drain via a via extending through the passivation layer;
  • the gate, the plurality of silicon-based nanowires, the source and the drain constitute a TFT; and the pixel electrode covers a region occupied by the TFT.
  • the transparent conductive material used in the gate is indium tin oxide
  • the scan line includes a bottom layer in the same layer as the gate layer and a metal layer pattern stacked on the bottom layer, and the material of the bottom layer and the gate electrode The materials are the same.
  • the silicon-based nanowires have a diameter of 50 nm to 100 nm.
  • the source is comb-shaped and includes a plurality of mutually parallel source branches, each of the source branches being in cross-contact with the plurality of silicon-based nanowires;
  • the drain is comb-shaped, including a plurality of parallel lines a drain branch, each drain branch being in cross-contact with the plurality of silicon-based nanowires;
  • the source branch and the drain branch are spaced apart.
  • the width of the source branch and the drain branch are both less than 2 ⁇ m.
  • the invention also provides a method for fabricating a TFT array substrate, comprising the following steps:
  • Step S1 providing a substrate, continuously depositing a layer of a transparent conductive material and a layer of a first metal layer on the substrate;
  • Step S2 performing the transparent conductive material layer and the first metal layer using a halftone mask Patterning processing to form a scan line and a gate connecting the scan lines;
  • the gate electrode only includes a transparent conductive material layer pattern;
  • the scan line includes a bottom layer in the same layer as the gate layer and a metal layer pattern laminated on the bottom layer;
  • Step S3 covering a substrate, a scan line and a gate with a gate insulating layer
  • Step S4 forming a plurality of silicon-based nanowires on the gate insulating layer, and projections of the plurality of silicon-based nanowires fall on the gate;
  • Step S5 depositing a second metal layer on the gate insulating layer and the plurality of silicon-based nanowires and performing patterning processing to form a data line insulated from the scan line, connecting the data line and contacting a source of the plurality of silicon-based nanowires and a drain of the plurality of silicon-based nanowires;
  • the gate, the plurality of silicon-based nanowires, the source and the drain form a TFT
  • Step S6 covering a gate insulating layer, a silicon-based nanowire, a data line, a source and a drain with a passivation layer and performing a patterning process to obtain a via hole penetrating the passivation layer;
  • Step S7 depositing a transparent conductive film on the passivation layer and performing a patterning process to form a pixel electrode covering a region occupied by the TFT, the pixel electrode contacting the drain via a via hole penetrating the passivation layer pole.
  • the transparent conductive material layer is an ITO layer, and the silicon-based nanowires have a diameter of 50 nm to 100 nm.
  • the source is comb-shaped and includes a plurality of mutually parallel source branches, each of the source branches being in cross-contact with the plurality of silicon-based nanowires;
  • the drain is comb-shaped, including a plurality of parallel lines a drain branch, each drain branch being in cross-contact with the plurality of silicon-based nanowires;
  • the source branch and the drain branch are spaced apart.
  • the width of the source branch and the drain branch are both less than 2 ⁇ m.
  • the present invention also provides a liquid crystal display panel including the TFT array substrate.
  • the present invention provides a TFT array substrate in which a light-transmissive silicon-based nanowire is used as a semiconductor layer of a TFT, and a gate electrode of the TFT is formed of a transparent material, and a pixel electrode covers the TFT.
  • the light emitted by the backlight can pass through the entire TFT and the pixel electrode, so that part of the pixel area occupied by the TFT is also transparent, which can greatly increase the pixel aperture ratio, improve the transmittance of the high PPI liquid crystal display panel, and improve High PPI LCD panel display.
  • the method for fabricating a TFT array substrate according to the present invention can produce the above-described TFT array substrate with improved pixel aperture ratio.
  • the liquid crystal display panel provided by the present invention includes the above TFT array substrate, so that it can have a high pixel aperture ratio and a superior display effect under the premise of high PPI.
  • FIG. 1 is a schematic cross-sectional structural view of a TFT array substrate of the present invention
  • FIG. 2 is a schematic top plan view of a TFT array substrate of the present invention.
  • FIG. 3 is a flow chart showing a method of fabricating a TFT array substrate of the present invention.
  • FIG. 4 is a cross-sectional structural view showing the step S1 of the method for fabricating the TFT array substrate of the present invention
  • step S2 of the method for fabricating a TFT array substrate of the present invention
  • FIG. 6 is a schematic top plan view showing the step S2 of the method for fabricating the TFT array substrate of the present invention.
  • step S4 is a schematic top plan view of step S4 of the method for fabricating a TFT array substrate of the present invention.
  • FIG. 8 is a cross-sectional view showing the structure of the step S4 of the method for fabricating the TFT array substrate of the present invention.
  • step S5 is a schematic top plan view of step S5 of the method for fabricating a TFT array substrate of the present invention.
  • Fig. 10 is a cross-sectional structural view showing the step S5 of the method for fabricating the TFT array substrate of the present invention.
  • the present invention first provides a TFT array substrate, including:
  • the gate 22 is made of a transparent conductive material
  • a passivation layer 6 covering the gate insulating layer 3, the silicon-based nanowires 4, the data lines 51, the source 52 and the drain 53;
  • the gate electrode 22, the plurality of silicon-based nanowires 4, the source electrode 52, and the drain electrode 53 constitute a TFT 20; the pixel electrode 7 covers a region occupied by the TFT 20.
  • the substrate 1 is preferably a glass substrate.
  • the transparent conductive material used for the gate 22 is Indium Tin Oxide (ITO); the scan line 21 includes a bottom layer 211 in the same layer as the gate 22 and a metal layer laminated on the bottom layer 211.
  • the material of the bottom layer 211 is the same as the material of the gate electrode 22.
  • the material of the metal layer pattern 212 may be aluminum (Al), molybdenum (Mo), copper (Cu) or the like.
  • the material of the gate insulating layer 3 may be selected from silicon oxide (SiOx) or silicon nitride (SiNx).
  • the silicon-based nanowires 4 have a diameter of about 50 nm to 100 nm.
  • the silicon-based nanowire 4 has advantages of high transparency, low process temperature ( ⁇ 350 ° C), high electron mobility, and insensitivity to light, and is used as a semiconductor layer of a TFT in the present invention. Further, the extending direction of the silicon-based nanowires 4 is parallel to the extending direction of the data lines 51.
  • the material of the data line 51, the source 52 and the drain 53 may be selected from metals such as Al, Mo, and Cu.
  • the source 52 includes a plurality of source branches 521 which are parallel to each other, and each source branch 521 and the source a plurality of silicon-based nanowires 4 are in cross-contact
  • the drain electrode 53 includes a plurality of mutually parallel drain branches 531, each of the drain branches 531 being in cross-contact with the plurality of silicon-based nanowires 4; the source branches The 521 is spaced apart from the drain branch 531.
  • the source 52 and the drain 53 are made of a metal material, in order to reduce the light blocking ratio of the source 52 and the drain 53 , the widths of the source branch 521 and the drain branch 531 are designed to be less than 2 ⁇ m, as much as possible. The occlusion of the light by the source 52 and the drain 53 is reduced.
  • the material of the passivation layer 6 may be selected from SiOx or SiNx.
  • the pixel electrode 7 is made of a transparent ITO film.
  • a thick layer of an inorganic material such as a color resist layer or a flat layer may be added to the passivation layer 6.
  • the TFT array substrate is made of a light-transmissive silicon-based nanowire 4 as a semiconductor layer of the TFT 20.
  • the gate electrode 22 of the TFT 20 is made of a transparent material, and the transparent pixel electrode 7 covers the TFT.
  • the light emitted by the backlight can pass through the entire TFT 20 and the pixel electrode 7, so that the portion of the pixel occupied by the TFT 20 is also transparent.
  • the pixel aperture ratio is greatly improved, the light transmittance of the high PPI liquid crystal display panel is improved, and the display effect of the high PPI liquid crystal display panel is improved.
  • the present invention also provides a method for fabricating a TFT array substrate, comprising the following steps:
  • Step S1 as shown in Fig. 4, a substrate 1 is provided, on which a layer of transparent conductive material 2' and a layer of first metal layer 3' are successively deposited.
  • the substrate 1 is preferably a glass substrate; the transparent conductive material layer 2' is preferably an ITO layer; and the material of the first metal layer 3' may be Al, Mo, Cu or the like.
  • Step S2 as shown in FIG. 5 and FIG. 6, the transparent conductive material layer 2' and the first metal layer 3' are patterned by using a Half Tone Mask (HTM) to form a scan line 21 And a gate electrode 22 connecting the scan lines 21; the gate electrode 22 includes only a transparent conductive material layer pattern; the scan line 21 includes a bottom layer 211 in the same layer as the gate electrode 22 and is stacked on the bottom layer 211 Metal layer pattern 212.
  • HTM Half Tone Mask
  • step S2 is:
  • the photoresist 4' is exposed and developed using a halftone mask to pattern the photoresist 4' to obtain a first photoresist region 41' and a second photoresist region 42' which are spaced apart.
  • the first photoresist region 41' is corresponding to the scan line region to be formed, and the second photoresist region 42' is corresponding to the gate region to be formed, the first photoresist region 41'
  • the thickness is greater than the thickness of the second photoresist region 42';
  • the first metal layer 3' and the transparent conductive material layer 2' are wet etched;
  • first photoresist region 41' and the second photoresist region 42' are subjected to an ashing process to remove the second photoresist region 42' and reduce the thickness of the first photoresist region 41'.
  • the first photoresist sub-region 41" is peeled off, and a scan line 21 including a bottom layer 211 in the same layer as the gate electrode 22 and a metal layer pattern 212 laminated on the bottom layer 211 is obtained.
  • Step S3 referring to FIG. 8, the substrate 1, the scan line 21, and the gate 22 are covered with a gate insulating layer 3.
  • the material of the gate insulating layer 3 may be selected from SiOx or SiNx.
  • Step S4 as shown in FIG. 7 and FIG. 8, a plurality of silicon bases are formed on the gate insulating layer 3. Nanowire 4, the projection of the plurality of silicon-based nanowires 4 falls on the gate 22.
  • the silicon-based nanowires 4 have a diameter of about 50 nm to 100 nm.
  • the silicon-based nanowire 4 has the advantages of high transparency, low process temperature ( ⁇ 350 ° C), high electron mobility, and insensitivity to illumination. Further, the extending direction of the silicon-based nanowires 4 is perpendicular to the extending direction of the scanning lines 21.
  • Step S5 depositing a second metal layer on the gate insulating layer 3 and the plurality of silicon-based nanowires 4 and performing patterning treatment to form insulation from the scan line 21.
  • the intersecting data lines 51 connect the data lines 51 and contact the source 52 of the plurality of silicon-based nanowires 4 and the drains 53 of the plurality of silicon-based nanowires 4.
  • the gate electrode 22, the plurality of silicon-based nanowires 4, the source electrode 52, and the drain electrode 53 constitute a TFT 20; and the silicon-based nanowire 4 serves as a semiconductor layer of the TFT 20.
  • the material of the second metal layer in the step S5 may be selected from Al, Mo, Cu, etc.;
  • the extending direction of the data line 51 is parallel to the extending direction of the silicon-based nanowires 4;
  • both the source 52 and the drain 53 are formed in a comb shape;
  • the source 52 includes a plurality of source branches 521 that are parallel to each other, and each source branch 521 is a plurality of silicon-based nanowires 4 are in cross-contact;
  • the drain electrode 53 includes a plurality of mutually parallel drain branches 531, each of the drain branches 531 being in cross-contact with the plurality of silicon-based nanowires 4; the source branches The 521 is spaced apart from the drain branch 531.
  • the source 52 and the drain 53 are made of a metal material, in order to reduce the light blocking ratio of the source 52 and the drain 53 , the widths of the source branch 521 and the drain branch 531 are designed to be less than 2 ⁇ m, as much as possible. The occlusion of the light by the source 52 and the drain 53 is reduced.
  • Step S6 referring to FIG. 1, the gate insulating layer 3, the silicon-based nanowire 4, the data line 51, the source 52 and the drain 53 are covered with a passivation layer 6 and patterned to obtain a through process.
  • the material of the passivation layer 6 may be SiOx or SiNx.
  • Step S7 referring to FIG. 1 and FIG. 2, a transparent conductive film is deposited on the passivation layer 6 and patterned to form a pixel electrode 7 covering the area occupied by the TFT 20, and the pixel electrode 7 is penetrated through The via 61 of the passivation layer 6 contacts the drain 53.
  • the transparent conductive film is an ITO film.
  • the TFT array substrate produced by the above method for fabricating the TFT array substrate is made of a light-transmissive silicon-based nanowire 4 as a semiconductor layer of the TFT 20.
  • the gate electrode 22 of the TFT 20 is made of a transparent material, and the transparent pixel electrode 7 is covered.
  • the TFT array substrate is applied to the liquid crystal display panel, the light emitted by the backlight can pass through the entire TFT 20 and
  • the pixel electrode 7 is transparent to the portion of the pixel occupied by the TFT 20, which can greatly increase the pixel aperture ratio, improve the transmittance of the high PPI liquid crystal display panel, and improve the display effect of the high PPI liquid crystal display panel.
  • the present invention also provides a liquid crystal display panel comprising the TFT array substrate as shown in FIG. 1 and FIG. 2, so that the liquid crystal display panel of the present invention can have a high pixel aperture ratio and is superior under the premise of high PPI.
  • the display effect is also provided.
  • the TFT array substrate of the present invention uses a light-transmissive silicon-based nanowire as the semiconductor layer of the TFT, and the gate of the TFT is made of a transparent material, and the pixel electrode covers the area occupied by the TFT, then The light emitted by the backlight can pass through the entire TFT and the pixel electrode, so that part of the pixel area occupied by the TFT is also transparent, which can greatly increase the pixel aperture ratio, improve the transmittance of the high PPI liquid crystal display panel, and improve the high PPI liquid crystal display. The display effect of the panel.
  • the TFT array substrate having the above-described pixel aperture ratio can be produced. Since the liquid crystal display panel of the present invention includes the above TFT array substrate, it can have a high pixel aperture ratio and a superior display effect under the premise of high PPI.

Abstract

一种TFT阵列基板及其制作方法以及液晶显示面板。该TFT阵列基板以可透光的硅基纳米线(4)来作为TFT(20)的半导体层，设置TFT(20)的栅极(22)由透明材料构成，像素电极(7)遮盖住TFT(20)所占据的区域，背光源发出的光线能够透过整个TFT(20)与像素电极(7)，TFT(20)所占据的那部分像素区域亦透光，能够大幅提高像素开口率，提升高PPI液晶显示面板的透光率，改善高PPI液晶显示面板的显示效果。

Description

TFT阵列基板及其制作方法以及液晶显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT阵列基板及其制作方法以及液晶显示面板。
背景技术
在显示技术领域，以液晶显示器(Liquid Crystal Display，LCD)为代表的平板显示器已经逐步取代了CRT显示器。
平板显示器主要分为主动发光型和非主动发光型两大类：主动发光型平板显示器是利用电压信号来调制各发光点即子像素的亮度和颜色，进行直接显示；非主动发光型平板显示器本身不发光，而是利用电压信号控制专用光源在每个发光点即子像素上的透过亮度，达到显示的目的。
LCD便是一种被广泛应用地非主动发光型平板显示器，其包括液晶显示面板及背光模组；液晶显示面板又包括薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，简称TFT阵列基板)、一彩膜(Color Filter，CF)基板以及一配置于两基板间的液晶层(Liquid Crystal Layer)。LCD通过液晶开关调制背光源的光场强度来实现画面显示。其中，TFT阵列基板上设置有呈矩阵式排布的多个薄膜晶体管TFT，一个TFT对应位于一个子像素区域内。在现有技术中，TFT通常是不透明的，会影响到像素的开口率。
随着增强现实(Augmented Reality，AR)、虚拟现实(Virtual Reality，VR)等新兴产品的开发和流行，要求液晶显示面板具有超高的像素密度(Pixels Per Inch，PPI)。对于液晶显示面板来说，随着PPI的逐步增高，TFT在单个子像素区域内所占据的面积相对于单个子像素面积的比例越来越大；换句话说，在高PPI的液晶显示面板中，相当大一部分的像素开口率会被TFT牺牲掉，造成高PPI液晶显示面板的透光率较低，显示效果较差。
发明内容
本发明的目的在于提供一种TFT阵列基板，能够使TFT所占据的那部分像素区域透光，提高像素开口率，提升高PPI液晶显示面板的透光率，改善高PPI液晶显示面板的显示效果。
本发明的另一目的在于提供一种TFT阵列基板的制作方法，通过该方 法制作的TFT阵列基板能够提高像素开口率，提升高PPI液晶显示面板的透光率，改善高PPI液晶显示面板的显示效果。
本发明的目的还在于提供一种液晶显示面板，能够在高PPI的前提下，具有较高的像素开口率及较优的显示效果。
为实现上述目的，本发明首先提供一种TFT阵列基板，包括：
基板；
设在所述基板上的扫描线；
设在所述基板上并连接所述扫描线的栅极，所述栅极采用透明导电材料；
覆盖所述基板、扫描线与栅极的栅极绝缘层；
设在栅极绝缘层上的多条硅基纳米线，所述多条硅基纳米线的投影落在所述栅极上；
设在所述栅极绝缘层上并与扫描线绝缘交叉的数据线；
设在所述栅极绝缘层上连接所述数据线并接触所述多条硅基纳米线的源极；
设在所述栅极绝缘层上并接触所述多条硅基纳米线的漏极；
覆盖所述栅极绝缘层、硅基纳米线、数据线、源极与漏极的钝化层；
以及设在所述钝化层上的像素电极，所述像素电极经由贯穿所述钝化层的过孔接触所述漏极；
所述栅极、多条硅基纳米线、源极及漏极构成TFT；所述像素电极遮盖住所述TFT所占据的区域。
所述栅极采用的透明导电材料为氧化铟锡，所述扫描线包括与所述栅极同层的底层及层叠在所述底层上的金属层图案，所述底层的材料与所述栅极的材料相同。
所述硅基纳米线的直径为50nm～100nm。
所述源极呈梳齿状，包括数条相互平行的源极分支，每一源极分支与所述多条硅基纳米线交叉接触；所述漏极呈梳齿状，包括数条相互平行的漏极分支，每一漏极分支与所述多条硅基纳米线交叉接触；
所述源极分支与漏极分支间隔排布。
所述源极分支与漏极分支的宽度均小于2μm。
本发明也提供一种TFT阵列基板的制作方法，包括以下步骤：
步骤S1、提供基板，在所述基板上连续沉积一层透明导电材料层与一层第一金属层；
步骤S2、使用半色调掩膜板对所述透明导电材料层与第一金属层进行 图案化处理，形成扫描线及连接所述扫描线的栅极；
所述栅极仅包括透明导电材料层图案；所述扫描线包括与所述栅极同层的底层及层叠在所述底层上的金属层图案；
步骤S3、在所述基板、扫描线及栅极上覆盖一层栅极绝缘层；
步骤S4、在所述栅极绝缘层上制作出多条硅基纳米线，所述多条硅基纳米线的投影落在所述栅极上；
步骤S5、在所述栅极绝缘层与多条硅基纳米线上沉积一层第二金属层并进行图案化处理，形成与所述扫描线绝缘交叉的数据线、连接所述数据线并接触所述多条硅基纳米线的源极及接触所述多条硅基纳米线的漏极；
所述栅极、多条硅基纳米线、源极及漏极构成TFT；
步骤S6、在所述栅极绝缘层、硅基纳米线、数据线、源极与漏极上覆盖一层钝化层并进行图案化处理，得到贯穿所述钝化层的过孔；
步骤S7、在所述钝化层上沉积透明导电薄膜并进行图案化处理，形成遮盖住所述TFT所占据区域的像素电极，所述像素电极经由贯穿所述钝化层的过孔接触所述漏极。
所述透明导电材料层为ITO层，所述硅基纳米线的直径为50nm～100nm。
所述源极呈梳齿状，包括数条相互平行的源极分支，每一源极分支与所述多条硅基纳米线交叉接触；所述漏极呈梳齿状，包括数条相互平行的漏极分支，每一漏极分支与所述多条硅基纳米线交叉接触；
所述源极分支与漏极分支间隔排布。
所述源极分支与漏极分支的宽度均小于2μm。
本发明还提供一种液晶显示面板，包括所述TFT阵列基板。
本发明的有益效果：本发明提供的一种TFT阵列基板，以可透光的硅基纳米线来作为TFT的半导体层，设置TFT的栅极由透明材料构成，像素电极遮盖住所述TFT所占据的区域，那么背光源发出的光线能够透过整个TFT与像素电极，所以TFT所占据的那部分像素区域亦透光，能够大幅提高像素开口率，提升高PPI液晶显示面板的透光率，改善高PPI液晶显示面板的显示效果。本发明提供的TFT阵列基板的制作方法能够制作出上述提高像素开口率的TFT阵列基板。本发明提供的液晶显示面板，包括上述TFT阵列基板，所以能够在高PPI的前提下，具有较高的像素开口率及较优的显示效果。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的TFT阵列基板的剖面结构示意图；
图2为本发明的TFT阵列基板的俯视结构示意图；
图3为本发明的TFT阵列基板的制作方法的流程图；
图4为本发明的TFT阵列基板的制作方法的步骤S1的剖面结构示意图；
图5为本发明的TFT阵列基板的制作方法的步骤S2的具体实施过程的剖面结构示意图；
图6为本发明的TFT阵列基板的制作方法的步骤S2完成之后的俯视结构示意图；
图7为本发明的TFT阵列基板的制作方法的步骤S4的俯视结构示意图；
图8为本发明的TFT阵列基板的制作方法的步骤S4的剖面视结构示意图；
图9为本发明的TFT阵列基板的制作方法的步骤S5的俯视结构示意图；
图10为本发明的TFT阵列基板的制作方法的步骤S5的剖面视结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请同时参阅图1与图2，结合图6、图7与图9，本发明首先提供一种TFT阵列基板，包括：
基板1；
设在所述基板1上的扫描线21；
设在所述基板1上并连接所述扫描线21的栅极22，所述栅极22采用透明导电材料；
覆盖所述基板1、扫描线21与栅极22的栅极绝缘层3；
设在栅极绝缘层3上的多条硅基纳米线4，所述多条硅基纳米线4的投影落在所述栅极22上；
设在所述栅极绝缘层3上并与扫描线21绝缘交叉的数据线51；
设在所述栅极绝缘层3上连接所述数据线51并接触所述多条硅基纳米线4的源极52；
设在所述栅极绝缘层3上并接触所述多条硅基纳米线4的漏极53；
覆盖所述栅极绝缘层3、硅基纳米线4、数据线51、源极52与漏极53的钝化层6；
以及设在所述钝化层6上的像素电极7，所述像素电极7经由贯穿所述钝化层6的过孔61接触所述漏极53；
所述栅极22、多条硅基纳米线4、源极52及漏极53构成TFT 20；所述像素电极7遮盖住所述TFT 20所占据的区域。
具体地：
所述基板1优选玻璃基板。
所述栅极22采用的透明导电材料为氧化铟锡(Indium Tin Oxide，ITO)；所述扫描线21包括与所述栅极22同层的底层211及层叠在所述底层211上的金属层图案212，所述底层211的材料与所述栅极22的材料相同，进一步地，所述金属层图案212的材料可选用铝(Al)、钼(Mo)、铜(Cu)等。
所述栅极绝缘层3的材料可选用氧化硅(SiOx)或氮化硅(SiNx)。
所述硅基纳米线4的直径约为50nm～100nm。所述硅基纳米线4具有透明度高、制程温度较低(＜350℃)、电子迁移率高、对光照不敏感等优势，在本发明中用作TFT的半导体层。进一步地，所述硅基纳米线4的延伸方向平行于数据线51的延伸方向。
所述数据线51、源极52与漏极53的材料可选用Al、Mo、Cu等金属。为了缩小TFT 20的沟道长度，优选将源极52与漏极53均设计成梳齿状；所述源极52包括数条相互平行的源极分支521，每一源极分支521与所述多条硅基纳米线4交叉接触；所述漏极53包括数条相互平行的漏极分支531，每一漏极分支531与所述多条硅基纳米线4交叉接触；所述源极分支521与漏极分支531间隔排布。进一步地，由于源极52与漏极53采用金属材料，为了减小源极52与漏极53的遮光率，设计所述源极分支521与漏极分支531的宽度均小于2μm，尽可能地减少源极52与漏极53对光线的遮挡。
所述钝化层6的材料可选用SiOx或SiNx。
所述像素电极7以透明的ITO薄膜为材料。
另外，为了减小像素电极7与源极52、漏极53之间的寄生电容，还可在钝化层6上增加一层较厚的无机材料层，如色阻层或平坦层等。
所述TFT阵列基板以可透光的硅基纳米线4来作为TFT 20的半导体层，设置TFT 20的栅极22由透明材料构成，透明的像素电极7遮盖住所述TFT 20所占据的区域，那么将该TFT阵列基板应用于液晶显示面板后，背光源发出的光线能够透过整个TFT 20与像素电极7，所以TFT 20所占据的那部分像素区域亦透光，能够大幅提高像素开口率，提升高PPI液晶显示面板的透光率，改善高PPI液晶显示面板的显示效果。
请参阅图3，本发明也提供一种TFT阵列基板的制作方法，包括如下步骤：
步骤S1、如图4所示，提供基板1，在所述基板1上连续沉积一层透明导电材料层2’与一层第一金属层3’。
具体地：所述基板1优选玻璃基板；所述透明导电材料层2’优选为ITO层；所述第一金属层3’的材料可选用Al、Mo、Cu等。
步骤S2、如图5及图6所示，使用半色调掩膜板(Half Tone Mask，HTM)对所述透明导电材料层2’与第一金属层3’进行图案化处理，形成扫描线21及连接所述扫描线21的栅极22；所述栅极22仅包括透明导电材料层图案；所述扫描线21包括与所述栅极22同层的底层211及层叠在所述底层211上的金属层图案212。
具体地，该步骤S2的具体实施过程为：
首先在第一金属层3’上涂布光阻4’；
再使用半色调掩膜板对光阻4’进行曝光、显影，以对所述光阻4’进行图案化处理，得到间隔设置的第一光阻区域41’和第二光阻区域42’，所述第一光阻区域41’对应位于欲形成的扫描线区域之上，所述第二光阻区域42’对应位于欲形成的栅极区域之上，所述第一光阻区域41’的厚度大于第二光阻区域42’的厚度；
接下来对所述第一金属层3’与透明导电材料层2’进行湿蚀刻；
之后对第一光阻区域41’和第二光阻区域42’进行灰化(Ash)处理，以将第二光阻区域42’去除及将第一光阻区域41’的厚度减薄，得到第一光阻子区域41”；
接着，以第一光阻子区域41”为遮挡，再次进行湿蚀刻，得到包括透明导电材料层图案的栅极22；
最后剥离掉所述第一光阻子区域41”，得到包括与所述栅极22同层的底层211及层叠在所述底层211上的金属层图案212的扫描线21。
步骤S3、请参阅图8，在所述基板1、扫描线21及栅极22上覆盖一层栅极绝缘层3。
具体地，所述栅极绝缘层3的材料可选用SiOx或SiNx。
步骤S4、如图7与图8所示，在所述栅极绝缘层3上制作出多条硅基 纳米线4，所述多条硅基纳米线4的投影落在所述栅极22上。
具体地，所述硅基纳米线4的直径约为50nm～100nm。所述硅基纳米线4具有透明度高、制程温度较低(＜350℃)、电子迁移率高、对光照不敏感等优势。进一步地，所述硅基纳米线4的延伸方向垂直于扫描线21的延伸方向。
步骤S5、如图9与图10所示，在所述栅极绝缘层3与多条硅基纳米线4上沉积一层第二金属层并进行图案化处理，形成与所述扫描线21绝缘交叉的数据线51、连接所述数据线51并接触所述多条硅基纳米线4的源极52及接触所述多条硅基纳米线4的漏极53。
所述栅极22、多条硅基纳米线4、源极52及漏极53构成TFT 20；所述硅基纳米线4用作TFT 20的半导体层。
具体地：
该步骤S5中的第二金属层的材料可选用Al、Mo、Cu等；
所述数据线51的延伸方向与硅基纳米线4的延伸方向平行；
为了缩小TFT 20的沟道长度，优选将源极52与漏极53均制作成梳齿状；所述源极52包括数条相互平行的源极分支521，每一源极分支521与所述多条硅基纳米线4交叉接触；所述漏极53包括数条相互平行的漏极分支531，每一漏极分支531与所述多条硅基纳米线4交叉接触；所述源极分支521与漏极分支531间隔排布。进一步地，由于源极52与漏极53采用金属材料，为了减小源极52与漏极53的遮光率，设计所述源极分支521与漏极分支531的宽度均小于2μm，尽可能地减少源极52与漏极53对光线的遮挡。
步骤S6、请参阅图1，在所述栅极绝缘层3、硅基纳米线4、数据线51、源极52与漏极53上覆盖一层钝化层6并进行图案化处理，得到贯穿所述钝化层6的过孔61。
具体地，所述钝化层6的材料可选用SiOx或SiNx。
步骤S7、请参阅图1与图2，在所述钝化层6上沉积透明导电薄膜并进行图案化处理，形成遮盖住所述TFT 20所占据区域的像素电极7，所述像素电极7经由贯穿所述钝化层6的过孔61接触所述漏极53。
具体地，所述透明导电薄膜为ITO薄膜。
经上述TFT阵列基板的制作方法制得的TFT阵列基板以可透光的硅基纳米线4来作为TFT 20的半导体层，设置TFT 20的栅极22由透明材料构成，透明的像素电极7遮盖住所述TFT 20所占据的区域，那么将该TFT阵列基板应用于液晶显示面板后，背光源发出的光线能够透过整个TFT 20与 像素电极7，所以TFT 20所占据的那部分像素区域亦透光，能够大幅提高像素开口率，提升高PPI液晶显示面板的透光率，改善高PPI液晶显示面板的显示效果。
本发明还提供一种液晶显示面板，包括上述如图1与图2所示的TFT阵列基板，所以本发明的液晶显示面板能够在高PPI的前提下，具有较高的像素开口率及较优的显示效果。
综上所述，本发明的TFT阵列基板，以可透光的硅基纳米线来作为TFT的半导体层，设置TFT的栅极由透明材料构成，像素电极遮盖住所述TFT所占据的区域，那么背光源发出的光线能够透过整个TFT与像素电极，所以TFT所占据的那部分像素区域亦透光，能够大幅提高像素开口率，提升高PPI液晶显示面板的透光率，改善高PPI液晶显示面板的显示效果。本发明的TFT阵列基板的制作方法能够制作出上述提高像素开口率的TFT阵列基板。本发明的液晶显示面板，包括上述TFT阵列基板，所以能够在高PPI的前提下，具有较高的像素开口率及较优的显示效果。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明的权利要求的保护范围。

Claims (10)

  1. 一种TFT阵列基板，包括：
    基板；
    设在所述基板上的扫描线；
    设在所述基板上并连接所述扫描线的栅极，所述栅极采用透明导电材料；
    覆盖所述基板、扫描线与栅极的栅极绝缘层；
    设在栅极绝缘层上的多条硅基纳米线，所述多条硅基纳米线的投影落在所述栅极上；
    设在所述栅极绝缘层上并与扫描线绝缘交叉的数据线；
    设在所述栅极绝缘层上连接所述数据线并接触所述多条硅基纳米线的源极；
    设在所述栅极绝缘层上并接触所述多条硅基纳米线的漏极；
    覆盖所述栅极绝缘层、硅基纳米线、数据线、源极与漏极的钝化层；
    以及设在所述钝化层上的像素电极，所述像素电极经由贯穿所述钝化层的过孔接触所述漏极；
    所述栅极、多条硅基纳米线、源极及漏极构成TFT；所述像素电极遮盖住所述TFT所占据的区域。
  2. 如权利要求1所述的TFT阵列基板，其中，所述栅极采用的透明导电材料为氧化铟锡，所述扫描线包括与所述栅极同层的底层及层叠在所述底层上的金属层图案，所述底层的材料与所述栅极的材料相同。
  3. 如权利要求1所述的TFT阵列基板，其中，所述硅基纳米线的直径为50nm～100nm。
  4. 如权利要求1所述的TFT阵列基板，其中，所述源极呈梳齿状，包括数条相互平行的源极分支，每一源极分支与所述多条硅基纳米线交叉接触；所述漏极呈梳齿状，包括数条相互平行的漏极分支，每一漏极分支与所述多条硅基纳米线交叉接触；
    所述源极分支与漏极分支间隔排布。
  5. 如权利要求4所述的TFT阵列基板，其中，所述源极分支与漏极分支的宽度均小于2μm。
  6. 一种TFT阵列基板的制作方法，包括以下步骤：
    步骤S1、提供基板，在所述基板上连续沉积一层透明导电材料层与一 层第一金属层；
    步骤S2、使用半色调掩膜板对所述透明导电材料层与第一金属层进行图案化处理，形成扫描线及连接所述扫描线的栅极；
    所述栅极仅包括透明导电材料层图案；所述扫描线包括与所述栅极同层的底层及层叠在所述底层上的金属层图案；
    步骤S3、在所述基板、扫描线及栅极上覆盖一层栅极绝缘层；
    步骤S4、在所述栅极绝缘层上制作出多条硅基纳米线，所述多条硅基纳米线的投影落在所述栅极上；
    步骤S5、在所述栅极绝缘层与多条硅基纳米线上沉积一层第二金属层并进行图案化处理，形成与所述扫描线绝缘交叉的数据线、连接所述数据线并接触所述多条硅基纳米线的源极及接触所述多条硅基纳米线的漏极；
    所述栅极、多条硅基纳米线、源极及漏极构成TFT；
    步骤S6、在所述栅极绝缘层、硅基纳米线、数据线、源极与漏极上覆盖一层钝化层并进行图案化处理，得到贯穿所述钝化层的过孔；
    步骤S7、在所述钝化层上沉积透明导电薄膜并进行图案化处理，形成遮盖住所述TFT所占据区域的像素电极，所述像素电极经由贯穿所述钝化层的过孔接触所述漏极。
  7. 如权利要求6所述的TFT阵列基板的制作方法，其中，所述透明导电材料层为氧化铟锡层，所述硅基纳米线的直径为50nm～100nm。
  8. 如权利要求6所述的TFT阵列基板的制作方法，其中，所述源极呈梳齿状，包括数条相互平行的源极分支，每一源极分支与所述多条硅基纳米线交叉接触；所述漏极呈梳齿状，包括数条相互平行的漏极分支，每一漏极分支与所述多条硅基纳米线交叉接触；
    所述源极分支与漏极分支间隔排布。
  9. 如权利要求8所述的TFT阵列基板的制作方法，其中，所述源极分支与漏极分支的宽度均小于2μm。
  10. 一种液晶显示面板，包括如权利要求1所述的TFT阵列基板。
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