WO2019012678A1 - 電子モジュール - Google Patents

電子モジュール Download PDF

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Publication number
WO2019012678A1
WO2019012678A1 PCT/JP2017/025641 JP2017025641W WO2019012678A1 WO 2019012678 A1 WO2019012678 A1 WO 2019012678A1 JP 2017025641 W JP2017025641 W JP 2017025641W WO 2019012678 A1 WO2019012678 A1 WO 2019012678A1
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WO
WIPO (PCT)
Prior art keywords
direction extending
extending portion
surface direction
terminal
substrate
Prior art date
Application number
PCT/JP2017/025641
Other languages
English (en)
French (fr)
Inventor
康亮 池田
理 松嵜
Original Assignee
新電元工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 新電元工業株式会社 filed Critical 新電元工業株式会社
Priority to JP2018530624A priority Critical patent/JP6517442B1/ja
Priority to CN201780012758.9A priority patent/CN109511279B/zh
Priority to US16/078,602 priority patent/US11658109B2/en
Priority to PCT/JP2017/025641 priority patent/WO2019012678A1/ja
Priority to NL2021291A priority patent/NL2021291B1/en
Priority to TW107124158A priority patent/TWI704858B/zh
Publication of WO2019012678A1 publication Critical patent/WO2019012678A1/ja

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Definitions

  • the present invention relates to an electronic module having a terminal portion.
  • An electronic module in which a plurality of electronic elements are provided in a sealing resin is conventionally known (see, for example, JP-A-2014-45157). It is desirable to miniaturize such an electronic module.
  • the number of electronic elements increases, and therefore, it is necessary to increase the number of terminals for connection with an external device.
  • the terminal is provided only on either the substrate on which the first electronic element is provided or the substrate on which the second electronic element is provided, a space for disposing the terminal is required, and the size in the plane direction increases.
  • the present invention provides an electronic module that can be prevented from becoming large in the plane direction.
  • the electronic module according to the invention is A first substrate, A first electronic element provided on one side of the first substrate; A second electronic device provided on one side of the first electronic device; A second substrate provided on one side of the second electronic device; A first terminal portion provided on the first substrate side and electrically connected to the first electronic element; A second terminal portion provided on the second substrate side and electrically connected to the second electronic element; Equipped with The first terminal portion is provided at a first surface direction extending portion extending along the surface direction of the first substrate and an end portion of the first surface direction extending portion, and extends to one side or the other side A first normal direction extending portion, The second terminal portion is provided at a second surface direction extending portion extending along the surface direction of the second substrate, and at an end portion of the second surface direction extending portion, and extends to one side or the other side A second normal direction extending portion, The second surface direction extending portion may be provided on one side of the first surface direction extending portion, and the first surface direction extending portion and the second surface direction extending portion may overlap in the surface direction.
  • the second normal direction extension portion extends to one side
  • the first surface direction extending portion extends outward to the peripheral edge of the second surface direction extending portion
  • the first normal direction extending portion may extend to one side further outward in the peripheral edge than the second normal direction extending portion.
  • One end of the first normal direction extending portion and one end of the second normal direction extending portion may extend to substantially the same position.
  • the first normal direction extending portion extends to the other side
  • the second normal direction extension may extend to one side
  • a plurality of first terminals are provided, The second terminal portion is provided in the same number as the first terminal portion, A second surface direction extending portion is provided on one side of each first surface direction extending portion, The first surface direction extending portion may be provided on the other side of each second surface direction extending portion.
  • the first surface direction extending portion and the second surface direction extending portion may substantially completely overlap in the width direction of the terminal portion.
  • the first terminal portion is provided on the first substrate side
  • the second terminal portion is provided on the second substrate side
  • the second surface direction extending portion is provided on one side of the first surface direction extending portion.
  • FIG. 1 is a longitudinal sectional view of an electronic module that can be used in the first embodiment of the present invention.
  • FIG. 2 is a plan view showing a first connection body and the like that can be used in the first embodiment of the present invention.
  • FIG. 3 is a longitudinal sectional view of an electronic module showing another example that can be used in the first embodiment of the present invention.
  • FIG. 4 (a) is a plan view showing the configuration on the first substrate side which can be used in the first embodiment of the present invention, and FIG. 4 (b) is a first embodiment of the present invention. It is the top view which showed the structure by the side of the 2nd board
  • FIG. 5 (a) is a plan view of an electronic module that can be used in the first embodiment of the present invention, and FIG.
  • FIG. 5 (b) is a cross-sectional view taken along line BB in FIG. 5 (a).
  • FIG. 6 (a) is a cross-sectional view corresponding to FIG. 5 (b) of an electronic module which can be used in the second embodiment of the present invention
  • FIG. 6 (b) is a second embodiment of the present invention
  • 6 (a) is a cross-sectional view corresponding to FIG. 6 (a) of another electronic module that can be used in the embodiment
  • FIG. 6 (c) is a further electronic module that may be used in the second embodiment of the present invention.
  • FIG. 7 (a) is a plan view of an electronic module that can be used in the third embodiment of the present invention
  • FIG. 7 (b) is an electronic module that may be used in the third embodiment of the present invention
  • FIG. 8 is a longitudinal sectional view of an electronic module that can be used in the fourth embodiment of the present invention.
  • FIG. 9 is a longitudinal sectional view of an electronic module that can be used in the fifth embodiment of the present invention.
  • FIG. 10 is a front view (viewed along a second direction) of an electronic module that can be used in the fifth embodiment of the present invention.
  • the first normal direction extending portion and the second normal direction extending portion are shown by broken lines
  • the first surface direction extending portion and the second surface direction extending portion are shown by solid lines.
  • FIG. 11 (a) is a front view of an electronic module that can be used in the sixth embodiment of the present invention
  • FIG. 11 (b) is another front view that can be used in the sixth embodiment of the present invention. It is a front view of an electronic module.
  • the first normal direction extending portion and the second normal direction extending portion are shown by broken lines, and the first surface direction extending portion and the second surface direction extending portion are shown by solid lines.
  • FIG. 12 is a plan view showing a first connecting body that can be used in the seventh embodiment of the present invention.
  • FIG. 13 is a longitudinal sectional view for showing a second connection body that can be used in the eighth embodiment of the present invention.
  • FIG. 14 is a longitudinal sectional view of an electronic module that can be used in the ninth embodiment of the present invention.
  • first direction the horizontal direction
  • second direction the front and back direction of the paper surface
  • third direction the front and back direction of the paper surface
  • the electronic module of the present embodiment may have a first electronic unit and a second electronic unit.
  • the first electronic unit is provided on one side of the first substrate 11, the plurality of first conductor layers 12 provided on one side of the first substrate 11, and the first conductor layer 12.
  • the first electronic element 13 may be a switching element or a control element.
  • the first electronic element 13 may be a MOSFET, an IGBT or the like.
  • Each of the first electronic element 13 and the second electronic element 23 described later may be composed of a semiconductor element, and the semiconductor material may be silicon, silicon carbide, gallium nitride or the like.
  • the other surface of the first electronic element 13 may be connected to the first conductor layer 12 via a conductive adhesive (not shown) such as solder.
  • a first connector 60 may be provided on one side of the first electronic element 13.
  • the first connection body 60 may be connected to the surface on one side of the first electronic element 13 via a conductive adhesive such as solder.
  • a second electronic unit may be provided on one side of the first connector 60.
  • the second electronic unit may have a second electronic element 23 provided on one side of the first connector 60.
  • the second electronic unit may have a second substrate 21 and a second conductor layer 22 provided on the other side of the second substrate 21.
  • a second connecting body 70 may be provided on the other side of the second conductor layer 22.
  • the second connection body 70 may be connected to the one surface of the second electronic element 23 and the other surface of the second conductor layer 22 via a conductive adhesive such as solder.
  • the second electronic element 23 may be a switching element or a control element.
  • the second electronic element 23 may be a MOSFET, an IGBT, or the like.
  • the first connection body 60 may have a first head portion 61 and a first column portion 62 extending from the first head portion 61 to the other side.
  • the second connection body 70 may have a second head portion 71 and a second pillar portion 72 extending from the second head portion 71 to the other side.
  • the first connector 60 may have a substantially T-shaped cross section, and the second connector 70 may have a substantially T-shaped cross section.
  • a ceramic substrate, an insulating resin layer or the like can be adopted as the first substrate 11 and the second substrate 21.
  • a material having Ag or Cu as a main component can also be used.
  • a metal such as Cu can be used as a material of the first connection body 60 and the second connection body 70.
  • a metal substrate subjected to circuit patterning can be used as the substrates 11 and 21. In this case, the substrates 11 and 21 also serve as the conductor layers 12 and 22, respectively.
  • the electronic module is a sealing resin for sealing the first electronic element 13, the second electronic element 23, the first connector 60, the second connector 70, the first conductor layer 12, the second conductor layer 22, etc. And the like may be provided.
  • the first conductor layer 12 may be connected to the terminal portion 100, and the tip end side of the terminal portion 100 may be exposed to the outside of the sealing portion 90 to be connectable to an external device such as a control board.
  • the terminal unit 100 may have a first terminal unit 110 electrically connected to the first electronic element 13 and a second terminal unit 120 electrically connected to the second electronic element 23.
  • the first terminal portion 110 is provided at an end of a first surface direction extending portion 114 extending along the surface direction of the first substrate 11 and an end portion of the first surface direction extending portion 114, and extends to one side And a normal direction extending portion 113.
  • the second terminal portion 120 is provided at an end of a second surface direction extending portion 124 extending along the surface direction of the second substrate 21 and an end portion of the second surface direction extending portion 124, and extends to one side It may have two normal direction extension parts 123. At least a portion of the second in-plane extending portion 124 may be positioned on one side of the first in-plane extending portion 114 (see FIG. 5).
  • the first surface direction extending portion 114 may extend further outward in the peripheral direction than the second surface direction extending portion 124.
  • the first normal direction extending portion 113 may extend outward on the peripheral edge of the second normal direction extending portion 123 to one side.
  • first normal direction extending portion 113 and one end of the second normal direction extending portion 123 may extend to substantially the same position.
  • the term “extends to substantially the same position” refers to a normal direction extending portion having a shorter length of the first normal direction extending portion 113 and the second normal direction extending portion 123 between the two. In the above-mentioned, it means that the difference within 5% of the whole length of the second normal direction extension part 123) does not exist.
  • a plurality of first terminal portions 110 may be provided.
  • a plurality of second terminal portions 120 may be provided.
  • the number of first terminal portions 110 and the number of second terminal portions 120 may be the same.
  • second surface direction extending portions 124 are provided on one side of each first surface direction extending portion 114. The two may overlap in the plane direction.
  • the number of first terminal portions 110 and the number of second terminal portions 120 are the same, and in planar view, the first surface direction extending portion 114
  • the present invention is not limited to such an aspect, and as in the second embodiment described later, only a part of the first surface direction extending portion 114 and the second surface direction extending portion 124 in a plan view You may employ
  • the first terminal portion 110 includes a first terminal base end portion 111 connected to the first conductor layer 12, the first surface direction extending portion 114 described above, and a first terminal base end portion. It may be provided between 111 and the 1st surface direction extension part 114, and may have the 1st bent part 112 bent to the other side by the 1st terminal base end part 111 side.
  • the first terminal base end 111 may be connected to the surface on one side of the first conductor layer 12 via a conductive adhesive.
  • the second terminal portion 120 extends from the second terminal base end portion 121 connected to the second conductor layer 22, the second surface direction extending portion 124 described above, the second terminal base end portion 121, and the second surface direction. And a second bent portion 122 provided between the recessed portion 124 and bent to one side on the second terminal base end portion 121 side.
  • the second terminal base end 121 may be connected to the other surface of the second conductor layer 22 via a conductive adhesive.
  • the first surface direction extending portion 114 and the second surface direction extending portion 124 may be separated by a distance equal to or greater than a threshold in the first direction on the outer side of the sealing portion 90.
  • the threshold may be a numerical value determined based on the safety standard. For example, when the electronic device uses a voltage of 600 V, the first surface direction extending portion 114 and the second surface direction extending portion 124 need to be separated by a distance of 3.6 mm or more. In this case, the threshold is 3.6 mm.
  • a first groove portion 64 may be provided on the surface on one side of the first head portion 61.
  • the first groove portion 64 is provided outward of the peripheral edge of the first column portion 62 in a plan view (surface direction), but may be provided at a part of the peripheral edge outward. It may be provided on the entire outer periphery.
  • a conductive adhesive such as a solder may be provided on the surface on one side of the first head portion 61 and inside the periphery of the first groove portion 64, and the second electronic element 23 may be provided via the conductive adhesive. May be provided.
  • a connector 85 connected to a terminal such as a second gate terminal 23 g described later of the second electronic element 23 may be used.
  • the present invention is not limited to such an aspect, and a third connection body 80 as shown in FIG. 3 may be used.
  • the third connector 80 may have a third head 81 and a third pillar 82 extending from the third head 81 to the other side.
  • the third connection body 80 may be connected to the other surface of the second conductor layer 22 and the surface on one side of the second electronic element 23 via a conductive adhesive such as solder.
  • the first electronic device 13 may be exposed outward from the first head portion 61.
  • the first electronic element 13 is a switching element such as a MOSFET
  • the first gate terminal 13g or the like may be provided on the surface on one side.
  • the second electronic element 23 is a switching element such as a MOSFET
  • the second gate terminal 23g or the like may be provided on the surface on one side.
  • the first electronic device 13 shown in FIG. 2 has a first gate terminal 13g and a first source terminal 13s on one side
  • the second electronic device 23 has a second gate terminal 23g and a second on the one side. It has two source terminals 23s.
  • the second connector 70 is connected to the second source terminal 23s of the second electronic element 23 via the conductive adhesive, and the connector 85 is conductively bonded to the second gate terminal 23g of the second electronic element 23. It may be connected via an agent.
  • the first connection body 60 may connect the first source terminal 13s of the first electronic element 13 and the second drain terminal provided on the other side of the second electronic element 23 through the conductive adhesive. .
  • the first drain terminal provided on the other side of the first electronic element 13 may be connected to the first conductor layer 12 via a conductive adhesive.
  • the first gate terminal 13g of the first electronic element 13 is connected to the connector 95 (see FIG. 1) via the conductive adhesive, and the connector 95 is connected to the first conductor layer 12 via the conductive adhesive. It may be done.
  • the second electronic element 23 mounted on the first connecting member 60 is used as a control element with low heat generation, It is also conceivable to make the electronic element 13 a switching element. Conversely, it is also conceivable to use the second electronic element 23 mounted on the first connection body 60 as a switching element and the first electronic element 13 as a control element with low heat generation.
  • the bonding between the terminal portion 100 and the conductor layers 12 and 22 may be performed not only by using a conductive adhesive such as solder, but also by laser welding or ultrasonic bonding.
  • the second electronic element 23 is provided on one side of the first electronic element 13 in order to miniaturize the electronic module, the number of electronic elements 13 and 23 is increased, and as a result, the number of terminal portions 100 is increased. Increase.
  • the first terminal portion 110 is provided on the first substrate 11 side
  • the second terminal portion 120 is provided on the second substrate 21 side
  • the second surface direction extending portion is provided on one side of the first surface direction extending portion 114.
  • the terminal portion 100 can be disposed using both the first substrate 11 and the second substrate 21. As a result, the size in the plane direction can be obtained. Is beneficial in that it can be reduced.
  • the number of terminal portions 100 for transmitting signals from the electronic devices 13 and 23 increases, and the size of the electronic module in the plane direction May become large.
  • a member for electrically connecting the first conductor layer 12 and the second conductor layer 22 is also required. become.
  • providing the first terminal portion 110 on the first substrate 11 side and providing the second terminal portion 120 on the second substrate 21 side is advantageous in that these problems can be solved.
  • the first conductor layer 12 provided on the first substrate 11 and the second substrate are provided by providing the first terminal portion 110 on the first substrate 11 side and providing the second terminal portion 120 on the second substrate 21 side. Both of the second conductor layers 22 provided in 21 can be used. As a result, a circuit pattern can be formed using both the first substrate 11 and the second substrate 21, and an increase in the size in the plane direction can be prevented.
  • the wiring length can be shortened, the inductance can be reduced, and the wiring resistance can be reduced. It is beneficial in that it can be reduced.
  • the external device can include, for example, a control board that controls an electronic module.
  • the first surface direction extending portion 114 extends outward from the second surface direction extending portion 124, and the first normal direction extending portion 113 extends from the second normal direction extending portion 123. It may also extend to one side at the periphery outward.
  • the first terminal portion 110 and the second terminal portion 120 can be obtained. Can be connected to the same external device such as a control board.
  • the first terminal portion 110 and the first terminal portion 110 can be obtained.
  • the second terminal portion 120 can be easily connected by the same external device such as a control board.
  • the number of first terminal portions 110 and the number of second terminal portions 120 are the same, and the first surface direction extending portion 114 and the second surface direction extending portion 124 are positioned at the same position in plan view, When the aspect in which the second surface direction extending portion 124 is provided on one side of the surface direction extending portion 114 is adopted, more first terminal portions 110 and second terminal portions 120 are overlapped in a plan view. Can. As a result, it is advantageous in that it can cope with the case where the number of required terminal portions 100 is increased or the width of the terminal portions 100 needs to be increased.
  • second surface direction extending portions 124 are provided on one side of each first surface direction extending portion 114, The aspect in which the first surface direction extending portion 114 is provided on the other side of each second surface direction extending portion 124 is useful. More specifically, a mode in which the first surface direction extending portion 114 and the second surface direction extending portion 124 substantially completely overlap in the width direction (third direction) of the terminal portion 100 (FIGS. It is useful to adopt 5). Note that “substantially completely overlaps” means that the first surface direction extending portion 114 and the second surface direction are between the first surface direction extending portion 114 and the second surface direction extending portion 124. This means that only a deviation of not more than one tenth of the width of the extension portion 124 exists in the plane direction.
  • the first surface direction extending portion 114 and the second surface direction extending portion 124 substantially completely overlap each other in plan view, but in the present embodiment, it is a diagram. As shown in 6, in plan view (in the third direction), a part of the first surface direction extending part 114 and a part of the second surface direction extending part 124 overlap.
  • the other configuration is the same as that of the first embodiment, and all aspects described in the first embodiment can be adopted.
  • the members described in the first embodiment will be described using the same reference numerals.
  • the first electronic element 13 provided on the first substrate 11 and the second electronic element 23 provided on the second substrate 21 perform functions different from each other.
  • the arrangement of the first terminal portion 110 and the second terminal portion 120 may be different.
  • first electronic element 13 provided on the first substrate 11 and the second electronic element 23 provided on the second substrate 21 perform the same function, they may be displaced in the surface direction. Even in such a case, only a part of the first surface direction extending part 114 and a part of the second surface direction extending part 124 overlap in plan view, and all of them do not overlap (FIG. 6). See (a)).
  • the shortest distance between the first terminal portion 110 and the second terminal portion 120 becomes an oblique distance in a plane including the first direction and the third direction. This is advantageous in that it is easy to earn the distance defined by the safety standard and, consequently, the length in the thickness direction can be shortened.
  • the first surface direction extending portion 114 and the second surface direction extending portion 124 do not overlap at all in plan view. It is also conceivable to do.
  • the first terminal portion 110 and the second terminal portion 120 are exposed outward from the sealing portion 90 from one side surface of the electronic module, so-called SIP (Single Inline Package) type It had a structure of In the present embodiment, as shown in FIG. 7, the first terminal portion 110 and the second terminal portion 120 are exposed outward from the sealing portion 90 from two opposing side surfaces of the electronic module, It has a so-called dual inline package (DIP) type structure.
  • SIP Single Inline Package
  • the number of the terminal portions 100 can be increased, and the length in the width direction of the terminal portion 100 can be increased. It is useful in that you can make When the magnitude of the current is increased, it may be necessary to increase the length of the terminal portion 100 in the width direction. Employing this embodiment is advantageous in that it can meet such requirements.
  • the first normal direction extending portion 113 of the first terminal portion 110 and the second normal direction extending portion 123 of the second terminal portion 120 are extended to one side.
  • the first normal direction extending portion 113 of the first terminal portion 110 and the second normal direction extending portion 123 of the second terminal portion 120 extend to the other side. It has become. Also in the present embodiment, any of the aspects described in the above embodiments can be adopted. About the member demonstrated by said each embodiment, it demonstrates using the same code
  • the second surface direction extending portion 124 extends outward in the peripheral edge of the first surface direction extending portion 114, and the second normal direction extending portion 123 is the first normal direction extending portion 113. It is an aspect which extends to the other side peripherally outward. By adopting such an aspect, even when the first surface direction extending portion 114 and the second surface direction extending portion 124 overlap in plan view, the first terminal portion 110 and the second terminal portion 120 can be obtained. Can be connected to the same external device such as a control board.
  • the other side end of the first normal direction extending portion 113 and the other side end of the second normal direction extending portion 123 may be extended to substantially the same position.
  • the first terminal portion 110 and the second terminal portion 120 can be easily connected by the same external device such as a control board.
  • the first normal direction extending portion 113 of the first terminal portion 110 and the second normal direction extending portion 123 of the second terminal portion 120 extend in the same direction.
  • the first normal direction extending portion 113 of the first terminal portion 110 extends to the other side
  • the second normal direction extending portion 123 of the second terminal portion 120 is It extends to one side, and both extend in the opposite direction.
  • any of the aspects described in the above embodiments can be adopted.
  • first surface direction extending portion 114 and the second surface direction extending portion 124 may extend to substantially the same position. Also, unlike such an embodiment, the first in-plane extending portion 114 may extend outward in the circumferential direction more than the second in-plane extending portion 124, or conversely, the second in-plane extending portion 124 May extend further outward in the circumferential direction than the first surface direction extending portion 114.
  • the first normal direction extending portion 113 of the first terminal portion 110 is extended to the other side, and the second normal direction extending portion 123 of the second terminal portion 120 is It can be extended to one side. Therefore, for example, it is possible to adopt an aspect in which the first terminal unit 110 is connected to the first external device and the second terminal unit 120 is connected to the second external device different from the first external device.
  • the present invention is not limited to such an aspect, and the first terminal unit 110 and the second terminal unit 120 may be connected to the same external device. Further, even in the case where the first external device and the second external device as described above are employed, the first external device and the second external device are electrically connected, and one device unit is configured by these. It is also good.
  • the number of first terminal portions 110 and the number of second terminal portions 120 are the same, and second surface direction extending portions 124 are provided on one side of each first surface direction extending portion 114.
  • the first surface direction extending portion 114 may be provided on the other side of each second surface direction extending portion 124. More specifically, in a plan view (in the third direction), the first surface direction extending portion 114 and the second surface direction extending portion 124 may be substantially completely overlapped (see FIG. 10). In this case, it is advantageous in that the number of terminal portions 100 can be increased or the width of the terminal portions 100 can be increased.
  • the first surface direction extending portion 114 and the second surface direction extending portion 124 are substantially completely overlapped in plan view, but in the present embodiment, they are shown in the figure. As shown in 11, in plan view (in the third direction), a part of the first surface direction extending part 114 and a part of the second surface direction extending part 124 overlap.
  • the other configuration is the same as that of the fifth embodiment. Any of the aspects described in the above embodiments can be employed. About the member demonstrated by said each embodiment, it demonstrates using the same code
  • the first electronic element 13 provided on the first substrate 11 and the second electronic element 23 provided on the second substrate 21 perform functions different from each other.
  • the arrangement of the first terminal portion 110 and the second terminal portion 120 may be different (see FIG. 11B).
  • FIG. 11B in a plan view, only a part of the first surface direction extending part 114 and a part of the second surface direction extending part 124 overlap, and all of them do not overlap.
  • first electronic element 13 provided on the first substrate 11 and the second electronic element 23 provided on the second substrate 21 perform the same function, they may be displaced in the surface direction. Even in such a case, only a portion of the first surface direction extending portion 114 and a portion of the second surface direction extending portion 124 overlap in plan view, and all of them do not overlap (FIG. 11). See (a)).
  • the first surface direction extending portion 114 and the second surface direction extending portion 124 are entirely not visible in plan view.
  • a non-overlapping aspect can also be adopted (though it is a drawing related to another embodiment, see also FIG. 6 (c)).
  • the first connection body 60 having a substantially T-shaped cross section is used. However, as shown in FIG. , And four supporting portions 65 (65a to 65d) extending from the other side.
  • the support 65 is in contact with the first conductor layer 12 or the first substrate 11. Also in the present embodiment, any of the aspects described in the above embodiments can be adopted. About the member demonstrated by said each embodiment, it demonstrates using the same code
  • the present embodiment is described using an aspect in which four supporting portions 65 are used, the present invention is not limited to this, and one, two, three, or five or more supporting portions 65 may be used. .
  • the second electronic element is mounted when the second electronic element 23 is mounted or after the second electronic element 23 is mounted.
  • the weight of 23 can prevent the first connection body 60 from being inclined.
  • the heat dissipation can be enhanced by the support portion 65 being in contact with the first substrate 11 or the first conductor layer 12 as described above.
  • the support portion 65 abuts on the first conductor layer 12, it is advantageous in that the heat dissipation effect can be further enhanced.
  • the first connection body 60 can be provided more stably and a higher heat dissipation effect can be realized. .
  • connection body 70 in which the cross section having the second column portion 72 has a substantially T shape, but in the present embodiment, as shown in FIG. 70 has an extending portion 75 (75a, 75b) extending from the second head portion 71 to the other side. Also in the present embodiment, any of the aspects described in the above embodiments can be adopted. About the member demonstrated by said each embodiment, it demonstrates using the same code
  • extension parts 75 are used, the present invention is not limited to this, and one or more extension parts 75 may be used.
  • the extension portion 75 since the extension portion 75 is provided, the heat from the second electronic element 23 can be efficiently dissipated, and a high heat dissipation effect can be realized also by the second connection body 70. .
  • the effects described for the terminal portion 100 described above can be obtained, and the size in the plane direction can be reduced.
  • first substrate 13 first electronic device 21 second substrate 23 second electronic device 110 first terminal portion 113 first normal direction extending portion 114 first surface direction extending portion 120 second terminal portion 123 second normal Direction extension part 124 second surface direction extension part

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Abstract

電子モジュールは、第一基板１１と、第一電子素子１３と、第二電子素子２３と、第二基板２１と、前記第一基板１１側に設けられた第一端子部１１０と、前記第二基板２１側に設けられた第二端子部１２０と、を備える。前記第一端子部１１０は、第一面方向延在部１１４と、一方側又は他方側に延びた第一法線方向延在部１１３と、を有する。前記第二端子部１２０は、第二面方向延在部１２４と、一方側又は他方側に延びた第二法線方向延在部１２３と、を有する。前記第一面方向延在部１１４の一方側に前記第二面方向延在部１２４が設けられ、前記第一面方向延在部１１４と前記第二面方向延在部１２４が面方向で重複する。

Description

電子モジュール
　本発明は、端子部を有する電子モジュールに関する。
　複数の電子素子が封止樹脂内に設けられた電子モジュールが従来から知られている（例えば特開２０１４－４５１５７号参照）。このような電子モジュールに関して小型化することが望まれている。
　小型化する一つの手段として、電子素子を層状に積み重ねていく態様を採用することが考えられる。その際には、電子素子（第一電子素子）の一方側（例えばおもて面側）に別の電子素子（第二電子素子）を設けることが考えられる。
　このような態様を採用した場合には電子素子の数が多くなることから、外部装置と接続するための端子の数を多くする必要がある。第一電子素子が設けられる基板又は第二電子素子が設けられる基板のいずれかにだけ端子が設けられる場合には、端子を配置するためのスペースが必要となり、面方向での大きさが大きくなってしまう。
　本発明は、面方向で大きくなることを防止できる電子モジュールを提供する。
　本発明による電子モジュールは、
　第一基板と、
　前記第一基板の一方側に設けられた第一電子素子と、
　前記第一電子素子の一方側に設けられた第二電子素子と、
　前記第二電子素子の一方側に設けられた第二基板と、
　前記第一基板側に設けられ、前記第一電子素子に電気的に接続される第一端子部と、
　前記第二基板側に設けられ、前記第二電子素子に電気的に接続される第二端子部と、
　を備え、
　前記第一端子部が、前記第一基板の面方向に沿って延びた第一面方向延在部と、前記第一面方向延在部の端部に設けられ、一方側又は他方側に延びた第一法線方向延在部と、を有し、
　前記第二端子部が、前記第二基板の面方向に沿って延びた第二面方向延在部と、前記第二面方向延在部の端部に設けられ、一方側又は他方側に延びた第二法線方向延在部と、を有し、
　前記第一面方向延在部の一方側に前記第二面方向延在部が設けられ、前記第一面方向延在部と前記第二面方向延在部が面方向で重複してもよい。
　本発明による電子モジュールにおいて、
　前記第二法線方向延在部は一方側に延び、
　前記第一面方向延在部は前記第二面方向延在部よりも周縁外方まで延び、
　前記第一法線方向延在部は、前記第二法線方向延在部よりも周縁外方で一方側に延びてもよい。
　本発明による電子モジュールにおいて、
　前記第一法線方向延在部の一方側端部と、前記第二法線方向延在部の一方側端部は略同一の位置まで延びてもよい。
　本発明による電子モジュールにおいて、
　前記第一法線方向延在部は他方側に延び、
　前記第二法線方向延在部は一方側に延びてもよい。
　本発明による電子モジュールにおいて、
　複数の第一端子部が設けられ、
　前記第一端子部と同数の第二端子部が設けられ、
　各第一面方向延在部の一方側に第二面方向延在部が設けられ、
　各第二面方向延在部の他方側に第一面方向延在部が設けられてもよい。
　本発明による電子モジュールにおいて、
　前記端子部の幅方向で、前記第一面方向延在部と前記第二面方向延在部が実質的に完全に重複してもよい。
　本発明の一態様として、第一基板側に第一端子部を設け、第二基板側に第二端子部を設け、第一面方向延在部の一方側に第二面方向延在部の少なくとも一部が位置づけられる態様を採用した場合には、第一基板及び第二基板の両方を用いて端子部を配置することができ、その結果として、面方向での大きさを小さくすることができる。
図１は、本発明の第１の実施の形態で用いられうる電子モジュールの縦断面図である。 図２、本発明の第１の実施の形態で用いられうる第一接続体等を示した平面図である。 図３は、本発明の第１の実施の形態で用いられうる別の例を示した電子モジュールの縦断面図である。 図４（ａ）は、本発明の第１の実施の形態で用いられうる第一基板側の構成を示した平面図であり、図４（ｂ）は、本発明の第１の実施の形態で用いられうる第二基板側の構成を示した平面図である。 図５（ａ）は、本発明の第１の実施の形態で用いられうる電子モジュールの平面図であり、図５（ｂ）は、図５（ａ）のＢ－Ｂ直線で切断した断面図である。 図６（ａ）は、本発明の第２の実施の形態で用いられうる電子モジュールの図５（ｂ）に対応する断面図であり、図６（ｂ）は、本発明の第２の実施の形態で用いられうる別の電子モジュールの図６（ａ）に対応する断面図であり、図６（ｃ）は、本発明の第２の実施の形態で用いられうるさらに別の電子モジュールの図６（ａ）に対応する断面図である。 図７（ａ）は、本発明の第３の実施の形態で用いられうる電子モジュールの平面図であり、図７（ｂ）は、本発明の第３の実施の形態で用いられうる電子モジュールの側方図（第三方向に沿って見た図）である。 図８は、本発明の第４の実施の形態で用いられうる電子モジュールの縦断面図である。 図９は、本発明の第５の実施の形態で用いられうる電子モジュールの縦断面図である。 図１０は、本発明の第５の実施の形態で用いられうる電子モジュールの正面図（第二方向に沿って見た図）である。図１０では、第一法線方向延在部及び第二法線方向延在部が破線で示され、第一面方向延在部及び第二面方向延在部が実線で示されている。 図１１（ａ）は、本発明の第６の実施の形態で用いられうる電子モジュールの正面図であり、図１１（ｂ）は、本発明の第６の実施の形態で用いられうる別の電子モジュールの正面図である。図１１でも、第一法線方向延在部及び第二法線方向延在部が破線で示され、第一面方向延在部及び第二面方向延在部が実線で示されている。 図１２は、本発明の第７の実施の形態で用いられうる第一接続体を示すための平面図である。 図１３は、本発明の第８の実施の形態で用いられうる第二接続体を示すための縦断面図である。 図１４は、本発明の第９の実施の形態で用いられうる電子モジュールの縦断面図である。
第１の実施の形態
《構成》
　本実施の形態において、「一方側」は図１の上方側を意味し、「他方側」は図１の下方側を意味する。図１の上下方向を「第一方向」と呼び、左右方向を「第二方向」と呼び、紙面の表裏方向を「第三方向」と呼ぶ。第二方向及び第三方向を含む面内方向を「面方向」といい、一方側から見た場合には「平面視」という。
　本実施の形態の電子モジュールは、第一電子ユニットと、第二電子ユニットとを有してもよい。
　図１に示すように、第一電子ユニットは、第一基板１１と、第一基板１１の一方側に設けられた複数の第一導体層１２と、第一導体層１２の一方側に設けられた第一電子素子１３と、を有してもよい。第一電子素子１３はスイッチング素子であってもよいし、制御素子であってもよい。第一電子素子１３がスイッチング素子である場合には、第一電子素子１３はＭＯＳＦＥＴやＩＧＢＴ等であってもよい。第一電子素子１３及び後述する第二電子素子２３の各々は半導体素子から構成されてもよく、半導体材料としてはシリコン、炭化ケイ素、窒化ガリウム等であってもよい。第一電子素子１３の他方側の面は第一導体層１２とはんだ等の導電性接着剤（図示せず）を介して接続されてもよい。
　第一電子素子１３の一方側には第一接続体６０が設けられてもよい。第一接続体６０は第一電子素子１３の一方側の面とはんだ等の導電性接着剤を介して接続されてもよい。
　図１に示すように、第一接続体６０の一方側には第二電子ユニットが設けられてもよい。第二電子ユニットは、第一接続体６０の一方側に設けられた第二電子素子２３を有してもよい。また、第二電子ユニットは、第二基板２１と、第二基板２１の他方側に設けられた第二導体層２２を有してもよい。第二導体層２２の他方側には第二接続体７０が設けられてもよい。第二接続体７０は第二電子素子２３の一方側の面及び第二導体層２２の他方側の面とはんだ等の導電性接着剤を介して接続されてもよい。
　第二電子素子２３はスイッチング素子であってもよいし、制御素子であってもよい。第二電子素子２３がスイッチング素子である場合には、第二電子素子２３はＭＯＳＦＥＴやＩＧＢＴ等であってもよい。
　第一接続体６０は、第一ヘッド部６１と、第一ヘッド部６１から他方側に延びた第一柱部６２を有してもよい。第二接続体７０は、第二ヘッド部７１と、第二ヘッド部７１から他方側に延びた第二柱部７２を有してもよい。第一接続体６０は断面が略Ｔ字形状となり、第二接続体７０も断面が略Ｔ字形状となってもよい。
　第一基板１１及び第二基板２１としては、セラミック基板、絶縁樹脂層等を採用することができる。導電性接着剤としては、はんだの他、ＡｇやＣｕを主成分とする材料を用いることもできる。第一接続体６０及び第二接続体７０の材料としてはＣｕ等の金属を用いることができる。なお、基板１１，２１としては例えば回路パターニングを施した金属基板を用いることもでき、この場合には、基板１１，２１が導体層１２，２２を兼ねることになる。
　電子モジュールは、前述した、第一電子素子１３、第二電子素子２３、第一接続体６０、第二接続体７０、第一導体層１２、第二導体層２２等を封止する封止樹脂等から構成される封止部９０を有してもよい。
　第一導体層１２は端子部１００と接続されてもよく、端子部１００の先端側は封止部９０の外方に露出して、制御基板等の外部装置と接続可能となってもよい。
　端子部１００は、第一電子素子１３に電気的に接続される第一端子部１１０と、第二電子素子２３に電気的に接続される第二端子部１２０と、を有してもよい。
　第一端子部１１０は、第一基板１１の面方向に沿って延びた第一面方向延在部１１４と、第一面方向延在部１１４の端部に設けられ、一方側に延びた第一法線方向延在部１１３と、を有してもよい。第二端子部１２０は、第二基板２１の面方向に沿って延びた第二面方向延在部１２４と、第二面方向延在部１２４の端部に設けられ、一方側に延びた第二法線方向延在部１２３と、を有してもよい。第一面方向延在部１１４の一方側に第二面方向延在部１２４の少なくとも一部が位置づけられてもよい（図５参照）。
　図１に示すように、第一面方向延在部１１４は第二面方向延在部１２４よりも周縁外方まで延びてもよい。第一法線方向延在部１１３は第二法線方向延在部１２３よりも周縁外方で一方側に延びてもよい。
　第一法線方向延在部１１３の一方側端部と、第二法線方向延在部１２３の一方側端部は略同一の位置まで延びてもよい。「略同一の位置まで延びる」とは、両者の間には第一法線方向延在部１１３及び第二法線方向延在部１２３のうち長さの短い法線方向延在部（本実施の形態では第二法線方向延在部１２３）の全体長さの５％以内の差しか存在しないことを意味する。
　複数の第一端子部１１０が設けられてもよい。同様に、複数の第二端子部１２０が設けられてもよい。また、第一端子部１１０の数と第二端子部１２０の数が同数であってもよい。このように第一端子部１１０の数と第二端子部１２０の数が同数である場合には、各第一面方向延在部１１４の一方側に第二面方向延在部１２４が設けられ、両者が面方向で重複してもよい。このような態様を採用する一例としては、第一基板１１に設けられる第一電子素子１３と第二基板２１に設けられる第二電子素子２３とが同様の働きをする場合を挙げることができる。
　本実施の形態では、以下、図４及び図５に示すように、第一端子部１１０の数と第二端子部１２０の数が同数であり、平面視において第一面方向延在部１１４と第二面方向延在部１２４とが同じ位置に位置づけられ、第一面方向延在部１１４の一方側に第二面方向延在部１２４が設けられる態様を用いて説明する。しかしながら、このような態様に限られることはなく、後述する第２の実施の形態のように、平面視において第一面方向延在部１１４と第二面方向延在部１２４とが一部だけで重複する態様を採用してもよい。
　図１に示すように、第一端子部１１０は、第一導体層１２に接続される第一端子基端部１１１と、前述した第一面方向延在部１１４と、第一端子基端部１１１と第一面方向延在部１１４との間に設けられ、第一端子基端部１１１側で他方側に曲げられた第一屈曲部１１２と、を有してもよい。第一端子基端部１１１は導電性接着剤を介して第一導体層１２の一方側の面に接続されてもよい。
　第二端子部１２０は、第二導体層２２に接続される第二端子基端部１２１と、前述した第二面方向延在部１２４と、第二端子基端部１２１と第二面方向延在部１２４との間に設けられ、第二端子基端部１２１側で一方側に曲げられた第二屈曲部１２２と、を有してもよい。第二端子基端部１２１は導電性接着剤を介して第二導体層２２の他方側の面に接続されてもよい。
　封止部９０の外方において、第一面方向延在部１１４と第二面方向延在部１２４は第一方向において閾値以上の距離だけ離れてもよい。閾値は安全規格に基づいて決定される数値であってもよい。例えば電子素子が６００Ｖの電圧を用いる場合には、第一面方向延在部１１４と第二面方向延在部１２４は３．６ｍｍ以上の距離だけ離れる必要がある。この場合には、閾値は３．６ｍｍとなる。
　図２に示すように、第一ヘッド部６１の一方側の面には第一溝部６４が設けられてもよい。第一溝部６４は、平面視（面方向）において、第一柱部６２の周縁外方に設けられているが、周縁外方の一部に設けられてもよいし、第一柱部６２の周縁外方の全部に設けられてもよい。第一ヘッド部６１の一方側の面であって、第一溝部６４の周縁内方にははんだ等の導電性接着剤が設けられてもよく、導電性接着剤を介して第二電子素子２３が設けられてもよい。
　図１に示すように、第二電子素子２３の後述する第二ゲート端子２３ｇ等の端子に接続される接続子８５が用いられてもよい。このような態様に限られることはなく、図３に示すような第三接続体８０が利用されてもよい。第三接続体８０は、第三ヘッド部８１と、第三ヘッド部８１から他方側に延びた第三柱部８２を有してもよい。第三接続体８０は、はんだ等の導電性接着剤を介して第二導体層２２の他方側の面及び第二電子素子２３の一方側の面に接続されてもよい。
　図２に示すように、平面視において、第一電子素子１３は、第一ヘッド部６１から外方に露出する態様となってもよい。第一電子素子１３がＭＯＳＦＥＴ等のスイッチング素子である場合には、一方側の面に第一ゲート端子１３ｇ等が設けられてもよい。同様に、第二電子素子２３がＭＯＳＦＥＴ等のスイッチング素子である場合には、一方側の面に第二ゲート端子２３ｇ等が設けられてもよい。図２に示す第一電子素子１３は、一方側の面に第一ゲート端子１３ｇと第一ソース端子１３ｓを有し、第二電子素子２３は、一方側の面に第二ゲート端子２３ｇと第二ソース端子２３ｓを有している。この場合、第二接続体７０が第二電子素子２３の第二ソース端子２３ｓに導電性接着剤を介して接続され、接続子８５が第二電子素子２３の第二ゲート端子２３ｇに導電性接着剤を介して接続されてもよい。また、第一接続体６０は第一電子素子１３の第一ソース端子１３ｓと第二電子素子２３の他方側に設けられた第二ドレイン端子とを導電性接着剤を介して接続してもよい。第一電子素子１３の他方側に設けられた第一ドレイン端子は導電性接着剤を介して第一導体層１２に接続されてもよい。第一電子素子１３の第一ゲート端子１３ｇは導電性接着剤を介して接続子９５（図１参照）に接続され、当該接続子９５は導電性接着剤を介して第一導体層１２に接続されてもよい。
　第一電子素子１３及び第二電子素子２３のいずれか一方だけがスイッチング素子の場合には、第一接続体６０に載置される第二電子素子２３を発熱性の低い制御素子とし、第一電子素子１３をスイッチング素子にすることも考えられる。逆に、第一接続体６０に載置される第二電子素子２３をスイッチング素子とし、第一電子素子１３を発熱性の低い制御素子にすることも考えられる。
　端子部１００と導体層１２，２２との接合は、はんだ等の導電性接着剤を利用する態様だけではなく、レーザ溶接を利用してもよいし、超音波接合を利用してもよい。
《作用・効果》
　次に、上述した構成からなる本実施の形態による作用・効果の一例について説明する。なお、「作用・効果」で説明するあらゆる態様を、上記構成で採用することができる。
　電子モジュールを小型化するために、第一電子素子１３の一方側に第二電子素子２３を設ける態様を採用した場合には電子素子１３，２３の数が増え、結果として端子部１００の数が増える。この点、第一基板１１側に第一端子部１１０を設け、第二基板２１側に第二端子部１２０を設け、第一面方向延在部１１４の一方側に第二面方向延在部１２４の少なくとも一部が位置づけられる態様を採用した場合には、第一基板１１及び第二基板２１の両方を用いて端子部１００を配置することができ、その結果として、面方向での大きさを小さくすることができる点で有益である。
　つまり、内部の電子素子１３，２３を層状に積層（スタック）しても、電子素子１３，２３からの信号を伝達するための端子部１００の数が多くなり、面方向において電子モジュールの大きさが大きくなってしまうことがある。また、第一基板１１側又は第二基板２１側にだけ端子部１００が接続される態様を採用すると、第一導体層１２と第二導体層２２とを電気的に接続するための部材も必要になる。この点、第一基板１１側に第一端子部１１０を設け、第二基板２１側に第二端子部１２０を設けることで、これらの問題を解決することができる点で有益である。
　すなわち、第一基板１１又は第二基板２１だけに端子部１００に電気的に接続するための導体層１２，２２による回路パターンを形成すると、部品点数が多くなるだけでなく、面方向における大きさが大きくなる。この点、第一基板１１側に第一端子部１１０を設け、第二基板２１側に第二端子部１２０を設けることで、第一基板１１に設けられた第一導体層１２と第二基板２１に設けられた第二導体層２２の両方を利用することができる。この結果、第一基板１１及び第二基板２１の両方を用いて回路パターンを形成でき、面方向の大きさが大きくなることを防止できる。
　なお、面方向の大きさが大きくなることを防止することで、第一基板１１及び第二基板２１に反りや歪みが発生することを防止できることにもなる。
　また、第一基板１１側に第一端子部１１０を設け、第二基板２１側に第二端子部１２０を設けることで、配線長さを短くすることができ、インダクタンスを低くし、配線抵抗を低減できる点で有益である。
　第一法線方向延在部１１３と第二法線方向延在部１２３が同じ方向、図１に示す態様では一方側に延びている態様を採用した場合には、第一端子部１１０及び第二端子部１２０を同じ外部装置に接続できる点で有益である。外部装置としては、例えば、電子モジュールを制御する制御基板を挙げることができる。
　この場合には、第一面方向延在部１１４は第二面方向延在部１２４よりも周縁外方まで延び、第一法線方向延在部１１３は第二法線方向延在部１２３よりも周縁外方で一方側に延びてもよい。このような態様を採用することで、第一面方向延在部１１４と第二面方向延在部１２４が平面視において重複する場合であっても、第一端子部１１０及び第二端子部１２０を制御基板等の同じ外部装置に接続させることができるようになる。
　第一法線方向延在部１１３の一方側端部と、第二法線方向延在部１２３の一方側端部は略同一の位置まで延びる態様を採用することで、第一端子部１１０及び第二端子部１２０を制御基板等の同じ外部装置により容易に接続させることができるようになる。
　第一端子部１１０の数と第二端子部１２０の数が同数であり、平面視において第一面方向延在部１１４と第二面方向延在部１２４とが同じ位置に位置づけられ、第一面方向延在部１１４の一方側に第二面方向延在部１２４が設けられる態様を採用した場合には、より多くの第一端子部１１０及び第二端子部１２０を平面視において重複させることができる。この結果、必要な端子部１００の数が増えた場合や端子部１００の幅を大きくする必要がある場合にも対応できる点で有益である。
　なお、端子部１００の数を増やしたり端子部１００の幅を大きくしたりするという観点からすると、各第一面方向延在部１１４の一方側に第二面方向延在部１２４が設けられ、各第二面方向延在部１２４の他方側に第一面方向延在部１１４が設けられる態様が有益である。より限定するならば、端子部１００の幅方向（第三方向）において、第一面方向延在部１１４と第二面方向延在部１２４が実質的に完全に重複する態様（図４及び図５参照）を採用することは有益である。なお、「実質的に完全に重複する」とは、第一面方向延在部１１４と第二面方向延在部１２４との間において、これら第一面方向延在部１１４と第二面方向延在部１２４の幅の１０分の１以下のずれしか面方向で存在しない態様を意味する。
第２の実施の形態
　次に、本発明の第２の実施の形態について説明する。
　第１の実施の形態では、平面視において、第一面方向延在部１１４と第二面方向延在部１２４が実質的に完全に重複する態様であったが、本実施の形態では、図６に示すように、平面視において（第三方向において）、第一面方向延在部１１４の一部と第二面方向延在部１２４の一部が重複する態様となっている。その他の構成については、第１の実施の形態と同様であり、第１の実施の形態で説明したあらゆる態様を採用することができる。第１の実施の形態で説明した部材については同じ符号を用いて説明する。
　第一基板１１に設けられる第一電子素子１３と第二基板２１に設けられる第二電子素子２３とは異なる機能を果たすことも当然にある。このような場合には、図６（ｂ）に示すように、第一端子部１１０と第二端子部１２０の配置態様も異なることがある。この結果、平面視において、第一面方向延在部１１４の一部と第二面方向延在部１２４の一部だけが重複し、これらの全部は重複しないことになる。
　第一基板１１に設けられる第一電子素子１３と第二基板２１に設けられる第二電子素子２３とが同様の機能を果たす場合であっても、面方向でずれて配置されることはある。このような場合にも、平面視において第一面方向延在部１１４の一部と第二面方向延在部１２４の一部だけが重複し、これらの全部は重複しないことになる（図６（ａ）参照）。
　また、このように面方向でずらすことで、第一端子部１１０と第二端子部１２０との間の最短距離が第一方向及び第三方向を含む面内において斜め方向の距離となる。このため、安全規格で定められている距離を稼ぎやすくなり、ひいては、厚み方向の長さを短くすることができる点で有益である。
　この観点からすると、前述した態様とは異なり、図６（ｃ）に示すように、平面視において、第一面方向延在部１１４と第二面方向延在部１２４が全く重複しない態様を採用することも考えられる。
第３の実施の形態
　次に、本発明の第３の実施の形態について説明する。
　上記各実施の形態では、電子モジュールの１つの側面から第一端子部１１０及び第二端子部１２０が封止部９０から外方に露出する態様となっており、いわゆるＳＩＰ（Single Inline Package）型の構造となっていた。本実施の形態では、図７に示すように、電子モジュールの対向する２つの側面から第一端子部１１０及び第二端子部１２０が封止部９０から外方に露出する態様となっており、いわゆるＤＩＰ（Dual Inline Package）型の構造となっている。本実施の形態では、上記各実施の形態で説明したあらゆる態様を採用することができる。上記各実施の形態で説明した部材については同じ符号を用いて説明する。
　本実施の形態によれば、２つの側面を利用して端子部１００を封止部９０の外方に露出させることから、端子部１００の数を増やしたり、端子部１００の幅方向の長さを大きくしたりすることができる点で有益である。電流の大きさが大きくなる場合には、端子部１００の幅方向の長さを大きくする必要があることもある。本実施の形態を採用することで、このような要求にも応えることができる点で有益である。
第４の実施の形態
　次に、本発明の第４の実施の形態について説明する。
　上記各実施の形態では、第一端子部１１０の第一法線方向延在部１１３と第二端子部１２０の第二法線方向延在部１２３が一方側に延びる態様となっていたが、本実施の形態では、図８に示すように、第一端子部１１０の第一法線方向延在部１１３と第二端子部１２０の第二法線方向延在部１２３が他方側に延びる態様となっている。本実施の形態でも、上記各実施の形態で説明したあらゆる態様を採用することができる。上記各実施の形態で説明した部材については同じ符号を用いて説明する。
　本実施の形態では、第二面方向延在部１２４が第一面方向延在部１１４よりも周縁外方まで延び、第二法線方向延在部１２３は第一法線方向延在部１１３よりも周縁外方で他方側に延びる態様となっている。このような態様を採用することで、第一面方向延在部１１４と第二面方向延在部１２４が平面視において重複する場合であっても、第一端子部１１０及び第二端子部１２０を制御基板等の同じ外部装置に接続させることができるようになる。
　第一法線方向延在部１１３の他方側端部と、第二法線方向延在部１２３の他方側端部は略同一の位置まで延びる態様を採用してもよい。このような態様を採用した場合には、第一端子部１１０及び第二端子部１２０を制御基板等の同じ外部装置により容易に接続させることができるようになる。
第５の実施の形態
　次に、本発明の第５の実施の形態について説明する。
　上記各実施の形態では、第一端子部１１０の第一法線方向延在部１１３と第二端子部１２０の第二法線方向延在部１２３が同じ方向に延びる態様となっていたが、本実施の形態では、図９に示すように、第一端子部１１０の第一法線方向延在部１１３は他方側に延び、第二端子部１２０の第二法線方向延在部１２３は一方側に延び、両者が逆方向に延びる態様となっている。本実施の形態でも、上記各実施の形態で説明したあらゆる態様を採用することができる。上記各実施の形態で説明した部材については同じ符号を用いて説明する。
　本実施の形態では、第一面方向延在部１１４と第二面方向延在部１２４は略同一の位置まで延びてもよい。また、このような態様とは異なり、第一面方向延在部１１４は第二面方向延在部１２４よりも周縁外方まで延びてもよいし、逆に、第二面方向延在部１２４は第一面方向延在部１１４よりも周縁外方まで延びてもよい。
　本実施の形態を採用した場合には、第一端子部１１０の第一法線方向延在部１１３を他方側に延在させ、第二端子部１２０の第二法線方向延在部１２３を一方側に延在させることができるようになる。このため、例えば、第一端子部１１０を第一外部装置に接続し、第二端子部１２０を第一外部装置とは異なる第二外部装置に接続する態様を採用することできる。
　このような態様に限ることはなく、第一端子部１１０と第二端子部１２０は同じ外部装置に接続されてもよい。また、前述したような第一外部装置と第二外部装置を採用する場合であっても、第一外部装置と第二外部装置が電気的に接続され、これらによって一つの装置ユニットが構成されてもよい。
　本実施の形態でも、第一端子部１１０の数と第二端子部１２０の数が同数であり、各第一面方向延在部１１４の一方側に第二面方向延在部１２４が設けられ、各第二面方向延在部１２４の他方側に第一面方向延在部１１４が設けられる態様であってもよい。より限定するならば、平面視において（第三方向において）、第一面方向延在部１１４と第二面方向延在部１２４が実質的に完全に重複する態様を採用してもよい（図１０参照）。この場合には、端子部１００の数を増やしたり端子部１００の幅を大きくしたりすることができる点で有益である。
第６の実施の形態
　次に、本発明の第６の実施の形態について説明する。
　第５の実施の形態では、平面視において、第一面方向延在部１１４と第二面方向延在部１２４が実質的に完全に重複する態様であったが、本実施の形態では、図１１に示すように、平面視において（第三方向において）、第一面方向延在部１１４の一部と第二面方向延在部１２４の一部が重複する態様となっている。その他の構成については、第５の実施の形態と同様である。上記各実施の形態で説明したあらゆる態様を採用することができる。上記各実施の形態で説明した部材については同じ符号を用いて説明する。
　前述したように、第一基板１１に設けられる第一電子素子１３と第二基板２１に設けられる第二電子素子２３とは異なる機能を果たすことも当然にある。このような場合には、第一端子部１１０と第二端子部１２０の配置態様も異なることがある（図１１（ｂ）参照）。この結果、平面視において、第一面方向延在部１１４の一部と第二面方向延在部１２４の一部だけが重複し、これらの全部は重複しないことになる。
　第一基板１１に設けられる第一電子素子１３と第二基板２１に設けられる第二電子素子２３とが同様の機能を果たす場合であっても、面方向でずれて配置されることはある。このような場合にも、平面視において第一面方向延在部１１４の一部と第二面方向延在部１２４の一部だけが重複し、これらの全部は重複しないことになる（図１１（ａ）参照）。
　また、第一面方向延在部１１４と第二面方向延在部１２４の距離を長くするために、平面視において、第一面方向延在部１１４と第二面方向延在部１２４が全く重複しない態様を採用することもできる（他の実施の形態に関する図面ではあるが、図６（ｃ）も参照）。
第７の実施の形態
　次に、本発明の第７の実施の形態について説明する。
　上記各実施の形態では、断面が略Ｔ字形状の第一接続体６０が用いられていたが、本実施の形態の第一接続体６０は、図１２に示すように、第一ヘッド部６１から他方側に延びた４つの支持部６５（６５ａ－６５ｄ）を有している。支持体６５は、第一導体層１２又は第一基板１１に当接するようになっている。本実施の形態でも、上記各実施の形態で説明したあらゆる態様を採用することができる。上記各実施の形態で説明した部材については同じ符号を用いて説明する。
　本実施の形態では４つの支持部６５が利用されている態様を用いて説明するが、これに限られることはなく、１、２、３又は５つ以上の支持部６５が用いられてもよい。
　本実施の形態のように第一ヘッド部６１から延びた支持部６５が設けられている場合には、第二電子素子２３の実装時又は第二電子素子２３を実装した後で第二電子素子２３の重みによって第一接続体６０が傾いてしまうことを防止できる。また、このように支持部６５が第一基板１１又は第一導体層１２に当接することで、放熱性を高めることができる。特に支持部６５が第一導体層１２に当接する場合には、放熱効果をより高めることができる点で有益である。
　また、本実施の形態のように複数の支持部６５が設けられている場合には、第一接続体６０をより安定に設けることができ、かつより高い放熱効果を実現できる点で有益である。
第８の実施の形態
　次に、本発明の第８の実施の形態について説明する。
　上記各実施の形態では第二柱部７２を有する断面が略Ｔ字形状からなる第二接続体７０を用いて説明したが、本実施の形態では、図１３に示すように、第二接続体７０は、第二ヘッド部７１から他方側に延びる延在部７５（７５ａ，７５ｂ）を有している。本実施の形態でも、上記各実施の形態で説明したあらゆる態様を採用することができる。上記各実施の形態で説明した部材については同じ符号を用いて説明する。
　本実施の形態では２つの延在部７５が利用されている態様を用いて説明するが、これに限られることはなく、１つ又は３つ以上の延在部７５が用いられてもよい。
　本実施の形態によれば、延在部７５が設けられていることから、第二電子素子２３からの熱を効率よく放熱することができ、第二接続体７０によっても高い放熱効果を実現できる。
　また、本実施の形態のように複数の延在部７５が設けられている場合には、より高い放熱効果を実現できる点で有益である。
第９の実施の形態
　次に、本発明の第９の実施の形態について説明する。
　上記各実施の形態では、第一接続体６０及び第二接続体７０が用いられている態様を用いて説明したが、このような態様には限られない。図１４に示すように、第一接続体６０及び第二接続体７０が設けられていなくてもよい。本実施の形態でも、上記各実施の形態で説明したあらゆる態様を採用することができる。上記各実施の形態で説明した部材については同じ符号を用いて説明する。
　本実施の形態でも、前述した端子部１００について説明した効果を得ることができ、面方向での大きさを小さくすることができる。
　上述した各実施の形態の記載及び図面の開示は、請求の範囲に記載された発明を説明するための一例に過ぎず、上述した実施の形態の記載又は図面の開示によって請求の範囲に記載された発明が限定されることはない。また、出願当初の請求項の記載はあくまでも一例であり、明細書、図面等の記載に基づき、請求項の記載を適宜変更することもできる。
１１　　　　第一基板
１３　　　　第一電子素子
２１　　　　第二基板
２３　　　　第二電子素子
１１０　　　第一端子部
１１３　　　第一法線方向延在部
１１４　　　第一面方向延在部
１２０　　　第二端子部
１２３　　　第二法線方向延在部
１２４　　　第二面方向延在部

Claims (6)

  1. 　第一基板と、
    　前記第一基板の一方側に設けられた第一電子素子と、
    　前記第一電子素子の一方側に設けられた第二電子素子と、
    　前記第二電子素子の一方側に設けられた第二基板と、
    　前記第一基板側に設けられ、前記第一電子素子に電気的に接続される第一端子部と、
    　前記第二基板側に設けられ、前記第二電子素子に電気的に接続される第二端子部と、
    　を備え、
    　前記第一端子部は、前記第一基板の面方向に沿って延びた第一面方向延在部と、前記第一面方向延在部の端部に設けられ、一方側又は他方側に延びた第一法線方向延在部と、を有し、
    　前記第二端子部は、前記第二基板の面方向に沿って延びた第二面方向延在部と、前記第二面方向延在部の端部に設けられ、一方側又は他方側に延びた第二法線方向延在部と、を有し、
    　前記第一面方向延在部の一方側に前記第二面方向延在部が設けられ、前記第一面方向延在部と前記第二面方向延在部が面方向で重複することを特徴とする電子モジュール。
  2. 　前記第二法線方向延在部は一方側に延び、
    　前記第一面方向延在部は前記第二面方向延在部よりも周縁外方まで延び、
    　前記第一法線方向延在部は、前記第二法線方向延在部よりも周縁外方で一方側に延びることを特徴とする請求項１に記載の電子モジュール。
  3. 　前記第一法線方向延在部の一方側端部と、前記第二法線方向延在部の一方側端部は略同一の位置まで延びることを特徴とする請求項２に記載の電子モジュール。
  4. 　前記第一法線方向延在部は他方側に延び、
    　前記第二法線方向延在部は一方側に延びることを特徴とする請求項１に記載の電子モジュール。
  5. 　複数の第一端子部が設けられ、
    　前記第一端子部と同数の第二端子部が設けられ、
    　各第一面方向延在部の一方側に第二面方向延在部が設けられ、
    　各第二面方向延在部の他方側に第一面方向延在部が設けられることを特徴とする請求項１乃至４のいずれか１項に記載の電子モジュール。
  6. 　前記端子部の幅方向において、前記第一面方向延在部と前記第二面方向延在部が実質的に完全に重複することを特徴とする請求項１乃至５のいずれか１項に記載の電子モジュール。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020153190A1 (ja) * 2019-01-21 2020-07-30 ローム株式会社 半導体モジュールおよびａｃ／ｄｃコンバータユニット

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114975128A (zh) * 2021-02-25 2022-08-30 珠海零边界集成电路有限公司 一种智能功率模块及其制备方法
CN117936520A (zh) * 2022-10-14 2024-04-26 力特半导体（无锡）有限公司 单片多通道保护设备

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004047850A (ja) * 2002-07-15 2004-02-12 Mitsubishi Electric Corp パワー半導体装置

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61166148A (ja) 1985-01-18 1986-07-26 Sanyo Electric Co Ltd 多層混成集積回路装置
US4941319A (en) 1987-09-30 1990-07-17 Honda Giken Kogyo Kabushiki Kaisha Engine control device
JPH0671062B2 (ja) 1989-08-30 1994-09-07 株式会社東芝 樹脂封止型半導体装置
JP3253765B2 (ja) 1993-06-25 2002-02-04 富士通株式会社 半導体装置
JP2007027432A (ja) * 2005-07-15 2007-02-01 Sanken Electric Co Ltd 半導体装置
DE102006021959B4 (de) * 2006-05-10 2011-12-29 Infineon Technologies Ag Leistungshalbleiterbauteil und Verfahren zu dessen Herstellung
US8045335B2 (en) 2006-08-09 2011-10-25 Honda Motor Co., Ltd. Semiconductor device
JP4820233B2 (ja) * 2006-08-09 2011-11-24 本田技研工業株式会社 半導体装置
JP5407198B2 (ja) 2008-07-02 2014-02-05 富士電機株式会社 電力変換装置のパワーモジュール
JPWO2010004609A1 (ja) * 2008-07-07 2011-12-22 三菱電機株式会社 電力用半導体装置
JP5557441B2 (ja) * 2008-10-31 2014-07-23 日立オートモティブシステムズ株式会社 電力変換装置および電動車両
JP2013247192A (ja) * 2012-05-24 2013-12-09 Nec Access Technica Ltd パワーモジュール
JP2014045157A (ja) 2012-08-29 2014-03-13 Hitachi Automotive Systems Ltd パワー半導体モジュール
JP6120704B2 (ja) 2013-07-03 2017-04-26 三菱電機株式会社 半導体装置
JP6086989B1 (ja) 2015-04-28 2017-03-01 新電元工業株式会社 半導体モジュール
CN106340513B (zh) * 2015-07-09 2019-03-15 台达电子工业股份有限公司 一种集成控制电路的功率模块
JP6147893B2 (ja) 2016-05-20 2017-06-14 日立オートモティブシステムズ株式会社 電力変換装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004047850A (ja) * 2002-07-15 2004-02-12 Mitsubishi Electric Corp パワー半導体装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020153190A1 (ja) * 2019-01-21 2020-07-30 ローム株式会社 半導体モジュールおよびａｃ／ｄｃコンバータユニット
CN113302736A (zh) * 2019-01-21 2021-08-24 罗姆股份有限公司 半导体模块和ac/dc转换器组件
JPWO2020153190A1 (ja) * 2019-01-21 2021-12-02 ローム株式会社 半導体モジュールおよびａｃ／ｄｃコンバータユニット
CN113302736B (zh) * 2019-01-21 2024-01-02 罗姆股份有限公司 半导体模块和ac/dc转换器组件
JP7461307B2 (ja) 2019-01-21 2024-04-03 ローム株式会社 Ａｃ／ｄｃコンバータユニット

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