CN109511279B - 电子模块 - Google Patents

电子模块 Download PDF

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Publication number
CN109511279B
CN109511279B CN201780012758.9A CN201780012758A CN109511279B CN 109511279 B CN109511279 B CN 109511279B CN 201780012758 A CN201780012758 A CN 201780012758A CN 109511279 B CN109511279 B CN 109511279B
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direction extending
terminal
extending portion
substrate
electronic component
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CN109511279A (zh
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池田康亮
松嵜理
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Shindengen Electric Manufacturing Co Ltd
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Shindengen Electric Manufacturing Co Ltd
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Abstract

本发明的电子模块,包括:第一基板11;第一电子元件13;第二电子元件23;第二基板21;设置在所述第一基板11侧的第一端子部110;以及设置在所述第二基板21侧的第二端子部120。所述第一端子部110具有第一面方向延伸部114、以及向一侧或另一侧延伸的第一法线方向延伸部113。所述第二端子部120具有第二面方向延伸部124、以及向一侧或另一侧延伸的第二法线方向延伸部123。在所述第一面方向延伸部114的一侧上设置有所述第二面方向延伸部124,所述第一面方向延伸部114与所述第二面方向延伸部124在面方向上重合。

Description

电子模块
技术领域
本发明涉及具有端子部的电子模块。
背景技术
以往,在封装树脂内配置有多个电子部件的电子模块已被普遍认知(例如,参照特开2014-45157号)。行业普遍要求能将这种电子模块小型化。
作为小型化的一种手段,可以考虑将电子元件叠层。在这种情况下,可以在电子元件(第一电子元件)的一侧(例如表面侧)设置其他电子元件(第二电子元件)。
由于在采用这种形态时电子元件的数量会变多,就需要增加用于与外部装置连接的端子的数量。当在设置了第一电子元件或者第二电子元件的任意一个基板上设置端子时,因需要留有配置端子所需的空间,因为会导致模块在面方向上的尺寸变大。
本发明的目的在于提供一种电子模块,其能够防止模块在面方向上的尺寸变大。
发明内容
本发明涉及的电子模块,可以包括:
第一基板;
第一电子元件,设置在所述第一基板的一侧;
第二电子元件,设置在所述第一电子元件的一侧;
第二基板,设置在所述第二电子元件的一侧;
第一端子部,设置在第一基板侧上,并且与所述第一电子元件电连接;以及
第二端子部,设置在所述第二基板侧上,并且与所述第二电子元件电连接,
其中,所述第一端子部具有:沿所述第一基板的面方向延伸的第一面方向延伸部、以及设置在所述第一面方向延伸部的端部上的,并且向一侧或另一侧延伸的第一法线方向延伸部,
所述第二端子部具有:沿所述第二基板的面方向延伸的第二面方向延伸部、以及设置在所述第二面方向延伸部的端部上的,并且向一侧或另一侧延伸的第二法线方向延伸部,
在所述第一面方向延伸部的一侧上设置有所述第二面方向延伸部,所述第一面方向延伸部与所述第二面方向延伸部在面方向上重合。
在本发明涉及的电子模块中,可以是:
其中,所述第二法线方向延伸部向一侧延伸,
所述第一面方向延伸部相比所述第二面方向延伸部更加延伸至边缘外部,
所述第一法线方向延伸部在比所述第二法线方向延伸部更靠近边缘外部的位置上向一侧延伸。
在本发明发明涉及的电子模块中,可以是:
其中,所述第一法线方向延伸部的一侧端部,与所述第二法线方向延伸部的一侧端部延伸至大致相同的位置上。
在本发明发明涉及的电子模块中,可以是:
其中,所述第一法线方向延伸部向另一侧延伸,
所述第二法线方向延伸部也可向一侧延伸。
在本发明发明涉及的电子模块中,可以是:
其中,设置多个第一端子部,
设置有与所述第一端子部相同数量的第二端子部,
在各个第一面方向延伸部的一侧上设置有第二面方向延伸部,
在各个第二面方向延伸部的另一侧上设置有第一面方向延伸部。
在本发明发明涉及的电子模块中,还可以是:
在所述端子部的宽度方向上,所述第一面方向延伸部与所述第二面方向延伸部实质上完全重合。
发明效果
作为本发明的一种形态,当采用在第一基板侧上设置第一端子部、在第二基板侧上设置第二端子部,以及在第一面方向延伸部的一侧上至少定位有第二面方向延伸部的一部分形态的情况下,就能够同时使用第一基板以及第二基板这两块基板来配置端子部。这样一来,就能够将其在面方向上的尺寸缩小。
附图说明
图1是可在本发明第一实施方式中使用的电子模块的纵截面图。
图2是可在本发明第一实施方式中使用的第一连接体等的平面图。
图3是可在本发明第一实施方式中使用的其他例电子模块的纵截面图。
图4(a)是可在本发明第一实施方式中使用的第一基板侧的结构的平面图,图4(b)是可在本发明第一实施方式中使用的第二基板侧的结构的平面图。
图5(a)是可在本发明第一实施方式中使用的电子模块的平面图,图5(b)是按图5(a)中的B-B直线切割后的截面图。
图6(a)是可在本发明第二实施方式中使用的电子模块与图5(b)相对应的截面图,图6(b)是可在本发明第二实施方式中使用的其他的电子模块与图6(a)相对应的截面图,图6(c)是可在本发明第二实施方式中使用的其他的电子模块与图6(a)相对应的截面图。
图7(a)是可在本发明第三实施方式中使用的电子模块的平面图,图7(b)是可在本发明第三实施方式中使用的电子模块的侧部图(沿第三方向看后的图)。
图8是可在本发明第四实施方式中使用的电子模块的纵截面图。
图9是可在本发明第五实施方式中使用的电子模块的纵截面图。
图10是可在本发明第五实施方式中使用的电子模块的正面图(沿第二方向看后的图),在图10中,第一法线方向延伸部以及第二法线方向延伸部用虚线表示,第一面方向延伸部以及第二面方向延伸部用实线表示。
图11(a)是可在本发明第六实施方式中使用的电子模块的正面图,图11(b)是可在本发明第六实施方式中使用的其他电子模块的正面图,在图11中也是,第一法线方向延伸部以及第二法线方向延伸部用虚线表示,第一面方向延伸部以及第二面方向延伸部用实线表示。
图12是可在本发明第七实施方式中使用的第一连接体的平面图。
图13是可在本发明第八实施方式中使用的第二连接体的纵截面图。
图14是可在本发明第九实施方式中使用的电子模块的纵截面图。
具体实施方式
第一实施方式
《构成》
在本实施方式中,“一侧”指的是图1中的上方侧,“另一侧”指的是图1中的下方侧。另外,将图1中的上下方向称为“第一方向”、左右方向称为“第二方向”、纸面的表里方向称为“第三方向”。将包含第二方向以及第三方向的面内方向称为“面方向”,将从一侧的方向进行观看称为“从平面看”。
在本实施方式中的电子模块,可以具有:第一电子单元、以及第二电子单元。
如图1所示,第一电子单元具有:第一基板11、在第一基板11的一侧设置的多个第一导体层12、以及在第一导体层12的一侧设置的第一电子元件13。其中,第一电子元件13可以是开关元件,也可以是控制元件。当第一电子元件13成为开关元件的情况下,第一电子元件13也可以是MOSFET或IGBT等。第一电子元件13以及后述的第二电子元件23其各自可由半导体元件构成,作为半导体材料可以是硅、碳化硅、氮化镓等。第一电子元件13的另一侧的面可与第一导体层12通过焊锡等导电性粘合剂(无图示)连接。
在第一电子元件13的一侧可设置第一连接体60。第一连接体60可与第一电子元件13的一侧的面通过焊锡等导电性粘合剂连接。
如图1所示,在第一连接体60的一侧可设置第二电子单元。第二电子单元可以具有:在第一连接体60的一侧设置的第二电子元件23。此外,第二电子单元也具有:第二基板21、以及在第二基板21的另一侧设置的第二导体层22。第二导体层22的另一侧可设置第二连接体70。第二连接体70与第二电子元件23的一侧的面以及第二导体层22的另一侧的面可通过焊锡等导电性粘合剂连接。
第二电子元件23既可以是开关元件,也可以是控制元件。当第二电子元件23成为开关元件的情况下,第二电子元件23可以是MOSFET或IGBT等。
第一连接体60可以具有:第一头部61、以及从第一头部61向另一侧延伸的第一柱部62。第二连接体70可以具有:第二头部71、以及从第二头部71向另一侧延伸的第二柱部72。第一连接体60的截面可以大致呈T字形,第二连接体70的截面也可大致呈T字形。
可采用陶瓷基板或绝缘树脂层等作为第一基板11以及第二基板21。作为导电性粘合剂,除了焊锡以外,也可以使用Ag或Cu来作为主要成分使用。Cu等金属同样可作为第一连接体60以及第二连接体70的材料使用。此外,作为基板11、21,可使用经过电路图案化后的金属基板。此情况下,基板11、21可以兼做导体层12、22。
如前述般,电子模块具有封装部90,封装部90由将第一电子元件13、第二电子元件23、第一连接体60、第二连接体70、第一导体层12、以及将第二导体层22等封装的封装树脂等构成。
第一导体层12可与端子部100连接,端子部100的前端侧露出至封装部90的外部,并可与控制基板等外部装置连接。
端子部100具有与第一电子元件13电连接的第一端子部110、以及与第二电子元件23电连接的第二端子部120。
第一端子部110具有:沿第一基板11的面方向延伸的第一面方向延伸部114、以及在第一面方向延伸部114的端部上设置的,沿一侧延伸的第一法线方向延伸部113。第二端子部120具有:沿第二基板21的面方向延伸的第二面方向延伸部124、以及在第二面方向延伸部124的端部上设置的,沿一侧延伸的第二法线方向延伸部123。其中,可以在第一面方向延伸部114的一侧上至少定位第二面方向延伸部124的一部分(参照图5)。
如图1所示,第一面方向延伸部114相比所述第二面方向延伸部124可以更加延伸至边缘外部。第一法线方向延伸部113相比所述第二法线方向延伸部123也可以在边缘外部上更向一侧延伸。
第一法线方向延伸部113的一侧端部,与第二法线方向延伸部123的一侧端部可以延伸至大致相同的位置。“延伸至大致相同的位置”指的是:两者之间的长度差在:第一法线方向延伸部113以及第二法线方向延伸部123中长度中较短的法线方向延伸部(在本实施方式中为第二法线方向延伸部123)的整体长度的5%以内。
可以设置多个第一端子部110。同样的,也可设置多个第二端子部120。另外,第一端子部110的数量可以与第二端子部120的总数相同。当第一端子部110的数量与第二端子部120的总数相同的情况下,在各个第一面方向延伸部114的一侧上可设置第二面方向延伸部124,两者在面方向上可以重合。作为采用这种形态的一例,能够指出将在第一基板11上设置的第一电子元件13与在第二基板21上设置的第二电子元件23发挥同样作用的情况。
在本实施方式中,以下如图4以及图5所示,对使用了第一端子部110与第二端子部120的数量相同,在平面看时第一面方向延伸部114与第二面方向延伸部124位于相同位置,以及在第一面方向延伸部114的一侧上设置第二面方向延伸部124的形态加以说明。但是,又不限于此形态,也可如后述第二实施方式,采用在平面看时第一面方向延伸部114与第二面方向延伸部124仅一部分重合的形态。
如图1所示,第一端子部110具有:与第一导体层12连接的第一端子基端部111、所述第一面方向延伸部114、以及设置在第一端子基端部111与第一面方向延伸部114之间的,在第一端子基端部111侧向另一侧弯曲的第一弯曲部112。其中,第一端子基端部111可通过导电性粘合剂与第一导体层12的一侧的面连接。
第二端子部120具有:与第二导体层22连接的第二端子基端部121、所述第二面方向延伸部124、以及设置在第二端子基端部121与第二面方向延伸部124之间的,在第二端子基端部121侧向一侧弯曲的第二弯曲部122。其中,第二端子基端部121也可通过导电性粘合剂与第二导体层22的另一侧的面连接。
在封装部90的外部,第一面方向延伸部114与第二面方向延伸部124之间可以在第一方向上隔开不小于阈值的距离。阈值的数值可以根据安全规格来决定。例如将电子部件在600V电压的环境下使用时,第一面方向延伸部114与第二面方向延伸部124的之间距离必须不低于3.6mm。这种情况下,阈值为3.6mm。
如图2所示,可在第一头部61的一侧的面上设置第一沟部64。第一沟部64,在平视方向(面方向)上,虽设置在第一柱部62的边缘外部上,但也可设置在边缘外部的一部分上,还可以设置在第一柱部62的整个边缘外部上。在第一头部61的一侧的面上,并且在第一沟部64的边缘内部上不仅可设置焊锡等导电性粘合剂,也可通过导电性粘合剂设置第二电子元件23。
如图1所示,可使用与第二电子元件23的后述第二栅极端子23g等的端子连接的连接件85。但又不限于此形态,也可使用如图3所示的第三连接体80。第三连接体80具有,第三头部81、以及从第三头部81向另一侧延伸的第三柱部82。第三连接体80,可通过焊锡等导电性粘合剂与第二导体层22的另一的面以及第二电子元件23的一侧的面连接。
如图2所示,在平面看,第一电子元件13可以是从第一头部61向外部露出的形态。当第一电子元件13是MOSFET等开关元件的情况下,可在一侧的面上设置第一栅极端子13g等。同样,当第二电子元件23是MOSFET等开关元件的情况下,可在一侧的面上设置第二栅极端子23g等。如图2所示,在第一电子元件13的一侧的面上具有第一栅极端子13g以及第一源极端子13s,在第二电子元件23一侧的面上具有第二栅极端子23g以及第二源极端子23s。在这种情况下,第二连接体70可与第二电子元件23的第二源极端子23s通过导电性粘合剂连接,连接件85也可与第二电子元件23的第二栅极端子23g通过导电性粘合剂连接。此外,第一连接体60与第一电子元件13的第一源极端子13s以及在第二电子元件23的另一侧设置的第二漏极端子可通过导电性粘合剂连接。在第一电子元件13的另一侧设置的第一漏极端子可通过导电性粘合剂与第一导体层12连接。第一电子元件13的第一栅极端子13g可通过导电性粘合剂与连接件95(参照图1)连接,该连接件95也可通过导电性粘合剂与第一导体层12连接。
当第一电子元件13以及第二电子元件23中的任何一方为开关元件的情况下,可考虑将载置在第一连接体60上的第二电子元件23作为发热性较低的控制元件,并且将第一电子元件13作为开关元件。相反,也可考虑将载置在第一连接体60上的第二电子元件23作为开关元件,并且将第一电子元件13作为发热性较低的控制元件。
端子部100与导体层12、22的接合,不仅可使用焊锡等导电性粘合剂来进行,也可使用激光焊接、以及超音波接合方式来进行。
《作用·效果》
接下来,对上述构成中本实施方式的作用以及效果进行说明。其中,“作用·效果”中说明的所有形态,均可适用于上述构造。
当为了将电子模块小型化从而在第一电子元件13的一侧设置第二电子元件23时,就会增加电子元件13、23的数量,这样一来端子部100的数量也将增加。这时,当采用:在第一基板11侧设置第一端子部110,并且在第二基板21侧设置第二端子部120,以及第二面方向延伸部124的至少一部分位于第一面方向延伸部114的一侧上的形态的情况下,就能够设置同时使用了第一基板11以及第二基板21这两块基板的端子部100,这样一来,就能够有利于将模块在面方向上的尺寸缩小。
也就是说,即使将内部的电子元件13、23叠层(堆层),也会导致用于发送来自于电子元件13、23的信号的端子部100数量变多,进而使其在面方向上的尺寸变大。另外,当端子部100只要与第一基板11侧或者第二基板21侧连接时,就必须要使用将第一导体层12与第二导体层22进行电连接的部件。这时,通过在第一基板11侧上设置第一端子部110、以及在第二基板21侧上设置第二端子部120,就能够解决这些问题。
即,当仅在第一基板11或第二基板21上形成用于与端子部100电连接的导体层12、22的电路图案时,不仅会导致部件数变多,而且其在面方向上的尺寸也会变大。这时,通过在第一基板11侧上设置第一端子部110、以及在第二基板21侧上设置第二端子部120,就能够同时使用在第一基板11上设置的第一导体层12以及在第二基板21上设置的第二导体层22这两个导体层。这样一来,就能够使用第一基板11以及第二基板21这两块基板来形成电路图案,从而防止其在面方向上的尺寸变大。
通过防止其在面方向上的尺寸变大,还能进一步防止第一基板11以及第二基板21发生翘曲变形。
另外,通过在第一基板11侧上设置第一端子部110,并且在第二基板21侧上设置第二端子部120,能够将布线长度缩短,从而降低电阻,有利于将布线电抗降低。
当第一法线方向延伸部113与第二法线方向延伸部123在相同方向,即如图1所示形态中向一侧延伸时,有利于将第一端子部110以及第二端子部120与相同的外部装置相连接,作为外部装置,可以例如用于控制电子模块的控制基板。
在这种情况下,第一面方向延伸部114相比所述第二面方向延伸部124更加延伸至边缘外部,第一法线方向延伸部113相比所述第二法线方向延伸部123在边缘外部上更向一侧延伸。通过采用这种形态,即使第一面方向延伸部114与第二面方向延伸部124在平面上看是重合的情况,也能够将第一端子部110以及第二端子部120与控制基板等相同的外部装置相连接。
当第一法线方向延伸部113的一侧端部,与第二法线方向延伸部123的一侧端部延伸至大致相同的位置上时,能够更容易将第一端子部110以及第二端子部120与控制基板等相同的外部装置相连接。
当第一端子部110的数量与第二端子部120的数量相同,在平面看时第一面方向延伸部114与第二面方向延伸部124位于相同位置,以及在第一面方向延伸部114的一侧上设置第二面方向延伸部124时,能够在平面上看时将更多的第一端子部110以及第二端子部120重合。这样一来,有利于应对在端子部100的数量必须增加或其宽度必须增大时的情况。
从将端子部100的数量增加或将其宽度增大的观点来说,对于在各第一面方向延伸部114的一侧上设置第二面方向延伸部124,以及在各第二面方向延伸部124的另一侧上设置第一面方向延伸部114的形态是有利的。以及,在端子部100的宽度方向(第三方向)上,有利于采用第一面方向延伸部114与第二面方向延伸部124实质上完全重合的形态(参照图4以及图5)。其中,“实质上完全重合”指的是,在第一面方向延伸部114与第二面方向延伸部124之间,两者在面方向上只存在十分之一以下的宽度偏差。
第二实施方式
接下来,将对本实施方式中的第二实施方式进行说明。
在第一实施方式中,在平面上看,虽然第一面方向延伸部114与第二面方向延伸部124完全实质性重合,但是在本实施方式中,如图6所示,在平面上看(第三方向上),第一面方向延伸部114的一部分与第二面方向延伸部124的一部分是重合的形态。关于其他的构造,与第一实施方式相同,可以适用于第一实施方式中说明过的所有形态。对于在第一实施方式中说明过的部件使用相同符号加以说明。
在第一基板11上设置的第一电子元件13与在第二基板21上设置的第二电子元件23当然可以实现不同的功能。这时,如图6(b)所示,第一端子部110与第二端子部120的设置形态也将不同。这样一来,在平面上看,仅第一面方向延伸部114的一部分与第二面方向延伸部124的一部分重合,而不是全部重合。
即使在第一基板11上设置的第一电子元件13与在第二基板21上设置的第二电子元件23实现相同的功能时,也能在面方向上设置为错开。在这种情况下,在平面上看,仅第一面方向延伸部114的一部分与第二面方向延伸部124的一部分重合,而不是全部重合(参照图6(a))。
就像这样通过在面方向上错开,第一端子部110与第二端子部120之间的最短距离会成为包含第一方向以及第三方向的面内倾斜方向的距离。因此,就容易获得安全规定中指定的距离,进而有利于能够将厚度方向上的长度缩短。
从这观点来看,与前述的形态不同,如图6(c)所示,在平面上看,可以考虑采用第一面方向延伸部114与第二面方向延伸部124完全不重合的形态。
第三实施方式
接下来,将对本实施方式中的第三实施方式进行说明。
在上述的各实施方式中,第一端子部110以及第二端子部120在电子模块的一个侧面上露出至封装部90的外部的,即所谓的SIP(Single Inline Package)型构造。而在本实施方式中,如图7所示,第一端子部110以及第二端子部120是在与电子模块相向的两个侧面上露出至封装部90的外部的,即所谓的DIP(Dual Inline Package)型构造。在本实施方式中,上述的各实施方式中说明过的所有形态都可采用。关于上述各实施方式中说明过的部件用相同符号加以说明。
根据本实施方式,由于是利用两个侧面来使端子部100露出至封装部90的外部,因此有助于增加端子部100的数量以及增加端子部100的宽度。在电流强度增大的情况下,有时有必要增加端子部100的宽度。通过采用本实施方式,有助于满足上述这些要求。
第四实施方式
接下来,将对本实施方式中的第四实施方式进行说明。
虽然在上述各实施方式中,第一端子部110的第一法线方向延伸部113与第二端子部120的第二法线方向延伸部123是向一侧延伸的形态,但是在本实施方式中,如图8所示,第一端子部110的第一法线方向延伸部113与第二端子部120的第二法线方向延伸部123是向另一侧延伸的形态。在本实施方式中,上述的各实施方式中说明过的所有形态都可采用。关于上述各实施方式中说明过的部件用相同符号加以说明。
在本实施方式中,第二面方向延伸部124相比所述第一面方向延伸部114可以更加延伸至边缘外部。第二法线方向延伸部123相比所述第一法线方向延伸部113可以在边缘外部上更向另一侧延伸。通过采用这种形态,即使第一面方向延伸部114与第二面方向延伸部124在平面上看是重合的情况,也能够将第一端子部110以及第二端子部120与控制基板等相同的外部装置相连接。
也可采用第一法线方向延伸部113的另一侧端部,与第二法线方向延伸部123的另一侧端部延伸至大致相同的位置形态,在采用这种形态时,能够更容易将第一端子部110以及第二端子部120与控制基板等相同的外部装置相连接。
第五实施方式
接下来,将对本实施方式中的第五实施方式进行说明。
在上述各实施方式种,虽然第一端子部110的第一法线方向延伸部113与第二端子部120的第二法线方向延伸部123是向相同方向延伸的,但在本实施方式中,如图9所示,第一端子部110的第一法线方向延伸部113是向另一侧延伸,第二端子部120的第二法线方向延伸部123向一侧延伸,两者是向相反方向延伸的形态。在本实施方式中,上述的各实施方式中说明过的所有形态都可采用。关于上述各实施方式中说明过的部件用相同符号加以说明。
在本实施方式中,第一面方向延伸部114与第二面方向延伸部124可以延伸至大致相同的位置。另外,与此形态不同,第一面方向延伸部114相比第二面方向延伸部124可以更加延伸至边缘外部,相反,第二面方向延伸部124相比第一面方向延伸部114可以更加延伸至边缘外部。
在采用本实施方式时,可以将第一端子部110的第一法线方向延伸部113向另一侧延伸,将第二端子部120的第二法线方向延伸部123向一侧延伸。因此,例如能够采用将第一端子部110与第一外部装置连接,将第二端子部120与第一外部装置不同的第二外部装置相连接的形态。
不限于此形态,第一端子部110以及第二端子部120也可以与相同的外部装置相连接。另外,即使如前述般采用第一外部装置与第二外部装置的情况,也可与第一外部装置与第二外部装置进行电连接,通过这些来构成一个装置单元。
即使在本实施方式中,第一端子部110与第二端子部120的数量相同,也可以是在各第一面方向延伸部114的一侧上设置第二面方向延伸部124,以及在各第二面方向延伸部124的另一侧上设置第一面方向延伸部114的形态。在平面方向上看(第三方向上),也可采用第一面方向延伸部114与第二面方向延伸部124完全实质重合的形态(参照图10)。在这种情况下,有利于能够将端子部100的数量增多以及将其宽度增大。
第六实施方式
接下来,将对本实施方式中的第六实施方式进行说明。
在第五实施方式中,从平面上看,虽然第一面方向延伸部114与第二面方向延伸部124是完全实质重合的形态,但是在本实施方式中,如图11所示,在平面上看(第三方向上),第一面方向延伸部114的一部分与第二面方向延伸部124的一部分是重合的形态。关于其他的构造,与第五实施方式相同。述的各实施方式中说明过的所有形态都可采用。关于上述各实施方式中说明过的部件用相同符号加以说明。
如前述在第一基板11上设置的第一电子元件13与在第二基板21上设置的第二电子元件23当然也可以实现不同的功能。在这种情况下,第一端子部110与第二端子部120的设置形态也将不同(参照图11(b))。这样一来,在平面上看,仅第一面方向延伸部114的一部分与第二面方向延伸部124的一部分重合。而不是全部重合。
即使在第一基板11上设置的第一电子元件13与在第二基板21上设置的第二电子元件23实现相同的功能时,也能在面方向上设置为错开。在这种情况下,在平面上看,仅第一面方向延伸部114的一部分与第二面方向延伸部124的一部分重合,而不是全部重合(参照图11(a))。
由于将第一面方向延伸部114与第二面方向延伸部124的距离变长,在平面上看,能够采用第一面方向延伸部114与第二面方向延伸部124完全不重合的形态(虽然有关于其他实施方式的附图,也可参照图6(c))。
第七实施方式
接下来,将对本实施方式中的第七实施方式进行说明。
在上述各实施的方式中,虽使用了截面呈大致T字型的第一连接体60,但在本实施方式中,第一连接体60,如图12所示,具有从第一头部61向另一侧延伸的四个支撑部65(65a-65d)。支撑部65与第一导体层12或是与第一基板11相抵接。在本实施方式中,上述的各实施方式中说明过的所有形态都可采用。关于上述各实施方式中说明过的部件用相同符号加以说明。
在本实施方式中,虽然对利用四个支撑部65的形态加以了说明,但不仅限于此,也可使用一个、两个、三个或是五个以上的支撑部65。
如本实施方式般,在设置有从第一头部61延伸的支撑部65的情况下,就能够在安装第二电子部件23时或安装第二电子部件23后,防止因第二电子部件23的重量而导致第一连接体60倾斜。此外,通过支撑部65与第一基板11或一侧第一导体层12相抵接,就能够提高散热性。特别是当支撑部65与第一导体层12相抵接的情况下,有助于进一步提高散热效果。
此外,如本实施方式中设置有多个支撑部65的情况下,就能够更稳定地来设置第一连接体60,并有助于实现更高的散热效果。
第八实施方式
接下来,将对本实施方式中的第八实施方式进行说明。
在上述各实施方式中虽使用了由具有第二柱部72的,并且截面呈大致T字型的第二连接体70加以了说明,但在本实施方式中,如图13所示,第二连接体70具有从第二头部71向另一侧延伸的延伸部75(75a、75b)。在本实施方式中,上述的各实施方式中说明过的所有形态都可采用。关于上述各实施方式中说明过的部件用相同符号加以说明。
虽在本实施方式中对使用两个延伸部75的形态加以了说明,但不仅限于此方式,也可使用一个或三个以上的延伸部75。
根据本实施方式,因设置有延伸部75,因此可以将第二电子部件23的热量有效地进行散热,从而通过第二连接体70实现高散热效果。
另外,如本实施方式般在设置有多个延伸部75的情况下,有助于实现更高的散热效果。
第九实施方式
接下来,将对本实施方式中的第九实施方式进行说明。
上述实施方式中,虽然对使用第一连接体60以及第二连接体70的形态加以了说明,但不仅限于此方式。如图14所示,也可不设置第一连接体60以及第二连接体70。在本实施方式中,上述的各实施方式中说明过的所有形态都可采用。关于上述各实施方式中说明过的部件用相同符号加以说明。
在本实施方式中,同样能够获得包含有关于端子部100的说明中所提到的效果等已述效果,从而能够使其在面方向上的尺寸缩小。
上述各实施方式种的记载以及附图中所展示的内容,仅为用于说明权利要求中记载的发明的一个例子,本发明不受上述记载的实施方式以及附图中所展示的内容所限制。另外,本发明最初申请的请权利要求仅为一例,可根据说明书、附图的记载,对权利要求进行适宜地修改。
符号说明
11 第一基板
13 第一电子元件
21 第二基板
23 第二电子元件
110 第一端子部
113 第一法线方向延伸部
114 第一面方向延伸部
120 第二端子部
123 第二法线方向延伸部
124 第二面方向延伸部

Claims (5)

1.一种电子模块,其特征在于,包括:
第一基板;
第一电子元件,设置在所述第一基板的一侧;
第二电子元件,设置在所述第一电子元件的一侧;
第二基板,设置在所述第二电子元件的一侧;
第一端子部,设置在第一基板侧上,并且与所述第一电子元件电连接;以及
第二端子部,设置在所述第二基板侧上,并且与所述第二电子元件电连接,
其中,所述第一端子部具有:第一端子基端部、沿所述第一基板的面方向延伸的第一面方向延伸部、以及设置在所述第一面方向延伸部的端部上的,并且向一侧或另一侧延伸的第一法线方向延伸部,
所述第二端子部具有:第二端子基端部、沿所述第二基板的面方向延伸的第二面方向延伸部、以及设置在所述第二面方向延伸部的端部上的,并且向一侧或另一侧延伸的第二法线方向延伸部
在所述第一面方向延伸部的一侧上设置有所述第二面方向延伸部,所述第一面方向延伸部与所述第二面方向延伸部在面方向上重合,
所述第一端子基端部与作为金属基板的所述第一基板或与在所述第一基板上设置的第一导体层相抵接,所述第二端子基端部与作为金属基板的所述第二基板或与在所述第二基板上设置的第二导体层相抵接,
在所述第一端子部的一侧以及另一侧上未设置所述第一电子元件,在所述第二端子部的一侧以及另一侧上未设置有所述第二电子元件。
2.根据权利要求1所述的电子模块,其特征在于:
其中,所述第一端子部具有设置在第一端子基端部与所述第一面方向延伸部之间的,并且向另一侧弯曲的第一弯曲部,
所述第二端子部具有设置在所述第二端子基端部与所述第二面方向延伸部之间的,并且向一侧弯曲的第二弯曲部。
3.根据权利要求1所述的电子模块,其特征在于:
其中,所述第一法线方向延伸部向另一侧延伸,
所述第二法线方向延伸部向一侧延伸。
4.根据权利要求1至3中任意一项所述的电子模块,其特征在于:
其中,设置多个第一端子部,
设置与所述第一端子部相同数量的第二端子部,
在各个第一面方向延伸部的一侧上设置有第二面方向延伸部,在各个第二面方向延伸部的另一侧上设置有第一面方向延伸部。
5.根据权利要求1至3中任意一项所述的电子模块,其特征在于,进一步包括:
设置在所述第一电子元件与所述第二电子元件之间的,并且设置在封装部内的第一连接体,
其中,所述第一连接体与所述第一端子部以及所述第二端子部是相互独立的构件。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004047850A (ja) * 2002-07-15 2004-02-12 Mitsubishi Electric Corp パワー半導体装置
CN101501847A (zh) * 2006-08-09 2009-08-05 本田技研工业株式会社 半导体装置
JP2013247192A (ja) * 2012-05-24 2013-12-09 Nec Access Technica Ltd パワーモジュール
JP2015015270A (ja) * 2013-07-03 2015-01-22 三菱電機株式会社 半導体装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61166148A (ja) 1985-01-18 1986-07-26 Sanyo Electric Co Ltd 多層混成集積回路装置
US4941319A (en) 1987-09-30 1990-07-17 Honda Giken Kogyo Kabushiki Kaisha Engine control device
JPH0671062B2 (ja) 1989-08-30 1994-09-07 株式会社東芝 樹脂封止型半導体装置
JP3253765B2 (ja) 1993-06-25 2002-02-04 富士通株式会社 半導体装置
JP2007027432A (ja) * 2005-07-15 2007-02-01 Sanken Electric Co Ltd 半導体装置
DE102006021959B4 (de) * 2006-05-10 2011-12-29 Infineon Technologies Ag Leistungshalbleiterbauteil und Verfahren zu dessen Herstellung
WO2008018332A1 (fr) 2006-08-09 2008-02-14 Honda Motor Co., Ltd. Dispositif à semi-conducteurs
JP5407198B2 (ja) * 2008-07-02 2014-02-05 富士電機株式会社 電力変換装置のパワーモジュール
WO2010004609A1 (ja) * 2008-07-07 2010-01-14 三菱電機株式会社 電力用半導体装置
JP5557441B2 (ja) * 2008-10-31 2014-07-23 日立オートモティブシステムズ株式会社 電力変換装置および電動車両
JP2014045157A (ja) 2012-08-29 2014-03-13 Hitachi Automotive Systems Ltd パワー半導体モジュール
EP3104411A4 (en) 2015-04-28 2017-12-06 Shindengen Electric Manufacturing Co., Ltd. Semiconductor module
CN106340513B (zh) * 2015-07-09 2019-03-15 台达电子工业股份有限公司 一种集成控制电路的功率模块
JP6147893B2 (ja) * 2016-05-20 2017-06-14 日立オートモティブシステムズ株式会社 電力変換装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004047850A (ja) * 2002-07-15 2004-02-12 Mitsubishi Electric Corp パワー半導体装置
CN101501847A (zh) * 2006-08-09 2009-08-05 本田技研工业株式会社 半导体装置
JP2013247192A (ja) * 2012-05-24 2013-12-09 Nec Access Technica Ltd パワーモジュール
JP2015015270A (ja) * 2013-07-03 2015-01-22 三菱電機株式会社 半導体装置

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