WO2018223476A1 - 铟镓锌氧化物薄膜晶体管的制作方法 - Google Patents

铟镓锌氧化物薄膜晶体管的制作方法 Download PDF

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WO2018223476A1
WO2018223476A1 PCT/CN2017/092002 CN2017092002W WO2018223476A1 WO 2018223476 A1 WO2018223476 A1 WO 2018223476A1 CN 2017092002 W CN2017092002 W CN 2017092002W WO 2018223476 A1 WO2018223476 A1 WO 2018223476A1
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thin film
film transistor
metal oxide
transparent insulating
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李松杉
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/244—Electrodes made of transparent conductive layers, e.g. transparent conductive oxide [TCO] layers
    • H10F77/247—Electrodes made of transparent conductive layers, e.g. transparent conductive oxide [TCO] layers comprising indium tin oxide [ITO]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an indium gallium zinc oxide thin film transistor.
  • Indium gallium zinc oxide semiconductors have attracted wide attention due to their high electron mobility, low leakage current, and low preparation temperature.
  • the plasma Ar, He, N 2 , etc. plasma
  • the impedance of the region where the source and drain are in contact gradually recovers, which affects the carrier transmission and ultimately affects the electrical properties of the thin film transistor.
  • the present invention provides a method of fabricating an indium gallium zinc oxide thin film transistor.
  • the present invention provides a method of fabricating an indium gallium zinc oxide thin film transistor, the method comprising:
  • the buffer layer, the active layer, the gate electrode layer and the gate insulating layer are sequentially formed on the substrate and patterned;
  • a passivation layer and a planar insulating organic layer are formed on the dielectric layer and patterned;
  • Indium tin oxide electrode fabrication and pixel definition layer are formed on the passivation layer and the flat insulating organic layer and patterned
  • An organic light emitting device is constructed on the indium tin oxide electrode.
  • the transparent insulating metal oxide layer is diffused toward the surface of the active layer in the annealing process for increasing the concentration of surface carriers on the active layer, and the source and drain electrode regions are electrically conductive,
  • the transparent insulating metal oxide layer is also used to function as a barrier layer to prevent the influence of water and oxygen on the active layer, thereby improving the electrical properties of the thin film transistor.
  • the transparent insulating metal oxide layer has a thickness of 8 nm to 12 nm.
  • the transparent insulating metal oxide layer has a thickness of 10 nm.
  • the annealing treatment temperature is 280-320 °C.
  • the annealing treatment temperature was 300 °C.
  • the transparent insulating metal oxide layer is annealed again.
  • the transparent insulating metal oxide layer is made of alumina.
  • the method for fabricating the indium gallium zinc oxide thin film transistor provided by the present invention deposits a thin transparent transparent metal oxide layer by sputtering and is annealed as compared with the prior art. After the subsequent annealing treatment is used to diffuse aluminum to the surface of the indium gallium zinc oxide semiconductor layer, the result of the conductor contact of the source and drain contact regions can be achieved, and the impedance does not recover and increase, thereby greatly improving the power of the thin film transistor. Sex.
  • the above technical features may be combined in various suitable ways or by equivalent technical features as long as the object of the invention can be achieved.
  • FIG. 1 is a flow chart of a method for fabricating an indium gallium zinc oxide thin film transistor in one embodiment of the present application.
  • FIG. 2 is a schematic view showing the structure of an indium gallium zinc oxide thin film transistor in one embodiment of the present application.
  • a method for fabricating an indium gallium zinc oxide thin film transistor comprising:
  • Step S101 A buffer layer, an active layer (IGZO), a gate electrode layer, and a gate insulator are sequentially formed on the substrate and patterned.
  • IGZO active layer
  • a gate electrode layer a gate insulator
  • Step S102 depositing a transparent insulating metal oxide layer (Al 2 O 3 ) on the treated buffer layer, the active layer, the gate electrode layer and the gate insulating layer by sputtering to oxidize the transparent insulating metal
  • the layer is subjected to an Anneal treatment to improve the electrical properties of the thin film transistor.
  • Step S103 depositing an inter layer dielectric (SiOx) on the transparent insulating metal oxide layer, and using a photo and a dry etch to dielectric layer and transparent insulating metal oxide The layer is graphically processed.
  • SiOx inter layer dielectric
  • Step S104 depositing a source drain (Mo/Al/M0) electrode on the dielectric layer and patterning the same;
  • Step S105 a passivation layer and a planar insulating organic layer are patterned on the dielectric layer and patterned.
  • Step S106 an indium tin oxide electrode (ITO) and a pixel defining layer (PDL) are formed on the passivation layer and the flat insulating organic layer and patterned.
  • ITO indium tin oxide electrode
  • PDL pixel defining layer
  • Step S107 An organic light emitting device (OLED) is constructed on the indium tin oxide electrode.
  • the transparent insulating metal oxide layer is diffused toward the surface of the active layer during the annealing process, for increasing the concentration of surface carriers on the active layer, and the result of conducting the contact of the source and drain electrodes It will not be restored during the subsequent annealing process.
  • the transparent insulating metal oxide layer acts as a barrier to prevent the influence of water (H 2 O) and oxygen (O 2 ) on the active layer, and the impedance will not The recovery is increased, and the electrical properties of the thin film transistor are improved.
  • the transparent insulating metal oxide layer has a thickness of 8 nm to 12 nm, and preferably, the transparent insulating metal oxide layer preferably has a thickness of 10 nm.
  • the indium gallium zinc oxide semiconductor layer, the gate electrode layer, and the gate insulating layer with a transparent insulating metal oxide layer are further annealed.
  • the annealing temperature is 280-320 °C.
  • the annealing treatment temperature is preferably 300 °C.
  • the transparent insulating metal oxide layer is annealed again.
  • the transparent insulating metal oxide layer is made of aluminum oxide or other transparent insulating metal oxide.
  • a buffer layer 4, an active layer 3, a gate insulating layer 2, and a gate electrode layer 1 were formed on the substrate 5, and patterned using a photolithography process.
  • a very thin (about 10 nm) transparent insulating metal oxide layer 6 is deposited by physical vapor deposition, and then an annealing process is performed, and the temperature is controlled at about 300 ° C.
  • the transparent insulating metal oxide layer 6 is Aluminum diffuses to the surface of the indium gallium zinc oxide semiconductor layer 3, increases the concentration of carriers on the surface of the indium gallium zinc oxide semiconductor layer 3, and electrically conducts the source and drain regions.
  • An inter-layer dielectric SiOx 7 is deposited, and an inter-layer dielectric SiOx 7 and a transparent insulating metal oxide layer 6 are formed by a photo and dry etch process. Graphically, the source drain 8 electrode (Mo/Al/M0) is then deposited and patterned.
  • ITO electrode 12 is formed and patterned to form a pixel division layer 10 and patterned.
  • organic light emitting diode Organic Light Emitting Diode
  • organic light emitting material is deposited to complete the fabrication of the organic light emitting diode device 11.
  • a very thin transparent insulating metal oxide layer (Al 2 O 3 ) 6 is deposited by sputtering, and then subjected to an annealing treatment, in which a subsequent annealing treatment is performed, in which a transparent insulating metal oxide layer 6 is used.
  • Aluminum (Al) diffuses to the surface of the active layer (IGZO) 3, increases the concentration of carriers on the surface of the active layer 3, and electrically conducts the source-drain (SD contact) 8 electrode region, and is subsequently annealed (anneal) ) It will not be restored during the process.
  • the transparent insulating metal oxide layer 6 can function as a good barrier layer, preventing the influence of water (H 2 O) and oxygen (O 2 ) on the active layer 3, and can greatly improve the thin film transistor (TFT). Electrical.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

铟镓锌氧化物薄膜晶体管的制作方法，包括：将缓冲层（4）、有源层（3）、栅电极层（1）和栅极绝缘层（2）依次构造在基板（5）上并做图形化处理；通过溅射的方式在处理后的缓冲层（4）、有源层（3）、栅电极层（1）和栅极绝缘层（2）上沉积透明绝缘金属氧化物层（6），将透明绝缘金属氧化物层（6）进行退火处理，使薄膜晶体管电性得到改善。在透明绝缘金属氧化物层（6）上沉积一层介电层（7），并利用黄光和干蚀刻工艺将介电层（7）和透明绝缘金属氧化物层（6）做图形化处理。通过溅射的方式沉积一层很薄的透明绝缘金属氧化物层（6），再进行退火处理，在利用后续的退火处理，将铝向铟镓锌氧化物半导体层表面扩散，同样可以达到源漏极接触区域导体化的结果，而且阻抗不会恢复增大，从而大幅度改善薄膜晶体管的电性。

Description

铟镓锌氧化物薄膜晶体管的制作方法
相关申请的交叉引用
本申请要求享有于2017年6月6日提交的名称为“铟镓锌氧化物薄膜晶体管的制作方法”的中国专利申请CN201710418690.6的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明涉及显示器技术领域，尤其涉及铟镓锌氧化物薄膜晶体管的制作方法。
背景技术
铟镓锌氧化物半导体由于电子迁移率高，漏电流低，制备温度低的特点，引起了广泛的关注。传统的顶栅自对准结构在完成层、栅电极层和栅极绝缘层的图形化后，会采用等离子体(Ar、He、N2等plasma)对源漏极接触的区域进行导体化处理来达到减小接触阻抗的目的，但是在后续的退火时，源漏极接触的区域的阻抗会渐渐恢复变大，影响载流子的传输，最终影响薄膜晶体管的电性。
发明内容
针对上述问题中存在的不足之处，本发明提供铟镓锌氧化物薄膜晶体管的制作方法。
为实现上述目的，本发明提供铟镓锌氧化物薄膜晶体管的制作方法，该方法包括：
将缓冲层、有源层、栅电极层和栅极绝缘层依次构造在基板上并做图形化处理；
通过溅射的方式在处理后的所述缓冲层、有源层、所述栅电极层和所述栅极绝缘层上沉积透明绝缘金属氧化物层，将所述透明绝缘金属氧化物层进行退火处理，使薄膜晶体管电性得到改善；
在所述透明绝缘金属氧化物层上沉积一层介电层，并利用黄光和干蚀刻工艺将所述介电层和所述透明绝缘金属氧化物层做图形化处理；
将源漏极电极沉积在所述介电层上并图形化处理；
钝化层和平坦绝缘有机层构造在所述介电层上并做图形化处理；
铟锡氧化物电极制作和像素定义层构造在所述钝化层和所述平坦绝缘有机层上并做图形化处理
有机发光器件构造在所述铟锡氧化物电极上。
上述的铟镓锌氧化物薄膜晶体管的制作方法，
所述退火处理中所述透明绝缘金属氧化物层向所述有源层表面扩散，用于增加所述有源层表面载流子的浓度，使所述源漏极电极区域导体化，在后续的退火过程中也不会复原，所述透明绝缘金属氧化物层用于起到阻挡层的作用，防止水和氧对所述主动层的影响，使所述薄膜晶体管电性得到改善。
上述的铟镓锌氧化物薄膜晶体管的制作方法，
所述透明绝缘金属氧化物层的厚度为8nm-12nm。
上述的铟镓锌氧化物薄膜晶体管的制作方法，
所述透明绝缘金属氧化物层的厚度为10nm。
上述的铟镓锌氧化物薄膜晶体管的制作方法，
所述退火处理温度为280-320℃。
上述的铟镓锌氧化物薄膜晶体管的制作方法，
所述退火处理温度为300℃。
上述的铟镓锌氧化物薄膜晶体管的制作方法，
对所述透明绝缘金属氧化物层再次退火处理。
上述的铟镓锌氧化物薄膜晶体管的制作方法，
所述透明绝缘金属氧化物层由氧化铝制成。
在上述技术方案中，本发明提供的铟镓锌氧化物薄膜晶体管的制作方法，与现有技术相比，通过溅射的方式沉积一层很薄的透明绝缘金属氧化物层，再进行退火处理，在利用后续的退火处理，将铝向铟镓锌氧化物半导体层表面扩散，同样可以达到源漏极接触区域导体化的结果，而且阻抗不会恢复增大，从而大幅度改善薄膜晶体管的电性。上述技术特征可以各种适合的方式组合或由等效的技术特征来替代，只要能够达到本发明的目的。
附图说明
在下文中将基于实施例并参考附图来对本发明进行更详细的描述。其中：
图1为本申请的一个实施例中铟镓锌氧化物薄膜晶体管的制作方法流程图。
图2为本申请的一个实施例中铟镓锌氧化物薄膜晶体管的结构示意图。
在附图中，相同的部件使用相同的附图标记。附图并未按照实际的比例。
具体实施方式
结合附图和本发明具体实施方式的描述，能够更加清楚地了解本发明的细节。但是，在此描述的本发明的具体实施方式，仅用于解释本发明的目的，而不能以任何方式理解成是对本发明的限制。在本发明的教导下，技术人员可以构想基于本发明的任意可能的变形，这些都应被视为属于本发明的范围，下面将结合附图对本发明作进一步说明。
如图1所示，铟镓锌氧化物薄膜晶体管的制作方法，该方法包括：
步骤S101：将缓冲层(Buffer)、有源层(IGZO)、栅电极层(Gate electrode)和栅极绝缘层(Gate insulator)依次构造在基板上并做图形化处理。
步骤S102：通过溅射(sputter)的方式在处理后的缓冲层、有源层、栅电极层和栅极绝缘层上沉积透明绝缘金属氧化物层(Al2O3)，将透明绝缘金属氧化物层进行退火(Anneal)处理，使薄膜晶体管电性得到改善。
步骤S103：在透明绝缘金属氧化物层上沉积一层介电层(inter layer dielectric：SiOx)，并利用黄光(photo)和干蚀刻工艺(dry etch)将介电层和透明绝缘金属氧化物层做图形化处理。
步骤S104：将源漏极(Mo/Al/M0)电极沉积在介电层上并图形化处理；
步骤S105：钝化层(passivation)和平坦绝缘有机层(planarizatio)构造在介电层上并做图形化处理。
步骤S106：铟锡氧化物电极(ITO)和像素定义层(PDL)构造在钝化层和平坦绝缘有机层上并做图形化处理。
步骤S107：有机发光器件(OLED)构造在铟锡氧化物电极上。
在一个实施例中，退火处理中透明绝缘金属氧化物层向有源层表面扩散，用于增加有源层表面载流子的浓度，使源漏极电极接触(contact)的区域导体化的结果，在后续的退火过程中也不会复原，透明绝缘金属氧化物层用于起到阻挡层的作用，防止水(H2O)和氧(O2)对主动层的影响，而且阻抗不会恢复增大，使薄膜晶体管电性得到改善。
在一个实施例中，透明绝缘金属氧化物层的厚度为8nm-12nm，优选的，透明绝缘金属氧化物层的厚度优选为10nm。
在一个实施例中，再将带有透明绝缘金属氧化物层的铟镓锌氧化物半导体层、栅电极层和栅极绝缘层进行退火处理。
在一个优选实施例中，退火处理温度为280-320℃。
在一个优选实施例中，退火处理温度优选为300℃。
在一个实施例中，对透明绝缘金属氧化物层再次退火处理。
在一个实施例中，透明绝缘金属氧化物层由氧化铝制成或其他透明绝缘金属氧化物制成。
如图2所示，具体使用时：
在基板5上制作缓冲层4，有源层3和栅极绝缘层2和栅电极层1(采用Al+Mo结构)，并使用光刻工艺使其图形化。
利用物理气象沉淀(physical vapor deposition)沉积一层很薄(约10nm)的透明绝缘金属氧化物层6，再进行退火制程，温度控制在300℃左右，此时透明绝缘金属氧化物层6中的铝会向铟镓锌氧化物半导体层3表面扩散，增加铟镓锌氧化物半导体层3表面载流子的浓度，使源漏极8区域导体化。
沉积氧化硅介电层(inter layer dielectric SiOx)7，并利用黄光(photo)和干蚀刻(dry etch)工艺将氧化硅介电层(inter layer dielectric SiOx)7和透明绝缘金属氧化物层6图形化，接着沉积源漏极8电极(Mo/Al/M0)并图形化。
a、制作钝化层(passivation)和平坦绝缘有机层(planarizatio)9并图形化。
b、制作铟锡氧化物(ITO)电极12并图形化，制作像素定义层(pixel division layer)10并图形化。
c、蒸镀有机发光二极管(Organic Light Emitting Diode)有机发光材料，完成有机发光二极管器件11的制作。
通过溅射的方式沉积一层很薄的透明绝缘金属氧化物层(Al2O3)6，再进行退火(anneal)处理，在利用后续的退火处理，此时透明绝缘金属氧化物层6中的铝(Al)会向有源层(IGZO)3表面扩散，增加有源层3表面载流子的浓度，使源漏极(SD contact)8电极区域导体化，而在后续的退火(anneal)过程中也不会复原。同时透明绝缘金属氧化物层6可以起到很好的阻挡层的作用，防止水(H2O)和氧气(O2)对有源层3的影响，进行可以大幅度改善薄膜晶体管(TFT)的电性。
虽然已经参考优选实施例对本发明进行了描述，但在不脱离本发明的范围的 情况下，可以对其进行各种改进并且可以用等效物替换其中的部件。尤其是，只要不存在结构冲突，各个实施例中所提到的各项技术特征均可以任意方式组合起来。本发明并不局限于文中公开的特定实施例，而是包括落入权利要求的范围内的所有技术方案。

Claims (14)

  1. 铟镓锌氧化物薄膜晶体管的制作方法，其中，该方法包括：
    步骤S101：将缓冲层、有源层、栅电极层和栅极绝缘层依次构造在基板上并做图形化处理；
    步骤S102：通过溅射的方式在处理后的所述缓冲层、有源层、所述栅电极层和所述栅极绝缘层上沉积透明绝缘金属氧化物层，将所述透明绝缘金属氧化物层进行退火处理，使薄膜晶体管电性得到改善；
    步骤S103：在所述透明绝缘金属氧化物层上沉积一层介电层，并利用黄光和干蚀刻工艺将所述介电层和所述透明绝缘金属氧化物层做图形化处理；
    步骤S104：将源漏极电极沉积在所述介电层上并图形化处理。
  2. 根据权利要求1所述的铟镓锌氧化物薄膜晶体管的制作方法，其中：
    在步骤S102中，所述退火处理中所述透明绝缘金属氧化物层向所述有源层表面扩散，用于增加所述有源层表面载流子的浓度，使所述源漏极电极区域导体化，在后续的退火过程中也不会复原，所述透明绝缘金属氧化物层用于起到阻挡层的作用，防止水和氧对所述主动层的影响，使所述薄膜晶体管电性得到改善。
  3. 根据权利要求2所述的铟镓锌氧化物薄膜晶体管的制作方法，其中：
    所述透明绝缘金属氧化物层的厚度为8nm-12nm。
  4. 根据权利要求3所述的铟镓锌氧化物薄膜晶体管的制作方法，其中：所述透明绝缘金属氧化物层的厚度为10nm。
  5. 根据权利要求1所述的铟镓锌氧化物薄膜晶体管的制作方法，其中：在步骤S102中，所述退火处理温度为280℃-320℃。
  6. 根据权利要求5所述的铟镓锌氧化物薄膜晶体管的制作方法，其中：所述退火处理温度为300℃。
  7. 根据权利要求1所述的铟镓锌氧化物薄膜晶体管的制作方法，其中：
    在步骤S102中，对所述透明绝缘金属氧化物层再次退火处理。
  8. 根据权利要求1所述的铟镓锌氧化物薄膜晶体管的制作方法，其中：所述透明绝缘金属氧化物层由氧化铝制成。
  9. 根据权利要求1所述的铟镓锌氧化物薄膜晶体管的制作方法，其中：
    还包括在所述介电层上构造钝化层和平坦绝缘有机层并做图形化处理。
  10. 根据权利要求9所述的铟镓锌氧化物薄膜晶体管的制作方法，其中：
    铟锡氧化物电极制作和像素定义层构造在所述钝化层和所述平坦绝缘有机层上并做图形化处理；
    有机发光器件构造在所述铟锡氧化物电极上。
  11. 根据权利要求2所述的铟镓锌氧化物薄膜晶体管的制作方法，其中：
    在步骤S102中，对所述透明绝缘金属氧化物层再次退火处理。
  12. 根据权利要求2所述的铟镓锌氧化物薄膜晶体管的制作方法，其中：
    还包括在所述介电层上构造钝化层和平坦绝缘有机层并做图形化处理。
  13. 根据权利要求12所述的铟镓锌氧化物薄膜晶体管的制作方法，其中：
    铟锡氧化物电极制作和像素定义层构造在所述钝化层和所述平坦绝缘有机层上并做图形化处理；
    有机发光器件构造在所述铟锡氧化物电极上。
  14. 根据权利要求9所述的铟镓锌氧化物薄膜晶体管的制作方法，其中：
    在步骤S102中，所述退火处理中所述透明绝缘金属氧化物层向所述有源层表面扩散，用于增加所述有源层表面载流子的浓度，使所述源漏极电极区域导体化，在后续的退火过程中也不会复原，所述透明绝缘金属氧化物层用于起到阻挡层的作用，防止水和氧对所述主动层的影响，使所述薄膜晶体管电性得到改善。
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