WO2018205752A1 - 掩模板、图案化膜层的制备方法和薄膜晶体管的制备方法 - Google Patents

掩模板、图案化膜层的制备方法和薄膜晶体管的制备方法 Download PDF

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Publication number
WO2018205752A1
WO2018205752A1 PCT/CN2018/079958 CN2018079958W WO2018205752A1 WO 2018205752 A1 WO2018205752 A1 WO 2018205752A1 CN 2018079958 W CN2018079958 W CN 2018079958W WO 2018205752 A1 WO2018205752 A1 WO 2018205752A1
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Prior art keywords
photoresist
pattern
mask
extension
patterned
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PCT/CN2018/079958
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English (en)
French (fr)
Inventor
姜涛
宋博韬
韩领
唐新阳
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US16/098,045 priority Critical patent/US11221555B2/en
Publication of WO2018205752A1 publication Critical patent/WO2018205752A1/zh

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • Embodiments of the present disclosure relate to a mask, a method of fabricating a patterned film layer, and a method of fabricating a thin film transistor.
  • a liquid crystal display (LCD) preparation process includes: providing a first electrode and a second electrode, and then forming a liquid crystal layer having a thickness of about 3 to 4 um between the first electrode and the second electrode.
  • the magnitude of the electric field in the liquid crystal layer can be controlled by changing the voltage applied between the first electrode and the second electrode to adjust the intensity of the transmitted light to form a gray scale image between full brightness and full darkness.
  • a liquid crystal display mainly consists of a color filter, a thin film transistor (TFT) array substrate and a backlight module. Each pixel in the pixel array of the liquid crystal display controls its voltage value through a TFT, thereby enabling the backlight module. The resulting light has a different color.
  • Each of the layers of these pixel arrays can be formed by multiple steps of thin film deposition, mask exposure, and etching.
  • the level of precision required to form each film layer is high. For example, in order to ensure current intensity and increase the width/height ratio, it is usually necessary to form a U-shaped groove on the conductive material layer.
  • a mask having a U-shaped pattern is required, and a U-shaped photoresist pattern is formed by the mask of the U-shaped pattern or a photoresist pattern complementary to the U-shape is formed.
  • a pattern of a corresponding U-shaped film layer is formed on the film to be patterned by etching to form a pixel array.
  • At least one embodiment of the present disclosure provides a reticle including: a first pattern and a second pattern; wherein the first pattern includes a first sidewall, a second sidewall, and the first sidewall a connecting portion with the second side wall and an extension portion of the connecting portion away from the side of the first side wall; the second pattern is located at the first side wall and the second side wall Between the first pattern and the second pattern, there is a slit, and the slit is a slit for diffraction.
  • the first pattern and the second pattern are both plural, and the first pattern and the second pattern are in one-to-one correspondence.
  • a plurality of the first patterns are connected to each other.
  • the extension portion is plural, and each of the first patterns is correspondingly provided with one of the extension portions.
  • the extension is connected to a center of the connecting portion.
  • the extension is an L-shaped structure.
  • the first side wall and the second side wall are parallel to each other, and the extension is perpendicular to the first side wall and the second side
  • the width in the direction of the wall is 1/10 - 1/2 of the distance between the first side wall and the second side wall.
  • the slit has a width of between 1.9 ⁇ m and 2.4 ⁇ m.
  • the slit has a width of between 2.1 ⁇ m and 2.3 ⁇ m.
  • At least one embodiment of the present disclosure further provides a method for preparing a patterned film layer, comprising: sequentially depositing a film to be patterned and a photoresist film; and performing the photoresist film by using the mask plate according to any one of the above Patterning to form a photoresist pattern, wherein the photoresist pattern comprises a photoresist full retention region, a photoresist portion retention region, and a photoresist complete removal region; and the photoresist pattern is thermally baked to a photoresist corresponding to the extension portion of the mask plate flows between the connection portion of the mask plate and a corresponding region of the second pattern; and a portion of the photoresist to be completely removed from the region to be patterned is etched And etching a portion of the resist portion to remove the photoresist in the remaining portion of the photoresist portion; etching a portion of the photoresist portion to be patterned corresponding to the portion to be patterned To form the patterned film layer.
  • the photoresist full retention region corresponds to the first pattern and the second pattern of the mask, the photoresist partially reserved region Corresponding to the slit of the reticle.
  • the thickness of the photoresist in the photoresist partial retention region is 1/4 to 1 of the thickness of the photoresist in the photoresist remaining region. /2.
  • the photoresist in the photoresist portion remaining region before the thermal baking has the first portion and the second portion having different thicknesses.
  • the first portion corresponds to a gap between the first sidewall and the second pattern of the reticle, the second sidewall and a gap between the second patterns; the second portion corresponds to a gap between the connecting portion of the mask and the second pattern.
  • the difference in thickness between the first portion and the second portion is 50-100 nm.
  • the method further includes: removing a portion of the patterned film layer corresponding to the extension of the mask.
  • the patterned film layer includes a conductive film layer, an organic insulating layer, and an inorganic insulating layer.
  • At least one embodiment of the present disclosure provides a method of fabricating a thin film transistor, comprising: forming a patterned film layer by the preparation method according to any one of the above.
  • FIG. 1 is a schematic structural view of a U-shaped groove in a mask for forming a pixel structure
  • FIG. 2 is a connection diagram of a source connection line that causes a "door latch effect"
  • Figure 3 is a schematic view of a channel short circuit caused by a gate plug effect
  • FIG. 4 is a schematic structural diagram of a mask according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of still another reticle according to an embodiment of the present disclosure, wherein a plurality of first patterns are connected to each other;
  • FIG. 6 is a flowchart of a method for preparing a patterned film layer according to an embodiment of the present disclosure
  • FIGS. 7A-7D are flow diagrams involved in the preparation of a patterned film layer according to an embodiment of the present disclosure.
  • FIG. 1 is a schematic view showing the structure of a U-shaped groove in a mask for forming a pixel structure.
  • the mask 100 is formed by a U-shaped pattern 10' and a columnar pattern 20' inserted into the U-shaped pattern 10' to form a U-shaped groove 30'.
  • the shape of the slit at the position is different from the topography at other positions (positions 1, 2, 3, 4), on the reticle
  • the diffracted light transmitted through the slit is more, and the exposure amount of the photoresist in the corresponding region under the mask is larger, and the exposed photoresist is thinner, which may cause the photoresist in the region to be serious. It is developed, which in turn causes the subsequent pixel array processed on the conductive material layer to fail.
  • the density and the number of thin film transistors in the function area (Gate On Array, GOA area) of the display device are larger than the display area (Active Area, AA), such that the functional area
  • the concentration of the developing solution is larger, and therefore, the functional region is more likely to cause the photoresist to be fully developed (PR open).
  • the SSM mask is a mask having a slit width of between 1.9 ⁇ m and 2.4 ⁇ m.
  • the SSM mask can utilize the diffraction principle of light to make the gap of the mask at the groove position narrow so that the light can only pass.
  • the diffraction is transmitted through, thereby reducing the exposure of the photoresist at the region, so that the photoresist is thinned. Since the SSM mask is exposed by the diffraction principle of light, the exposure accuracy is high, and how to ensure the uniformity of the thickness of the photoresist corresponding to the slit after the exposure processing is a difficulty of the present disclosure.
  • the process of forming a pixel structure by using a mask includes a process of cleaning a substrate, plating a substrate, and exposing, developing, and baking a film.
  • FIG. 3 is a schematic diagram of a "channel bridge" caused by the gate plug effect. As shown in FIG. 3, a problem of channel short circuit occurs. This design approach is rejected in the usual design due to the undesired "channel short" problem in the fabrication of the pixel structure.
  • Embodiments of the present disclosure provide a mask, a method of fabricating a patterned film layer, and a method of fabricating a thin film transistor.
  • an extension is added at a position at the center of the bottom of the first pattern.
  • the photoresist formed by the mask is also provided with an extension on the pattern, thereby avoiding the "door latch effect".
  • the photoresist corresponding to the extended portion of the mask is heated to flow to a region corresponding to the gap between the bottom of the first pattern of the mask and the second pattern, whereby, the integrity of the photoresist pattern after exposure is ensured, and the shape of the slit of the U-shaped groove of the mask is solved differently from the gaps at other positions, and the diffracted light transmitted through the slit of the tip position is more
  • the result is that the amount of exposure in the region is large, and the photoresist in the region is thin after exposure, and the problem of photoresist disconnection at the position of the tip of the U-shaped groove corresponding to the mask is prone to occur.
  • FIG. 4 is a schematic structural diagram of a mask according to an embodiment of the present disclosure.
  • the mask 200 includes: a first pattern 201 and a second pattern 202.
  • a pattern 201 includes a first sidewall 2011, a second sidewall 2012, a connecting portion 2013 connecting the first sidewall 2011 and the second sidewall 2012, and an extension at a side of the connecting portion 2013 away from the first sidewall 2011
  • the second pattern 202 is located between the first sidewalls of the first sidewalls 2011 and 2012
  • the slit 203 is formed between the first pattern 201 and the second pattern 202
  • the slit 203 is a slit for diffraction.
  • the slit 203 is a U-shaped slit having a width of between 1.9 ⁇ m and 2.4 ⁇ m.
  • the slit 203 includes position 1, position 2, position 3, position 4, and position 5.
  • the width of the slit is between 2.1 ⁇ m and 2.3 ⁇ m.
  • the slit 203 includes position 1, position 2, position 3, position 4, and position 5.
  • the first pattern 201 may be a substantially U-shaped inner portion for mating with the second pattern 202 to form a U-shaped slit.
  • the form of the first pattern 201 is not particularly limited, for example, the outside of the first pattern 201 and It is not limited to the U-shaped outer contour in FIG.
  • the position where the extension portion 2014 is connected to the connection portion 2013 is not limited, and further, the extension portion 2014 is connected to the center of the connection portion 2013.
  • the extension 2014 includes a corner that extends a portion of the extension 2014 toward the second side wall 2012.
  • the extension portion 2014 has an L-shaped structure.
  • first side wall 2011 and the second side wall 2012 are parallel to each other, and the width of the extension portion 2014 in a direction perpendicular to the first side wall 2011 and the second side wall 2012 is the first side wall 2011 and the second side
  • the distance between the walls 2012 is 1/10-1/2.
  • the width of the extension portion 2014 in a direction perpendicular to the first side wall 2011 and the second side wall 2012 is 1/10, 1/8 of the distance between the first side wall 2011 and the second side wall 2012, 1/6, 1/4 or 1/2.
  • FIG. 5 is a schematic structural diagram of still another reticle according to an embodiment of the present disclosure, in which a plurality of first patterns are connected to each other.
  • the first pattern 201 and the second pattern 202 are multiple, and the first pattern 201 and the second pattern 202 are in one-to-one correspondence, and each of the second patterns 202 is at least partially located in the first pattern 201 . .
  • the plurality of first patterns 201 are connected to each other to form a first pattern 201 arranged side by side, and the adjacent first patterns 201 share one side wall, for example, the second side wall of the first pattern 201 on the left side and The first side wall of the first pattern 201 on the right side is shared.
  • the function area (Gate On Array, GOA area) of the display device is different from the display area (Active Area, AA), and the density and number of Thin Film Transistors (TFTs) are different, and the functional area of the thin film transistor is
  • the mask forming the photoresist pattern may include a plurality of first patterns connected to each other and an extension portion respectively connected to the bottom of each of the first patterns, the plurality of extensions The shapes are the same or different.
  • the extension portion 2014 is plural, and each of the first patterns 201 is correspondingly provided with one extension portion 2014.
  • the extensions 2014 are each connected to the center of each of the connection portions 2013.
  • the photoresist pattern corresponding to the extended portion at the center of the bottom of the first pattern of the mask is uniformly baked while being thermally baked.
  • the ground flows to the center and the vicinity of the corresponding region of the bottom of the first pattern, thereby preventing the occurrence of the problem of photoresist breakage.
  • each of the first patterns 201 are parallel to each other, and each of the extensions 2014 has a width in a direction perpendicular to the first side wall 2011 and the second side wall 2012. 1/10-1/2 of the distance between the first side wall 2011 and the second side wall 2012.
  • the width of the extension portion 2014 in a direction perpendicular to the first side wall 2011 and the second side wall 2012 is 1/10, 1/8 of the distance between the first side wall 2011 and the second side wall 2012, 1/6, 1/4 or 1/2.
  • the shape of the extension portion of the mask for forming the photoresist pattern is not particularly limited as long as the photoresist corresponding to the extension portion of the mask plate flows to the bottom of the first pattern to realize light.
  • the compensation for the glue can be used. From this, it can be seen that, for example, the shape of the extension portion may be an irregular shape such as a rectangle, an ellipse, a cone, a square, a circle, or a drop.
  • the extension 2014 may be located at the entire bottom of the first pattern 201, ie the width of the extension 2014 and the width of the connection 2013 are the same or substantially the same, or the width of the extension 2014 is slightly shorter than the entire bottom, ie the width of the extension 2014 It is smaller than the width of the connecting portion 2013.
  • the compensation effect is relatively good when the width of the extension portion 2014 on the reticle is 1/5 or more and 1/2 or less of the width of the bottom of the first pattern 201, and the width of the extension portion 2014 on the reticle is the first.
  • the compensation effect is not conspicuous, that is, when the width of the extension portion 2014 on the mask plate is 1/5 or more and 1/2 or less of the width of the connection portion 2013, the compensation effect is relatively excellent. .
  • the width of the extension portion 2014 (refer to the width of the extension portion 2014 in the vertical direction of the first side wall 2011 and the second side wall 2012) is the bottom width of the first pattern 201 (the substantially parallel first side wall and the second side) 1/5 or more and 1/2 or less of the distance between the walls, or the width of the extension portion 2014 (refer to the width of the extension portion 2014 in the vertical direction of the first side wall 2011 and the second side wall 2012) is The width of the bottom of the first pattern 201 (the distance between the substantially parallel first side wall and the second side wall) is 1/10 or more and 1/2 or less.
  • FIG. 6 is a flowchart of a method for preparing a patterned film layer
  • FIG. 7 is a patterning method according to an embodiment of the present disclosure.
  • a process diagram of a method for preparing a film layer, and a method for preparing the patterned film layer will be described below with reference to FIG. 6 and FIGS. 7A-7D:
  • S101 depositing a film to be patterned and a photoresist film in sequence.
  • the film to be patterned 301 may be first formed on the substrate substrate 300 by chemical vapor deposition, magnetron sputtering, or the like, and a photoresist film 302 is formed on the film to be patterned 301, and then
  • the film to be patterned 301 may be, for example, a film of a conductive material, such as a positive photoresist.
  • the photoresist film 301 is patterned by using any one of the masks 200 to form a photoresist pattern 303, wherein the photoresist pattern 303 includes a photoresist full retention region 3031 and a photoresist portion retention region. 3032 and photoresist completely removed the area.
  • the photoresist full retention region 3031 corresponds to a region corresponding to the first pattern 201 and the second pattern 202 of the mask 200
  • the photoresist portion retention region 3032 corresponds to the mask 200.
  • Slit 203 Slit 203.
  • the thickness of the photoresist in the photoresist full retention region 3031 is the same as the thickness of the deposited photoresist film, and the thickness of the photoresist in the photoresist portion retention region 3032 is thinned, and the photoresist is completely removed. The photoresist in the area is completely removed.
  • the thickness of the photoresist in the photoresist portion retention region 3032 is 1/4 to 1/2 of the thickness of the photoresist in the photoresist full retention region 3031, for example, the photoresist portion remains in the region 3032.
  • the thickness of the photoresist is 1/4, 1/3 and 1/2 of the thickness of the photoresist in the photoresist full retention region 3031.
  • the photoresist in the photoresist portion retention region 3032 has a first portion having a larger thickness (a portion corresponding to positions 1, 2, 3, and 4) and a second portion having a smaller thickness (a portion corresponding to the position 5). .
  • the first portion having a larger thickness corresponds to a gap (including position 1 and position 2) between the first sidewall 2011 and the second pattern 202 of the mask 200, and the second sidewalls 2012 and 2 of the mask
  • the gap between the patterns 202 corresponds to the gap (position 5) between the connection portion 2013 of the reticle and the second pattern 202.
  • the difference in thickness between the first portion and the second portion is 50-100 nm.
  • the difference in thickness between the first portion and the second portion is 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, and 100 nm.
  • the photoresist pattern can be formed by photolithography and etching by mask transfer.
  • a photoresist film is covered with a mask, and a photoresist film is irradiated by ultraviolet light, near-ultraviolet light, and a part of a wavelength band of visible light near 400 nm by photolithography, for example, the photoresist is positive light.
  • the positive photoresist is rotated to a position where the light is irradiated to form a photoresist full retention region 3031, a photoresist portion retention region 3032, and a photoresist removal region, after removing the mask Then, the photoresist residue in the photoresist removal region is washed away by a chemical cleaning method, and then the photoresist to be patterned corresponding to the photoresist removal region is removed, and the photoresist in the photoresist portion retention region 3032 is subjected to a photoresist. An ashing process is performed to remove the photoresist in the photoresist portion retention region 3032 to form a photoresist pattern.
  • the above reticle used may be, for example, a single slit diffraction (SSM) reticle including a pattern: a first pattern, a second pattern forming a U-shaped slit in cooperation with the first pattern, and a bottom portion connected to the first pattern
  • the extension has a width of between 1.9 ⁇ m and 2.4 ⁇ m.
  • the first pattern refers to a pattern having a substantially U-shaped inner shape for processing a U-shaped slit in cooperation with the second pattern.
  • the shape of the first pattern is not particularly limited.
  • the outside of the first pattern is not limited to U. Outer contour.
  • the SSM mask uses the diffraction principle of light to make the mask gap at the groove position narrow enough that the light can only be transmitted through the diffraction, thereby reducing the exposure of the region on the photoresist to form a semi-transparent. membrane.
  • the photoresist pattern is thermally baked, so that the photoresist corresponding to the extended portion of the mask is heated to flow between the connection portion of the mask and the corresponding region of the second pattern, for example, the photoresist corresponding to the connection portion. Flow to location 5.
  • the photoresist pattern can be baked to a temperature at which the flow can be performed, so that the extension forms a "door latch" according to the bolt effect, and the photoresist corresponding to the extension of the mask plate flows.
  • the photoresist corresponding to the extension of the reticle flows between the connection portion of the reticle and the corresponding region of the second pattern, so that the thickness of the photoresist at the position of 5 is thickened, and the gap from the tip of the U-shaped groove is avoided. 5
  • There is a large amount of diffracted light transmitted which causes a problem that the exposed photoresist is broken.
  • the shape of the extension portion is not particularly limited as long as the photoresist after the hot baking is allowed to flow to the bottom of the first pattern to achieve compensation of the photoresist.
  • the photoresist pattern corresponding to the extension of the reticle may be rectangular, elliptical, tapered, drop-shaped, square, circular, irregular, or the like.
  • S104 etching the photoresist to completely remove a portion of the film to be patterned corresponding to the region.
  • S105 Perform ashing treatment on a portion of the resist remaining region to remove the photoresist in the remaining portion of the photoresist portion.
  • step S105 the photoresist in the remaining portion of the photoresist portion is subjected to ashing treatment to remove the photoresist in the remaining portion of the photoresist portion, thereby saving re-exposure of the photoresist pattern. Process, which saves production costs.
  • the photoresist layer in the U-shaped slit is removed corresponding to the material of the diffraction slit.
  • S106 etching a portion of the photoresist to be patterned corresponding to a portion of the photoresist to be patterned to form a patterned film layer.
  • step S106 the film to be patterned corresponding to the slit of the mask is removed.
  • the compensation effect is relatively excellent when the width of the photoresist pattern corresponding to the extended portion of the mask is 1/10 or more of the width of the photoresist pattern corresponding to the connection portion of the mask. That is, the width of the extension of the mask (refer to the width of the extension in the vertical direction of the first side wall and the second side wall) is 1/ of the width of the connecting portion (the distance between the two substantially parallel side walls) 10 or more or 1/5 or more, and 1/2 or less.
  • the patterned film layer is cleaned by etching, the patterned film layer covered by the photoresist pattern is retained, and the patterned film layer outside the photoresist coverage is removed to form a patterned film layer.
  • the patterned film layer has a pattern corresponding to the photoresist pattern, that is, the patterned film layer includes a pattern corresponding to the first pattern and the second pattern of the mask.
  • the patterned film layer prior to forming the patterned film layer, further comprising: removing material on the patterned film layer corresponding to the extension of the reticle.
  • the film to be patterned corresponding to the extension may be removed by photolithography, etching, or the like. It should be noted that since the patterned film layer corresponding to the formed extension portion belongs to a dummy pattern, it may not be removed without affecting the circuit arrangement.
  • the method further includes removing a portion of the patterned film layer corresponding to the extension of the reticle.
  • portions of the patterned film layer corresponding to the extension of the reticle may be removed by photolithography, etching, or the like.
  • the patterned film layer includes a conductive film layer, an organic insulating layer, and an inorganic insulating layer.
  • At least one embodiment of the present disclosure also provides a method of fabricating a thin film transistor, comprising: forming a patterned film layer by using the above-described method for preparing a patterned film layer.
  • the patterned film layer will be described as an example of a conductive material film layer.
  • Table 1 shows the test results of the HT (photoresist thickness) of the TFT structure.
  • the HT at the position 5 is lower than the position 1-4 when the conductive pattern has no conductive extension. So, so, this SSM-TFT structure has the risk of photoresist disconnection during mass production.
  • the extension portion is added at the tip end position of the U-shaped pattern, so that the mask plate is formed.
  • the photoresist pattern also has an extension.
  • the extension of the photoresist pattern is heated to the position of the U-shaped pattern of the photoresist, which ensures the thickness of the photoresist after exposure, and solves the existing position of the U-shaped groove of the tongue.
  • the shape of the slit is different from other positions, resulting in more diffracted light transmitted through the slit, which leads to a larger exposure amount in the region, and the photoresist after exposure is thin and easily broken.
  • the thin film transistor may be a bottom gate type thin film transistor or a top gate type thin film transistor including a gate, a gate insulating layer, an active layer, a first source drain electrode, and a second source drain electrode.
  • the thin film transistor may be a thin film transistor located in a region of a gate driving circuit substrate or a thin film transistor located in a display region.
  • At least one embodiment of the present disclosure provides a mask, a method of fabricating a patterned film layer, and a method of fabricating a thin film transistor having at least one of the following beneficial effects:
  • a mask provided in at least one embodiment of the present disclosure wherein an extension is added at a position in the center of the bottom of the first pattern, and when a positive photoresist is used, a pattern of a photoresist formed by using the mask is used. It also has an extension to avoid the "door latch effect".
  • a mask provided in at least one embodiment of the present disclosure in the step of thermally baking the photoresist pattern formed by using the mask, the photoresist corresponding to the extension of the mask is heated to the mask.
  • the gap between the bottom of the first pattern and the gap between the second patterns corresponds to the area, thereby ensuring the integrity of the exposed photoresist pattern.
  • the mask provided by at least one embodiment of the present disclosure solves the problem that the shape of the slit of the U-shaped groove of the mask is different from that of the other positions, and the diffracted light transmitted through the slit of the tip position is more
  • the result is that the amount of exposure in the region is large, and the photoresist in the region is thin after exposure, and the problem of photoresist disconnection at the position of the tip of the U-shaped groove corresponding to the mask is prone to occur.

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Abstract

一种掩模板、图案化膜层的制备方法和薄膜晶体管的制备方法，该掩模板(200)包括：第一图案(201)和第二图案(202)，该第一图案(201)包括第一侧壁(2011)、第二侧壁(2012)、连接该第一侧壁(2011)和第二侧壁(2012)的连接部(2013)和位于连接部(2013)的远离第一侧壁(2011)一侧的延长部(2014)，该第二图案(202)位于第一侧壁(2011)和(2012)第二侧壁之间，第一图案(201)和第二图案(202)之间具有狭缝(203)，该狭缝(203)为用于衍射的狭缝。在采用正性光刻胶时，该掩模板(200)的延长部(2014)使得利用该掩模板(200)形成的光刻胶的图案上也具有延长部(2014)对应的区域，从而避免了"门栓效应"，保证了曝光后的光刻胶图案的完整性。

Description

掩模板、图案化膜层的制备方法和薄膜晶体管的制备方法
本申请要求于2017年5月9日递交的中国专利申请第201710321666.0号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种掩模板、图案化膜层的制备方法和薄膜晶体管的制备方法。
背景技术
在显示器件的制备过程中，例如，液晶显示器(LCD)的制备过程包括：提供第一电极和第二电极，然后在第一电极和第二电极之间形成厚度约3～4um的液晶层。这样，可以通过改变施加在第一电极和第二电极之间的电压来控制液晶层中电场的大小，以调节穿透光的强度，进而形成介于全亮与全暗之间的灰阶画面。目前，液晶显示器主要由彩色滤光片、薄膜晶体管(TFT)阵列基板和背光模块三大部分组成，该液晶显示器的像素阵列中的每个像素均通过TFT来控制其电压值，从而使背光模块产生的光线具有不同的色彩。这些像素阵列中的各个膜层可通过多次薄膜沉积、掩膜曝光和刻蚀等步骤来形成。
在形成像素阵列的过程中，对于形成各个膜层的精度水平要求较高。例如，为了保证电流强度，提高宽/高比，通常需要在导电材料层上形成U形沟槽。在形成该U形沟槽的过程中，需要用到具有U形图案的掩模板，利用该U形图案的掩模板形成U形的光刻胶图案或者形成与U形互补的光刻胶图案，再通过刻蚀的方式在待图案化薄膜上形成对应的U形的膜层的图案，从而形成像素阵列。
发明内容
本公开至少一实施例提供一种掩模板，该掩模板包括：第一图案和第二图案；其中，所述第一图案包括第一侧壁、第二侧壁、连接所述第一侧 壁和所述第二侧壁的连接部和位于所述连接部的远离所述第一侧壁一侧的延长部；所述第二图案位于所述第一侧壁和所述第二侧壁之间；所述第一图案和所述第二图案之间具有狭缝，所述狭缝为用于衍射的狭缝。
例如，在本公开至少一实施例提供的掩模板中，所述第一图案和所述第二图案均为多个，所述第一图案和所述第二图案一一对应。
例如，在本公开至少一实施例提供的掩模板中，多个所述第一图案相互连接。
例如，在本公开至少一实施例提供的掩模板中，所述延长部为多个，每个所述第一图案上都对应地设置有一个所述延长部。
例如，在本公开至少一实施例提供的掩模板中，所述延长部连接于所述连接部的中央。
例如，在本公开至少一实施例提供的掩模板中，所述延长部为L型结构。
例如，在本公开至少一实施例提供的掩模板中，所述第一侧壁和所述第二侧壁相互平行，所述延长部在垂直于所述第一侧壁和所述第二侧壁的方向上的宽度为所述第一侧壁和所述第二侧壁之间的距离的1/10-1/2。
例如，在本公开至少一实施例提供的掩模板中，所述狭缝的宽度在1.9μm-2.4μm之间。
例如，在本公开至少一实施例提供的掩模板中，所述狭缝的宽度在2.1μm-2.3μm之间。
本公开至少一实施例还提供一种图案化膜层的制备方法，包括：依次沉积待图案化薄膜和光刻胶薄膜；采用上述任一项所述的掩模板对所述光刻胶薄膜进行构图以形成光刻胶图案，其中，所述光刻胶图案包括光刻胶全保留区域、光刻胶部分保留区域和光刻胶完全去除区域；对所述光刻胶图案进行热烘，使所述掩模板的延长部对应的光刻胶流动至所述掩模板的连接部和第二图案对应的区域之间；刻蚀所述光刻胶完全去除区域对应的部分所述待图案化薄膜；对所述光刻胶部分保留区域进行灰化处理，以去除所述光刻胶部分保留区域中的光刻胶；刻蚀所述光刻胶部分保留区域对应的部分所述待图案化薄膜，以形成所述图案化膜层。
例如，在本公开至少一实施例提供的制备方法中，所述光刻胶全保留 区域对应于所述掩模板的所述第一图案和所述第二图案，所述光刻胶部分保留区域对应于所述掩模板的所述狭缝。
例如，在本公开至少一实施例提供的制备方法中，所述光刻胶部分保留区域中光刻胶的厚度为所述光刻胶全保留区域中光刻胶的厚度的1/4～1/2。
例如，在本公开至少一实施例提供的制备方法中，热烘之前所述光刻胶部分保留区域中的光刻胶具有厚度不同的第一部分和第二部分。
例如，在本公开至少一实施例提供的制备方法中，所述第一部分对应于所述掩模板的所述第一侧壁和所述第二图案之间的间隙、所述第二侧壁和所述第二图案之间的间隙；所述第二部分对应于所述掩模板的所述连接部和所述第二图案之间的间隙。
例如，在本公开至少一实施例提供的制备方法中，所述第一部分和所述第二部分的厚度差为50-100nm。
例如，在本公开至少一实施例提供的制备方法中，在形成所述图案化膜层之后，还包括：去除所述图案化膜层的对应于所述掩模板的延长部的部分。
例如，在本公开至少一实施例提供的制备方法中，所述图案化膜层包括导电膜层、有机绝缘层和无机绝缘层。
本公开至少一实施例还提供一种薄膜晶体管的制备方法，包括：采用上述任一项所述的制备方法形成图案化膜层。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种用于形成像素结构的掩模板中的U形沟槽的结构示意图；
图2为一种导致“门栓效应”的源极连接线的连接方式图；
图3为门栓效应导致的沟道短路的示意图；
图4为本公开一实施例提供的一种掩模板的结构示意图；
图5为本公开一实施例提供的再一种掩模板的结构示意图，其中，多 个第一图案相互连接；
图6为本公开一实施例提供的一种图案化膜层的制备方法的流程图；以及
图7A-7D为本公开一实施例提供的一种图案化膜层的制备过程中涉及的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的术语“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为一种用于形成像素结构的掩模板中的U形沟槽的结构示意图。如图1所示，该掩模板100采用U形图案10’和插入U形图案10’中的柱状图案20’共同构成U形槽30’，图1中的U形槽30’包括位置标号为1、2、3、4、5构成的图形。
但是，在U形槽30’的舌尖位置处(位置5)，由于该位置处的缝隙的形貌同其他位置处的形貌(位置1、2、3、4)不同，在该掩模板上，从该缝隙透过的衍射光较多，进而导致掩模板下方对应区域的光刻胶的曝光量较大，且曝光后的光刻胶较薄，严重时会导致该区域的光刻胶全部被显影，进而导致后续在导电材料层上加工出的像素阵列不合格。
例如，在显示器件的制备过程中，相较于显示区(Active Area，AA)， 显示器件的功能区域(Gate On Array，GOA区)中的薄膜晶体管的密度和数量均较大，这样功能区域中显影液的浓度会更大，因此，该功能区域更易导致光刻胶全部被显影(PR open)。
为了提高加工精度，目前，还提出一种利用单缝衍射掩模板(Single Slit Mask，SSM)制作上述像素阵列的工艺。SSM掩模板是狭缝的宽度在1.9μm-2.4μm之间的掩模板，SSM掩模板可以利用光的衍射原理，将沟槽位置处的掩模板的缝隙做得很窄，使光只能通过衍射的方式透过，从而降低了在该区域处对光刻胶的曝光量，使得光刻胶减薄。由于SSM掩模板是利用光的衍射原理进行曝光，所以对曝光精度的要求较高，如何保证曝光处理后对应于狭缝处的光刻胶的厚度的均一性是本公开的难点。
例如，在形成像素结构的过程中，还需要避免一种“门栓效应”，以下结合图2进行说明。图2为一种容易产生“门栓效应”的TFT像素的图案。图2中未示出的TFT的源极通过连接线40’(位置6)与信号线相连，与其相邻的狭缝为位置4所示的狭缝。利用掩模板形成像素结构的过程依次包括清洗衬底基板、在衬底基板上镀膜、对薄膜进行曝光、显影、热烘(Hard Bake)等工序。由于光刻胶在热烘的过程中会受热变形，因此连接线(位置6)处的光刻胶会热变形流动导致位置4处的光刻胶(Half Tone)的厚度增加，从而导致位置4处的光刻胶的厚度较大，这就是所谓的“门栓效应”。图3为门栓效应导致的“沟道短路(Channel Bridge)”的示意图，如图3所示，出现了沟道短路的问题。由于在制备像素结构的过程中出现了不期望出现的“沟道短路”的问题，所以在通常的设计中会摒弃这种设计方式。
本公开的实施例提供了一种掩模板、图案化膜层的制备方法和薄膜晶体管的制备方法，通过改进掩模板的设计，在第一图案的底部中央的位置增加了延长部，在采用正性光刻胶时，使得利用该掩模板形成的光刻胶的图案上也具有延长部，从而避免了“门栓效应”。在对形成的光刻胶图案进行热烘的工序中，掩模板的延长部对应的光刻胶会受热流动至掩模板的第一图案的底部和第二图案之间的间隙对应的区域中，从而保证了曝光后的光刻胶图案的完整性，解决了掩模板的U形槽的舌尖位置的缝隙的形貌同其他位置的缝隙不同，导致的从舌尖位置的缝隙透过的衍射光较多，进而 导致该区域的曝光量较大，曝光后该区域的光刻胶较薄，易于出现对应于掩模板的U形槽的舌尖位置处的光刻胶断开的问题。
本公开至少一实施例提供一种掩模板，例如，图4为本公开一实施例提供的一种掩模板的结构示意图，该掩模板200包括：第一图案201和第二图案202，该第一图案201包括第一侧壁2011、第二侧壁2012、连接该第一侧壁2011和第二侧壁2012的连接部2013和位于连接部2013的远离第一侧壁2011一侧的延长部2014，该第二图案202位于第一侧壁2011和2012第二侧壁之间，第一图案201和第二图案202之间具有狭缝203，该狭缝203为用于衍射的狭缝。
例如，该狭缝203为U形狭缝，狭缝的宽度在1.9μm-2.4μm之间。例如，该狭缝203包括位置1、位置2、位置3、位置4和位置5。
再例如，该狭缝的宽度在2.1μm-2.3μm之间。例如，该狭缝203包括位置1、位置2、位置3、位置4和位置5。
例如，第一图案201可以是内部大致呈U形、用于与第二图案202配合形成U形狭缝的图案，第一图案201的形式并不特别限定，例如，第一图案201的外部并不限定为图4中的U形外轮廓。
例如，该延长部2014连接于连接部2013的位置不限，进一步地，该延长部2014连接于连接部2013的中央。
例如，该延长部2014包括一拐角，该拐角使得延长部2014的一部分向第二侧壁2012的方向延伸。
例如，该延长部2014为L型结构。
例如，该第一侧壁2011和第二侧壁2012相互平行，该延长部2014在垂直于第一侧壁2011和第二侧壁2012的方向上的宽度为第一侧壁2011和第二侧壁2012之间的距离的1/10-1/2。
例如，该延长部2014在垂直于第一侧壁2011和第二侧壁2012的方向上的宽度为第一侧壁2011和第二侧壁2012之间的距离的1/10，1/8，1/6，1/4或者1/2。
例如，图5为本公开一实施例提供的再一种掩模板的结构示意图，其中，多个第一图案相互连接。如图5所示，该第一图案201和第二图案202均为多个，第一图案201和第二图案202一一对应，每个第二图案202都 至少部分地位于第一图案201内。
例如，该多个第一图案201相互连接，以形成并排设置的第一图案201，且相邻的第一图案201共用一个侧壁，例如，左侧的第一图案201的第二侧壁和右侧的第一图案201的第一侧壁共用。
例如，在实际的工艺过程中，同一层待图案化膜层的图案上需要形成不止一个第一图案。例如，显示器件的功能区域(Gate On Array，GOA区)相较于显示区(Active Area，AA)，薄膜晶体管(Thin Film Transistor，TFT)的密度和数量均不一样，功能区域的薄膜晶体管的密度高于显示区中薄膜晶体管的密度，因此，形成光刻胶图案的掩模板可以包括相互连接的多个第一图案和分别连接于每一个第一图案底部的延长部，多个延长部的形状相同或不同。
例如，该延长部2014为多个，每个第一图案201上都对应地设置有一个延长部2014。
例如，该延长部2014均分别连接于各个连接部2013的中央。
例如，在利用该掩模板形成光刻胶图案时，对应于掩模板的第一图案底部中央的延长部的光刻胶图案，在对其进行热烘时，热烘后的光刻胶会均匀地流动至第一图案的底部对应的区域的中央及附近，从而防止出现光刻胶断裂的问题。
例如，每个第一图案201的第一侧壁2011和第二侧壁2012均相互平行，每个延长部2014在垂直于第一侧壁2011和第二侧壁2012的方向上的宽度均为第一侧壁2011和第二侧壁2012之间的距离的1/10-1/2。
例如，该延长部2014在垂直于第一侧壁2011和第二侧壁2012的方向上的宽度为第一侧壁2011和第二侧壁2012之间的距离的1/10，1/8，1/6，1/4或者1/2。
需要说明的是，形成光刻胶图案的掩模板的延长部的形状并不特别限制，只要能够实现热烘后，掩模板的延长部对应的光刻胶流动至第一图案的底部，实现光刻胶的补偿即可。由此可知，例如，该延长部的形状可以是长方形、椭圆形、锥形、正方形、圆形或者水滴状等不规则形状。
例如，延长部2014可以位于第一图案201的整个底部，即延长部2014的宽度和连接部2013的宽度相同或者基本相同，或者延长部2014的宽度 稍短于整个底部，即延长部2014的宽度小于连接部2013的宽度。
另外，实验证明，掩模板上的延长部2014的宽度为第一图案201底部宽度的1/5以上且1/2以下时补偿效果相对较优，掩模板上的延长部2014的宽度为第一图案201底部宽度的1/10以下时，补偿效果就会不明显，即掩模板上的延长部2014的宽度为连接部2013的宽度的1/5以上且1/2以下时补偿效果相对较优。例如，延长部2014的宽度(指延长部2014在第一侧壁2011和第二侧壁2012的垂直方向上的宽度)为第一图案201底部宽度(大致平行的第一侧壁和第二侧壁之间的距离)的1/5以上，且1/2以下，或者，延长部2014的宽度(指延长部2014在第一侧壁2011和第二侧壁2012的垂直方向上的宽度)为第一图案201底部宽度(大致平行的第一侧壁和第二侧壁之间的距离)的1/10以上，且1/2以下。
本公开至少一实施例还提供一种图案化膜层的制备方法，例如，图6为一种图案化膜层的制备方法的流程图，图7为本公开一实施例提供的一种图案化膜层的制备方法的过程图，下面结合图6和图7A-7D说明该图案化膜层的制备方法：
S101：依次沉积待图案化薄膜和光刻胶薄膜。
例如，如图7A所示，可以首先在衬底基板300上利用化学气相沉积、磁控溅射等方式形成待图案化薄膜301，并在待图案化薄膜301上形成光刻胶薄膜302，然后进行后续的操作，该待图案化薄膜301，例如可以为导电材料薄膜，该光刻胶薄膜301例如为正性光刻胶。
S102：采用上述任意一种掩模板200对该光刻胶薄膜301进行构图以形成光刻胶图案303，其中，该光刻胶图案303包括光刻胶全保留区域3031、光刻胶部分保留区域3032和光刻胶完全去除区域。
例如，如图7B和7C所示，该光刻胶全保留区域3031对应于掩模板200的第一图案201和第二图案202对应的区域，该光刻胶部分保留区域3032对应于掩模板200的狭缝203。
例如，该光刻胶全保留区域3031中的光刻胶的厚度和沉积的光刻胶薄膜的厚度一致，光刻胶部分保留区域3032中的光刻胶的厚度减薄，光刻胶完全去除区域中的光刻胶被完全去除。
例如，该光刻胶部分保留区域3032中光刻胶的厚度为光刻胶全保留 区域3031中光刻胶的厚度的1/4～1/2，例如，该光刻胶部分保留区域3032中光刻胶的厚度为光刻胶全保留区域3031中光刻胶的厚度的1/4，1/3和1/2。
例如，该光刻胶部分保留区域3032中的光刻胶具有厚度较大的第一部分(位置1，2，3和4对应的部分)和厚度较小的第二部分(位置5对应的部分)。
例如，该厚度较大的第一部分对应于掩模板200的第一侧壁2011和第二图案202之间的间隙(包括位置1和位置2)，以及掩模板的第二侧壁2012和第二图案202之间的间隙(包括位置3和位置4)，第二部分对应于掩模板的连接部2013和第二图案202之间的间隙(位置5)。
例如，该第一部分和第二部分的厚度差为50-100nm。
例如，该第一部分和第二部分的厚度差为50nm、60nm、70nm、80nm、90nm和100nm。
例如，可以采用光刻和蚀刻的方法，通过掩模板转印的方式形成该光刻胶图案。
例如，首先用掩模板覆盖光刻胶薄膜，通过光刻的方式，利用紫外线、近紫外光和其他波长400nm附近的部分波段的可见光照射光刻胶薄膜，例如，该光刻胶为正性光刻胶，使被光照射到的位置的正性光刻胶发生转性，以形成光刻胶全保留区域3031、光刻胶部分保留区域3032和光刻胶去除区域，在移除掩模板之后，再利用化学清洗的方法将光刻胶去除区域的光刻胶残留物洗去，然后，去除光刻胶去除区域对应的待图案化薄膜，对光刻胶部分保留区域3032的光刻胶进行灰化处理以去除光刻胶部分保留区域3032中的光刻胶以形成光刻胶图案。
所使用的上述掩模板例如可以为单缝衍射(SSM)掩模板，其包括如下图案：第一图案、与该第一图案配合形成U形狭缝的第二图案，以及连接于第一图案底部的延长部，该狭缝的宽度在1.9μm-2.4μm之间。该第一图案是指内部大致呈U形、用于与第二图案配合加工U形狭缝的图案，第一图案的形状并不特别限定，例如，该第一图案的外部并不限定为U形外轮廓。
例如，SSM掩模板是利用光的衍射原理，将沟槽位置的掩模缝隙做 得足够窄，使光只能通过衍射透过，从而降低该区域在光刻胶上的曝光量，形成半透膜。
S103：对该光刻胶图案进行热烘，使掩模板的延长部对应的光刻胶流动至掩模板的连接部和第二图案对应的区域之间。
例如，对该光刻胶图案进行热烘，使掩模板的延长部对应的光刻胶受热流动至掩模板的连接部和第二图案对应的区域之间，例如，连接部对应的光刻胶流至位置5处。
需要说明的是，在这一步骤中，光刻胶图案可以被烘烤至可以流动的温度，从而根据门栓效应，延长部形成“门栓”，掩模板的延长部对应的光刻胶流动至掩模板的连接部和第二图案对应的区域之间。掩模板的延长部对应的光刻胶流动至掩模板的连接部和第二图案对应的区域之间能够使得光刻胶在5位置处的厚度加厚，避免从U形槽的舌尖位置的缝隙5透过的衍射光较多而导致曝光后的光刻胶断裂的问题。
延长部的形状并不特别限制，只要是能够实现热烘后的光刻胶流动至第一图案底部，实现光刻胶的补偿即可。例如，对应于掩模板的延长部的光刻胶图案可以是长方形、椭圆形、锥形、水滴状、正方形、圆形、不规则形等均可。
S104：刻蚀光刻胶完全去除区域对应的部分待图案化薄膜。
S105：对光刻胶部分保留区域进行灰化处理，以去除光刻胶部分保留区域中的光刻胶。
例如，在步骤S105中，即将光刻胶部分保留区域中的光刻胶进行灰化处理，以去除光刻胶部分保留区域中的光刻胶，这样就节省了对光刻胶图案进行再曝光的过程，从而节省了生产成本。
如图7D所示，将光刻胶部分保留区域中的光刻胶去除了。
例如，掩模板中存在U形狭缝，该U形狭缝用于衍射。在灰化处理中之后，U形狭缝中的光刻胶层对应于衍射狭缝的材料被去除。
S106：刻蚀光刻胶部分保留区域对应的部分待图案化薄膜，以形成图案化膜层。
在步骤S106中，即将掩模板的缝隙对应的待图案化薄膜进行去除。
另外，实验证明，掩模板的延长部对应的光刻胶图案的宽度为掩模板 的连接部对应的光刻胶图案的宽度的1/10或1/5以上则补偿效果相对较优。即掩模板的延长部的宽度(指延长部在第一侧壁和第二侧壁的垂直方向上的宽度)为连接部的宽度(两个大致平行的侧壁之间的距离)的1/10以上或1/5以上，且1/2以下。
例如，通过蚀刻的方式对图案化膜层进行清洗，将光刻胶图案覆盖的图案化膜层予以保留，将光刻胶覆盖范围以外的图案化膜层去除，形成图案化膜层。该图案化膜层具有与光刻胶图案相应的图案，即该图案化膜层包括与掩模板的第一图案和第二图案对应的图案。
例如，在形成该图案化膜层之前，还包括：去除图案化膜层上对应于掩模板的延长部的材料。例如，可以继续利用光刻和蚀刻等方式对对应于延长部的待图案化薄膜进行去除。需要说明的是，由于所形成的延长部对应的图案化膜层属于dummy pattern，因此在不影响电路布置的前提下，同样可以不去除。
或者，在通过蚀刻形成图案化膜层的步骤之后，该方法还包括：去除图案化膜层上对应于掩模板的延长部的部分。
例如，可以继续利用光刻和蚀刻等方式去除图案化膜层上对应于掩模板的延长部的部分。
例如，该图案化膜层包括导电膜层、有机绝缘层和无机绝缘层。
本公开至少一实施例还提供一种薄膜晶体管的制备方法，包括：采用上述图案化膜层的制备方法形成图案化膜层。以下以图案化膜层为导电材料膜层为例加以说明。
表1为TFT结构的HT(光刻胶厚度)的测试结果，从表1可以看出，在导电图案没有导电延长部时，位置5的HT比位置1-4平均低
Figure PCTCN2018079958-appb-000001
左右，因此，这种SSM-TFT结构在量产过程中有光刻胶断开的风险。
Figure PCTCN2018079958-appb-000002
表1
通过上述内容可知，在薄膜晶体管的制备过程中，利用常规的制备方法需要避免的“门栓效应”，通过改进掩模板，在U形图案的舌尖位置增加了延长部，使得利用掩模板形成的光刻胶图案也具有延长部。在热烘的工序中，光刻胶图案的延长部会受热流动至光刻胶的U形图案的位置，保证了曝光后光刻胶的厚度，解决了目前存在的“U形槽的舌尖位置的缝隙的形貌同其他位置不同，导致该缝隙透过的衍射光较多，进而导致该区域的曝光量较大，曝光后的光刻胶较薄易断裂”的问题。
例如，该薄膜晶体管可以为底栅型的薄膜晶体管，也可以为顶栅型的薄膜晶体管，该薄膜晶体管包括栅极、栅绝缘层、有源层、第一源漏电极和第二源漏电极。
在本公开的一个实施例中，该薄膜晶体管可以是位于闸极驱动电路基板区域的薄膜晶体管，或者是位于显示区域的薄膜晶体管。
本公开至少一实施例提供的一种掩模板、图案化膜层的制备方法和薄膜晶体管的制备方法具有以下至少一项有益效果：
(1)本公开至少一实施例提供的掩模板，在第一图案的底部中央的位置增加了延长部，在采用正性光刻胶时，使得利用该掩模板形成的光刻胶的图案上也具有延长部，从而避免了“门栓效应”。
(2)本公开至少一实施例提供的掩模板，在对采用该掩模板形成的光刻胶图案进行热烘的工序中，掩模板的延长部对应的光刻胶会受热流动至掩模板的第一图案的底部和第二图案之间的间隙对应的区域中，从而保证了曝光后的光刻胶图案的完整性。
(3)本公开至少一实施例提供的掩模板，解决了掩模板的U形槽的舌尖位置的缝隙的形貌同其他位置的缝隙不同，导致的从舌尖位置的缝隙透过的衍射光较多，进而导致该区域的曝光量较大，曝光后该区域的光刻胶较薄，易于出现对应于掩模板的U形槽的舌尖位置处的光刻胶断开的问题。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域 的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种掩模板，包括：
    第一图案和第二图案；其中，
    所述第一图案包括第一侧壁、第二侧壁、连接所述第一侧壁和所述第二侧壁的连接部和位于所述连接部的远离所述第一侧壁一侧的延长部；
    所述第二图案位于所述第一侧壁和所述第二侧壁之间；
    所述第一图案和所述第二图案之间具有狭缝，所述狭缝为用于衍射的狭缝。
  2. 根据权利要求1所述的掩模板，其中，所述第一图案和所述第二图案均为多个，所述第一图案和所述第二图案一一对应。
  3. 根据权利要求2所述的掩模板，其中，多个所述第一图案相互连接。
  4. 根据权利要求2或3所述的掩模板，其中，所述延长部为多个，每个所述第一图案上都对应地设置有一个所述延长部。
  5. 根据权利要求1-4中任一项所述的掩模板，其中，所述延长部连接于所述连接部的中央。
  6. 根据权利要求5所述的掩模板，其中，所述延长部为L型结构。
  7. 根据权利要求1-6中任一项所述的掩模板，其中，所述第一侧壁和所述第二侧壁相互平行，所述延长部在垂直于所述第一侧壁和所述第二侧壁的方向上的宽度为所述第一侧壁和所述第二侧壁之间的距离的1/10-1/2。
  8. 根据权利要求1-7中任一项所述的掩模板，其中，所述狭缝的宽度在1.9μm-2.4μm之间。
  9. 根据权利要求8所述的掩模板，其中，所述狭缝的宽度在2.1μm-2.3μm之间。
  10. 一种图案化膜层的制备方法，包括：
    依次沉积待图案化薄膜和光刻胶薄膜；
    采用权利要求1-9中任一项所述的掩模板对所述光刻胶薄膜进行构图以形成光刻胶图案，其中，所述光刻胶图案包括光刻胶全保留区域、光刻 胶部分保留区域和光刻胶完全去除区域；
    对所述光刻胶图案进行热烘，使所述掩模板的延长部对应的光刻胶流动至掩模板的连接部和第二图案对应的区域之间；
    刻蚀所述光刻胶完全去除区域对应的部分所述待图案化薄膜；
    对所述光刻胶部分保留区域进行灰化处理，以去除所述光刻胶部分保留区域中的光刻胶；
    刻蚀所述光刻胶部分保留区域对应的部分所述待图案化薄膜，以形成所述图案化膜层。
  11. 根据权利要求10所述的制备方法，其中，所述光刻胶全保留区域对应于所述掩模板的所述第一图案和所述第二图案，所述光刻胶部分保留区域对应于所述掩模板的所述狭缝。
  12. 根据权利要求11所述的制备方法，其中，所述光刻胶部分保留区域中光刻胶的厚度为所述光刻胶全保留区域中光刻胶的厚度的1/4～1/2。
  13. 根据权利要求10-12中任一项所述的制备方法，其中，热烘之前所述光刻胶部分保留区域中的光刻胶具有厚度不同的第一部分和第二部分。
  14. 根据权利要求13所述的制备方法，其中，所述第一部分对应于所述掩模板的所述第一侧壁和所述第二图案之间的间隙、所述第二侧壁和所述第二图案之间的间隙；所述第二部分对应于所述掩模板的所述连接部和所述第二图案之间的间隙。
  15. 根据权利要求13或14所述的制备方法，其中，所述第一部分和所述第二部分的厚度差为50-100nm。
  16. 根据权利要求10-15中任一项所述的制备方法，其中，在形成所述图案化膜层之后，还包括：去除所述图案化膜层的对应于所述掩模板的延长部的部分。
  17. 根据权利要求10-16中任一项所述的制备方法，其中，所述图案化膜层包括导电膜层、有机绝缘层和无机绝缘层。
  18. 一种薄膜晶体管的制备方法，包括：采用权利要求10-17中任一项所述的制备方法形成图案化膜层。
PCT/CN2018/079958 2017-05-09 2018-03-22 掩模板、图案化膜层的制备方法和薄膜晶体管的制备方法 WO2018205752A1 (zh)

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