WO2018043008A1 - Procédé de fabrication de dispositif à semi-conducteur - Google Patents

Procédé de fabrication de dispositif à semi-conducteur Download PDF

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Publication number
WO2018043008A1
WO2018043008A1 PCT/JP2017/027956 JP2017027956W WO2018043008A1 WO 2018043008 A1 WO2018043008 A1 WO 2018043008A1 JP 2017027956 W JP2017027956 W JP 2017027956W WO 2018043008 A1 WO2018043008 A1 WO 2018043008A1
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WO
WIPO (PCT)
Prior art keywords
sealing body
manufacturing
semiconductor device
protective film
semiconductor
Prior art date
Application number
PCT/JP2017/027956
Other languages
English (en)
Japanese (ja)
Inventor
智則 篠田
拓 根本
勇人 中西
Original Assignee
リンテック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by リンテック株式会社 filed Critical リンテック株式会社
Priority to KR1020187035416A priority Critical patent/KR102385965B1/ko
Priority to JP2018537054A priority patent/JP7096766B2/ja
Priority to CN201780037693.3A priority patent/CN109463007B/zh
Priority to KR1020227010945A priority patent/KR102487681B1/ko
Publication of WO2018043008A1 publication Critical patent/WO2018043008A1/fr
Priority to JP2022096710A priority patent/JP7317187B2/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J201/00—Adhesives based on unspecified macromolecular compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device.
  • a semiconductor chip (sometimes simply referred to as a chip) may be mounted in a package close to its size. Such a package may be referred to as a chip scale package (CSP).
  • CSP chip scale package
  • WLP wafer level package
  • WLP Wafer level package
  • WLP before dicing a package into individual pieces, external electrodes and the like are formed on the chip circuit formation surface, and finally a package wafer including chips is diced into individual pieces.
  • WLP there are a fan-in type and a fan-out type.
  • a semiconductor chip sealing body is formed by covering a semiconductor chip with a sealing member so as to be an area larger than the chip size.
  • the rewiring layer and the external electrode are formed not only on the circuit surface of the semiconductor chip but also on the surface region of the sealing member.
  • Patent Document 1 describes a method for manufacturing WLP or the like using an adhesive tape for temporarily fixing a chip.
  • the chip is attached by a method of attaching the circuit surface of the chip toward the adhesive layer of the adhesive tape on the substrate (sometimes referred to as a face-down method). .
  • the adhesive tape and the substrate are peeled off from the layer formed by sealing the chip with the resin (sometimes referred to as a chip sealing layer) and exposed. Electrodes are formed on the circuit surface.
  • the chip sealing layer is not supported by the substrate when the electrodes are formed on the chip circuit surface, the stress of the chip sealing layer is caused by the stress accompanying the curing of the sealing resin. There is a risk of warping. When warping of the chip sealing layer occurs, it is difficult to form a rewiring layer and electrodes on the chip circuit surface.
  • An object of the present invention is to provide a method for manufacturing a semiconductor device capable of suppressing warpage of a sealing body.
  • a plurality of semiconductor elements having a circuit surface and an element back surface opposite to the circuit surface are provided on the pressure-sensitive adhesive layer of the support substrate having the pressure-sensitive adhesive layer.
  • the step of attaching the sealing body to the first support sheet and the first support sheet were attached. It is preferable that the method further includes a step of dividing the sealing body into pieces.
  • the method for manufacturing a semiconductor device after electrically connecting the semiconductor element and the external terminal electrode, before separating the support substrate from the sealing body, it is preferable that the method further includes a step of sticking the sealing body to the second support sheet, and sticking the external terminal electrode of the sealing body toward the second support sheet.
  • the sealing body is attached to the second support sheet, and the support substrate is peeled off from the sealing body, and then the exposed semiconductor element.
  • the protective film forming layer is preferably formed on the back surface of the element.
  • the method further includes a step of separating the sealing body attached to the second support sheet after forming the protective film. .
  • the step of peeling the sealing body from the second support sheet and attaching the sealant to the third support sheet after forming the protective film, the step of peeling the sealing body from the second support sheet and attaching the sealant to the third support sheet; It is preferable that the method further includes a step of separating the sealing body attached to the third support sheet.
  • a method for manufacturing a semiconductor device that can suppress warping of a sealing body can be provided.
  • FIG. 1C is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 1A, FIG. 1B, and FIG. 1C.
  • FIG. 1C is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 1A, FIG. 1B, and FIG. 1C.
  • FIG. 1C is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 1A, FIG. 1B, and FIG. 1C.
  • FIG. 1C is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 1A, FIG. 1B, and FIG. 1C.
  • FIG. 1C is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 1A, FIG. 1B, and FIG. 1C.
  • FIG. 1C is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 1A, FIG. 1B, and FIG. 1C.
  • FIG. 1C is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 1A, FIG. 1B, and FIG. 1C.
  • 2A, 2B, 2C and 2D are cross-sectional views for explaining the manufacturing method according to the first embodiment.
  • FIG. 2A, 2B, 2C and 2D are cross-sectional views for explaining the manufacturing method according to the first embodiment.
  • FIG. It is sectional drawing of the double-sided adhesive sheet used by 1st embodiment. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 2nd embodiment. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 2nd embodiment. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 2nd embodiment. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 2nd embodiment. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 3rd embodiment. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 3rd embodiment. It is sectional drawing explaining the manufacturing
  • the manufacturing method of the semiconductor device according to this embodiment is as follows: A plurality of semiconductor elements having a circuit surface and an element back surface opposite to the circuit surface are bonded to the pressure-sensitive adhesive layer of the support substrate having the pressure-sensitive adhesive layer, and the element back surface is directed to the pressure-sensitive adhesive layer.
  • Sealing the semiconductor element attached to the support substrate to form a sealing body Forming an external terminal electrode on the sealing body and electrically connecting the semiconductor element attached to the support substrate and the external terminal electrode; After electrically connecting the semiconductor element and the external terminal electrode, peeling the support substrate from the sealing body to expose the back surface of the semiconductor element; Forming a curable protective film forming layer on the exposed back surface of the semiconductor element; Curing the protective film forming layer to form a protective film; After forming the protective film, the step of sticking the sealing body to the first support sheet; Separating the sealing body adhered to the first support sheet.
  • FIG. 1 (FIGS. 1A, 1B, and 1C), FIG. 2 (FIGS. 2A, 2B, 2C, and 2D) and FIG. 3 (FIGS. 3A and 3B) illustrate a method for manufacturing a semiconductor device according to the present embodiment. It is a figure which shows an example.
  • FIG. 1A and 1B are schematic cross-sectional views illustrating a step of attaching a semiconductor chip CP as a semiconductor element to a support substrate 10 having an adhesive layer (sometimes referred to as a semiconductor chip attaching step). It is shown.
  • 1A shows one semiconductor chip CP, in the present embodiment, a plurality of semiconductor chips CP are attached to the adhesive layer as shown in FIG. 1B.
  • the semiconductor chips CP may be bonded one by one or a plurality of semiconductor chips CP may be bonded simultaneously.
  • the semiconductor chip CP is attached to the adhesive layer provided in the double-sided adhesive sheet 20 attached to the support substrate 10.
  • the double-sided pressure-sensitive adhesive sheet 20 has a base material 21, a first pressure-sensitive adhesive layer 22, and a second pressure-sensitive adhesive layer 23.
  • the base material 21 has a first base material surface 211 and a second base material surface 212 opposite to the first base material surface 211.
  • the first pressure-sensitive adhesive layer 22 is formed on the first base material surface 211.
  • the second pressure-sensitive adhesive layer 23 is formed on the second base material surface 212.
  • the semiconductor chip CP is attached to the first adhesive layer 22, and the second adhesive layer 23 is attached to the support substrate 10. As shown in FIG.
  • the semiconductor chip CP used in this embodiment has a circuit surface W1 provided with a connection terminal W3, and an element back surface W2 opposite to the circuit surface W1.
  • the element back surface W ⁇ b> 2 is attached to the first pressure-sensitive adhesive layer 22.
  • the method of attaching the first pressure-sensitive adhesive layer 22 with the circuit surface W1 facing upward may be referred to as a face-up method.
  • the first pressure-sensitive adhesive layer 22 contains a pressure-sensitive adhesive.
  • the pressure-sensitive adhesive contained in the first pressure-sensitive adhesive layer 22 is not particularly limited, and various types of pressure-sensitive adhesives can be applied to the first pressure-sensitive adhesive layer 22.
  • Examples of the pressure-sensitive adhesive contained in the first pressure-sensitive adhesive layer 22 include a pressure-sensitive adhesive selected from the group consisting of rubber-based, acrylic-based, silicone-based, polyester-based, urethane-based, and the like.
  • the kind of adhesive is selected in consideration of the use and the kind of adherend to be attached.
  • the energy ray polymerizable compound When the energy ray polymerizable compound is blended in the first pressure-sensitive adhesive layer 22, the energy ray polymerizable compound is cured by irradiating the first pressure-sensitive adhesive layer 22 with energy rays from the support substrate 10 side.
  • the energy beam polymerizable compound When the energy beam polymerizable compound is cured, the cohesive force of the first pressure-sensitive adhesive layer 22 is increased, the pressure-sensitive adhesive force between the first pressure-sensitive adhesive layer 22 and the semiconductor chip CP, and the first pressure-sensitive adhesive layer 22 The adhesive force with the sealing member can be reduced or eliminated.
  • the energy rays include ultraviolet rays (UV) and electron beams (EB), and ultraviolet rays are preferable.
  • the 1st adhesive layer 22 may contain the foaming agent which foams by heating.
  • the second pressure-sensitive adhesive layer 23 also contains a pressure-sensitive adhesive.
  • the pressure-sensitive adhesive contained in the second pressure-sensitive adhesive layer 23 is not particularly limited as long as it can fix the support substrate 10 and the double-sided pressure-sensitive adhesive sheet 20. It is preferable that the adhesive contained in the 2nd adhesive layer 23 is an adhesive which can peel the double-sided adhesive sheet 20 from the support substrate 10 as needed.
  • the support substrate 10 is a substrate for supporting the semiconductor chip CP and the sealing body.
  • the support substrate 10 is not particularly limited as long as it is made of a material that can support the semiconductor chip CP and the sealing body.
  • the support substrate 10 is preferably formed of a hard material. In the present embodiment, the support substrate 10 is preferably made of glass.
  • the support substrate 10 is preferably made of a hard plastic film.
  • FIG. 1C is a schematic cross-sectional view illustrating a process of sealing a plurality of semiconductor chips CP (sometimes referred to as a sealing process).
  • a method for sealing the plurality of semiconductor chips CP using the sealing member 30 is not particularly limited.
  • the sealing body 3 is formed by sealing with the sealing member 30 so that the circuit surface W1 side of the semiconductor chip CP is not covered with the sealing member 30.
  • a sealing member 30 is also filled between the plurality of semiconductor chips CP.
  • the material of the sealing member 30 is preferably made of a resin, and examples thereof include an epoxy resin.
  • the epoxy resin used as the sealing member 30 may include, for example, a phenol resin, an elastomer, an inorganic filler, a curing accelerator, and the like.
  • a liquid sealing resin can be used so that the circuit surface W1 side of the semiconductor chip CP is not covered with the sealing member 30.
  • You may implement the process it may call an additional hardening process which further hardens the sealing member 30 between a sealing process and the following process. In this step, a method of heating the sealing resin layer to promote curing is given as an example.
  • FIG. 2A is a schematic cross-sectional view illustrating a step of forming the rewiring layer 4 that is electrically connected to the semiconductor chip CP (sometimes referred to as a rewiring layer forming step).
  • the rewiring layer 4 and the connection terminal W3 exposed on the surface of the sealing body 3 are electrically connected.
  • the rewiring layer 4 is formed on the circuit surface W ⁇ b> 1 and the surface of the sealing body 3.
  • a method of forming the rewiring layer 4 a conventionally known method can be adopted.
  • the rewiring layer 4 has external electrode pads 41 for connecting external terminal electrodes. In the present embodiment, a plurality of external electrode pads 41 are formed on the surface side of the rewiring layer 4.
  • FIG. 2B shows a schematic cross-sectional view illustrating a step of connecting the external terminal electrode 5 to the rewiring layer 4 (sometimes referred to as an external terminal electrode connection step).
  • the semiconductor chip CP and the external terminal electrode 5 are electrically connected.
  • the external terminal electrode 5 such as a solder ball is placed on the external electrode pad 41, and the external terminal electrode 5 and the external electrode pad 41 are electrically connected by solder bonding or the like.
  • the material of the solder ball is not particularly limited. Examples of the material of the solder ball include lead-containing solder and lead-free solder.
  • FIG. 2C shows a schematic cross-sectional view illustrating a process of peeling the support substrate 10 from the sealing body 3 to expose the element back surface W2 of the semiconductor chip CP (sometimes referred to as a support board peeling process).
  • the method for peeling the support substrate 10 from the sealing body 3 is not particularly limited.
  • a method of a support substrate peeling process after peeling the support substrate 10 from the double-sided adhesive sheet 20, the method of peeling the double-sided adhesive sheet 20 from the sealing body 3 is mentioned.
  • the method of peeling the support substrate 10 and the double-sided adhesive sheet 20 integrally from the sealing body 3 is mentioned.
  • the energy ray polymerizable compound When the energy ray polymerizable compound is blended in the first pressure-sensitive adhesive layer 22, the energy ray polymerizable compound is cured by irradiating the first pressure-sensitive adhesive layer 22 with energy rays from the support substrate 10 side. When the energy ray polymerizable compound is cured, the cohesive force of the first pressure-sensitive adhesive layer 22 is increased, and the pressure-sensitive adhesive force between the first pressure-sensitive adhesive layer 22 and the sealing body 3 can be reduced or eliminated. .
  • the energy rays include ultraviolet rays (UV) and electron beams (EB), and ultraviolet rays are preferable.
  • the method for reducing or eliminating the adhesive force between the first pressure-sensitive adhesive layer 22 and the sealing body 3 is not limited to energy beam irradiation. Examples of the method for reducing or eliminating the adhesive strength include a method using heating, a method using heating and energy beam irradiation, and a method using cooling.
  • FIG. 2D is a schematic cross-sectional view illustrating a step of forming a curable protective film forming layer 60 on the element back surface W2 of the exposed semiconductor chip CP (sometimes referred to as a protective film forming layer forming step). ing.
  • the element back surface W2 is covered by forming the protective film forming layer 60 on the back surface (the surface opposite to the surface on which the rewiring layer 4 and the like are formed) of the sealing body 3.
  • the protective film forming layer 60 in the present embodiment for example, any one of thermosetting and energy ray curable protective film forming layers can be used.
  • the protective film forming layer 60 in this embodiment is preferably formed using a material containing a curable adhesive composition that is cured by receiving energy from the outside. More preferably, an adhesive sheet containing the curable adhesive composition is affixed to the back surface of the sealing body 3 to form the protective film forming layer 60 and cover the element back surface W2. Examples of the energy supplied from the outside include ultraviolet rays, electron beams, and heat.
  • the protective film forming layer 60 preferably contains at least one of an ultraviolet curable adhesive and a thermosetting adhesive.
  • the protective film forming layer 60 is also preferably a thermosetting layer containing a thermosetting adhesive, and is preferably an ultraviolet curable layer containing an ultraviolet curable adhesive.
  • First support sheet sticking step In FIG. 3A, after the protective film forming layer 60 is cured to form the protective film 60A, the sealing body 3 is attached to the first support sheet 70 to which the ring frame RF is attached (first step).
  • a schematic cross-sectional view for explaining (sometimes referred to as a support sheet sticking step) is shown.
  • the first support sheet 70 in the present embodiment is preferably a dicing sheet used in the manufacturing process of the semiconductor device. It is preferable that the 1st support sheet 70 as a dicing sheet has a base film and an adhesive layer.
  • the sealing body 3 is adhered to the first support sheet 70 with the protective film 60 ⁇ / b> A facing the pressure-sensitive adhesive layer of the first support sheet 70.
  • the ring frame RF is placed on the adhesive layer of the first support sheet 70, the ring frame RF is lightly pressed, and the ring frame RF and the first support sheet 70 are fixed. Thereafter, the pressure-sensitive adhesive layer exposed inside the ring shape of the ring frame RF is pressed against the protective film 60 ⁇ / b> A of the sealing body 3 to fix the sealing body 3 to the first support sheet 70.
  • FIG. 3B shows a schematic cross-sectional view illustrating a step of dividing the sealing body 3 adhered to the first support sheet 70 (sometimes referred to as an individualization step).
  • the sealing body 3 is separated into individual semiconductor chips CP.
  • the method for dividing the sealing body 3 into individual pieces is not particularly limited. Examples of the method of dividing into pieces include a method of dividing into pieces using a cutting means such as a dicing saw, and a laser irradiation method.
  • the semiconductor device manufacturing method of the present embodiment preferably includes a step of mounting the semiconductor package 1 on a printed wiring board or the like (sometimes referred to as a mounting step).
  • the semiconductor package 1 is picked up from the first support sheet 70 with the protective film 60A attached to the element back surface W2.
  • the rewiring layer forming step and the external terminal electrode connecting step can be performed while the sealing body 3 is supported by the support substrate 10. If the sealing body is warped, the surface of the sealing body is curved and it is difficult to form the rewiring layer and the external terminal electrode. However, since the warping of the sealing body 3 is suppressed, a plurality of the sealing bodies 3 The rewiring layer 4 and the external terminal electrode 5 can be formed with high accuracy on the semiconductor chip CP.
  • the handleability of the sealing body 3 improves.
  • the method for manufacturing a semiconductor element according to this embodiment is effective.
  • the manufacturing method of the semiconductor device according to this embodiment is as follows: A plurality of semiconductor elements having a circuit surface and an element back surface opposite to the circuit surface are bonded to the pressure-sensitive adhesive layer of the support substrate having the pressure-sensitive adhesive layer, and the element back surface is directed to the pressure-sensitive adhesive layer.
  • Sealing the semiconductor element attached to the support substrate to form a sealing body Forming an external terminal electrode on the sealing body and electrically connecting the semiconductor element attached to the support substrate and the external terminal electrode; After electrically connecting the semiconductor element and the external terminal electrode, the step of attaching the sealing body to the second support sheet; After pasting the sealing body to the second support sheet, peeling the support substrate from the sealing body to expose the back surface of the semiconductor element; Forming a curable protective film forming layer on the exposed back surface of the semiconductor element; Curing the protective film forming layer to form a protective film; Separating the sealing body adhered to the second support sheet.
  • the sealing body is attached to the second support sheet with the external terminal electrode facing the second support sheet.
  • the same processes as those from the semiconductor chip attaching process to the external terminal electrode connecting process of the first embodiment are performed.
  • the semiconductor device manufacturing method according to the present embodiment is mainly different from the first embodiment in the step after the external terminal electrode connecting step. Since the second embodiment is the same as the first embodiment in other points, the description is omitted or simplified.
  • FIG. 5 is a diagram showing an example of a method for manufacturing a semiconductor device according to the present embodiment.
  • FIG. 5A After the external terminal electrode 5 is electrically connected to the semiconductor chip CP and before the supporting substrate 10 is peeled from the sealing body 3, the sealing body 3 is removed from the second supporting sheet 71.
  • the cross-sectional schematic explaining the process (it may be called a 2nd support sheet sticking process) attached to is shown.
  • the sealing body 3 supported by the support substrate 10 is attached to the second support sheet 71.
  • the sealing body 3 is adhered with the external terminal electrode 5 facing the second support sheet 71.
  • the 2nd support sheet 71 has a base film and an adhesive layer.
  • the sealing body 3 it is preferable to support the sealing body 3 on the second support sheet 71 to which the ring frame RF is attached.
  • the 2nd support sheet 71 is a dicing sheet used in the manufacturing process of a semiconductor device.
  • the support substrate 10 is peeled from the sealing body 3 to expose the element back surface W2 of the semiconductor chip CP (support substrate peeling process).
  • the method of peeling the support substrate 10 from the sealing body 3 is not specifically limited.
  • the method described in the first embodiment can be adopted.
  • the method of peeling the support substrate peeling process of this embodiment after peeling the support substrate 10 from the double-sided adhesive sheet 20, the method of peeling the double-sided adhesive sheet 20 from the sealing body 3 is mentioned.
  • the method of peeling the support substrate 10 and the double-sided adhesive sheet 20 integrally from the sealing body 3 is mentioned.
  • FIG. 5C shows a schematic cross-sectional view illustrating a step of forming a curable protective film forming layer 60 on the element back surface W2 of the exposed semiconductor chip CP (protective film forming layer forming step).
  • the protective film forming layer 60 is formed on the sealing body 3 supported by the second support sheet 71.
  • the element back surface W2 is covered by forming a protective film forming layer 60 on the back surface (surface opposite to the surface on which the rewiring layer 4 and the like are formed) side of the sealing body 3.
  • the formation method of the protective film formation layer 60 of this embodiment is the same as that of the protective film formation layer 60 of 1st embodiment.
  • the protective film forming layer 60 contains a thermosetting adhesive because generation of residual stress at the time of thermosetting and adhesive residue can be suppressed.
  • a thermosetting layer is preferred.
  • the protective film forming layer 60 is also preferably an ultraviolet curable layer containing an ultraviolet curable adhesive. Also in this embodiment, the process (protective film formation process) which hardens the protective film formation layer 60 of the sealing body 3 supported by the 2nd support sheet 71, and forms protective film 60A (refer FIG. 5D) is implemented. To do.
  • the method for curing the protective film forming layer 60 is the same as in the first embodiment.
  • FIG. 5D shows a schematic cross-sectional view for explaining a process of separating the sealing body 3 adhered to the second support sheet 71 (individualization process). Also in this embodiment, the sealing body 3 is separated into pieces like the first embodiment. By separating the sealing body 3 into individual pieces, the semiconductor package 1 as a semiconductor device is manufactured.
  • the semiconductor device manufacturing method of the present embodiment preferably includes a step of mounting the semiconductor package 1 on a printed wiring board or the like (sometimes referred to as a mounting step).
  • the semiconductor package 1 is picked up from the second support sheet 71 with the protective film 60A attached to the element back surface W2.
  • the manufacturing method of the semiconductor device according to this embodiment is as follows: A plurality of semiconductor elements having a circuit surface and an element back surface opposite to the circuit surface are bonded to the pressure-sensitive adhesive layer of the support substrate having the pressure-sensitive adhesive layer, and the element back surface is directed to the pressure-sensitive adhesive layer.
  • Sealing the semiconductor element attached to the support substrate to form a sealing body Forming an external terminal electrode on the sealing body and electrically connecting the semiconductor element attached to the support substrate and the external terminal electrode; After electrically connecting the semiconductor element and the external terminal electrode, the step of attaching the sealing body to the second support sheet; After pasting the sealing body to the second support sheet, peeling the support substrate from the sealing body to expose the back surface of the semiconductor element; Forming a curable protective film forming layer on the exposed back surface of the semiconductor element; Curing the protective film forming layer to form a protective film; After forming the protective film, the step of peeling the sealing body from the second support sheet and sticking to the third support sheet; Separating the sealing body stuck to the third support sheet.
  • the sealing body is attached to the second support sheet, the sealing body is attached with the external terminal electrode facing the second support sheet.
  • the sealing body is attached to the third support sheet, the sealing body is attached with the protective film facing the third support sheet.
  • the same processes as those from the semiconductor chip attaching process to the external terminal electrode connecting process of the first embodiment are performed.
  • the same steps as those from the second support sheet attaching step to the protective film forming step of the second embodiment are performed.
  • the manufacturing method of the semiconductor device according to this embodiment is mainly different from the first embodiment and the second embodiment in the process after the protective film forming process. Since the third embodiment is the same as the first embodiment and the second embodiment in other points, the description is omitted or simplified.
  • FIG. 6 is a diagram showing an example of a method for manufacturing a semiconductor device according to the present embodiment.
  • the sealing body 3 is peeled from the second support sheet 71 and attached to the third support sheet 72 (a third support sheet attaching process and A schematic cross-sectional view is shown to explain.
  • the third support sheet attaching step the sealing body 3 on which the protective film 60 ⁇ / b> A is formed is attached to the third support sheet 72.
  • the sealing body 3 is stuck with the protective film 60 ⁇ / b> A facing the third support sheet 72.
  • the third support sheet 72 in the present embodiment is also preferably a dicing sheet used in the manufacturing process of the semiconductor device. Also in this embodiment, it is preferable to support the sealing body 3 on the third support sheet 72 to which the ring frame RF2 is attached.
  • FIG. 6B shows a schematic cross-sectional view illustrating a step of separating the sealing body 3 adhered to the third support sheet 72 (single step). Also in this embodiment, the sealing body 3 is separated into pieces like the first embodiment. By separating the sealing body 3 into individual pieces, the semiconductor package 1 as a semiconductor device is manufactured.
  • the semiconductor device manufacturing method of the present embodiment preferably includes a step of mounting the semiconductor package 1 on a printed wiring board or the like (sometimes referred to as a mounting step).
  • the semiconductor package 1 is picked up from the third support sheet 72 with the protective film 60A attached to the element back surface W2.
  • the support substrate peeling step can be performed on the sealing body 3 supported by the second support sheet 71. It becomes easy to peel from. Furthermore, also in this embodiment, since the sealing body 3 after peeling the support substrate 10 is supported by the second support sheet 71 as in the second embodiment, the protective film forming layer forming step is performed. Easy to do. According to this embodiment, even when the second support sheet 71 does not have the characteristics as a dicing sheet, sealing is performed by sticking the sealing body 3 to the third support sheet 72 as a dicing sheet.
  • the semiconductor package 1 can be obtained by dividing the body 3 into individual pieces.
  • the present invention is not limited to the embodiment.
  • the present invention includes a modification of the above-described embodiment as long as the object of the present invention can be achieved.
  • a step of performing laser printing on the protective film may be performed.
  • Laser printing is performed by a laser marking method, and the surface of the protective film is scraped off by laser light irradiation to mark a product number or the like on the protective film.
  • the protective film may be directly irradiated with laser light, or laser light may be irradiated through the support sheet.
  • the laser printing step is after forming the protective film, and from the step of separating the sealing body attached to the support sheet. It is preferable to carry out before.
  • the warping of the sealing body can be suppressed. Therefore, when the laser printing process is performed, the focal point of the laser beam is accurately determined and marking can be performed with high accuracy.
  • the sealing body is exposed between the supporting substrate peeling step and the protective film forming layer forming step.
  • You may implement the process it may call a sealing body grinding process which grinds the element back surface side. By performing this grinding process, the thickness of the sealing body can be reduced, and the semiconductor device can be reduced in thickness.
  • a protective film forming layer is formed on the ground surface of the sealing body.
  • the double-sided adhesive sheet 20 was affixed on the support substrate 10 and the semiconductor chip CP was affixed and demonstrated to the 1st adhesive layer 22 which the double-sided adhesive sheet 20 has mentioned as an example, this embodiment was demonstrated.
  • the invention is not limited to such an embodiment.
  • an adhesive layer is formed on the surface of the support substrate, and the semiconductor element is formed on the adhesive layer. You may make it stick.
  • the pressure-sensitive adhesive layer preferably contains the same pressure-sensitive adhesive as the first pressure-sensitive adhesive layer 22.
  • the method for sealing the plurality of semiconductor chips CP using the sealing member is not limited to the method described in the embodiment.
  • a plurality of semiconductor chips CP supported by the support substrate 10 are mounted in a mold.
  • a method may be employed in which a sealing resin material having fluidity is poured into a mold and the sealing resin material is heated and cured to form a sealing resin layer.
  • the sheet-shaped sealing resin is covered with the circuit surfaces W1 of the plurality of semiconductor chips CP.
  • a method may be employed in which the sealing resin layer is formed by placing the sheet-shaped sealing resin so as to cover the semiconductor chip CP, and heating and curing the sealing resin.
  • the sealing resin layer is formed by placing the sheet-shaped sealing resin so as to cover the semiconductor chip CP, and heating and curing the sealing resin.
  • the sealing member 30 may cover the circuit surface W1 side of the semiconductor chip CP.
  • a step of exposing the connection terminal W3 of the semiconductor chip CP on the surface of the sealing body 3 (sometimes referred to as a connection terminal exposure step) is performed.
  • this connection terminal exposing step the connection terminal W3 is exposed by removing a part or the whole of the sealing resin layer on the surface side of the sealing body 3 covering the circuit surface W1 and the connection terminal W3 of the semiconductor chip CP.
  • the method for exposing the connection terminal W3 of the semiconductor chip CP is not particularly limited.
  • connection terminal W3 of the semiconductor chip CP for example, a method of grinding the sealing resin layer to expose the connection terminal W3, or removing the sealing resin layer by a method such as laser irradiation to remove the connection terminal W3.
  • a method of exposing and a method of exposing the connection terminal W3 by removing the sealing resin layer by an etching method include a method of exposing and a method of exposing the connection terminal W3 by removing the sealing resin layer by an etching method. If the connection terminal W3 can be electrically connected to the rewiring layer 4 and the external terminal electrode 5, the entire connection terminal W3 may be exposed or a part of the connection terminal W3 may be exposed. .
  • the semiconductor package is not limited to the embodiment described in the embodiment and the modification of the embodiment.
  • An FO-WLP type semiconductor package in which an external electrode pad is fanned out outside the region of the semiconductor element in the sealing body and an external terminal electrode is connected to the external electrode pad may be used.
  • a semiconductor package including a plurality of semiconductor elements may be manufactured by separating the sealing body so as to include a plurality of semiconductor elements.
  • SYMBOLS 1 Semiconductor package (semiconductor device), 3 ... Sealing body, 5 ... External terminal electrode, 10 ... Support substrate, 22 ... 1st adhesive layer (adhesive layer), 30 ... Sealing member, 60 ... Protective film Forming layer, 60A ... protective film, 70 ... first support sheet, 71 ... second support sheet, 72 ... third support sheet, CP ... semiconductor chip (semiconductor element), W1 ... circuit surface, W2 ... element back surface , W3... Connection terminal.

Abstract

L'invention concerne un procédé de fabrication de dispositif à semi-conducteur caractérisé en ce qu'il comprend : une étape consistant à faire adhérer une pluralité d'éléments semi-conducteurs, chacun ayant une surface de circuit (W1) et une surface arrière d'élément (W2), à une couche adhésive d'un substrat de support (10) ayant la couche adhésive en ayant la surface arrière d'élément (W2) face à la couche adhésive; une étape de formation d'un corps d'étanchéité (3) en scellant les éléments semi-conducteurs collés au substrat de support (10); une étape consistant à former une électrode de borne externe sur le corps d'étanchéité (3), et se connectant électriquement l'une à l'autre l'électrode de borne externe et les éléments semi-conducteurs collés au substrat de support (10); une étape consistant à peler le substrat de support (10) à partir du corps d'étanchéité (3) après la connexion électrique des éléments semi-conducteurs et de l'électrode de borne externe l'un à l'autre, et l'exposition de la surface arrière d'élément (W2) de chacun des éléments semi-conducteurs; une étape consistant à former une couche de formation de film de protection durcissable sur la surface arrière de l'élément exposé (W2) de chacun des éléments semi-conducteurs; et une étape de formation d'un film de protection par durcissement de la couche de formation de film de protection.
PCT/JP2017/027956 2016-08-31 2017-08-02 Procédé de fabrication de dispositif à semi-conducteur WO2018043008A1 (fr)

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KR1020187035416A KR102385965B1 (ko) 2016-08-31 2017-08-02 반도체 장치의 제조 방법
JP2018537054A JP7096766B2 (ja) 2016-08-31 2017-08-02 半導体装置の製造方法
CN201780037693.3A CN109463007B (zh) 2016-08-31 2017-08-02 半导体装置的制造方法
KR1020227010945A KR102487681B1 (ko) 2016-08-31 2017-08-02 반도체 장치의 제조 방법
JP2022096710A JP7317187B2 (ja) 2016-08-31 2022-06-15 半導体装置の製造方法

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JP2016-169152 2016-08-31

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KR20220045255A (ko) 2022-04-12
JP7096766B2 (ja) 2022-07-06
JP2022123045A (ja) 2022-08-23
KR102385965B1 (ko) 2022-04-12
KR20190045091A (ko) 2019-05-02
TW202137340A (zh) 2021-10-01
KR102487681B1 (ko) 2023-01-11
JPWO2018043008A1 (ja) 2019-06-24
CN109463007B (zh) 2022-11-08
CN109463007A (zh) 2019-03-12

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