WO2018043008A1 - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
WO2018043008A1
WO2018043008A1 PCT/JP2017/027956 JP2017027956W WO2018043008A1 WO 2018043008 A1 WO2018043008 A1 WO 2018043008A1 JP 2017027956 W JP2017027956 W JP 2017027956W WO 2018043008 A1 WO2018043008 A1 WO 2018043008A1
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WO
WIPO (PCT)
Prior art keywords
sealing body
manufacturing
semiconductor device
protective film
semiconductor
Prior art date
Application number
PCT/JP2017/027956
Other languages
French (fr)
Japanese (ja)
Inventor
智則 篠田
拓 根本
勇人 中西
Original Assignee
リンテック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by リンテック株式会社 filed Critical リンテック株式会社
Priority to KR1020227010945A priority Critical patent/KR102487681B1/en
Priority to KR1020187035416A priority patent/KR102385965B1/en
Priority to JP2018537054A priority patent/JP7096766B2/en
Priority to CN201780037693.3A priority patent/CN109463007B/en
Publication of WO2018043008A1 publication Critical patent/WO2018043008A1/en
Priority to JP2022096710A priority patent/JP7317187B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J201/00—Adhesives based on unspecified macromolecular compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device.
  • a semiconductor chip (sometimes simply referred to as a chip) may be mounted in a package close to its size. Such a package may be referred to as a chip scale package (CSP).
  • CSP chip scale package
  • WLP wafer level package
  • WLP Wafer level package
  • WLP before dicing a package into individual pieces, external electrodes and the like are formed on the chip circuit formation surface, and finally a package wafer including chips is diced into individual pieces.
  • WLP there are a fan-in type and a fan-out type.
  • a semiconductor chip sealing body is formed by covering a semiconductor chip with a sealing member so as to be an area larger than the chip size.
  • the rewiring layer and the external electrode are formed not only on the circuit surface of the semiconductor chip but also on the surface region of the sealing member.
  • Patent Document 1 describes a method for manufacturing WLP or the like using an adhesive tape for temporarily fixing a chip.
  • the chip is attached by a method of attaching the circuit surface of the chip toward the adhesive layer of the adhesive tape on the substrate (sometimes referred to as a face-down method). .
  • the adhesive tape and the substrate are peeled off from the layer formed by sealing the chip with the resin (sometimes referred to as a chip sealing layer) and exposed. Electrodes are formed on the circuit surface.
  • the chip sealing layer is not supported by the substrate when the electrodes are formed on the chip circuit surface, the stress of the chip sealing layer is caused by the stress accompanying the curing of the sealing resin. There is a risk of warping. When warping of the chip sealing layer occurs, it is difficult to form a rewiring layer and electrodes on the chip circuit surface.
  • An object of the present invention is to provide a method for manufacturing a semiconductor device capable of suppressing warpage of a sealing body.
  • a plurality of semiconductor elements having a circuit surface and an element back surface opposite to the circuit surface are provided on the pressure-sensitive adhesive layer of the support substrate having the pressure-sensitive adhesive layer.
  • the step of attaching the sealing body to the first support sheet and the first support sheet were attached. It is preferable that the method further includes a step of dividing the sealing body into pieces.
  • the method for manufacturing a semiconductor device after electrically connecting the semiconductor element and the external terminal electrode, before separating the support substrate from the sealing body, it is preferable that the method further includes a step of sticking the sealing body to the second support sheet, and sticking the external terminal electrode of the sealing body toward the second support sheet.
  • the sealing body is attached to the second support sheet, and the support substrate is peeled off from the sealing body, and then the exposed semiconductor element.
  • the protective film forming layer is preferably formed on the back surface of the element.
  • the method further includes a step of separating the sealing body attached to the second support sheet after forming the protective film. .
  • the step of peeling the sealing body from the second support sheet and attaching the sealant to the third support sheet after forming the protective film, the step of peeling the sealing body from the second support sheet and attaching the sealant to the third support sheet; It is preferable that the method further includes a step of separating the sealing body attached to the third support sheet.
  • a method for manufacturing a semiconductor device that can suppress warping of a sealing body can be provided.
  • FIG. 1C is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 1A, FIG. 1B, and FIG. 1C.
  • FIG. 1C is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 1A, FIG. 1B, and FIG. 1C.
  • FIG. 1C is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 1A, FIG. 1B, and FIG. 1C.
  • FIG. 1C is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 1A, FIG. 1B, and FIG. 1C.
  • FIG. 1C is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 1A, FIG. 1B, and FIG. 1C.
  • FIG. 1C is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 1A, FIG. 1B, and FIG. 1C.
  • FIG. 1C is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 1A, FIG. 1B, and FIG. 1C.
  • 2A, 2B, 2C and 2D are cross-sectional views for explaining the manufacturing method according to the first embodiment.
  • FIG. 2A, 2B, 2C and 2D are cross-sectional views for explaining the manufacturing method according to the first embodiment.
  • FIG. It is sectional drawing of the double-sided adhesive sheet used by 1st embodiment. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 2nd embodiment. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 2nd embodiment. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 2nd embodiment. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 2nd embodiment. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 3rd embodiment. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 3rd embodiment. It is sectional drawing explaining the manufacturing
  • the manufacturing method of the semiconductor device according to this embodiment is as follows: A plurality of semiconductor elements having a circuit surface and an element back surface opposite to the circuit surface are bonded to the pressure-sensitive adhesive layer of the support substrate having the pressure-sensitive adhesive layer, and the element back surface is directed to the pressure-sensitive adhesive layer.
  • Sealing the semiconductor element attached to the support substrate to form a sealing body Forming an external terminal electrode on the sealing body and electrically connecting the semiconductor element attached to the support substrate and the external terminal electrode; After electrically connecting the semiconductor element and the external terminal electrode, peeling the support substrate from the sealing body to expose the back surface of the semiconductor element; Forming a curable protective film forming layer on the exposed back surface of the semiconductor element; Curing the protective film forming layer to form a protective film; After forming the protective film, the step of sticking the sealing body to the first support sheet; Separating the sealing body adhered to the first support sheet.
  • FIG. 1 (FIGS. 1A, 1B, and 1C), FIG. 2 (FIGS. 2A, 2B, 2C, and 2D) and FIG. 3 (FIGS. 3A and 3B) illustrate a method for manufacturing a semiconductor device according to the present embodiment. It is a figure which shows an example.
  • FIG. 1A and 1B are schematic cross-sectional views illustrating a step of attaching a semiconductor chip CP as a semiconductor element to a support substrate 10 having an adhesive layer (sometimes referred to as a semiconductor chip attaching step). It is shown.
  • 1A shows one semiconductor chip CP, in the present embodiment, a plurality of semiconductor chips CP are attached to the adhesive layer as shown in FIG. 1B.
  • the semiconductor chips CP may be bonded one by one or a plurality of semiconductor chips CP may be bonded simultaneously.
  • the semiconductor chip CP is attached to the adhesive layer provided in the double-sided adhesive sheet 20 attached to the support substrate 10.
  • the double-sided pressure-sensitive adhesive sheet 20 has a base material 21, a first pressure-sensitive adhesive layer 22, and a second pressure-sensitive adhesive layer 23.
  • the base material 21 has a first base material surface 211 and a second base material surface 212 opposite to the first base material surface 211.
  • the first pressure-sensitive adhesive layer 22 is formed on the first base material surface 211.
  • the second pressure-sensitive adhesive layer 23 is formed on the second base material surface 212.
  • the semiconductor chip CP is attached to the first adhesive layer 22, and the second adhesive layer 23 is attached to the support substrate 10. As shown in FIG.
  • the semiconductor chip CP used in this embodiment has a circuit surface W1 provided with a connection terminal W3, and an element back surface W2 opposite to the circuit surface W1.
  • the element back surface W ⁇ b> 2 is attached to the first pressure-sensitive adhesive layer 22.
  • the method of attaching the first pressure-sensitive adhesive layer 22 with the circuit surface W1 facing upward may be referred to as a face-up method.
  • the first pressure-sensitive adhesive layer 22 contains a pressure-sensitive adhesive.
  • the pressure-sensitive adhesive contained in the first pressure-sensitive adhesive layer 22 is not particularly limited, and various types of pressure-sensitive adhesives can be applied to the first pressure-sensitive adhesive layer 22.
  • Examples of the pressure-sensitive adhesive contained in the first pressure-sensitive adhesive layer 22 include a pressure-sensitive adhesive selected from the group consisting of rubber-based, acrylic-based, silicone-based, polyester-based, urethane-based, and the like.
  • the kind of adhesive is selected in consideration of the use and the kind of adherend to be attached.
  • the energy ray polymerizable compound When the energy ray polymerizable compound is blended in the first pressure-sensitive adhesive layer 22, the energy ray polymerizable compound is cured by irradiating the first pressure-sensitive adhesive layer 22 with energy rays from the support substrate 10 side.
  • the energy beam polymerizable compound When the energy beam polymerizable compound is cured, the cohesive force of the first pressure-sensitive adhesive layer 22 is increased, the pressure-sensitive adhesive force between the first pressure-sensitive adhesive layer 22 and the semiconductor chip CP, and the first pressure-sensitive adhesive layer 22 The adhesive force with the sealing member can be reduced or eliminated.
  • the energy rays include ultraviolet rays (UV) and electron beams (EB), and ultraviolet rays are preferable.
  • the 1st adhesive layer 22 may contain the foaming agent which foams by heating.
  • the second pressure-sensitive adhesive layer 23 also contains a pressure-sensitive adhesive.
  • the pressure-sensitive adhesive contained in the second pressure-sensitive adhesive layer 23 is not particularly limited as long as it can fix the support substrate 10 and the double-sided pressure-sensitive adhesive sheet 20. It is preferable that the adhesive contained in the 2nd adhesive layer 23 is an adhesive which can peel the double-sided adhesive sheet 20 from the support substrate 10 as needed.
  • the support substrate 10 is a substrate for supporting the semiconductor chip CP and the sealing body.
  • the support substrate 10 is not particularly limited as long as it is made of a material that can support the semiconductor chip CP and the sealing body.
  • the support substrate 10 is preferably formed of a hard material. In the present embodiment, the support substrate 10 is preferably made of glass.
  • the support substrate 10 is preferably made of a hard plastic film.
  • FIG. 1C is a schematic cross-sectional view illustrating a process of sealing a plurality of semiconductor chips CP (sometimes referred to as a sealing process).
  • a method for sealing the plurality of semiconductor chips CP using the sealing member 30 is not particularly limited.
  • the sealing body 3 is formed by sealing with the sealing member 30 so that the circuit surface W1 side of the semiconductor chip CP is not covered with the sealing member 30.
  • a sealing member 30 is also filled between the plurality of semiconductor chips CP.
  • the material of the sealing member 30 is preferably made of a resin, and examples thereof include an epoxy resin.
  • the epoxy resin used as the sealing member 30 may include, for example, a phenol resin, an elastomer, an inorganic filler, a curing accelerator, and the like.
  • a liquid sealing resin can be used so that the circuit surface W1 side of the semiconductor chip CP is not covered with the sealing member 30.
  • You may implement the process it may call an additional hardening process which further hardens the sealing member 30 between a sealing process and the following process. In this step, a method of heating the sealing resin layer to promote curing is given as an example.
  • FIG. 2A is a schematic cross-sectional view illustrating a step of forming the rewiring layer 4 that is electrically connected to the semiconductor chip CP (sometimes referred to as a rewiring layer forming step).
  • the rewiring layer 4 and the connection terminal W3 exposed on the surface of the sealing body 3 are electrically connected.
  • the rewiring layer 4 is formed on the circuit surface W ⁇ b> 1 and the surface of the sealing body 3.
  • a method of forming the rewiring layer 4 a conventionally known method can be adopted.
  • the rewiring layer 4 has external electrode pads 41 for connecting external terminal electrodes. In the present embodiment, a plurality of external electrode pads 41 are formed on the surface side of the rewiring layer 4.
  • FIG. 2B shows a schematic cross-sectional view illustrating a step of connecting the external terminal electrode 5 to the rewiring layer 4 (sometimes referred to as an external terminal electrode connection step).
  • the semiconductor chip CP and the external terminal electrode 5 are electrically connected.
  • the external terminal electrode 5 such as a solder ball is placed on the external electrode pad 41, and the external terminal electrode 5 and the external electrode pad 41 are electrically connected by solder bonding or the like.
  • the material of the solder ball is not particularly limited. Examples of the material of the solder ball include lead-containing solder and lead-free solder.
  • FIG. 2C shows a schematic cross-sectional view illustrating a process of peeling the support substrate 10 from the sealing body 3 to expose the element back surface W2 of the semiconductor chip CP (sometimes referred to as a support board peeling process).
  • the method for peeling the support substrate 10 from the sealing body 3 is not particularly limited.
  • a method of a support substrate peeling process after peeling the support substrate 10 from the double-sided adhesive sheet 20, the method of peeling the double-sided adhesive sheet 20 from the sealing body 3 is mentioned.
  • the method of peeling the support substrate 10 and the double-sided adhesive sheet 20 integrally from the sealing body 3 is mentioned.
  • the energy ray polymerizable compound When the energy ray polymerizable compound is blended in the first pressure-sensitive adhesive layer 22, the energy ray polymerizable compound is cured by irradiating the first pressure-sensitive adhesive layer 22 with energy rays from the support substrate 10 side. When the energy ray polymerizable compound is cured, the cohesive force of the first pressure-sensitive adhesive layer 22 is increased, and the pressure-sensitive adhesive force between the first pressure-sensitive adhesive layer 22 and the sealing body 3 can be reduced or eliminated. .
  • the energy rays include ultraviolet rays (UV) and electron beams (EB), and ultraviolet rays are preferable.
  • the method for reducing or eliminating the adhesive force between the first pressure-sensitive adhesive layer 22 and the sealing body 3 is not limited to energy beam irradiation. Examples of the method for reducing or eliminating the adhesive strength include a method using heating, a method using heating and energy beam irradiation, and a method using cooling.
  • FIG. 2D is a schematic cross-sectional view illustrating a step of forming a curable protective film forming layer 60 on the element back surface W2 of the exposed semiconductor chip CP (sometimes referred to as a protective film forming layer forming step). ing.
  • the element back surface W2 is covered by forming the protective film forming layer 60 on the back surface (the surface opposite to the surface on which the rewiring layer 4 and the like are formed) of the sealing body 3.
  • the protective film forming layer 60 in the present embodiment for example, any one of thermosetting and energy ray curable protective film forming layers can be used.
  • the protective film forming layer 60 in this embodiment is preferably formed using a material containing a curable adhesive composition that is cured by receiving energy from the outside. More preferably, an adhesive sheet containing the curable adhesive composition is affixed to the back surface of the sealing body 3 to form the protective film forming layer 60 and cover the element back surface W2. Examples of the energy supplied from the outside include ultraviolet rays, electron beams, and heat.
  • the protective film forming layer 60 preferably contains at least one of an ultraviolet curable adhesive and a thermosetting adhesive.
  • the protective film forming layer 60 is also preferably a thermosetting layer containing a thermosetting adhesive, and is preferably an ultraviolet curable layer containing an ultraviolet curable adhesive.
  • First support sheet sticking step In FIG. 3A, after the protective film forming layer 60 is cured to form the protective film 60A, the sealing body 3 is attached to the first support sheet 70 to which the ring frame RF is attached (first step).
  • a schematic cross-sectional view for explaining (sometimes referred to as a support sheet sticking step) is shown.
  • the first support sheet 70 in the present embodiment is preferably a dicing sheet used in the manufacturing process of the semiconductor device. It is preferable that the 1st support sheet 70 as a dicing sheet has a base film and an adhesive layer.
  • the sealing body 3 is adhered to the first support sheet 70 with the protective film 60 ⁇ / b> A facing the pressure-sensitive adhesive layer of the first support sheet 70.
  • the ring frame RF is placed on the adhesive layer of the first support sheet 70, the ring frame RF is lightly pressed, and the ring frame RF and the first support sheet 70 are fixed. Thereafter, the pressure-sensitive adhesive layer exposed inside the ring shape of the ring frame RF is pressed against the protective film 60 ⁇ / b> A of the sealing body 3 to fix the sealing body 3 to the first support sheet 70.
  • FIG. 3B shows a schematic cross-sectional view illustrating a step of dividing the sealing body 3 adhered to the first support sheet 70 (sometimes referred to as an individualization step).
  • the sealing body 3 is separated into individual semiconductor chips CP.
  • the method for dividing the sealing body 3 into individual pieces is not particularly limited. Examples of the method of dividing into pieces include a method of dividing into pieces using a cutting means such as a dicing saw, and a laser irradiation method.
  • the semiconductor device manufacturing method of the present embodiment preferably includes a step of mounting the semiconductor package 1 on a printed wiring board or the like (sometimes referred to as a mounting step).
  • the semiconductor package 1 is picked up from the first support sheet 70 with the protective film 60A attached to the element back surface W2.
  • the rewiring layer forming step and the external terminal electrode connecting step can be performed while the sealing body 3 is supported by the support substrate 10. If the sealing body is warped, the surface of the sealing body is curved and it is difficult to form the rewiring layer and the external terminal electrode. However, since the warping of the sealing body 3 is suppressed, a plurality of the sealing bodies 3 The rewiring layer 4 and the external terminal electrode 5 can be formed with high accuracy on the semiconductor chip CP.
  • the handleability of the sealing body 3 improves.
  • the method for manufacturing a semiconductor element according to this embodiment is effective.
  • the manufacturing method of the semiconductor device according to this embodiment is as follows: A plurality of semiconductor elements having a circuit surface and an element back surface opposite to the circuit surface are bonded to the pressure-sensitive adhesive layer of the support substrate having the pressure-sensitive adhesive layer, and the element back surface is directed to the pressure-sensitive adhesive layer.
  • Sealing the semiconductor element attached to the support substrate to form a sealing body Forming an external terminal electrode on the sealing body and electrically connecting the semiconductor element attached to the support substrate and the external terminal electrode; After electrically connecting the semiconductor element and the external terminal electrode, the step of attaching the sealing body to the second support sheet; After pasting the sealing body to the second support sheet, peeling the support substrate from the sealing body to expose the back surface of the semiconductor element; Forming a curable protective film forming layer on the exposed back surface of the semiconductor element; Curing the protective film forming layer to form a protective film; Separating the sealing body adhered to the second support sheet.
  • the sealing body is attached to the second support sheet with the external terminal electrode facing the second support sheet.
  • the same processes as those from the semiconductor chip attaching process to the external terminal electrode connecting process of the first embodiment are performed.
  • the semiconductor device manufacturing method according to the present embodiment is mainly different from the first embodiment in the step after the external terminal electrode connecting step. Since the second embodiment is the same as the first embodiment in other points, the description is omitted or simplified.
  • FIG. 5 is a diagram showing an example of a method for manufacturing a semiconductor device according to the present embodiment.
  • FIG. 5A After the external terminal electrode 5 is electrically connected to the semiconductor chip CP and before the supporting substrate 10 is peeled from the sealing body 3, the sealing body 3 is removed from the second supporting sheet 71.
  • the cross-sectional schematic explaining the process (it may be called a 2nd support sheet sticking process) attached to is shown.
  • the sealing body 3 supported by the support substrate 10 is attached to the second support sheet 71.
  • the sealing body 3 is adhered with the external terminal electrode 5 facing the second support sheet 71.
  • the 2nd support sheet 71 has a base film and an adhesive layer.
  • the sealing body 3 it is preferable to support the sealing body 3 on the second support sheet 71 to which the ring frame RF is attached.
  • the 2nd support sheet 71 is a dicing sheet used in the manufacturing process of a semiconductor device.
  • the support substrate 10 is peeled from the sealing body 3 to expose the element back surface W2 of the semiconductor chip CP (support substrate peeling process).
  • the method of peeling the support substrate 10 from the sealing body 3 is not specifically limited.
  • the method described in the first embodiment can be adopted.
  • the method of peeling the support substrate peeling process of this embodiment after peeling the support substrate 10 from the double-sided adhesive sheet 20, the method of peeling the double-sided adhesive sheet 20 from the sealing body 3 is mentioned.
  • the method of peeling the support substrate 10 and the double-sided adhesive sheet 20 integrally from the sealing body 3 is mentioned.
  • FIG. 5C shows a schematic cross-sectional view illustrating a step of forming a curable protective film forming layer 60 on the element back surface W2 of the exposed semiconductor chip CP (protective film forming layer forming step).
  • the protective film forming layer 60 is formed on the sealing body 3 supported by the second support sheet 71.
  • the element back surface W2 is covered by forming a protective film forming layer 60 on the back surface (surface opposite to the surface on which the rewiring layer 4 and the like are formed) side of the sealing body 3.
  • the formation method of the protective film formation layer 60 of this embodiment is the same as that of the protective film formation layer 60 of 1st embodiment.
  • the protective film forming layer 60 contains a thermosetting adhesive because generation of residual stress at the time of thermosetting and adhesive residue can be suppressed.
  • a thermosetting layer is preferred.
  • the protective film forming layer 60 is also preferably an ultraviolet curable layer containing an ultraviolet curable adhesive. Also in this embodiment, the process (protective film formation process) which hardens the protective film formation layer 60 of the sealing body 3 supported by the 2nd support sheet 71, and forms protective film 60A (refer FIG. 5D) is implemented. To do.
  • the method for curing the protective film forming layer 60 is the same as in the first embodiment.
  • FIG. 5D shows a schematic cross-sectional view for explaining a process of separating the sealing body 3 adhered to the second support sheet 71 (individualization process). Also in this embodiment, the sealing body 3 is separated into pieces like the first embodiment. By separating the sealing body 3 into individual pieces, the semiconductor package 1 as a semiconductor device is manufactured.
  • the semiconductor device manufacturing method of the present embodiment preferably includes a step of mounting the semiconductor package 1 on a printed wiring board or the like (sometimes referred to as a mounting step).
  • the semiconductor package 1 is picked up from the second support sheet 71 with the protective film 60A attached to the element back surface W2.
  • the manufacturing method of the semiconductor device according to this embodiment is as follows: A plurality of semiconductor elements having a circuit surface and an element back surface opposite to the circuit surface are bonded to the pressure-sensitive adhesive layer of the support substrate having the pressure-sensitive adhesive layer, and the element back surface is directed to the pressure-sensitive adhesive layer.
  • Sealing the semiconductor element attached to the support substrate to form a sealing body Forming an external terminal electrode on the sealing body and electrically connecting the semiconductor element attached to the support substrate and the external terminal electrode; After electrically connecting the semiconductor element and the external terminal electrode, the step of attaching the sealing body to the second support sheet; After pasting the sealing body to the second support sheet, peeling the support substrate from the sealing body to expose the back surface of the semiconductor element; Forming a curable protective film forming layer on the exposed back surface of the semiconductor element; Curing the protective film forming layer to form a protective film; After forming the protective film, the step of peeling the sealing body from the second support sheet and sticking to the third support sheet; Separating the sealing body stuck to the third support sheet.
  • the sealing body is attached to the second support sheet, the sealing body is attached with the external terminal electrode facing the second support sheet.
  • the sealing body is attached to the third support sheet, the sealing body is attached with the protective film facing the third support sheet.
  • the same processes as those from the semiconductor chip attaching process to the external terminal electrode connecting process of the first embodiment are performed.
  • the same steps as those from the second support sheet attaching step to the protective film forming step of the second embodiment are performed.
  • the manufacturing method of the semiconductor device according to this embodiment is mainly different from the first embodiment and the second embodiment in the process after the protective film forming process. Since the third embodiment is the same as the first embodiment and the second embodiment in other points, the description is omitted or simplified.
  • FIG. 6 is a diagram showing an example of a method for manufacturing a semiconductor device according to the present embodiment.
  • the sealing body 3 is peeled from the second support sheet 71 and attached to the third support sheet 72 (a third support sheet attaching process and A schematic cross-sectional view is shown to explain.
  • the third support sheet attaching step the sealing body 3 on which the protective film 60 ⁇ / b> A is formed is attached to the third support sheet 72.
  • the sealing body 3 is stuck with the protective film 60 ⁇ / b> A facing the third support sheet 72.
  • the third support sheet 72 in the present embodiment is also preferably a dicing sheet used in the manufacturing process of the semiconductor device. Also in this embodiment, it is preferable to support the sealing body 3 on the third support sheet 72 to which the ring frame RF2 is attached.
  • FIG. 6B shows a schematic cross-sectional view illustrating a step of separating the sealing body 3 adhered to the third support sheet 72 (single step). Also in this embodiment, the sealing body 3 is separated into pieces like the first embodiment. By separating the sealing body 3 into individual pieces, the semiconductor package 1 as a semiconductor device is manufactured.
  • the semiconductor device manufacturing method of the present embodiment preferably includes a step of mounting the semiconductor package 1 on a printed wiring board or the like (sometimes referred to as a mounting step).
  • the semiconductor package 1 is picked up from the third support sheet 72 with the protective film 60A attached to the element back surface W2.
  • the support substrate peeling step can be performed on the sealing body 3 supported by the second support sheet 71. It becomes easy to peel from. Furthermore, also in this embodiment, since the sealing body 3 after peeling the support substrate 10 is supported by the second support sheet 71 as in the second embodiment, the protective film forming layer forming step is performed. Easy to do. According to this embodiment, even when the second support sheet 71 does not have the characteristics as a dicing sheet, sealing is performed by sticking the sealing body 3 to the third support sheet 72 as a dicing sheet.
  • the semiconductor package 1 can be obtained by dividing the body 3 into individual pieces.
  • the present invention is not limited to the embodiment.
  • the present invention includes a modification of the above-described embodiment as long as the object of the present invention can be achieved.
  • a step of performing laser printing on the protective film may be performed.
  • Laser printing is performed by a laser marking method, and the surface of the protective film is scraped off by laser light irradiation to mark a product number or the like on the protective film.
  • the protective film may be directly irradiated with laser light, or laser light may be irradiated through the support sheet.
  • the laser printing step is after forming the protective film, and from the step of separating the sealing body attached to the support sheet. It is preferable to carry out before.
  • the warping of the sealing body can be suppressed. Therefore, when the laser printing process is performed, the focal point of the laser beam is accurately determined and marking can be performed with high accuracy.
  • the sealing body is exposed between the supporting substrate peeling step and the protective film forming layer forming step.
  • You may implement the process it may call a sealing body grinding process which grinds the element back surface side. By performing this grinding process, the thickness of the sealing body can be reduced, and the semiconductor device can be reduced in thickness.
  • a protective film forming layer is formed on the ground surface of the sealing body.
  • the double-sided adhesive sheet 20 was affixed on the support substrate 10 and the semiconductor chip CP was affixed and demonstrated to the 1st adhesive layer 22 which the double-sided adhesive sheet 20 has mentioned as an example, this embodiment was demonstrated.
  • the invention is not limited to such an embodiment.
  • an adhesive layer is formed on the surface of the support substrate, and the semiconductor element is formed on the adhesive layer. You may make it stick.
  • the pressure-sensitive adhesive layer preferably contains the same pressure-sensitive adhesive as the first pressure-sensitive adhesive layer 22.
  • the method for sealing the plurality of semiconductor chips CP using the sealing member is not limited to the method described in the embodiment.
  • a plurality of semiconductor chips CP supported by the support substrate 10 are mounted in a mold.
  • a method may be employed in which a sealing resin material having fluidity is poured into a mold and the sealing resin material is heated and cured to form a sealing resin layer.
  • the sheet-shaped sealing resin is covered with the circuit surfaces W1 of the plurality of semiconductor chips CP.
  • a method may be employed in which the sealing resin layer is formed by placing the sheet-shaped sealing resin so as to cover the semiconductor chip CP, and heating and curing the sealing resin.
  • the sealing resin layer is formed by placing the sheet-shaped sealing resin so as to cover the semiconductor chip CP, and heating and curing the sealing resin.
  • the sealing member 30 may cover the circuit surface W1 side of the semiconductor chip CP.
  • a step of exposing the connection terminal W3 of the semiconductor chip CP on the surface of the sealing body 3 (sometimes referred to as a connection terminal exposure step) is performed.
  • this connection terminal exposing step the connection terminal W3 is exposed by removing a part or the whole of the sealing resin layer on the surface side of the sealing body 3 covering the circuit surface W1 and the connection terminal W3 of the semiconductor chip CP.
  • the method for exposing the connection terminal W3 of the semiconductor chip CP is not particularly limited.
  • connection terminal W3 of the semiconductor chip CP for example, a method of grinding the sealing resin layer to expose the connection terminal W3, or removing the sealing resin layer by a method such as laser irradiation to remove the connection terminal W3.
  • a method of exposing and a method of exposing the connection terminal W3 by removing the sealing resin layer by an etching method include a method of exposing and a method of exposing the connection terminal W3 by removing the sealing resin layer by an etching method. If the connection terminal W3 can be electrically connected to the rewiring layer 4 and the external terminal electrode 5, the entire connection terminal W3 may be exposed or a part of the connection terminal W3 may be exposed. .
  • the semiconductor package is not limited to the embodiment described in the embodiment and the modification of the embodiment.
  • An FO-WLP type semiconductor package in which an external electrode pad is fanned out outside the region of the semiconductor element in the sealing body and an external terminal electrode is connected to the external electrode pad may be used.
  • a semiconductor package including a plurality of semiconductor elements may be manufactured by separating the sealing body so as to include a plurality of semiconductor elements.
  • SYMBOLS 1 Semiconductor package (semiconductor device), 3 ... Sealing body, 5 ... External terminal electrode, 10 ... Support substrate, 22 ... 1st adhesive layer (adhesive layer), 30 ... Sealing member, 60 ... Protective film Forming layer, 60A ... protective film, 70 ... first support sheet, 71 ... second support sheet, 72 ... third support sheet, CP ... semiconductor chip (semiconductor element), W1 ... circuit surface, W2 ... element back surface , W3... Connection terminal.

Abstract

Disclosed is a semiconductor device manufacturing method characterized by including: a step for adhering a plurality of semiconductor elements, each having a circuit surface (W1) and an element rear surface (W2), to an adhesive layer of a supporting substrate (10) having the adhesive layer by having the element rear surface (W2) face the adhesive layer; a step for forming a sealing body (3) by sealing the semiconductor elements adhered to the supporting substrate (10); a step for forming an external terminal electrode on the sealing body (3), and electrically connecting to each other the external terminal electrode and the semiconductor elements adhered to the supporting substrate (10); a step for peeling the supporting substrate (10) from the sealing body (3) after electrically connecting the semiconductor elements and the external terminal electrode to each other, and exposing the element rear surface (W2) of each of the semiconductor elements; a step for forming a curable protection film forming layer on the exposed element rear surface (W2) of each of the semiconductor elements; and a step for forming a protection film by curing the protection film forming layer.

Description

半導体装置の製造方法Manufacturing method of semiconductor device
　本発明は、半導体装置の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor device.
　近年、電子機器の小型化、軽量化、及び高機能化が進んでいる。電子機器に搭載される半導体装置にも、小型化、薄型化、及び高密度化が求められている。半導体チップ（単に、チップと称する場合がある。）は、そのサイズに近いパッケージに実装されることがある。このようなパッケージは、チップスケールパッケージ（Ｃｈｉｐ　Ｓｃａｌｅ　Ｐａｃｋａｇｅ；ＣＳＰ）と称されることもある。ＣＳＰを製造するプロセスの一つとして、ウエハレベルパッケージ（Ｗａｆｅｒ　Ｌｅｖｅｌ　Ｐａｃｋａｇｅ；ＷＬＰ）が挙げられる。ＷＬＰにおいては、ダイシングによりパッケージを個片化する前に、チップ回路形成面に外部電極などを形成し、最終的にはチップを含むパッケージウエハをダイシングして、個片化する。ＷＬＰとしては、ファンイン（Ｆａｎ－Ｉｎ）型とファンアウト（Ｆａｎ－Ｏｕｔ）型が挙げられる。ファンアウト型のＷＬＰ（以下、ＦＯ－ＷＬＰと略記する場合がある。）においては、半導体チップを、チップサイズよりも大きな領域となるように封止部材で覆って半導体チップ封止体を形成し、再配線層や外部電極を、半導体チップの回路面だけでなく封止部材の表面領域においても形成する。 In recent years, electronic devices are becoming smaller, lighter, and more functional. Semiconductor devices mounted on electronic devices are also required to be smaller, thinner, and higher in density. A semiconductor chip (sometimes simply referred to as a chip) may be mounted in a package close to its size. Such a package may be referred to as a chip scale package (CSP). As one of processes for manufacturing CSP, there is a wafer level package (WLP). In WLP, before dicing a package into individual pieces, external electrodes and the like are formed on the chip circuit formation surface, and finally a package wafer including chips is diced into individual pieces. As WLP, there are a fan-in type and a fan-out type. In a fan-out type WLP (hereinafter sometimes abbreviated as FO-WLP), a semiconductor chip sealing body is formed by covering a semiconductor chip with a sealing member so as to be an area larger than the chip size. The rewiring layer and the external electrode are formed not only on the circuit surface of the semiconductor chip but also on the surface region of the sealing member.
　例えば、特許文献１には、チップ仮固定用の粘着テープを用いたＷＬＰなどの製造方法が記載されている。特許文献１の方法においては、チップの回路面を、基板上の粘着テープの粘着剤層に向けて貼着する方式（フェイスダウン方式と称する場合がある。）によって、チップを貼着している。 For example, Patent Document 1 describes a method for manufacturing WLP or the like using an adhesive tape for temporarily fixing a chip. In the method of Patent Document 1, the chip is attached by a method of attaching the circuit surface of the chip toward the adhesive layer of the adhesive tape on the substrate (sometimes referred to as a face-down method). .
特開２０１２－６２３７２号公報JP 2012-62372 A
　特許文献１の方法においては、チップを樹脂封止した後に、粘着テープ及び基板を、チップを樹脂により封止してなる層（チップ封止層と称する場合がある。）から剥離し、露出した回路面に電極を形成している。このように、特許文献１の方法においては、チップ回路面に電極を形成する際にチップ封止層は基板によって支持されていないため、封止樹脂の硬化に伴う応力によって、チップ封止層の反りが発生するおそれがある。チップ封止層の反りが発生すると、チップ回路面に再配線層及び電極を形成し難い。 In the method of Patent Document 1, after the chip is resin-sealed, the adhesive tape and the substrate are peeled off from the layer formed by sealing the chip with the resin (sometimes referred to as a chip sealing layer) and exposed. Electrodes are formed on the circuit surface. As described above, in the method of Patent Document 1, since the chip sealing layer is not supported by the substrate when the electrodes are formed on the chip circuit surface, the stress of the chip sealing layer is caused by the stress accompanying the curing of the sealing resin. There is a risk of warping. When warping of the chip sealing layer occurs, it is difficult to form a rewiring layer and electrodes on the chip circuit surface.
　本発明の目的は、封止体の反りを抑制できる半導体装置の製造方法を提供することである。 An object of the present invention is to provide a method for manufacturing a semiconductor device capable of suppressing warpage of a sealing body.
　本発明の一態様に係る半導体装置の製造方法は、回路面及び前記回路面とは反対側の素子裏面を有する複数の半導体素子を、粘着剤層を有する支持基板の前記粘着剤層に、前記素子裏面を前記粘着剤層に向けて、貼着する工程と、前記支持基板に貼着された前記半導体素子を封止して、封止体を形成する工程と、外部端子電極を前記封止体に形成して、前記支持基板に貼着された前記半導体素子と前記外部端子電極とを電気的に接続させる工程と、前記半導体素子と前記外部端子電極とを電気的に接続させた後に、前記支持基板を前記封止体から剥離して前記半導体素子の前記素子裏面を露出させる工程と、露出した前記半導体素子の前記素子裏面に硬化性の保護膜形成層を形成する工程と、前記保護膜形成層を硬化させて保護膜を形成する工程と、を含む、ことを特徴とする。 In the method for manufacturing a semiconductor device according to one aspect of the present invention, a plurality of semiconductor elements having a circuit surface and an element back surface opposite to the circuit surface are provided on the pressure-sensitive adhesive layer of the support substrate having the pressure-sensitive adhesive layer. A step of attaching the back surface of the element to the pressure-sensitive adhesive layer, a step of sealing the semiconductor element attached to the support substrate to form a sealing body, and sealing the external terminal electrode Forming the body, electrically connecting the semiconductor element and the external terminal electrode adhered to the support substrate, and electrically connecting the semiconductor element and the external terminal electrode; Peeling the support substrate from the sealing body to expose the element back surface of the semiconductor element, forming a curable protective film forming layer on the exposed element back surface of the semiconductor element, and the protection Curing the film forming layer to form a protective film And a step, and characterized in that.
　本発明の一態様に係る半導体装置の製造方法において、前記保護膜を形成した後に、前記封止体を第一の支持シートに貼着する工程と、前記第一の支持シートに貼着された前記封止体を個片化する工程と、をさらに含む、ことが好ましい。 In the method for manufacturing a semiconductor device according to one embodiment of the present invention, after forming the protective film, the step of attaching the sealing body to the first support sheet and the first support sheet were attached. It is preferable that the method further includes a step of dividing the sealing body into pieces.
　本発明の一態様に係る半導体装置の製造方法において、前記半導体素子と前記外部端子電極とを電気的に接続させた後であって、前記支持基板を前記封止体から剥離する前に、前記封止体を第二の支持シートに貼着する工程をさらに含み、前記封止体の前記外部端子電極を前記第二の支持シートに向けて貼着する、ことが好ましい。 In the method for manufacturing a semiconductor device according to one embodiment of the present invention, after electrically connecting the semiconductor element and the external terminal electrode, before separating the support substrate from the sealing body, It is preferable that the method further includes a step of sticking the sealing body to the second support sheet, and sticking the external terminal electrode of the sealing body toward the second support sheet.
　本発明の一態様に係る半導体装置の製造方法において、前記封止体を前記第二の支持シートに貼着し、前記支持基板を前記封止体から剥離した後に、露出した前記半導体素子の前記素子裏面に前記保護膜形成層を形成する、ことが好ましい。 In the method for manufacturing a semiconductor device according to one embodiment of the present invention, the sealing body is attached to the second support sheet, and the support substrate is peeled off from the sealing body, and then the exposed semiconductor element. The protective film forming layer is preferably formed on the back surface of the element.
　本発明の一態様に係る半導体装置の製造方法において、前記保護膜を形成した後に、前記第二の支持シートに貼着された前記封止体を個片化する工程をさらに含む、ことが好ましい。 In the method for manufacturing a semiconductor device according to one embodiment of the present invention, it is preferable that the method further includes a step of separating the sealing body attached to the second support sheet after forming the protective film. .
　本発明の一態様に係る半導体装置の製造方法において、前記保護膜を形成した後に、前記封止体を前記第二の支持シートから剥離して、第三の支持シートに貼着する工程と、前記第三の支持シートに貼着された前記封止体を個片化する工程と、をさらに含む、ことが好ましい。 In the method for manufacturing a semiconductor device according to one embodiment of the present invention, after forming the protective film, the step of peeling the sealing body from the second support sheet and attaching the sealant to the third support sheet; It is preferable that the method further includes a step of separating the sealing body attached to the third support sheet.
　本発明の一態様によれば、封止体の反りを抑制できる半導体装置の製造方法を提供することができる。 According to one embodiment of the present invention, a method for manufacturing a semiconductor device that can suppress warping of a sealing body can be provided.
第一実施形態に係る半導体装置の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 1st embodiment. 第一実施形態に係る半導体装置の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 1st embodiment. 第一実施形態に係る半導体装置の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 1st embodiment. 図１Ａ、図１Ｂ及び図１Ｃに続いて、第一実施形態に係る製造方法を説明する断面図である。FIG. 1C is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 1A, FIG. 1B, and FIG. 1C. 図１Ａ、図１Ｂ及び図１Ｃに続いて、第一実施形態に係る製造方法を説明する断面図である。FIG. 1C is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 1A, FIG. 1B, and FIG. 1C. 図１Ａ、図１Ｂ及び図１Ｃに続いて、第一実施形態に係る製造方法を説明する断面図である。FIG. 1C is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 1A, FIG. 1B, and FIG. 1C. 図１Ａ、図１Ｂ及び図１Ｃに続いて、第一実施形態に係る製造方法を説明する断面図である。FIG. 1C is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 1A, FIG. 1B, and FIG. 1C. 図２Ａ、図２Ｂ、図２Ｃ及び図２Ｄに続いて、第一実施形態に係る製造方法を説明する断面図である。2A, 2B, 2C and 2D are cross-sectional views for explaining the manufacturing method according to the first embodiment. FIG. 図２Ａ、図２Ｂ、図２Ｃ及び図２Ｄに続いて、第一実施形態に係る製造方法を説明する断面図である。2A, 2B, 2C and 2D are cross-sectional views for explaining the manufacturing method according to the first embodiment. FIG. 第一実施形態で用いる両面粘着シートの断面図である。It is sectional drawing of the double-sided adhesive sheet used by 1st embodiment. 第二実施形態に係る半導体装置の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 2nd embodiment. 第二実施形態に係る半導体装置の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 2nd embodiment. 第二実施形態に係る半導体装置の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 2nd embodiment. 第二実施形態に係る半導体装置の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 2nd embodiment. 第三実施形態に係る半導体装置の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 3rd embodiment. 第三実施形態に係る半導体装置の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 3rd embodiment.
〔第一実施形態〕
　以下、本実施形態に係る半導体装置の製造方法について説明する。
　本実施形態に係る半導体装置の製造方法は、
　回路面及び前記回路面とは反対側の素子裏面を有する複数の半導体素子を、粘着剤層を有する支持基板の前記粘着剤層に、前記素子裏面を前記粘着剤層に向けて、貼着する工程と、
　前記支持基板に貼着された前記半導体素子を封止して、封止体を形成する工程と、
　外部端子電極を前記封止体に形成して、前記支持基板に貼着された前記半導体素子と前記外部端子電極とを電気的に接続させる工程と、
　前記半導体素子と前記外部端子電極とを電気的に接続させた後に、前記支持基板を前記封止体から剥離して前記半導体素子の前記素子裏面を露出させる工程と、
　露出した前記半導体素子の前記素子裏面に硬化性の保護膜形成層を形成する工程と、
　前記保護膜形成層を硬化させて保護膜を形成する工程と、
　前記保護膜を形成した後に、前記封止体を第一の支持シートに貼着する工程と、
　前記第一の支持シートに貼着された前記封止体を個片化する工程と、を含む。 [First embodiment]
Hereinafter, a method for manufacturing the semiconductor device according to the present embodiment will be described.
The manufacturing method of the semiconductor device according to this embodiment is as follows:
A plurality of semiconductor elements having a circuit surface and an element back surface opposite to the circuit surface are bonded to the pressure-sensitive adhesive layer of the support substrate having the pressure-sensitive adhesive layer, and the element back surface is directed to the pressure-sensitive adhesive layer. Process,
Sealing the semiconductor element attached to the support substrate to form a sealing body;
Forming an external terminal electrode on the sealing body and electrically connecting the semiconductor element attached to the support substrate and the external terminal electrode;
After electrically connecting the semiconductor element and the external terminal electrode, peeling the support substrate from the sealing body to expose the back surface of the semiconductor element;
Forming a curable protective film forming layer on the exposed back surface of the semiconductor element;
Curing the protective film forming layer to form a protective film;
After forming the protective film, the step of sticking the sealing body to the first support sheet;
Separating the sealing body adhered to the first support sheet.
　図１（図１Ａ、図１Ｂ及び図１Ｃ）、図２（図２Ａ、図２Ｂ、図２Ｃ及び図２Ｄ）及び図３（図３Ａ及び図３Ｂ）は、本実施形態に係る半導体装置の製造方法の一例を示す図である。 1 (FIGS. 1A, 1B, and 1C), FIG. 2 (FIGS. 2A, 2B, 2C, and 2D) and FIG. 3 (FIGS. 3A and 3B) illustrate a method for manufacturing a semiconductor device according to the present embodiment. It is a figure which shows an example.
（半導体チップ貼着工程）
　図１Ａ及び図１Ｂには、粘着剤層を有する支持基板１０に、半導体素子としての半導体チップＣＰを貼着させる工程（半導体チップ貼着工程と称する場合がある。）を説明する断面概略図が示されている。なお、図１Ａには、半導体チップＣＰが１つ示されているが、本実施形態では、図１Ｂに示すように複数の半導体チップＣＰを粘着剤層に貼着させる。半導体チップＣＰを貼着させる際は、１つずつ貼着させてもよいし、複数の半導体チップＣＰを同時に貼着させてもよい。
　本実施形態では、支持基板１０に貼着された両面粘着シート２０が備える粘着剤層に半導体チップＣＰが貼着される。 (Semiconductor chip pasting process)
1A and 1B are schematic cross-sectional views illustrating a step of attaching a semiconductor chip CP as a semiconductor element to a support substrate 10 having an adhesive layer (sometimes referred to as a semiconductor chip attaching step). It is shown. 1A shows one semiconductor chip CP, in the present embodiment, a plurality of semiconductor chips CP are attached to the adhesive layer as shown in FIG. 1B. When the semiconductor chips CP are bonded, the semiconductor chips CP may be bonded one by one or a plurality of semiconductor chips CP may be bonded simultaneously.
In the present embodiment, the semiconductor chip CP is attached to the adhesive layer provided in the double-sided adhesive sheet 20 attached to the support substrate 10.
・両面粘着シート
　図４には、両面粘着シート２０の断面概略図が示されている。
　両面粘着シート２０は、基材２１と、第一の粘着剤層２２と、第二の粘着剤層２３とを、有する。基材２１は、第一の基材面２１１と、第一の基材面２１１とは反対側の第二の基材面２１２とを有する。
　第一の粘着剤層２２は、第一の基材面２１１に形成されている。
　第二の粘着剤層２３は、第二の基材面２１２に形成されている。
　本実施形態では、第一の粘着剤層２２に半導体チップＣＰが貼着され、第二の粘着剤層２３が支持基板１０に貼着される。
　図１に示すように、本実施形態で用いる半導体チップＣＰは、接続端子Ｗ３が設けられた回路面Ｗ１と、回路面Ｗ１とは反対側の素子裏面Ｗ２とを有する。本実施形態では、素子裏面Ｗ２を第一の粘着剤層２２に貼着させる。このように、回路面Ｗ１を上に向けて第一の粘着剤層２２に貼着させる方式を、フェイスアップ方式と称する場合がある。 -Double-sided adhesive sheet The cross-sectional schematic of the double-sided adhesive sheet 20 is shown by FIG.
The double-sided pressure-sensitive adhesive sheet 20 has a base material 21, a first pressure-sensitive adhesive layer 22, and a second pressure-sensitive adhesive layer 23. The base material 21 has a first base material surface 211 and a second base material surface 212 opposite to the first base material surface 211.
The first pressure-sensitive adhesive layer 22 is formed on the first base material surface 211.
The second pressure-sensitive adhesive layer 23 is formed on the second base material surface 212.
In the present embodiment, the semiconductor chip CP is attached to the first adhesive layer 22, and the second adhesive layer 23 is attached to the support substrate 10.
As shown in FIG. 1, the semiconductor chip CP used in this embodiment has a circuit surface W1 provided with a connection terminal W3, and an element back surface W2 opposite to the circuit surface W1. In the present embodiment, the element back surface W <b> 2 is attached to the first pressure-sensitive adhesive layer 22. As described above, the method of attaching the first pressure-sensitive adhesive layer 22 with the circuit surface W1 facing upward may be referred to as a face-up method.
　第一の粘着剤層２２は、粘着剤を含有している。第一の粘着剤層２２に含まれる粘着剤は、特に限定されず、様々な種類の粘着剤を第一の粘着剤層２２に適用できる。第一の粘着剤層２２に含まれる粘着剤としては、例えば、ゴム系、アクリル系、シリコーン系、ポリエステル系、及びウレタン系等からなる群から選択される粘着剤が挙げられる。なお、粘着剤の種類は、用途及び貼着される被着体の種類等を考慮して選択される。第一の粘着剤層２２にエネルギー線重合性化合物が配合されている場合には、第一の粘着剤層２２に支持基板１０側からエネルギー線を照射し、エネルギー線重合性化合物を硬化させる。エネルギー線重合性化合物を硬化させると、第一の粘着剤層２２の凝集力が高まり、第一の粘着剤層２２と半導体チップＣＰとの間の粘着力、並びに第一の粘着剤層２２と封止部材との間の粘着力を低下、又は消失させることができる。エネルギー線としては、例えば、紫外線（ＵＶ）及び電子線（ＥＢ）等が挙げられ、紫外線が好ましい。
　第一の粘着剤層２２は、加熱によって発泡する発泡剤を含有しても良い。この場合、加熱によって発泡剤を発泡させることにより、第一の粘着剤層２２と半導体チップＣＰとの間の粘着力、並びに第一の粘着剤層２２と封止部材との間の粘着力を低下、又は消失させることができる。
　第二の粘着剤層２３も、粘着剤を含有している。第二の粘着剤層２３に含まれる粘着剤は特に限定されず、支持基板１０と両面粘着シート２０とを固定できる材質であればよい。第二の粘着剤層２３に含まれる粘着剤は、必要に応じて両面粘着シート２０を支持基板１０から剥離できるような粘着剤であることが好ましい。 The first pressure-sensitive adhesive layer 22 contains a pressure-sensitive adhesive. The pressure-sensitive adhesive contained in the first pressure-sensitive adhesive layer 22 is not particularly limited, and various types of pressure-sensitive adhesives can be applied to the first pressure-sensitive adhesive layer 22. Examples of the pressure-sensitive adhesive contained in the first pressure-sensitive adhesive layer 22 include a pressure-sensitive adhesive selected from the group consisting of rubber-based, acrylic-based, silicone-based, polyester-based, urethane-based, and the like. In addition, the kind of adhesive is selected in consideration of the use and the kind of adherend to be attached. When the energy ray polymerizable compound is blended in the first pressure-sensitive adhesive layer 22, the energy ray polymerizable compound is cured by irradiating the first pressure-sensitive adhesive layer 22 with energy rays from the support substrate 10 side. When the energy beam polymerizable compound is cured, the cohesive force of the first pressure-sensitive adhesive layer 22 is increased, the pressure-sensitive adhesive force between the first pressure-sensitive adhesive layer 22 and the semiconductor chip CP, and the first pressure-sensitive adhesive layer 22 The adhesive force with the sealing member can be reduced or eliminated. Examples of the energy rays include ultraviolet rays (UV) and electron beams (EB), and ultraviolet rays are preferable.
The 1st adhesive layer 22 may contain the foaming agent which foams by heating. In this case, by foaming the foaming agent by heating, the adhesive force between the first adhesive layer 22 and the semiconductor chip CP and the adhesive force between the first adhesive layer 22 and the sealing member are increased. It can be reduced or eliminated.
The second pressure-sensitive adhesive layer 23 also contains a pressure-sensitive adhesive. The pressure-sensitive adhesive contained in the second pressure-sensitive adhesive layer 23 is not particularly limited as long as it can fix the support substrate 10 and the double-sided pressure-sensitive adhesive sheet 20. It is preferable that the adhesive contained in the 2nd adhesive layer 23 is an adhesive which can peel the double-sided adhesive sheet 20 from the support substrate 10 as needed.
・支持基板
　支持基板１０は、半導体チップＣＰ及び封止体を支持するための基板である。支持基板１０は、半導体チップＣＰ及び封止体を支持することができる材質で形成されていれば特に限定されない。支持基板１０は、硬質材料で形成されていることが好ましい。本実施形態において、支持基板１０は、ガラス製であることが好ましい。また、支持基板１０は、硬質プラスチックフィルム製であることも好ましい。 Support substrate The support substrate 10 is a substrate for supporting the semiconductor chip CP and the sealing body. The support substrate 10 is not particularly limited as long as it is made of a material that can support the semiconductor chip CP and the sealing body. The support substrate 10 is preferably formed of a hard material. In the present embodiment, the support substrate 10 is preferably made of glass. The support substrate 10 is preferably made of a hard plastic film.
（封止工程）
　図１Ｃには、複数の半導体チップＣＰを封止する工程（封止工程と称する場合がある。）を説明する断面概略図が示されている。
　封止部材３０を用いて複数の半導体チップＣＰを封止する方法は、特に限定されない。本実施形態では、半導体チップＣＰの回路面Ｗ１側が封止部材３０で覆われないように、封止部材３０を用いて封止することにより封止体３が形成される。複数の半導体チップＣＰの間にも封止部材３０が充填されている。図１Ｃに示すように、封止体３の表面において、半導体チップＣＰの回路面Ｗ１及び接続端子Ｗ３が露出する。
　封止部材３０の材質としては、樹脂製であることが好ましく、例えば、エポキシ樹脂などが挙げられる。封止部材３０として用いられるエポキシ樹脂には、例えば、フェノール樹脂、エラストマー、無機充填材、及び硬化促進剤などが含まれていてもよい。例えば、液状の封止樹脂を用いて半導体チップＣＰの回路面Ｗ１側が封止部材３０で覆われないように封止できる。
　封止工程と次の工程との間に封止部材３０をさらに硬化させる工程（追加の硬化工程と称する場合がある。）を実施してもよい。この工程では、封止樹脂層を加熱して硬化を促進させる方法が例として挙げられる。なお、追加の硬化工程を実施せずに封止工程における加熱によって封止部材３０を十分に硬化させてもよい。 (Sealing process)
FIG. 1C is a schematic cross-sectional view illustrating a process of sealing a plurality of semiconductor chips CP (sometimes referred to as a sealing process).
A method for sealing the plurality of semiconductor chips CP using the sealing member 30 is not particularly limited. In the present embodiment, the sealing body 3 is formed by sealing with the sealing member 30 so that the circuit surface W1 side of the semiconductor chip CP is not covered with the sealing member 30. A sealing member 30 is also filled between the plurality of semiconductor chips CP. As shown in FIG. 1C, on the surface of the sealing body 3, the circuit surface W1 and the connection terminal W3 of the semiconductor chip CP are exposed.
The material of the sealing member 30 is preferably made of a resin, and examples thereof include an epoxy resin. The epoxy resin used as the sealing member 30 may include, for example, a phenol resin, an elastomer, an inorganic filler, a curing accelerator, and the like. For example, a liquid sealing resin can be used so that the circuit surface W1 side of the semiconductor chip CP is not covered with the sealing member 30.
You may implement the process (it may call an additional hardening process) which further hardens the sealing member 30 between a sealing process and the following process. In this step, a method of heating the sealing resin layer to promote curing is given as an example. In addition, you may fully harden the sealing member 30 by the heating in a sealing process, without implementing an additional hardening process.
（再配線層形成工程）
　図２Ａには、半導体チップＣＰと電気的に接続する再配線層４を形成する工程（再配線層形成工程と称する場合がある。）を説明する断面概略図が示されている。
　本実施形態では、再配線層４と、封止体３の表面に露出している接続端子Ｗ３とを電気的に接続させる。本実施形態においては、再配線層４を、回路面Ｗ１及び封止体３の面の上に形成する。再配線層４を形成する方法は、従来公知の方法を採用することができる。
　再配線層４は、外部端子電極を接続させるための外部電極パッド４１を有する。本実施形態では、複数の外部電極パッド４１が、再配線層４の表面側に形成されている。 (Rewiring layer formation process)
FIG. 2A is a schematic cross-sectional view illustrating a step of forming the rewiring layer 4 that is electrically connected to the semiconductor chip CP (sometimes referred to as a rewiring layer forming step).
In the present embodiment, the rewiring layer 4 and the connection terminal W3 exposed on the surface of the sealing body 3 are electrically connected. In the present embodiment, the rewiring layer 4 is formed on the circuit surface W <b> 1 and the surface of the sealing body 3. As a method of forming the rewiring layer 4, a conventionally known method can be adopted.
The rewiring layer 4 has external electrode pads 41 for connecting external terminal electrodes. In the present embodiment, a plurality of external electrode pads 41 are formed on the surface side of the rewiring layer 4.
（外部端子電極接続工程）
　図２Ｂには、再配線層４に外部端子電極５を電気的に接続させる工程（外部端子電極接続工程と称する場合がある。）を説明する断面概略図が示されている。この外部端子電極接続工程により、半導体チップＣＰと外部端子電極５とが電気的に接続される。
　本実施形態では、外部電極パッド４１に、はんだボール等の外部端子電極５を載置し、はんだ接合などにより、外部端子電極５と外部電極パッド４１とを電気的に接続させる。はんだボールの材質は、特に限定されない。はんだボールの材質としては、例えば、含鉛はんだ及び無鉛はんだ等が挙げられる。 (External terminal electrode connection process)
FIG. 2B shows a schematic cross-sectional view illustrating a step of connecting the external terminal electrode 5 to the rewiring layer 4 (sometimes referred to as an external terminal electrode connection step). By this external terminal electrode connection step, the semiconductor chip CP and the external terminal electrode 5 are electrically connected.
In the present embodiment, the external terminal electrode 5 such as a solder ball is placed on the external electrode pad 41, and the external terminal electrode 5 and the external electrode pad 41 are electrically connected by solder bonding or the like. The material of the solder ball is not particularly limited. Examples of the material of the solder ball include lead-containing solder and lead-free solder.
（支持基板剥離工程）
　図２Ｃには、支持基板１０を封止体３から剥離して半導体チップＣＰの素子裏面Ｗ２を露出させる工程（支持基板剥離工程と称する場合がある。）を説明する断面概略図が示されている。
　支持基板１０を封止体３から剥離する方法は特に限定されない。支持基板剥離工程の方法としては、支持基板１０を両面粘着シート２０から剥離した後に、両面粘着シート２０を封止体３から剥離する方法が挙げられる。また、支持基板剥離工程の方法としては、支持基板１０と両面粘着シート２０とを一体として封止体３から剥離する方法が挙げられる。
　第一の粘着剤層２２にエネルギー線重合性化合物が配合されている場合には、第一の粘着剤層２２に支持基板１０側からエネルギー線を照射し、エネルギー線重合性化合物を硬化させる。エネルギー線重合性化合物を硬化させると、第一の粘着剤層２２の凝集力が高まり、第一の粘着剤層２２と封止体３との間の粘着力を低下、又は消失させることができる。エネルギー線としては、例えば、紫外線（ＵＶ）及び電子線（ＥＢ）等が挙げられ、紫外線が好ましい。第一の粘着剤層２２と封止体３との間の粘着力を低下、又は消失させる方法は、エネルギー線照射に限定されない。この粘着力を低下させる方法、又は消失させる方法としては、例えば、加熱による方法、加熱及びエネルギー線照射による方法、並びに冷却による方法が挙げられる。 (Support substrate peeling process)
FIG. 2C shows a schematic cross-sectional view illustrating a process of peeling the support substrate 10 from the sealing body 3 to expose the element back surface W2 of the semiconductor chip CP (sometimes referred to as a support board peeling process). Yes.
The method for peeling the support substrate 10 from the sealing body 3 is not particularly limited. As a method of a support substrate peeling process, after peeling the support substrate 10 from the double-sided adhesive sheet 20, the method of peeling the double-sided adhesive sheet 20 from the sealing body 3 is mentioned. Moreover, as a method of a support substrate peeling process, the method of peeling the support substrate 10 and the double-sided adhesive sheet 20 integrally from the sealing body 3 is mentioned.
When the energy ray polymerizable compound is blended in the first pressure-sensitive adhesive layer 22, the energy ray polymerizable compound is cured by irradiating the first pressure-sensitive adhesive layer 22 with energy rays from the support substrate 10 side. When the energy ray polymerizable compound is cured, the cohesive force of the first pressure-sensitive adhesive layer 22 is increased, and the pressure-sensitive adhesive force between the first pressure-sensitive adhesive layer 22 and the sealing body 3 can be reduced or eliminated. . Examples of the energy rays include ultraviolet rays (UV) and electron beams (EB), and ultraviolet rays are preferable. The method for reducing or eliminating the adhesive force between the first pressure-sensitive adhesive layer 22 and the sealing body 3 is not limited to energy beam irradiation. Examples of the method for reducing or eliminating the adhesive strength include a method using heating, a method using heating and energy beam irradiation, and a method using cooling.
（保護膜形成層形成工程）
　図２Ｄには、露出した半導体チップＣＰの素子裏面Ｗ２に硬化性の保護膜形成層６０を形成する工程（保護膜形成層形成工程と称する場合がある。）を説明する断面概略図が示されている。本実施形態では、封止体３の裏面（再配線層４等が形成されている面とは反対側の面）側に、保護膜形成層６０を形成することで、素子裏面Ｗ２を覆う。
　本実施形態における保護膜形成層６０としては、例えば、熱硬化性、及びエネルギー線硬化性のいずれかの保護膜形成層を用いることができる。本実施形態における保護膜形成層６０は、外部からエネルギーを受けて硬化する硬化性の接着剤組成物を含有する材料を用いて形成されることが好ましい。当該硬化性の接着剤組成物を含有する接着シートを封止体３の裏面に貼付し、保護膜形成層６０を形成して、素子裏面Ｗ２を覆うことがより好ましい。
　外部から供給されるエネルギーとしては、例えば、紫外線、電子線、及び熱などが挙げられる。保護膜形成層６０は、紫外線硬化型接着剤、及び熱硬化型接着剤の少なくともいずれか一種を含有していることが好ましい。保護膜形成層６０は、熱硬化型接着剤を含有する熱硬化性の層であることも好ましく、紫外線硬化型接着剤を含有する紫外線硬化性の層であることも好ましい。
　保護膜形成層６０を形成した後、保護膜形成層６０を硬化させて保護膜６０Ａ（図３Ａ参照）を形成する工程（保護膜形成工程と称する場合がある。）を実施する。 (Protective film forming layer forming step)
2D is a schematic cross-sectional view illustrating a step of forming a curable protective film forming layer 60 on the element back surface W2 of the exposed semiconductor chip CP (sometimes referred to as a protective film forming layer forming step). ing. In the present embodiment, the element back surface W2 is covered by forming the protective film forming layer 60 on the back surface (the surface opposite to the surface on which the rewiring layer 4 and the like are formed) of the sealing body 3.
As the protective film forming layer 60 in the present embodiment, for example, any one of thermosetting and energy ray curable protective film forming layers can be used. The protective film forming layer 60 in this embodiment is preferably formed using a material containing a curable adhesive composition that is cured by receiving energy from the outside. More preferably, an adhesive sheet containing the curable adhesive composition is affixed to the back surface of the sealing body 3 to form the protective film forming layer 60 and cover the element back surface W2.
Examples of the energy supplied from the outside include ultraviolet rays, electron beams, and heat. The protective film forming layer 60 preferably contains at least one of an ultraviolet curable adhesive and a thermosetting adhesive. The protective film forming layer 60 is also preferably a thermosetting layer containing a thermosetting adhesive, and is preferably an ultraviolet curable layer containing an ultraviolet curable adhesive.
After forming the protective film forming layer 60, a step of curing the protective film forming layer 60 to form a protective film 60A (see FIG. 3A) (sometimes referred to as a protective film forming step) is performed.
（第一の支持シート貼着工程）
　図３Ａには、保護膜形成層６０を硬化させて保護膜６０Ａを形成した後、リングフレームＲＦが貼着された第一の支持シート７０に封止体３を貼着する工程（第一の支持シート貼着工程と称する場合がある。）を説明する断面概略図が示されている。
　本実施形態における第一の支持シート７０は、半導体装置の製造工程で使用されるダイシングシートであることが好ましい。ダイシングシートとしての第一の支持シート７０は、基材フィルム及び粘着剤層を有することが好ましい。保護膜６０Ａを第一の支持シート７０の粘着剤層に向けて、第一の支持シート７０に封止体３を貼着する。この場合、第一の支持シート７０の粘着剤層の上に、リングフレームＲＦを載置し、リングフレームＲＦを軽く押圧し、リングフレームＲＦと第一の支持シート７０とを固定する。その後、リングフレームＲＦの環形状の内側にて露出する粘着剤層を封止体３の保護膜６０Ａに押し当てて、第一の支持シート７０に封止体３を固定する。 (First support sheet sticking step)
In FIG. 3A, after the protective film forming layer 60 is cured to form the protective film 60A, the sealing body 3 is attached to the first support sheet 70 to which the ring frame RF is attached (first step). A schematic cross-sectional view for explaining (sometimes referred to as a support sheet sticking step) is shown.
The first support sheet 70 in the present embodiment is preferably a dicing sheet used in the manufacturing process of the semiconductor device. It is preferable that the 1st support sheet 70 as a dicing sheet has a base film and an adhesive layer. The sealing body 3 is adhered to the first support sheet 70 with the protective film 60 </ b> A facing the pressure-sensitive adhesive layer of the first support sheet 70. In this case, the ring frame RF is placed on the adhesive layer of the first support sheet 70, the ring frame RF is lightly pressed, and the ring frame RF and the first support sheet 70 are fixed. Thereafter, the pressure-sensitive adhesive layer exposed inside the ring shape of the ring frame RF is pressed against the protective film 60 </ b> A of the sealing body 3 to fix the sealing body 3 to the first support sheet 70.
（個片化工程）
　図３Ｂには、第一の支持シート７０に貼着された封止体３を個片化する工程（個片化工程と称する場合がある。）を説明する断面概略図が示されている。
　本実施形態では、封止体３を半導体チップＣＰ単位で個片化する。封止体３を個片化する方法は、特に限定されない。個片化する方法としては、例えば、ダイシングソーなどの切断手段を用いて個片化する方法、及びレーザー照射法などが挙げられる。
　封止体３を個片化することで、半導体装置としての半導体パッケージ１が製造される。 (Individualization process)
FIG. 3B shows a schematic cross-sectional view illustrating a step of dividing the sealing body 3 adhered to the first support sheet 70 (sometimes referred to as an individualization step).
In the present embodiment, the sealing body 3 is separated into individual semiconductor chips CP. The method for dividing the sealing body 3 into individual pieces is not particularly limited. Examples of the method of dividing into pieces include a method of dividing into pieces using a cutting means such as a dicing saw, and a laser irradiation method.
By separating the sealing body 3 into individual pieces, the semiconductor package 1 as a semiconductor device is manufactured.
　本実施形態の半導体装置の製造方法は、半導体パッケージ１を、プリント配線基板等に実装する工程（実装工程と称する場合がある。）を含むことも好ましい。半導体パッケージ１は、素子裏面Ｗ２に保護膜６０Ａが付いたまま第一の支持シート７０からピックアップされる。 The semiconductor device manufacturing method of the present embodiment preferably includes a step of mounting the semiconductor package 1 on a printed wiring board or the like (sometimes referred to as a mounting step). The semiconductor package 1 is picked up from the first support sheet 70 with the protective film 60A attached to the element back surface W2.
・実施形態の効果
　本実施形態によれば、封止工程において、支持基板１０によって半導体チップＣＰが支持されているので、封止部材３０で半導体チップＣＰを封止した際の反りを抑制できる。
　本実施形態によれば、支持基板１０で封止体３を支持したままで、再配線層形成工程及び外部端子電極接続工程を実施できる。封止体が反っていると封止体の表面が湾曲し、再配線層及び外部端子電極を形成し難いが、封止体３の反りが抑制されているので、封止体３中の複数の半導体チップＣＰに対して再配線層４及び外部端子電極５を精度良く形成できる。
　また、封止体３は、支持基板１０で支持されているので、封止体３のハンドリング性が向上する。特に、半導体チップＣＰの厚み及び封止体３の厚みが薄い場合には、本実施形態に係る半導体素子の製造方法は有効である。 -Effect of embodiment Since according to this embodiment, semiconductor chip CP is supported by the support substrate 10 in the sealing process, the curvature at the time of sealing the semiconductor chip CP with the sealing member 30 can be suppressed.
According to this embodiment, the rewiring layer forming step and the external terminal electrode connecting step can be performed while the sealing body 3 is supported by the support substrate 10. If the sealing body is warped, the surface of the sealing body is curved and it is difficult to form the rewiring layer and the external terminal electrode. However, since the warping of the sealing body 3 is suppressed, a plurality of the sealing bodies 3 The rewiring layer 4 and the external terminal electrode 5 can be formed with high accuracy on the semiconductor chip CP.
Moreover, since the sealing body 3 is supported by the support substrate 10, the handleability of the sealing body 3 improves. In particular, when the thickness of the semiconductor chip CP and the thickness of the sealing body 3 are thin, the method for manufacturing a semiconductor element according to this embodiment is effective.
〔第二実施形態〕
　次に、本発明の第二実施形態について説明する。
　本実施形態に係る半導体装置の製造方法は、
　回路面及び前記回路面とは反対側の素子裏面を有する複数の半導体素子を、粘着剤層を有する支持基板の前記粘着剤層に、前記素子裏面を前記粘着剤層に向けて、貼着する工程と、
　前記支持基板に貼着された前記半導体素子を封止して、封止体を形成する工程と、
　外部端子電極を前記封止体に形成して、前記支持基板に貼着された前記半導体素子と前記外部端子電極とを電気的に接続させる工程と、
　前記半導体素子と前記外部端子電極とを電気的に接続させた後に、前記封止体を前記第二の支持シートに貼着する工程と、
　前記封止体を前記第二の支持シートに貼着した後に、前記支持基板を前記封止体から剥離して前記半導体素子の前記素子裏面を露出させる工程と、
　露出した前記半導体素子の前記素子裏面に硬化性の保護膜形成層を形成する工程と、
　前記保護膜形成層を硬化させて保護膜を形成する工程と、
　前記第二の支持シートに貼着された前記封止体を個片化する工程と、を含む。
　前記封止体は、前記外部端子電極を第二の支持シートに向けて第二の支持シートに貼着される。 [Second Embodiment]
Next, a second embodiment of the present invention will be described.
The manufacturing method of the semiconductor device according to this embodiment is as follows:
A plurality of semiconductor elements having a circuit surface and an element back surface opposite to the circuit surface are bonded to the pressure-sensitive adhesive layer of the support substrate having the pressure-sensitive adhesive layer, and the element back surface is directed to the pressure-sensitive adhesive layer. Process,
Sealing the semiconductor element attached to the support substrate to form a sealing body;
Forming an external terminal electrode on the sealing body and electrically connecting the semiconductor element attached to the support substrate and the external terminal electrode;
After electrically connecting the semiconductor element and the external terminal electrode, the step of attaching the sealing body to the second support sheet;
After pasting the sealing body to the second support sheet, peeling the support substrate from the sealing body to expose the back surface of the semiconductor element;
Forming a curable protective film forming layer on the exposed back surface of the semiconductor element;
Curing the protective film forming layer to form a protective film;
Separating the sealing body adhered to the second support sheet.
The sealing body is attached to the second support sheet with the external terminal electrode facing the second support sheet.
　本実施形態に係る半導体装置の製造方法において、第一実施形態の半導体チップ貼着工程から外部端子電極接続工程までと同様の工程が実施される。
　本実施形態に係る半導体装置の製造方法は、外部端子電極接続工程の後の工程が、第一実施形態と主に相違する。第二実施形態は、その他の点において第一実施形態と同様であるため、説明を省略又は簡略化する。 In the manufacturing method of the semiconductor device according to the present embodiment, the same processes as those from the semiconductor chip attaching process to the external terminal electrode connecting process of the first embodiment are performed.
The semiconductor device manufacturing method according to the present embodiment is mainly different from the first embodiment in the step after the external terminal electrode connecting step. Since the second embodiment is the same as the first embodiment in other points, the description is omitted or simplified.
　図５（図５Ａ、図５Ｂ、図５Ｃ及び図５Ｄ）は、本実施形態に係る半導体装置の製造方法の一例を示す図である。 FIG. 5 (FIGS. 5A, 5B, 5C, and 5D) is a diagram showing an example of a method for manufacturing a semiconductor device according to the present embodiment.
（第二の支持シート貼着工程）
　図５Ａには、半導体チップＣＰに外部端子電極５を電気的に接続させた後であって、支持基板１０を封止体３から剥離する前に、封止体３を第二の支持シート７１に貼着する工程（第二の支持シート貼着工程と称する場合がある。）を説明する断面概略図が示されている。
　第二の支持シート貼着工程では、支持基板１０で支持された状態の封止体３を第二の支持シート７１に貼着する。封止体３は、外部端子電極５を第二の支持シート７１に向けて貼着される。本実施形態においても、第二の支持シート７１は、基材フィルム及び粘着剤層を有することが好ましい。本実施形態においても、リングフレームＲＦが貼着された第二の支持シート７１に封止体３を支持させることが好ましい。また、第二の支持シート７１は、半導体装置の製造工程で使用されるダイシングシートであることが好ましい。 (Second support sheet sticking step)
In FIG. 5A, after the external terminal electrode 5 is electrically connected to the semiconductor chip CP and before the supporting substrate 10 is peeled from the sealing body 3, the sealing body 3 is removed from the second supporting sheet 71. The cross-sectional schematic explaining the process (it may be called a 2nd support sheet sticking process) attached to is shown.
In the second support sheet attaching step, the sealing body 3 supported by the support substrate 10 is attached to the second support sheet 71. The sealing body 3 is adhered with the external terminal electrode 5 facing the second support sheet 71. Also in this embodiment, it is preferable that the 2nd support sheet 71 has a base film and an adhesive layer. Also in this embodiment, it is preferable to support the sealing body 3 on the second support sheet 71 to which the ring frame RF is attached. Moreover, it is preferable that the 2nd support sheet 71 is a dicing sheet used in the manufacturing process of a semiconductor device.
（支持基板剥離工程）
　図５Ｂには、封止体３を第二の支持シート７１に貼着した後に、支持基板１０を封止体３から剥離して半導体チップＣＰの素子裏面Ｗ２を露出させる工程（支持基板剥離工程）を説明する断面概略図が示されている。
　本実施形態においても、支持基板１０を封止体３から剥離する方法は、特に限定されない。例えば、第一実施形態で説明した方法などを採用できる。本実施形態の支持基板剥離工程の方法としては、支持基板１０を両面粘着シート２０から剥離した後に、両面粘着シート２０を封止体３から剥離する方法が挙げられる。また、本実施形態の支持基板剥離工程の方法としては、支持基板１０と両面粘着シート２０とを一体として封止体３から剥離する方法が挙げられる。 (Support substrate peeling process)
In FIG. 5B, after the sealing body 3 is adhered to the second support sheet 71, the support substrate 10 is peeled from the sealing body 3 to expose the element back surface W2 of the semiconductor chip CP (support substrate peeling process). ) Is a schematic cross-sectional view explaining the above.
Also in this embodiment, the method of peeling the support substrate 10 from the sealing body 3 is not specifically limited. For example, the method described in the first embodiment can be adopted. As a method of the support substrate peeling process of this embodiment, after peeling the support substrate 10 from the double-sided adhesive sheet 20, the method of peeling the double-sided adhesive sheet 20 from the sealing body 3 is mentioned. Moreover, as a method of the support substrate peeling process of this embodiment, the method of peeling the support substrate 10 and the double-sided adhesive sheet 20 integrally from the sealing body 3 is mentioned.
（保護膜形成層形成工程）
　図５Ｃには、露出した半導体チップＣＰの素子裏面Ｗ２に硬化性の保護膜形成層６０を形成する工程（保護膜形成層形成工程）を説明する断面概略図が示されている。
　本実施形態においては、第二の支持シート７１に支持された封止体３に保護膜形成層６０を形成する。封止体３の裏面（再配線層４等が形成されている面とは反対側の面）側に、保護膜形成層６０を形成することで、素子裏面Ｗ２を覆う。
　本実施形態の保護膜形成層６０の形成方法は、第一実施形態の保護膜形成層６０の場合と同様である。第二の支持シート７１が、耐熱性を備えている場合は、熱硬化時の残存応力の発生、及び糊残りなどを抑制できることから、保護膜形成層６０は、熱硬化型接着剤を含有する熱硬化性の層であることが好ましい。保護膜形成層６０は、紫外線硬化型接着剤を含有する紫外線硬化性の層であることも好ましい。
　本実施形態においても、第二の支持シート７１に支持された封止体３の保護膜形成層６０を硬化させて保護膜６０Ａ（図５Ｄ参照）を形成する工程（保護膜形成工程）を実施する。保護膜形成層６０を硬化させる方法は、第一実施形態と同様である。 (Protective film forming layer forming step)
FIG. 5C shows a schematic cross-sectional view illustrating a step of forming a curable protective film forming layer 60 on the element back surface W2 of the exposed semiconductor chip CP (protective film forming layer forming step).
In the present embodiment, the protective film forming layer 60 is formed on the sealing body 3 supported by the second support sheet 71. The element back surface W2 is covered by forming a protective film forming layer 60 on the back surface (surface opposite to the surface on which the rewiring layer 4 and the like are formed) side of the sealing body 3.
The formation method of the protective film formation layer 60 of this embodiment is the same as that of the protective film formation layer 60 of 1st embodiment. When the second support sheet 71 has heat resistance, the protective film forming layer 60 contains a thermosetting adhesive because generation of residual stress at the time of thermosetting and adhesive residue can be suppressed. A thermosetting layer is preferred. The protective film forming layer 60 is also preferably an ultraviolet curable layer containing an ultraviolet curable adhesive.
Also in this embodiment, the process (protective film formation process) which hardens the protective film formation layer 60 of the sealing body 3 supported by the 2nd support sheet 71, and forms protective film 60A (refer FIG. 5D) is implemented. To do. The method for curing the protective film forming layer 60 is the same as in the first embodiment.
（個片化工程）
　図５Ｄには、第二の支持シート７１に貼着された封止体３を個片化する工程（個片化工程）を説明する断面概略図が示されている。
　本実施形態においても、第一実施形態と同様に封止体３を個片化する。封止体３を個片化することで、半導体装置としての半導体パッケージ１が製造される。 (Separation process)
FIG. 5D shows a schematic cross-sectional view for explaining a process of separating the sealing body 3 adhered to the second support sheet 71 (individualization process).
Also in this embodiment, the sealing body 3 is separated into pieces like the first embodiment. By separating the sealing body 3 into individual pieces, the semiconductor package 1 as a semiconductor device is manufactured.
　本実施形態の半導体装置の製造方法は、半導体パッケージ１を、プリント配線基板等に実装する工程（実装工程と称する場合がある。）を含むことも好ましい。半導体パッケージ１は、素子裏面Ｗ２に保護膜６０Ａが付いたまま第二の支持シート７１からピックアップされる。 The semiconductor device manufacturing method of the present embodiment preferably includes a step of mounting the semiconductor package 1 on a printed wiring board or the like (sometimes referred to as a mounting step). The semiconductor package 1 is picked up from the second support sheet 71 with the protective film 60A attached to the element back surface W2.
・実施形態の効果
　本実施形態によれば、第一実施形態と同様の効果を奏する。
　さらに、本実施形態によれば、支持基板剥離工程は、第二の支持シート７１に支持された封止体３に対して実施できるので、支持基板１０を封止体３から剥離し易くなる。
　さらに、本実施形態によれば、支持基板１０を剥離した後の封止体３は、第二の支持シート７１に支持されているので、保護膜形成層形成工程を実施し易い。
　第二の支持シート７１がダイシングシートである場合、支持基板剥離工程から個片化工程まで、封止体３を第二の支持シート７１で支持したままで実施できるので、半導体装置の製造工程を簡略化できる。 -Effect of embodiment According to this embodiment, there exists an effect similar to 1st embodiment.
Furthermore, according to this embodiment, since the support substrate peeling process can be performed with respect to the sealing body 3 supported by the second support sheet 71, the support substrate 10 can be easily peeled from the sealing body 3.
Furthermore, according to this embodiment, since the sealing body 3 after peeling the support substrate 10 is supported by the 2nd support sheet 71, it is easy to implement a protective film formation layer formation process.
When the second support sheet 71 is a dicing sheet, the sealing body 3 can be carried out while being supported by the second support sheet 71 from the support substrate peeling step to the singulation step. It can be simplified.
〔第三実施形態〕
　次に、本発明の第三実施形態について説明する。
　本実施形態に係る半導体装置の製造方法は、
　回路面及び前記回路面とは反対側の素子裏面を有する複数の半導体素子を、粘着剤層を有する支持基板の前記粘着剤層に、前記素子裏面を前記粘着剤層に向けて、貼着する工程と、
　前記支持基板に貼着された前記半導体素子を封止して、封止体を形成する工程と、
　外部端子電極を前記封止体に形成して、前記支持基板に貼着された前記半導体素子と前記外部端子電極とを電気的に接続させる工程と、
　前記半導体素子と前記外部端子電極とを電気的に接続させた後に、前記封止体を前記第二の支持シートに貼着する工程と、
　前記封止体を前記第二の支持シートに貼着した後に、前記支持基板を前記封止体から剥離して前記半導体素子の前記素子裏面を露出させる工程と、
　露出した前記半導体素子の前記素子裏面に硬化性の保護膜形成層を形成する工程と、
　前記保護膜形成層を硬化させて保護膜を形成する工程と、
　前記保護膜を形成した後に、前記封止体を前記第二の支持シートから剥離して、第三の支持シートに貼着する工程と、
　前記第三の支持シートに貼着された前記封止体を個片化する工程と、を含む。
　前記封止体を前記第二の支持シートに貼着する際、前記封止体は、前記外部端子電極を第二の支持シートに向けて貼着される。
　前記封止体を前記第三の支持シートに貼着する際、前記封止体は、前記保護膜を前記第三の支持シートに向けて貼着される。 [Third embodiment]
Next, a third embodiment of the present invention will be described.
The manufacturing method of the semiconductor device according to this embodiment is as follows:
A plurality of semiconductor elements having a circuit surface and an element back surface opposite to the circuit surface are bonded to the pressure-sensitive adhesive layer of the support substrate having the pressure-sensitive adhesive layer, and the element back surface is directed to the pressure-sensitive adhesive layer. Process,
Sealing the semiconductor element attached to the support substrate to form a sealing body;
Forming an external terminal electrode on the sealing body and electrically connecting the semiconductor element attached to the support substrate and the external terminal electrode;
After electrically connecting the semiconductor element and the external terminal electrode, the step of attaching the sealing body to the second support sheet;
After pasting the sealing body to the second support sheet, peeling the support substrate from the sealing body to expose the back surface of the semiconductor element;
Forming a curable protective film forming layer on the exposed back surface of the semiconductor element;
Curing the protective film forming layer to form a protective film;
After forming the protective film, the step of peeling the sealing body from the second support sheet and sticking to the third support sheet;
Separating the sealing body stuck to the third support sheet.
When the sealing body is attached to the second support sheet, the sealing body is attached with the external terminal electrode facing the second support sheet.
When the sealing body is attached to the third support sheet, the sealing body is attached with the protective film facing the third support sheet.
　本実施形態に係る半導体装置の製造方法において、第一実施形態の半導体チップ貼着工程から外部端子電極接続工程までと同様の工程が実施される。
　また、本実施形態に係る半導体装置の製造方法において、外部端子電極接続工程の後、第二実施形態の第二の支持シート貼着工程から保護膜形成工程までと同様の工程が実施される。
　本実施形態に係る半導体装置の製造方法は、保護膜形成工程の後の工程が、第一実施形態及び第二実施形態と主に相違する。第三実施形態は、その他の点において第一実施形態及び第二実施形態と同様であるため、説明を省略又は簡略化する。 In the manufacturing method of the semiconductor device according to the present embodiment, the same processes as those from the semiconductor chip attaching process to the external terminal electrode connecting process of the first embodiment are performed.
In the method for manufacturing a semiconductor device according to the present embodiment, after the external terminal electrode connecting step, the same steps as those from the second support sheet attaching step to the protective film forming step of the second embodiment are performed.
The manufacturing method of the semiconductor device according to this embodiment is mainly different from the first embodiment and the second embodiment in the process after the protective film forming process. Since the third embodiment is the same as the first embodiment and the second embodiment in other points, the description is omitted or simplified.
　図６（図６Ａ及び図６Ｂ）は、本実施形態に係る半導体装置の製造方法の一例を示す図である。 FIG. 6 (FIGS. 6A and 6B) is a diagram showing an example of a method for manufacturing a semiconductor device according to the present embodiment.
（第三の支持シート貼着工程）
　図６Ａには、保護膜６０Ａを形成した後に、封止体３を第二の支持シート７１から剥離して、第三の支持シート７２に貼着する工程（第三の支持シート貼着工程と称する場合がある。）を説明する断面概略図が示されている。
　第三の支持シート貼着工程では、保護膜６０Ａを形成した封止体３を第三の支持シート７２に貼着する。封止体３は、保護膜６０Ａを第三の支持シート７２に向けて貼着される。本実施形態における第三の支持シート７２も、第一実施形態と同様、半導体装置の製造工程で使用されるダイシングシートであることが好ましい。本実施形態においても、リングフレームＲＦ２が貼着された第三の支持シート７２に封止体３を支持させることが好ましい。 (Third support sheet sticking step)
In FIG. 6A, after forming the protective film 60A, the sealing body 3 is peeled from the second support sheet 71 and attached to the third support sheet 72 (a third support sheet attaching process and A schematic cross-sectional view is shown to explain.
In the third support sheet attaching step, the sealing body 3 on which the protective film 60 </ b> A is formed is attached to the third support sheet 72. The sealing body 3 is stuck with the protective film 60 </ b> A facing the third support sheet 72. Similarly to the first embodiment, the third support sheet 72 in the present embodiment is also preferably a dicing sheet used in the manufacturing process of the semiconductor device. Also in this embodiment, it is preferable to support the sealing body 3 on the third support sheet 72 to which the ring frame RF2 is attached.
（個片化工程）
　図６Ｂには、第三の支持シート７２に貼着された封止体３を個片化する工程（個片化工程）を説明する断面概略図が示されている。
　本実施形態においても、第一実施形態と同様に封止体３を個片化する。封止体３を個片化することで、半導体装置としての半導体パッケージ１が製造される。 (Separation process)
FIG. 6B shows a schematic cross-sectional view illustrating a step of separating the sealing body 3 adhered to the third support sheet 72 (single step).
Also in this embodiment, the sealing body 3 is separated into pieces like the first embodiment. By separating the sealing body 3 into individual pieces, the semiconductor package 1 as a semiconductor device is manufactured.
　本実施形態の半導体装置の製造方法は、半導体パッケージ１を、プリント配線基板等に実装する工程（実装工程と称する場合がある。）を含むことも好ましい。半導体パッケージ１は、素子裏面Ｗ２に保護膜６０Ａが付いたまま第三の支持シート７２からピックアップされる。 The semiconductor device manufacturing method of the present embodiment preferably includes a step of mounting the semiconductor package 1 on a printed wiring board or the like (sometimes referred to as a mounting step). The semiconductor package 1 is picked up from the third support sheet 72 with the protective film 60A attached to the element back surface W2.
・実施形態の効果
　本実施形態によれば、第一実施形態と同様の効果を奏する。
　さらに、本実施形態においても、第二実施形態と同様、支持基板剥離工程は、第二の支持シート７１に支持された封止体３に対して実施できるので、支持基板１０を封止体３から剥離し易くなる。
　さらに、本実施形態においても、第二実施形態と同様、支持基板１０を剥離した後の封止体３は、第二の支持シート７１に支持されているので、保護膜形成層形成工程を実施し易い。
　本実施形態によれば、第二の支持シート７１がダイシングシートとしての特性を有していない場合でも、ダイシングシートとしての第三の支持シート７２に封止体３を貼着することで封止体３を個片化し、半導体パッケージ１を得ることができる。 -Effect of embodiment According to this embodiment, there exists an effect similar to 1st embodiment.
Further, in the present embodiment as well, as in the second embodiment, the support substrate peeling step can be performed on the sealing body 3 supported by the second support sheet 71. It becomes easy to peel from.
Furthermore, also in this embodiment, since the sealing body 3 after peeling the support substrate 10 is supported by the second support sheet 71 as in the second embodiment, the protective film forming layer forming step is performed. Easy to do.
According to this embodiment, even when the second support sheet 71 does not have the characteristics as a dicing sheet, sealing is performed by sticking the sealing body 3 to the third support sheet 72 as a dicing sheet. The semiconductor package 1 can be obtained by dividing the body 3 into individual pieces.
〔実施形態の変形〕
　本発明は、前記実施形態に何ら限定されない。本発明は、本発明の目的を達成できる範囲で、前記実施形態を変形した態様などを含む。 (Modification of the embodiment)
The present invention is not limited to the embodiment. The present invention includes a modification of the above-described embodiment as long as the object of the present invention can be achieved.
　前記実施形態に係る半導体装置の製造方法のいずれかにおいて、保護膜にレーザー印字する工程（レーザー印字工程と称する場合がある。）を実施してもよい。
　レーザー印字はレーザーマーキング法により行われ、レーザー光の照射により保護膜の表面を削り取ることで保護膜に品番等をマーキングする。
　レーザー印字工程においては、保護膜に、直接、レーザー光を照射してもよいし、支持シート越しにレーザー光を照射してもよい。
　例えば、前記実施形態に係る半導体装置の製造方法のいずれかにおいては、レーザー印字工程は、保護膜を形成した後であって、支持シートに貼着された封止体を個片化する工程よりも前に実施することが好ましい。前記実施形態に係る半導体装置の製造方法のいずれかによれば封止体の反りが抑制できるため、レーザー印字工程を実施する場合にレーザー光の焦点が正確に定まり、精度よくマーキングできる。 In any of the methods for manufacturing a semiconductor device according to the embodiment, a step of performing laser printing on the protective film (sometimes referred to as a laser printing step) may be performed.
Laser printing is performed by a laser marking method, and the surface of the protective film is scraped off by laser light irradiation to mark a product number or the like on the protective film.
In the laser printing step, the protective film may be directly irradiated with laser light, or laser light may be irradiated through the support sheet.
For example, in any one of the methods for manufacturing a semiconductor device according to the embodiment, the laser printing step is after forming the protective film, and from the step of separating the sealing body attached to the support sheet. It is preferable to carry out before. According to any one of the manufacturing methods of the semiconductor device according to the embodiment, the warping of the sealing body can be suppressed. Therefore, when the laser printing process is performed, the focal point of the laser beam is accurately determined and marking can be performed with high accuracy.
　前記実施形態に係る半導体装置の製造方法、並びに実施形態の変形に係る半導体装置の製造方法のいずれかにおいて、支持基板剥離工程と保護膜形成層形成工程との間に、封止体の露出した素子裏面側を研削する工程（封止体研削工程と称する場合がある。）を実施してもよい。この研削工程を実施することにより、封止体の厚みを薄くすることができ、半導体装置の薄型化を図ることができる。封止体研削工程を実施した場合、封止体の研削面に保護膜形成層を形成する。 In any of the manufacturing method of the semiconductor device according to the embodiment and the manufacturing method of the semiconductor device according to the modification of the embodiment, the sealing body is exposed between the supporting substrate peeling step and the protective film forming layer forming step. You may implement the process (it may call a sealing body grinding process) which grinds the element back surface side. By performing this grinding process, the thickness of the sealing body can be reduced, and the semiconductor device can be reduced in thickness. When the sealing body grinding step is performed, a protective film forming layer is formed on the ground surface of the sealing body.
　前記実施形態においては、支持基板１０に両面粘着シート２０を貼付し、両面粘着シート２０が有する第一の粘着剤層２２に半導体チップＣＰを貼着させる態様を例に挙げて説明したが、本発明はこのような態様に限定されない。
　例えば、前記実施形態に係る半導体装置の製造方法、並びに実施形態の変形に係る半導体装置の製造方法のいずれかにおいて、支持基板の表面に粘着剤層を形成し、この粘着剤層に半導体素子を貼着させてもよい。この場合の粘着剤層は、第一の粘着剤層２２と同様の粘着剤を含有していることが好ましい。 In the said embodiment, although the double-sided adhesive sheet 20 was affixed on the support substrate 10 and the semiconductor chip CP was affixed and demonstrated to the 1st adhesive layer 22 which the double-sided adhesive sheet 20 has mentioned as an example, this embodiment was demonstrated. The invention is not limited to such an embodiment.
For example, in any of the manufacturing method of the semiconductor device according to the embodiment and the manufacturing method of the semiconductor device according to the modification of the embodiment, an adhesive layer is formed on the surface of the support substrate, and the semiconductor element is formed on the adhesive layer. You may make it stick. In this case, the pressure-sensitive adhesive layer preferably contains the same pressure-sensitive adhesive as the first pressure-sensitive adhesive layer 22.
　封止部材を用いて複数の半導体チップＣＰを封止する方法は、前記実施形態で説明した方法に限定されない。例えば、前記実施形態に係る半導体装置の製造方法、並びに実施形態の変形に係る半導体装置の製造方法のいずれかにおいて、支持基板１０に支持された状態の複数の半導体チップＣＰを金型内に載置し、金型内に流動性を有する封止樹脂材料を注入し、封止樹脂材料を加熱硬化させて封止樹脂層を形成する方法を採用してもよい。
　また、前記実施形態に係る半導体装置の製造方法、並びに実施形態の変形に係る半導体装置の製造方法のいずれかにおいて、シート状の封止樹脂を複数の半導体チップＣＰの回路面Ｗ１を覆うように載置し、シート状の封止樹脂を半導体チップＣＰを覆うように載置し、封止樹脂を加熱硬化させて、封止樹脂層を形成する方法を採用してもよい。
　シート状の封止樹脂を用いる場合には、真空ラミネート法により半導体チップＣＰを封止することが好ましい。 The method for sealing the plurality of semiconductor chips CP using the sealing member is not limited to the method described in the embodiment. For example, in any one of the manufacturing method of the semiconductor device according to the embodiment and the manufacturing method of the semiconductor device according to the modification of the embodiment, a plurality of semiconductor chips CP supported by the support substrate 10 are mounted in a mold. Alternatively, a method may be employed in which a sealing resin material having fluidity is poured into a mold and the sealing resin material is heated and cured to form a sealing resin layer.
Moreover, in any one of the manufacturing method of the semiconductor device according to the embodiment and the manufacturing method of the semiconductor device according to the modification of the embodiment, the sheet-shaped sealing resin is covered with the circuit surfaces W1 of the plurality of semiconductor chips CP. A method may be employed in which the sealing resin layer is formed by placing the sheet-shaped sealing resin so as to cover the semiconductor chip CP, and heating and curing the sealing resin.
When using a sheet-shaped sealing resin, it is preferable to seal the semiconductor chip CP by a vacuum laminating method.
　前記実施形態に係る半導体装置の製造方法、並びに実施形態の変形に係る半導体装置の製造方法のいずれかの封止工程においては、封止部材３０で半導体チップＣＰの回路面Ｗ１側を覆ってもよい。この場合、封止体３の表面に半導体チップＣＰの接続端子Ｗ３を露出させる工程（接続端子露出工程と称する場合がある。）を実施する。
　この接続端子露出工程では、半導体チップＣＰの回路面Ｗ１や接続端子Ｗ３を覆う封止体３の表面側の封止樹脂層の一部又は全体を除去して接続端子Ｗ３を露出させる。半導体チップＣＰの接続端子Ｗ３を露出させる方法は特に限定されない。半導体チップＣＰの接続端子Ｗ３を露出させる方法としては、例えば、封止樹脂層を研削して接続端子Ｗ３を露出させる方法、封止樹脂層をレーザー照射等の方法により除去して接続端子Ｗ３を露出させる方法、及び封止樹脂層をエッチング法により除去して接続端子Ｗ３を露出させる方法などが挙げられる。接続端子Ｗ３と、再配線層４及び外部端子電極５とが電気的に接続可能であれば、接続端子Ｗ３の全体を露出させてもよいし、接続端子Ｗ３の一部を露出させてもよい。 In any of the sealing steps of the method for manufacturing a semiconductor device according to the embodiment and the method for manufacturing a semiconductor device according to a modification of the embodiment, the sealing member 30 may cover the circuit surface W1 side of the semiconductor chip CP. Good. In this case, a step of exposing the connection terminal W3 of the semiconductor chip CP on the surface of the sealing body 3 (sometimes referred to as a connection terminal exposure step) is performed.
In this connection terminal exposing step, the connection terminal W3 is exposed by removing a part or the whole of the sealing resin layer on the surface side of the sealing body 3 covering the circuit surface W1 and the connection terminal W3 of the semiconductor chip CP. The method for exposing the connection terminal W3 of the semiconductor chip CP is not particularly limited. As a method of exposing the connection terminal W3 of the semiconductor chip CP, for example, a method of grinding the sealing resin layer to expose the connection terminal W3, or removing the sealing resin layer by a method such as laser irradiation to remove the connection terminal W3. Examples thereof include a method of exposing and a method of exposing the connection terminal W3 by removing the sealing resin layer by an etching method. If the connection terminal W3 can be electrically connected to the rewiring layer 4 and the external terminal electrode 5, the entire connection terminal W3 may be exposed or a part of the connection terminal W3 may be exposed. .
　半導体パッケージは、前記実施形態、並びに実施形態の変形において説明した態様に限定されない。封止体における半導体素子の領域外に外部電極パッドをファンアウトさせ、当該外部電極パッドに外部端子電極を接続させたＦＯ－ＷＬＰ型の半導体パッケージであってもよい。 The semiconductor package is not limited to the embodiment described in the embodiment and the modification of the embodiment. An FO-WLP type semiconductor package in which an external electrode pad is fanned out outside the region of the semiconductor element in the sealing body and an external terminal electrode is connected to the external electrode pad may be used.
　前記実施形態、並びに実施形態の変形では、封止体を半導体素子単位で個片化する態様を例に挙げて説明したが、本発明はこのような態様に限定されない。例えば、複数の半導体素子を含むように封止体を個片化することにより、複数の半導体素子を含んだ半導体パッケージを製造してもよい。 In the above-described embodiment and the modification of the embodiment, the embodiment in which the sealing body is separated into individual semiconductor elements has been described as an example, but the present invention is not limited to such an embodiment. For example, a semiconductor package including a plurality of semiconductor elements may be manufactured by separating the sealing body so as to include a plurality of semiconductor elements.
　１…半導体パッケージ（半導体装置）、３…封止体、５…外部端子電極、１０…支持基板、２２…第一の粘着剤層（粘着剤層）、３０…封止部材、６０…保護膜形成層、６０Ａ…保護膜、７０…第一の支持シート、７１…第二の支持シート、７２…第三の支持シート、ＣＰ…半導体チップ（半導体素子）、Ｗ１…回路面、Ｗ２…素子裏面、Ｗ３…接続端子。 DESCRIPTION OF SYMBOLS 1 ... Semiconductor package (semiconductor device), 3 ... Sealing body, 5 ... External terminal electrode, 10 ... Support substrate, 22 ... 1st adhesive layer (adhesive layer), 30 ... Sealing member, 60 ... Protective film Forming layer, 60A ... protective film, 70 ... first support sheet, 71 ... second support sheet, 72 ... third support sheet, CP ... semiconductor chip (semiconductor element), W1 ... circuit surface, W2 ... element back surface , W3... Connection terminal.

Claims (6)

  1. 　回路面及び前記回路面とは反対側の素子裏面を有する複数の半導体素子を、粘着剤層を有する支持基板の前記粘着剤層に、前記素子裏面を前記粘着剤層に向けて、貼着する工程と、
    　前記支持基板に貼着された前記半導体素子を封止して、封止体を形成する工程と、
    　外部端子電極を前記封止体に形成して、前記支持基板に貼着された前記半導体素子と前記外部端子電極とを電気的に接続させる工程と、
    　前記半導体素子と前記外部端子電極とを電気的に接続させた後に、前記支持基板を前記封止体から剥離して前記半導体素子の前記素子裏面を露出させる工程と、
    　露出した前記半導体素子の前記素子裏面に硬化性の保護膜形成層を形成する工程と、
    　前記保護膜形成層を硬化させて保護膜を形成する工程と、を含む、
    　ことを特徴とする半導体装置の製造方法。     A plurality of semiconductor elements having a circuit surface and an element back surface opposite to the circuit surface are bonded to the pressure-sensitive adhesive layer of the support substrate having the pressure-sensitive adhesive layer, and the element back surface is directed to the pressure-sensitive adhesive layer. Process,
    Sealing the semiconductor element attached to the support substrate to form a sealing body;
    Forming an external terminal electrode on the sealing body and electrically connecting the semiconductor element attached to the support substrate and the external terminal electrode;
    After electrically connecting the semiconductor element and the external terminal electrode, peeling the support substrate from the sealing body to expose the back surface of the semiconductor element;
    Forming a curable protective film forming layer on the exposed back surface of the semiconductor element;
    Curing the protective film forming layer to form a protective film,
    A method for manufacturing a semiconductor device.
  2. 　請求項１に記載の半導体装置の製造方法において、
    　前記保護膜を形成した後に、前記封止体を第一の支持シートに貼着する工程と、
    　前記第一の支持シートに貼着された前記封止体を個片化する工程と、をさらに含む、
    　ことを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 1,
    After forming the protective film, the step of sticking the sealing body to the first support sheet;
    Further comprising the step of separating the sealing body attached to the first support sheet.
    A method for manufacturing a semiconductor device.
  3. 　請求項１に記載の半導体装置の製造方法において、
    　前記半導体素子と前記外部端子電極とを電気的に接続させた後であって、前記支持基板を前記封止体から剥離する前に、前記封止体を第二の支持シートに貼着する工程をさらに含み、
    　前記封止体の前記外部端子電極を前記第二の支持シートに向けて貼着する、
    　ことを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 1,
    A step of attaching the sealing body to the second support sheet after electrically connecting the semiconductor element and the external terminal electrode and before peeling the support substrate from the sealing body. Further including
    Adhering the external terminal electrode of the sealing body toward the second support sheet,
    A method for manufacturing a semiconductor device.
  4. 　請求項３に記載の半導体装置の製造方法において、
    　前記封止体を前記第二の支持シートに貼着し、前記支持基板を前記封止体から剥離した後に、露出した前記半導体素子の前記素子裏面に前記保護膜形成層を形成する、
    　ことを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 3,
    After the sealing body is attached to the second support sheet and the support substrate is peeled from the sealing body, the protective film forming layer is formed on the exposed element back surface of the semiconductor element.
    A method for manufacturing a semiconductor device.
  5. 　請求項４に記載の半導体装置の製造方法において、
    　前記保護膜を形成した後に、前記第二の支持シートに貼着された前記封止体を個片化する工程をさらに含む、
    　ことを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 4,
    After the protective film is formed, the method further includes a step of separating the sealing body attached to the second support sheet.
    A method for manufacturing a semiconductor device.
  6. 　請求項４に記載の半導体装置の製造方法において、
    　前記保護膜を形成した後に、前記封止体を前記第二の支持シートから剥離して、第三の支持シートに貼着する工程と、
    　前記第三の支持シートに貼着された前記封止体を個片化する工程と、をさらに含む、
    　ことを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 4,
    After forming the protective film, the step of peeling the sealing body from the second support sheet and sticking to the third support sheet;
    Further comprising the step of separating the sealing body adhered to the third support sheet.
    A method for manufacturing a semiconductor device.
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