WO2018003602A1 - Gabarit d'alignement, procédé d'alignement et procédé de transfert - Google Patents

Gabarit d'alignement, procédé d'alignement et procédé de transfert Download PDF

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Publication number
WO2018003602A1
WO2018003602A1 PCT/JP2017/022686 JP2017022686W WO2018003602A1 WO 2018003602 A1 WO2018003602 A1 WO 2018003602A1 JP 2017022686 W JP2017022686 W JP 2017022686W WO 2018003602 A1 WO2018003602 A1 WO 2018003602A1
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WO
WIPO (PCT)
Prior art keywords
alignment jig
semiconductor
semiconductor chip
alignment
pressure
Prior art date
Application number
PCT/JP2017/022686
Other languages
English (en)
Japanese (ja)
Inventor
岡本　直也
忠知 山田
利彰 毛受
Original Assignee
リンテック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by リンテック株式会社 filed Critical リンテック株式会社
Priority to CN201780039795.9A priority Critical patent/CN109417045B/zh
Priority to JP2018525080A priority patent/JP6983775B2/ja
Priority to KR1020187035156A priority patent/KR102413733B1/ko
Publication of WO2018003602A1 publication Critical patent/WO2018003602A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67259—Position monitoring, e.g. misposition detection or presence detection

Definitions

  • the present invention relates to an alignment jig, an alignment method, and a transfer method.
  • a semiconductor wafer (hereinafter simply referred to as a wafer) is cut into a predetermined shape and a predetermined size, and is singulated into a plurality of semiconductor chips (hereinafter sometimes simply referred to as chips).
  • the chips are separated from each other and the distance between the chips is increased and then mounted on an object to be mounted such as a lead frame or a substrate.
  • a semiconductor chip may be mounted in a package close to the size of the semiconductor chip. Such a package may be referred to as a chip scale package (CSP).
  • CSP chip scale package
  • WLP wafer level package
  • WLP wafer level package
  • WLP before dicing a package into individual pieces, external electrodes and the like are formed on the chip circuit formation surface, and finally a package wafer including chips is diced into individual pieces.
  • WLP there are a fan-in type and a fan-out type.
  • a semiconductor chip sealing body is formed by covering a semiconductor chip with a sealing member so as to be an area larger than the chip size.
  • the rewiring layer and the external electrode are formed not only on the circuit surface of the semiconductor chip but also on the surface region of the sealing member.
  • Patent Document 1 discloses a process of forming an extended wafer by enclosing a plurality of semiconductor chips separated from a semiconductor wafer while leaving a circuit formation surface and using a mold member, and outside the semiconductor chip.
  • a manufacturing method of a semiconductor package including a step of forming a rewiring pattern extending in a region is described.
  • the semiconductor chip before enclosing a plurality of individual semiconductor chips with a mold member, the semiconductor chip is replaced with an expandable wafer mount tape, and the wafer mount tape is spread to expand the plurality of semiconductor chips. The distance between them is expanding.
  • a frame support means for supporting a wafer (plate-like member) integrated with the frame via a film (adhesive sheet), and a film surface
  • a film adheresive sheet
  • a film surface for example, see Patent Document 2.
  • tensions in four directions of + X axis direction, ⁇ X axis direction, + Y axis direction, and ⁇ Y axis direction are applied to the adhesive sheet, for example, located on the outermost periphery.
  • the adhesive sheet has a composite direction thereof, that is, a composite direction of + X-axis direction and + Y-axis direction, + X-axis direction and -Y-axis direction.
  • Tensile force is also applied to the direction of combining the -X axis direction and the + Y axis direction, and the direction of combining the -X axis direction and the -Y axis direction.
  • each chip is assumed to have an evenly expanded distance, and is transported based on a position derived by calculation (hereinafter sometimes referred to as a theoretical position).
  • the product is transported by a transporting means such as a device and a pickup device, and mounted on an object to be mounted to form a product.
  • a transporting means such as a device and a pickup device
  • the relative positional relationship between the chip and the mounted object in the product may be slightly shifted, the connection position of wire bonding may be shifted, or the positions of the terminals of the chip and the mounted object may be shifted.
  • they cannot be connected to each other, and the yield of the product is lowered.
  • Such a problem can occur not only in the manufacture of semiconductor devices, but also in, for example, dense mechanical parts and fine ornaments.
  • a plurality of pieces can be aligned at equal intervals, but it is necessary to prepare a pick-and-place device. Furthermore, in the pick-and-place method, a plurality of pieces cannot be aligned together. Therefore, there is a demand for a method capable of aligning a plurality of pieces in a quicker manner with a simpler method.
  • an alignment jig having a plurality of accommodating portions is used.
  • the accommodating portion is formed so as to accommodate a semiconductor chip.
  • the semiconductor chip is accommodated in the accommodating portion.
  • the position and the inclination of the semiconductor chip are adjusted by moving at least one of the alignment jig and the semiconductor chip and bringing the semiconductor chip into contact with the wall portion of the housing portion.
  • the corners of the semiconductor chip and the corners of the housing part may come into contact with each other, and the piece may be inclined.
  • An alignment jig is an alignment jig including a plurality of accommodating portions capable of accommodating a piece-like body, and an accommodating corner portion of the accommodating portion is provided in the plurality of the accommodating portions. Are formed so that the piece-like corners of the piece do not come into contact with the containing corners when the pieces are brought into contact with the wall of the containing portion. It is characterized by.
  • the plurality of accommodating portions are arranged in a lattice shape.
  • the piece has a first side and a second side adjacent to the first side, and the piece corner is the first side.
  • the wall portion of the housing portion Located at the end of the side surface and the end of the second side surface, the wall portion of the housing portion has a first side wall and a second side wall adjacent to the first side wall, and the housing corner portion Is located at the end of the first side wall and the end of the second side wall, and the receiving corner is recessed from the surface of the first side wall and the surface of the second side wall.
  • the first side surface of the piece-like body and the first side wall of the housing portion are brought into contact with each other, and the second side surface of the piece-like body is brought into contact with the second side wall of the housing portion.
  • the piece-like body corners of the piece-like body are preferably housed in the depressions of the housing corners.
  • the plurality of accommodating portions are arranged in a square lattice shape.
  • the alignment method according to an aspect of the present invention is characterized in that the plurality of pieces are aligned using the alignment jig according to the above-described aspect of the present invention.
  • the plurality of pieces arranged by the alignment method according to one aspect of the present invention are transferred to the adhesive surface of a hard support having an adhesive surface. It is characterized by that.
  • an alignment jig and an alignment method that can align a plurality of pieces at a more even interval in a simple and rapid manner.
  • the corner of the piece (the piece corner) is aligned.
  • Do not contact the corner of the housing part (the housing corner). That is, according to this alignment jig, it is possible to prevent the flakes from being inclined when the flakes are brought into contact with the wall portion.
  • a plurality of pieces can be quickly aligned together with a simpler configuration than the pick and place device.
  • the transfer method according to one aspect of the present invention, it is possible to transfer a plurality of pieces that are aligned by the alignment method according to one aspect of the present invention to a support.
  • FIG. 4A, 4B, and 4C are cross-sectional views illustrating the manufacturing method according to the first embodiment.
  • FIG. 4A, 4B, and 4C are cross-sectional views illustrating the manufacturing method according to the first embodiment.
  • FIG. 5B is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 5A and FIG. 5B.
  • FIG. 5B is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 5A and FIG.
  • FIG. 6A and 6B are cross-sectional views illustrating the manufacturing method according to the first embodiment, following FIG. 6A and FIG. 6B.
  • 6A and 6B are cross-sectional views illustrating the manufacturing method according to the first embodiment, following FIG. 6A and FIG. 6B.
  • FIG. 7B is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 7A and FIG. 7B.
  • FIG. 7B is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 7A and FIG. 7B.
  • FIG. 7B is a cross-sectional view illustrating the manufacturing method according to the first embodiment following FIG. 7A and FIG. 7B.
  • FIG. 8A, 8B, and 8C are cross-sectional views illustrating the manufacturing method according to the first embodiment, following FIG. 8A, FIG. 8B, and FIG. 8C.
  • 8A, 8B, and 8C are cross-sectional views illustrating the manufacturing method according to the first embodiment, following FIG. 8A, FIG. 8B, and FIG. 8C.
  • 8A, 8B, and 8C are cross-sectional views illustrating the manufacturing method according to the first embodiment, following FIG. 8A, FIG. 8B, and FIG. 8C.
  • 10A, 10B, 10C, and 10D are cross-sectional views illustrating a manufacturing method according to the second embodiment.
  • 10A, 10B, 10C, and 10D are cross-sectional views illustrating a manufacturing method according to the second embodiment.
  • 10A, 10B, 10C, and 10D are cross-sectional views illustrating a manufacturing method according to the second embodiment.
  • 11A, 11B, and 11C are cross-sectional views illustrating the manufacturing method according to the second embodiment.
  • FIG. 11A, 11B, and 11C are cross-sectional views illustrating the manufacturing method according to the second embodiment.
  • FIG. 17D is a cross-sectional view illustrating the manufacturing method according to the sixth embodiment following FIG. 16A, FIG. 16B, and FIG. 16C.
  • FIG. 17D is a cross-sectional view illustrating the manufacturing method according to the sixth embodiment following FIG. 16A, FIG. 16B, and FIG. 16C.
  • FIG. 17D is a cross-sectional view illustrating the manufacturing method according to the sixth embodiment following FIG. 17A and FIG. 17B.
  • FIG. 17D is a cross-sectional view illustrating the manufacturing method according to the sixth embodiment following FIG. 17A and FIG. 17B.
  • FIG. 17D is a cross-sectional view illustrating the manufacturing method according to the sixth embodiment following FIG. 17A and FIG. 17B. It is sectional drawing explaining the transfer method which concerns on 7th Embodiment. It is sectional drawing explaining the transfer method which concerns on 7th Embodiment.
  • the alignment jig is used in the manufacturing process of the semiconductor device.
  • the use of the alignment jig of the present invention is not limited to the use for manufacturing a semiconductor device.
  • a mode in which semiconductor chips are aligned as a piece will be described as an example.
  • the strips that can be aligned by the alignment jig of the present invention are not limited to semiconductor chips.
  • FIG. 1 also shows a plan view in which a part of the alignment jig 100 is enlarged.
  • the alignment jig 100 includes a frame-shaped main body 110 and a housing 101 that can house the semiconductor chip CP.
  • the alignment jig 100 includes a plurality of accommodating portions 101.
  • the alignment jig 100 according to the present embodiment is a frame-like member in which accommodating portions 101 that open in a substantially square shape in a plan view are arranged in a lattice shape. More preferably, the plurality of accommodating portions 101 are arranged in a square lattice pattern.
  • the outer shape of the main body 110 of the present embodiment is formed in a circular shape.
  • the main body 110 includes an outer frame 110A and an inner frame 110B formed inside the outer frame 110A.
  • the outer frame 110A is a circular frame.
  • the inner frame 110B is a frame assembled in a lattice shape inside the circular outer frame 110A.
  • the circular shape is larger than the width of the grid-shaped inner frame 110B that partitions each of the plurality of accommodating portions 101. It is preferable that the width of the outer frame 110A is larger.
  • the outer shape of the body portion of the alignment jig is not limited to a circular shape, and may be a shape other than a circular shape.
  • the accommodating part 101 has the wall part 102 and the accommodation corner
  • the accommodating portion 101 is formed in a substantially square shape in plan view by the wall portion 102 and the accommodating corner portion 103.
  • the opening size of the accommodating portion 101 is not particularly limited as long as it is formed to a size that can accommodate a semiconductor chip.
  • the plurality of accommodating portions 101 are formed at regular intervals.
  • the accommodating part 101 of this embodiment penetrates the upper surface side and lower surface side of the main body part 110. That is, the accommodating part 101 has an opening on the upper surface side and an opening on the lower surface side.
  • the alignment jig 100 is placed on the holding surface of the holding member, or a plate-like member is attached to one of the upper surface side and the lower surface side of the main body portion 110.
  • the main body part 110 is composed of an outer frame 110A and an inner frame 110B, and the housing part 101 penetrates the upper surface side and the lower surface side of the main body part 110, thereby reducing the weight of the alignment jig 100 according to the present embodiment. it can.
  • the depth of the accommodating part 101 is not particularly limited.
  • the surface of the semiconductor chip CP may be located above or below the surface of the main body portion 110, or the main body portion.
  • the surface of 110 and the surface of the semiconductor chip CP may be located on the same plane.
  • the depth of the accommodating portion 101 corresponds to the height of the wall portion 102.
  • the wall part 102 is comprised by the 1st side wall 102a, the 2nd side wall 102b, the 3rd side wall 102c, and the 4th side wall 102d.
  • the first side wall 102a and the second side wall 102b are adjacent to each other
  • the second side wall 102b and the third side wall 102c are adjacent to each other
  • the third side wall 102c and the fourth side wall 102d are adjacent to each other
  • the fourth side wall 102d and the first side wall 102a are adjacent to each other.
  • the accommodating corner portion 103 is located at the end of the wall portion 102.
  • the housing corner part 103 includes a first housing corner part 103a, a second housing corner part 103b, a third housing corner part 103c, and a fourth housing corner part 103d.
  • the first housing corner 103a is located at the end of the first side wall 102a and the end of the second side wall 102b
  • the second housing corner 103b is the end of the second side wall 102b and the third side.
  • the third receiving corner 103c is located at the end of the third side wall 102c and the end of the fourth side wall 102d
  • the fourth receiving corner 103d is the end of the fourth side wall 102d.
  • the end of the first side wall 102a is located at the end of the first side wall 102a.
  • Each of the four housing corners 103 is formed in the following shape.
  • the corner of the semiconductor chip CP may be referred to as a chip corner or a piece-like body corner.
  • the four receiving corners 103 are formed from the wall surface of the wall 102 as a shape for preventing the corners of the semiconductor chip CP from contacting the receiving corners 103 in this way.
  • An example having an indented portion 104 recessed on the back side will be described as an example.
  • this invention is not limited to the aspect which has such a hollow part 104.
  • FIG. The recessed portion 104 of the present embodiment has a shape recessed in a semicircular shape, but is not particularly limited as long as the corner portion of the semiconductor chip CP and the accommodation corner portion 103 do not contact each other.
  • the shape of the recess 104 may be, for example, an ellipse or a polygon.
  • the hollow part 104 is not limited to the aspect formed in four corners as demonstrated in this embodiment, The hollow part 104 should just be formed in the at least 1 accommodation corner part 103.
  • FIG. for example, in the case of an alignment jig in which one recess 104 is formed, the recess 104 is formed in the same corner (for example, the first receiving corner 103a) in each recess 101. It is preferable that
  • the alignment jig 100 is preferably formed of a heat-resistant material.
  • the sealing member described later is a thermosetting resin
  • the curing temperature of the thermosetting resin is about 120 ° C. to 180 ° C. Therefore, it is preferable that the alignment jig 100 has heat resistance that does not cause deformation of the alignment jig even at the curing temperature of the thermosetting resin.
  • the material of the alignment jig 100 include metals and heat-resistant resins. Examples of the metal include copper, 42 alloy, and stainless steel. Examples of the heat resistant resin include a polyimide resin and a glass epoxy resin.
  • the manufacturing method of the alignment jig 100 is not particularly limited.
  • the alignment jig 100 can be manufactured by punching a plate-like member.
  • the alignment jig 100 can also be manufactured by etching a plate-like member. It is preferable to select a processing method as appropriate according to the dimensional accuracy required for the accommodating portion 101 and the recessed portion 104.
  • FIGS. 2A, 2B, and 2C (these may be collectively referred to as FIG. 2), the semiconductor chip CP as a piece is formed using the alignment jig 100 according to the present embodiment.
  • a plan view illustrating a method of aligning is shown.
  • FIG. 2A shows an alignment jig 100 placed on the holding surface of the holding member and a plan view illustrating a state in which the semiconductor chip CP is housed in the housing portion 101. Since the alignment jig 100 is placed on the holding surface of the holding member, the opening on the lower surface side of the housing portion 101 is blocked.
  • the semiconductor chip CP has a rectangular shape in plan view.
  • the semiconductor chip CP has a first side surface cp1 and a second side surface cp2 adjacent to the first side surface cp1. In FIG. 2A, the plurality of semiconductor chips CP are not aligned.
  • FIG. 2B is a plan view for explaining a state in which the alignment jig 100 is moved in the arrow direction 2B in the drawing and the wall portion 102 of the housing portion 101 is brought into contact with the side surface of the semiconductor chip CP.
  • the alignment jig 100 is moved in the arrow direction 2B, the first side surface cp1 of each semiconductor chip CP accommodated in the accommodating portion 101 and the first side wall 102a of the alignment jig 100 abut.
  • the plurality of semiconductor chips CP are aligned with each other at regular intervals with respect to the arrangement in the arrow direction 2B.
  • FIG. 2C shows a plan view for explaining a state in which the alignment jig 100 is moved in the arrow direction 2C in the drawing and the wall portion 102 of the housing portion 101 is brought into contact with the side surface of the semiconductor chip CP.
  • the arrow direction 2C is preferably orthogonal to the arrow direction 2B.
  • the chip corner portion cp3 of the semiconductor chip CP is accommodated in the recess 104 without contacting the first accommodation corner portion 103a. Since the chip corner portion cp3 of the semiconductor chip CP does not contact the first receiving corner portion 103a, the second side surface cp2 contacts the second side wall 102b while the first side surface cp1 of the semiconductor chip CP is along the first side wall 102a. .
  • the side surfaces adjacent to each other of the semiconductor chip CP can be brought into contact with the adjacent wall portions of the housing portion 101 without tilting the semiconductor chip CP.
  • the plurality of semiconductor chips CP are aligned at equal intervals with respect to the arrangement in the arrow direction 2B and the arrow direction 2C.
  • the alignment jig 300 includes a plurality of storage portions 301, and includes a wall portion 302 and a storage corner portion 303.
  • the wall 302 includes a first side wall 302a and a second side wall 302b adjacent to the first side wall 302a.
  • the shape of the accommodation corner portion 303 is different from the accommodation corner portion 103 of the alignment jig 100 according to the present embodiment, and the accommodation corner portion 303 does not have the hollow portion 104 and is inside the wall surface of the wall portion 102. Curved and overhangs.
  • FIG. 3A shows an alignment jig 300 placed on the holding surface of the holding member and a plan view for explaining a state in which the semiconductor chip CP is housed in the housing portion 301, as in FIG. 2A. Since the alignment jig 300 is placed on the holding surface of the holding member, the opening on the lower surface side of the housing portion 301 is blocked.
  • FIG. 3B is a plan view for explaining a state in which the alignment jig 300 is moved in the arrow direction 3B in the drawing and the wall portion 302 of the housing portion 301 is brought into contact with the side surface of the semiconductor chip CP.
  • the alignment jig 300 When the alignment jig 300 is moved in the arrow direction 3B, the first side surface cp1 of each semiconductor chip CP accommodated in the accommodating portion 301 and the first side wall 302a of the alignment jig 300 abut. As a result, the plurality of semiconductor chips CP are aligned with each other at regular intervals with respect to the arrangement in the arrow direction 3B.
  • FIG. 3C is a plan view for explaining the alignment state when the alignment jig 300 is moved in the direction of the arrow 3C in the drawing and the wall 302 of the housing 301 is brought into contact with the side surface of the semiconductor chip CP. It is shown.
  • the alignment jig 300 is moved in the arrow direction 3C, the semiconductor chip CP is brought into contact with the second side surface cp2 of each semiconductor chip CP accommodated in the accommodating portion 301 and the second side wall 302b of the alignment jig 300.
  • the chip corner portion cp3 comes into contact with the protruding portion of the housing corner portion 303, and the semiconductor chip CP is inclined.
  • the semiconductor chips CP can be evenly aligned without being inclined.
  • semiconductor device manufacturing method Next, a semiconductor device manufacturing method according to the present embodiment will be described.
  • the aforementioned semiconductor chip alignment step is performed during the steps of the semiconductor device manufacturing method.
  • FIG. 4A shows the semiconductor wafer W attached to the first pressure-sensitive adhesive sheet 10.
  • the semiconductor wafer W has a circuit surface W1, and a circuit W2 is formed on the circuit surface W1.
  • the first adhesive sheet 10 is attached to the back surface W3 of the semiconductor wafer W opposite to the circuit surface W1.
  • the semiconductor wafer W may be, for example, a silicon wafer or a compound semiconductor wafer such as gallium / arsenic. Examples of a method for forming the circuit W2 on the circuit surface W1 of the semiconductor wafer W include a widely used method, and examples include an etching method and a lift-off method.
  • the semiconductor wafer W is ground to a predetermined thickness in advance, and is attached to the first adhesive sheet 10 with the back surface W3 exposed.
  • the method for grinding the semiconductor wafer W is not particularly limited, and examples thereof include a known method using a grinder.
  • a surface protective sheet is adhered to the circuit surface W1 in order to protect the circuit W2.
  • the circuit surface W1 side of the semiconductor wafer W that is, the surface protection sheet side is fixed by a chuck table or the like, and the backside where no circuit is formed is ground by a grinder.
  • the thickness of the semiconductor wafer W after grinding is not particularly limited, and is usually 20 ⁇ m or more and 500 ⁇ m or less.
  • the first pressure-sensitive adhesive sheet 10 has a first base film 11 and a first pressure-sensitive adhesive layer 12.
  • the first pressure-sensitive adhesive layer 12 is laminated on the first base film 11.
  • the first adhesive sheet 10 may be attached to the semiconductor wafer W and the first ring frame. In this case, the first ring frame and the semiconductor wafer W are placed on the first pressure-sensitive adhesive layer 12 of the first pressure-sensitive adhesive sheet 10, and the first ring frame and the semiconductor wafer W are lightly pressed, One ring frame and the semiconductor wafer W are fixed to the first adhesive sheet 10.
  • the material of the first base film 11 is not particularly limited.
  • Examples of the material of the first base film 11 include polyvinyl chloride resin, polyester resin (polyethylene terephthalate, etc.), acrylic resin, polycarbonate resin, polyethylene resin, polypropylene resin, acrylonitrile / butadiene / styrene resin, polyimide resin, and polyurethane. Examples thereof include resins and polystyrene resins.
  • the pressure-sensitive adhesive contained in the first pressure-sensitive adhesive layer 12 is not particularly limited, and various types of pressure-sensitive adhesives can be applied to the first pressure-sensitive adhesive layer 12.
  • Examples of the pressure-sensitive adhesive contained in the first pressure-sensitive adhesive layer 12 include rubber-based, acrylic-based, silicone-based, polyester-based, and urethane-based materials.
  • the kind of adhesive is selected in consideration of the use and the kind of adherend to be attached.
  • the first pressure-sensitive adhesive layer 12 When the energy ray polymerizable compound is blended in the first pressure-sensitive adhesive layer 12, the first pressure-sensitive adhesive layer 12 is irradiated with energy rays from the first base film 11 side, and the energy ray polymerizable compound is irradiated. Is cured. When the energy beam polymerizable compound is cured, the cohesive force of the first pressure-sensitive adhesive layer 12 is increased, and the pressure-sensitive adhesive force between the first pressure-sensitive adhesive layer 12 and the semiconductor wafer W can be reduced or eliminated. Examples of the energy rays include ultraviolet rays (UV) and electron beams (EB), and ultraviolet rays are preferable.
  • UV ultraviolet rays
  • EB electron beams
  • the method for reducing or eliminating the adhesive force between the first adhesive layer 12 and the semiconductor wafer W is not limited to energy beam irradiation.
  • Examples of the method for reducing or eliminating the adhesive force include a method using heating, a method using heating and energy ray irradiation, and a method using cooling.
  • Examples of the cooling method include a method in which the first pressure-sensitive adhesive sheet 10 is cooled to change the crystal structure of the polymer used in the first pressure-sensitive adhesive layer 12 to change the adhesive force.
  • FIG. 4B shows a plurality of semiconductor chips CP held on the first pressure-sensitive adhesive sheet 10.
  • the semiconductor wafer W held on the first adhesive sheet 10 is divided into pieces by dicing, and a plurality of semiconductor chips CP are formed.
  • a cutting means such as a dicing saw is used for dicing.
  • the cutting depth at the time of dicing is set to a depth that takes into account the sum of the thickness of the semiconductor wafer W and the thickness of the first pressure-sensitive adhesive layer 12 and the amount of wear of the dicing saw.
  • the first pressure-sensitive adhesive layer 12 is also cut into the same size as the semiconductor chip CP by dicing. Furthermore, a cut may be formed in the first base film 11 by dicing.
  • the method for dicing the semiconductor wafer W is not limited to the method using a dicing saw.
  • the semiconductor wafer W may be diced by a laser irradiation method.
  • Irradiation of energy rays to the first pressure-sensitive adhesive layer 12 is performed at any stage after the semiconductor wafer W is adhered to the first pressure-sensitive adhesive sheet 10 and before the first pressure-sensitive adhesive sheet 10 is peeled off. May be. Irradiation of energy rays may be performed after dicing, for example, or may be performed after an expanding step described later. You may irradiate an energy ray in multiple times.
  • FIG. 4C shows a diagram illustrating a process of extending the first adhesive sheet 10 that holds a plurality of semiconductor chips CP (sometimes referred to as a first expanding process). After dicing into several semiconductor chips CP by dicing, the 1st adhesive sheet 10 is extended and the space
  • the method for extending the first pressure-sensitive adhesive sheet 10 in the first expanding step is not particularly limited.
  • a method of extending the first pressure-sensitive adhesive sheet 10 for example, a method of extending the first pressure-sensitive adhesive sheet 10 by pressing an annular expander or a circular expander against the first pressure-sensitive adhesive sheet 10, and a gripping member
  • a method of stretching the first pressure-sensitive adhesive sheet 10 by gripping the outer peripheral portion of the first pressure-sensitive adhesive sheet 10 may be used.
  • the distance between the semiconductor chips CP after the first expanding process is D1.
  • the distance D1 is preferably 15 ⁇ m or more and 110 ⁇ m or less, for example.
  • FIG. 5A shows a diagram for explaining a process of transferring a plurality of semiconductor chips CP to the second pressure-sensitive adhesive sheet 20 (sometimes referred to as a first transfer process) after the first expanding process. Yes.
  • the first pressure-sensitive adhesive sheet 10 is stretched to increase the distance between the plurality of semiconductor chips CP to the distance D1, and then the second pressure-sensitive adhesive sheet 20 is adhered to the circuit surface W1 of the semiconductor chip CP.
  • the second pressure-sensitive adhesive sheet 20 has a second base film 21 and a second pressure-sensitive adhesive layer 22. It is preferable that the 2nd adhesive sheet 20 is stuck so that the circuit surface W1 may be covered with the 2nd adhesive layer 22.
  • the material of the second base film 21 is not particularly limited. Examples of the material of the second base film 21 include the same materials as those exemplified for the first base film 11.
  • the second pressure-sensitive adhesive layer 22 is laminated on the second base film 21.
  • the pressure-sensitive adhesive contained in the second pressure-sensitive adhesive layer 22 is not particularly limited, and various types of pressure-sensitive adhesives can be applied to the second pressure-sensitive adhesive layer 22.
  • the kind of adhesive is selected in consideration of the use and the kind of adherend to be attached.
  • the second pressure-sensitive adhesive layer 22 may also contain an energy ray polymerizable compound.
  • the second adhesive sheet 20 preferably has a smaller tensile elastic modulus than the first adhesive sheet 10.
  • the tensile modulus of the second pressure-sensitive adhesive sheet 20 is preferably 10 MPa or more and 2000 MPa or less.
  • the breaking elongation of the second pressure-sensitive adhesive sheet 20 is also preferably 50% or more.
  • the tensile elasticity modulus and breaking elongation in this specification are measured using a tensile test apparatus based on JIS K7161 and JIS K7127.
  • the adhesive force of the second adhesive layer 22 is larger than the adhesive force of the first adhesive layer 12. If the adhesive force of the second pressure-sensitive adhesive layer 22 is greater, the first pressure-sensitive adhesive sheet 10 can be easily peeled after the plurality of semiconductor chips CP are transferred to the second pressure-sensitive adhesive sheet 20.
  • the second pressure-sensitive adhesive sheet 20 preferably has heat resistance.
  • the sealing member described later is a thermosetting resin, for example, the curing temperature of the thermosetting resin is about 120 ° C. to 180 ° C., and the heating time is about 30 minutes to 2 hours.
  • the second pressure-sensitive adhesive sheet 20 preferably has heat resistance such that wrinkles do not occur when the sealing member is thermoset.
  • the 2nd adhesive sheet 20 is comprised with the material which can peel from the semiconductor chip CP after a thermosetting process.
  • the second adhesive sheet 20 may be attached to the second ring frame.
  • the second ring frame is placed on the second pressure-sensitive adhesive layer 22 of the second pressure-sensitive adhesive sheet 20, the second ring frame is lightly pressed, and the second ring frame is moved to the second pressure frame. Fix to the adhesive sheet 20. Thereafter, the second pressure-sensitive adhesive layer 22 exposed inside the ring shape of the second ring frame is pressed against the circuit surface W1 of the semiconductor chip CP to fix the plurality of semiconductor chips CP to the second pressure-sensitive adhesive sheet 20. To do.
  • the “MD direction” is used as a term indicating a direction parallel to the longitudinal direction of the original fabric that gives the base film (the feed direction during production of the original fabric).
  • MD is an abbreviation for Machine Direction.
  • the amount of extension extending along a direction that is easily stretched in the first expanding step (sometimes referred to as a first direction) and a direction orthogonal to the first direction (a direction that is less likely to stretch than the first direction).
  • the second expanding step may be referred to as the second direction.)
  • the amount of extension extending along the second direction is different, the direction in which the second base film 21 is easily extended is matched with the second direction.
  • the amount of extension in the second direction can be made larger than that in the first direction, and the intervals between the plurality of semiconductor chips CP can be adjusted more uniformly.
  • the semiconductor chips CP are divided into pieces along the grid-like division lines, according to this aspect, the intervals between the semiconductor chips CP are more uniformly expanded in the vertical direction and the horizontal direction. Is done.
  • the first pressure-sensitive adhesive sheet 10 When the first pressure-sensitive adhesive sheet 10 is peeled after the second pressure-sensitive adhesive sheet 20 is attached to the plurality of semiconductor chips CP, the back surfaces W3 of the plurality of semiconductor chips CP are exposed. Even after the first pressure-sensitive adhesive sheet 10 is peeled, it is preferable that the distance D1 between the plurality of semiconductor chips CP expanded in the first expanding step is maintained.
  • the energy ray polymerizable compound is blended in the first pressure-sensitive adhesive layer 12, the first pressure-sensitive adhesive layer 12 is irradiated with energy rays from the first base film 11 side, and the energy ray polymerizable compound is irradiated. It is preferable to peel the first pressure-sensitive adhesive sheet 10 after curing.
  • FIG. 5B shows a diagram illustrating a process of extending the second adhesive sheet 20 that holds a plurality of semiconductor chips CP (sometimes referred to as a second expanding process).
  • the interval between the plurality of semiconductor chips CP is further expanded.
  • the method of extending the second adhesive sheet 20 in the second expanding step is not particularly limited. Examples of the method of stretching the second pressure-sensitive adhesive sheet 20 include a method of pressing a ring-shaped expander or a circular expander against the second pressure-sensitive adhesive sheet 20 to stretch the second pressure-sensitive adhesive sheet 20, and a gripping member. For example, a method of stretching the second pressure-sensitive adhesive sheet 20 by gripping the outer peripheral portion of the second pressure-sensitive adhesive sheet 20 may be used.
  • the interval between the semiconductor chips CP after the second expanding process is D2.
  • the distance D2 is larger than the distance D1.
  • the distance D2 is preferably 200 ⁇ m or more and 5000 ⁇ m or less.
  • FIG. 6A shows a diagram for explaining a process of transferring a plurality of semiconductor chips CP onto the holding surface of the holding member (sometimes referred to as a second transfer process) after the second expanding process.
  • FIG. 6A shows a plurality of semiconductor chips CP transferred to the holding member 200.
  • the holding member 200 has a holding surface 201 that can hold the semiconductor chip CP by suction.
  • the semiconductor chip CP is adsorbed and held on the holding surface 201 by decompression means (not shown).
  • the holding surface 201 is preferably a flat surface, and preferably has a plurality of suction holes so that the semiconductor chip CP can be sucked and held.
  • Examples of the decompression means include a decompression pump and a vacuum ejector.
  • the back surfaces W ⁇ b> 3 of the plurality of semiconductor chips CP held on the second adhesive sheet 20 are placed toward the holding surface 201.
  • the plurality of semiconductor chips CP placed on the holding surface 201 have their back surfaces W3 in contact with the holding surface 201.
  • the plurality of semiconductor chips CP are attracted and held on the holding surface 201 by driving the decompression means. It is preferable that the second adhesive sheet 20 is peeled after the plurality of semiconductor chips CP are attracted and held on the holding surface 201.
  • FIG. 6B is a diagram illustrating a process of placing the alignment jig 100 on the holding surface 201 of the holding member 200 (sometimes referred to as a jig placing process).
  • the alignment jig 100 is placed on the holding surface 201 so that the semiconductor chip CP held on the holding surface 201 is accommodated in the accommodating portion 101.
  • the opening on the lower surface side of the housing portion 101 is closed.
  • the alignment jig 100 in which the housing portions 101 are arranged in a lattice shape from the viewpoint of easily housing the semiconductor chips CP in the housing portion 101.
  • a semiconductor chip alignment process for aligning the plurality of semiconductor chips CP using the alignment jig 100 is performed.
  • the semiconductor chip alignment step can be performed in the same manner as the semiconductor chip alignment method described above.
  • an example of a method of moving the alignment jig 100 and bringing the wall portion 102 of the housing portion 101 into contact with the side surface of the semiconductor chip CP will be described as an example.
  • the outer frame 110 ⁇ / b> A of the main body 110 of the alignment jig 100 is gripped using the gripping means.
  • the gripping means is connected to a driving device (not shown).
  • the alignment jig 100 is moved by this driving device, and the wall 102 of the alignment jig 100 is brought into contact with the side surface of the semiconductor chip CP.
  • the order and direction in which the alignment jig 100 is moved are not limited to the order and direction of the arrow direction 2B in FIG. 2B and the arrow direction 2C in FIG. 2C.
  • the driving device is configured to be able to move the alignment jig 100 in any direction along the holding surface 201.
  • the alignment jig 100 is preferably moved away from the holding surface 201 and moved along the holding surface 201. Further, the alignment jig 100 may be moved while being in contact with the holding surface 201.
  • the semiconductor chip CP can be easily moved by releasing the suction holding by the decompression unit of the holding member 200 or reducing the suction holding force.
  • the driving device may have a detection unit (not shown). The position of the semiconductor chip CP placed on the holding surface 201 may be detected by the detection means.
  • the drive device may include a control unit that controls the movement amount and the movement direction of the semiconductor chip CP based on the detection result of the detection unit. In the driving device, the gripping means, the detection means, and the control means may be interlocked.
  • the method for aligning the plurality of semiconductor chips CP is not limited to the method described above.
  • a method of moving the holding member 200 and bringing the alignment jig 100 into contact with the semiconductor chip CP may be used instead of moving the alignment jig 100.
  • a method of aligning the plurality of semiconductor chips CP a method of moving both the alignment jig 100 and the holding member 200 and bringing the alignment jig 100 into contact with the semiconductor chip CP may be used.
  • FIG. 7A is a diagram for explaining a step (sometimes referred to as a third transfer step) of transferring the semiconductor chips CP aligned in the semiconductor chip alignment step to the surface protection sheet 40 as a fourth adhesive sheet. It is shown.
  • a surface protection sheet 40 is attached to the circuit surface W1 of the aligned semiconductor chips CP.
  • the semiconductor chip CP is attached to the surface protective sheet 40, but the alignment jig 100 is not attached to the surface protective sheet 40.
  • the surface protection sheet 40 includes a fourth base film 41 and a fourth pressure-sensitive adhesive layer 42. It is preferable that the surface protection sheet 40 is stuck so that the circuit surface W1 may be covered with the fourth pressure-sensitive adhesive layer 42.
  • the material of the surface protection sheet 40 is not particularly limited. Examples of the material of the fourth base film 41 include the same materials as those exemplified for the first base film 11.
  • the fourth pressure-sensitive adhesive layer 42 is laminated on the fourth base film 41.
  • the pressure-sensitive adhesive contained in the fourth pressure-sensitive adhesive layer 42 is not particularly limited, and various types of pressure-sensitive adhesives can be applied to the fourth pressure-sensitive adhesive layer 42. As an adhesive contained in the 4th adhesive layer 42, the adhesive similar to the adhesive demonstrated about the 1st adhesive layer 12 is mentioned, for example. In addition, the kind of adhesive is selected in consideration of the use and the kind of adherend to be attached.
  • the fourth pressure-sensitive adhesive layer 42 may also contain an energy ray polymerizable compound.
  • the surface protective sheet 40 preferably has heat resistance.
  • the curing temperature of the thermosetting resin is about 120 ° C. to 180 ° C., and the heating time is about 30 minutes to 2 hours.
  • the surface protective sheet 40 preferably has heat resistance so that wrinkles do not occur when the sealing member is thermally cured.
  • the surface protection sheet 40 is comprised with the material which can peel from the semiconductor chip CP after a thermosetting process.
  • FIG. 7B shows a diagram illustrating a process of sealing a plurality of semiconductor chips CP held by the surface protection sheet 40 (sometimes referred to as a sealing process).
  • the sealing body 3 is formed by covering the plurality of semiconductor chips CP with the sealing member 60 while leaving the circuit surface W1.
  • the sealing member 60 is also filled between the plurality of semiconductor chips CP.
  • the circuit surface W1 and the circuit W2 are covered with the surface protection sheet 40, it is possible to prevent the circuit surface W1 from being covered with the sealing member 60.
  • the sealing body 3 in which a plurality of semiconductor chips CP separated by a predetermined distance are embedded in the sealing member is obtained.
  • the plurality of semiconductor chips CP are preferably covered with the sealing member 60 while the distance D2 is maintained.
  • the method for covering the plurality of semiconductor chips CP with the sealing member 60 is not particularly limited. For example, a method is adopted in which a plurality of semiconductor chips CP are accommodated in a mold while the circuit surface W1 is covered with the surface protection sheet 40, a fluid resin material is injected into the mold, and the resin material is cured. May be.
  • a method of embedding the plurality of semiconductor chips CP in the sealing resin by placing the sheet-shaped sealing resin so as to cover the back surfaces W3 of the plurality of semiconductor chips CP and heating the sealing resin is adopted. May be.
  • the material of the sealing member 60 include an epoxy resin.
  • the epoxy resin used as the sealing member 60 may include, for example, a phenol resin, an elastomer, an inorganic filler, a curing accelerator, and the like.
  • FIG. 8 semiconductor package manufacturing process 8A, 8B, and 8C (these may be collectively referred to as FIG. 8), and FIGS. 9A, 9B, and 9C (these may be collectively referred to as FIG. 9).
  • the figure explaining the process of manufacturing a semiconductor package using this semiconductor chip CP is shown.
  • the present embodiment preferably includes a manufacturing process of such a semiconductor package.
  • FIG. 8A shows a cross-sectional view of the sealing body 3 after the surface protective sheet 40 is peeled off.
  • rewiring layer forming step rewirings connected to the circuits W2 of the plurality of exposed semiconductor chips CP are formed on the circuit surface W1 and the surface 3S of the sealing body 3.
  • an insulating layer is formed on the sealing body 3.
  • FIG. 8B is a cross-sectional view illustrating a process of forming the first insulating layer 61 on the circuit surface W1 of the semiconductor chip CP and the surface 3S of the sealing body 3.
  • a first insulating layer 61 containing an insulating resin is formed on the circuit surface W1 and the surface 3S so as to expose the circuit W2 or the internal terminal electrode W4 of the circuit W2.
  • the insulating resin include polyimide resin, polybenzoxazole resin, and silicone resin.
  • the material of the internal terminal electrode W4 is not limited as long as it is a conductive material, and examples thereof include metals such as gold, silver, copper, and aluminum, and alloys.
  • FIG. 8C is a cross-sectional view illustrating a process of forming the rewiring 5 that is electrically connected to the semiconductor chip CP sealed in the sealing body 3.
  • the rewiring 5 is formed following the formation of the first insulating layer 61.
  • the material of the rewiring 5 is not limited as long as it is a conductive material, and examples thereof include metals such as gold, silver, copper, and aluminum, and alloys.
  • the rewiring 5 can be formed by a known method.
  • FIG. 9A is a cross-sectional view illustrating a process of forming the second insulating layer 62 that covers the rewiring 5.
  • the rewiring 5 has external electrode pads 5A for external terminal electrodes. An opening or the like is provided in the second insulating layer 62 to expose the external electrode pad 5A for the external terminal electrode.
  • the external electrode pad 5A is exposed in the region of the semiconductor chip CP of the sealing body 3 (region corresponding to the circuit surface W1) and outside the region (region corresponding to the surface 3S on the sealing member 60). I am letting.
  • the rewiring 5 is formed on the surface 3S of the sealing body 3 so that the external electrode pads 5A are arranged in an array.
  • the sealing body 3 since the sealing body 3 has a structure in which the external electrode pad 5A is exposed outside the region of the semiconductor chip CP, a fan-out type WLP can be obtained.
  • FIG. 9B is a cross-sectional view illustrating a process of connecting the external terminal electrode to the external electrode pad 5A of the sealing body 3.
  • An external terminal electrode 7 such as a solder ball is placed on the external electrode pad 5A exposed from the second insulating layer 62, and the external terminal electrode 7 and the external electrode pad 5A are electrically connected by solder bonding or the like.
  • the material of the solder ball is not particularly limited, and examples thereof include lead-containing solder and lead-free solder.
  • FIG. 9C shows a cross-sectional view illustrating a process of separating the sealing body 3 to which the external terminal electrode 7 is connected (sometimes referred to as a second dicing process).
  • the sealing body 3 is separated into individual semiconductor chips CP.
  • the method for dividing the sealing body 3 into individual pieces is not particularly limited.
  • the sealing body 3 can be separated into pieces by adopting a method similar to the method of dicing the semiconductor wafer W described above.
  • the step of dividing the sealing body 3 into pieces may be performed by sticking the sealing body 3 to an adhesive sheet such as a dicing sheet.
  • the semiconductor package 1 of the semiconductor chip CP unit is manufactured by separating the sealing body 3 into pieces. As described above, the semiconductor package 1 in which the external terminal electrode 7 is connected to the external electrode pad 5A fanned out outside the region of the semiconductor chip CP is manufactured as a fan-out type wafer level package (FO-WLP).
  • FO-WLP fan-out type wafer level package
  • the chip corner portion cp3 of the semiconductor chip CP is difficult to contact the receiving corner portion 103 of the alignment jig 100. Therefore, it is possible to prevent damage to apexes such as corners of the semiconductor chip CP.
  • the alignment jig 100 and the alignment method according to the present embodiment are more preferable from the viewpoint of preventing damage to the semiconductor chip CP.
  • the manufacturing method of the semiconductor device in order to perform the alignment method using the alignment jig 100 in the semiconductor chip alignment step, after aligning the plurality of semiconductor chips CP at equal intervals, A sealing process and a semiconductor packaging process can be implemented. Therefore, in the sealing body 3, the plurality of semiconductor chips CP are sealed at a more even interval. Further, since the plurality of semiconductor chips CP are sealed at equal intervals, it is possible to suppress the displacement of the connection position between the circuit W2 of the plurality of semiconductor chips CP and the rewiring 5 in the rewiring layer forming step.
  • the manufacturing method of the semiconductor device according to the present embodiment is excellent in adaptability to the process of manufacturing the FO-WLP type semiconductor package 1. Specifically, according to the present embodiment, the uniformity and accuracy of the chip interval in the FO-WLP type semiconductor package 1 can be improved.
  • the manufacturing method of the semiconductor device includes the semiconductor according to the first embodiment from the step of dividing into semiconductor chips CP using the semiconductor wafer W to the step of widening the interval between the plurality of semiconductor chips CP. Mainly different from the manufacturing method of the apparatus.
  • the other points are the same as those in the second embodiment and the first embodiment, and thus the description is omitted or simplified. Note that the alignment jig and alignment method described in the first embodiment are also applied in this embodiment.
  • FIG. 10A shows a diagram for explaining a process of forming a groove having a predetermined depth from the circuit surface W1 side of the semiconductor wafer W (sometimes referred to as a groove forming process).
  • the semiconductor wafer W has a circuit surface W1 as a first surface.
  • a circuit W2 is formed on the circuit surface W1.
  • the semiconductor wafer is cut from the circuit surface W1 side using a dicing blade of a dicing apparatus.
  • a groove W5 is formed by making a cut with a depth shallower than the thickness of the semiconductor wafer W from the circuit surface W1 of the semiconductor wafer W.
  • the groove W5 is formed so as to partition a plurality of circuits W2 formed on the circuit surface W1 of the semiconductor wafer W.
  • the depth of the groove W5 is not particularly limited as long as it is a little deeper than the thickness of the target semiconductor chip.
  • FIG. 10B shows a semiconductor wafer W in which a protective sheet 30 as a third adhesive sheet is adhered to the circuit surface W1 after the formation of the groove W5.
  • the protective sheet 30 is attached to the circuit surface W1 of the semiconductor wafer W before the semiconductor wafer W is ground in the next grinding step.
  • the protection sheet 30 protects the circuit surface W1 and the circuit W2.
  • the protective sheet 30 has a third base film 31 and a third pressure-sensitive adhesive layer 32.
  • the third pressure-sensitive adhesive layer 32 is laminated on the third base film 31.
  • the material of the third base film 31 is not particularly limited.
  • Examples of the material of the third base film 31 include polyvinyl chloride resin, polyester resin (polyethylene terephthalate, etc.), acrylic resin, polycarbonate resin, polyethylene resin, polypropylene resin, acrylonitrile / butadiene / styrene resin, polyimide resin, and polyurethane resin. Examples thereof include resins and polystyrene resins.
  • the pressure-sensitive adhesive contained in the third pressure-sensitive adhesive layer 32 is not particularly limited, and various types of pressure-sensitive adhesives can be applied to the third pressure-sensitive adhesive layer 32.
  • Examples of the pressure-sensitive adhesive contained in the third pressure-sensitive adhesive layer 32 include a rubber-based pressure-sensitive adhesive, an acrylic pressure-sensitive adhesive, a silicone-based pressure-sensitive adhesive, a polyester-based pressure-sensitive adhesive, and a urethane-based pressure-sensitive adhesive.
  • the kind of adhesive is selected in consideration of the use and the kind of adherend to be attached.
  • the third pressure-sensitive adhesive layer 32 is irradiated with energy rays from the third base film 31 side, and the energy ray polymerizable compound is irradiated. Is cured.
  • the energy beam polymerizable compound is cured, the cohesive force of the third pressure-sensitive adhesive layer 32 increases, and the pressure-sensitive adhesive force between the third pressure-sensitive adhesive layer 32 and the semiconductor wafer W decreases or disappears.
  • the energy rays include ultraviolet rays (UV) and electron beams (EB), and ultraviolet rays are preferable.
  • the method described in the first embodiment can be adopted as a method for reducing or eliminating the adhesive force.
  • FIG. 10C is a diagram for explaining a process of grinding the back surface W6 as the second surface of the semiconductor wafer W after forming the groove W5 and attaching the protective sheet 30 (sometimes referred to as a grinding process). It is shown. After sticking the protective sheet 30, the semiconductor wafer W is ground from the back surface W6 side using the grinder 50. By grinding, the thickness of the semiconductor wafer W is reduced, and finally the semiconductor wafer W is divided into a plurality of semiconductor chips CP. Grinding is performed from the back surface W6 side until the bottom of the groove W5 is removed, and the semiconductor wafer W is separated into pieces for each circuit W2. Thereafter, back grinding is further performed as necessary to obtain a semiconductor chip CP having a predetermined thickness. In this embodiment, grinding is performed until the back surface W3 as the third surface is exposed.
  • FIG. 10D shows a state where a plurality of divided semiconductor chips CP are held on the protective sheet 30.
  • the semiconductor chip CP with the back surface W3 exposed is held on the protective sheet 30.
  • FIG. 11A shows a diagram for explaining a step of sticking the second adhesive sheet 20 to a plurality of semiconductor chips CP (sometimes referred to as a sticking step) after the grinding step.
  • the second adhesive sheet 20 is attached to the back surface W3 of the semiconductor chip CP.
  • the second pressure-sensitive adhesive sheet 20 has a second base film 21 and a second pressure-sensitive adhesive layer 22.
  • the 2nd adhesive sheet 20 is the same as that of 1st Embodiment.
  • the adhesive force of the second adhesive layer 22 to the semiconductor wafer W is preferably larger than the adhesive force of the third adhesive layer 32 to the semiconductor wafer W. If the adhesive force of the second pressure-sensitive adhesive layer 22 is larger, the protective sheet 30 can be easily peeled off.
  • the second adhesive sheet 20 may be attached to the first ring frame.
  • the first ring frame is placed on the second pressure-sensitive adhesive layer 22 of the second pressure-sensitive adhesive sheet 20, and the first ring frame is lightly pressed, The adhesive sheet 20 and the first ring frame are fixed. Thereafter, the second adhesive layer 22 exposed inside the ring shape of the first ring frame is pressed against the back surface W3 of the semiconductor chip CP, and the plurality of semiconductor chips CP are fixed to the second adhesive sheet 20. .
  • FIG. 11B shows a diagram illustrating a process of peeling the protective sheet 30 (sometimes referred to as a peeling process) after the second pressure-sensitive adhesive sheet 20 is attached to the plurality of semiconductor chips CP.
  • the protective sheet 30 is peeled off, the circuit surfaces W1 of the plurality of semiconductor chips CP are exposed.
  • the distance between the semiconductor chips CP divided by the previous dicing method is D3.
  • the distance D3 is preferably 15 ⁇ m or more and 110 ⁇ m or less, for example.
  • FIG. 11C shows a diagram illustrating a process of stretching the second adhesive sheet 20 that holds the plurality of semiconductor chips CP.
  • the method for extending the second pressure-sensitive adhesive sheet 20 in the expanding step is not particularly limited.
  • Examples of the method for stretching the second pressure-sensitive adhesive sheet 20 include a method of stretching the second pressure-sensitive adhesive sheet 20 by pressing an annular expander or a circular expander against the second pressure-sensitive adhesive sheet 20, and a gripping member.
  • a method of stretching the second pressure-sensitive adhesive sheet 20 by gripping the outer peripheral portion of the second pressure-sensitive adhesive sheet 20 using the above-mentioned method is exemplified.
  • the distance between the semiconductor chips CP after the expanding process is D4.
  • the distance D4 is larger than the distance D3.
  • the distance D4 is preferably, for example, 200 ⁇ m or more and 5000 ⁇ m or less.
  • FIG. 12A shows a diagram for explaining a process of transferring the semiconductor chip CP to the surface protection sheet 40 as a fourth pressure-sensitive adhesive sheet (sometimes referred to as a fourth transfer process) after the expanding process.
  • the surface protection sheet 40 is the same as in the first embodiment.
  • the surface protection sheet 40 is attached to the circuit surfaces W1 of the plurality of semiconductor chips CP.
  • FIG. 12B shows a diagram illustrating a process of peeling the second adhesive sheet 20 from the plurality of semiconductor chips CP. By peeling off the second adhesive sheet 20, the back surface W3 of the semiconductor chip CP is exposed.
  • the steps after the semiconductor chip alignment step can be performed in the same manner as in the first embodiment.
  • the semiconductor wafer W is divided into a plurality of semiconductor chips CP by a so-called tip dicing method, disorder of the alignment state of the semiconductor chips CP when separated into pieces can be prevented.
  • a plurality of semiconductor chips CP separated by the tip dicing method are attached to the second pressure-sensitive adhesive sheet 20, and the second pressure-sensitive adhesive sheet 20 is stretched to form a plurality of semiconductor chips CP. The distance between each other can be increased. Also in the expanding process, it is possible to prevent disorder of the alignment state of the plurality of semiconductor chips CP.
  • the sealing process after sealing the plurality of semiconductor chips CP transferred to the surface protection sheet 40 is performed in the first embodiment.
  • This is mainly different from the manufacturing method of the semiconductor device.
  • the other points are the same as those in the third embodiment and the first embodiment, and thus the description is omitted or simplified. Note that the alignment jig and alignment method described in the first embodiment are also applied in this embodiment.
  • FIG. 13A shows a diagram illustrating a step of attaching the frame member 400 to the fourth pressure-sensitive adhesive layer 42 of the surface protection sheet 40 (sometimes referred to as a frame member attachment step).
  • the frame member attaching step is preferably performed after the third transfer step shown in FIG. 7A of the first embodiment.
  • the frame member 400 is attached to the surface protection sheet 40 to which the semiconductor chip CP is transferred.
  • the surface protection sheet 40 is the same as in the first embodiment.
  • the frame member 400 according to the present embodiment is formed in a lattice shape and has a plurality of openings 401.
  • the frame member 400 is preferably formed of a material having heat resistance. Examples of the material of the frame member 400 include metals and heat resistant resins.
  • the opening 401 is a hole that penetrates the front and back surfaces of the frame member 400.
  • the shape of the opening 401 is not particularly limited as long as the semiconductor chip CP can be accommodated in the frame.
  • the depth of the hole of the opening 401 is not particularly limited as long as the semiconductor chip CP can be accommodated.
  • FIG. 13B is a diagram illustrating a process of sealing the semiconductor chip CP and the frame member 400 that are adhered to the surface protection sheet 40.
  • the material of the sealing resin 63 is a thermosetting resin, and examples thereof include an epoxy resin.
  • the epoxy resin used as the sealing resin 63 may include, for example, a phenol resin, an elastomer, an inorganic filler, a curing accelerator, and the like.
  • the sealing body 3D is formed by covering the semiconductor chip CP and the frame member 400 with the sealing resin 63.
  • a method for sealing the semiconductor chip CP and the frame member 400 with the sealing resin 63 is not particularly limited. For example, a method using a sheet-like sealing resin can be mentioned.
  • a sheet-shaped sealing resin is placed so as to cover the semiconductor chip CP and the frame member 400, and the sealing resin is heated and cured to form a sealing resin layer.
  • a sheet-like sealing resin it is preferable to seal the semiconductor chip CP and the frame member 400 by a vacuum laminating method.
  • the temperature condition range for heat curing by the vacuum laminating method is, for example, 80 ° C. or more and 120 ° C. or less.
  • the semiconductor package manufacturing process and subsequent steps can be performed in the same manner as in the first embodiment.
  • the semiconductor device manufacturing method according to the present embodiment is the first embodiment in that the alignment jig 100 is placed on the holding surface 201 of the holding member 200 in advance before transferring the plurality of semiconductor chips CP to the holding member 200. Mainly different from the manufacturing method of the semiconductor device according to the embodiment. Since the other points are the same as those in the first embodiment, the description thereof will be omitted or simplified. Note that the alignment jig and alignment method described in the first embodiment are also applied in this embodiment.
  • FIG. 14A is a diagram illustrating a process of placing the alignment jig 100 on the holding surface 201 of the holding member 200.
  • the jig placement step of this embodiment is different from the jig placement step of the first embodiment in that a plurality of semiconductor chips CP are not transferred to the holding surface 201 in advance.
  • the alignment jig 100 is preferably held by suction on the holding surface 201. Since the jig mounting process of the present embodiment is the same as that of the first embodiment in other respects, the description thereof is omitted.
  • FIG. 14B is a diagram illustrating a process of transferring a plurality of semiconductor chips CP onto the holding surface 201 of the holding member 200 after the second expanding process (see FIG. 5B) described in the first embodiment. Yes.
  • the transfer process of this embodiment is different from the second transfer process of the first embodiment in that the alignment jig 100 is placed on the holding surface 201 in advance.
  • the back surfaces W3 of the plurality of semiconductor chips CP held on the second adhesive sheet 20 are placed toward the holding surface 201.
  • the semiconductor chip CP is placed so as to be accommodated in the accommodating portion 101 of the alignment jig 100.
  • the alignment jig 100 by holding the alignment jig 100 on the holding surface 201, it is possible to prevent the alignment jig 100 from moving on the holding surface 201 during the transfer process.
  • the contact between the semiconductor chip CP and the alignment jig 100 can be prevented by preventing the movement of the alignment jig.
  • FIG. 14C is a diagram illustrating a process of peeling the second adhesive sheet 20 from the semiconductor chip CP after placing the semiconductor chip CP on the holding surface.
  • the second adhesive sheet 20 is peeled off, it is preferable to drive the decompression unit to suck and hold the plurality of semiconductor chips CP on the holding surface 201.
  • the alignment jig 100 is also held by suction on the holding surface 201.
  • the step of aligning the semiconductor chips CP can be performed in the same manner as the semiconductor chip alignment step of the first embodiment.
  • the steps after the semiconductor chip alignment step can be performed in the same manner as in the first embodiment.
  • the semiconductor device manufacturing method according to the present embodiment is the first embodiment in that after aligning a plurality of semiconductor chips CP, not only the semiconductor chips CP but also the alignment jig 100 is transferred to the surface protection sheet 40 together. Mainly different from the manufacturing method of the semiconductor device according to the embodiment. Since the other points are the same as those in the first embodiment, the description thereof will be omitted or simplified. Note that the alignment jig and alignment method described in the first embodiment are also applied in this embodiment.
  • FIG. 15A is a diagram illustrating a process of transferring the semiconductor chip CP and the alignment jig 100 aligned in the semiconductor chip alignment process to the surface protection sheet 40.
  • the transfer process of this embodiment is preferably performed after the semiconductor chip alignment process of the first embodiment or the third embodiment.
  • the surface protection sheet 40 is attached to the circuit surface W1 of the aligned semiconductor chips CP and the alignment jig 100.
  • the plurality of semiconductor chips CP and the alignment jig 100 be held by suction on the holding surface 201. After sticking, the semiconductor chip CP and the alignment jig 100 are separated from the holding surface 201 of the holding member 200.
  • FIG. 15B is a diagram illustrating a process of sealing the plurality of semiconductor chips CP and the alignment jig 100 held by the surface protection sheet 40.
  • the sealing body 3E is formed by covering the semiconductor chip CP and the alignment jig 100 with the sealing member 60.
  • the sealing member 60 is also filled around the semiconductor chip CP accommodated in the accommodating portion 101 of the alignment jig 100.
  • the sealing method is the same as described above.
  • the semiconductor package manufacturing process and subsequent steps can be performed in the same manner as in the first embodiment.
  • the method for manufacturing a semiconductor device includes a step of manufacturing a semiconductor package after aligning a plurality of semiconductor chips CP and sealing the plurality of semiconductor chips CP transferred to the surface protection sheet 40. Mainly different from the manufacturing method of the semiconductor device according to the embodiment. Since the other points are the same as those in the first embodiment, the description thereof will be omitted or simplified. Note that the alignment jig and alignment method described in the first embodiment are also applied in this embodiment.
  • FIG. 16A, 16B and 16C (these may be collectively referred to as FIG. 16), FIG. 17A and FIG. 17B (these may be collectively referred to as FIG. 17), and FIGS. 18A and 18B.
  • FIG. 18C (which may be collectively referred to as FIG. 18) illustrates a diagram for explaining a process of manufacturing a semiconductor package using a plurality of semiconductor chips CP.
  • the present embodiment includes a step of forming a rewiring layer on the support and electrically connecting the rewiring layer and the semiconductor chip sealed inside the sealing body.
  • the semiconductor package manufacturing process described in this embodiment may be referred to as RDL-First.
  • RDL is an abbreviation for Redistribution Layer.
  • FIG. 16A shows a support 80 having a support substrate 81 and a release layer 82 formed on the surface of the support substrate 81.
  • the material of the support substrate 81 include glass and a silicon wafer.
  • the surface of the support substrate 81 is preferably smooth.
  • the release layer 82 is formed of a material having peelability.
  • the release layer 82 can be formed by laminating a release tape on the support substrate 81.
  • the release tape preferably has a release substrate and a release agent layer. When the release tape having such a configuration is used, the release tape is laminated on the surface of the support substrate 81 so that the release agent layer is exposed on the surface.
  • the method for adhering the release substrate and the support substrate 81 is not particularly limited.
  • the release tape and the support substrate 81 can be attached by interposing an adhesive layer between the release substrate and the support substrate 81.
  • a metal film may be formed on the release layer 82 as necessary.
  • the metal film can be formed by, for example, a sputtering method.
  • a metal which comprises a metal film the metal selected from the group which consists of titanium and aluminum is mentioned, for example.
  • a rewiring layer to be described later is formed on the metal film.
  • FIG. 16B shows a diagram for explaining a process of forming the rewiring layer RDL on the peeling layer 82 of the support 80.
  • the rewiring layer RDL includes an insulating resin layer 83 and a rewiring 84 covered with the insulating resin layer 83.
  • a rewiring 84 and an insulating resin layer 83 covering the rewiring 84 are formed.
  • the rewiring layer RDL can also be formed by adopting a known rewiring layer forming method.
  • the rewiring layer RDL can also be formed by adopting a method of forming a rewiring layer in the RDL-First manufacturing process.
  • the rewiring layer RDL can also be formed by adopting the same method as the rewiring layer forming method described in the first embodiment.
  • the rewiring 84 includes an internal electrode pad 84A that is electrically connected to the internal terminal electrode W4 of the semiconductor chip CP, and an external electrode pad 84B that is electrically connected to the external terminal electrode.
  • the internal electrode pad 84A is located on the surface side of the first stacked body 80A in the first stacked body 80A in which the rewiring layer RDL is formed on the support body 80. In the first stacked body 80A, the internal electrode pad 84A is exposed.
  • the external electrode pad 84B is located inside the first stacked body 80A in the first stacked body 80A.
  • the external electrode pad 84B faces the release layer 82 inside the first stacked body 80A. In the first stacked body 80A, the external electrode pad 84B is not exposed.
  • FIG. 16C is a diagram illustrating a process of forming the bump 85 on the internal electrode pad 84A of the first stacked body 80A.
  • a solder ball or the like is placed on the internal electrode pad 84A, and the bump 85 and the internal electrode pad 84A are electrically connected by solder bonding or the like.
  • the material of the solder ball is not particularly limited, and examples thereof include lead-containing solder and lead-free solder.
  • the sealing resin film 86 is attached to the surface of the first stacked body 80A so as to cover the plurality of bumps 85. Examples of the sealing resin film 86 include NCF (Non Conductivity Film).
  • FIG. 17A shows a sealing body 3A in which a plurality of semiconductor chips CP aligned by the semiconductor chip alignment method according to the first embodiment are sealed.
  • 3A of sealing bodies can be formed similarly to 1st Embodiment.
  • the number of sealed semiconductor chips CP is different for convenience of explanation.
  • the sealing body 3A can also be formed in the same manner as the sealing body 3 by performing the sealing process after performing the semiconductor chip alignment process. After sealing the semiconductor chip CP, the surface protection sheet 40 is peeled off to obtain a sealing body 3A in which the circuit surface W1 and the internal terminal electrodes W4 of the semiconductor chip CP are exposed.
  • the sealing body in the present embodiment may be a sealing body in which not only the semiconductor chip CP but also the frame member 400 is sealed as in the sealing body 3D of the third embodiment. Further, the sealing body in the present embodiment may be a sealing body in which not only the semiconductor chip CP but also the alignment jig 100 is sealed as in the sealing body 3E of the fifth embodiment.
  • FIG. 17B is a diagram illustrating a process of electrically connecting the semiconductor chip CP of the sealing body 3A and the internal electrode pad 84A of the first stacked body 80A.
  • This connection step can be performed by a flip-chip connection method.
  • position control is performed so that the positions of the plurality of internal terminal electrodes W4 of the sealing body 3A and the positions of the plurality of bumps 85 of the first stacked body 80A are matched.
  • the sealing body 3A is pressed against the first stacked body 80A so that the internal terminal electrode W4 of the semiconductor chip CP enters the sealing resin film 86, and the internal terminal electrode W4 and the bump 85 are brought into contact with each other.
  • a second stacked body 80B in which the sealing body 3A and the first stacked body 80A are bonded is formed.
  • the second laminated body 80B is sandwiched between the sealing body 3A side and the first laminated body 80A side by using a crimping member, and the second laminated body 80B is heated and crimped for a predetermined time.
  • An example of the crimping member is a crimping plate.
  • Examples of the material for the pressure plate include metals and resins.
  • the internal terminal electrodes W4 and the internal electrode pads 84A are electrically connected via the bumps 85, and the sealing resin film 86 is cured.
  • the sealing resin film 86 is filled between the sealing body 3A and the first stacked body 80A, so that the electrical connection between the internal terminal electrode W4 and the bump 85 is reinforced.
  • FIG. 18A shows a diagram illustrating a process of peeling the support body 80 from the second stacked body 80B.
  • the support body 80 is peeled from the second stacked body 80B, the external electrode pads 84B of the rewiring 84 are exposed.
  • a third stacked body 80C in which the rewiring layer RDL and the sealing body 3A are stacked is obtained.
  • FIG. 18B is a diagram illustrating a process of connecting the external terminal electrode to the third stacked body 80C.
  • An external terminal electrode 87 such as a solder ball is placed on the external electrode pad 84B of the third stacked body 80C, and the external terminal electrode 87 and the external electrode pad 84B are electrically connected by solder bonding or the like.
  • the material of the solder ball is not particularly limited, and examples thereof include lead-containing solder and lead-free solder.
  • FIG. 18C shows a diagram illustrating a process of separating the third stacked body 80C to which the external terminal electrode 87 is connected.
  • the third stacked body 80C is separated into individual semiconductor chips CP.
  • the method for dividing the third stacked body 80C into individual pieces is not particularly limited.
  • the third stacked body 80 ⁇ / b> C can be separated into pieces by adopting a method similar to the method of dicing the semiconductor wafer W described above.
  • the step of dividing the third laminated body 80C into pieces may be performed by sticking the third laminated body 80C to an adhesive sheet such as a dicing sheet.
  • the semiconductor chip alignment process is performed as in the first embodiment, and the alignment method using the alignment jig 100 is performed. Therefore, after aligning the plurality of semiconductor chips CP at equal intervals, A sealing process and a semiconductor packaging process can be implemented. Therefore, in the sealing body 3A, the plurality of semiconductor chips CP are sealed at a more even interval. Further, since the plurality of semiconductor chips CP are sealed at equal intervals, the positions of the plurality of internal terminal electrodes W4 of the sealing body 3A and the positions of the plurality of bumps 85 of the first stacked body 80A are matched. In addition, the displacement of the connection position can be suppressed.
  • the present embodiment relates to a method of transferring a plurality of strips aligned by the alignment method according to the embodiment to a support.
  • a mode in which semiconductor chips are aligned as a piece and then transferred to a support will be described as an example.
  • the flakes that can be transferred by the transfer method of the present invention are not limited to semiconductor chips.
  • the step of transferring the semiconductor chip CP aligned after the semiconductor chip alignment step to the surface protection sheet 40 (third transfer step) is performed, whereas the transfer method according to this embodiment is The first embodiment is mainly different from the present embodiment in that the aligned semiconductor chips CP are transferred to a hard support having an adhesive surface instead of the surface protective sheet 40.
  • FIG. 19A and 19B are diagrams illustrating a method for transferring the semiconductor chip CP onto a hard support having an adhesive surface.
  • FIG. 19A shows a hard support 500 ⁇ / b> A having a hard base 500 and an adhesive layer 501 formed on the surface of the hard base 500.
  • the outer surface of the adhesive layer 501 corresponds to the adhesive surface 502.
  • the hard base material 500 for example, a base material formed of glass or the like can be used.
  • the hard substrate 500 preferably has heat resistance.
  • the temperature at which the hard base material 500 is deformed by heating is preferably higher than the temperature at which the adhesive sheet is deformed by heating.
  • the adhesive layer 501 contains an adhesive.
  • the pressure-sensitive adhesive contained in the pressure-sensitive adhesive layer 501 is not particularly limited, and various types of pressure-sensitive adhesives can be applied to the pressure-sensitive adhesive layer 501.
  • Examples of the adhesive contained in the adhesive layer 501 include rubber, acrylic, silicone, polyester, and urethane.
  • the kind of adhesive is selected in consideration of the use and the kind of adherend to be attached.
  • UV ultraviolet rays
  • EB electron beams
  • ultraviolet rays are preferable.
  • a method by energy beam irradiation a method by heating, a method by heating and energy beam irradiation As well as any of the methods by cooling.
  • FIG. 19B shows a hard support 500 ⁇ / b> B having a hard base 500 and a surface protective sheet 40 adhered to the surface of the hard base 500.
  • the surface protection sheet 40 includes a fourth base film 41 and a fourth pressure-sensitive adhesive layer 42.
  • the fourth pressure-sensitive adhesive layer 42 is exposed on the surface, and the outer surface of the fourth pressure-sensitive adhesive layer 42 corresponds to the pressure-sensitive adhesive surface 43.
  • the semiconductor chips CP aligned in the semiconductor chip alignment step are transferred to the adhesive surface 502 of the hard support 500A or the adhesive surface 43 of the hard support 500B.
  • 19A and 19B illustrate a mode in which the alignment jig 100 is not attached, but the alignment jig 100 may be transferred to a hard support together with the aligned semiconductor chips CP.
  • the semiconductor device manufacturing method can be performed in the same manner as in the above-described embodiment.
  • the transfer step of this embodiment is performed, and the other steps can be performed in the same manner as in the first embodiment.
  • the hard support to which the semiconductor chip CP is transferred is a process that requires high-temperature heating. Can be used.
  • the hard base material 500 is formed of a harder material than the surface protection sheet or the like, according to the present embodiment, the semiconductor chip CP is more stably supported and transported in the manufacturing process of the semiconductor package or the like. can do.
  • the present invention is not limited to the above-described embodiment.
  • the present invention includes a modification of the above-described embodiment as long as the object of the present invention can be achieved.
  • the circuits and the like in the semiconductor wafer and the semiconductor chip are not limited to the illustrated arrangement and shape.
  • the connection structure with the external terminal electrode in the semiconductor package is not limited to the mode described in the above embodiment.
  • the aspect of manufacturing the FO-WLP type semiconductor package has been described as an example.
  • the present invention can also be applied to an aspect of manufacturing other semiconductor packages such as a fan-in type WLP.
  • the number of accommodating portions included in the alignment jig is not limited to the example of the alignment jig described in the first embodiment.
  • An alignment jig having an accommodation portion corresponding to the number of pieces such as semiconductor chips can be used.
  • the outer shape of the main body portion of the alignment jig is not limited to the circular shape as described in the first embodiment, and examples of the shape other than the circular shape include a rectangle, a square, and an ellipse. .
  • the method of aligning semiconductor chips by moving the alignment jig in two steps in the 2B direction and 2C direction in the drawing has been described as an example. It is not limited to such an aspect.
  • the alignment jig or moving the holding surface of the holding member in a direction for example, an oblique direction
  • Semiconductor chips can be aligned.
  • the direction in which the holding surface is moved is not limited to the horizontal direction.
  • the semiconductor chip CP may be moved and brought into contact with the wall portion of the alignment jig by inclining the holding surface.
  • the embodiment in which the expanding step is performed twice has been described as an example, but the present invention is not limited to such an embodiment.
  • the expanding process may be performed once.
  • a mode in which the protective sheet 30 is attached to the circuit surface W1 of the semiconductor wafer W and the groove forming step is performed is illustrated, but the present invention is not limited to such a mode.
  • the groove forming step is performed with the circuit surface W1 exposed, and the first adhesive sheet 10 is applied to the circuit surface W1 after the groove is formed.
  • a passivation film that covers the circuit surface W1 may be formed before the groove forming step.
  • the passivation film preferably has a shape that exposes the internal terminal electrode W4 of the circuit W2.
  • the passivation film is preferably formed using, for example, silicon nitride, silicon oxide, polyimide, or the like.
  • the second adhesive sheet 20 is extended to widen the intervals between the plurality of semiconductor chips CP
  • an expansion process may be additionally performed.
  • the plurality of semiconductor chips CP held by the second adhesive sheet 20 are transferred to another expanding sheet while maintaining the expanded space, and the expanding sheet is stretched.
  • the interval between the plurality of semiconductor chips CP can be increased.
  • the surface protection sheet 40 may be extended to further increase the interval between the plurality of semiconductor chips CP.
  • the semiconductor device manufacturing method including the step of forming a groove having a depth of cut smaller than the thickness of the semiconductor wafer has been described as an example.
  • the semiconductor wafer in which the groove is formed in advance is described. May be used.
  • the groove W5 was formed in the semiconductor wafer W and it demonstrated and demonstrated as an example the aspect which affixes the protective sheet 30 as a 3rd adhesive sheet on the circuit surface W1
  • This invention is such an aspect. It is not limited to.
  • the groove W5 is formed in a state where the circuit surface W1 is protected by the circuit surface protection sheet, the circuit surface W1 and the circuit W2 can be prevented from being contaminated or damaged by cutting waste.
  • an incision is made from the circuit surface protection sheet side, the circuit surface protection sheet is completely cut, an incision having a depth shallower than the thickness of the semiconductor wafer W is made from the circuit surface W1 of the semiconductor wafer W, and the groove W5 Form.
  • the first pressure-sensitive adhesive sheet 10 may be attached to the protective sheet 30 side before grinding. After adhering the first adhesive sheet 10, the semiconductor wafer W is ground from the back surface W 6 side using the grinder 50.
  • the first pressure-sensitive adhesive sheet 10 has a first base film 11 and a first pressure-sensitive adhesive layer 12.
  • the first pressure-sensitive adhesive layer 12 is laminated on the first base film 11.
  • the first pressure-sensitive adhesive sheet 10 may be cut in advance so as to have substantially the same shape as the semiconductor wafer W, or a first pressure-sensitive adhesive sheet 10 larger than the semiconductor wafer W is prepared, and the semiconductor wafer W is prepared. You may cut to the same shape as the semiconductor wafer W after sticking.
  • the first pressure-sensitive adhesive layer 12 contains a relatively strong pressure-sensitive adhesive so that the cut protective sheet 30 can be peeled together in a later step. Is preferred. It is preferable that the first base film 11 has relatively high rigidity like polyethylene terephthalate so that it does not stretch when it is peeled off.
  • An alignment method for aligning a plurality of pieces using an alignment jig The piece has a first side, a second side adjacent to the first side, and an end of the first side and a corner of the piece located at the end of the second side.
  • the alignment jig includes a plurality of accommodating portions capable of accommodating a piece-like body, and the accommodating portion includes a wall portion and an accommodating corner portion,
  • the wall portion includes a first side wall and a second side wall adjacent to the first side wall,
  • the accommodation corner is located at an end of the first side wall and an end of the second side wall,
  • the accommodation corner has a recessed portion that is recessed deeper than the surface of the first side wall and the surface of the second side wall, Contacting the first side surface of the piece and the first side wall of the housing; Contacting the second side surface of the piece and the second side wall of the housing; Accommodating the piece-like body corner portion of the piece-like body in the hollow portion of the containing corner portion.
  • this alignment method it is possible to align a plurality of pieces at a more even interval simply and quickly.
  • the plurality of accommodating portions are preferably arranged in a lattice shape, and more preferably in a square lattice shape.
  • Example 1 the alignment method using the alignment jig according to the first embodiment was performed. That is, in the first embodiment, a copper alignment jig having a plurality of accommodating portions having the shape shown in FIG. 2A was used. A copper plate having a thickness of 3 mm is attached to one side of the aligning jig to close one opening, and after placing the semiconductor chip on the copper plate from the other opening side, the semiconductor chip is applied to the wall of the housing portion. (See FIG. 2C).
  • Reference Example 1 an alignment method using the alignment jig according to the reference example described in FIG. In Reference Example 1, the same operation as in Example 1 was performed except that the alignment jig was changed.
  • the inner dimension (distance between opposing side walls) of the alignment jig housing portion used in this example (Example 1 and Reference Example 1), the lattice frame width of the alignment jig, and the semiconductor chip used in this example The dimensions are as follows.
  • the shape of the hollow part of the alignment jig used in Example 1 was a semicircle having a diameter of about 0.4 mm.
  • the degree to which the semiconductor chips are aligned at equal intervals was compared.
  • Dimensions of semiconductor chip 3 mm ⁇ 3 mm, thickness 350 ⁇ m
  • the shape of the accommodating portion has the same shape as the accommodating portion described in the first embodiment and the reference example, but more accommodating portions than those illustrated in the embodiment and the reference example.
  • tool which has was used.
  • three storage areas having a total of 16 storage portions of 4 vertical lengths ⁇ 4 horizontal locations are defined, and the semiconductor chip is stored in the storage portions (total 48 locations) of the 3 storage areas for alignment. The method was carried out.
  • the central coordinates of each semiconductor chip were digitized in a common coordinate system using a measuring instrument having an XY stage.
  • the measuring instrument used was a CNC image measuring instrument (product name: QV ACCEL HYBRID TYPE1) manufactured by Mitutoyo Corporation.
  • the three accommodation areas one accommodation area (first area) was selected, the first area was used as a reference, and the other two areas were designated as the second area and the third area.
  • the angle (tilt) of the storage area so that the amount of deviation between the X-axis direction and Y-axis direction of the first area as a reference and the X-axis direction and Y-axis direction of the second area is minimized.
  • the first area and the third area were also superimposed on the data as described above. After the overlapping, the coordinates of the semiconductor chips accommodated in the corresponding accommodating portions in each area were compared between the 16 accommodating portions in the first area and the 16 accommodating portions in the second area or the third area. .
  • the degree of deviation of the coordinates of the semiconductor chip in the second area from the reference coordinates was calculated.
  • how much the coordinates of the semiconductor chip in the third area are shifted with respect to the first area was calculated.
  • Table 1 shows the calculation results of the amount of variation in the X-axis direction, the Y-axis direction, and the tilt calculated after the alignment method of Example 1 and Reference Example 1 was performed. Note that the inclination indicates the degree of inclination by comparing the line connecting the diagonal lines of the semiconductor chips in the second area or the third area with reference to the line connecting the diagonal lines of the semiconductor chips in the first area.
  • the alignment method using the alignment jig according to the first embodiment As shown in Table 1, according to the alignment method using the alignment jig according to the first embodiment, as compared with the first reference example, the amount of positional deviation between the semiconductor chips in the X-axis direction, the Y-axis direction, and the tilt. It turns out that there are few. That is, according to the alignment method using the alignment jig according to Example 1, it was possible to align a plurality of semiconductor chips at more uniform intervals. Similar to the first embodiment, the alignment jig and the alignment method described in the embodiments other than the first embodiment and the modifications of the embodiment also provide a more uniform spacing between the plurality of semiconductor chips as compared to the reference example 1. Can be aligned with.
  • DESCRIPTION OF SYMBOLS 100 Alignment jig
  • tool 101 ... Accommodating part, 102 ... Wall part, 102a ... First side wall, 102b ... Second side wall, 103 ... Accommodating corner part, 103a ... First accommodating corner part, 104 ... Depression part, CP ... Semiconductor Chip (piece-shaped body), cp1... First side surface, cp2... Second side surface, cp3.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

Un gabarit d'alignement (100) pourvu d'une pluralité de portions de contenant (101) dans lesquelles des éléments de puce (CP) peuvent être contenus est caractérisé en ce que les portions de contenant (101) ont une partie de coin de contenant (103) qui est formée de telle sorte que, lorsque les éléments de puce (CP) sont respectivement contenues dans la pluralité de portions de contenant (101) et les éléments de puce (CP) sont en butée contre une portion de paroi (102) des portions de contenant (101), une partie de coin d'élément de puce de l'élément de puce (CP) n'entre pas en contact avec la partie de coin de récipient (103).
PCT/JP2017/022686 2016-06-28 2017-06-20 Gabarit d'alignement, procédé d'alignement et procédé de transfert WO2018003602A1 (fr)

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CN109417045B (zh) 2023-06-23
KR20190021223A (ko) 2019-03-05
CN109417045A (zh) 2019-03-01
TW201810507A (zh) 2018-03-16
KR102413733B1 (ko) 2022-06-27
JPWO2018003602A1 (ja) 2019-04-11
JP6983775B2 (ja) 2021-12-17

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