WO2010058646A1 - Boîtier de semi-conducteur et son procédé de fabrication - Google Patents

Boîtier de semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2010058646A1
WO2010058646A1 PCT/JP2009/065316 JP2009065316W WO2010058646A1 WO 2010058646 A1 WO2010058646 A1 WO 2010058646A1 JP 2009065316 W JP2009065316 W JP 2009065316W WO 2010058646 A1 WO2010058646 A1 WO 2010058646A1
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Prior art keywords
wafer
semiconductor
back surface
chip
forming
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PCT/JP2009/065316
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English (en)
Japanese (ja)
Inventor
隆史 久田
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インターナショナル・ビジネス・マシーンズ・コーポレーション
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Publication of WO2010058646A1 publication Critical patent/WO2010058646A1/fr

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Definitions

  • the present invention relates to a wafer level package technology, and more particularly to a wafer level semiconductor package that realizes a wide mounting area of peripheral connection terminals and a method for manufacturing the same.
  • the wafer level package (WLP) technology assembles the wafer as it is, and divides the wafer into individual pieces by dicing in the final process.
  • This is a technology for realizing a surface mountable chip scale package (CSP) that can be miniaturized to the same scale (Non-patent Document 1).
  • CSP surface mountable chip scale package
  • multi-chip package technology has been developed in which multiple chips are stacked and systematized (special Japanese Laid-Open Patent Publication No. 2008-166752: Patent Document 1).
  • a rewiring layer including polyimide and copper wiring is formed on a passivation insulating film on a circuit surface of a semiconductor chip, and metal posts, solder balls, solder ball pads, etc. are mounted on the rewiring layer,
  • An array of connection terminal bumps is formed in a form such as a grid array (BGA).
  • FIG. 11 is a cross-sectional view schematically showing a conventional wafer level semiconductor package.
  • a rewiring layer 510 is formed so as to be connected to a contact pad 506 for external connection exposed from a passivation film 504 on a silicon chip (die) 502.
  • a solder resist 512 is applied thereon, and solder balls 513 are disposed on the terminal pads (lands).
  • a layer such as a flexible layer 508 may be provided to alleviate the problem of reliability due to a mismatch in thermal expansion coefficient with a printed wiring board (PCB) on which the semiconductor package 500 is mounted.
  • PCB printed wiring board
  • the conventional WLP is often used in a memory having a small number of input / output pins (for example, less than 100 pins), but a memory, a logic IC, an ASIC (specific application integrated circuit), a processor that requires a large number of input / output pins. It has not yet spread. Further expansion of the application range of WLP is desired.
  • Patent Document 1 an individual semiconductor chip obtained by dicing a silicon wafer is obtained by using a pick-and-place system for the purpose of increasing the package size in order to improve the heat dissipation performance of the package.
  • a technique is disclosed in which a molding material is formed on a panel so as to be disposed on the panel so as to surround the chip, and a pad of a semiconductor chip is connected to a redistribution metal by a buildup layer process.
  • Patent Document 1 it is necessary to place the separated chips once at the desired positions on the panel.
  • the operation of placing individual chips on the panel one by one using a pick-and-place system or the like is based on the premise that the chip is flip-chip mounted on a substrate, a normal flip chip package
  • a burden is generated in terms of time, cost, and yield of a bumping process, a flip chip bonding process, and a substrate process of a fine design rule formed on a chip.
  • the multi-chip package of Patent Document 1 is insufficient in that the thickness of the package is increased because the panel (substrate) is provided on the back surface of the chip.
  • the technology disclosed in the above-mentioned patent document aims to systematize a stacked structure of a plurality of chips.
  • the restriction on the number of connection terminals due to the chip size is relaxed, and connection terminals are mounted. It is not intended to expand the possible area.
  • the present invention has been made in view of the above-described problems, and relaxes restrictions on the number of connection terminals such as solder balls due to the chip size at the wafer level, and thus has a high number of input / output pins and is connected.
  • An object of the present invention is to provide a semiconductor package with high reliability and good yield, and a method for manufacturing the same.
  • the present invention first encloses a plurality of semiconductor chips separated from a semiconductor wafer with a mold member by enlarging the distance between the semiconductor chips and leaving a circuit formation surface. Thus, an extended wafer is formed. Then, a rewiring layer having a rewiring pattern is formed on the extended wafer.
  • the rewiring pattern has a terminal pad for mounting a connection terminal bump, and extends from the electrode pad on the circuit formation surface of the semiconductor chip to a region outside the semiconductor chip. Then, the extended wafer on which the rewiring layer is formed is divided into individual pieces to form a plurality of semiconductor packages.
  • the limitation due to the size of the semiconductor chip with respect to the range in which rewiring can be routed that is, the range in which the connection terminal bump can be mounted is removed, and the pitch interval of the connection terminal bump is maintained It is possible to increase the number of terminals while maintaining. Therefore, it is possible to suitably prevent a decrease in yield and connection reliability due to an increase in the number of terminals, and thus a semiconductor package having a high number of input / output pins, a high connection reliability, and a high yield. It becomes possible to provide.
  • the extended wafer can be handled as a wafer used in an existing wafer processing process, a production line is constructed as a normal wafer process by changing the process for forming the extended wafer. be able to. Furthermore, the rewiring pattern can be applied with a wafer level design ground rule, and is excellent in high density wiring design.
  • the distance between the semiconductor chips can be increased by spreading the support tape in which the plurality of semiconductor chips are arranged in contact with the circuit forming surfaces.
  • the distance between the separated semiconductor chips can be expanded at once. This realizes wafer level packaging of semiconductor chips, which is advantageous in terms of time, cost, and yield.
  • a plurality of semiconductor chips on the extended support tape are arranged in a mold having a wafer shape, and the molding material is injected into the mold to be molded, thereby An extended wafer can be formed.
  • a via hole is formed in the mold member at the periphery of the semiconductor chip, filled with a conductive material, and extends from the surface of the expansion wafer to the back surface of the expansion wafer through the mold member.
  • the surface of the expansion wafer is a surface including the circuit formation surface of the semiconductor chip.
  • the via hole can be formed by forming a pin as a part of a mold, or by penetrating a mold member with a mechanical drill or a laser drill.
  • a back surface terminal pad for providing an external connection can be formed on the back surface of the expansion wafer.
  • a protective layer can be formed on the back surface of the expansion wafer so as to expose the back surface terminal pads.
  • the rewiring pattern of the rewiring layer can be connected to the through via on the surface of the expansion wafer.
  • the back surface terminal pad can be a pad array extending from a region immediately below the semiconductor chip on the back surface of the expansion wafer to a region outside the semiconductor chip.
  • the external connection terminals can be disposed over the back surface of the semiconductor package in addition to the surface area on the semiconductor chip and the mold member. Therefore, by maintaining the total number of terminals and relaxing the pitch between the connection terminal bumps, it is possible to realize higher connection reliability and yield.
  • the obtained extended wafer can be polished on the back surface to expose the back surface of the semiconductor chip surrounded by the mold member.
  • the semiconductor package is thinned.
  • high heat dissipation can be obtained by arranging a heat sink or the like in contact with the semiconductor chip.
  • the rewiring layer is formed on the first dielectric layer having a first dielectric layer having an opening for connecting the rewiring pattern to the electrode pad, A second dielectric layer covering the rewiring pattern and opening to expose the terminal pad.
  • 1 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention.
  • 1 is a plan view of a semiconductor package according to a first embodiment of the present invention.
  • the figure (1/2) which shows the manufacturing method of the semiconductor package by the 1st Embodiment of this invention with the cross-sectional structure in each process.
  • the figure (2/2) which shows the manufacturing method of the semiconductor package by the 1st Embodiment of this invention with the cross-sectional structure in each process.
  • the figure (1/2) which shows the manufacturing method of the semiconductor package by the 2nd Embodiment of this invention with the cross-sectional structure in each process.
  • the figure (2/2) which shows the manufacturing method of the semiconductor package by the 2nd Embodiment of this invention with the cross-sectional structure in each process.
  • Sectional drawing of the semiconductor package by the 3rd and 4th embodiment of this invention Sectional drawing which shows the outline of the conventional semiconductor package of a wafer level.
  • a semiconductor package having a wafer level BGA (Ball Grid Array) structure in which solder balls are arranged in an array on a rewiring layer on a silicon chip will be described as an example.
  • FIG. 1 shows a cross-sectional view of a semiconductor package according to a first embodiment of the present invention.
  • a semiconductor package 100 shown in FIG. 1 includes a silicon chip 102 in which a plurality of electrode pads 106 are provided on a circuit formation surface.
  • the silicon chip 102 is diced through a dicing process after the wafer processing process.
  • the wafer processing process is usually a base process for fabricating elements on a silicon wafer, an element interconnection, an upper process for creating a wiring structure for power supply and grounding, formation of electrode pads 106 for external connection, described later.
  • Including a passivation step for forming the passivation film 104 is usually a base process for fabricating elements on a silicon wafer, an element interconnection, an upper process for creating a wiring structure for power supply and grounding, formation of electrode pads 106 for external connection, described later.
  • the circuit forming surface of the silicon chip 102 is coated with a passivation film 104 that mechanically, electrically and chemically protects the circuit pattern from the external environment.
  • the electrode pad 106 is exposed from the passivation film 104.
  • the electrode pad 106 is not particularly limited, but is provided at the outer edge or the center of the circuit formation surface of the silicon chip 102.
  • the material of the passivation film 104 is not particularly limited.
  • photosensitive or non-photosensitive polyimide, PSG (Phospho-Silicate-Glass), silicon nitride film (Si 3 N 4 ), silicon oxide film, A silicon oxynitride film, a combination of these, or the like can be used.
  • the material of the electrode pad 106 is not particularly limited, and for example, a conductive material including a metal such as aluminum or copper and an alloy such as an aluminum alloy can be used. Although not shown, the electrode pad 106 can appropriately include a seed layer in order to obtain good adhesion with a rewiring pattern to be described later.
  • the semiconductor package 100 further includes a mold member 108 surrounding the silicon chip 102 except for the circuit forming surface side.
  • a member such as a redistribution layer can be disposed only in a region on a silicon chip.
  • the mold member 108 does not limit the region where the member such as the rewiring layer can be disposed within the region on the silicon chip 102, but on the mold member 108. Extend across the area.
  • the silicon chip 102 and the mold member 108 constitute a chip 110 (hereinafter referred to as an expansion chip) having an outer size larger than that of the silicon chip 102.
  • the expansion chip 110 the surface on the circuit forming surface side of the silicon chip 102 is referred to as a front surface, and the opposite surface is referred to as a back surface.
  • the mold member 108 is not particularly limited, but can be formed using an epoxy resin molding material containing a filler such as spherical fused silica.
  • the mold member 108 is formed by, for example, transfer molding in which a molding material plasticized in a heating chamber is pressed into a heated mold, or the supplied molding material is molded into a mold. It can be formed by compression molding or the like in which a mold is clamped and pressure is applied.
  • the semiconductor package 100 is manufactured by molding the silicon chip 102 and forming it into a wafer shape having a diameter larger than that of the original silicon wafer. For this reason, from the viewpoint of the manufacturing process, it is preferable to use a molding material having a small molding shrinkage ratio, low elasticity, low stress, and low warpage.
  • the material of the mold member 108 it is preferable to use a biphenyl epoxy resin or a polyfunctional epoxy resin having a glass transition temperature (Tg) in the range of 100 ° C. to 250 ° C.
  • Tg glass transition temperature
  • the material of the mold member 108 is adjusted so that the difference from the thermal expansion coefficient of the silicon chip 102 (for example, silicon is about 3 ppm / K) is small so as not to warp during molding or reflow. It is preferable.
  • the mold member 108 may be formed of super engineering plastic with improved heat resistance, ceramics such as alumina, or the like. In the following description, a case where a resin molding material is used as the material of the mold member 108 and transfer molding is performed will be described as an example.
  • the semiconductor package 100 further includes a re-distribution layer (RDL) 116 formed on the silicon chip 102 and the mold member 108.
  • the rewiring layer 116 includes a first dielectric layer 112b formed on the mold member 108 and the passivation film 104, a rewiring pattern 114 formed on the dielectric layer 112b, and a rewiring pattern. 114 and a second dielectric layer 112a formed on the substrate.
  • the first dielectric layer 112 b has an opening at a position corresponding to the electrode pad 106 and exposes the electrode pad 106.
  • the rewiring pattern 114 is connected to the electrode pad 106 and extends from the electrode pad 106 on the circuit formation surface of the silicon chip 102 to a region outside the silicon chip 102.
  • the rewiring pattern 114 includes pads (hereinafter referred to as external terminal pads) 107a and 107b for mounting solder balls arranged in an array.
  • the second dielectric layer 112a is opened to expose the external terminal pads 107a and 107b.
  • the material of the dielectric layers 112a and 112b is not particularly limited, and an insulating resin material containing polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or the like can be used.
  • the dielectric layers 112a and 112b can be formed, for example, by applying the insulating resin material and patterning using an appropriate mask.
  • the material of the rewiring pattern 114 is not particularly limited, and a conductive material including a metal such as copper, nickel, palladium, silver, or an alloy material thereof can be used.
  • the rewiring pattern 114 can be formed as a single layer or a plurality of layers by a sputtering method, an electrolytic plating method, an electroless plating method, or the like.
  • a UBM (Under Bump Metallurgy) or BLM (Ball limiting Metallurgy) layer (hereinafter referred to as a BLM layer) having solder wettability can be appropriately formed. .
  • the semiconductor package 100 further includes a solder ball 118 disposed on the external terminal pad 107 of the rewiring layer 116.
  • the solder balls 118 are not particularly limited, but can be soldered by placing the solder balls 118 directly on the external terminal pads 107 by a ball mounting method and performing reflow.
  • the solder balls 118 can also be formed by vapor deposition, plating, or solder paste printing.
  • the material of the solder ball 118 is not particularly limited, but at least selected from the group consisting of lead-containing solder made of a Pb—Sn alloy, or Ag, Cu, Zn, Bi and Sb containing Sn as a main component. Lead-free solder made of a tin alloy having one element can be used.
  • the solder ball 118 includes 118 b disposed in a region on the mold member 108 in addition to 118 a disposed in a region on the normal silicon chip 102.
  • the rewiring pattern 114 provides an electrical connection from the electrode pad 106 on the silicon chip 102 to the solder ball 118.
  • FIG. 2 is a plan view of the semiconductor package 100 according to the first embodiment of the present invention.
  • FIG. 2 shows a chip region 130 b on the silicon chip 102 and a mold region 130 a expanded by the mold member 108.
  • solder balls 118 are arranged in an array over the mold region 130a and the chip region 130b.
  • the solder balls 118 are connected to the electrode pads 106 disposed on the outer edge of the circuit formation surface of the silicon chip 102 via the rewiring pattern 114, respectively. 1 corresponds to a cross-sectional view taken along the cutting line A in FIG.
  • the solder balls 118 can be arranged over an expanded range outside the chip region 130b. For this reason, it can be said that the restriction due to the chip size with respect to the number of input / output pins is relaxed.
  • the number of input / output pins can be increased while maintaining the pitch interval, it is possible to suitably prevent a decrease in yield and connection reliability due to an increase in the number of input / output pins.
  • a semiconductor package having a high number of input / output pins, high connection reliability, and high yield can be provided.
  • the back surface of the semiconductor package 100 is released from a substrate such as a PCB, the entire package is thinned.
  • FIGS. 3A to 3E and FIGS. 4A to 4E are views showing a method of manufacturing the semiconductor package 100 according to the first embodiment of the present invention, along with cross-sectional structures in the respective steps.
  • the silicon wafer 20 is mounted on the ring frame 10 via the wafer mount tape 11 for back surface polishing.
  • the silicon wafer 20 has been subjected to a wafer processing process including a base process, an upper process, an electrode pad formation, a passivation process, and the like.
  • the silicon wafer 20 is mounted such that the circuit forming surface of the silicon wafer 20 is in contact with the wafer mount tape 11.
  • FIG. 3B subsequently, the silicon wafer 20 is subjected to a back surface polishing process to be thinned.
  • the back surface polishing wafer mount tape 11 protects the surface of the silicon wafer 20 and prevents contamination due to intrusion of grinding water or grinding waste during back surface polishing.
  • the silicon wafer 20 is aligned, and is attached to the wafer mounting tape 13 for dicing, and is subjected to a dicing process.
  • the individual silicon chips 22 are obtained in a state of being bonded onto the wafer mount tape 13.
  • FIG. 5A shows an aspect of the silicon wafer 20 after the dicing process. As shown in FIG. 5A, the silicon wafer 20 is diced along the cutting lines 20a and 20b to obtain a plurality of individual silicon chips 22. Note that the back surface polishing wafer mount tape 11 is peeled off at an appropriate timing.
  • the dicing method is not particularly limited, and can be performed using a blade dicing method in which a wafer is directly cut out or a stealth dicing method in which a wafer is cut out by laser processing and chips are separated by tape expansion.
  • the wafer is then attached to an expanding wafer mount tape (support tape) 15 in order to uniformly increase the chip interval.
  • a tape expanding process is performed.
  • the silicon chips 22 with the gaps widened are obtained in a state where they are stuck on the wafer mount tape 15.
  • a margin having a predetermined substantially uniform width is formed between the silicon chips 22.
  • the tape expanding step is not particularly limited, but can be performed by a method of extending the wafer mount tape 15 by pressing a ring or a circular expander against the wafer mount tape 15.
  • any method that can spread the wafer mount tape 15 radially in the wafer surface direction and can enlarge the chip interval on the wafer mount tape 15 substantially uniformly can be adopted.
  • a molding process is subsequently performed.
  • the wafer-shaped dies 32 and 34 are prepared in contact with the wafer mount tape 15 so that the silicon chip 22 with the chip interval widened enters inside thereof.
  • the mold 32 is provided with a gate 32a for injecting a resin molding material.
  • a resin molding material is injected into the molds 32 and 34 through the gate 32a while maintaining the chip interval on the wafer mount tape 15 by transfer molding, and the silicon chip 22 except for the surface in contact with the tape 15 is formed. Molded.
  • a plurality of gates can be provided in consideration of the fluidity and filling properties of the molded resin material.
  • the molds 32 and 34 are appropriately provided with one or a plurality of air vents for venting the air in the mold.
  • the air vent is not particularly limited.
  • the air vent is provided at the end portion of the mold 32 in contact with the wafer mount tape 15.
  • the extended wafer 26 has a configuration in which a plurality of individual silicon chips 22 are surrounded by a mold member 24 except for a circuit formation surface.
  • the extended wafer 26 is formed into a standard wafer shape having a larger diameter (300 mm wafer shape) than the original silicon wafer 20 (for example, 200 mm wafer shape) so as to be suitably adapted to an existing manufacturing process.
  • FIG. 5B shows an aspect of the extended wafer 26 obtained after the molding process. As shown in FIG. 5B, an expanded wafer 26 is obtained in which the separated silicon chips 22 are embedded in the mold member 24 while being separated by a substantially constant distance.
  • a rewiring layer forming step is performed on the obtained expansion wafer 26 to form a rewiring layer 28 on the expansion wafer 26.
  • the detailed structure of the rewiring layer 28 is omitted in FIG. More specifically, the rewiring layer 28 has a structure as shown in FIGS. 1 and 2 for each silicon chip 22.
  • the rewiring layer forming step first, polyimide or the like is applied on the expansion wafer 26. Next, an opening of the polyimide film is formed at a position corresponding to an electrode pad (corresponding to the electrode pad 106 in FIG. 1) of each silicon chip 22 (corresponding to the silicon chip 102 in FIG. 1) by patterning. A first dielectric layer (corresponding to the dielectric layer 112b in FIG. 1) is formed. Subsequently, rewiring patterns (corresponding to the rewiring pattern 114 in FIG. 1) for the respective silicon chips 22 are collectively formed by patterning. Further, polyimide or the like is applied so as to cover the rewiring pattern.
  • an opening of a polyimide film is provided at a position corresponding to the external terminal pad (corresponding to the external terminal pad 107 in FIG. 1) by patterning, and the second dielectric layer (dielectric layer in FIG. 1). 112a) is formed.
  • the extended wafer 26 is formed as a large-diameter standard wafer shape.
  • the rewiring pattern 114 can be formed by a manufacturing apparatus capable of handling a large-diameter standard wafer (for example, 300 mm wafer), which is excellent in high-density design according to a wafer level ground rule.
  • solder balls 30 are directly arranged on the external terminal pads for mounting the solder balls of the rewiring layer 28 by the ball mounting method. And a solder joint is formed by a subsequent reflow process.
  • the expansion wafer 26 on which the solder balls 30 are mounted is aligned and mounted on the ring frame 16 via the wafer mounting tape 17 for dicing.
  • the surface of the expansion wafer 26 not including the circuit formation surface of the silicon chip (hereinafter simply referred to as the back surface) is mounted so as to be in contact with the wafer mount tape 17.
  • FIG. 5C shows a mode after the dicing process for the expansion wafer 26.
  • the extended wafer 26 is diced along the cutting lines 26a and 26b, and the semiconductor package 100 separated into pieces is obtained.
  • the dicing method is not particularly limited, and can be performed using the same method as dicing to the silicon wafer 20.
  • the separated semiconductor package 100 is separated by, for example, a tape expanding process, and mounted on a tray, a tape and reel, or a tube by a pick and place system and packed. Then, it is provided for the subsequent characteristic inspection process, mounting process on PCB, and the like.
  • the silicon wafer 20 shown in FIG. 3B is polished on the back surface, and then the dicing process shown in FIG. I have done it.
  • a DBG (Dicing Before Grinding) process is applied, the silicon wafer is half-cut, and the half-cut silicon wafer is mounted on the ring frame 10 via the wafer mount tape 11 (FIG. 3 ( A), and then a back surface polishing step is performed (corresponding to FIG. (B)), so that the silicon wafer can be thinned and singulated simultaneously.
  • DBG Dynamicing Before Grinding
  • the expanding step can be performed using the wafer mount tape 11 for polishing the back surface as it is as the wafer mount tape for expanding (corresponding to FIG. 3D).
  • the wafer mount tape 11 for polishing the back surface as it is as the wafer mount tape for expanding (corresponding to FIG. 3D).
  • the silicon wafer 20 shown in FIG. 3B has been described as performing the back surface polishing step.
  • the back surface polishing step shown in FIG. 3B may be omitted.
  • the ring frame is interposed via the wafer mounting tape 13 for dicing. 10 can be started from the dicing process (corresponding to FIG. 3C).
  • a back surface polishing process is performed on the expansion wafer 26 until the back surface of the silicon chip 22 is exposed. Can be scraped off.
  • the backside polishing process of the extended wafer 26 is preferably performed after the rewiring layer forming process shown in FIG. 4B from the viewpoint of obtaining sufficient flatness in the rewiring layer forming process.
  • the solder ball 30 is low (for example, 200 ⁇ m or less)
  • the back surface polishing step of the expansion wafer 26 can be performed after obtaining the solder joint in FIG.
  • the thinning and individualization of the extended wafer 26 are performed simultaneously. You can also.
  • the back surface polishing process of the extended wafer 26 is performed, the back surface polishing process for the silicon wafer 20 shown in FIG. 3B may be omitted, and the silicon chip 22 together with the mold member 24 may be thinned.
  • the solder ball 30 is mounted before the expansion wafer 26 is separated into individual pieces in FIG. 4E.
  • the process of mounting the solder ball 30 is performed by a semiconductor. The process may be performed after being separated into packages 100, and is not particularly limited.
  • the cut silicon chips 22 are molded in a state where the chip intervals are enlarged substantially uniformly at once by the tape expanding process, and the intervals are enlarged. Therefore, wafer level packaging advantageous in terms of time, cost, and yield is realized.
  • the process is simplified compared with the pick-and-place process in which the individual silicon chips 22 are arranged one by one on the substrate, which is advantageous in process time. .
  • the extended wafer 26 can be handled as a standard size wafer used in an existing wafer processing process. Therefore, by preparing the molds 32 and 34 and the apparatus for the molding process according to the present invention, a production line can be constructed as a normal wafer process. Furthermore, the rewiring pattern can be applied to a wafer-level design ground rule (for example, a wiring width of 5 ⁇ m) instead of a package carrier design ground rule (for example, a wiring width of 40 ⁇ m), and is excellent in high-density design.
  • a wafer-level design ground rule for example, a wiring width of 5 ⁇ m
  • a package carrier design ground rule for example, a wiring width of 40 ⁇ m
  • FIG. 6 is a sectional view of a semiconductor package according to the second embodiment of the present invention. Since the semiconductor package 200 of the second embodiment has a structure and material configuration similar to those of the first embodiment, the following description focuses on the differences.
  • a semiconductor package 200 shown in FIG. 6 includes a silicon chip 202 having a circuit formation surface coated with a passivation film 204 and provided with a plurality of exposed electrode pads 206. Similar to the first embodiment, the silicon chip 202 is singulated through a dicing process after the wafer processing process.
  • the semiconductor package 200 includes a mold member 208 that surrounds the silicon chip 202 except for the circuit formation surface.
  • the silicon chip 202 and the mold member 208 constitute the expansion chip 210 as in the first embodiment.
  • a via hole penetrating from the front surface to the back surface of the expansion chip 210 is formed in the mold region on the outer periphery of the silicon chip 202 of the expansion chip 210.
  • the via hole is filled with a conductive material to form a through via 220.
  • the via hole formed in the outer peripheral mold region of the extension chip 210 is preferably formed at the time of molding.
  • the via hole can be formed by penetrating the mold member 208 using a mechanical drill or a laser drill.
  • the conductive material filling the via hole is not particularly limited, but a metal containing copper, tungsten, or the like can be preferably used.
  • a seed layer is formed on the inner side by electroless plating, and a metal is deposited and filled thereon by electrolytic plating to form a through via 220.
  • a non-metallic material such as a conductive polymer may be used as long as appropriate conductivity is obtained.
  • the through via 220 does not necessarily need to be completely filled, and may be configured by only a plating layer that covers the inner wall of the via hole, for example, as long as desired conductivity is obtained.
  • the semiconductor package 200 further includes a rewiring layer 216 formed on the silicon chip 202 and the mold member 208. More specifically, the redistribution layer 216 includes a first dielectric layer 212b, a redistribution pattern 214, and a second dielectric layer 212a.
  • the first dielectric layer 212b covers the extension chip 210 so that the electrode pad 206 on the circuit forming surface of the silicon chip 202 and the end portion on the surface side of the through via 220 are exposed.
  • the rewiring pattern 214 is formed to include an external terminal pad 207 and a via land 209 for connecting to the end of the through via 220 on the surface side, and is electrically connected to the through via 220.
  • the second dielectric layer 212a covers the rewiring pattern 214 so that the external terminal pads 207 are exposed.
  • the semiconductor package 200 of the second embodiment further includes a backside rewiring layer (hereinafter referred to as a backside rewiring layer) formed on the backside of the expansion chip 210.
  • the back surface side redistribution layer 228 includes a back surface side terminal pad 222 provided on the back surface of the extension chip 210 and connected to the through via 220, and a solder protection layer 226 that covers the back surface of the expansion chip 210. .
  • the solder protective layer 226 is opened at a position corresponding to the back surface side terminal pad 222 to expose the back surface side terminal pad 222.
  • the material of the solder protective layer 226 is not particularly limited, and an insulating resin material including polyimide, PBO, BCB, solder resist, and the like can be used.
  • the material of the back-side terminal pad 222 is not particularly limited, and a metal material such as copper or aluminum or an alloy material thereof can be used.
  • the back-side terminal pad 222 can be formed as a single layer or a plurality of layers by sputtering, electrolytic plating, electroless plating, or the like.
  • the back surface side terminal pad 222 is formed of the same material as the through via 220, the through via 220 and the plating layer on the back surface of the extension chip 210 (corresponding to the back surface side terminal pad 222) are simultaneously finished. You can also.
  • electroless plating is performed on the inner wall of the via hole and the base of the back surface of the extension chip 210, followed by electrolytic plating, thereby forming a through via 220 and a solid pattern plating layer on the back surface of the expansion chip 210. Then, the plating layer can be patterned by subsequent etching to form the final back surface side terminal pad 222.
  • the back surface side terminal pad 222 can be subjected to a surface treatment such as a nickel or gold plating layer (BLM layer) formation treatment or an antioxidant treatment (OSP) on the surface thereof.
  • a surface treatment such as a nickel or gold plating layer (BLM layer) formation treatment or an antioxidant treatment (OSP) on the surface thereof.
  • BBM layer nickel or gold plating layer
  • OSP antioxidant treatment
  • the back-side terminal pad 222 has a solder ball mounted thereon to provide connection with another package. Used for.
  • the semiconductor package 200 includes solder balls 218 disposed on the external terminal pads 207 of the redistribution layer 216, as in the first embodiment.
  • the solder balls 218 may also be arranged in the mold area around the silicon chip 202.
  • the rewiring pattern 214 provides electrical connection from the electrode pad 206 on the silicon chip 202 to the solder ball 218, and further from the electrode pad 206 to the back-side terminal pad 222 via the through via 220. Is giving a good connection.
  • a through silicon via (Through Silicon Vias; TSV) penetrating from the front surface to the back surface of the silicon chip 202 had to be formed.
  • TSV Through Silicon Vias
  • the through via 220 is formed in the mold member 208, it is not necessary to secure a region for forming the via in the circuit formation surface of the silicon chip 202. .
  • via lands for connection to the through vias 220 can be formed in a mold region that is substantially free of size restrictions. For this reason, it is possible to provide a connection to the back surface via the via land and the through via 220 and at the same time to secure a sufficient solder ball mounting area on the surface of the extension chip 210.
  • FIGS. 7A to 7E and FIGS. 8A to 8E are views showing a method for manufacturing the semiconductor package 200 according to the second embodiment of the present invention, together with the cross-sectional structure in each step.
  • the silicon wafer 20 that has been subjected to the wafer processing step is mounted on the ring frame 10 via a wafer mount tape 11 for back surface polishing.
  • the silicon wafer 20 is appropriately thinned by performing a back surface polishing process.
  • the silicon wafer 20 is aligned, replaced with a wafer mounting tape 13 for dicing, and subjected to a dicing process.
  • the wafer is mounted on the expanding wafer mount tape 15 and subjected to a tape expanding process.
  • the tape expanding process the silicon chips 22 with the gaps widened are obtained in a state where they are stuck on the wafer mount tape 15.
  • the manufacturing method is the same as in the first embodiment.
  • a description will be given with reference to FIGS.
  • the mold 36 is mounted on the wafer so that the silicon chip 22 arranged on the wafer mount tape 15 enters inside. Arranged in contact with the tape 15.
  • a mold 38 is prepared in which a pin 38a located around each silicon chip 22 is a part of the mold.
  • the shape of the pin 38a of the mold 38 is preferably a tapered shape in order to break through the wafer mount tape 15 and in consideration of mold release properties.
  • the mold 38 is pressed to contact the wafer mount tape 15, and at the same time, the pins 38a break through the wafer mount tape 15. It is inserted into the mold 36.
  • a molding process including via hole formation is performed.
  • the mold 38 is provided with a gate 36a for injecting a resin molding material. Then, the resin molding material is injected into the molds 36 and 38 while maintaining the chip interval on the wafer mount tape 15 by transfer molding, and the pins of the silicon chip 22 and the mold 38 are removed except for the surface in contact with the tape 15. 38a is molded.
  • the extended wafer 40 has a configuration in which a plurality of individual silicon chips 22 are surrounded by a mold member 24 except for a circuit formation surface. Further, since the extended wafer 40 is formed using the pins 38a as a part of the mold, a via hole 42 is formed so as to penetrate the mold member 24 from the front surface to the back surface of the extended wafer 40, located around each silicon chip 22. Is done.
  • the expansion wafer 40 is appropriately subjected to a step of polishing the back surface of the mold.
  • the back portion thereof is scraped off to obtain the extended wafer 40 having a desired thickness.
  • a conductive material is filled into the via hole 42 formed in the mold member 24 of the expansion wafer 40 by, for example, electroless plating and electrolytic plating. Thereby, a through via 44 extending from the surface of the expansion wafer 40 to the back surface through the mold member 24 is formed.
  • a back surface side rewiring layer (corresponding to the back surface side rewiring layer 228 in FIG. 6) 45 is formed on the back surface of the expansion wafer 40. Note that in FIG. 8B, the detailed structure of the back-side rewiring layer 45 is omitted.
  • a back-side terminal pad (corresponding to the back-side terminal pad 222 in FIG. 6) of the back-side rewiring layer 45 is provided at a position corresponding to the back-side end of the through via 44, and a BLM layer thereon. Is appropriately formed.
  • Polyimide or the like is applied to the back surface of the expansion wafer 40 including the back surface side terminal pad, and a polyimide film opening is provided at a position corresponding to the back surface side terminal pad by patterning, and a solder protective layer (solder protection in FIG. 6). Corresponding to layer 226).
  • a surface-side rewiring layer forming step is performed on the obtained expansion wafer 40 to thereby expand the expansion wafer 40.
  • a rewiring layer 46 on the surface side is formed thereon. Note that in FIG. 8C, the detailed structure of the rewiring layer 46 on the surface side is omitted. More specifically, the surface-side rewiring layer 46 has a structure as shown in FIG. 6 for each silicon chip 22.
  • polyimide or the like is first applied on the expansion wafer 40, and patterning is performed to form electrode pads (in FIG. 6, corresponding to the silicon chip 202) of the respective silicon chips 22 (in FIG. 6). , Corresponding to the electrode pad 206) and an opening corresponding to the through via 44, an opening of the polyimide film is provided to correspond to the first dielectric layer (corresponding to the dielectric layer 212 b in FIG. 6). Is formed. Subsequently, a rewiring pattern (corresponding to the rewiring pattern 214 in FIG. 6) is collectively formed on each silicon chip 22 by patterning. At this time, the rewiring pattern is electrically connected to the electrode pad on the silicon chip 22.
  • the rewiring pattern is electrically connected to the through via 44 (corresponding to the through via 220 in FIG. 6) via the via land (corresponding to the via land 209 in FIG. 6). Further, polyimide or the like is applied so as to cover the rewiring pattern, and an opening of the polyimide film is provided at a position corresponding to the external terminal pad (corresponding to the external terminal pad 207 in FIG. 6) by patterning. Two dielectric layers (corresponding to the dielectric layer 212a in FIG. 6) are formed.
  • solder balls 48 are disposed directly on the external terminal pads of the rewiring layer 46 by a ball mounting method.
  • a solder joint is formed by a subsequent reflow process.
  • the expansion wafer 40 on which the solder balls 48 are mounted is aligned, mounted on the ring frame 16 via the wafer mounting tape 17 for dicing, and subjected to a dicing process. .
  • the semiconductor package 200 separated from the extended wafer 40 is obtained by the dicing process.
  • the separated semiconductor package 200 is separated by, for example, a tape expanding process, and is mounted on a tray, a tape and reel, or a tube and packed by a pick and place system. Then, it is provided for the subsequent characteristic inspection process, mounting process on PCB, and the like.
  • the via holes 42 are collectively formed in the mold member 24 using the pins 38a as a part of the mold, and a conductive material is filled in the via holes 42 from the surface of the expansion wafer 40.
  • a through via 44 penetrating to the back surface is formed. This eliminates the need for advanced processing techniques such as deep reactive ion etching in the wafer processing process required for TSV.
  • the via hole 42 is collectively formed in the mold member 24 using the pin 38a as a part of the mold.
  • via holes can be formed in the mold member of the expansion wafer using a laser drill or a mechanical drill.
  • the mold for forming the expansion wafer does not need to have pins.
  • a plurality of expansion wafers can be stacked to form via holes at once.
  • FIG. 9 is a sectional view of a stacked package using a semiconductor package according to the second embodiment of the present invention.
  • a stacked package 250 shown in FIG. 9 has a PoP in which a solder ball 262 is mounted on a back surface side terminal pad 222 provided on the back surface of the semiconductor package 200 and another package 260 is connected via the solder ball 262. It has a structure.
  • no members other than the back-side terminal pads 222 for mounting the solder balls 262 are disposed on the back surface of the semiconductor package 200, and other members such as silicon chips are used. Because of the substantial release, the height restriction on the solder ball 262 is relaxed. Since the restriction on the height of the solder balls 262 is relaxed, the pitch of the solder balls 262 can be reduced without reducing the yield.
  • FIG. 10A is a sectional view of a semiconductor package according to the third embodiment of the present invention. Since the semiconductor package 300 of the third embodiment has a structure and material configuration similar to those of the first embodiment, the following description will focus on differences.
  • a semiconductor package 300 shown in FIG. 10A has a structure in which the back portion of the mold member of the semiconductor package shown in FIG. Yes.
  • the semiconductor package is thinned, and a heat sink or the like can be disposed in contact with the silicon chip 302. Therefore, high heat dissipation can be obtained.
  • FIG. 10B is a sectional view of a semiconductor package according to the fourth embodiment of the present invention. Since the semiconductor package 400 of the fourth embodiment has a structure and material configuration similar to those of the second embodiment, the following description will focus on the differences.
  • the back-side terminal pads 424 are formed in an array from the center over the entire back surface of the semiconductor package shown in FIG.
  • a back surface via land 422 is formed on the back surface of the expansion chip 210 and located immediately below the through via 420.
  • the backside via land 422 and the backside terminal pad 424 are connected by a wiring (not shown) (hereinafter referred to as a backside rewiring).
  • the back-side terminal pads 424 are electrically connected to the electrode pads 406 on the circuit formation surface of the silicon chip 402 via the back-side rewiring, the back-side via land 422, the through via 420, and the front-side rewiring pattern, respectively. Connected.
  • the semiconductor package 400 of the fourth embodiment further includes a solder protective layer that covers the back-side terminal pads 424, the back-side via lands 422, and the back-side rewiring (hereinafter collectively referred to as the back-side rewiring pattern). 426.
  • the solder protective layer 426 is opened at a position corresponding to the back-side terminal pad 424 to provide external connection, and the back-side terminal pad 424 is exposed.
  • An opening of the solder protective layer 426 may be provided at a position corresponding to the back via land 422 immediately below the through via 420, and a part of the back via land 422 may be used as a terminal pad.
  • the material for the backside rewiring pattern is not particularly limited, but a metal such as copper or aluminum or an alloy thereof can be used. Similar to the semiconductor package of the second embodiment, the back-side rewiring pattern can be formed as a single layer or a plurality of layers by a sputtering method, an electrolytic plating method, an electroless plating method, or the like. A BLM layer having solder wettability can be appropriately formed on the back-side terminal pad 424 of the back-side rewiring pattern, and solder balls can be mounted thereon.
  • the back side redistribution pattern and the protective layer 426 can be formed.
  • the back-side rewiring layer 428 including the back-side rewiring pattern and the protective layer 426 is formed on the back surface of the expansion wafer 40 from a region immediately below each silicon chip 22 to a region outside the silicon chip 22.
  • terminal pads can be provided on the back surface of the package from the central portion to the outer peripheral portion. Therefore, when the predetermined number of input / output pins is required, the pitch between the solder balls can be relaxed by using the back surface side terminal pad 424, and the yield and the reliability of connection can be improved. It becomes possible.
  • the back portion of the silicon chip 402 of the mold member 408 may be scraped to reduce the thickness to about the silicon chip 402 thickness. it can.
  • an insulating layer is appropriately provided on the back surface of the silicon chip 402, and a back surface side rewiring pattern can be formed thereon.
  • the restriction due to the chip size with respect to the number of connection terminals such as solder balls is relaxed, so that the number of connection pins has a high number of input / output pins.
  • a highly reliable semiconductor package with a good yield and a method for manufacturing the same are provided.
  • connection terminal bump to the outside of the package is not particularly limited.
  • an LGA (Land Grid Array) structure including planar electrode pads or a PGA (Pin Grid Array) structure may be employed instead of the solder balls.
  • An array structure in which bumps are formed by forming a rewiring layer on a resin core instead of the solder balls can also be adopted.
  • silicon has been described as an example of a semiconductor material constituting a semiconductor wafer and a semiconductor chip.
  • silicon is polycrystalline even if it is a single crystal of any crystal plane. Also good.
  • an SOI (Silicon On On Insulator) wafer, a SiGe / SOI wafer, a GaAs wafer, and other compound semiconductor wafers may be used instead of the silicon wafer and the silicon chip.
  • connection terminal bumps in the semiconductor package is not limited to the illustrated lattice-like embodiment, and an array having any arrangement structure can be used.
  • the number of solder balls is not limited to the number shown.
  • the shapes of the silicon chip and the extension chip are not limited to the illustrated square.

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Abstract

L'invention porte sur un boîtier de semi-conducteur de niveau tranche possédant une surface de région de montage importante pour des bornes de connexion périphériques et sur un procédé de fabrication du boîtier de semi-conducteur. Le procédé de fabrication comprend : (a) une étape de division d'une tranche semi-conductrice (20) en une pluralité de puces semi-conductrices (22); (b) une étape d'augmentation de distance entre les puces semi-conductrices (22); (c) une étape de formation d'une tranche expansée (26) par entourage des puces semi-conductrices (22) au moyen d'un élément de moule (24) en laissant les surfaces de formation de circuit, respectivement; (d) une étape de formation d'une couche de recâblage (28) qui possède, sur la tranche d'expansion (26), un motif de recâblage (114) présentant une plage de connexion de borne (107) pour monter un bossage de borne de connexion, et qui s'étend à partir d'un plage de connexion d'électrode (106) sur une surface de formation de circuit (19) de la puce semi-conductrice (22) vers la région à l'extérieur de la puce semi-conductrice (22); et (e) une étape de formation d'une pluralité de boîtiers de semi-conducteur (100) par division de la tranche expansée (26) possédant la couche de recâblage (28) formée sur celle-ci en morceaux.
PCT/JP2009/065316 2008-11-21 2009-09-02 Boîtier de semi-conducteur et son procédé de fabrication WO2010058646A1 (fr)

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WO2016125683A1 (fr) * 2015-02-06 2016-08-11 リンテック株式会社 Feuille adhésive et procédé de fabrication de dispositif à semi-conducteur
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KR20180062401A (ko) * 2016-11-30 2018-06-08 에이에스엠 테크놀러지 싱가포르 피티이 엘티디 웨이퍼 레벨 반도체 패키지들을 제조하기 위한 방법
CN108831860A (zh) * 2018-08-09 2018-11-16 苏州晶方半导体科技股份有限公司 堆叠式芯片封装方法及封装结构
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JP2019129222A (ja) * 2018-01-24 2019-08-01 リンテック株式会社 長尺積層シートおよびその巻収体
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