WO2017177498A1 - Tft基板及其制作方法 - Google Patents

Tft基板及其制作方法 Download PDF

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WO2017177498A1
WO2017177498A1 PCT/CN2016/081967 CN2016081967W WO2017177498A1 WO 2017177498 A1 WO2017177498 A1 WO 2017177498A1 CN 2016081967 W CN2016081967 W CN 2016081967W WO 2017177498 A1 WO2017177498 A1 WO 2017177498A1
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layer
active layer
photoresist
tft
forming
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French (fr)
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王涛
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/039,853 priority Critical patent/US20180083047A1/en
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a TFT substrate and a method of fabricating the same.
  • Liquid crystal display is one of the most widely used flat panel displays.
  • the liquid crystal panel is a core component of liquid crystal displays.
  • a conventional liquid crystal display panel usually consists of a color filter (CF) substrate, a thin film transistor array substrate (TFT Array Substrate), and a liquid crystal layer disposed between the two substrates (Liquid Crystal). Layer), the working principle is to place liquid crystal molecules in two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates. The liquid crystal molecules can be controlled to change direction by energizing or not. The light is refracted to produce a picture.
  • a thin film transistor array is prepared on the thin film transistor array substrate for driving the rotation of the liquid crystal to control the display of each pixel, and the color filter substrate is provided with a color filter layer for forming the color of each pixel.
  • FIG. 1 is a schematic structural view of a conventional TFT substrate, including a base substrate 100 ′ and a light shielding layer 200 ′ and a buffer layer 300 ′ disposed on the substrate substrate 100 ′ from bottom to top. , TFT 400 ′, planarization layer 500 ′, underlying electrode 600 ′, passivation layer 700 ′, and top electrode 800 ′.
  • the TFT 400' includes an active layer 410', a gate insulating layer 420', a gate 430', an interlayer dielectric layer 440', a source 450', and a drain 460', which are sequentially disposed from bottom to top, and a source
  • the 450' and the drain 460' are respectively connected to both ends of the active layer 410' through the first via hole 910' and the second via hole 920' penetrating through the gate insulating layer 420' and the interlayer dielectric layer 440.
  • FIG. 2 is a top plan view of a TFT in the TFT substrate of FIG. 1.
  • the TFT 400' is a top gate structure, and the active layer 410' is disposed under the gate 430'.
  • the active layer 410' is fabricated. This is accomplished by applying a mask photoresist on the active layer 410' and performing dry etching.
  • 3 is a cross-sectional view of the TFT in the TFT substrate of FIG. 1 taken along the line A'-A' in FIG. 2. As can be seen from FIG. 3, along the length direction of the gate 430', The active layer 410' has a tip 415' on both sides thereof.
  • the tip 415' on both sides of the active layer 410' When the TFT 400' is in operation, the tip 415' on both sides of the active layer 410' generates an electric field concentration effect, and the carrier induced at the tip 415' is generated. The concentration increases to form a side parasitic TFT, thereby changing the output electrical properties of the TFT 400', causing a phenomenon that the TFT is opened in advance, which affects the normal display operation of the liquid crystal display panel.
  • Another object of the present invention is to provide a method for fabricating a TFT substrate, which avoids the influence of the active layer structure on the output power of the TFT, improves the quality of the TFT, and enhances the operational stability of the TFT substrate.
  • the present invention first provides a TFT substrate, comprising: a substrate substrate, and a TFT disposed on the substrate;
  • the TFT includes: an active layer, a gate insulating layer disposed on the active layer, a gate disposed on the gate insulating layer and having a horizontal position corresponding to the active layer, disposed at the gate And an interlayer dielectric layer on the gate insulating layer; and a source and a drain disposed on the interlayer dielectric layer;
  • the active layer includes at least a first region in the middle and a second region on both sides of the first region along a length direction of the gate, the thickness of the first region being greater than the thickness of the second region, such that The active layer has at least one step on both sides.
  • the active layer prepared in the step 2 has a step on both sides.
  • the TFT substrate further includes: a light shielding layer and a buffer layer disposed between the base substrate and the TFT, a planarization layer disposed on the TFT, a bottom electrode disposed on the planarization layer, and disposed on a passivation layer on the bottom electrode and a top electrode disposed on the passivation layer.
  • the active layer corresponds to the light shielding layer, and the light shielding layer completely covers the active layer in the horizontal direction.
  • the gate insulating layer and the interlayer dielectric layer are provided with first through holes and second through holes at positions corresponding to opposite ends of the active layer, and the source and the drain respectively pass through the first through holes and the second through holes Connecting the two ends of the active layer;
  • a third via is disposed at a position corresponding to the drain on the planarization layer, and the top electrode is connected to the drain through the third via.
  • the invention also provides a method for fabricating a TFT substrate, comprising the following steps:
  • Step 1 Providing a substrate, forming a semiconductor material layer on the substrate, forming a photoresist layer on the semiconductor material layer, and exposing the photoresist layer by using a gray scale mask Developing, obtaining a photoresist pattern, along the length direction of the gate, the photoresist pattern includes at least a first photoresist segment located in the middle, and a second photoresist segment on both sides, and the a thickness of the photoresist segment is greater than a thickness of the second photoresist segment;
  • Step 2 performing at least two-step etching on the photoresist pattern and the semiconductor material layer by using a gas that can etch both the photoresist pattern and the semiconductor material layer:
  • the first etching is to thin a portion of the semiconductor material layer outside the second photoresist segment while thinning the first photoresist segment of the photoresist pattern, and the lithography Glue pattern
  • the second photoresist segment is completely etched away;
  • the second etching step is to completely etch away the first photoresist segment of the photoresist pattern, completely etch away the portion of the semiconductor material layer outside the second photoresist segment, and simultaneously A portion of the semiconductor material layer corresponding to the second photoresist segment is thinned to obtain an active layer, the active layer including at least a first region located in the middle and corresponding to the first photoresist segment, and located at the a second region on both sides of a region and corresponding to the second photoresist segment, the thickness of the first region being greater than the thickness of the second region, such that both sides of the active layer have at least one step;
  • Step 3 forming a gate insulating layer on the active layer, forming a gate on the gate insulating layer corresponding to the position of the active layer, and forming an interlayer dielectric on the gate and the gate insulating layer A layer is formed on the interlayer dielectric layer to form a source and a drain, thereby completing fabrication of the TFT.
  • the active layer prepared in the step 2 has a step on both sides.
  • the step 1 further includes a step of forming a light shielding layer and a buffer layer between the base substrate and the semiconductor material layer;
  • the method for fabricating the TFT substrate further includes: step 4, forming a planarization layer on the TFT, forming an underlying electrode on the planarization layer, and forming a passivation layer on the underlying electrode, in the passivation A top electrode is formed on the layer.
  • the active layer prepared in the step 2 corresponds to the light shielding layer, and the light shielding layer completely covers the active layer in the horizontal direction.
  • the step 3 further includes a step of forming a first via hole and a second via hole at positions corresponding to both ends of the active layer on the gate insulating layer and the interlayer dielectric layer; the source and the drain respectively pass through a through hole and a second through hole are connected to both ends of the active layer;
  • the step 4 further includes a step of forming a third via hole at a position corresponding to the drain on the planarization layer, the top electrode being connected to the drain through the third via hole.
  • the invention also provides a method for fabricating a TFT substrate, comprising the following steps:
  • Step 1 Providing a substrate, forming a semiconductor material layer on the substrate, forming a photoresist layer on the semiconductor material layer, and exposing and developing the photoresist layer by using a photomask And obtaining a photoresist pattern, along the length direction of the gate, the photoresist pattern includes at least a first photoresist segment located in the middle, and a second photoresist segment on both sides, and the first light The thickness of the engraved segment is greater than the thickness of the second photoresist segment;
  • Step 2 performing at least two-step etching on the photoresist pattern and the semiconductor material layer by using a gas that can etch both the photoresist pattern and the semiconductor material layer:
  • the first etching is to thin a portion of the semiconductor material layer outside the second photoresist segment while thinning the first photoresist segment of the photoresist pattern, and the lithography
  • the second photoresist segment of the glue pattern is completely etched away;
  • the second etching step is to completely etch away the first photoresist segment of the photoresist pattern, completely etch away the portion of the semiconductor material layer outside the second photoresist segment, and simultaneously A portion of the semiconductor material layer corresponding to the second photoresist segment is thinned to obtain an active layer, the active layer including at least a first region located in the middle and corresponding to the first photoresist segment, and located at the a second region on both sides of a region and corresponding to the second photoresist segment, the thickness of the first region being greater than the thickness of the second region, such that both sides of the active layer have at least one step;
  • Step 3 forming a gate insulating layer on the active layer, forming a gate on the gate insulating layer corresponding to the position of the active layer, and forming an interlayer dielectric on the gate and the gate insulating layer a layer, a source and a drain are formed on the interlayer dielectric layer to complete fabrication of the TFT;
  • the active layer prepared in the step 2 has a step on both sides;
  • the step 1 further includes a step of forming a light shielding layer and a buffer layer between the base substrate and the semiconductor material layer;
  • the method further includes: step 4, forming a planarization layer on the TFT, forming a bottom electrode on the planarization layer, forming a passivation layer on the underlying electrode, and forming a top electrode on the passivation layer.
  • the TFT substrate provided by the present invention includes: a base substrate, and a TFT disposed on the base substrate, the TFT substrate being activated by improving a structure of an active layer in the TFT
  • the two sides of the layer have at least one step.
  • the electric field concentration effect of the tip of the side surface of the active layer can be effectively weakened, and the concentration of carriers in the active layer is made. Uniformity makes the output of the TFT stable, the quality of the TFT is high, and the working stability of the TFT array substrate is strong.
  • the method for fabricating the TFT array substrate provided by the invention can effectively reduce the electric field concentration effect of the tip of the active layer side step in the TFT, make the carrier concentration in the active layer uniform, stabilize the output electrical property of the TFT, and improve the TFT.
  • the quality in turn, enhances the operational stability of the TFT array substrate.
  • 1 is a schematic structural view of a conventional TFT substrate
  • FIG. 2 is a schematic plan view of a TFT in the TFT substrate of FIG. 1;
  • FIG 3 is a cross-sectional view of the TFT in the TFT substrate of Figure 1 taken along the line A'-A' in Figure 2;
  • FIG. 4 is a schematic structural view of a TFT substrate of the present invention.
  • FIG. 5 is a schematic plan view of a TFT in the TFT substrate of FIG. 4;
  • FIG. 6 is a cross-sectional view of the TFT in the TFT substrate of FIG. 4 taken along line A-A of FIG. 5;
  • FIG. 7 is a flow chart showing a method of fabricating a TFT substrate of the present invention.
  • FIGS. 8-9 are schematic diagrams showing the first step of the method for fabricating the TFT substrate of the present invention.
  • FIGS 10-11 are schematic views showing the second step of the method for fabricating the TFT substrate of the present invention.
  • the present invention provides a TFT substrate, comprising: a substrate substrate 100, and a TFT 400 disposed on the substrate substrate 100;
  • the TFT 400 includes an active layer 410, a gate insulating layer 420 disposed on the active layer 410, a gate 430 disposed on the gate insulating layer 420 and corresponding to the active layer 410 at a horizontal position, An interlayer dielectric layer 440 disposed on the gate 430 and the gate insulating layer 420, and a source 450 and a drain 460 disposed on the interlayer dielectric layer 440;
  • the active layer 410 includes at least a first region 411 located in the middle and a second region 412 located at two sides of the first region 411.
  • the thickness of the first region 411 is greater than the thickness of the second region 412 such that both sides of the active layer 410 have at least one step.
  • the width of the second region 412 is one-twentieth to one-tenth of the width of the first region 411.
  • the active layer 410 has a step on both sides.
  • the TFT substrate further includes: a light shielding layer 200 and a buffer layer 300 disposed between the base substrate 100 and the TFT 400, a planarization layer 500 disposed on the TFT 400, and a planarization layer disposed on the TFT
  • the active layer 410 corresponds to the light shielding layer 200, and the light shielding layer 200 completely covers the active layer 410 in the horizontal direction, so that the active layer 410 can be shielded from light to prevent photoelectric effect from being caused by the TFT.
  • the leakage current affects the display effect.
  • a first via 910 and a second via 920 are disposed on the gate insulating layer 420 and the interlayer dielectric layer 440 at positions opposite to the active layer 410.
  • the source 450 and the drain 460 are respectively Connecting the two ends of the active layer 410 through the first through hole 910 and the second through hole 920;
  • a third via hole 930 is disposed on the planarization layer 500 corresponding to the drain 460.
  • the top electrode 800 is connected to the drain 460 through the third via 930.
  • the base substrate 100 is a glass substrate.
  • the bottom electrode 600 and the top electrode 800 are a common electrode and a pixel electrode, respectively, and the materials of the bottom electrode 600 and the top electrode 800 are transparent conductive materials, and the transparent conductive material is preferably indium tin (Indium Tin). Oxides, ITO).
  • the material of the active layer 410 is polysilicon (Poly-Si).
  • the above TFT substrate is modified by the structure of the active layer 410 in the TFT 400 such that both sides of the active layer 400 have at least one step, and the active layer 410 is on both sides of the active layer 410 compared to the active layer in the prior art.
  • the electric field concentration effect is weakened, the carrier concentration inside the active layer 410 is uniform, and the side surface of the active layer 410 and the upper gate 430 are prevented from forming side parasitic TFTs, thereby effectively controlling the output electrical properties of the TFT 400 and improving the quality of the TFT 400. Further, the stability of the operation of the TFT substrate is enhanced.
  • the present invention further provides a method for fabricating a TFT substrate based on the TFT substrate, which includes the following steps:
  • Step 1 as shown in FIG. 8-9, a substrate substrate 100 is formed, a semiconductor material layer 10 is formed on the substrate substrate 100, and a photoresist layer 11 is formed on the semiconductor material layer 10, using a The photoresist layer 11 exposes and develops the photoresist layer 11 to obtain a photoresist pattern 20.
  • the photoresist pattern 20 includes at least a first photoresist segment 21 located in the middle along the length direction of the gate electrode. And a second photoresist segment 22 on both sides, and the thickness of the first photoresist segment 21 is greater than the thickness of the second photoresist segment 22.
  • the step 1 further includes the step of forming the light shielding layer 200 and the buffer layer 300 between the base substrate 100 and the semiconductor material layer 10 .
  • Step 2 As shown in FIG. 10-11, the photoresist pattern 20 and the semiconductor material layer 10 are etched at least two steps by using a gas that can be etched by the photoresist pattern 20 and the semiconductor material layer 10:
  • the first etching is to thin the portion of the semiconductor material layer 10 outside the second photoresist segment 22 while the first photoresist of the photoresist pattern 20 is used.
  • the segment 21 is thinned, and the second photoresist segment 22 of the photoresist pattern 20 is completely etched away;
  • the second etching step is to completely etch the first photoresist segment 21 of the photoresist pattern 20, and the semiconductor material layer 10 is located outside the second photoresist segment 22.
  • the portion is completely etched away while the portion of the semiconductor material layer 10 corresponding to the second photoresist segment 22 is thinned to obtain an active layer 410, the active layer 410 including at least the middle and corresponding to the first a first region 411 of the photoresist segment 21 and a second region 412 located on both sides of the first region 411 and corresponding to the second photoresist segment 22, the first region 411 having a thickness greater than the second region 412
  • the thickness of the active layer 410 has at least one step on both sides.
  • the active layer 410 prepared in the step 2 has a step on both sides.
  • the reticle 15 is a Gray Tone Mask (GTM), a Half Tone Mask (HTM), or a Single Slit Mask (SSM). ).
  • GTM Gray Tone Mask
  • HTM Half Tone Mask
  • SSM Single Slit Mask
  • the etching gas used in the step 2 is composed of a plurality of gas components, and the etching rate of the etching gas to the semiconductor material layer 10 and the etching gas can be made to light by adjusting the ratio of each gas component.
  • the etching rate of the engraved pattern 20 is maintained at a certain ratio.
  • the first etching and the second etching are both dry etching.
  • the active layer 410 prepared in the step 2 corresponds to the light shielding layer 200, and the light shielding layer 200 completely covers the active layer 410 in the horizontal direction, so that the active layer 410 can be shielded from light. Preventing the photoelectric effect causes the TFT to generate leakage current to affect the display effect.
  • Step 3 as shown in FIG. 4, a gate insulating layer 420 is formed on the active layer 410, and a gate 430 is formed on the gate insulating layer 420 corresponding to the position of the active layer 410.
  • An interlayer dielectric layer 440 is formed on the 430 and the gate insulating layer 420, and a source 450 and a drain 460 are formed on the interlayer dielectric layer 440 to complete the fabrication of the TFT 400.
  • the method for fabricating the TFT substrate further includes: step 4, forming a planarization layer 500 on the TFT 400, and forming a bottom electrode 600 on the planarization layer 500, A passivation layer 700 is formed on the underlying electrode 600, and a top electrode 800 is formed on the passivation layer 700.
  • the step 3 further includes forming a first via 910 and a second via at a position corresponding to both ends of the active layer 410 on the gate insulating layer 420 and the interlayer dielectric layer 440.
  • Step 920; the source 450 and the drain 460 are respectively connected to both ends of the active layer 410 through the first through hole 910 and the second through hole 920;
  • the step 4 further includes a step of forming a third via 930 on the planarization layer 500 corresponding to the position of the drain 460.
  • the top electrode 800 is connected to the drain 460 through the third via 930.
  • the base substrate 100 is a glass substrate.
  • the bottom electrode 600 and the top electrode 800 are a common electrode and a pixel electrode, respectively, and the materials of the bottom electrode 600 and the top electrode 800 are transparent conductive materials, and the transparent conductive material is preferably indium tin (Indium Tin). Oxides, ITO).
  • the material of the active layer 410 is polysilicon (Poly-Si).
  • the active layer 410 has at least one step on both sides thereof, and the active layer is compared to the active layer in the prior art.
  • the electric field concentration effect on both sides of the 410 is weakened, so that the carrier concentration inside the active layer 410 is uniform, and the side surface of the active layer 410 and the upper gate 430 are prevented from forming side parasitic
  • the TFT effectively controls the output power of the TFT 400, improves the quality of the TFT 400, and further enhances the stability of the operation of the TFT substrate.
  • the TFT substrate of the present invention includes: a base substrate, and a TFT disposed on the base substrate, the TFT substrate being improved in structure of an active layer in the TFT such that the active layer At least one step on both sides, compared with the active layer in the prior art, the electric field concentration effect of the tip on both sides of the active layer can be effectively weakened, the concentration of carriers in the active layer is uniform, and the output of the TFT is made.
  • the electrical stability is stable, the quality of the TFT is high, and the working stability of the TFT substrate is strong.
  • the method for fabricating the TFT substrate of the present invention can effectively reduce the electric field concentration effect at the tip end of the active layer in the TFT, make the carrier concentration in the active layer uniform, stabilize the output electrical properties of the TFT, and improve the quality of the TFT. Enhance the working stability of the TFT substrate.

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Abstract

一种TFT基板及其制作方法，该TFT基板通过对TFT(400)中的有源层(410)的结构进行改进，使得有源层(410)的两侧均具有至少一个台阶，相比于现有技术中的有源层(410')，能够有效减弱有源层(410)两侧的尖端电场集中效应，使有源层(410)中载流子的浓度均匀，控制TFT(400)的输出电性，TFT(400)的质量高，TFT基板的工作稳定性强。TFT基板的制作方法，能够有效减弱TFT(400)中有源层(410)两侧的尖端电场集中效应，使有源层(410)中的载流子浓度均匀，控制TFT(400)的输出电性，TFT(400)的质量高，TFT基板的工作稳定性强。

Description

TFT基板及其制作方法 技术领域
本发明涉及液晶显示技术领域，尤其涉及一种TFT基板及其制作方法。
背景技术
液晶显示器(Liquid Crystal Display，LCD)是目前最广泛使用的平板显示器之一，液晶面板是液晶显示器的核心组成部分。
传统的液晶显示面板通常是由一彩色滤光片(Color Filter，CF)基板、一薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)以及一配置于两基板间的液晶层(Liquid Crystal Layer)所构成，其工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。其中薄膜晶体管阵列基板上制备薄膜晶体管阵列，用于驱动液晶的旋转，控制每个像素的显示，而彩色滤光片基板上设有彩色滤光层，用于形成每个像素的色彩。
请参阅图1，为现有的TFT基板的结构示意图，包括衬底基板100’及在衬底基板100’上由下而上依次设置的遮光层(Light shielding Layer)200’、缓冲层300’、TFT400’、平坦化层500’、底层电极600’、钝化层700’、及顶层电极800’。其中，TFT400’包括由下至上依次设置的有源层410’、栅极绝缘层420’、栅极430’、层间介电层440’、源极450’、及漏极460’，源极450’与漏极460’分别通过贯穿栅极绝缘层420’、及层间介电层440的第一通孔910’及第二通孔920’与有源层410’的两端连接。
请参阅图2，为图1的TFT基板中的TFT的俯视示意图，该TFT400’为顶栅结构，有源层410’设置在栅极430’的下方，所述有源层410’的制作是通过在有源层410’上涂布掩膜光刻胶并进行干蚀刻而完成的。请参阅图3，为图1的TFT基板中的TFT沿图2中的A’-A’线的剖视示意图，从图3中可以看出，沿所述栅极430’的长度方向，所述有源层410’的两侧均具有一尖端415’，在TFT400’工作时，有源层410’两侧的尖端415’会产生电场集中效应，使尖端415’处感应出的载流子的浓度增大，形成侧面寄生TFT，从而使TFT400’的输出电性改变，产生TFT提前打开的现象，影响液晶显示面板正常的显示工作。
发明内容
本发明的目的在于提供一种TFT基板，避免有源层结构对TFT输出电性的影响，TFT质量高，工作稳定性强。
本发明的另一目的在于提供一种TFT基板的制作方法，避免有源层结构对TFT输出电性的影响，提升TFT质量，增强TFT基板的工作稳定性。
为实现上述目的，本发明首先提供一种TFT基板，包括：衬底基板、及设置在所述衬底基板上的TFT；
所述TFT包括：有源层、设置在所述有源层上的栅极绝缘层、设置在所述栅极绝缘层上且水平位置与有源层对应的栅极、设置在所述栅极及栅极绝缘层上的层间介电层、及设置在所述层间介电层上的源极及漏极；
沿栅极的长度方向，所述有源层至少包括位于中间的第一区域、及位于所述第一区域两侧的第二区域，所述第一区域的厚度大于第二区域的厚度，使得所述有源层的两侧均具有至少一个台阶。
所述步骤2制得的有源层的两侧均具有一个台阶。
所述TFT基板还包括：设置在所述衬底基板与TFT之间的遮光层与缓冲层、设置在所述TFT上的平坦化层、设置在所述平坦化层上的底层电极、设置在所述底层电极上的钝化层、及设置在所述钝化层上的顶层电极。
所述有源层与遮光层相对应，且所述遮光层在水平方向上完全覆盖所述有源层。
所述栅极绝缘层和层间介电层上对应有源层两端的位置设有第一通及第二通孔，所述源极与漏极分别通过第一通孔及第二通孔与有源层的两端连接；
所述平坦化层上对应漏极的位置设有第三通孔，所述顶层电极通过第三通孔与漏极连接。
本发明还提供一种TFT基板的制作方法，包括以下步骤：
步骤1、提供一衬底基板，在所述衬底基板上形成半导体材料层，并在所述半导体材料层上形成光刻胶层，采用一道灰阶光罩对所述光刻胶层进行曝光、显影，得到光刻胶图案，沿栅极的长度方向，所述光刻胶图案至少包括位于中间的第一光刻胶段、及位于两侧的第二光刻胶段，且所述第一光刻胶段的厚度大于所述第二光刻胶段的厚度；
步骤2、采用对所述光刻胶图案与半导体材料层均能进行蚀刻的气体对所述光刻胶图案与半导体材料层进行至少两步蚀刻：
第一步蚀刻是将所述半导体材料层上位于所述第二光刻胶段外侧的部分变薄，同时将所述光刻胶图案的第一光刻胶段变薄，将所述光刻胶图案 的第二光刻胶段完全蚀刻掉；
第二步蚀刻是将所述光刻胶图案的第一光刻胶段完全蚀刻掉，将所述半导体材料层上位于所述第二光刻胶段外侧的部分完全蚀刻掉，同时将所述半导体材料层上对应于第二光刻胶段的部分变薄，得到有源层，所述有源层至少包括位于中间且对应于第一光刻胶段的第一区域、及位于所述第一区域两侧且对应于第二光刻胶段的第二区域，所述第一区域的厚度大于第二区域的厚度，使得所述有源层的两侧均具有至少一个台阶；
步骤3、在所述有源层上形成栅极绝缘层，在所述栅极绝缘层上对应有源层的位置形成栅极，在所述栅极及栅极绝缘层上形成层间介电层，在所述层间介电层上形成源极及漏极，完成TFT的制作。
所述步骤2制得的有源层的两侧均具有一个台阶。
所述步骤1还包括在所述衬底基板与半导体材料层之间形成遮光层与缓冲层的步骤；
所述TFT基板的制作方法还包括：步骤4、在所述TFT上形成平坦化层，在所述平坦化层上形成底层电极，在所述底层电极上形成钝化层，在所述钝化层上形成顶层电极。
所述步骤2制得的有源层与遮光层相对应，且所述遮光层在水平方向上完全覆盖所述有源层。
所述步骤3还包括在所述栅极绝缘层和层间介电层上对应有源层两端的位置形成第一通孔及第二通孔的步骤；所述源极与漏极分别通过第一通孔及第二通孔与有源层的两端连接；
所述步骤4还包括一在平坦化层上对应漏极的位置形成第三通孔的步骤，所述顶层电极通过第三通孔与漏极连接。
本发明还提供一种TFT基板的制作方法，包括以下步骤：
步骤1、提供一衬底基板，在所述衬底基板上形成半导体材料层，并在所述半导体材料层上形成光刻胶层，采用一道光罩对所述光刻胶层进行曝光、显影，得到光刻胶图案，沿栅极的长度方向，所述光刻胶图案至少包括位于中间的第一光刻胶段、及位于两侧的第二光刻胶段，且所述第一光刻胶段的厚度大于所述第二光刻胶段的厚度；
步骤2、采用对所述光刻胶图案与半导体材料层均能进行蚀刻的气体对所述光刻胶图案与半导体材料层进行至少两步蚀刻：
第一步蚀刻是将所述半导体材料层上位于所述第二光刻胶段外侧的部分变薄，同时将所述光刻胶图案的第一光刻胶段变薄，将所述光刻胶图案的第二光刻胶段完全蚀刻掉；
第二步蚀刻是将所述光刻胶图案的第一光刻胶段完全蚀刻掉，将所述半导体材料层上位于所述第二光刻胶段外侧的部分完全蚀刻掉，同时将所述半导体材料层上对应于第二光刻胶段的部分变薄，得到有源层，所述有源层至少包括位于中间且对应于第一光刻胶段的第一区域、及位于所述第一区域两侧且对应于第二光刻胶段的第二区域，所述第一区域的厚度大于第二区域的厚度，使得所述有源层的两侧均具有至少一个台阶；
步骤3、在所述有源层上形成栅极绝缘层，在所述栅极绝缘层上对应有源层的位置形成栅极，在所述栅极及栅极绝缘层上形成层间介电层，在所述层间介电层上形成源极及漏极，完成TFT的制作；
其中，所述步骤2制得的有源层的两侧均具有一个台阶；
其中，所述步骤1还包括在所述衬底基板与半导体材料层之间形成遮光层与缓冲层的步骤；
还包括：步骤4、在所述TFT上形成平坦化层，在所述平坦化层上上形成底层电极，在所述底层电极上形成钝化层，在所述钝化层上形成顶层电极。
本发明的有益效果：本发明提供的TFT基板，包括：衬底基板、及设置在所述衬底基板上的TFT，该TFT基板通过对TFT中的有源层的结构进行改进，使得有源层的两侧均具有至少一个台阶，相比于现有技术中侧面为单个台阶的有源层，能够有效减弱有源层侧面台阶的尖端电场集中效应，使有源层中载流子的浓度均匀，使TFT的输出电性稳定，TFT的质量高，TFT阵列基板的工作稳定性强。本发明提供的TFT阵列基板的制作方法，能够有效减弱TFT中有源层侧面台阶的尖端电场集中效应，使有源层中的载流子浓度均匀，使TFT的输出电性稳定，提升TFT的质量，进而增强TFT阵列基板的工作稳定性。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的TFT基板的结构示意图；
图2为图1的TFT基板中的TFT的俯视示意图；
图3为图1的TFT基板中的TFT沿图2中的A’-A’线的剖视示意图；
图4为本发明的TFT基板的结构示意图；
图5为图4的TFT基板中的TFT的俯视示意图；
图6为图4的TFT基板中的TFT沿图5中的A-A线的剖视示意图；
图7为本发明的TFT基板的制作方法的流程图；
图8-9为本发明的TFT基板的制作方法的步骤1的示意图；
图10-11为本发明的TFT基板的制作方法的步骤2的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图4至图6，本发明提供一种TFT基板，包括：衬底基板100、及设置在所述衬底基板100上的TFT400；
所述TFT400包括：有源层410、设置在所述有源层410上的栅极绝缘层420、设置在所述栅极绝缘层420上且水平位置与有源层410对应的栅极430、设置在所述栅极430及栅极绝缘层420上的层间介电层440、及设置在所述层间介电层440上的源极450及漏极460；
如图5至图6所示，沿所述栅极430的长度方向，所述有源层410至少包括位于中间的第一区域411、及位于所述第一区域411两侧的第二区域412，所述第一区域411的厚度大于第二区域412的厚度，使得所述有源层410的两侧均具有至少一个台阶。
优选的，所述第二区域412的宽度为所述第一区域411的宽度的二十分之一至十分之一。
优选的，所述有源层410的两侧均具有一个台阶。
具体的，所述TFT基板还包括：设置在所述衬底基板100与TFT400之间的遮光层200与缓冲层300、设置在所述TFT400上的平坦化层500、设置在所述平坦化层上500上的底层电极600、设置在所述底层电极600上的钝化层700、及设置在所述钝化层700上的顶层电极800。
具体的，所述有源层410与遮光层200相对应，且所述遮光层200在水平方向上完全覆盖所述有源层410，从而能够对有源层410进行遮光，防止光电效应使TFT产生漏电流影响显示效果。
具体的，所述栅极绝缘层420和层间介电层440上对应有源层410两端的位置设有第一通孔910及第二通孔920，所述源极450与漏极460分别通过第一通孔910及第二通孔920与有源层410的两端连接；
所述平坦化层500上对应漏极460的位置设有第三通孔930，所述顶层电极800通过第三通孔930与漏极460连接。
优选的，所述衬底基板100为玻璃基板。
具体的，所述底层电极600和顶层电极800分别为公共电极与像素电极，所述底层电极600与顶层电极800的材料均为透明导电材料，所述透明导电材料优选为氧化铟锡(Indium Tin Oxides，ITO)。
具体的，所述有源层410的材料为多晶硅(Poly-Si)。
上述TFT基板通过对TFT400中的有源层410的结构进行改进，使得有源层400的两侧均具有至少一个台阶，相比于现有技术中的有源层，有源层410两侧的电场集中效应减弱，使有源层410内部的载流子浓度均匀，防止有源层410的侧面与其上部的栅极430形成侧面寄生TFT，有效地控制TFT400的输出电性，提升TFT400的质量，进而使TFT基板的工作的稳定性增强。
请参阅图7，基于上述TFT基板，本发明还提供一种TFT基板的制作方法，包括以下步骤：
步骤1、如图8-9所示，提供一衬底基板100，在所述衬底基板100上形成半导体材料层10，并在所述半导体材料层10上形成光刻胶层11，采用一道光罩15对所述光刻胶层11进行曝光、显影，得到光刻胶图案20，沿栅极的长度方向，所述光刻胶图案20至少包括位于中间的第一光刻胶段21、及位于两侧的第二光刻胶段22，且所述第一光刻胶段21的厚度大于所述第二光刻胶段22的厚度。
具体的，如图8所示，所述步骤1还包括在所述衬底基板100与半导体材料层10之间形成遮光层200与缓冲层300的步骤。
步骤2、如图10-11所示，采用对所述光刻胶图案20及半导体材料层10均能进行蚀刻的气体对所述光刻胶图案20与半导体材料层10进行至少两步蚀刻：
如图10所示，第一步蚀刻是将所述半导体材料层10上位于所述第二光刻胶段22外侧的部分变薄，同时将所述光刻胶图案20的第一光刻胶段21变薄，将所述光刻胶图案20的第二光刻胶段22完全蚀刻掉；
如图11所示，第二步蚀刻是将所述光刻胶图案20的第一光刻胶段21完全蚀刻掉，将所述半导体材料层10上位于所述第二光刻胶段22外侧的部分完全蚀刻掉，同时将所述半导体材料层10上对应于第二光刻胶段22的部分变薄，得到有源层410，所述有源层410至少包括位于中间且对应于第一光刻胶段21的第一区域411、及位于所述第一区域411两侧且对应于第二光刻胶段22的第二区域412，所述第一区域411的厚度大于第二区域412的厚度，使得所述有源层410的两侧均具有至少一个台阶。
优选的，所述步骤2制得的有源层410的两侧均具有一个台阶。
具体的，所述步骤2中，所述光罩15为灰阶光罩(Gray Tone Mask，GTM)、半色调光罩(Half Tone Mask，HTM)、或单缝光罩(Single Slit Mask，SSM)。
具体的，所述步骤2采用的蚀刻气体由多种气体组分组成，通过调节各气体组分的比例，可使得所述蚀刻气体对半导体材料层10的刻蚀速率与所述蚀刻气体对光刻胶图案20的刻蚀速率之间保持一定的比例。
具体的，所述第一步蚀刻与第二步蚀刻均为干蚀刻。
具体的，所述步骤2制得的有源层410与遮光层200相对应，且所述遮光层200在水平方向上完全覆盖所述有源层410，从而能够对有源层410进行遮光，防止光电效应使TFT产生漏电流影响显示效果。
步骤3、如图4所示，在所述有源层410上形成栅极绝缘层420，在所述栅极绝缘层420上对应有源层410的位置形成栅极430，在所述栅极430及栅极绝缘层420上形成层间介电层440，在所述层间介电层440上形成源极450及漏极460，完成TFT400的制作。
具体的，如图4所示，所述TFT基板的制作方法还包括：步骤4、在所述TFT400上形成平坦化层500，在所述平坦化层上500上形成底层电极600，在所述底层电极600上形成钝化层700，在所述钝化层700上形成顶层电极800。
具体的，如图4所示，所述步骤3还包括在所述栅极绝缘层420和层间介电层440上对应有源层410两端的位置形成第一通孔910及第二通孔920的步骤；所述源极450与漏极460分别通过第一通孔910及第二通孔920与有源层410的两端连接；
所述步骤4还包括一在平坦化层500上对应漏极460的位置形成第三通孔930的步骤，所述顶层电极800通过第三通孔930与漏极460连接。
优选的，所述衬底基板100为玻璃基板。
具体的，所述底层电极600和顶层电极800分别为公共电极与像素电极，所述底层电极600与顶层电极800的材料均为透明导电材料，所述透明导电材料优选为氧化铟锡(Indium Tin Oxides，ITO)。
具体的，所述有源层410的材料为多晶硅(Poly-Si)。
上述TFT基板的制作方法，通过对TFT400中的有源层410的结构进行改进，使得有源层410的两侧均具有至少一个台阶，相比于现有技术中的有源层，有源层410两侧的电场集中效应减弱，使有源层410内部的载流子浓度均匀，防止有源层410的侧面与其上部的栅极430形成侧面寄生 TFT，有效地控制TFT400的输出电性，提升TFT400的质量，进而使TFT基板的工作的稳定性增强。
综上所述，本发明的TFT基板，包括：衬底基板、及设置在所述衬底基板上的TFT，该TFT基板通过对TFT中的有源层的结构进行改进，使得有源层的两侧均具有至少一个台阶，相比于现有技术中的有源层，能够有效减弱有源层两侧的尖端电场集中效应，使有源层中载流子的浓度均匀，使TFT的输出电性稳定，TFT的质量高，TFT基板的工作稳定性强。本发明的TFT基板的制作方法，能够有效减弱TFT中有源层侧面的尖端电场集中效应，使有源层中的载流子浓度均匀，使TFT的输出电性稳定，提升TFT的质量，进而增强TFT基板的工作稳定性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (13)

  1. 一种TFT基板，包括：衬底基板、及设置在所述衬底基板上的TFT；
    所述TFT包括：有源层、设置在所述有源层上的栅极绝缘层、设置在所述栅极绝缘层上且水平位置与有源层对应的栅极、设置在所述栅极及栅极绝缘层上的层间介电层、及设置在所述层间介电层上的源极及漏极；
    沿所述栅极的长度方向，所述有源层至少包括位于中间的第一区域、及位于所述第一区域两侧的第二区域，且所述第一区域的厚度大于第二区域的厚度，使得所述有源层的两侧均具有至少一个台阶。
  2. 如权利要求1所述的TFT基板，其中，所述有源层的两侧均具有一个台阶。
  3. 如权利要求1所述的TFT基板，还包括：设置在所述衬底基板与TFT之间的遮光层与缓冲层、设置在所述TFT上的平坦化层、设置在所述平坦化层上上的底层电极、设置在所述底层电极上的钝化层、及设置在所述钝化层上的顶层电极。
  4. 如权利要求3所述的TFT基板，其中，所述有源层与遮光层相对应，且所述遮光层在水平方向上完全覆盖所述有源层。
  5. 如权利要求3所述的TFT基板，其中，所述栅极绝缘层和层间介电层上对应有源层两端的位置设有第一通孔及第二通孔，所述源极与漏极分别通过第一通孔及第二通孔与有源层的两端连接；
    所述平坦化层上对应漏极的位置设有第三通孔，所述顶层电极通过第三通孔与漏极连接。
  6. 一种TFT基板的制作方法，包括以下步骤：
    步骤1、提供一衬底基板，在所述衬底基板上形成半导体材料层，并在所述半导体材料层上形成光刻胶层，采用一道光罩对所述光刻胶层进行曝光、显影，得到光刻胶图案，沿栅极的长度方向，所述光刻胶图案至少包括位于中间的第一光刻胶段、及位于两侧的第二光刻胶段，且所述第一光刻胶段的厚度大于所述第二光刻胶段的厚度；
    步骤2、采用对所述光刻胶图案与半导体材料层均能进行蚀刻的气体对所述光刻胶图案与半导体材料层进行至少两步蚀刻：
    第一步蚀刻是将所述半导体材料层上位于所述第二光刻胶段外侧的部分变薄，同时将所述光刻胶图案的第一光刻胶段变薄，将所述光刻胶图案的第二光刻胶段完全蚀刻掉；
    第二步蚀刻是将所述光刻胶图案的第一光刻胶段完全蚀刻掉，将所述半导体材料层上位于所述第二光刻胶段外侧的部分完全蚀刻掉，同时将所述半导体材料层上对应于第二光刻胶段的部分变薄，得到有源层，所述有源层至少包括位于中间且对应于第一光刻胶段的第一区域、及位于所述第一区域两侧且对应于第二光刻胶段的第二区域，所述第一区域的厚度大于第二区域的厚度，使得所述有源层的两侧均具有至少一个台阶；
    步骤3、在所述有源层上形成栅极绝缘层，在所述栅极绝缘层上对应有源层的位置形成栅极，在所述栅极及栅极绝缘层上形成层间介电层，在所述层间介电层上形成源极及漏极，完成TFT的制作。
  7. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤2制得的有源层的两侧均具有一个台阶。
  8. 如权利要求6所述的TFT基板的制作方法，其中，所述步骤1还包括在所述衬底基板与半导体材料层之间形成遮光层与缓冲层的步骤；
    还包括：步骤4、在所述TFT上形成平坦化层，在所述平坦化层上上形成底层电极，在所述底层电极上形成钝化层，在所述钝化层上形成顶层电极。
  9. 如权利要求8所述的TFT基板的制作方法，其中，所述步骤2制得的有源层与遮光层相对应，且所述遮光层在水平方向上完全覆盖所述有源层。
  10. 如权利要求8所述的TFT基板的制作方法，其中，所述步骤3还包括在所述栅极绝缘层和层间介电层上对应有源层两端的位置形成第一通孔及第二通孔的步骤；所述源极与漏极分别通过第一通孔及第二通孔与有源层的两端连接；
    所述步骤4还包括一在平坦化层上对应漏极的位置形成第三通孔的步骤，所述顶层电极通过第三通孔与漏极连接。
  11. 一种TFT基板的制作方法，包括以下步骤：
    步骤1、提供一衬底基板，在所述衬底基板上形成半导体材料层，并在所述半导体材料层上形成光刻胶层，采用一道光罩对所述光刻胶层进行曝光、显影，得到光刻胶图案，沿栅极的长度方向，所述光刻胶图案至少包括位于中间的第一光刻胶段、及位于两侧的第二光刻胶段，且所述第一光刻胶段的厚度大于所述第二光刻胶段的厚度；
    步骤2、采用对所述光刻胶图案与半导体材料层均能进行蚀刻的气体对所述光刻胶图案与半导体材料层进行至少两步蚀刻：
    第一步蚀刻是将所述半导体材料层上位于所述第二光刻胶段外侧的部 分变薄，同时将所述光刻胶图案的第一光刻胶段变薄，将所述光刻胶图案的第二光刻胶段完全蚀刻掉；
    第二步蚀刻是将所述光刻胶图案的第一光刻胶段完全蚀刻掉，将所述半导体材料层上位于所述第二光刻胶段外侧的部分完全蚀刻掉，同时将所述半导体材料层上对应于第二光刻胶段的部分变薄，得到有源层，所述有源层至少包括位于中间且对应于第一光刻胶段的第一区域、及位于所述第一区域两侧且对应于第二光刻胶段的第二区域，所述第一区域的厚度大于第二区域的厚度，使得所述有源层的两侧均具有至少一个台阶；
    步骤3、在所述有源层上形成栅极绝缘层，在所述栅极绝缘层上对应有源层的位置形成栅极，在所述栅极及栅极绝缘层上形成层间介电层，在所述层间介电层上形成源极及漏极，完成TFT的制作；
    其中，所述步骤2制得的有源层的两侧均具有一个台阶；
    其中，所述步骤1还包括在所述衬底基板与半导体材料层之间形成遮光层与缓冲层的步骤；
    还包括：步骤4、在所述TFT上形成平坦化层，在所述平坦化层上上形成底层电极，在所述底层电极上形成钝化层，在所述钝化层上形成顶层电极。
  12. 如权利要求11所述的TFT基板的制作方法，其中，所述步骤2制得的有源层与遮光层相对应，且所述遮光层在水平方向上完全覆盖所述有源层。
  13. 如权利要求11所述的TFT基板的制作方法，其中，所述步骤3还包括在所述栅极绝缘层和层间介电层上对应有源层两端的位置形成第一通孔及第二通孔的步骤；所述源极与漏极分别通过第一通孔及第二通孔与有源层的两端连接；
    所述步骤4还包括一在平坦化层上对应漏极的位置形成第三通孔的步骤，所述顶层电极通过第三通孔与漏极连接。
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