WO2014190713A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2014190713A1
WO2014190713A1 PCT/CN2013/088829 CN2013088829W WO2014190713A1 WO 2014190713 A1 WO2014190713 A1 WO 2014190713A1 CN 2013088829 W CN2013088829 W CN 2013088829W WO 2014190713 A1 WO2014190713 A1 WO 2014190713A1
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Prior art keywords
layer
common electrode
gate metal
metal layer
gate
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PCT/CN2013/088829
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English (en)
French (fr)
Inventor
崔贤植
李会
徐智强
严允晟
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京东方科技集团股份有限公司
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Priority to US14/374,987 priority Critical patent/US9484465B2/en
Publication of WO2014190713A1 publication Critical patent/WO2014190713A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned

Definitions

  • Embodiments of the present invention relate to the field of display, and in particular, to an array substrate, a method of manufacturing the same, and a display device. Background technique
  • liquid crystal displays Due to its light weight, low power consumption, low radiation, and large space saving, liquid crystal displays have replaced traditional cathode ray tube displays and are widely used in various display fields such as homes, public places, office places and personal electronics. Products, etc.
  • the conventional liquid crystal display includes display pixels (cells) and thin film transistors (TFTs) for controlling display data loading.
  • the thin film transistor generally adopts a bottom gate structure (the gate of the thin film transistor is located below the semiconductor layer), and includes: a substrate 1, a gate metal layer 2, a gate insulating layer 3, and a semiconductor layer which are sequentially disposed on the substrate 1 from bottom to top.
  • display pixels include: common electrode 6, passivation layer 8, pixel electrode 7 disposed on passivation layer 8 and liquid crystal (located above pixel electrode 7, not shown), pixel The electrode 7 is connected to the drain of the thin film transistor, the common electrode 6 is connected to the common electrode line 9, the pixel electrode 7 loads the display data through the TFT, and a driving electric field is generated between the common electrode 6 and the pixel electrode 7, and the liquid crystal molecules act on the driving electric field. A deflection occurs to display an image.
  • the gate metal layer 2 can block the light emitted from the backlight on the array substrate side, and the external light (the external light entering from the side of the color filter substrate) is blocked by the black matrix BM, but the inventors have found that: When the alignment of the color filter substrate and the array substrate occurs, or when the process of the array substrate is defective, the semiconductor layer is likely to be exposed. At this time, the leakage current of the TFT is abnormally increased due to the irradiation of external light, and as a result, the liquid crystal display is greenish ( Greenish) and horizontal grayscale unevenness (X-talk) are not well displayed.
  • liquid crystal displays especially high-resolution products, need to reduce the resistance of the common electrode. Otherwise, the delay of the common electrode resistance is too large, and the greenish and green-scale (X-talk) of the liquid crystal display are prone to occur. The display is poor, affecting the picture quality, but if the resistance of the common electrode is lowered by increasing the line width of the common electrode, the aperture ratio is reduced.
  • Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display device, which can prevent greenish display and horizontal grayscale unevenness (X-talk) from being displayed on the liquid crystal display without lowering the transmittance.
  • X-talk horizontal grayscale unevenness
  • an array substrate including: a substrate and a first gate metal layer, a first gate insulating layer, a semiconductor layer, and a source/drain electrode layer disposed on the substrate in this order from bottom to top;
  • the array substrate further includes:
  • a second gate metal layer is disposed on the second gate insulating layer.
  • the array substrate further includes:
  • the first common electrode line is located in the same layer as the first gate metal layer or in the same layer as the second gate metal layer.
  • the array substrate further includes: a second common electrode line,
  • the second common electrode line and the second gate metal layer are in the same layer; when the first common electrode line and the When the second gate metal layer is in the same layer, the second common electrode line is in the same layer as the first gate metal layer.
  • the second common electrode line is connected in parallel with the first common electrode line, and the second common electrode line is the same as the line width of the first common electrode line.
  • the array substrate further includes:
  • a first electrode for generating an electric field to drive the liquid crystal
  • a second electrode for generating an electric field to drive the liquid crystal
  • a passivation layer disposed between the first electrode and the second electrode, the first electrode being disposed on the resin layer
  • the second electrode is disposed over the passivation layer.
  • the first electrode is connected to the first common electrode line through a via hole in the resin layer.
  • the second electrode is connected to the drain of the source/drain electrode layer through a drain via in the passivation layer, the resin layer, and the second gate insulating layer.
  • the second gate metal layer is located directly above the first gate metal layer.
  • a display device comprising the above array substrate.
  • a method of fabricating an array substrate comprising: forming a first gate metal layer on a substrate;
  • a semiconductor layer, a source/drain electrode layer, a second gate insulating layer, and a second gate metal layer are sequentially formed from bottom to top.
  • the above method further includes:
  • a second transparent conductive film layer is formed, and a second electrode is formed by a patterning process.
  • the above method further includes forming a first common electrode line while forming the second gate metal layer.
  • the above method further includes forming a second common electrode line while forming the first gate metal layer.
  • the second common electrode line is connected in parallel with the first common electrode line, and the second common electrode line is the same as the line width of the first common electrode line.
  • the first gate metal layer and the second gate metal layer are formed by a patterning process using the same mask.
  • 1 is a schematic structural view of a conventional array substrate
  • FIG. 2 is a schematic structural diagram of an array substrate according to Embodiment 1 of the present invention.
  • FIG. 3 is a schematic structural diagram of an array substrate according to Embodiment 2 of the present invention.
  • FIG. 4 is a flowchart of a method for manufacturing an array substrate according to Embodiment 4 of the present invention
  • 5a to 5g are schematic cross-sectional views of a substrate in a process of manufacturing an array substrate according to Embodiment 4 of the present invention
  • Figure 6 is a flow chart of step 103 in Figure 4.
  • FIG. 7a through 7d are schematic cross-sectional views of the substrate during the manufacturing process of step 103 of Fig. 4.
  • the embodiment of the invention provides an array substrate, a manufacturing method thereof, and a display device, which can improve display defects such as greenish and horizontal X-talk of the liquid crystal display without lowering the transmittance, and improve the display device. Picture quality.
  • the array substrate includes: a substrate 10 and a first gate metal layer 111, a first gate insulating layer 121, and a first gate insulating layer 121, which are sequentially disposed on the substrate from bottom to top.
  • the semiconductor layer 13, the source and drain electrode layer 14, further includes:
  • a second gate metal layer 112 is disposed on the second gate insulating layer 122.
  • the first gate metal layer 111 and the second gate metal layer 112 may be made of the same material, for example, one or more selected from the group consisting of molybdenum, aluminum, chromium, and copper.
  • the first gate insulating layer 121 and the second gate insulating layer 122 may also be made of the same material, for example, may be silicon nitride films, and of course, different materials may be used.
  • the first gate metal layer 111 and the second gate metal layer 112 described in this embodiment each include a gate and a gate line pattern.
  • the first gate metal layer 111 and the second gate metal layer 112 have the same pattern, and can be photolithographically formed by using the same mask. Therefore, the first gate metal layer 111 and the second gate metal layer 112 each include a gate and a gate line connected to the gate.
  • the designer can select one of the following two options as needed.
  • the first solution is that the thin film transistor adopts a top gate structure, and a gate scan signal is applied to the top gate and the gate line formed by the second gate metal layer 112.
  • the first gate metal layer 111 only functions to block the backlight;
  • a bottom gate structure may be employed, and a gate scan signal is applied to the bottom gate and the gate line formed by the first gate metal layer 111, and the second gate metal layer 112 functions only to block external light.
  • the second solution is to form a dual-channel thin film transistor, that is, the thin film transistor adopts a double gate structure, and the gate scan signal is simultaneously loaded to: the gate line formed by the second gate metal layer 112 and the top gate and the first gate metal layer 111 are formed.
  • the material of the second gate insulating layer 122 and the first gate insulating layer 121 are both SiNx, which are interfaces of carrier movement.
  • a dual-channel thin film transistor can increase the turn
  • the second gate metal layer 112 and the first gate metal layer 111 are respectively disposed above and below the semiconductor layer 13, and the second gate metal layer 112 located above the semiconductor layer 13 blocks the incident from above.
  • External light (light entering from the side of the color filter substrate); the first gate metal layer 111 located under the semiconductor layer 13 blocks light emitted from the lower side (backlight on the array substrate side), thereby preventing the semiconductor layer 13 from being irradiated with light
  • the abnormal increase in the TFT leakage current due to the light irradiation is prevented, and the positions of the second gate metal layer 112 and the first gate metal layer 111 overlap each other, so that the transmittance does not decrease.
  • the process of the array substrate usually has a deviation of 3 ⁇ 4 ⁇ m, and the overlay layer has an overlay error of less than 1 ⁇ m, so that the horizontal X-talk characteristic can be improved.
  • the array substrate of the present embodiment can improve the display defects such as greenish and horizontal X-talk of the liquid crystal display without lowering the transmittance, thereby improving the picture quality of the display device.
  • the array substrate may further include: a first common electrode line 192 located in the same layer as the second gate metal layer 112 (as shown in FIG. 2) or in the same layer as the first gate metal layer 111.
  • the array substrate may further include: a resin layer 15 covering the second gate metal layer 112; a first electrode (for example, the common electrode 17 in the drawing) for generating an electric field to drive the liquid crystal, a second electrode (for example, the pixel electrode 20 in the drawing), and a passivation layer disposed between the first electrode and the second electrode 18.
  • the first electrode (common electrode 17) is disposed over the resin layer 15, and the second electrode (pixel electrode 20) is disposed over the passivation layer 18.
  • the first electrode and the second electrode in this embodiment may also refer to a pixel electrode and a common electrode, respectively.
  • the other (first electrode) is a common electrode.
  • the upper electrode is a slit electrode
  • the lower electrode may be a plate electrode or a slit electrode.
  • a second electrode (which may be a first electrode) as a pixel electrode is connected to the drain of the thin film transistor, and a first electrode (corresponding to a second electrode) as a common electrode is connected to the common electrode line. For example, as shown in FIG.
  • the lower common electrode 17 is a plate electrode, and is connected to the first common electrode line 192 through a via hole in the resin layer 15; the upper pixel electrode 20 is a slit electrode, which is passivated.
  • the via holes in the layer 18, the resin layer 15 and the second gate insulating layer 122 are connected to the drain of the thin film transistor, and the thin film transistor may include: a first gate metal layer 111, a first gate insulating layer 121, and a source/drain electrode.
  • the display data is loaded to the pixel electrode 20 and the common electrode 17 via the thin film transistor, and the pixel electrode 20 and the common electrode 17 generate a driving electric field, and the liquid crystal molecules are deflected by the driving electric field to display an image.
  • the array substrate of the present embodiment can improve display defects such as greenish and horizontal X-talk of the liquid crystal display without lowering the transmittance, and improve the picture quality of the display device.
  • the embodiment of the present invention provides an array substrate, which is different from the first embodiment shown in FIG. 2 in that the array substrate further includes: a second common electrode line.
  • the second common electrode line and the second gate metal layer are in the same layer; when the first common electrode line When the second gate metal layer is in the same layer, the second common electrode line and the first gate metal layer are in the same layer;
  • the second common electrode line is connected to the first common electrode line through a via hole in the first gate insulating layer and the second gate insulating layer.
  • the array substrate includes: a substrate 10, which is firstly disposed on the substrate 10 from bottom to top. Gate metal layer 111, first gate insulating layer 121, semiconductor layer 13, source/drain electrode layer 14, second gate insulating The layer 122 and the second gate metal layer 112; in addition, the array substrate further includes:
  • the first common electrode line 192 is located on the same layer as the second gate metal layer 112;
  • the second common electrode line 191 is located in the same layer as the first gate metal layer 111;
  • the second common electrode line 191 is connected to the first common electrode line 192 through a via hole in the first gate insulating layer 121 and the second gate insulating layer 122.
  • the first common electrode line 192 and the second gate metal layer 112 are located in the same layer, and may be formed by simultaneously coating, exposing, etching, developing, and the like of the same metal film layer.
  • the second common electrode line 191 and the first gate metal layer 111 are also in the same layer, and can also be made synchronously by the same metal film layer.
  • the common electrode resistance When the common electrode resistance is too large, delay occurs to affect the picture quality, and display failures such as greenish and horizontal X-talk of the liquid crystal display device are likely to occur, which affects the picture quality.
  • the common electrode resistance By increasing the width of the common electrode or forming a common electrode using a low-resistance material, the common electrode resistance can be lowered, but increasing the width of the common electrode generally affects the pixel aperture ratio; while using a low-resistance material, the resistance reduction of the common electrode is limited, and It may also be necessary to change the preparation process and therefore lack practicality.
  • the second common electrode line 191 is further formed under the thin film transistor, and the line width of the second common electrode line 191 is less than or equal to the line width of the first common electrode line 192.
  • the second common electrode line 191 is connected in parallel with the first common electrode line 192, and the position of the second common electrode line 191 overlaps with the first common electrode line 192 to block each other, so that the line width can be prevented without affecting the pixel opening.
  • the resistance of the common electrode is reduced under the premise of the rate, and the delay due to excessive resistance of the common electrode is avoided, which is particularly important for display devices, especially high resolution products.
  • the second common electrode line 191 is connected in parallel with the first common electrode line 192, and the second common electrode line 191 has the same line width as the first common electrode line 192.
  • the array substrate may further include: the data line 16 is located in the same layer as the source/drain electrode layer 14 of the thin film transistor.
  • the array substrate may further include:
  • a pixel electrode 20 for generating an electric field to drive the liquid crystal, a common electrode 17, and a passivation layer 18 disposed between the pixel electrode 20 and the common electrode 17, the common electrode 17 being disposed over the resin layer 15, and the pixel electrode 20 being disposed at Above the passivation layer 18.
  • the common electrode 17 is passed through the via hole in the resin layer 15 to the first common electrode line 192.
  • the pixel electrode 20 is connected to the source/drain metal layer 14 (the drain of the thin film transistor) through a via hole in the passivation layer 18, the resin layer 15, and the second gate insulating layer 122 thereunder.
  • the upper pixel electrode 20 has a slit shape, and the lower common electrode 17 may have a plate shape or a slit shape.
  • the pixel electrode is connected to the drain
  • the common electrode is connected to the common electrode line
  • the positions of the common electrode and the pixel electrode are interchangeable, but the upper electrode needs to be a slit.
  • the lower electrode may be plate-shaped or slit-shaped.
  • the abnormal leakage current of the TFT caused by the light irradiation of the semiconductor layer can be avoided; and the first and second common electrode lines are simultaneously adopted.
  • the overlapping double-line structure can reduce the resistance of the common electrode without affecting the pixel aperture ratio, and avoid delay due to excessive resistance of the common electrode. Therefore, the array substrate of the embodiment can improve the greenish appearance of the liquid crystal display without reducing the transmittance.
  • the embodiment of the invention further provides a display device comprising any of the array substrates described in Embodiments 1 and 2.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any display product or component.
  • the display device according to the present embodiment is applied to the array substrate according to the present invention, it is possible to improve display defects such as greenish and horizontal X-talk in the display device without lowering the transmittance. , the display effect is improved.
  • the embodiment of the invention further provides a method for manufacturing an array substrate. As shown in FIG. 4 and FIG. 5, the method includes:
  • the array substrate in this embodiment may also include a first common electrode line 192 and a second common electrode line 191, and the second common electrode line 191 may be in the same layer as the first gate metal layer 111.
  • a gate metal film layer is formed on the substrate 10, and the film is usually formed by various methods such as deposition, coating, sputtering, etc., and then coated by photoresist coating, exposure, development, and etching, etc., on the substrate.
  • a pattern of the first gate metal layer 111 (including a pattern of gate and gate lines) and a pattern of the second common electrode line 191 are formed on 10. 102, forming a first gate insulating layer 121 on the substrate on which the step 101 is completed (FIG. 5b);
  • the first gate insulating layer 121 has the same pattern as the gate insulating layer 12 shown in FIG. 1. Therefore, in this step, a mask used in forming the gate insulating layer 3 in the prior art can be used, thereby forming the first gate insulating layer 121. At the same time, a via hole is formed to expose the second common electrode line 191. Of course, it is also possible to form a first gate insulating layer by forming a via hole without using a mask.
  • the material of the first and second gate insulating layers in this embodiment is, for example, an insulating material such as SiNx.
  • the source/drain electrode layer 14 includes a source electrode , drain electrode, data line pattern ( Figure 5c);
  • the mask used in forming the first gate metal layer 111 of the thin film transistor in the step 103 may be used in forming the second gate metal layer 112 so that the widths of the two gate metal layers are the same.
  • the drain vias exposing the drains of the thin film transistors may be formed in the second gate insulating layer 122 using the mask simultaneously.
  • the array substrate further includes a first common electrode line 192 located in the same layer as the second gate metal layer 112, and the first common electrode line 192 passes through the second gate insulating layer 122 and the first The via hole in the gate insulating layer 121 is connected to the second common electrode line 191. Then, in this step, the first common electrode line 192 is formed in synchronization with the second gate metal layer 112, and further, it is required to be formed at this time. : a connection via of the second common electrode line 191 and the first common electrode line 192.
  • the semiconductor layer 13, the source/drain electrode layer 14, the second gate insulating layer 122, and the second gate metal layer 112 are made of a conventional material, and the preparation process includes, for example, a second mask process to form a semiconductor layer, and a third
  • the sub-mask process forms the source/drain electrode layer 14
  • the fourth mask process forms the connection vias and drain vias of 191 and 192 in the second gate insulating layer 122
  • the fifth mask process forms the second gate metal.
  • two via holes are provided on the second gate insulating layer 122, so that the mask used in forming the resin layer 15 in step 104 can be used.
  • Forming a via pattern of the resin layer and the resin layer on the substrate on which the step 103 is completed (FIG. 5d); forming a via pattern of the resin layer 15 means forming a via of the common electrode 17 and the first common electrode line 192 . Further, the drain electrode and the drain of the thin film transistor may be formed together at the time of forming the connection via of the resin layer.
  • 105. Form a first transparent conductive film layer on the substrate on which the step 104 is completed, and form a first electrode by a patterning process (FIG. 5e). In FIG. 5e, the first electrode is a common electrode 17, and the common electrode 17 is connected to the first common electrode line 192 through a via hole in the resin layer 15 above the first common electrode line 192.
  • a drain via may be formed on the passivation layer 18, penetrating the passivation layer 18, the resin layer 15, and the second gate insulating layer 122.
  • the drain electrode is exposed; the second solution may also form a drain via in a stepwise manner, that is, a via hole penetrating the passivation layer 18 is formed on the basis of the resin layer 15 on which the drain via has been formed.
  • the second electrode is the pixel electrode 20 and the pixel electrode 20 is connected to the drain of the thin film transistor through a drain via penetrating through the passivation layer 18, the resin layer 15, and the second gate insulating layer 122.
  • the first and second gate metal layers formed by the steps 101 to 103 can be used as a shielding layer of the thin film transistor semiconductor layer, thereby avoiding an abnormal increase in leakage current of the TFT due to light irradiation of the semiconductor layer.
  • the array substrate of the present embodiment can improve the display defects such as greenish and horizontal X-talk of the liquid crystal display without lowering the transmittance, and improve the picture quality of the display device.
  • the formed array substrate is further provided with a stacked first common electrode line and a second common electrode line, which can reduce the resistance of the common electrode without affecting the pixel aperture ratio, and avoid delay due to excessive resistance of the common electrode. .
  • the array substrate manufacturing method provided in this embodiment does not need to add a new mask, so that it is not necessary to make major changes to the existing manufacturing methods and equipment.
  • the second electrode (pixel electrode 20 in the drawing) may have a slit shape.
  • step 103 is as shown in FIG. 6, and may include:
  • a common electrode line 192 (FIG. 7d), wherein the first common electrode line 192 is located at a corresponding position above the second common electrode line 191.
  • the method for manufacturing the array substrate provided in this embodiment does not need to add a new mask, and the formed array substrate can improve the greenish and horizontal X-talk of the liquid crystal display without lowering the transmittance. Poor display, improve the picture quality of the display device.

Abstract

一种阵列基板，包括：基板（10），自下而上依次设置于基板（10）上的第一栅金属层（111）、第一栅绝缘层（121）、半导体层（13）、源漏电极层（14），阵列基板（10）还包括：设置在源漏电极层（14）上的第二栅绝缘层（122）；以及，设置在第二栅绝缘层（122）上的第二栅金属层（112）。还披露了一种阵列基板的制造方法。

Description

阵列基板及其制造方法、 显示装置 技术领域
本发明实施例涉及显示领域， 尤其涉及一种阵列基板及其制造方法、 显 示装置。 背景技术
液晶显示器因其质量轻、 功耗低， 辐射小、 能大量节省空间等优点， 现 已取代传统的阴极射线管显示器， 广泛应用于各个显示领域， 如家庭、 公共 场所、 办公场所及个人电子相关产品等。
如图 1所示， 现有液晶显示器包括显示像素 （单元）和用于控制显示数 据加载的薄膜晶体管（TFT )。 其中， 薄膜晶体管通常采用底栅结构（薄膜晶 体管的栅极位于半导体层的下方）， 包括： 基板 1、 自下而上依次设置在基板 1上的栅金属层 2、栅绝缘层 3、半导体层 4和源漏电极层 5; 显示像素包括： 公共电极 6、钝化层 8、设置在钝化层 8上的像素电极 7和液晶（位于像素电 极 7的上方， 图中未示出），像素电极 7连接至薄膜晶体管的漏极，公共电极 6连接至公共电极线 9, 像素电极 7通过 TFT加载显示数据， 在公共电极 6 与像素电极 7之间产生驱动电场， 液晶分子在该驱动电场作用下发生偏转从 而显示出图像。
采用底栅结构 TFT, 栅金属层 2可以遮挡从阵列基板侧的背光源发出的 光， 而外部光（从彩膜基板一侧进入的外部光）则由黑矩阵 BM遮挡， 但发 明人发现： 当彩膜基板与阵列基板出现对位偏差时， 或者阵列基板的工艺出 现不良时， 容易发生半导体层露出， 此时因外部光的照射导致 TFT的漏电流 异常增加， 结果液晶显示器出现偏绿（Greenish )及水平灰度不均 （X-talk ) 等显示不良。
另外， 液晶显示器尤其高分辨率的产品， 需要降低公共电极的电阻， 否 则会因公共电极电阻过大产生延迟， 也容易发生液晶显示器偏绿（Greenish ) 及灰度不均 （X-talk )等显示不良， 影响画面品质， 但如果通过增大公共电 极的线宽来降低公共电极的电阻， 又会导致开口率减小。 发明内容
本发明实施例提供一种阵列基板及其制造方法、 显示装置， 可在不降低 透过率的前提下， 避免液晶显示器出现偏绿（Greenish )及水平灰度不均 ( X-talk )等显示不良问题， 提高显示装置尤其是高分辨率产品的画面品质。
为达到上述目的， 本发明的实施例采用如下技术方案：
根据本发明的第一方面， 提供一种阵列基板， 包括： 基板和自下而上依 次设置于所述基板上的第一栅金属层、 第一栅绝缘层、 半导体层、 源漏电极 层， 所述阵列基板还包括：
设置在所述源漏电极层上的第二栅绝缘层； 以及，
设置在所述第二栅绝缘层上第二栅金属层。
在一个示例中， 上述阵列基板还包括：
第一公共电极线， 与所述第一栅金属层位于同一层， 或者与所述第二栅 金属层位于同一层。
在一个示例中， 上述阵列基板还包括： 第二公共电极线，
当所述第一公共电极线与所述第一栅金属层位于同一层时， 所述第二公 共电极线与所述第二栅金属层位于同一层； 当所述第一公共电极线与所述第 二栅金属层位于同一层时， 所述第二公共电极线与所述第一栅金属层位于同 一层。
在一个示例中， 所述第二公共电极线与所述第一公共电极线并联， 且第 二公共电极线与第一公共电极线的线宽相同。
在一个示例中， 上述阵列基板还包括：
树脂层， 覆盖在所述第二栅金属层上； 以及，
用于产生电场以驱动液晶的第一电极、 第二电极， 以及设置在所述的第 一电极、 第二电极之间的钝化层， 所述第一电极设置在所述树脂层之上， 所 述第二电极设置在所述钝化层之上。
在一个示例中， 所述第一电极通过所述树脂层中的过孔与所述第一公共 电极线相连接。
在一个示例中， 所述第二电极通过所述钝化层、 树脂层及所述第二栅绝 缘层中的漏极过孔与所述源漏电极层的漏极相连。
在一个示例中， 所述第二栅金属层位于第一栅金属层的正上方。 根据本发明的第二方面， 提供一种显示装置， 包括上述的阵列基板。 根据本发明的第三方面， 提供一种阵列基板的制造方法， 包括： 在基板上形成第一栅金属层；
在形成有第一栅金属层的基板上形成第一栅绝缘层；
在形成有第一栅金属层和第一栅绝缘层的基板上， 自下而上依次形成半 导体层、 源漏电极层、 第二栅绝缘层和第二栅金属层。
在一个示例中， 上述方法还包括：
在形成有第一栅金属层、 第一栅绝缘层、 半导体层、 源漏电极层、 第二 栅绝缘层和第二栅金属层的基板上， 形成树脂层及树脂层的过孔图形；
在完成上述步骤的基板上形成第一透明导电膜层， 采用构图工艺形成第 一电极；
形成钝化层及钝化层的过孔图形；
形成第二透明导电膜层， 采用构图工艺形成第二电极。
在一个示例中， 上述方法还包括在形成所述第二栅金属层同时， 形成第 一公共电极线。
在一个示例中， 上述方法还包括在形成第一栅金属层的同时， 形成第二 公共电极线。
在一个示例中， 所述第二公共电极线与所述第一公共电极线并联， 且第 二公共电极线与第一公共电极线的线宽相同。
在一个示例中， 所述第一栅金属层和第二栅金属层采用相同的掩模板通 过构图工艺形成。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为一种现有阵列基板的结构示意图；
图 2为本发明实施例一提供的阵列基板的结构示意图；
图 3为本发明实施例二提供的阵列基板的结构示意图；
图 4为本发明实施例四提供的阵列基板的制造方法流程图； 图 5a至图 5g为本发明实施例四中阵列基板的制造过程中基板的截面示 意图；
图 6为图 4中步骤 103的流程图；
图 7a至图 7d为图 4中步骤 103的制造过程中基板的截面示意图。
附图标记说明
1, 10-基板， 2-栅金属层， 3-栅绝缘层， 111-第一栅金属层，
112-第二栅金属层， 121-第一栅绝缘层， 122-第二栅绝缘层，
4,13-半导体层， 5,14-源漏电极层， 15-树脂层， 16-数据线，
6,17-公共电极， 8,18-钝化层， 9-公共电极线，
191-第二公共电极线， 192-第一公共电极线， 7, 20-像素电极。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例提供一种阵列基板及其制造方法、 显示装置， 可在不降低 透过率的前提下， 改善液晶显示器出现的偏绿（Greenish )及水平 X-talk等 显示不良， 提高显示装置的画面品质。
实施例一
本发明实施例提供一种阵列基板， 如图 2所示， 该阵列基板包括： 基板 10 和自下而上依次设置于所述基板上的第一栅金属层 111、 第一栅绝缘层 121、 半导体层 13、 源漏电极层 14, 还包括：
设置在所述源漏电极层 14上的第二栅绝缘层 122; 以及，
设置在第二栅绝缘层 122上的第二栅金属层 112。
所述的第一栅金属层 111与第二栅金属层 112可采用相同的材质， 例如 选自钼、 铝、 铬、 铜中的一种或多种。 所述的第一栅绝缘层 121与第二栅绝 缘层 122也可采用相同的材质， 例如可以均为氮化硅薄膜， 当然也可采用不 同的材质。 另外， 本实施例中所述的第一栅金属层 111与第二栅金属层 112均包括 栅极和栅线图案。 优选地， 第一栅金属层 111与第二栅金属层 112具有相同 的图形， 可以采用同一掩模板进行光刻而成。 因此， 第一栅金属层 111与第 二栅金属层 112均包括栅极和与栅极相连的栅线。
具体实施中， 设计人员可以根据需要选择以下两个方案中的一个。 第一 个方案是薄膜晶体管采用顶栅结构， 栅极扫描信号加到第二栅金属层 112形 成的顶栅和栅线上， 第一栅金属层 111仅起遮挡背光的作用； 当然薄膜晶体 管也可以采用底栅结构， 栅极扫描信号加到第一栅金属层 111形成的底栅和 栅线上， 第二栅金属层 112仅起遮挡外部光的作用。 第二个方案是形成双沟 道的薄膜晶体管， 即薄膜晶体管采用双栅结构， 栅极扫描信号同时加载到： 第二栅金属层 112形成的栅线及顶栅和第一栅金属层 111形成的栅线及底栅 上。 第二栅绝缘层 122和第一栅绝缘层 121的材质都是 SiNx, 都是载流子运 动的界面。 双沟道的薄膜晶体管可以增大开启电流。
本实施例所述阵列基板,在半导体层 13的上方和下方分别设置有第二栅 金属层 112与第一栅金属层 111 , 位于半导体层 13上方的第二栅金属层 112 遮挡从上方入射的外部光（从彩膜基板一侧进入的光）； 位于半导体层 13下 方的第一栅金属层 111遮挡从下方（阵列基板侧的背光源发出的光），这样可 防止半导体层 13受到光照射， 避免因光照射导致的 TFT漏电流异常增加， 并且第二栅金属层 112和第一栅金属层 111的位置相互重叠， 透过率不会因 此降低。 具体实施中， 阵列基板的工艺通常会出现 3~4 μ ιη的偏差， 而栅金 属层的层叠覆盖 ( Overlay )误差在 1 μ m以下， 因此能够改善水平 X-talk特 性。
综上所述， 本实施例所述阵列基板可在不降低透过率的前提下， 改善液 晶显示器出现的偏绿（Greenish )及水平 X-talk等显示不良， 提高显示装置 的画面品质。
在一个示例中， 所述阵列基板还可包括： 第一公共电极线 192, 与第二 栅金属层 112位于同一层（如图 2所示 ),或者与第一栅金属层 111位于同一 层。
在一个示例中， 所述阵列基板还可包括： 树脂层 15 , 覆盖在第二栅金属 层 112上； 以及， 用于产生电场以驱动液晶的第一电极 (例如图中的公共电极 17 )、 第二 电极（例如图中的像素电极 20 ), 以及设置在第一电极、 第二电极之间的钝 化层 18, 第一电极（公共电极 17 )设置在树脂层 15之上， 第二电极 (像素电 极 20)设置在钝化层 18之上。
本实施例中的第一电极和第二电极还可以分别指像素电极和公共电极。 换言之， 若其中之一（如第二电极）为像素电极， 另一（第一电极）则为公 共电极。 一般地， 在上的电极为狭缝状电极， 在下的电极可以为板状电极， 也可以为狭缝状电极。 并且，作为像素电极的第二电极（也可以为第一电极） 与上述薄膜晶体管的漏极相连， 作为公共电极的第一电极（对应地为第二电 极）与公共电极线相连。例如，如图 2所示，下方的公共电极 17为板状电极， 通过树脂层 15中的过孔与第一公共电极线 192相连接； 上方的像素电极 20 为狭缝状电极， 通过钝化层 18、 树脂层 15及第二栅绝缘层 122中的过孔与 薄膜晶体管的漏极相连， 所述的薄膜晶体管可包括： 第一栅金属层 111、 第 一栅绝缘层 121、 源漏电极层 14、 半导体层 13。 显示数据经该薄膜晶体管加 载到像素电极 20和公共电极 17 ,像素电极 20和公共电极 17产生驱动电场， 液晶分子在该驱动电场作用下发生偏转从而显示出图像。
本实施例所述阵列基板可在不降低透过率的前提下， 改善液晶显示器出 现的偏绿（Greenish )及水平 X-talk等显示不良， 提高显示装置的画面品质。
实施例二
本发明实施例提供一种阵列基板，与图 2所示实施例一的区别之处在于， 所述阵列基板还包括： 第二公共电极线。
例如， 当所述第一公共电极线与所述第一栅金属层位于同一层时， 所述 第二公共电极线与所述第二栅金属层位于同一层； 当所述第一公共电极线与 所述第二栅金属层位于同一层时， 所述第二公共电极线与所述第一栅金属层 位于同一层；
所述第二公共电极线通过所述第一栅绝缘层以及所述第二栅绝缘层中的 过孔与所述第一公共电极线相连。
为更好的理解本实施例， 在此举出本实施例的一种具体实施方式， 如图 3所示， 该阵列基板包括： 基板 10, 自下而上依次设置于基板 10上的第一栅 金属层 111、 第一栅绝缘层 121、 半导体层 13、 源漏电极层 14、 第二栅绝缘 层 122和第二栅金属层 112; 除此之外， 该阵列基板还包括：
第一公共电极线 192, 与第二栅金属层 112位于同一层；
第二公共电极线 191 , 与第一栅金属层 111位于同一层；
第二公共电极线 191通过第一栅绝缘层 121以及第二栅绝缘层 122中的 过孔与第一公共电极线 192相连。
本实施例中， 第一公共电极线 192与第二栅金属层 112位于同一层， 可 以由同一金属膜层经涂胶、 曝光、 刻蚀、 显影等步骤同步制成。 类似地， 第 二公共电极线 191与第一栅金属层 111也位于同一层， 同样可由同一金属膜 层同步制成。
公共电极电阻过大产生延迟而影响画面品质， 也容易发生液晶显示装置 偏绿（Greenish )及水平 X-talk等显示不良， 影响画面品质。 通过加大公共 电极的宽度或者使用低电阻材料形成公共电极， 可以降低公共电极电阻， 但 是加大公共电极的宽度一般会影响像素开口率； 而使用低电阻材料， 公共电 极的电阻降低有限， 而且还可能需要改变制备工艺， 因此缺乏实用性。
而本实施例在薄膜晶体管的下方再形成第二公共电极线 191 , 第二公共 电极线 191的线宽小于等于第一公共电极线 192的线宽。第二公共电极线 191 与第一公共电极线 192并联， 且第二公共电极线 191的位置与第一公共电极 线 192相重叠， 相互遮挡， 因此无需加大线宽就能在不影响像素开口率的前 提下降低公共电极的电阻， 避免因公共电极电阻过大产生延迟， 这对显示装 置尤其是高分辨率的产品尤为重要。 其中， 优选地， 第二公共电极线 191与 第一公共电极线 192并联，且第二公共电极线 191采用与第一公共电极线 192 相同的线宽。
在一个示例中， 所述阵列基板还可包括： 数据线 16, 与薄膜晶体管的源 漏电极层 14位于同一层。
在一个示例中， 所述阵列基板还可包括：
树脂层 15, 覆盖在第二栅金属层 112上； 以及，
用于产生电场以驱动液晶的像素电极 20、公共电极 17, 以及设置在像素 电极 20、公共电极 17之间的钝化层 18,公共电极 17设置在树脂层 15之上， 像素电极 20设置在钝化层 18之上。
可选地， 公共电极 17通过树脂层 15中的过孔与第一公共电极线 192相 连接； 像素电极 20通过钝化层 18、树脂层 15及其下的第二栅绝缘层 122中 的过孔与源漏金属层 14 (薄膜晶体管的漏极）相连。 在上的像素电极 20为 狭缝状， 位于下方的公共电极 17可以是板状的也可以是狭缝状的。
另外， 需要说明的是， 本实施例中与漏极相连的为像素电极， 与公共电 极线相连的为公共电极， 公共电极与像素电极的位置可以互换， 但在上的电 极需为狭缝状， 在下的电极可以是板状的也可以是狭缝状的。
本实施例提供的阵列基板， 由于第一栅金属层和第二栅金属层的遮挡作 用， 可避免因半导体层受到光照射导致的 TFT漏电流异常增加； 同时采用第 一、 第二公共电极线的重叠双线结构， 可在不影响像素开口率的前提下降低 公共电极的电阻， 避免因公共电极电阻过大产生延迟。 因此， 本实施例所述 阵列基板可在不降低透过率的前提下， 改善液晶显示器出现的偏绿
( Greenish )及水平 X-talk等显示不良， 提高显示装置的画面品质。
实施例三
本发明实施例还提供了一种显示装置， 其包括实施例一和二中所述的任 意一种阵列基板。 所述显示装置可以为： 液晶面板、 电子纸、 OLED面板、 手机、 平板电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何 具有显示功能的产品或部件。
本实施例所述显示装置， 因采用了本发明所述的阵列基板上， 因此可在 不降低透过率的前提下， 改善显示装置出现的偏绿（ Greenish )及水平 X-talk 等显示不良， 显示效果得以提高。
实施例四
本发明实施例还提供一种阵列基板的制造方法， 如图 4和图 5所示， 该 方法包括：
101、 在基板 10上形成第一栅金属层 111 (图 5a );
本实施例中阵列基板还可如图 3所示， 包括第一公共电极线 192和第二 公共电极线 191 , 第二公共电极线 191可与第一栅金属层 111位于同一层。 例如， 在基板 10上形成栅金属膜层， 通常形成薄膜可以采用沉积、 涂覆、 溅 射等多种方式， 然后通过涂覆光刻胶涂胶、 曝光、 显影和刻蚀等步骤， 在基 板 10上形成第一栅金属层 111 (包括栅极及栅线的图案）的图案， 以及第二 公共电极线 191的图案。 102、 在完成 101步骤的基板上形成第一栅绝缘层 121 (图 5b );
第一栅绝缘层 121与图 1所示的栅绝缘层 12图形相同，因此本步骤可采 用现有技术中形成栅绝缘层 3时所使用的掩模板， 从而在形成第一栅绝缘层 121的同时形成过孔，暴露第二公共电极线 191。 当然也可以不使用掩模板形 成过孔， 形成第一栅绝缘层即可。 本实施例中的第一、 第二栅绝缘层的材料 例如采用 SiNx等绝缘材料。
103、 在完成 102步骤的基板上自下而上依次形成： 半导体层 13、 源漏 电极层 14、 第二栅绝缘层 122和第二栅金属层 112; 其中， 源漏电极层 14 包括源电极、 漏电极、 数据线的图案（图 5c );
本步骤中， 在形成第二栅金属层 112时可使用步骤 103中形成薄膜晶体 管的第一栅金属层 111时所使用的掩模板， 以使两个栅金属层的宽度相同。 在形成第二栅绝缘层 122时， 可同时利用掩模板在第二栅绝缘层 122中形成 暴露薄膜晶体管的漏极的漏极过孔。
可选地， 如图 3所示， 如果阵列基板还包括与第二栅金属层 112位于同 一层的第一公共电极线 192, 且第一公共电极线 192通过第二栅绝缘层 122 及第一栅绝缘层 121中的过孔与第二公共电极线 191相连，那么在本步骤中， 与第二栅金属层 112同步形成的还有第一公共电极线 192, 另外此时还需要 形成的是： 第二公共电极线 191与第一公共电极线 192的连接过孔。
本步骤中半导体层 13、源漏电极层 14、第二栅绝缘层 122和第二栅金属 层 112采用常规的材料， 其制备过程包括， 例如， 第 2次掩模工艺形成半导 体层， 第 3次掩模工艺形成源漏电极层 14, 第 4次掩模工艺在第二栅绝缘层 122中形成 191与 192的连接过孔以及漏极过孔， 第 5次掩模工艺形成第二 栅金属层 112。
在本步骤中，第二栅绝缘层 122上需设置两个过孔，因此可使用步骤 104 形成树脂层 15时所使用的掩模板。
104、在完成 103步骤的基板上形成树脂层及树脂层的过孔图形（图 5d ); 形成树脂层 15的过孔图形是指：形成公共电极 17与第一公共电极线 192 的连接过孔。 进一步地， 可以在形成树脂层的该连接过孔时一并形成漏极过 素电极和薄膜晶体管的漏极。 105、在完成 104步骤的基板上形成第一透明导电膜层，采用构图工艺形 成第一电极（图 5e )。 图 5e中， 第一电极为公共电极 17, 公共电极 17通过 第一公共电极线 192上方的树脂层 15中的过孔与第一公共电极线 192相连。
106、 在完成 105步骤的基板上形成钝化层 18及钝化层的过孔图形 （图 5f );
本步骤形成钝化层的过孔图形可以有 2个方案： 第一个方案， 可以在钝 化层 18上形成漏极过孔， 贯穿钝化层 18、 树脂层 15和第二栅绝缘层 122, 露出漏电极； 第二个方案也可以分步形成漏极过孔， 即在已形成有漏极过孔 的树脂层 15的基础上再形成贯穿钝化层 18的过孔。
107、在完成 106步骤的基板上形成第二透明导电膜层，采用构图工艺形 成第二电极（图 5g )。
如图 5g所示， 第二电极为像素电极 20且像素电极 20通过贯穿钝化层 18、 树脂层 15及第二栅绝缘层 122的漏极过孔与薄膜晶体管的漏极相连。
在上述制造方法中， 通过步骤 101~103所形成的第一、 第二栅金属层可 作为薄膜晶体管半导体层的遮挡层， 可避免因半导体层受到光照射导致的 TFT漏电流异常增加， 因此， 本实施例所述阵列基板可在不降低透过率的前 提下， 改善液晶显示器出现的偏绿（Greenish )及水平 X-talk等显示不良， 提高显示装置的画面品质。 进一步地， 形成的阵列基板中还设置有层叠的第 一公共电极线和第二公共电极线， 可在不影响像素开口率的前提下降低公共 电极的电阻， 避免因公共电极电阻过大产生延迟。 本实施例提供的阵列基板 制造方法， 无需增加新的掩模板， 因此不需要对现有制造方法和设备做较大 改动。
在上述方法中， 第二电极（图中的像素电极 20 )可为狭缝状。
在上述方法中， 步骤 103如图 6所示， 可包括：
1031、 在第一栅绝缘层 121上形成半导体层 13, 并采用构图工艺形成所 述薄膜晶体管的半导体层图案（图 7a );
1032、 形成源漏电极层 14, 采用构图工艺分别在半导体层 13上形成所 述薄膜晶体管的源极和漏极以及数据线 16 (图 7b );
1033、 形成第二栅绝缘层 122 (图 7c );
1034、 形成第二栅金属层 112, 采用构图工艺形成栅极， 栅线， 以及第 一公共电极线 192 (图 7d ), 其中第一公共电极线 192位于第二公共电极线 191上方的对应位置。
本实施例提供的阵列基板的制造方法， 无需增加新的掩模板， 形成的阵 列基板即可在不降低透过率的前提下， 改善液晶显示器出现的偏绿 ( Greenish )及水平 X-talk等显示不良， 提高显示装置的画面品质。
需要说明的是， 在本发明实施例中， 所述各步骤的序号并不能用于限定 各步骤的先后顺序， 对于本领域普通技术人员来讲， 在不付出创造性劳动的 前提下， 对各步骤的先后变化也在本发明的保护范围之内。 本发明实施例所 述的技术特征， 在不沖突的情况下， 可任意相互组合使用。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、一种阵列基板， 包括： 基板和自下而上依次设置于所述基板上的第一 栅金属层、 第一栅绝缘层、 半导体层、 源漏电极层， 所述阵列基板还包括： 设置在所述源漏电极层上的第二栅绝缘层； 以及，
设置在所述第二栅绝缘层上第二栅金属层。
2、 根据权利要求 1所述的阵列基板， 还包括：
第一公共电极线， 与所述第一栅金属层位于同一层， 或者与所述第二栅 金属层位于同一层。
3、 根据权利要求 2所述的阵列基板， 还包括： 第二公共电极线， 当所述第一公共电极线与所述第一栅金属层位于同一层时， 所述第二公 共电极线与所述第二栅金属层位于同一层； 当所述第一公共电极线与所述第 二栅金属层位于同一层时， 所述第二公共电极线与所述第一栅金属层位于同 一层。
4、根据权利要求 3所述的阵列基板，其中所述第二公共电极线与所述第 一公共电极线并联， 且第二公共电极线与第一公共电极线的线宽相同。
5、 根据权利要求 1-4任一项所述的阵列基板， 还包括：
树脂层， 覆盖在所述第二栅金属层上； 以及，
用于产生电场以驱动液晶的第一电极、 第二电极， 以及设置在所述的第 一电极、 第二电极之间的钝化层， 所述第一电极设置在所述树脂层之上， 所 述第二电极设置在所述钝化层之上。
6、根据权利要求 5所述的阵列基板，其中所述第一电极通过所述树脂层 中的过孔与所述第一公共电极线相连接。
7、根据权利要求 5所述的阵列基板,其中所述第二电极通过所述钝化层、 树脂层及所述第二栅绝缘层中的漏极过孔与所述源漏电极层的漏极相连。
8、根据权利要求 7所述的阵列基板，其中所述第二栅金属层位于第一栅 金属层的正上方。
9、 一种显示装置， 包括权利要求 1-8任一项所述的阵列基板。
10、 一种阵列基板的制造方法， 包括：
在基板上形成第一栅金属层； 在形成有第一栅金属层的基板上形成第一栅绝缘层；
在形成有第一栅金属层和第一栅绝缘层的基板上， 自下而上依次形成半 导体层、 源漏电极层、 第二栅绝缘层和第二栅金属层。
11、 根据权利要求 10所述的方法， 还包括：
在形成有第一栅金属层、 第一栅绝缘层、 半导体层、 源漏电极层、 第二 栅绝缘层和第二栅金属层的基板上， 形成树脂层及树脂层的过孔图形；
在完成上述步骤的基板上形成第一透明导电膜层， 采用构图工艺形成第 一电极；
形成钝化层及钝化层的过孔图形；
形成第二透明导电膜层， 采用构图工艺形成第二电极。
12、 根据权利要求 10或 11所述的方法， 还包括在形成所述第二栅金属 层同时， 形成第一公共电极线。
13、 根据权利要求 12所述的方法， 还包括在形成第一栅金属层的同时， 形成第二公共电极线。
14、根据权利要求 13所述的方法，其中所述第二公共电极线与所述第一 公共电极线并联， 且第二公共电极线与第一公共电极线的线宽相同。
15、 根据权利要求 11-14任一项所述的方法， 其中所述第一栅金属层和 第二栅金属层采用相同的掩模板通过构图工艺形成。
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