TWI686647B - Tft基板、esd保護電路及tft基板的製作方法 - Google Patents
Tft基板、esd保護電路及tft基板的製作方法 Download PDFInfo
- Publication number
- TWI686647B TWI686647B TW107140853A TW107140853A TWI686647B TW I686647 B TWI686647 B TW I686647B TW 107140853 A TW107140853 A TW 107140853A TW 107140853 A TW107140853 A TW 107140853A TW I686647 B TWI686647 B TW I686647B
- Authority
- TW
- Taiwan
- Prior art keywords
- gate
- tft
- source
- protection circuit
- insulating layer
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title abstract description 14
- 238000000034 method Methods 0.000 abstract description 29
- 230000002159 abnormal effect Effects 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 16
- 229920005591 polysilicon Polymers 0.000 description 16
- 238000000206 photolithography Methods 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 239000004973 liquid crystal related substance Substances 0.000 description 12
- 230000003068 static effect Effects 0.000 description 10
- 230000005611 electricity Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 238000000059 patterning Methods 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- 239000011521 glass Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Theoretical Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Liquid Crystal (AREA)
Abstract
本發明涉及了一種TFT基板、ESD保護電路及TFT基板的製作方法,該實施例的TFT基板包括:襯底基板;設於襯底基板上的第一閘極;設於第一閘極上方的第一絕緣層;設於第一絕緣層上方的汲極、源極及有源層;設於汲極、源極及有源層上方的第二絕緣層;設於第二絕緣層上方的第二閘極。這樣,可避免液晶面板畫面顯示異常。
Description
本發明涉及液晶顯示領域,尤其涉及一種TFT基板、ESD保護電路及TFT基板的製作方法。
由於TFT-LCD(Thin Film Transistor Liquid Crystal Display,薄膜電晶體液晶顯示器)具有輕、薄、耗電小等優點,被廣泛應用於電視、筆記型電腦、行動電話等設備。
作為一種平板顯示器件,液晶顯示器的液晶面板通常是由兩片玻璃基板及玻璃基板之間的液晶層組成。下玻璃基板上集成有若干數據線和若干掃描線,它們垂直交錯形成若干單元區域,這些單元區域被定義為像素單元。每個像素單元主要包括像素電極、存儲電容和TFT管等器件。掃描線上的驅動訊號可以控制TFT管的工作狀態,從而適時地將數據線上的驅動訊號寫入像素電極。形成上述驅動陣列的玻璃基板一般稱為TFT基板。上玻璃基板上集成有黑色矩陣、彩色濾光膜層及公用電極層。上玻璃基板由於設置有彩色濾光膜層,所以通常又稱為彩膜基板。TFT基板和彩膜基板可統稱為液晶顯示基板。
然而,在液晶顯示基板的製造過程中,如顯影、刻蝕(etching)、液晶配向成盒以及搬運等多個工序都可能導致靜電釋放(Electro-Static Discharge,簡稱ESD)。靜電產生的電荷會使TFT管器件及絕緣層受到損傷,從而導致液晶面板等級降低和影響生產良率。因此,在液晶面板的設計中,也會
在面板上設計出用於釋放靜電荷的專用路徑及元件,這樣的設計可稱為ESD保護電路。
圖1是現有技術中一種ESD保護電路的結構示意圖,在該ESD保護電路中,TFT管M1的源極連接TFT管M2的汲極,TFT管M1的汲極接正電壓(VGH),TFT管M2的源極接負電壓(VGL),而且,TFT管M1的閘極與其源極並接,TFT管M2的閘極與其源極也並接。數據訊號(Data)由驅動IC生成並輸出至相應的像素電極,而且,中間經過該ESD保護電路來防止從外部流入的靜電問題。當發生靜電時,靜電(為-KV的高的電壓)從外部流入進來時,會排出到每個VGH和VGL邊。但是,在該ESD保護電路中,由於TFT管製程上初始開啟電壓的均勻性分佈較差,所以,實際產品中TFT管的初始開啟電壓會向負電壓移動,即,TFT管的初始開啟電壓小於0。結合圖2,兩個TFT管M1、M2因初始開啟電壓為負電壓而導通,從而產生較大的汲電流。當數據訊號進入時,由於汲電流的存在使得數據訊號(Data)中摻雜正電壓(VGH),如圖3所示,其中,實線代表從驅動IC輸出的數據訊號,虛線代表經ESD保護電路後的數據訊號。在使用該數據訊號驅動像素電極時,由於數據訊號中摻雜了不想要的電壓,所以該像素電極的亮度就會發生異常,從而使得液晶面板顯示的畫面發生異常。
本發明要解決的技術問題在於,現有技術的上述TFT管因開啟電壓小於零導致在靜電發生時液晶面板顯示異常。
本發明解決其技術問題所採用的技術方案是:構造一種TFT基板,包括:襯底基板;
設於所述襯底基板上的第一閘極;設於所述第一絕緣層上方的汲極、源極及有源層,至少部分所述汲極及至少部分所述源極間隔設置於所述有源層的外端,且通過所述有源層連接;設於所述汲極、所述源極及所述有源層上方的第二絕緣層;設於所述第二絕緣層上方的第二閘極,而且,所述第二閘極接入負電壓。
優選地,所述第一閘極和所述第二閘極到所述有源層的距離相同。
優選地,所述第二閘極為U型。
優選地,所述有源層在所述襯底基板上的正投影至少部分地覆蓋所述第一閘極在所述襯底基板上的正投影。
優選地,所述汲極和所述源極呈階梯狀,且對稱設置於所述有源層的外端。
優選地,所述第一閘極和所述第二閘極的形狀和尺寸相同。
本發明還構造一種ESD保護電路,其特徵在於,包括以上所述的TFT基板,所述TFT基板包括第一TFT管和第二TFT管,其中,第一TFT管的汲極接入正電壓訊號,第二TFT管的源極接入負電壓訊號,第一TFT管的源極、第一TFT管的第一閘極與所述第二TFT管的汲極一併接入數據訊號,第二TFT管的第一閘極與源極相連。
優選地,所述第一TFT管的第二閘極和所述第二TFT管的第二閘極分別連接所述第二TFT管的源極。
本發明還構造一種TFT基板的製作方法,包括以下步驟:步驟S11.提供一襯底基板,並在所述襯底基板上形成第一閘極;步驟S12.在所述第一閘極及所述襯底基板上形成第一絕緣層,且所述第一絕緣層完全覆蓋所述第一閘極;步驟S13.在所述第一絕緣層上形成汲極、源極及有源層,至少部分所述汲極及至少部分所述源極間隔設置於所述有源層的外端,且通過所述有源層連接;步驟S14.在所述汲極、所述源極及所述有源層上方形成第二絕緣層,且所述第二絕緣層完全覆蓋所述汲極、所述源極及所述有源層;步驟S15.在所述第二絕緣層上方形成接負電壓的第二閘極。
優選地,在所述步驟S11中,在所述襯底基板上形成所述第一閘極,包括:在所述襯底基板上沉積第一金屬層,採用一道光刻製程對所述第一金屬層進行圖案化處理,得到所述第一閘極;或者,通過在所述襯底基板上形成第一多晶矽層,對所述第一多晶矽層進行N型摻雜後,採用一道光刻製程對所述N型摻雜多晶矽層進行圖案化處理,得到所述第一閘極。
優選地,所述步驟S13包括:
採用化學或物理氣相沉積方法在所述第一絕緣層上沉積半導體層,採用一道光刻製程對所述半導體層進行圖案化處理後得到所述有源層;通過在所述有源層及所述第一絕緣層上沉積第二金屬層,採用一道光刻製程對所述第二金屬層進行圖案化處理,得到所述源極和所述汲極;或,通過在所述有源層及所述第一絕緣層上形成第二多晶矽層,對所述第二多晶矽層進行N型摻雜後,採用一道光刻製程對所述第二多晶矽層進行圖案化處理,得到所述源極和所述汲極。
優選地,所述步驟S15包括:在所述第二絕緣層上沉積第三金屬層,採用一道光刻製程對所述第三金屬層進行圖案化處理,得到所述第二閘極;或者,通過在所述第二絕緣層上形成第三多晶矽層,對所述第三多晶矽層進行N型摻雜後,採用一道光刻製程對所述N型摻雜多晶矽層進行圖案化處理,得到所述第二閘極。
優選地,所述光刻製程包括光阻、曝光、顯影及蝕刻製程。
實施本發明的技術方案,由於TFT基板採用雙閘極結構,且第二閘極接負電壓,所以可使TFT管的開啟電壓往正方向移動。而且,當使用TFT管構建ESD保護電路時,即使發生靜電,由於兩個TFT管的開啟電壓都大於0,漏電流(leakage currents)非常小,可忽略,這樣,從驅動IC輸出至像素電極的數據訊號中就不會摻雜不想要的電壓信號了,也就不會發生像素電極亮度異常的情況,從而避免液晶面板畫面異常的發生。
為了更清楚地說明本發明實施例,下面將對實施例描述中所需要使用的附圖作簡單地介紹,顯而易見地,下面描述中的附圖僅僅是本發明的一些實施例,對於任何所屬技術領域中具有通常知識者來講,還可以根據這些附圖獲得其他的附圖。
11:襯底基板
12:第一閘極
13:第一絕緣層
14:汲極
15:源極
16:有源層
17:第二絕緣層
18:第二閘極
S11~S15:步驟
VGH:汲極接正電壓
VGL:源極接負電壓
M1、M2:TFT管
圖1是現有技術中一種ESD保護電路的電路結構圖。
圖2是圖1中的ESD保護電路在發生靜電時的示意圖。
圖3是在發生靜電時輸入的數據訊號和輸出的數據訊號的波形圖;圖4是本發明TFT基板實施例一的結構示意圖。
圖5是現有技術的TFT管與本發明的TFT管的開啟電壓的模擬示意圖。
圖6是本發明ESD保護電路的電路結構圖。
圖7是本發明TFT基板的製作方法實施例一的流程圖。
下面將結合本發明實施例中的附圖,對本發明實施例中的技術方案進行清楚、完整地描述,顯然,所描述的實施例僅僅是本發明一部分實施例,而不是全部的實施例。基於本發明中的實施例,任何所屬技術領域中具有通常知識者在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾所獲得的所有其他實施例,都屬於本發明保護的範圍。
圖4是本發明TFT基板實施例一的結構示意圖,該實施例的TFT基板包括層疊設置的襯底基板11、第一閘極12、第一絕緣層13、汲極14、源極15、有源層16、第二絕緣層17及第二閘極18。其中,第一閘極12設於襯底基板11上,其面積小於襯底基板11,優選設置於襯底基板11的中
間部分。第一絕緣層13設於第一閘極12上方,汲極14、源極15及有源層16設於第一絕緣層13上方,而且,至少部分汲極14及至少部分源極15間隔設置於有源層16的外端,且通過有源層16連接。另外,第二絕緣層17設於汲極14、源極15及有源層16上方,覆蓋汲極14、源極15及有源層16,第二閘極18設於第二絕緣層17上方,而且,第二閘極18接入負電壓。
而且,在該實施例中,有源層16在襯底基板11上的正投影部分地覆蓋第一閘極12在襯底基板11上的正投影。當然,在其它實施例中,也可全部覆蓋第一閘極12在襯底基板11上的正投影。
進一步地,汲極14和源極15呈階梯狀,且對稱設置於有源層16的兩端及頂端。當然,在其它實施例中,汲極14和源極15也可為其它形狀,而且,也可設置在有源層的左右兩端、底端或頂端。
進一步地,第二閘極18的形狀為U型。當然,在其它實施例中,第一閘極12與第二閘極18的形狀、尺寸也可相同,而且,兩者分別到有源層16的距離相同,當然,在其它實施例中,兩者的形狀、尺寸及到有源層16的距離也可不等。
該實施例的TFT基板採用雙閘極結構,且第一閘極12和第二閘極18分佈在有源層的兩側。當給第一閘極施加電壓時,會產生導電溝道的導通電流,而由於第二閘極18施加的是負電壓,所以會抑制導電溝道的電流量,進而阻止導電溝道的截面積的增大,即,相當於增大了TFT管的開啟電壓。結合圖5,在未增加第二閘極18時,TFT管的開啟電壓為-5V,當增加第二閘極18後,TFT管的開啟電壓往正方向移動,變為0V。
圖6是本發明ESD保護電路的電路結構圖,該實施例的ESD保護電路包括以上實施例所示的TFT基板,而且,該TFT基板包括第一TFT管M1和第二TFT管M2,其中,第一TFT管M1的汲極接入正電壓訊號(VGH),第二TFT管M2的源極接入負電壓訊號(VGL),第一TFT管M1的源極、第一TFT管M1的第一閘極與第二TFT管M2的汲極一併接入數據訊號(Data),第二TFT管M2的第一閘極與源極相連。
優選地,第一TFT管M1的第二閘極和第二TFT管M2的第二閘極分別連接第二TFT管M2的源極,這樣,可以在沒有增加電壓源的基礎上,利用已有的負電壓信號(VGL)來連接第一TFT管M1的第二閘極和第二TFT管M2的第二閘極。
在該實施例的中,當驅動IC輸出資料信號(Data)後,經ESD保護電路輸出至像素電極,當發生靜電時,由於兩個TFT管M1、M2的開啟電壓都大於0,汲電流非常小,可忽略,這樣,數據訊號(Data)中就不會摻雜不想要的正電壓訊號(VGH)了,從而使得輸出至像素電極的數據訊號(Data)較準確,不會發生像素電極亮度異常的情況。
圖7是本發明TFT基板的製作方法實施例一的流程圖,該實施例的TFT基板的製作方法包括以下步驟:步驟S11.提供一襯底基板,並在襯底基板上形成第一閘極;具體地,在一個例子中,第一閘極的製作方法可為:在襯底基板上沉積第一金屬層,採用一道光刻製程對第一金屬層進行圖案化處理,得到第一閘極。第一金屬層的材料可為鋁、鉬、銅、銀。當然,在另一個例子中,第一閘極的製作方法可為:通過在襯底基板上形成第一多晶
矽層,對第一多晶矽層進行N型摻雜後,採用一道光刻製程對N型摻雜多晶矽層進行圖案化處理,得到第一閘極。
步驟S12.在第一閘極及襯底基板上形成第一絕緣層,且第一絕緣層完全覆蓋第一閘極;步驟S13.在第一絕緣層上形成汲極、源極及有源層,至少部分汲極及至少部分源極間隔設置於有源層的外端,且通過有源層連接;具體地,有源層的製作方法可為:採用化學或物理氣相沉積方法在第一絕緣層上沉積半導體層,採用一道光刻製程對半導體層進行圖案化處理後得到有源層。
具體地,汲極和源極的製作方法可為:通過在有源層及第一絕緣層上沉積第二金屬層,採用一道光刻製程對第二金屬層進行圖案化處理,得到源極和汲極;或,通過在有源層及第一絕緣層上形成第二多晶矽層,對第二多晶矽層進行N型摻雜後,採用一道光刻製程對第二多晶矽層進行圖案化處理,得到源極和汲極。
步驟S14.在汲極、源極及有源層上方形成第二絕緣層,且第二絕緣層完全覆蓋汲極、源極及有源層;步驟S15.在第二絕緣層上方形成接負電壓的第二閘極。
具體地,第二閘極的製作方法可為:在第二絕緣層上沉積第三金屬層,採用一道光刻製程對第三金屬層進行圖案化處理,得到第二閘極;或者,通過在第二絕緣層上案成第三多晶矽層,對第三多晶矽層進行N型摻雜後,採用一道光刻製程對N型摻雜多晶矽層進行圖案化處理,得到第二閘極。
進一步地,上述實施例中的光刻製程包括光阻、曝光、顯影及蝕刻製程。
以上所述僅為本發明的優選實施例而已,並不用於限制本發明,對於任何所屬技術領域中具有通常知識者來說,本發明可以有各種更改和變化。凡在本發明的精神和原則之內,所作的任何纂改、等同替換、改進等,均應包含在本發明的申請專利範圍範圍之內。
11:襯底基板
12:第一閘極
13:第一絕緣層
14:汲極
15:源極
16:有源層
17:第二絕緣層
18:第二閘極
Claims (7)
- 一種靜電釋放(ESD)保護電路,其中包括TFT基板,所述TFT基板包括第一TFT管和第二TFT管,其中,所述第一TFT管的汲極接入正電壓訊號,所述第二TFT管的源極接入負電壓訊號,所述第一TFT管的源極、所述第一TFT管的第一閘極與所述第二TFT管的汲極一併接入數據訊號,所述第二TFT管的第一閘極與源極相連;其中,所述TFT基板,包括:襯底基板;設於所述襯底基板上的第一閘極;設於所述第一閘極上方的第一絕緣層;設於所述第一絕緣層上方的汲極、源極及有源層,至少部分所述汲極及至少部分所述源極間隔設置於所述有源層的外端,且通過所述有源層連接;設於所述汲極、所述源極及所述有源層上方的第二絕緣層;以及設於所述第二絕緣層上方的第二閘極,而且,所述第二閘極接入負電壓。
- 如申請專利範圍第1項所述之ESD保護電路,其中所述第一閘極和所述第二閘極到所述有源層的距離相同。
- 如申請專利範圍第1項所述之ESD保護電路,其特徵在於,所述第二閘極為U型。
- 如申請專利範圍第1項所述之ESD保護電路,其中所述有源 層在所述襯底基板上的正投影至少部分地覆蓋所述第一閘極在所述襯底基板上的正投影。
- 如申請專利範圍第1項所述之ESD保護電路,其中所述汲極和所述源極呈階梯狀,且對稱設置於所述有源層的外端。
- 如申請專利範圍第1項所述之ESD保護電路,其中所述第一閘極和所述第二閘極的形狀和尺寸相同。
- 如申請專利範圍第1項所述的ESD保護電路,其中所述第一TFT管的第二閘極和所述第二TFT管的第二閘極分別連接所述第二TFT管的源極。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
??PCT/CN2017/113151 | 2017-11-27 | ||
WOPCT/CN2017/113151 | 2017-11-27 | ||
PCT/CN2017/113151 WO2019100394A1 (zh) | 2017-11-27 | 2017-11-27 | Tft基板、esd保护电路及tft基板的制作方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201925871A TW201925871A (zh) | 2019-07-01 |
TWI686647B true TWI686647B (zh) | 2020-03-01 |
Family
ID=66630829
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW107140853A TWI686647B (zh) | 2017-11-27 | 2018-11-16 | Tft基板、esd保護電路及tft基板的製作方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US20200365576A1 (zh) |
EP (1) | EP3719838A4 (zh) |
JP (1) | JP2021504952A (zh) |
KR (1) | KR20200087854A (zh) |
CN (1) | CN111357107A (zh) |
TW (1) | TWI686647B (zh) |
WO (1) | WO2019100394A1 (zh) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6479883B1 (en) * | 2000-05-04 | 2002-11-12 | United Microelectronics Corp. | Electrostatic discharge protection circuit |
US6912109B1 (en) * | 2000-06-26 | 2005-06-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Power-rail ESD clamp circuits with well-triggered PMOS |
CN103165525A (zh) * | 2011-12-13 | 2013-06-19 | 上海天马微电子有限公司 | Tft阵列基板及其上esd保护电路的制备方法 |
CN106373955A (zh) * | 2015-07-20 | 2017-02-01 | 马利峰 | 一种用于esd防护的双栅scr结构设计 |
CN106960663A (zh) * | 2015-10-23 | 2017-07-18 | Nlt科技股份有限公司 | 保护电路及电子设备 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009272479A (ja) * | 2008-05-08 | 2009-11-19 | Sharp Corp | 半導体装置、集積回路及び表示装置 |
TWI642043B (zh) * | 2009-09-10 | 2018-11-21 | 日商半導體能源研究所股份有限公司 | 半導體裝置和顯示裝置 |
TWI535028B (zh) * | 2009-12-21 | 2016-05-21 | 半導體能源研究所股份有限公司 | 薄膜電晶體 |
US8698137B2 (en) * | 2011-09-14 | 2014-04-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
WO2014002916A1 (en) * | 2012-06-29 | 2014-01-03 | Semiconductor Energy Laboratory Co., Ltd. | Method for using sputtering target and method for manufacturing oxide film |
US10269839B2 (en) * | 2015-03-26 | 2019-04-23 | Carestream Health, Inc. | Apparatus and method using a dual gate TFT structure |
WO2016175034A1 (ja) * | 2015-04-28 | 2016-11-03 | 三菱電機株式会社 | トランジスタ、薄膜トランジスタ基板および液晶表示装置 |
JP2017103408A (ja) * | 2015-12-04 | 2017-06-08 | 株式会社ジャパンディスプレイ | 表示装置 |
CN106252395B (zh) * | 2016-08-30 | 2019-12-03 | 昆山工研院新型平板显示技术中心有限公司 | 一种薄膜晶体管及其制备方法 |
CN106409844A (zh) * | 2016-11-29 | 2017-02-15 | 深圳市华星光电技术有限公司 | 底栅型多晶硅tft基板及其制作方法 |
JP6315113B2 (ja) * | 2017-01-12 | 2018-04-25 | セイコーエプソン株式会社 | 電気光学装置及び電子機器 |
-
2017
- 2017-11-27 CN CN201780096933.7A patent/CN111357107A/zh active Pending
- 2017-11-27 EP EP17933069.1A patent/EP3719838A4/en not_active Withdrawn
- 2017-11-27 US US16/765,970 patent/US20200365576A1/en not_active Abandoned
- 2017-11-27 JP JP2020528306A patent/JP2021504952A/ja active Pending
- 2017-11-27 WO PCT/CN2017/113151 patent/WO2019100394A1/zh unknown
- 2017-11-27 KR KR1020207017967A patent/KR20200087854A/ko not_active Application Discontinuation
-
2018
- 2018-11-16 TW TW107140853A patent/TWI686647B/zh not_active IP Right Cessation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6479883B1 (en) * | 2000-05-04 | 2002-11-12 | United Microelectronics Corp. | Electrostatic discharge protection circuit |
US6912109B1 (en) * | 2000-06-26 | 2005-06-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Power-rail ESD clamp circuits with well-triggered PMOS |
CN103165525A (zh) * | 2011-12-13 | 2013-06-19 | 上海天马微电子有限公司 | Tft阵列基板及其上esd保护电路的制备方法 |
CN106373955A (zh) * | 2015-07-20 | 2017-02-01 | 马利峰 | 一种用于esd防护的双栅scr结构设计 |
CN106960663A (zh) * | 2015-10-23 | 2017-07-18 | Nlt科技股份有限公司 | 保护电路及电子设备 |
Also Published As
Publication number | Publication date |
---|---|
WO2019100394A1 (zh) | 2019-05-31 |
US20200365576A1 (en) | 2020-11-19 |
EP3719838A4 (en) | 2021-07-07 |
CN111357107A (zh) | 2020-06-30 |
JP2021504952A (ja) | 2021-02-15 |
KR20200087854A (ko) | 2020-07-21 |
TW201925871A (zh) | 2019-07-01 |
EP3719838A1 (en) | 2020-10-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10725356B2 (en) | Array substrate, display panel and display apparatus | |
US9638975B2 (en) | Method for manufacturing COA liquid crystal panel comprising color resist blocks having first and second intersection zones and COA liquid crystal panel | |
US10216057B2 (en) | Array substrate and manufacturing method thereof, display panel and display device | |
US10209596B2 (en) | Pixel structure, method of manufacturing the same, array substrate and display device | |
US7129923B2 (en) | Active matrix display device | |
JP4699395B2 (ja) | 液晶ディスプレイの製造方法 | |
WO2016095316A1 (zh) | 一种液晶显示面板及其制造方法 | |
WO2017219702A1 (zh) | 一种显示基板、其制作方法及显示装置 | |
WO2017024744A1 (zh) | 显示基板及其制作方法和显示装置 | |
KR101622655B1 (ko) | 액정 표시 장치 및 이의 제조 방법 | |
US20140160416A1 (en) | Array substrate for tft-led, method of manufacturing the same, and display device | |
CN107958653B (zh) | 阵列基板及其驱动方法、驱动电路及显示装置 | |
WO2020015175A1 (zh) | 像素驱动电路及液晶显示装置 | |
WO2018010481A1 (en) | Array substrate and display panel, and fabrication methods thereof | |
CN103235452A (zh) | 一种阵列基板及显示装置 | |
US9524989B2 (en) | Array substrate and method of manufacturing the same, and liquid crystal display screen | |
WO2017177764A1 (zh) | 显示基板及液晶显示装置 | |
TWI406074B (zh) | 主動元件陣列基板 | |
US10802363B2 (en) | Array substrate and manufacturing method therefor, display device and driving method therefor | |
JP2007140458A (ja) | 液晶表示装置アレイ基板及びその製造方法 | |
TWI686647B (zh) | Tft基板、esd保護電路及tft基板的製作方法 | |
JP2003280016A (ja) | 液晶表示装置及びその製造方法 | |
CN107300813B (zh) | 阵列基板及液晶显示面板 | |
KR102059321B1 (ko) | 액정 디스플레이 장치와 이의 제조방법 | |
WO2015188540A1 (zh) | 阵列基板、显示装置及驱动方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |