CN105607368B - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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CN105607368B
CN105607368B CN201610006495.8A CN201610006495A CN105607368B CN 105607368 B CN105607368 B CN 105607368B CN 201610006495 A CN201610006495 A CN 201610006495A CN 105607368 B CN105607368 B CN 105607368B
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color
layer
forming
primary
array substrate
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CN105607368A (zh
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余道平
金熙哲
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BOE Technology Group Co Ltd
Chongqing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chongqing BOE Optoelectronics Technology Co Ltd
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Priority to CN201610006495.8A priority Critical patent/CN105607368B/zh
Publication of CN105607368A publication Critical patent/CN105607368A/zh
Priority to PCT/CN2016/096884 priority patent/WO2017118050A1/zh
Priority to US15/508,796 priority patent/US10126620B2/en
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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Abstract

本发明公开了一种阵列基板及其制备方法、显示装置，涉及显示领域，能够将彩膜制作于阵列基板上，且减少构图次数，降低成本。本发明的阵列基板制备方法，包括：薄膜晶体管和设置于所述薄膜晶体管之上的彩膜层，所述彩膜层包括：设置于像素区域的单基色色阻块和设置于遮光区域的多基色色阻块，所述单基色色阻块包括一种基色的色阻层，所述多基色色阻块包括多个层叠设置的色阻层，且每一色阻层对应一种基色。

Description

阵列基板及其制备方法、显示装置
技术领域
本发明涉及显示领域，尤其涉及一种阵列基板及其制备方法、显示装置。
背景技术
液晶显示器因其质量轻、功耗低，辐射小、能大量节省空间等优点，现已取代传统的阴极射线管显示器，广泛应用于各个显示领域，如家庭、公共场所、办公场及个人电子相关产品等。
现有液晶面板的制作工艺都是单独制造阵列(Array)基板和彩膜(Color Filter)基板，然后再将阵列基板和彩膜基板进行对位、成盒(Cell)。但在阵列基板与彩膜基板对位成盒时，由于对位精度的限制，极易出现对位偏差，而对位偏差又会导致漏光、透过率降低等不良；如果将黑矩阵做的足够宽来避免这些问题，又会损失面板的透过率，增加背光成本。
目前解决的办法是将彩膜也制作于阵列基板上，该项技术通常称为COA(ColorFilter On Array)。如图1所示，为现有采用COA技术的高级超维场转换(ADvanced SuperDimension Switch，简称ADS)模式的阵列基板的结构示意图。基板10上依次设置栅金属层11、栅绝缘层12、有源层13(半导体层)和源漏金属层14，以构成薄膜晶体管及信号线。薄膜晶体管之后，形成第一透明电极17和彩膜，其中，黑矩阵15设置在源漏金属层14之上，覆盖薄膜晶体管对应区域，彩膜层16(R/G/B)覆盖第一透明电极17。黑矩阵15及彩膜层16之上依次设置有机膜层18、钝化层19，钝化层19之上设置第二透明电极20。上述ADS模式的阵列基板结构，制造时需要的构图次数较多，工艺较复杂。
发明内容
本发明提供一种阵列基板及其制备方法、显示装置，能够将彩膜制作于阵列基板上，且减少构图次数，降低成本。
为达到上述目的，本发明的实施例采用如下技术方案：
一种阵列基板，包括：薄膜晶体管和设置于所述薄膜晶体管之上的彩膜层，所述彩膜层包括：设置于像素区域的单基色色阻块和设置于遮光区域的多基色色阻块，所述单基色色阻块包括一种基色的色阻层，所述多基色色阻块包括多个层叠设置的色阻层，且每一色阻层对应一种基色。
所述遮光区域包括薄膜晶体管的对应区域、数据线对应区域、栅线对应区域和阵列基板周边需要遮光的区域。
所述阵列基板还包括：第一透明电极，设置于所述彩膜层之下。
所述阵列基板，还包括：钝化层，位于所述第一透明电极所在层和所述彩膜层之间。
所述阵列基板还包括：第二透明电极，设置于所述彩膜层上。
所述阵列基板还包括：金属层，设置于所述第二透明电极所在层上；所述金属层包括：位于公共电极线上方非透光区域对应位置，并与所述公共电极线并联的第二公共电极线。
所述金属层还包括：位于数据线上方的第一遮蔽部。
所述金属层还包括：位于栅线上方的第二遮蔽部。
所述金属层还包括：与隔垫物对应的隔垫物枕。
本发明还提供一种显示装置，包括：任一项所述的阵列基板。
本发明还提供一种阵列基板的制备方法，包括：形成栅金属层的工序，所述栅金属层包括栅线和公共电极线；形成栅绝缘层及有源层的工序；形成源漏金属层的工序，所述源漏金属层包括源极、漏极和数据线；形成第一透明电极的工序；以及，形成钝化层的工序；在形成钝化层的工序之后，还包括：形成彩膜层的工序，所述彩膜层包括：设置于像素区域的单基色色阻块和设置于遮光区域的多基色色阻块，所述单基色色阻块包括一种基色的色阻层，所述多基色色阻块包括多个层叠设置的色阻层，且每一色阻层对应一种基色。
所述形成彩膜层的工序，包括：形成第一基色层，通过构图工艺在第一子像素区域形成第一厚度的色阻块，在遮光区域形成第二厚度的色阻块，所述第二厚度小于所述第一厚度；形成第二基色层，通过构图工艺在第二子像素区域形成第三厚度的色阻块，在遮光区域形成第四厚度的色阻块，所述第四厚度小于所述第三厚度；形成第三基色层，通过构图工艺在第三子像素区域形成第五厚度的色阻块，在遮光区域形成第六厚度的色阻块，所述第六厚度小于所述第五厚度。
所述形成彩膜层的工序中，在公共电极线与公共电极连接的对应位置还形成有贯穿所述彩膜层的过孔；形成所述彩膜层之后，还包括：以所述彩膜层为隔离保护层，对钝化层和栅绝缘层进行干刻，形成贯穿钝化层及栅绝缘层的过孔。
在形成彩膜层的工序之后，还包括：形成第二透明电极的工序。所述形成第二透明电极的工序，包括：沉积透明导电层和金属层；通过半透掩膜工艺，形成第二透明电极和图案化的金属层，所述图案化的金属层包括：位于公共电极线上方非透光区域对应位置，并与所述公共电极线并联的第二公共电极线。
本发明实施例提供的一种阵列基板制备方法和阵列基板、显示装置，将彩膜层设置在阵列基板上，所述彩膜层除包括设置于像素区域的单基色色阻层外，还在栅线、数据线及外围区域等遮光区域形成层叠设置的色阻层，利用多基色补色原理进行遮光，实现高对比度，并且本方案不需要特别的材料，能够采用常规工艺和材料实现COA技术，且可以省去黑矩阵层，减少构图次数，降低成本。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为现有采用COA技术的ADS阵列基板的结构示意图；
图2为本发明实施例提供的ADS阵列基板的结构示意图；
图3为本发明实施例提供的ADS阵列基板的制备方法流程图；
图4为本发明实施例提供的ADS模式阵列基板制备过程示意图；
图5为本发明实施例提供的ADS模式阵列基板中彩膜层制备过程示意图；
图6为本发明实施例提供IPS阵列基板的结构示意图。
附图标记
10-基板，11-栅金属层，12-栅绝缘层，13-有源层，14-源漏金属层，
17-第一透明电极，15-黑矩阵，16-彩膜层，17-第一透明电极，
18-有机膜层，19-钝化层，20-第二透明电极，30-基板，31-ITO，32-隔垫物。
具体实施方式
本发明实施例提供一种阵列基板制备方法和阵列基板、显示装置，能够将彩膜制作于阵列基板上，且减少构图次数，降低成本。
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
本发明实施例提供一种阵列基板，包括：薄膜晶体管和设置于所述薄膜晶体管之上的彩膜层，所述彩膜层包括：设置于像素区域的单基色色阻块和设置于遮光区域的多基色色阻块，所述单基色色阻块包括一种基色的色阻层，所述多基色色阻块包括多个层叠设置的色阻层，且每一色阻层对应一种基色。
本实施例中的彩膜层又成为显色层(现有技术中彩膜层形成于单独的基板，称彩色滤光片)，为液晶平面显示器彩色化之关键，因液晶平面显示器为非主动发光之组件，其色彩之显示必需内部的背光模块提供光源，再搭配驱动IC与液晶控制形成灰阶显示，然后透过而后透过彩膜层的R、G、B(红、绿、蓝)彩色层提供色相，形成彩色显示画面。本实施例提供的阵列基板，采用COA技术，将彩膜层也制作于阵列基板上，在基板形成薄膜晶体管之后，再形成彩膜层，彩膜层具体与阵列基板上各膜层间的位置关系本实施例不做限定，本领域技术人员可以根据实际情况进行设计。
一般而言，液晶显示装置多采用红、绿、蓝三基色的混色方案，即像素区域包括红、绿、蓝三个亚像素，当然实际应用时，并不限于此，还包括红绿蓝白(RGBW)，红绿蓝黄(RGBY)等混色方案。下面以红、绿、蓝三基色的混色方案为例对本实施例的彩膜层进行说明：彩膜层包括：位于像素区域的单基色色阻块，均由某一种基色的色阻层形成，例如红色阻块、绿色阻块和蓝色阻块(R、G、B)；除此之外，彩膜层还包括设置于遮光区域的多基色色阻块，该种多基色色阻块包括层叠设置的红色阻层、绿色阻层和蓝色阻层，由于红色阻层只允许红可见光通过，阻挡其余颜色的可见光，类似地，绿色阻层和蓝色阻层也只允许对应颜色的可见光通过，阻挡其余颜色的可见光，因此，当红、绿、蓝三种色阻层层叠在一起时，可以阻挡所有颜色的可见光，担当黑矩阵的遮光功能。上述遮光区域一般包括薄膜晶体管的对应区域、数据线对应区域、栅线对应区域和阵列基板周边需要遮光的区域。
本实施例阵列基板，不需要特别的材料，只需普通的色阻材料采用常规工艺即可实现COA技术，而且可以省去黑矩阵层，减少构图次数，降低成本。为了本领域技术人员更好的理解本发明实施例提供的阵列基板，下面通过具体的实施例对本发明提供的方案进行详细说明。
如图2所示，本实施例提供一种ADS(Advanced-Super Dimensional Switching，高级超维场开关技术)阵列基板，包括基板10、依次设置于基板10上的栅极金属层11、栅极绝缘层12、有源层13和源漏金属层14，栅极金属层11包括栅极、栅线和公共电极线111；然后形成第一透明电极17，第一透明电极分布在像素区域，为板式电极，通过搭接方式连接至薄膜晶体管的漏极；第一透明电极17之上依次形成钝化层19、彩膜层16和第二透明电极20，即钝化层19位于第一透明电极17所在层和彩膜层16之间，第二透明电极20设置于彩膜层16上。第二透明电极层20为狭缝电极。
上述彩膜层16包括位于像素区域的单基色色阻块，如红(R)色阻块、绿(G)色阻块和蓝(B)色阻块；除此之外，彩膜层还包括设置于遮光区域的多基色色阻块(见图2中的虚线框区域)，该种多基色色阻块包括层叠设置的红色阻层、绿色阻层和蓝色阻层，其中，遮光区域包括薄膜晶体管的对应区域、数据线对应区域、栅线对应区域和阵列基板周边需要遮光的区域。利用多基色补色原理进行遮光，实现高对比度，并且本方案不需要特别的材料，能够采用常规工艺和材料实现COA技术，且可以省去黑矩阵层，减少构图次数，降低成本。
另外，彩膜层16设置于第一透明电极17所在层和第二透明电极20所在层之间，而形成彩膜层16的色阻材料一般为绝缘有机材料，彩膜层16同时可以起到有机膜层的作用，因此本实施例可以省去有机膜层。
进一步地，上述阵列基板第二透明电极层上设置有一层金属层。优选地，制备时，金属层通过半透掩模工艺(HTM Mask)，通过一次构图工艺形成，金属层图形下方保留第二透明电极层。金属层图形存在多种设计，一种可选的方案为，金属层包括：位于公共电极线上方非透光区域对应位置，并与公共电极线并联的第二公共电极线，可以降低公共电极线上的电阻及因此导致的信号延迟。
另一种可选的方案为，金属层还可以以包括：位于数据线上方的第一遮蔽部。这部分区域的金属层(第一遮蔽部)位于两个像素的交界处，可以起到遮挡作用，防止漏光；另外，数据线上方使用透明导电层或金属层还可以屏蔽侧向电场，避免交界处的液晶紊乱形成的漏光，特别对曲面显示装置尤为重要。可选地，上述金属层还可进一步包括：位于栅线上方的第二遮蔽部，作用与第一遮蔽部相类似。考虑到金属层会增加电容负载，可根据功耗要求，灵活设置金属层形成第一、二遮蔽部。
另外，上述金属层还可包括：与隔垫物对应的隔垫物枕。上述金属层还可以在与隔垫物对应的位置保留，做为隔垫物的隔垫物枕使用。
综上，第二透明电极层上增设一层金属层，制备时可以使用半透掩模工艺一次完成，不需要增加工序；同时增设的金属层用途较多，具体设计时可以根据实际情况决定金属层保留位置。一般而言，金属层是否保留使用，主要看公共电极线的信号延迟情况及上基板的隔垫物设计情况来综合考量。所述金属层，降低第二透明电极电阻，还可以屏蔽漏光及形成段差以支撑不同高度的支撑隔离物。并在上述结构及工艺情况下，降低曝光次数。
本发明还提供一种ADS阵列基板的制备方法，如图3和图4所示，该方法包括：
101、形成栅金属层11的工序，所述栅金属层包括栅线和公共电极线111；
本步骤在基板上通过沉积\涂胶曝光\显影\刻蚀\剥离等步骤(第1次MASK)，形成包括栅极、栅线、公共电极线及其他功能图形的栅金属层11。
102、形成栅绝缘层12及有源层13的工序；
本步骤继续在基板上依次沉积栅绝缘层12和有源层13的膜层，本步骤中只进行成膜工序，不进行刻蚀，在下一工序中有源层13与源漏金属层14通过半透掩模工艺一次构图同步形成；当然，也可以选择在本步骤中对有源层13进行单独刻蚀。
103、形成源漏金属层14的工序；
本步骤通过沉积\涂胶曝光\显影\刻蚀\剥离等步骤(第2次MASK)，形成有源层13与源漏金属层14的图案，源漏金属层14的图案包括源极、漏极和数据线。
104、形成第一透明电极17的工序。
本步骤通过沉积\涂胶曝光\显影\刻蚀\剥离等步骤(第3次MASK)，形成第一透明电极17。
105、形成钝化层19的工序；本步骤只进行成膜工序，不进行刻蚀。
106、形成彩膜层16的工序，彩膜层16包括：设置于像素区域的单基色色阻块(R、G、B色阻块)和设置于遮光区域的多基色色阻块(如图中虚线框区域)，单基色色阻块包括一种基色的色阻层，多基色色阻块包括多个层叠设置的色阻层，且每一色阻层对应一种基色。对于通常的R、G、B三基色混色方案，本步骤一般共需要3次MASK(即第4、5、6次MASK)。
具体而言，如图5所示，形成彩膜层的工序包括：形成第一基色层(例如红阻块R)，通过构图工艺在第一子像素区域形成第一厚度的色阻块，在遮光区域形成第二厚度的色阻块，第二厚度小于第一厚度；形成第二基色层(例如绿阻块G)，通过构图工艺在第二子像素区域形成第三厚度的色阻块，在遮光区域形成第四厚度的色阻块，第四厚度小于第三厚度；形成第三基色层(例如蓝阻块B)，通过构图工艺在第三子像素区域形成第五厚度的色阻块，在遮光区域形成第六厚度的色阻块，第六厚度小于第五厚度。在遮光区域，所述第二、四、六厚度的色阻块复合在一起达成遮光效果，其中，优选地，第一厚、第三厚度和第五厚度的取值相等，第二厚、第四厚度和第六厚度的取值相等。上述构图工艺为半透掩膜工艺。
需要注意的是，在上述形成彩膜层的工序中，在公共电极与公共电极线连接的位置(即形成连接过孔的位置)不保留色阻。
107、以彩膜层16为隔离保护层，对钝化层19和栅绝缘层12进行干刻，在公共电极与公共电极线连接的位置形成贯穿钝化层19及栅绝缘层12的过孔。
本步骤直接以显色色阻(彩膜层16)为隔离物，进行钝化层19和栅绝缘层12干刻，将第一次构图中形成的公共电极线上的钝化层19和栅绝缘层12刻蚀掉形成过孔，以用于工序108中通过透明导电材料(第二透明电极层)将公共电极线引出。
108、形成第二透明电极20的工序。
本步骤通过沉积\涂胶曝光\显影\刻蚀\剥离等步骤(第7次MASK)，形成第二透明电极20。
优选地，本步骤还可以同步在第二透明电极20所在层上形成金属层，金属层可以设计位于公共电极线上方非透光区域对应位置，并与所述公共电极线并联的第二公共电极线；和/或，位于数据线上方的第一遮蔽部；和/或，位于栅线上方的第二遮蔽部，和/或，与隔垫物对应的隔垫物枕(通常位于栅线的对应区域)。具体而言，所述形成第二透明电极的工序，包括：沉积透明导电层和金属层；通过半透掩膜工艺，形成第二电极和图案化的金属层，所述图案化的金属层可包括：位于公共电极线上方非透光区域对应位置，并与所述公共电极线并联的第二公共电极线；还可包括位于数据线上方的第一遮蔽部；和/或，位于栅线上方的第二遮蔽部，和/或，与隔垫物对应的隔垫物枕(通常位于栅线的对应区域)。
如图6所示，本发明还提供一种IPS(In-Plane Switching,平面转换)阵列基板的结构和制备方法，与前面所述阵列基板的结构和制备方法类似，具体如图6所示，区别仅在上述101～108工艺方法中进行工艺变更，包括：不进行形成第一透明电极的工序(步骤104)；在形成第二透明电极20的工序(步骤108)中，同步形成像素电极和公共电极(即图6中的第一透明电极17和第二透明电极20)，像素电极和公共电极均为梳齿状电极，二者的梳齿状电极交叉呈咬合配置(电极间隔一定的距离，形成空间平面电场)，像素电极通过过孔和数据线连接，公共电极通过过孔和底层的公共引线连接，可以省去1次mask，这样通过6mask可达成IPS COA结构。
以上为本实施例提供的阵列基板的制作工艺，不需要特殊材料，使用常规色阻材料，只需7MASK即可形成能实现COA技术的阵列基板，可以省去黑矩阵和有机膜层的工序，降低MASK次数，从而降低了产品成本。同时，通过在第二透明电极层上设置金属层，以形成第二公共电极线和遮挡部，可以降低公共电极的阻值，并在数据线上形成屏蔽部起到屏蔽侧向电场作用，解决漏光；并且金属层可以作为隔垫物(Triple PS)的隔垫物枕(pillow)，对应的不同高度的支撑隔离物。
在第二基板(与上述阵列基板对盒的基板)，如图2所示，在基板30上先制作薄层ITO 31，一来屏蔽ADS结构稳定性的外来电场，而来保证隔垫物PS的粘附性；然后在ITO层上制作常规材料的隔垫物(PS)32。另外，对于第二基板，还可以在第二基板背面上制作透明导电屏蔽层，基板正面(面向阵列基板的一侧)制作不同高度的支撑隔离物。
第二基板与阵列基板对盒后，完整的COA工艺完成，整个液晶盒阶段只需8～9次MASK。有的现有技术中，黑矩阵形成于对盒基板侧，采用特殊材料(同时满足黑矩阵和隔垫物对材料的要求)制作BPS，同时实现黑矩阵和隔垫物的功能，而同时满足遮光和隔垫物弹性要求的材料比较难以寻找，增加了成本。而本实施例则只需色阻材料，降低了成本。
本发明实施例还提供一种显示装置，其包括上述任意一种阵列基板。所述显示装置，成本低，高解析度，并解决了ADS/IPS漏光问题，所述显示装置可以为：液晶面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
需要注意的是，本发明虽然以ADS/IPS模式的阵列基板为例，但仅是为描述方面而进行的示例，并不用于限定。本发明还可以应用于其它结构的阵列基板及显示器上。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于设备实施例而言，由于其基本相似于方法实施例，所以描述得比较简单，相关之处参见方法实施例的部分说明即可。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。

Claims (8)

1.一种阵列基板，包括：薄膜晶体管和设置于所述薄膜晶体管之上的彩膜层，其特征在于，
所述彩膜层包括：设置于像素区域的单基色色阻块和设置于遮光区域的多基色色阻块，所述单基色色阻块包括一种基色的色阻层，所述多基色色阻块包括多个层叠设置的色阻层，且每一色阻层对应一种基色；
所述阵列基板还包括：第二透明电极，设置于所述彩膜层上；金属层，设置于所述第二透明电极所在层之上；
所述金属层包括：位于公共电极线上方非透光区域对应位置，并与所述公共电极线并联的第二公共电极线；位于数据线上方的第一遮蔽部；以及位于栅线上方的第二遮蔽部；
所述金属层还包括：与隔垫物对应的隔垫物枕。
2.根据权利要求1所述的阵列基板，其特征在于，所述遮光区域包括薄膜晶体管的对应区域、数据线对应区域、栅线对应区域和阵列基板周边需要遮光的区域。
3.根据权利要求1所述的阵列基板，其特征在于，还包括：第一透明电极，设置于所述彩膜层之下。
4.根据权利要求3所述的阵列基板，其特征在于，还包括：钝化层，位于所述第一透明电极所在层和所述彩膜层之间。
5.一种显示装置，其特征在于，包括：权利要求1-4任一项所述的阵列基板。
6.一种阵列基板的制备方法，包括：形成栅金属层的工序，所述栅金属层包括栅线和公共电极线；形成栅绝缘层及有源层的工序；形成源漏金属层的工序，所述源漏金属层包括源极、漏极和数据线；形成第一透明电极的工序；以及，形成钝化层的工序；其特征在于，在形成钝化层的工序之后，还包括：
形成彩膜层的工序，所述彩膜层包括：设置于像素区域的单基色色阻块和设置于遮光区域的多基色色阻块，所述单基色色阻块包括一种基色的色阻层，所述多基色色阻块包括多个层叠设置的色阻层，且每一色阻层对应一种基色；
在形成彩膜层的工序之后，还包括：形成第二透明电极的工序；
所述形成第二透明电极的工序，包括：
沉积透明导电层和金属层；
通过半透掩膜工艺，形成第二透明电极和图案化的金属层，所述图案化的金属层包括：位于公共电极线上方非透光区域对应位置，并与所述公共电极线并联的第二公共电极线；位于数据线上方的第一遮蔽部；位于栅线上方的第二遮蔽部；以及，与隔垫物对应的隔垫物枕。
7.根据权利要求6所述的制备方法，其特征在于，所述形成彩膜层的工序，包括：
形成第一基色层，通过构图工艺在第一子像素区域形成第一厚度的色阻块，在遮光区域形成第二厚度的色阻块，所述第二厚度小于所述第一厚度；
形成第二基色层，通过构图工艺在第二子像素区域形成第三厚度的色阻块，在遮光区域形成第四厚度的色阻块，所述第四厚度小于所述第三厚度；
形成第三基色层，通过构图工艺在第三子像素区域形成第五厚度的色阻块，在遮光区域形成第六厚度的色阻块，所述第六厚度小于所述第五厚度。
8.根据权利要求6或7所述的制备方法，其特征在于，所述形成彩膜层的工序中，在公共电极线与公共电极连接的对应位置还形成有贯穿所述彩膜层的过孔；形成所述彩膜层之后，还包括：
以所述彩膜层为隔离保护层，对钝化层和栅绝缘层进行干刻，在公共电极线与公共电极连接的对应位置形成贯穿钝化层及栅绝缘层的过孔。
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CN105607368A (zh) 2016-05-25

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