WO2017118050A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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WO2017118050A1
WO2017118050A1 PCT/CN2016/096884 CN2016096884W WO2017118050A1 WO 2017118050 A1 WO2017118050 A1 WO 2017118050A1 CN 2016096884 W CN2016096884 W CN 2016096884W WO 2017118050 A1 WO2017118050 A1 WO 2017118050A1
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Prior art keywords
layer
color
forming
common electrode
array substrate
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PCT/CN2016/096884
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English (en)
French (fr)
Inventor
余道平
金熙哲
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京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Priority to US15/508,796 priority Critical patent/US10126620B2/en
Publication of WO2017118050A1 publication Critical patent/WO2017118050A1/zh

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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device.
  • liquid crystal displays Due to its light weight, low power consumption, low radiation, and large space saving, liquid crystal displays are widely used in various display fields, such as computers, mobile phones, televisions and other electronic products.
  • the manufacturing process of the liquid crystal panel is to separately manufacture an array substrate and a color filter substrate, and then align the array substrate and the color filter substrate into a cell.
  • the alignment deviation is likely to occur, and the alignment deviation may cause leakage, low transmittance, etc.; if the black matrix is used Wide enough to avoid these problems, which will reduce the transmittance of the panel and increase the cost of backlighting.
  • FIG. 1 is a schematic structural diagram of an array substrate of an Advanced Super Dimension Switch (ADS) mode using COA technology.
  • a gate metal layer 11, a gate insulating layer 12, an active layer 13 (semiconductor layer), and a source/drain metal layer 14 are sequentially disposed on the base substrate 10 to constitute a thin film transistor and a signal line.
  • a black matrix 15, a color filter layer 16, and a first transparent electrode 17 are disposed on the thin film transistor, wherein the black matrix 15 is disposed on the source/drain metal layer 14 to cover a region corresponding to the thin film transistor.
  • the organic film layer 18 and the passivation layer 19 are sequentially disposed on the black matrix 15 and the first transparent electrode 17, and the second transparent electrode 20 is disposed on the passivation layer 19.
  • the array substrate structure of the ADS mode described above requires a large number of patterning processes and a complicated process.
  • Embodiments of the present invention provide an array substrate, a method for fabricating the same, and a display device.
  • a color film can be fabricated on an array substrate, and the number of patterning can be reduced, and the production cost can be reduced.
  • At least one embodiment of the present invention provides an array substrate including: a substrate substrate, gate lines, data lines disposed on the substrate substrate, the gate lines and the data lines crossing defining pixels a thin film transistor is disposed in the pixel region; a color film layer is disposed on the thin film transistor; wherein the color film layer includes: a single primary color block disposed in the pixel region and disposed in the light blocking region
  • the multi-primary color block includes a color resist layer of a primary color, and the multi-primary color block comprises a plurality of stacked color resist layers to block light.
  • the light shielding region includes a region corresponding to the thin film transistor, a region corresponding to the gate line, a region corresponding to the data line, and a peripheral portion of the array substrate. Shaded area.
  • an array substrate further includes: a first transparent electrode disposed under the color film layer.
  • an array substrate further includes: a passivation layer disposed between the first transparent electrode and the color film layer.
  • an array substrate further includes: a second transparent electrode disposed on the color film layer.
  • an array substrate provided by an embodiment of the present invention further includes a metal layer disposed on the second transparent electrode, wherein the metal layer includes: a position corresponding to a non-transmissive region above the common electrode line a second common electrode line at and in parallel with the common electrode line.
  • the metal layer further includes: a first shielding portion located above the data line.
  • the metal layer further includes: a second shielding portion located above the gate line.
  • a spacer is further disposed on the metal layer, and the metal layer further includes a spacer pillow corresponding to the spacer.
  • an array substrate further includes: a pixel electrode and a common electrode disposed on the color filter layer, wherein the pixel electrode and the common electrode are both comb-shaped electrodes, The pixel electrode is interdigitated with the comb-shaped electrode of the common electrode, the pixel electrode is connected to the drain of the thin film transistor through a third via, and the common electrode passes through the fourth via and the common electrode line connection.
  • At least one embodiment of the present invention also provides a display device comprising: the array substrate described above.
  • At least one embodiment of the present invention also provides a method of fabricating an array substrate, comprising: providing a substrate; forming gate lines, data lines, and common electrode lines on the substrate, wherein And forming a thin film transistor in the pixel region; forming a color film layer on the thin film transistor, wherein forming the color film layer comprises: forming in the pixel region a single primary color block and a multi-primary color block formed in the light-shielding region, the single-primary color block comprising a primary color resist layer, the multi-primary color block comprising a plurality of stacked color resist layers Block light.
  • the pixel region includes a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region.
  • the forming the color film layer further includes: forming a first primary color layer, the first primary color layer including a color block having a first thickness and having a second thickness a color blocking block, wherein the first thickness of the color block is formed in the first sub-pixel region by a patterning process, and the second thickness of the color block is formed in the light-shielding region, the second thickness Less than the first thickness.
  • the forming the color film layer further includes: forming a second primary color layer, the second primary color layer including a color block having a third thickness and having a fourth thickness a color blocking block, wherein the third thickness of the color block is formed in the second sub-pixel region by a patterning process, and the fourth thickness of the color block is formed in the light shielding region, wherein the fourth thickness is smaller than the The third thickness.
  • the forming the color film layer further includes: forming a third primary color layer, the third primary color layer including a color block having a fifth thickness and having a sixth thickness a color blocking block, wherein the fifth thickness of the color block is formed in the third sub-pixel region by a patterning process, and the sixth thickness of the color block is formed in the light shielding region, wherein the sixth thickness is smaller than the Fifth thickness.
  • the forming the first transparent electrode comprises: depositing a transparent conductive layer film, A photoresist is coated on the transparent conductive layer film, and then the first transparent electrode is formed by exposing, developing, etching, and stripping the photoresist.
  • the method before the forming the first transparent electrode, the method further includes a process of forming a gate insulating layer; and/or after forming the first transparent electrode and The method further includes the step of forming a passivation layer before forming the color film layer.
  • the method further includes: a process of forming a second transparent electrode and a metal layer, and forming the second The transparent electrode and the metal layer include: depositing a transparent conductive layer film and a metal layer film; patterning the transparent conductive layer film and the metal layer film by a halftone mask process to form the second transparent electrode And the metal layer.
  • the metal layer includes: a second common electrode line located at a corresponding position of the non-transmissive region above the common electrode line and connected in parallel with the common electrode line.
  • the common electrode line is connected to the common electrode, and in the process of forming the color film layer, the method further includes: at a corresponding position where the common electrode line is connected to the common electrode A first via hole penetrating the color film layer is formed.
  • the method further includes: using the color film layer as an isolation protection layer, and performing the passivation layer and the gate insulating layer Dry etching, forming a second via hole penetrating the passivation layer and the gate insulating layer at a corresponding position where the common electrode line is connected to the common electrode.
  • the method further includes: forming a pixel electrode and a common electrode, wherein the pixel electrode and the common electrode are comb-shaped electrodes, The pixel electrode is interdigitated with the comb-shaped electrode of the common electrode, the pixel electrode is connected to the drain of the thin film transistor through a third via, and the common electrode passes through the fourth via and the common electrode Wire connection.
  • FIG. 1 is a schematic structural view of an ADS array substrate using COA technology
  • FIG. 2 is a schematic structural diagram of an ADS array substrate according to an embodiment of the present invention.
  • FIG. 2a is a schematic diagram showing a planar structure of an ADS array substrate according to an embodiment of the present invention
  • FIG. 3 is a flowchart of a method for preparing an ADS array substrate according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of a process for preparing an ADS mode array substrate according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of a process for preparing a color film layer in an ADS mode array substrate according to an embodiment of the present invention
  • FIG. 6 is a schematic structural diagram of an IPS array substrate according to an embodiment of the present invention.
  • 10-substrate substrate 11-gate metal layer, 111-common electrode line, 112-second common electrode line, 12-gate insulating layer, 13-active layer, 14-source drain metal layer, 141-drain, 15-black matrix, 16-color film layer, 17-first transparent electrode, 18-organic film layer, 19-passivation layer, 20-second transparent electrode, 30-second substrate, 31-ITO film layer, 32 - spacers; 41-pixel electrodes; 42-common electrodes, 43-thin film transistors, 44-gate lines, 45-data lines, 46-first shielding portions, 47-second shielding portions, 48-light-shielding regions.
  • the embodiment of the invention provides an array substrate, a preparation method thereof, and a display device.
  • the color film can be fabricated on the array substrate, thereby reducing the number of patterning and reducing the production cost.
  • An array substrate provided by an embodiment of the present invention includes: a substrate substrate, a gate line and a data line disposed on the base substrate, wherein the gate line and the data line intersect to define a pixel area; a thin film transistor is disposed in the pixel area; and the thin film transistor a color film layer is disposed on the color film layer; the color film layer includes: a single primary color block disposed in the pixel region; and a multi-primary color block disposed in the light-shielding region, wherein the single-primary color block includes a primary color resist layer
  • the multi-primary color block includes a plurality of stacked color resist layers to block light.
  • the color film layer in this embodiment is also called a color developing layer (the color film layer currently formed on a separate substrate is called a color filter), which is the key to colorization of the liquid crystal display because the liquid crystal display is inactive light.
  • the component must display the color by the internal backlight module, and then form a gray scale display with the driver IC and the liquid crystal control, and then provide the hue through the R, G, B (red, green, blue) color layers of the color film layer. , forming a color display screen.
  • the color film layer is also formed on the array substrate by using the COA technology, and after the thin film transistor is formed on the substrate, the color film layer is formed, and the color film layer and the film layer on the array substrate are formed.
  • the positional relationship is not limited in this embodiment, and those skilled in the art can design according to actual conditions.
  • a color mixing scheme of three primary colors of red, green, and blue is used, that is, a pixel region includes three sub-pixels of red, green, and blue, and of course, the actual application is not limited thereto, and includes Red, green, blue and white (RGBW), red, green, blue and yellow (RGBY) and other color mixing schemes.
  • RGBW Red, green, blue and white
  • RGBY red, green, blue and yellow
  • the color film layer of the present embodiment is described by taking a color mixing scheme of three primary colors of red, green, and blue as an example.
  • the color film layer includes: a single primary color blocking block located in a pixel region, and each of the color resisting layers of a primary color Forming, for example, a red block, a green block, and a blue block (R, G, B); in addition, the color film layer further includes a multi-primary color block disposed in the light-shielding region, the multi-primary color resist
  • the block includes a red resist layer, a green resist layer and a blue resist layer which are arranged in a stack. Since the red resist layer only allows red visible light to pass, blocking visible light of the remaining colors, similarly, the green resist layer and the blue resist layer only allow corresponding colors. The visible light passes through and blocks the visible light of the remaining colors.
  • the light-shielding region 48 generally includes a corresponding region of the thin film transistor 43, a corresponding region of the data line 45, a corresponding region of the gate line 44, and a region where the periphery of the array substrate needs to be shielded from light.
  • the color film layer does not need special materials, and the conventional color processing material can realize the COA technology by using a conventional process, and the black matrix layer can be omitted, the number of patterning is reduced, and the production cost is reduced.
  • the solution provided by the present invention will be described in detail below.
  • FIG. 2 is an array substrate of an ADS (Advanced-Super Dimensional Switching) mode, which includes a base substrate 10 and a grid disposed on the base substrate 10.
  • a line (disposed in the gate metal layer 11), a data line (not shown), and a common electrode line 111 disposed in the same layer as the gate line, wherein the gate line and the data line intersect to define a pixel area;
  • a film is disposed in the pixel area a color film layer 16 is disposed on the thin film transistor;
  • the color film layer 16 includes: a single primary color blocking block disposed in the pixel region; and a multi-primary color blocking block disposed in the light shielding region, the single primary color blocking block includes a A primary color resist layer, the multi-primary color block comprises a plurality of stacked color resist layers to block light.
  • the array substrate further includes: a gate metal layer 11 sequentially disposed on the base substrate 10, a gate insulating layer 12, an active layer 13, and a source/drain metal layer 14.
  • the gate metal layer 11 includes a gate, a gate line, and a common electrode line 111; then a first transparent electrode 17 is formed, the first transparent electrode 17 is distributed in the pixel region, is a plate electrode, is connected to the drain of the thin film transistor by a lap joint; and is formed bluntly on the first transparent electrode 17
  • the layer 19, the color film layer 16 and the second transparent electrode 20, that is, the passivation layer 19 are located between the layer of the first transparent electrode 17 and the color film layer 16, and the second transparent electrode 20 is disposed on the color film layer 16.
  • the second transparent electrode layer 20 is a slit electrode.
  • the color film layer 16 includes a single primary color block in the pixel region, such as a red (R) color block, a green (G) color block, and a blue (B) color block; in addition, the color film layer is further A multi-primary color block (see the dotted frame area in FIG. 2) disposed in the light-shielding region, the multi-primary color block includes a red resist layer, a green resist layer and a blue resist layer, wherein the light-shielding region is disposed The corresponding area of the thin film transistor, the corresponding area of the data line, the corresponding area of the gate line, and the area where the periphery of the array substrate needs to be shielded.
  • the multi-primary complementary color principle is used for shading to achieve high contrast, and the solution does not require special materials, and can implement COA technology by using conventional processes and materials, and can eliminate the black matrix layer, reduce the number of patterning, and reduce the cost.
  • the color film layer 16 is disposed between the layer where the first transparent electrode 17 is located and the layer where the second transparent electrode 20 is located, and the color resist material forming the color film layer 16 is generally an insulating organic material, and the color film layer 16 can simultaneously The role of the organic film layer, and thus the organic film layer can be omitted in this embodiment.
  • a second metal layer (not shown) is disposed on the second transparent electrode layer 20 in the array substrate.
  • the metal layer is formed by a patterning process by a half mask process (HTM Mask), and the second transparent electrode layer 20 is left under the metal layer pattern.
  • HTM Mask half mask process
  • the metal layer pattern includes: a second common electrode line 112 located at a corresponding position of the non-transmissive region above the common electrode line and connected in parallel with the common electrode line, which can lower the common electrode The resistance on the line and the resulting signal delay.
  • the metal layer may further include: a first shielding portion 46 located above the data line 45.
  • the metal layer (the first shielding portion 46) of the partial region is located at the boundary of the two pixels, and can block the light to prevent light leakage; in addition, the transparent conductive layer or the metal layer can be used to shield the lateral direction above the data line 45.
  • the electric field avoids light leakage caused by liquid crystal turbulence at the junction, which is especially important for curved display devices.
  • the metal layer may further include: a second shielding portion 47 located above the gate line 44, which functions similarly to the first shielding portion 46. Considering that the metal layer increases the capacitive load, the metal layer can be flexibly set to form the first and second shielding portions according to the power consumption requirement.
  • the metal layer may further include: a spacer pillow corresponding to the spacer 32.
  • the metal layer may also be retained at a position corresponding to the spacer 32 as a spacer for the spacer 32.
  • a metal layer is added on the second transparent electrode layer 20, which can be completed in one time by using a semi-transparent mask process, without adding an additional process; at the same time, the added metal layer has many uses, and the specific design can be based on actual conditions.
  • the situation determines where the metal layer remains. Whether the metal layer is reserved or not depends mainly on the signal delay of the common electrode line and the design of the spacer on the upper substrate.
  • the metal layer can reduce the resistance of the second transparent electrode, and can also shield the light leakage and form a step to support the supporting spacers of different heights. In the above structure and process, the number of exposures is reduced.
  • An embodiment of the present invention further provides a method for preparing an ADS array substrate, as shown in FIG. 3 and FIG. 4, the method includes:
  • the process is: forming a gate metal layer including a gate electrode, a gate line, a common electrode line, and other functional patterns on a substrate by a step of deposition, glue exposure, development, etching, and lift-off (first MASK). 11.
  • the process continues to deposit the gate insulating layer 12 and the active layer 13 sequentially on the substrate. In this step, only the film forming process is performed, and etching is not performed. In the next process, the active layer 13 and the source/drain metal layer 14 pass through the semi-transparent mask. The patterning process is formed in one pattern synchronously; of course, the active layer 13 may be separately etched in this step.
  • a pattern of the active layer 13 and the source/drain metal layer 14 is formed by a deposition/coating exposure/development/etching/peeling step (2nd MASK), and the pattern of the source/drain metal layer 14 includes a source and a drain. Pole and data lines.
  • the first transparent electrode 17 is formed by a deposition/coating exposure/development/etching/peeling step (3rd MASK).
  • the color film layer 16 includes: a single primary color block (R, G, B color block) disposed in the pixel region and a multi-primary color block disposed in the light blocking region (as shown in the figure)
  • the single primary color block includes a color resist layer of a primary color
  • the multi-primary color block includes a plurality of stacked color resist layers, and each of the resist layers corresponds to a primary color.
  • this step generally requires 3 MASKs (ie, 4th, 5th, and 6th MASK).
  • the pixel region includes a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region.
  • the process of forming a color film layer includes: forming a first primary color layer (for example, a red block R), and forming a first-thick color block in the first sub-pixel region by a patterning process, in the light-shielding region Forming a color block of a second thickness, the second thickness being less than the first thickness; forming a second primary color layer (eg, a green blocking block G), forming a third-thick color blocking block in the second sub-pixel region by a patterning process, forming a fourth-thick color blocking block in the light-shielding region, the fourth thickness being less than the third thickness; forming the third primary color layer ( For example, the blue block B) forms a fifth-thick color block in the third sub-pixel region by a patterning process, and forms a sixth-thick color block in the light-shielding region, and the sixth thickness is smaller than the fifth thickness.
  • a first primary color layer for example, a red block R
  • the second, fourth, and sixth thickness color block blocks are combined to achieve a light-shielding effect, wherein the first thickness, the third thickness, and the fifth thickness are equal, and the second thickness, the fourth thickness, and the sixth The thicknesses are equal.
  • the above patterning process is a semi-transparent mask process.
  • the color resistance is not retained at the position where the common electrode is connected to the common electrode line (that is, the position at which the first via hole is formed).
  • the color filter layer 16 is used as an isolation protection layer, and the passivation layer 19 and the gate insulating layer 12 are dry-etched, and a second pass through the passivation layer 19 and the gate insulating layer 12 is formed at a position where the common electrode and the common electrode line are connected. Through hole.
  • the passivation layer 19 and the gate insulating layer 12 are dry-etched directly with the color-developing color resist (color film layer 16) as a spacer, and the passivation layer 19 and the gate on the common electrode line formed in the first patterning are performed.
  • the insulating layer 12 is etched away to form a second via for the common electrode line to be drawn through the transparent conductive material (second transparent electrode layer) in the process 108.
  • a step of forming the second transparent electrode 20 is a step of forming the second transparent electrode 20.
  • the second transparent electrode 20 is formed by a deposition/coating exposure/development/etching/peeling step (7th MASK).
  • a metal layer may be formed on the layer where the second transparent electrode 20 is located, and the metal layer includes a second common electrode line 112 located at a position corresponding to the non-transmissive region above the common electrode line and connected in parallel with the common electrode line. And/or a first shielding portion located above the data line; and/or a second shielding portion located above the gate line, and/or a spacer pillow corresponding to the spacer (usually located in the grid line) region).
  • a process of forming a second transparent electrode includes: depositing a transparent conductive layer and a metal layer; forming a second electrode and a patterned metal layer by a semi-transparent mask process, and the patterned metal layer may include: located at a common electrode line a second common electrode line 112 corresponding to the position of the upper non-transmissive region and in parallel with the common electrode line; may further include a first shielding portion located above the data line; and/or a second shielding portion located above the gate line, and / or, a spacer pillow corresponding to the spacer (usually located in the corresponding area of the grid line).
  • the above manufacturing process of the ADS array substrate provided by the embodiment does not require special materials, and the conventional color resist material can be used to form an array substrate capable of realizing COA technology by only 7MASK.
  • the process of eliminating the black matrix and the organic film layer reduces the number of MASK times, thereby reducing the production cost.
  • the resistance value of the common electrode can be reduced, and the shielding portion is formed on the data line to shield the lateral electric field and solve the problem.
  • Light leakage; and the metal layer can act as a spacer for the Triple PS, corresponding to different heights of the support spacer.
  • the ITO film layer 31 is formed on the second substrate 30 to shield the external electric field of the ADS structural stability, and also to ensure the adhesion of the spacer PS; then, the ITO film layer 31 is conventionally fabricated.
  • Material spacer (PS) 32 As shown in FIG. 2, the ITO film layer 31 is formed on the second substrate 30 to shield the external electric field of the ADS structural stability, and also to ensure the adhesion of the spacer PS; then, the ITO film layer 31 is conventionally fabricated.
  • Material spacer (PS) 32 material spacer
  • a transparent conductive shield layer may be formed on the back surface of the second substrate 30, and support spacers of different heights may be formed on the front surface (the side facing the array substrate) of the second substrate 30.
  • the complete COA process is completed, and only 8-9 times of MASK is required for the entire liquid crystal cell stage.
  • the black matrix is formed on the side of the counter substrate, and the special material (while satisfying the requirements of the black matrix and the spacer for the material) is used to fabricate the BPS, and at the same time realize the functions of the black matrix and the spacer, while satisfying the shading and the spacer. Materials that require elasticity are more difficult to find and increase costs. In this embodiment, only the color resist material is needed, which reduces the production cost.
  • the embodiment of the present invention further provides an IPS (In-Plane Switching) mode array substrate structure and a preparation method thereof, which are similar to the structure and preparation method of the ADS array substrate described above.
  • the difference is only the process change in the above-mentioned 101-108 process method, the process of forming the first transparent electrode is not performed in the formation process of the IPS array substrate (step 104);
  • the pixel electrode 41 and the common electrode 42 are formed in synchronization, and the pixel electrode 41 and the common electrode 42 are comb-shaped electrodes, and the comb-shaped electrodes of the two are in a occlusal arrangement (the electrode spacing is constant) a distance, forming a spatial plane electric field), the pixel electrode 41 is connected to the drain 141 of the thin film transistor through the third via hole, and the common electrode 42 is connected to the common electrode line through the fourth via hole, so that the mask can be omitted once, so that 6mas
  • the conventional color resist material can be used to form an array substrate capable of realizing COA technology by 6MASK, which can eliminate the process of black matrix and organic film layer, and reduce MASK. The number of times, thereby reducing production costs.
  • 6MASK realizing COA technology
  • the metal layer can be used as a spacer for the Triple PS, corresponding to different heights. Degree of support spacers.
  • the ITO film layer 31 is formed on the second substrate 30 to shield the external electric field of the IPS structure stability, and also to ensure the adhesion of the spacer PS; then, the ITO film layer 31 is conventionally fabricated.
  • Material spacer (PS) 32 Further, for the second substrate 30, a transparent conductive shielding layer may be formed on the back surface of the second substrate 30, and the front surface of the second substrate 30 (the side facing the array substrate) may be formed with support spacers of different heights.
  • the complete COA process is completed, and only 7-8 times of MASK is required for the entire liquid crystal cell stage.
  • the black matrix is formed on the side of the counter substrate, and the special material (while satisfying the requirements of the black matrix and the spacer for the material) is used to fabricate the BPS, and at the same time realize the functions of the black matrix and the spacer, while satisfying the shading and the spacer. Materials that require elasticity are more difficult to find and increase costs. In this embodiment, only the color resist material is needed, which reduces the production cost.
  • the embodiment of the invention further provides a display device comprising any of the above array substrates.
  • the display device has the advantages of low cost, high resolution, and solves the problem of ADS/IPS light leakage.
  • the display device can be: a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, Any product or part that has a display function, such as a navigator.
  • An embodiment of the present invention provides an array substrate manufacturing method, an array substrate, and a display device.
  • the color film layer is disposed on an array substrate, and the color film layer includes a single primary color resist layer disposed in the pixel region.
  • the light-shielding regions such as the gate lines, the data lines, and the peripheral regions form a stacked color resist layer, which is shielded by the multi-primary complementary color principle to achieve high contrast, and the present scheme does not require special materials, and the COA technology can be realized by using conventional processes and materials.
  • the black matrix layer can be omitted, the number of patterning is reduced, and the cost is reduced.

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Abstract

一种阵列基板及其制备方法、显示装置。该阵列基板包括：衬底基板（10），设置在所述衬底基板（10）上的栅线（44）、数据线（45），其中，所述栅线（44）和所述数据线（45）交叉限定像素区域；所述像素区域内设置有薄膜晶体管（43）；所述薄膜晶体管（43）上设置有彩膜层（16）；所述彩膜层（16）包括：设置于所述像素区域内的单基色色阻块（R、G、B）和设置于遮光区域内的多基色色阻块，所述单基色色阻块（R、G、B）包括一种基色的色阻层，所述多基色色阻块包括多个层叠设置的色阻层以遮挡光线，由此能够将彩膜制作于阵列基板上，减少了构图次数，降低了生产成本。

Description

阵列基板及其制备方法、显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制备方法、显示装置。
背景技术
液晶显示器因其质量轻、功耗低，辐射小、能大量节省空间等优点，广泛地应用于各个显示领域，例如电脑、手机、电视等电子产品中。
目前，液晶面板的制作工艺都是单独制造阵列(Array)基板和彩膜(Color Filter)基板，然后再将阵列基板和彩膜基板进行对位、成盒(Cell)。但在阵列基板与彩膜基板对位成盒时，由于对位精度的限制，极易出现对位偏差，而对位偏差又会导致漏光、透过率降低等不良；如果将黑矩阵做的足够宽来避免这些问题，又会降低面板的透过率，增加背光成本。
目前，解决上述问题的办法是将彩膜也制作于阵列基板上，该项技术通常称为COA(Color Filter On Array)。如图1所示，为一种采用COA技术的高级超维场转换(ADvanced Super Dimension Switch，简称ADS)模式的阵列基板的结构示意图。衬底基板10上依次设置栅金属层11、栅绝缘层12、有源层13(半导体层)和源漏金属层14，以构成薄膜晶体管及信号线。在薄膜晶体管上设置有黑矩阵15、彩膜层16和第一透明电极17，其中，黑矩阵15设置在源漏金属层14上，覆盖薄膜晶体管对应的区域。黑矩阵15及第一透明电极17之上依次设置有机膜层18、钝化层19，钝化层19之上设置第二透明电极20。上述ADS模式的阵列基板结构，制造时需要的构图次数较多，工艺较复杂。
发明内容
本发明的实施例提供了一种阵列基板及其制备方法、显示装置，在本发明的实施例中，能够将彩膜制作于阵列基板上，且能够减少构图的次数，降低生产成本。
本发明的至少一个实施例提供了一种阵列基板，其包括：衬底基板，设置在所述衬底基板上的栅线、数据线，所述栅线和所述数据线交叉限定像素 区域；所述像素区域内设置有薄膜晶体管；所述薄膜晶体管上设置有彩膜层；其中，所述彩膜层包括：设置于所述像素区域内的单基色色阻块和设置于遮光区域内的多基色色阻块，所述单基色色阻块包括一种基色的色阻层，所述多基色色阻块包括多个层叠设置的色阻层以遮挡光线。
例如，在本发明一实施例提供的阵列基板中，所述遮光区域包括所述薄膜晶体管对应的区域、所述栅线对应的区域、所述数据线对应的区域和所述阵列基板的周边需要遮光的区域。
例如，本发明一实施例提供的阵列基板，还包括：设置于所述彩膜层下的第一透明电极。
例如，本发明一实施例提供的阵列基板，还包括：设置于所述第一透明电极和所述彩膜层之间的钝化层。
例如，本发明一实施例提供的阵列基板，还包括：设置于所述彩膜层之上的第二透明电极。
例如，本发明一实施例提供的阵列基板，还包括设置于所述第二透明电极之上的金属层，其中，所述金属层包括：位于所述公共电极线上方非透光区域对应的位置处并与所述公共电极线并联的第二公共电极线。
例如，在本发明一实施例提供的阵列基板中，所述金属层还包括：位于所述数据线上方的第一遮蔽部。
例如，在本发明一实施例提供的阵列基板中，所述金属层还包括：位于所述栅线上方的第二遮蔽部。
例如，在本发明一实施例提供的阵列基板中，所述金属层上还设置有隔垫物，所述金属层还包括与所述隔垫物对应的隔垫物枕。
例如，本发明一实施例提供的阵列基板，还包括：设置在所述彩膜层上的像素电极和公共电极，其中，所述像素电极和所述公共电极均为梳齿状电极，所述像素电极与所述公共电极的梳齿状电极交叉咬合配置，所述像素电极通过第三过孔与所述薄膜晶体管的漏极连接，所述公共电极通过第四过孔与所述公共电极线连接。
本发明的至少一个实施例还提供一种显示装置，包括：上述中的阵列基板。
本发明的至少一个实施例还提供一种阵列基板的制备方法，包括：提供衬底基板；在所述衬底基板上形成栅线、数据线和公共电极线，其中，所述 栅线和所述数据线交叉限定像素区域；在所述像素区域内形成薄膜晶体管；在所述薄膜晶体管上形成彩膜层，其中，形成所述彩膜层包括：在所述像素区域内形成单基色色阻块和在遮光区域内形成多基色色阻块，所述单基色色阻块包括一种基色的色阻层，所述多基色色阻块包括多个层叠设置的色阻层以遮挡光线。
例如，在本发明一实施例提供的制备方法中，所述像素区域包括第一子像素区域、第二子像素区域和第三子像素区域。
例如，在本发明一实施例提供的制备方法中，形成所述彩膜层还包括：形成第一基色层，所述第一基色层包括具有第一厚度的色阻块和具有第二厚度的色阻块，其中，通过构图工艺在所述第一子像素区域内形成所述第一厚度的色阻块，在所述遮光区域形成所述第二厚度的色阻块，所述第二厚度小于所述第一厚度。
例如，在本发明一实施例提供的制备方法中，形成所述彩膜层还包括：形成第二基色层，所述第二基色层包括具有第三厚度的色阻块和具有第四厚度的色阻块，其中，通过构图工艺在所述第二子像素区域形成所述第三厚度的色阻块，在遮光区域形成所述第四厚度的色阻块，所述第四厚度小于所述第三厚度。
例如，在本发明一实施例提供的制备方法中，形成所述彩膜层还包括：形成第三基色层，所述第三基色层包括具有第五厚度的色阻块和具有第六厚度的色阻块，其中，通过构图工艺在所述第三子像素区域形成所述第五厚度的色阻块，在遮光区域形成所述第六厚度的色阻块，所述第六厚度小于所述第五厚度。
例如，在本发明一实施例提供的制备方法中，在形成所述彩膜层之前，还包括形成第一透明电极，其中，形成所述第一透明电极的工序包括：沉积透明导电层薄膜，在所述透明导电层薄膜上涂覆光刻胶，然后通过曝光、显影、刻蚀、剥离光刻胶形成所述第一透明电极。
例如，在本发明一实施例提供的制备方法中，在形成所述第一透明电极之前，所述方法还包括形成栅极绝缘层的工序；并且/或者在形成所述第一透明电极之后且形成所述彩膜层之前，所述方法还包括形成钝化层的工序。
例如，在本发明一实施例提供的制备方法中，在形成所述彩膜层之后，所述方法还包括：形成第二透明电极和金属层的工序，并且，形成所述第二 透明电极和所述金属层的工序包括：沉积透明导电层薄膜和金属层薄膜；通过半色调掩膜工艺对所述透明导电层薄膜和所述金属层薄膜进行构图，形成所述第二透明电极和所述金属层。
例如，在本发明一实施例提供的制备方法中，所述金属层包括：位于所述公共电极线上方非透光区域对应位置，并与所述公共电极线并联的第二公共电极线。
例如，在本发明一实施例提供的制备方法中，所述公共电极线与公共电极连接，在形成所述彩膜层的工序中，还包括：在公共电极线与公共电极连接的对应位置处形成贯穿所述彩膜层的第一过孔。
例如，在本发明一实施例提供的制备方法中，在形成所述彩膜层之后，还包括：以所述彩膜层为隔离保护层，对所述钝化层和所述栅绝缘层进行干刻，在所述公共电极线与所述公共电极连接的对应位置形成贯穿所述钝化层及所述栅绝缘层的第二过孔。
例如，在本发明一实施例提供的制备方法中，在形成所述彩膜层之后，还包括：形成像素电极和公共电极，所述像素电极和所述公共电极均为梳齿状电极，所述像素电极与所述公共电极的梳齿状电极交叉咬合配置，所述像素电极通过第三过孔与所述薄膜晶体管的漏极连接，所述公共电极通过第四过孔与所述公共电极线连接。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为一种采用COA技术的ADS阵列基板的结构示意图；
图2为本发明实施例提供的ADS阵列基板的结构示意图；
图2a为本发明实施例提供的ADS阵列基板的平面结构示意图；
图3为本发明实施例提供的ADS阵列基板的制备方法流程图；
图4为本发明实施例提供的ADS模式阵列基板制备过程示意图；
图5为本发明实施例提供的ADS模式阵列基板中彩膜层制备过程示意图；
图6为本发明实施例提供IPS阵列基板的结构示意图。
附图标记
10-衬底基板，11-栅金属层，111-公共电极线，112-第二公共电极线，12-栅绝缘层，13-有源层，14-源漏金属层，141-漏极，15-黑矩阵，16-彩膜层，17-第一透明电极，18-有机膜层，19-钝化层，20-第二透明电极，30-第二基板，31-ITO膜层，32-隔垫物；41-像素电极；42-公共电极，43-薄膜晶体管，44-栅线，45-数据线，46-第一遮蔽部，47-第二遮蔽部，48-遮光区域。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的实施例提供一种阵列基板及其制备方法、显示装置，在本发明实施例中能够将彩膜制作于阵列基板上，从而减少构图次数，降低生产成本。
本发明的实施例提供的阵列基板包括：衬底基板，设置在衬底基板上的栅线、数据线，其中，栅线和数据线交叉限定像素区域；像素区域内设置有薄膜晶体管；薄膜晶体管上设置有彩膜层；该彩膜层包括：设置于像素区域内的单基色色阻块和设置于遮光区域内的多基色色阻块，单基色色阻块包括一种基色的色阻层，多基色色阻块包括多个层叠设置的色阻层以遮挡光线。
本实施例中的彩膜层又称为显色层(而目前形成于单独的基板上的彩膜层称为彩色滤光片)，为液晶显示器彩色化的关键，因为液晶显示器为非主动发光的组件，其显示色彩必需由内部的背光模块提供光源，再搭配驱动IC与液晶控制形成灰阶显示，然后透过彩膜层的R、G、B(红、绿、蓝)彩色层提供色相，形成彩色显示画面。本实施例提供的阵列基板，采用COA技术，将彩膜层也制作于阵列基板上，在衬底基板上形成薄膜晶体管之后，再形成彩膜层，彩膜层与阵列基板上各膜层间的位置关系在本实施例中不做限定，本领域的技术人员可以根据实际情况进行设计。
例如，在液晶显示装置中，多采用红、绿、蓝三基色的混色方案，即像素区域包括红、绿、蓝三个亚像素，当然实际应用时，并不限于此，还包括 红绿蓝白(RGBW)，红绿蓝黄(RGBY)等混色方案。下面以红、绿、蓝三基色的混色方案为例对本实施例的彩膜层进行说明，该彩膜层包括：位于像素区域的单基色色阻块，均由某一种基色的色阻层形成，例如红色阻块、绿色阻块和蓝色阻块(R、G、B)；除此之外，彩膜层还包括设置于遮光区域的多基色色阻块，该种多基色色阻块包括层叠设置的红色阻层、绿色阻层和蓝色阻层，由于红色阻层只允许红色可见光通过，阻挡其余颜色的可见光，类似地，绿色阻层和蓝色阻层也只允许对应颜色的可见光通过，阻挡其余颜色的可见光，因此，当红、绿、蓝三种色阻层层叠在一起时，可以阻挡所有颜色的可见光，可以代替黑矩阵起到遮光作用。如图2a所示，上述遮光区域48一般包括薄膜晶体管43的对应区域、数据线45对应区域、栅线44对应区域和阵列基板周边需要遮光的区域。
在本实施例提供的阵列基板中，彩膜层不需要特别的材料，只需普通的色阻材料采用常规工艺即可实现COA技术，而且可以省去黑矩阵层，减少构图次数，降低生产成本。为了让本领域技术人员更好的理解本发明实施例提供的阵列基板，下面对本发明提供的方案进行详细地说明。
例如，图2为本实施例提供的一种ADS(Advanced-Super Dimensional Switching，高级超维场开关技术)模式的阵列基板，该阵列基板包括衬底基板10，设置在衬底基板10上的栅线(设置于栅极金属层11中)、数据线(未示出)和与栅线同层设置的公共电极线111，其中，栅线和数据线交叉限定像素区域；像素区域内设置有薄膜晶体管；薄膜晶体管上设置有彩膜层16；该彩膜层16包括：设置于像素区域内的单基色色阻块和设置于遮光区域内的多基色色阻块，单基色色阻块包括一种基色的色阻层，多基色色阻块包括多个层叠设置的色阻层以遮挡光线。
该阵列基板还包括：依次设置于衬底基板10上的栅极金属层11、栅极绝缘层12、有源层13和源漏金属层14，栅极金属层11包括栅极、栅线和公共电极线111；然后形成第一透明电极17，第一透明电极17分布在像素区域，为板式电极，通过搭接方式连接至薄膜晶体管的漏极；在第一透明电极17之上依次形成钝化层19、彩膜层16和第二透明电极20，即钝化层19位于第一透明电极17所在层和彩膜层16之间，第二透明电极20设置于彩膜层16上。第二透明电极层20为狭缝电极。
上述彩膜层16包括位于像素区域的单基色色阻块，如红(R)色阻块、绿(G)色阻块和蓝(B)色阻块；除此之外，彩膜层还包括设置于遮光区域的多基色色阻块(见图2中的虚线框区域)，该种多基色色阻块包括层叠设置的红色阻层、绿色阻层和蓝色阻层，其中，遮光区域包括薄膜晶体管的对应区域、数据线对应区域、栅线对应区域和阵列基板周边需要遮光的区域。利用多基色补色原理进行遮光，实现高对比度，并且本方案不需要特别的材料，能够采用常规工艺和材料实现COA技术，且可以省去黑矩阵层，减少构图次数，降低成本。
另外，彩膜层16设置于第一透明电极17所在层和第二透明电极20所在层之间，而形成彩膜层16的色阻材料一般为绝缘有机材料，彩膜层16同时可以起到有机膜层的作用，因此本实施例可以省去有机膜层。
进一步地，上述阵列基板中第二透明电极层20上设置有一层金属层(未示出)。例如，该金属层通过半透掩模工艺(HTM Mask)，通过一次构图工艺形成，金属层图形下方保留第二透明电极层20。金属层图形存在多种设计，一种可选的方案为，金属层包括：位于公共电极线上方非透光区域对应位置，并与公共电极线并联的第二公共电极线112，可以降低公共电极线上的电阻及因此导致的信号延迟。
另一种可选的方案为，例如，如图2a所示，金属层还可以包括：位于数据线45上方的第一遮蔽部46。这部分区域的金属层(第一遮蔽部46)位于两个像素的交界处，可以起到遮挡光线的作用，防止漏光；另外，数据线45上方使用透明导电层或金属层还可以屏蔽侧向电场，避免交界处的液晶紊乱造成的漏光，对曲面显示装置尤为重要。例如，上述金属层还可进一步包括：位于栅线44上方的第二遮蔽部47，其起到的作用与第一遮蔽46部相类似。考虑到金属层会增加电容负载，可根据功耗要求，灵活地设置金属层形成第一、第二遮蔽部。
另外，上述金属层还可以包括：与隔垫物32对应的隔垫物枕。上述金属层还可以在与隔垫物32对应的位置保留，做为隔垫物32的隔垫物枕使用。
综上，在第二透明电极层20上增设一层金属层，制备时可以使用半透掩模工艺一次完成，不需要增加工序；同时增设的金属层的用途较多，具体设计时可以根据实际情况决定金属层保留的位置。金属层是否保留使用，主要看公共电极线的信号延迟情况及上基板的隔垫物设计的情况来综合考量。该 金属层，可以降低第二透明电极的电阻，也可以屏蔽漏光及形成段差以支撑不同高度的支撑隔离物。并在上述结构及工艺情况下，减少曝光的次数。
本发明的实施例还提供一种ADS阵列基板的制备方法，如图3和图4所示，该方法包括：
101、形成栅金属层11的工序，形成栅金属层包括形成栅线和公共电极线111；
该过程为：在衬底基板上通过沉积\涂胶曝光\显影\刻蚀\剥离等步骤(第1次MASK)，形成包括栅极、栅线、公共电极线及其他功能图形的栅金属层11。
102、形成栅绝缘层12及有源层13的工序；
该过程继续在基板上依次沉积栅绝缘层12和有源层13，本步骤中只进行成膜工序，不进行刻蚀，在下一工序中有源层13与源漏金属层14通过半透掩模工艺一次构图同步形成；当然，也可以选择在本步骤中对有源层13进行单独刻蚀。
103、形成源漏金属层14的工序；
本步骤通过沉积\涂胶曝光\显影\刻蚀\剥离等步骤(第2次MASK)，形成有源层13与源漏金属层14的图案，源漏金属层14的图案包括源极、漏极和数据线。
104、形成第一透明电极17的工序。
本步骤通过沉积\涂胶曝光\显影\刻蚀\剥离等步骤(第3次MASK)，形成第一透明电极17。
105、形成钝化层19的工序；本步骤只进行成膜工序，不进行刻蚀。
106、形成彩膜层16的工序，彩膜层16包括：设置于像素区域的单基色色阻块(R、G、B色阻块)和设置于遮光区域的多基色色阻块(如图中虚线框区域)，单基色色阻块包括一种基色的色阻层，多基色色阻块包括多个层叠设置的色阻层，且每一色阻层对应一种基色。对于通常的R、G、B三基色混色方案，本步骤一般共需要3次MASK(即第4、5、6次MASK)。像素区域包括第一子像素区域、第二子像素区域和第三子像素区域。
例如，如图5所示，形成彩膜层的工序包括：形成第一基色层(例如红阻块R)，通过构图工艺在第一子像素区域形成第一厚度的色阻块，在遮光区域形成第二厚度的色阻块，第二厚度小于第一厚度；形成第二基色层(例如 绿阻块G)，通过构图工艺在第二子像素区域形成第三厚度的色阻块，在遮光区域形成第四厚度的色阻块，第四厚度小于第三厚度；形成第三基色层(例如蓝阻块B)，通过构图工艺在第三子像素区域形成第五厚度的色阻块，在遮光区域形成第六厚度的色阻块，第六厚度小于第五厚度。在遮光区域，第二、四、六厚度的色阻块复合在一起达成遮光效果，其中，第一厚度、第三厚度和第五厚度的取值相等，第二厚度、第四厚度和第六厚度的取值相等。上述构图工艺为半透掩膜工艺。
需要说明的是，在上述形成彩膜层的工序中，在公共电极与公共电极线连接的位置(即形成第一过孔的位置)不保留色阻。
107、以彩膜层16为隔离保护层，对钝化层19和栅绝缘层12进行干刻，在公共电极与公共电极线连接的位置形成贯穿钝化层19及栅绝缘层12的第二过孔。
本步骤直接以显色色阻(彩膜层16)为隔离物，进行钝化层19和栅绝缘层12干刻，将第一次构图中形成的公共电极线上的钝化层19和栅绝缘层12刻蚀掉形成第二过孔，以用于工序108中通过透明导电材料(第二透明电极层)将公共电极线引出。
108、形成第二透明电极20的工序。
本步骤通过沉积\涂胶曝光\显影\刻蚀\剥离等步骤(第7次MASK)，形成第二透明电极20。
例如，本步骤还可以同步在第二透明电极20所在层上形成金属层，该金属层包括位于公共电极线上方非透光区域对应的位置处并与公共电极线并联的第二公共电极线112；和/或，位于数据线上方的第一遮蔽部；和/或，位于栅线上方的第二遮蔽部，和/或，与隔垫物对应的隔垫物枕(通常位于栅线的对应区域)。
例如，形成第二透明电极的工序，包括：沉积透明导电层和金属层；通过半透掩膜工艺，形成第二电极和图案化的金属层，图案化的金属层可包括：位于公共电极线上方非透光区域对应位置，并与公共电极线并联的第二公共电极线112；还可包括位于数据线上方的第一遮蔽部；和/或，位于栅线上方的第二遮蔽部，和/或，与隔垫物对应的隔垫物枕(通常位于栅线的对应区域)。
以上为本实施例提供的ADS阵列基板的制作工艺，不需要特殊材料，使用常规色阻材料，只需7MASK即可形成能实现COA技术的阵列基板，可以 省去黑矩阵和有机膜层的工序，减少MASK的次数，从而降低生产成本。同时，通过在第二透明电极层上设置金属层，以形成第二公共电极线和遮挡部，可以降低公共电极的阻值，并在数据线上形成屏蔽部起到屏蔽侧向电场作用，解决漏光；并且金属层可以作为隔垫物(Triple PS)的隔垫物枕(pillow)，对应的不同高度的支撑隔离物。
如图2所示，在第二基板30上先制作ITO膜层31，可以屏蔽ADS结构稳定性的外来电场，也可以保证隔垫物PS的粘附性；然后在ITO膜层31上制作常规材料的隔垫物(PS)32。另外，对于第二基板30，还可以在第二基板30的背面上制作透明导电屏蔽层，在第二基板30的正面(面向阵列基板的一侧)制作不同高度的支撑隔离物。
第二基板与阵列基板对盒后，完整的COA工艺完成，整个液晶盒阶段只需8～9次MASK。目前，黑矩阵形成于对盒基板侧，采用特殊材料(同时满足黑矩阵和隔垫物对材料的要求)制作BPS，同时实现黑矩阵和隔垫物的功能，而同时满足遮光和隔垫物弹性要求的材料比较难以寻找，增加了成本。而本实施例则只需色阻材料，降低了生产成本。
如图6所示，本发明的实施例还提供一种IPS(In-Plane Switching,平面转换)模式的阵列基板的结构及其制备方法，与上述中的ADS阵列基板的结构和制备方法类似。例如，如图6所示，区别之处仅在上述101～108工艺方法中进行工艺变更，在IPS阵列基板的形成过程中不进行形成第一透明电极的工序(步骤104)；在形成第二透明电极20的工序(步骤108)中，同步形成像素电极41和公共电极42，像素电极41和公共电极42均为梳齿状电极，二者的梳齿状电极交叉呈咬合配置(电极间隔一定的距离，形成空间平面电场)，像素电极41通过第三过孔和与薄膜晶体管的漏极141连接，公共电极42通过第四过孔和公共电极线连接，可以省去1次mask，这样通过6mask可实现IPS COA结构。
在以上IPS阵列基板的制作工艺中，不需要特殊的材料，使用常规色阻材料，只需6MASK即可形成能实现COA技术的阵列基板，可以省去黑矩阵和有机膜层的工序，减少MASK的次数，从而降低生产成本。同时，通过在像素电极上设置金属层，以形成第二公共电极线和遮挡部，可以降低公共电极的阻值，并在数据线上形成屏蔽部起到屏蔽侧向电场作用，解决漏光；并且金属层可以作为隔垫物(Triple PS)的隔垫物枕(pillow)，对应的不同高 度的支撑隔离物。
如图6所示，在第二基板30上先制作ITO膜层31，可以屏蔽IPS结构稳定性的外来电场，还可以保证隔垫物PS的粘附性；然后在ITO膜层31上制作常规材料的隔垫物(PS)32。另外，对于第二基板30，还可以在第二基板30背面上制作透明导电屏蔽层，第二基板30正面(面向阵列基板的一侧)制作不同高度的支撑隔离物。
第二基板与阵列基板对盒后，完整的COA工艺完成，整个液晶盒阶段只需7～8次MASK。目前，黑矩阵形成于对盒基板侧，采用特殊材料(同时满足黑矩阵和隔垫物对材料的要求)制作BPS，同时实现黑矩阵和隔垫物的功能，而同时满足遮光和隔垫物弹性要求的材料比较难以寻找，增加了成本。而本实施例则只需色阻材料，降低了生产成本。
本发明实施例还提供一种显示装置，其包括上述任意一种阵列基板。该显示装置，成本低，高解析度，并解决了ADS/IPS漏光的问题，所述显示装置可以为：液晶面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
需要注意的是，本发明虽然以ADS/IPS模式的阵列基板为例，但仅是为描述方面而进行的示例，并不限定于此。本发明还可以应用于其它结构的阵列基板及显示器上。
本发明的实施例提供的一种阵列基板制备方法和阵列基板、显示装置，将彩膜层设置在阵列基板上，该彩膜层除包括设置于像素区域的单基色色阻层外，还在栅线、数据线及外围区域等遮光区域形成层叠设置的色阻层，利用多基色补色原理进行遮光，实现高对比度，并且本方案不需要特别的材料，能够采用常规工艺和材料实现COA技术，且可以省去黑矩阵层，减少构图次数，降低成本。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于设备实施例而言，由于其基本相似于方法实施例，所以描述得比较简单，相关之处参见方法实施例的部分说明即可。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发 明的保护范围应该以权利要求的保护范围为准。
本申请要求于2016年1月4日递交的中国专利申请第201610006495.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (23)

  1. 一种阵列基板，包括：
    衬底基板，
    设置在所述衬底基板上的栅线、数据线，所述栅线和所述数据线交叉限定像素区域；所述像素区域内设置有薄膜晶体管；所述薄膜晶体管上设置有彩膜层；
    其中，所述彩膜层包括：设置于所述像素区域内的单基色色阻块和设置于遮光区域内的多基色色阻块，所述单基色色阻块包括一种基色的色阻层，所述多基色色阻块包括多个层叠设置的色阻层以遮挡光线。
  2. 根据权利要求1所述的阵列基板，其中，所述遮光区域包括所述薄膜晶体管对应的区域、所述栅线对应的区域、所述数据线对应的区域和所述阵列基板的周边需要遮光的区域。
  3. 根据权利要求1所述的阵列基板，还包括：设置于所述彩膜层下的第一透明电极。
  4. 根据权利要求3所述的阵列基板，还包括：设置于所述第一透明电极和所述彩膜层之间的钝化层。
  5. 根据权利要求1所述的阵列基板，还包括：设置于所述彩膜层之上的第二透明电极。
  6. 根据权利要求5所述的阵列基板，还包括:与所述栅线同层设置的公共电极线,设置于所述第二透明电极之上的金属层，其中，所述金属层包括：位于所述公共电极线上方非透光区域对应的位置处并与所述公共电极线并联的第二公共电极线。
  7. 根据权利要求6所述的阵列基板，所述金属层还包括：位于所述数据线上方的第一遮蔽部。
  8. 根据权利要求6所述的阵列基板，所述金属层还包括：位于所述栅线上方的第二遮蔽部。
  9. 根据权利要求6-8中任一项所述的阵列基板，其中，所述金属层上还设置有隔垫物，所述金属层还包括与所述隔垫物对应的隔垫物枕。
  10. 根据权利要求1或2所述的阵列基板，还包括：设置在所述彩膜层上的像素电极和公共电极，其中，所述像素电极和所述公共电极均为梳齿状电 极，所述像素电极与所述公共电极的梳齿状电极交叉咬合配置，所述像素电极通过第三过孔与所述薄膜晶体管的漏极连接，所述公共电极通过第四过孔与所述公共电极线连接。
  11. 一种显示装置，包括：权利要求1-10中任一项所述的阵列基板。
  12. 一种阵列基板的制备方法，包括：
    提供衬底基板；
    在所述衬底基板上形成栅线、数据线，其中，所述栅线和所述数据线交叉限定像素区域；
    在所述像素区域内形成薄膜晶体管；
    在所述薄膜晶体管上形成彩膜层，其中，形成所述彩膜层包括：在所述像素区域内形成单基色色阻块和在遮光区域内形成多基色色阻块，所述单基色色阻块包括一种基色的色阻层，所述多基色色阻块包括多个层叠设置的色阻层以遮挡光线。
  13. 根据权利要求12所述的制备方法，其中，所述像素区域包括第一子像素区域、第二子像素区域和第三子像素区域。
  14. 根据权利要求13所述的制备方法，其中，形成所述彩膜层还包括：
    形成第一基色层，所述第一基色层包括具有第一厚度的色阻块和具有第二厚度的色阻块，其中，通过构图工艺在所述第一子像素区域内形成所述第一厚度的色阻块，在所述遮光区域形成所述第二厚度的色阻块，所述第二厚度小于所述第一厚度。
  15. 根据权利要求14所述的制备方法，其中，形成所述彩膜层还包括：
    形成第二基色层，所述第二基色层包括具有第三厚度的色阻块和具有第四厚度的色阻块，其中，通过构图工艺在所述第二子像素区域形成所述第三厚度的色阻块，在遮光区域形成所述第四厚度的色阻块，所述第四厚度小于所述第三厚度。
  16. 根据权利要求15所述的制备方法，其中，形成所述彩膜层还包括：
    形成第三基色层，所述第三基色层包括具有第五厚度的色阻块和具有第六厚度的色阻块，其中，通过构图工艺在所述第三子像素区域形成所述第五厚度的色阻块，在遮光区域形成所述第六厚度的色阻块，所述第六厚度小于所述第五厚度。
  17. 根据权利要求12-16中任一项所述的制备方法，其中，在形成所述彩 膜层之前，还包括形成第一透明电极，其中，形成所述第一透明电极的工序包括：沉积透明导电层薄膜，在所述透明导电层薄膜上涂覆光刻胶，然后通过曝光、显影、刻蚀、剥离光刻胶形成所述第一透明电极。
  18. 根据权利要求17所述的制备方法，其中
    在形成所述第一透明电极之前，所述方法还包括形成栅极绝缘层的工序；并且/或者
    在形成所述第一透明电极之后且形成所述彩膜层之前，所述方法还包括形成钝化层的工序。
  19. 根据权利要求18所述的制备方法，其中，
    在形成所述彩膜层之后，所述方法还包括：形成第二透明电极和金属层的工序，并且
    形成所述第二透明电极和所述金属层的工序包括：
    沉积透明导电层薄膜和金属层薄膜；
    通过半色调掩膜工艺对所述透明导电层薄膜和所述金属层薄膜进行构图，形成所述第二透明电极和所述金属层。
  20. 根据权利要求19所述的制备方法，还包括:与所述栅线同层设置公共电极线,其中，所述金属层包括：位于所述公共电极线上方非透光区域对应位置，并与所述公共电极线并联的第二公共电极线。
  21. 根据权利要求20所述的制备方法，其中，所述公共电极线与公共电极连接，在形成所述彩膜层的工序中，还包括：在公共电极线与公共电极连接的对应位置处形成贯穿所述彩膜层的第一过孔。
  22. 根据权利要求21所述的制备方法，在形成所述彩膜层之后，还包括：以所述彩膜层为隔离保护层，对所述钝化层和所述栅绝缘层进行干刻，在所述公共电极线与所述公共电极连接的对应位置形成贯穿所述钝化层及所述栅绝缘层的第二过孔。
  23. 根据权利要求12-16中任一项所述的制备方法，在形成所述彩膜层之后，还包括：形成像素电极和公共电极，所述像素电极和所述公共电极均为梳齿状电极，所述像素电极与所述公共电极的梳齿状电极交叉咬合配置，所述像素电极通过第三过孔与所述薄膜晶体管的漏极连接，所述公共电极通过第四过孔与所述公共电极线连接。
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