WO2023273402A1 - 阵列基板、显示装置 - Google Patents

阵列基板、显示装置 Download PDF

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Publication number
WO2023273402A1
WO2023273402A1 PCT/CN2022/080085 CN2022080085W WO2023273402A1 WO 2023273402 A1 WO2023273402 A1 WO 2023273402A1 CN 2022080085 W CN2022080085 W CN 2022080085W WO 2023273402 A1 WO2023273402 A1 WO 2023273402A1
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WIPO (PCT)
Prior art keywords
sub
touch
array substrate
substrate
electrode
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PCT/CN2022/080085
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English (en)
French (fr)
Inventor
王骁
闫岩
马禹
陈维涛
张吉亮
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/021,205 priority Critical patent/US20230314888A1/en
Publication of WO2023273402A1 publication Critical patent/WO2023273402A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices

Definitions

  • the disclosure belongs to the technical field of touch display, and in particular relates to an array substrate and a display device.
  • Liquid crystal display panels are mainly used in display devices such as notebook computers and televisions.
  • the liquid crystal display panel mainly includes an array substrate and a counter substrate 61 arranged oppositely, and a liquid crystal layer arranged between the array substrate and the counter substrate 61.
  • a driving electric field is generated, and the liquid crystal molecules in the liquid crystal layer are deflected under the driving action of the driving electric field, thereby realizing the display function of the liquid crystal display panel.
  • the Incell (embedded) touch screen embeds the touch electrode unit of the touch screen inside the liquid crystal display, which can reduce the thickness of the module and reduce the production cost.
  • the advantages of image quality and the ability to realize Multi-Touch are favored by consumers and panel manufacturers, and become a new development direction in the future.
  • the present disclosure at least partially solves the problem of relatively small pixel aperture ratio in the existing Incell touch screen, and provides an array substrate and a display device.
  • the first aspect of the present disclosure is an array substrate, comprising:
  • a data line arranged on the substrate and extending along a first direction
  • the touch signal line is arranged on the base; the extension direction of the touch signal line is the same as the extension direction of the data line; the data line is insulated from the touch signal line in different layers, and the The orthographic projection of the touch signal line on the substrate and the orthographic projection of the data line on the substrate at least partially overlap.
  • the touch signal line is located on a side of the data line away from the direction of the substrate.
  • the orthographic projection of the touch signal line on the substrate completely covers the orthographic projection of the data line on the substrate.
  • the touch signal line has a center line extending along the first direction;
  • the data line has a center line extending along the first direction;
  • the orthographic projection of the center line of the touch signal line on the base completely overlaps the orthographic projection of the center line of the data line on the base.
  • the size of the touch signal line in the second direction is larger than the size of the data line in the second direction; the second direction is perpendicular to the first direction.
  • the array substrate further includes: a plurality of touch electrode units correspondingly coupled to the touch signal lines; the layer where the touch electrode units are located is located on the side of the data lines away from the direction of the substrate ;
  • the orthographic projection of the gap between two adjacent touch electrode units in the second direction on the substrate overlaps with the orthographic projection of the data line on the substrate;
  • the second direction is perpendicular to the first direction.
  • the layer where the touch electrode unit is located is located between the layer where the touch signal line is located and the layer where the data line is located.
  • the orthographic projection of the touch electrode unit on the substrate partially overlaps the orthographic projection of the touch signal line on the substrate.
  • the overlapping portion of the orthographic projection of the touch electrode unit on the substrate and the orthographic projection of the touch signal line on the substrate in the second direction The length is 1.5 to 3 microns.
  • the array substrate further includes: an organic insulating layer disposed between the layer where the data line is located and the layer where the touch electrode unit is located.
  • the array substrate also includes:
  • the array substrate includes a plurality of touch sub-regions, and the touch electrode units are located in the touch sub-regions one by one; each of the touch-control sub-regions corresponds to a plurality of the sub-pixel regions;
  • Common electrodes of a plurality of sub-pixels located in the same touch sub-region are coupled, and the plurality of coupled common electrodes are multiplexed as a touch-control electrode unit in the touch sub-region.
  • the array substrate further includes: a first passivation layer; along a direction away from the substrate, the layer where the common electrode is located, the first passivation layer, the layer where the touch signal line is located, the The layers where the pixel electrodes are located are sequentially arranged;
  • the common electrode is coupled to the touch signal line through a first connection via hole, and the first connection via hole at least penetrates through the first passivation layer.
  • the array substrate further includes: a second passivation layer; the second passivation layer is located on a side of the layer where the touch signal lines are located away from the substrate;
  • the first connection via hole includes a first part and a second part, the first part penetrates through the first passivation layer, the layer where the touch signal line is located, and the second passivation layer, and connects the At least part of the common electrode is exposed; the second part penetrates through the second passivation layer and exposes at least part of the touch signal;
  • the array substrate further includes a first connection pattern, and the orthographic projection of the first connection pattern on the substrate covers the first part and the second part of the first connection via hole on the substrate. orthographic projection to couple the common electrode with the touch signal line.
  • the first connection pattern is set on the same layer as the pixel electrode and made of the same material.
  • the sub-pixel further includes: a driving circuit, at least part of an output electrode of the driving circuit is located on a side of the organic insulating layer close to the substrate;
  • the pixel electrode is coupled to the output electrode through a second connection via hole, and the second connection via hole at least penetrates through the organic insulating layer, the first passivation layer and the second passivation layer, so as to The output electrode of the driving circuit is exposed, and the pixel electrode is coupled to the output electrode.
  • the driving circuit includes: a driving transistor; the second connection via hole includes: a first sub-via hole and a second sub-via hole; the first sub-via hole penetrates through the organic insulating layer, and the The second sub-via penetrates through the first passivation layer and the second passivation layer, and the orthographic projection of the first sub-via on the substrate includes the second sub-via on the substrate. orthographic projection; the pixel electrode is coupled to the output electrode through the second sub-via hole.
  • the array substrate further includes: an auxiliary electrode located between two adjacent sub-pixel regions along the first direction and extending along the second direction; Multiple common electrodes in the control sub-region are coupled through the auxiliary electrodes;
  • the conductivity of the auxiliary electrode is greater than that of the common electrode.
  • the auxiliary electrode is insulated from the gate line and is provided in the same layer and the same material.
  • the array substrate further includes a gate insulating layer, a third connection via hole, and a second connection pattern; at least part of the gate insulating layer is located on the side of the auxiliary electrode away from the substrate; the third The connection via hole includes a third sub-via hole and a fourth sub-via hole, the third sub-via hole penetrates the organic insulating layer; the fourth sub-via hole penetrates the second passivation layer and the first passivation layer.
  • a passivation layer, exposing the auxiliary electrode and the common electrode, and the orthographic projection of the third sub-via on the substrate includes the orthographic projection of the fourth sub-via on the substrate;
  • the projection of the second connection pattern on the substrate covers the fourth sub-via to couple the auxiliary electrode to the common electrode.
  • a second aspect of the present disclosure provides a display device, including any one of the above-mentioned array substrates.
  • FIG. 1 is a schematic diagram of a first layout of a sub-pixel provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic layout diagram of multiple common electrodes located in the same touch sub-region in the array substrate provided by the embodiment of the present disclosure
  • FIG. 3 is a schematic layout diagram of multiple common electrodes located in different touch sub-regions in the array substrate provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a second layout of another sub-pixel provided by an embodiment of the present disclosure.
  • Fig. 5 is a schematic cross-sectional view along the A1A2 direction in Fig. 1 or Fig. 4;
  • Fig. 6 is a schematic cross-sectional view along the B1B2 direction in Fig. 1 or Fig. 4;
  • Fig. 7 is a schematic cross-sectional view along the C1C2 direction in Fig. 4;
  • FIG. 8 is a schematic diagram of connection between an output electrode and a pixel electrode provided by an embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of the positional relationship between the black matrix, the touch signal line and the data line provided by the embodiment of the present disclosure.
  • the two structures are "set in the same layer” means that the two structures are formed by the same material layer, so they are in the same layer in the layered relationship, but it does not mean that the distance between them and the substrate 60 is equal, and also It does not mean that they have the same structure as other layers of the substrate 60 .
  • patterning process refers to the step of forming a structure with a specific pattern, which can be a photolithography process.
  • the photolithography process includes forming a material layer, coating photoresist, exposing, developing, etching, photolithography, etc.
  • One or more steps in steps such as resist stripping; of course, the “patterning process” can also be other processes such as embossing process, inkjet printing process, etc.
  • the disclosure discloses an array substrate, which integrates the touch electrode layer and the touch signal line 31 inside the array substrate, so that when the array substrate is used to manufacture a liquid crystal display panel, the liquid crystal display panel can be used to realize The touch electrode layer and the touch signal line 31 of the touch function are integrated inside the liquid crystal display panel to realize a liquid crystal touch display panel with a full in cell touch (Full In Cell Touch) structure.
  • the liquid crystal touch display panel with Full In Cell Touch structure integrates touch function and display function, not only can realize one-stop seamless production, but also has the characteristics of integration, thinness, low cost, low power consumption and high image quality. , can realize multi-type touch (ie Multi-Touch) and other advantages.
  • the touch signal line 31 and the data line 30 in the array substrate are generally arranged side by side in the non-opening area between adjacent sub-pixel columns.
  • the touch signal line 31 and the data line 30 are arranged in the same layer and the same material, it is necessary to widen the distance between the data line 30 and the touch signal line 31 located in the same non-opening area (currently located in the same non-opening area).
  • the distance between the data line 30 and the touch signal line 31 is generally more than 6.5 ⁇ m), so as to avoid the short circuit between the data line 30 and the touch signal line 31, but this method will reduce the aperture ratio of the liquid crystal display panel, It is not conducive to the improvement of the display quality of the liquid crystal display panel.
  • the present disclosure insulates the touch signal line 31 and the data line 30 in different layers, so that there is no need to consider the short circuit problem between the data line 30 and the touch signal line 31, that is, there is no need to specifically limit the touch signal.
  • the distance between the line 31 and the data line 30 on the plane of the array substrate can reduce the limitation of the size of the non-opening area between the adjacent sub-pixel columns by the touch signal line 31 and the data line 30 compared with the prior art, and then Improve the aperture ratio of the liquid crystal display panel.
  • an embodiment of the present disclosure provides an array substrate.
  • the array substrate includes: a substrate 60; a data line 30 arranged on the substrate 60 and extending along a first direction; a touch signal line 31 arranged on the substrate 60; The extending direction is the same; the data line 30 and the touch signal line 31 are insulated from each other, and the orthographic projection of the touch signal line 31 on the substrate 60 and the orthographic projection of the data line 30 on the substrate 60 at least partially overlap.
  • the first direction includes a vertical direction
  • the second direction includes a horizontal direction
  • the touch signal lines 31 can be respectively coupled to the corresponding touch electrode units in the array substrate and the subsequent chip bound on the array substrate. After the array substrate and the opposite substrate 61 are combined to form a liquid crystal display panel, when a touch operation occurs in the touch area of the liquid crystal display panel, the touch operation can change the touch control formed on the touch electrode unit in the array substrate. At the same time, the touch signal line 31 is used to transmit the touch signal collected on the touch unit to the chip, and the chip judges the specific position of the touch according to the touch signal received from each touch signal line 31 .
  • the touch signal line 31 and the data line 30 may not be provided on the same layer.
  • the touch signal line 31 and the data line 30 may not be provided on the same layer.
  • the projections of the touch signal lines 31 and the data lines 30 on the substrate 60 can even overlap. Therefore, the arrangement provided in the present disclosure can effectively reduce the area of the non-aperture area around the sub-pixels, thereby increasing the pixel aperture ratio of the liquid crystal display panel formed by the array substrate by about 6%.
  • the rubbing cloth needs to rub the alignment film in a direction perpendicular to the extending direction of the data lines 30, so that the rubbing cloth rubs near the data lines 30 and the touch signal lines 31
  • Rubbing Shadow the width of the alignment shadow area in the prior art is about 6.5 ⁇ m
  • this area is easy Light leakage occurs. Therefore, the non-opening area of the pixel needs to be shielded by the black matrix pattern on the opposite substrate 61 after the box is assembled.
  • the touch signal lines 31 are arranged in the non-opening area, when aligning the array substrate and the counter substrate 61, it is necessary to consider the accuracy of the box alignment from the touch signal lines 31, and it is also necessary to increase the The area of the black matrix pattern will increase the width of the black matrix pattern in the direction perpendicular to the extension of the data lines 30, resulting in a decrease in the aperture ratio of the liquid crystal display panel.
  • the array substrate provided by the embodiment of the present disclosure, by setting the orthographic projection of the touch signal line 31 on the substrate 60 to partially overlap with the orthographic projection of the data line 30 on the substrate 60, the array substrate and the opposite When the substrate 61 is in the box, the increase in width of the black matrix pattern perpendicular to the extending direction of the data line 30 caused by the touch signal line 31 is reduced, thereby effectively reducing the black matrix pattern on the opposite substrate 61 area.
  • the material of the substrate 60 can be selected according to actual needs, for example, a glass substrate 60 can be selected, but not limited thereto.
  • the touch signal lines 31 are respectively coupled to the corresponding touch electrode units in the array substrate and the subsequent chip bound on the array substrate. After the array substrate and the opposite substrate 61 are combined to form a liquid crystal display panel, when a touch operation occurs in the touch area of the liquid crystal display panel, the touch operation can change the touch control formed on the touch electrode unit in the array substrate. At the same time, the touch signal line 31 is used to transmit the touch signal collected on the touch unit to the chip, and the chip judges the specific position of the touch according to the touch signal received from each touch signal line 31 .
  • the touch signal line 31 is located on a side of the data line 30 away from the direction of the substrate 60 .
  • the layer where the touch signal line 31 is located is above the layer where the data line 30 is located, and the two can be insulated and separated by an insulating layer structure.
  • the touch signal line 31 is located on the side of the data line 30 away from the direction of the substrate 60 (the touch signal line 31 is located above the data line 30 in FIG. After the box is assembled, the touch signal line 31 is located between the data line 30 and the liquid crystal layer.
  • the orthographic projections of the touch signal lines 31 and the data lines 30 on the substrate 60 overlap.
  • the touch signal lines 31 can have a certain shielding effect on the data lines 30 and shield the data lines to a certain extent. 30 electric field, so that the influence of the electric field of the data line 30 on the liquid crystal can further weaken the dependence on the light-shielding function of the black matrix, that is, the area of the black matrix pattern on the opposite substrate 61 can be effectively reduced.
  • the orthographic projection of the touch signal lines 31 on the substrate 60 completely covers the orthographic projection of the data lines 30 on the substrate 60 .
  • the touch signal line 31 is located on the side of the data line 30 that is close to and away from the substrate 60, that is, after the array substrate and the opposite substrate 61 are boxed, the touch signal line 31 is located
  • the data lines 30 face toward the light emitting surface side of the display panel.
  • the touch signal line 31 can completely wrap the data line 30, thereby increasing the coverage of the data line 30.
  • the shielding effect of the electric field weakens the influence of the electric field of the data line 30 on the liquid crystal.
  • the touch signal line 31 has a center line extending along the first direction; the data line 30 has a center line extending along the first direction; the center line of the touch signal line 31 is on the base 60
  • the orthographic projection on is completely overlapped with the orthographic projection of the center line of the data line 30 on the substrate 60 .
  • the center of the touch signal line 31 overlaps with the center of the data line 30.
  • the touch signal line 31 can wrap the signal line, and the touch signal line 31 is opposite to the signal line.
  • the degree of wrapping of the sub-pixels is the same in the second direction, which is beneficial to the same luminous display of two adjacent sub-pixels located on both sides of the touch signal line 31, ensuring the display effect of the display panel.
  • the size of the touch signal line 31 in the second direction is larger than the size of the data line 30 in the second direction. That is, the width of the touch signal line 31 is greater than the width of the data line 30 .
  • the touch signal line 31 is located on the side of the data line 30 that is close to and away from the substrate 60, that is, after the array substrate and the opposite substrate 61 are boxed, the touch signal line 31 is located
  • the data lines 30 face toward the light emitting surface side of the display panel.
  • the touch signal line 31 can completely wrap the data line 30, thereby increasing the shielding effect on the electric field of the data line 30 and weakening the electric field of the data line 30. LCD effects.
  • the opening area corresponding to the sub-pixel is the actual light-transmitting area of the sub-pixel
  • the non-opening area corresponding to the sub-pixel is the non-light-transmitting area corresponding to the sub-pixel.
  • the non-opening area is located around the opening area.
  • the driving circuit corresponding to the sub-pixel is located in the non-opening area corresponding to the sub-pixel, and the gate line 10 and the data line 30 included in the array substrate are also located in the non-opening area.
  • the array substrate includes a first layer of indium tin oxide layer (1ITO layer) and a second layer of indium tin oxide layer (2ITO layer).
  • the layer includes a pixel electrode 40 .
  • the array substrate further includes: a plurality of touch electrode units, which are correspondingly coupled to the touch signal lines 31; The orthographic projection of the gap between two adjacent touch electrode units on the substrate 60 overlaps with the orthographic projection of the data line 30 on the substrate 60 ; the second direction is perpendicular to the first direction.
  • the touch electrode layer included in the array substrate can be located in the touch area of the array substrate, the touch electrode layer includes a plurality of mutually independent touch electrode units, and the plurality of touch electrode units can be arranged in an array, but not limited to this.
  • the touch area can be divided into a plurality of touch sub-areas, and the touch electrode units are located in the touch sub-areas in one-to-one correspondence. It is worth noting that the specific position of the touch area can be set according to actual needs. For example, after the touch area and the array substrate form a liquid crystal display panel, the entire display area of the liquid crystal display panel overlaps; or the touch area is set to be located in the display area within, and only coincides with, the specified area in the display area.
  • each touch electrode unit is coupled to a corresponding touch signal line 31 , and the end of the touch signal line 31 away from the touch electrode unit can be coupled to a chip subsequently bound on the array substrate.
  • the touch operation can change the touch control formed on the touch electrode unit in the array substrate.
  • the touch signal line 31 is used to transmit the touch signal collected on the touch unit to the chip, and the chip judges the specific position of the touch according to the touch signal received from each touch signal line 31 .
  • the touch signal lines 31 are respectively coupled to the corresponding touch electrode units in the array substrate and the chips subsequently bonded on the array substrate. After the array substrate and the opposite substrate 61 are combined to form a liquid crystal display panel, when a touch operation occurs in the touch area of the liquid crystal display panel, the touch operation can change the touch control formed on the touch electrode unit in the array substrate. At the same time, the touch signal line 31 is used to transmit the touch signal collected on the touch unit to the chip, and the chip judges the specific position of the touch according to the touch signal received from each touch signal line 31 .
  • the layer where the touch electrode unit is located is located between the layer where the touch signal line 31 is located and the layer where the data line 30 is located.
  • the touch electrode unit and the touch signal line 31 are located at the data line 30 close to the liquid crystal display panel to emit light. side of the face.
  • the touch signal line 31 is coupled to the corresponding touch electrode, that is, when the liquid crystal display panel is in the working state, the electric field state of the touch signal line 31 is consistent with the touch electrode.
  • the electric field of the data line 30 can be shielded by the touch electrode and the touch signal line 31, so that the area where the data line 30 is located is a dark area, thereby reducing the adverse effect on the deflection of the liquid crystal in the liquid crystal display panel and improving the performance of the liquid crystal display panel. Opening rate.
  • the orthographic projection of the touch electrode unit on the substrate 60 partially overlaps the orthographic projection of the touch signal line 31 on the substrate 60 .
  • the touch electrode unit and the touch signal line 31 on the substrate 60 overlaps, the touch electrode unit and the touch signal line 31 jointly realize the entire surface of the electric field of the data line 30 in the array substrate. Shielding, so that the electric field of the data line 30 can be completely shielded to form a dark area, so as to avoid light leakage of the liquid crystal display panel in the area where the data line 30 is located. Therefore, with this arrangement, there is no need to use the black matrix to block the pixel non-aperture area of the array substrate, thereby increasing the aperture ratio of the liquid crystal display panel.
  • the overlapping portion of the orthographic projection of the touch electrode unit on the substrate 60 and the orthographic projection of the touch signal line 31 on the substrate 60 has a length in the second direction of 1.5-3 microns.
  • the width of the overlapping area of the touch electrode unit and the touch signal line 31 may include 1.5-3 microns.
  • the size can be adjusted and determined according to the specific size of the display panel and the specific size of the sub-pixels.
  • the width of the overlapping area between the touch electrode unit and the touch signal line 31 can be 2 microns.
  • the array substrate further includes: an organic insulating layer 51 disposed between the layer where the data line 30 is located and the layer where the touch electrode unit is located.
  • an organic insulating layer 51 disposed between the layer where the data line 30 is located and the layer where the touch electrode unit is located. Referring to FIGS. 5-6 , in a direction perpendicular to the substrate 60 , the data lines 30 , the organic insulating layer 51 and the touch signal lines 31 are sequentially stacked in a direction away from the substrate 60 .
  • the thickness of the organic insulating layer 51 is relatively thick, and has a planar effect.
  • At least part of the above-mentioned arrangement of the organic insulating layer 51 is located between the touch signal line 31 and the common electrode 20, which increases the distance between the touch signal line 31 and the pixel electrode 40, which is beneficial to improve the touch caused by the process fluctuation of the pixel electrode 40.
  • the left and right side electric fields formed between the control signal line 31 and the pixel electrode 40 are asymmetrical, thereby improving the transmittance deviation in the opening area, and better solving the visually inconsistent brightness and darkness caused by the transmittance deviation. Black stains or white stains are formed on the surface, which effectively improves the yield rate of the product.
  • the array substrate further includes: a plurality of gate lines 10, a plurality of data lines 30, and a plurality of sub-pixels; the plurality of gate lines 10 and the plurality of data lines 30 define a plurality of sub-pixel regions, and the plurality of sub-pixels are correspondingly located within a plurality of sub-pixel regions; the sub-pixels include pixel electrodes 40 and common electrodes 20 .
  • the data lines 30 are intersected with the gate lines 10 .
  • the data lines 30 extend along a first direction
  • the gate lines 10 extend along a second direction.
  • the array substrate may include a plurality of gate lines 10 and a plurality of data lines 30, the plurality of gate lines 10 and the plurality of data lines 30 are intersected, and a plurality of sub-pixel regions distributed in an array are defined on the substrate 60, and the plurality of sub-pixels are one by one Correspondingly located within a plurality of sub-pixel regions.
  • the plurality of sub-pixels may include a plurality of sub-pixel columns arranged along the second direction, and each sub-pixel column includes a plurality of sub-pixels arranged along the first direction.
  • the touch area of the array substrate is provided with a touch electrode layer, and the touch electrode layer includes a plurality of mutually independent touch electrode units, and the plurality of touch electrode units may be arranged in an array, but is not limited thereto.
  • the touch area can be divided into a plurality of touch sub-areas, and the touch electrode units are located in the touch sub-areas in one-to-one correspondence. It is worth noting that the specific position of the touch area can be set according to actual needs. For example, after the touch area and the array substrate form a liquid crystal display panel, the entire display area of the liquid crystal display panel overlaps; or the touch area is set to be located in the display area within, and only coincides with, the specified area in the display area.
  • each touch electrode unit is coupled to a corresponding touch signal line 31 , and the end of the touch signal line 31 away from the touch electrode unit can be coupled to a chip subsequently bound on the array substrate.
  • the touch operation can change the touch control formed on the touch electrode unit in the array substrate.
  • the touch signal line 31 is used to transmit the touch signal collected on the touch unit to the chip, and the chip judges the specific position of the touch according to the touch signal received from each touch signal line 31 .
  • the touch signal line 31 and the data line 30 can be arranged on the base 60 with different layers of insulation, and the orthographic projection of the touch signal line 31 on the base 60, and the array substrate
  • the orthographic projections of the upper data lines 30 on the substrate 60 all overlap; this arrangement does not need to consider the short circuit problem between the touch signal lines 31 and the data lines 30, so that the touch signal lines 31 and the data lines 30 in the array substrate are
  • the spacing in the plane of the base 60 is not particularly limited, and the projections of the touch signal lines 31 and the data lines 30 on the base 60 may even overlap. Therefore, the arrangement provided in the present disclosure can effectively reduce the area of the non-aperture area around the sub-pixels, thereby increasing the pixel aperture ratio of the liquid crystal display panel formed by the array substrate by about 6%.
  • the rubbing cloth needs to rub the alignment film in a direction perpendicular to the extending direction of the data lines 30, so that the rubbing cloth rubs near the data lines 30 and the touch signal lines 31
  • Rubbing Shadow the width of the alignment shadow area in the prior art is about 6.5 ⁇ m
  • this area is easy Light leakage occurs. Therefore, the non-opening area of the pixel needs to be shielded by the black matrix pattern on the opposite substrate 61 after the box is assembled.
  • the touch signal lines 31 are arranged in the non-opening area, when aligning the array substrate and the counter substrate 61, it is necessary to consider the accuracy of the box alignment from the touch signal lines 31, and it is also necessary to increase the The area of the black matrix pattern will increase the width of the black matrix pattern in the direction perpendicular to the extension of the data lines 30, resulting in a decrease in the aperture ratio of the liquid crystal display panel.
  • the array substrate provided by the embodiment of the present disclosure, by setting the orthographic projection of the touch signal line 31 on the substrate 60 to partially overlap with the orthographic projection of the data line 30 on the substrate 60, the array substrate and the opposite When the substrate 61 is in the box, the increase in width of the black matrix pattern perpendicular to the extending direction of the data line 30 caused by the touch signal line 31 is reduced, thereby effectively reducing the black matrix pattern on the opposite substrate 61 area.
  • the sub-pixel includes a pixel electrode 40 and a common electrode 20 .
  • the pixel electrode 40 and the common electrode 20 are arranged opposite to each other along a direction perpendicular to the substrate 60 .
  • the pixel electrode 40 is coupled to a driving circuit to receive electrical signals provided by the driving circuit.
  • the pixel electrode 40 and the common electrode 20 together form a driving electric field to drive the liquid crystal in the liquid crystal display panel to deflect and realize the display function of the liquid crystal display panel.
  • the array substrate includes a plurality of touch sub-regions, and the touch electrode units are located in the touch sub-regions one by one; each touch sub-region corresponds to a plurality of sub-pixel regions;
  • the common electrodes 20 of the sub-pixels are coupled, and the coupled common electrodes 20 are multiplexed as touch electrode units in the touch sub-region.
  • the common electrodes 20 located in the same touch sub-region can be multiplexed as touch electrode units in the touch sub-region, so that there is no need to additionally manufacture touch electrodes in the array substrate unit. Moreover, the common electrodes 20 located in the same touch sub-area are all coupled together, so that the resistance of the common electrodes 20 is low, and the loss generated is small. Therefore, the common electrodes 20 located in the same touch sub-area When 20 is multiplexed as the touch electrode unit in the touch sub-region, the resistance of the touch electrode unit is lower, thereby effectively reducing the loss on the touch signal line 31, improving the touch sensitivity, and improving the overall Product competitiveness and added value (ie touch function).
  • multiple common electrodes 20 located in the same touch sub-region can be coupled together through a connecting portion.
  • the plurality of common electrodes 20 arranged along the second direction pass through the first connecting portion 21 located between adjacent common electrodes 20
  • the connection can be connected as an integral structure; the plurality of common electrodes 20 arranged along the second direction can be connected through the second connection part 22 .
  • the first connecting portion 21 is not provided between the common electrodes 20 in different touch sub-regions, so that the common electrodes 20 are disconnected;
  • the common electrodes 20 in different touch sub-regions are disconnected from the second connection portion 22 , so as to realize the disconnection between the common electrodes 20 .
  • the common electrode 20 may be coupled to the touch signal line 31 through the first connecting portion 21 .
  • the orthographic projection of the first connecting portion 21 on the substrate covers the orthographic projection of the first part of the first connecting via Via1 on the substrate and overlaps, and the first part of the first connecting via Via1 exposes the first connecting part 21 ;
  • the orthographic projection of the second part of the first connection via hole Via1 on the substrate overlaps with the orthographic projection of part of the pattern of the touch signal line 31 on the substrate, and exposes this part of the touch signal line 31 .
  • the first connecting portion 21 and the second connecting portion 22 can be disposed on the same layer as the common electrode 20 and made of the same material. That is, the first connection portion 21 , the second connection portion 22 and the common electrode 20 can be formed in the same patterning process, thereby simplifying the manufacturing process of the array substrate and reducing the manufacturing cost of the array substrate.
  • the liquid crystal display panel is used to realize touch control.
  • the specific process of the display function is as follows:
  • the touch signal line 31 provides a touch signal to the coupled common electrode 20 (that is, the touch electrode unit).
  • the touch operation occurs in the touch area of the liquid crystal display panel.
  • the touch signal corresponding to the touch electrode unit at the position will change, and the touch electrode unit transmits the changed touch signal to the chip through the corresponding touch signal line 31, and the chip judges the touch signal based on the changed touch signal.
  • the specific location where the control operation takes place is not limited to the coupled common electrode 20 (that is, the touch electrode unit).
  • the touch signal line 31 provides the common electrode 20 signal required for display to the coupled common electrode 20, and at the same time, the sub-pixel driving circuit in the array substrate provides a driving signal for the corresponding pixel electrode 40, so that the pixel electrode 40 An electric field for driving the deflection of the liquid crystal is generated between the 40 and the common electrode 20, so that the liquid crystal display panel realizes the display function.
  • the array substrate further includes: a first passivation layer 52; along the direction away from the substrate 60, the layer where the common electrode 20 is located, the first passivation layer 52, the layer where the touch signal line 31 is located, and the layer where the pixel electrode 40 is located
  • the layers are arranged in sequence; the common electrode 20 is coupled to the touch signal line 31 through the first connection via hole Via1 , and the first connection via hole Via1 at least penetrates the first passivation layer 52 .
  • the first connection via hole Via1 is directly formed in the first passivation layer 52 , and the touch signal line 31 can be directly connected to the common electrode 20 through the first connection via hole Via1 .
  • the array substrate further includes: a second passivation layer 53; the second passivation layer 53 is located on the side where the touch signal line 31 is located away from the substrate 60; the first connection via hole Via1 includes the first part and the second Two parts, the first part penetrates the first passivation layer 52, the layer where the touch signal line 31 is located, and the second passivation layer 53, and exposes at least part of the common electrode 20; the second part penetrates the second passivation layer 53 , and expose at least part of the touch signal; the array substrate also includes a first connection pattern 42, and the orthographic projection of the first connection pattern 42 on the substrate 60 covers the first part and the second part of the first connection via hole Via1 on the substrate 60 to couple the common electrode 20 with the touch signal line 31 .
  • the touch signal line 31 can be connected to the common electrode 20 through the first connection pattern 42 .
  • the orthographic projection of the first connection pattern 42 on the substrate 60 covers the orthographic projection of the first part and the second part of the first connection via hole Via1 on the substrate 60 .
  • the first passivation layer 52 and the second passivation layer 53 can be etched once through a patterning process to remove the holes located above at least part of the common electrode 20 (corresponding to the first via hole).
  • the first via holes in the first passivation layer 52 and the second passivation layer 53 expose at least part of the common electrode 20 and at least part of the touch signal line 31 . That is, based on this setting method, a separate etching step for the first passivation layer 52 can be omitted, and a mask process can be saved, thereby simplifying the manufacturing process of the array substrate and saving the manufacturing cost of the array substrate.
  • the first connection pattern 42 is disposed on the same layer as the pixel electrode 40 and made of the same material.
  • the first connection pattern 42 and the pixel electrode 40 are arranged on the same layer and the same material, so that the first connection pattern 42 and the pixel electrode 40 can be formed in the same patterning process, which is conducive to simplifying the manufacturing process of the array substrate and reducing the production cost of the array substrate. cost.
  • the first connection pattern 42 couples the common electrode 20 and the corresponding touch signal line 31 through the first part and the second part of the first via hole.
  • the sub-pixel further includes: a driving circuit, at least part of the output electrode 33 of the driving circuit is located on the side of the organic insulating layer 51 close to the substrate 60; the pixel electrode 40 is coupled to the output electrode 33 through the second connection via hole Via2 connected, the second connection via hole Via2 at least penetrates the organic insulating layer 51, the first passivation layer 52 and the second passivation layer 53, so as to expose the output electrode 33 of the driving circuit, and couple the pixel electrode 40 to the output electrode 33 .
  • the driving circuit includes a thin film transistor, the gate 12 of the thin film transistor is coupled to the corresponding gate line 10, the input electrode of the thin film transistor is coupled to the corresponding data line 30, and the output electrode 33 of the thin film transistor is used as the output of the driving circuit
  • the electrode 33 and the output electrode 33 are coupled to the pixel electrode 40 .
  • the output electrode 33 includes the source electrode 32 of the thin film transistor.
  • the output electrode 33 and the data line 30 and the touch signal line 31 are provided in the same layer and with the same material.
  • the gate insulating layer 50 , the output electrode 33 , the organic insulating layer 51 , the common electrode 20 , the first passivation layer 52 and the pixel electrode 40 are sequentially stacked.
  • the driving circuit includes: a driving transistor; the second connection via hole Via2 includes: a first sub-via hole and a second sub-via hole; the first sub-via hole penetrates the organic insulating layer 51, and the second sub-via hole penetrates the first sub-via hole A passivation layer 52 and a second passivation layer 53, the orthographic projection of the first sub-via on the substrate 60 includes the orthographic projection of the second sub-via on the substrate 60; the pixel electrode 40 passes through the second sub-via and the output The electrodes 33 are coupled.
  • a patterning process is performed to form an opening on the organic insulating layer 51, and the gate insulating layer 50 is continuously etched in the opening, thereby forming a pattern penetrating through the organic insulating layer 51 and the gate insulating layer. 50 for the first sub-via.
  • the first passivation layer 52 is formed, and the next patterning process is performed to pattern the first passivation layer 52 to form a second sub-via hole penetrating through the first passivation layer 52 .
  • a part of the first passivation layer 52 is located in the first sub-via, and the part is etched to form a second sub-via, and the orthographic projection of the first sub-via on the substrate 60 surrounds the second sub-via.
  • the orthographic projection of the holes on the substrate 60 forms a trap.
  • a pixel electrode 40 is formed, and the pixel electrode 40 is coupled to the output electrode 33 through the first sub-via hole and the second sub-via hole.
  • the orthographic projection of the boundary of the first sub-via on the substrate 60 and the orthographic projection of the output electrode 33 on the substrate 60 are at least partially overlapped, so that at least the boundary of the first sub-via Part of it can be located on the output electrode 33, and at least part of the boundary of the second sub-via can be controlled to be located on the output electrode 33, which can prevent the pixel electrode 40 from being completely disconnected at the boundary of the output electrode 33, thereby ensuring that the pixel electrode 40 is completely disconnected. 40 and the output electrode 33 have good connection performance.
  • the array substrate further includes: an auxiliary electrode 13 located between two adjacent sub-pixel regions along the first direction and extending along the second direction;
  • the plurality of common electrodes 20 in the touch sub-region are coupled through the auxiliary electrodes 13 ; the conductivity of the auxiliary electrodes 13 is greater than that of the common electrodes 20 .
  • the auxiliary electrode 13 can be provided in the non-opening area between adjacent sub-pixel regions, and the auxiliary electrode 13 can be coupled with the common electrode 20, so that the common electrode 20 located in the same touch sub-region
  • the resistance is low, which effectively reduces the loss on the touch signal line 31, improves the touch sensitivity, and improves product competitiveness and added value (ie, touch function) as a whole.
  • the material of the common electrode 20 may include ITO, and the material of the auxiliary electrode 13 may include conductive metal.
  • the square resistance of ITO is 30 ⁇ /square, and the square resistance of conductive metal is 0.01 ⁇ /square, that is, the resistivity of conductive metal is much lower than that of ITO.
  • the overall resistance of the common electrodes 20 in the array substrate can be greatly reduced, and the resistance uniformity of the common electrodes 20 in the same touch sub-region can be improved. sex.
  • the array substrate further includes a gate insulating layer 50, a third connection via hole Via3, and a second connection pattern 43; at least part of the gate insulating layer 50 is located on the side of the auxiliary electrode 13 away from the substrate 60;
  • the third connection via hole Via3 includes a third sub-via hole and a fourth sub-via hole, the third sub-via hole penetrates the organic insulating layer 51; the fourth sub-via hole penetrates the second passivation layer 53 and the first passivation layer 52,
  • the auxiliary electrode 13 and the common electrode 20 are exposed, and the orthographic projection of the third sub-via on the substrate 60 includes the orthographic projection of the fourth sub-via on the substrate 60; the projection of the second connection pattern 43 on the substrate 60 covers the first The four sub-vias couple the auxiliary electrode 13 and the common electrode 20 .
  • the plurality of sub-pixels includes a plurality of red sub-pixels, a plurality of green sub-pixels and a plurality of blue sub-pixels. At least one red sub-pixel (R), at least one green sub-pixel (G) and at least one blue sub-pixel (B) constitute a pixel unit.
  • the third connection via hole Via3 can be set in the blue sub-pixel area, which has no influence on the overall transmittance. Taking a 23.8 FIC (Full In Cell) display panel as an example , the aperture ratio is 64% (RG) and 62.9% (B). The conventional product aperture ratio was 50.6%, and the aperture ratio increased by 26.4%. Similarly, the transmittance rate will also increase by more than 20%.
  • the auxiliary electrode 13 is insulated from the gate line 10 and is provided in the same layer and the same material.
  • the auxiliary electrode 13 and the gate line 10 are arranged in the same layer and material, so that the auxiliary electrode 13 and the gate line 10 can be formed in the same patterning process, which is conducive to simplifying the manufacturing process of the array substrate and reducing the manufacturing cost of the array substrate.
  • the array substrate and the opposite substrate 61 fabricating the array substrate and the opposite substrate 61 first, wherein a driving circuit layer, 20 layers of common electrodes, 40 layers of pixel electrodes, and a first alignment film are formed on the array substrate, and the driving circuit layer includes the same sub-pixels as those included in the liquid crystal display panel.
  • Corresponding driving circuits, and signal lines for providing various signals to the driving circuits include a plurality of gate lines 10 and a plurality of data lines 30, and the gate lines 10 and data lines 30 are intersected to define a plurality of sub-pixels
  • the pixel electrode 40 layer includes pixel electrodes 40 corresponding to the sub-pixels one by one, and each pixel electrode 40 is electrically connected to the output electrode 33 of the drive transistor in the corresponding drive circuit;
  • the first alignment film covers the drive circuit layer, the common electrode 20 layers and 40 layers of pixel electrodes, use rubbing cloth to align the first alignment film to form a first alignment layer with grooves in a fixed direction;
  • color resist units corresponding to sub-pixels are formed on the opposite substrate 61 , a black matrix pattern located around each color-resist unit, and a second alignment film covering the color-resist unit and the black matrix pattern, the second alignment film is aligned with a rubbing cloth to form a second alignment layer with grooves in a fixed direction .
  • the array substrate and the opposite substrate 61 are boxed, and the first alignment layer and the second alignment layer are both located in the box after the box alignment, and are perpendicular to the base of the array substrate.
  • the color resist unit is facing the opening area of the corresponding sub-pixel, and the black matrix pattern can block the non-opening area around each sub-pixel.
  • liquid crystal molecules are injected into the liquid crystal cell formed by the array substrate and the opposite substrate 61 , and the liquid crystal molecules can be ordered in accordance with the direction of the grooves in the first alignment layer and the second alignment layer.
  • ADS Advanced Super Dimension Switching technology
  • the pixel electrodes 40 included in the liquid crystal display panel are designed with slits 41, and the extending direction of the slits 41 is set to be perpendicular to the extending direction of the data lines 30 .
  • the extension direction of the groove in the alignment layer in order to ensure the normal display function of the liquid crystal display panel, it is necessary to set the extension direction of the groove in the alignment layer to be the same as the extension direction of the slit 41, that is, during the alignment process, the rubbing cloth needs to be aligned with the data
  • the direction perpendicular to the extension direction of the line 30 rubs the alignment film, so that when the rubbing cloth rubs near the data line 30, it needs to climb a slope at the data line 30, which will easily lead to a larger alignment shadow near the data line 30 (i.e.
  • the discloser of the present disclosure has found through research that by changing the extending direction of the slit 41, the extending direction of the slit 41 can be made to be the same as the extending direction of the data line 30, and the aligned groove of the alignment layer can be The direction of the groove is the same as the extending direction of the data line 30, so that during the alignment process, it is possible to avoid forming an alignment shadow area near the data line 30, thereby reducing the black matrix pattern used to shield the data line 30 from being perpendicular to the data line. 30 in the extending direction, effectively improving the aperture ratio of the liquid crystal display panel.
  • the pixel electrode 40 has a plurality of slits 41 , and at least part of the slits 41 extend along the first direction.
  • each sub-pixel includes a pixel electrode 40
  • the pixel electrode 40 can be made of indium tin oxide material, and in the manufacturing process, a plurality of slits 41 can be formed through a patterning process, and the extension of the slits 41 The direction is the same as the extending direction of the data line 30, realizing a vertical ADS (ie, H-ADS) design.
  • Each pixel electrode 40 is electrically connected to the output electrode 33 of the driving transistor in the corresponding sub-pixel driving circuit, and receives the driving signal provided by the driving transistor.
  • the process of forming an alignment layer on an array substrate includes:
  • an alignment material thin film is made on the side of the array substrate where the pixel electrode 40 is arranged, and then a rubbing cloth is used to carry out rubbing alignment along the extending direction of the slit 41 in the pixel electrode 40 (that is, the extending direction of the data line 30) to form an array substrate with grooves.
  • the extending direction of the groove is the same as the extending direction of the slit 41 .
  • the extension direction of the slit 41 in each pixel electrode 40 is set to be the same as the extension direction of the data line 30, so that the alignment material on the array substrate During the process of film alignment, a larger Rubbing Shadow region will not be formed near the data line 30 .
  • the black matrix pattern BM used to shield the data lines 30 in the opposite substrate 61 can be reduced.
  • the substrate 60 and perpendicular to the width of the extending direction of the data line 30, thereby effectively increasing the aperture ratio of the liquid crystal display panel.
  • the angle formed between the alignment direction and the extending direction of the slit 41 is between 7° and 11°
  • the endpoint values may be included.
  • the array substrate provided by the embodiments of the present disclosure further includes a black matrix pattern BM.
  • the orthographic projection of the black matrix pattern BM on the substrate 60 covers the orthographic projection of the touch signal lines 31 on the substrate 60 .
  • the boundary of the orthographic projection of the black matrix pattern BM on the substrate 60 exceeds the orthographic projection of the touch signal lines 31 on the substrate 60.
  • Projected boundaries 1.9 ⁇ m to 2.3 ⁇ m endpoint values may be included. Exemplarily, as shown in FIG. 9 , it exceeds 2.1 microns.
  • the data line 30 when the data line 30 produces a Rubbing Shadow area, and when the touch signal line 31 and the corresponding data line 30 are arranged side by side in the non-opening area, the area that needs to be shielded at the data line 30 is perpendicular to the data line 30
  • the width in the direction of extension can reach about 8.5um, resulting in a loss of about 3% of the aperture ratio.
  • the array substrate provided by the above-mentioned embodiment, by setting the extension direction of the slit 41 in the pixel electrode 40 to be the same as the extension direction of the data line 30, and insulating the touch signal line 31 and the data line 30 in different layers, And on the substrate 60, while avoiding the generation of the Rubbing Shadow area, and considering the need for box accuracy and short circuit from the touch signal line 31, thereby reducing the area that needs to be shielded at the data line 30 perpendicular to the data line 30
  • the width in the extending direction of the array substrate makes it possible to increase the pixel aperture ratio of the liquid crystal display panel by about 3% when the array substrate is formed into a liquid crystal display panel.
  • the array substrate is laid out in the above manner, which is beneficial to improve the working stability of the array substrate and reduce the layout difficulty of the array substrate in the priority layout space.
  • Embodiments of the present disclosure also provide a display device, including the array substrate provided in the above embodiments.
  • the display device can be any product or component with a display function such as a liquid crystal display panel, a TV, a monitor, a digital photo frame, a mobile phone, an electronic paper, a tablet computer, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal display panel, a TV, a monitor, a digital photo frame, a mobile phone, an electronic paper, a tablet computer, a notebook computer, a digital photo frame, a navigator, and the like.
  • the touch signal lines 31 and the data lines 30 are insulated from each other, so that there is no need to consider the short circuit problem between the data lines 30 and the touch signal lines 31, that is, there is no need to specifically limit the touch control.
  • the distance between the signal line 31 and the data line 30 on the plane of the array substrate can reduce the limitation of the touch signal line 31 and the data line 30 on the size of the non-opening area between adjacent sub-pixel columns compared with the prior art, Further, the aperture ratio of the liquid crystal display panel is increased.
  • the orthographic projection of the touch signal line 31 on the substrate 60 is set to partially overlap with the orthographic projection of the data line 30 on the substrate 60, so that the array substrate When the substrate and the opposite substrate 61 are boxed, the increase in width of the black matrix pattern in the direction perpendicular to the extension of the data line 30 due to the touch signal line 31 is reduced, thereby effectively reducing the size of the width on the opposite substrate 61.
  • the area of the black matrix graphics is set to partially overlap with the orthographic projection of the data line 30 on the substrate 60, so that the array substrate When the substrate and the opposite substrate 61 are boxed, the increase in width of the black matrix pattern in the direction perpendicular to the extension of the data line 30 due to the touch signal line 31 is reduced, thereby effectively reducing the size of the width on the opposite substrate 61.
  • the area of the black matrix graphics is set to partially overlap with the orthographic projection of the data line 30 on the substrate 60, so that the array substrate When the substrate and the opposite substrate 61 are boxed, the increase in
  • the display device provided by the embodiments of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned array substrate, which will not be repeated here.
  • the embodiment of the present disclosure also provides a preparation method of an array substrate, the preparation method comprising:
  • the data line 30 extends along the first direction
  • the extending direction of the touch signal line 31 is the same as the extending direction of the data line 30;
  • the orthographic projections on 60 overlap at least partially.
  • the touch signal line 31 and the data line 30 are insulated in different layers, so that there is no need to consider the short circuit problem between the data line 30 and the touch signal line 31, and the That is, there is no need to specifically limit the distance between the touch signal line 31 and the data line 30 on the plane where the array substrate is located, so that the difference between the touch signal line 31 and the data line 30 and adjacent sub-pixel columns can be reduced compared with the prior art.
  • the limitation of the size of the opening area further increases the opening ratio of the liquid crystal display panel.
  • the orthographic projection of the touch signal line 31 on the substrate 60 is set to partially overlap with the orthographic projection of the data line 30 on the substrate 60, so that the array substrate When the substrate and the opposite substrate 61 are boxed, the increase in width of the black matrix pattern in the direction perpendicular to the extension of the data line 30 due to the touch signal line 31 is reduced, thereby effectively reducing the size of the width on the opposite substrate 61.
  • the area of the black matrix graphics is set to partially overlap with the orthographic projection of the data line 30 on the substrate 60, so that the array substrate When the substrate and the opposite substrate 61 are boxed, the increase in width of the black matrix pattern in the direction perpendicular to the extension of the data line 30 due to the touch signal line 31 is reduced, thereby effectively reducing the size of the width on the opposite substrate 61.
  • the area of the black matrix graphics is set to partially overlap with the orthographic projection of the data line 30 on the substrate 60, so that the array substrate When the substrate and the opposite substrate 61 are boxed, the increase in
  • the preparation method includes:
  • Gate lines 10 and auxiliary electrodes 13 on the substrate 60 ; the auxiliary electrodes 13 and the gate lines 10 extend along the second direction; the auxiliary electrodes 13 are used for subsequent coupling with the common electrode 20 to reduce the transmission resistance of the common electrode 20 .
  • the first gate metal layer is formed on the substrate 60, and the first gate metal layer includes a first molybdenum metal layer, a first aluminum metal layer and a second molybdenum metal layer stacked in sequence along the direction away from the substrate 60, The thickness of the first molybdenum metal layer is The thickness of the first aluminum metal layer is The thickness of the second molybdenum metal layer is A patterning process is performed on the first gate metal layer.
  • the patterning process sequentially includes processes such as coating, exposure, development, and wet etching to form gate lines 10 and auxiliary electrodes 13 .
  • the driving circuit and the data line 30 are prepared on the substrate 60 formed with the gate line 10 and the auxiliary electrode 13 .
  • the entire layer of gate insulating layer 50 is deposited first, and the gate insulating layer 50 covers the gate line 10 and the auxiliary electrode 13; the material of the gate insulating layer 50 includes silicon nitride.
  • the thickness of the gate insulating layer 50 is
  • the active layer 70 and the source-drain metal layer of the thin film transistor are fabricated by the SSM Mask process (ie, the 4Mask process).
  • the thickness of the active layer 70 is
  • the source-drain metal layer includes a third molybdenum metal layer, a second aluminum metal layer and a fourth molybdenum metal layer stacked in sequence along the direction away from the substrate 60, and the thickness of the third molybdenum metal layer is The thickness of the second aluminum metal layer is The thickness of the fourth molybdenum metal layer is A patterning process is performed on the source-drain metal layer.
  • the patterning process sequentially includes processes such as coating, exposure, development, and wet etching to form the input electrode and output electrode 33 of the driving circuit, and the data line 30 .
  • the organic insulating layer 51 covers the output electrode 33 and the data line 30 of the driving circuit;
  • a buffer layer may be formed by depositing silicon nitride material, and the thickness of the buffer layer is Using organic resin, continue to deposit the whole layer of organic insulating layer 51 on the side of the buffer layer facing away from the substrate 60, the thickness of the organic insulating layer 51 is
  • the first sub-via hole and the third sub-via hole are formed in one patterning process; the first sub-via hole penetrates the organic insulating layer 51 and exposes at least part of the output electrode 33 of the driving circuit; the third sub-via hole penetrates the organic insulating layer 51, and expose the above-mentioned auxiliary electrode 13.
  • the organic insulating layer 51 is patterned once to form an opening penetrating through the organic insulating layer 51 and the buffer layer, and the gate insulating layer 50 is continuously etched in the opening to form a penetrating organic insulating layer 51. and the first sub-via hole of the gate insulating layer 50 .
  • indium tin oxide material can be used to make 1ITO layer, and the thickness of 1ITO layer is
  • the patterning process is performed on the 1ITO layer.
  • the patterning process includes coating, exposure, development, wet etching and other processes in sequence to form the common electrode 20.
  • the common electrode 20 is coupled to the corresponding first connection pattern 42 through the third connection via hole Via3.
  • the first passivation layer 52 covers the common electrode 20;
  • silicon nitride material is used to deposit and form the entire first first passivation layer 52 .
  • the thickness of the first first passivation layer 52 is
  • Mo material is used to make the film layer (TPM) of the touch signal line 31 .
  • the thickness of the film layer of the touch signal line 31 is A patterning process is performed on the film layer of the touch signal line 31 , and the patterning process sequentially includes processes such as coating, exposure, development, and wet etching to form the touch signal line 31 .
  • the touch signal line 31 includes a first connection pattern 42 for coupling with the 1ITO layer.
  • the second passivation layer 53 covers the touch signal line 31;
  • silicon nitride material is used to deposit and form the entire second first passivation layer 52 .
  • the thickness of the second first passivation layer 52 is .
  • the second passivation layer 53 is patterned to form the second sub-via, the fourth sub-via and the first connection via Via1;
  • a patterning process is performed on the second first passivation layer 52, and the second first passivation layer 52 is patterned to form the second sub-via holes and the second sub-vias penetrating through the first passivation layer 52.
  • the second sub-via penetrates through the first passivation layer 52 and the second passivation layer 53, and the orthographic projection of the first sub-via on the substrate 60 includes the second sub-via Orthographic projection on the substrate 60.
  • the fourth sub-via penetrates through the second passivation layer 53 and the first passivation layer 52, exposing the auxiliary electrode 13 and the common electrode 20, and the third sub-via is in the
  • the orthographic projection on the substrate 60 includes the orthographic projection of the fourth sub-via on the substrate 60;
  • the first connection via hole Via1 includes a first part and a second part, and the first part penetrates the first passivation layer 52 and the second passivation layer 53, and expose at least part of the common electrode 20;
  • the second part penetrates through the second passivation layer 53, and expose at least part of the touch signal .
  • the pixel electrode 40 is coupled with the output electrode 33 through the second connection via hole Via2, and the first connection pattern 42 is connected to the corresponding contact through the first connection via hole Via1.
  • the control signal line 31 is coupled, and the second connection pattern 43 couples the auxiliary electrode 13 and the common electrode 20 through the fourth sub-via hole.
  • the material of indium tin oxide is used to make the 2ITO layer, and the thickness of the 2ITO layer is
  • the patterning process is carried out on the 2ITO layer.
  • the patterning process includes coating, exposure, development, wet etching and other processes in sequence to form the pixel electrode 40, the second connection pattern 43 and the first connection pattern 42.
  • the pixel electrode 40 passes through the second connection via hole Via2 (Specifically, the second sub-via hole) is coupled to the output electrode 33 of the driving circuit, and the first connection pattern 42 couples the common electrode 20 to the corresponding touch signal line 31 through the first connection via hole Via1.
  • the second connection pattern 43 couples the auxiliary electrode 13 and the common electrode 20 through the fourth sub-via.
  • Embodiments according to the present disclosure are as above, and these embodiments do not describe all details in detail, nor do they limit the disclosure to only specific embodiments. Obviously many modifications and variations are possible in light of the above description. This description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present disclosure, so that those skilled in the art can make good use of the present disclosure and its modifications based on the present disclosure. The present disclosure is to be limited only by the claims, along with their full scope and equivalents.

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Abstract

一种阵列基板、显示装置，可至少部分解决现有的Incell触摸屏中，像素开口率较小的问题。阵列基板包括：基底（60）；数据线（30），设置在基底（60）上，并沿第一方向延伸；触控信号线（31），设置在基底（60）上；触控信号线（31）的延伸方向与数据线（30）的延伸方向相同；数据线（30）与触控信号线（31）异层绝缘设置，且触控信号线（31）在基底（60）上的正投影与数据线（30）在基底（60）上的正投影至少部分重叠。

Description

阵列基板、显示装置 技术领域
本公开属于触控显示技术领域，具体涉及一种阵列基板、显示装置。
背景技术
液晶显示面板主要应用于笔记本电脑、电视机等显示设备中。液晶显示面板主要包括相对设置的阵列基板和对置基板61，以及设置在该阵列基板和对置基板61之间的液晶层，液晶显示面板在工作时，在阵列基板和对置基板61之间产生驱动电场，液晶层中的液晶分子在驱动电场的驱动作用下发生偏转，从而实现液晶显示面板的显示功能。
随着显示技术的飞速发展，触摸屏的应用已经非常普及。其中，Incell(内嵌式)触摸屏将触摸屏的触控电极单元内嵌在液晶显示屏内部，可以减薄模组的厚度、降低制作成本，具有集成化、轻薄、低成本、低功耗、高画质、可以实现Multi-Touch等优势，受到消费者和面板厂商的青睐，成为未来新的发展方向。
现有技术的常规Incell触摸屏中，像素开口率较小。
公开内容
本公开至少部分解决现有的Incell触摸屏中，像素开口率较小的问题，提供一种阵列基板、显示装置。
本公开的第一方面一种阵列基板，包括：
基底；
数据线，设置在所述基底上，并沿第一方向延伸；
触控信号线，设置在所述基底上；所述触控信号线的延伸方向与所述数据线的延伸方向相同；所述数据线与所述触控信号线异层绝缘设置，且所述触控信号线在所述基底上的正投影与所述数据线在基底上的正投影至少部分重叠。
可选的，所述触控信号线位于所述数据线背离所述基底方向的一侧。
可选的，所述触控信号线在所述基底上的正投影完全覆盖所述数据线在所述基底上的正投影。
可选的，所述触控信号线具有沿所述第一方向延伸的中心线；所述数据线具有沿第一方向延伸的中心线；
所述触控信号线的中心线在所述基底上的正投影与所述数据线的中心线在所述基底上的正投影完全重叠。
可选的，所述触控信号线在第二方向上的尺寸大于所述数据线在所述第二方向上的尺寸；所述第二方向垂直于所述第一方向。
可选的，所述阵列基板还包括：多个触控电极单元，与所述触控信号线对应耦接；所述触控电极单元所在层位于所述数据线背离所述基底方向的一侧；
在第二方向上相邻两个所述触控电极单元之间的间隙在所述基底上的正投影与所述数据线在所述基底上的正投影交叠；
所述第二方向垂直于所述第一方向。
可选的，所述触控电极单元所在层位于所述触控信号线所在层与所述数据线所在层之间。
可选的，所述触控电极单元在所述基底上的正投影与所述触控信号线在所述基底上的正投影部分重叠。
可选的，所述触控电极单元在所述触控电极单元在所述基底上的正投影与所述触控信号线在所述基底上的正投影的重叠部分，在第二方向上的长度为1.5～3微米。
可选的，所述阵列基板还包括：有机绝缘层，所述有机绝缘层设置在所述数据线所在层与所述触控电极单元所述在层之间。
可选的，所述阵列基板还包括：
多条栅线、多条数据线和多个所述子像素；所述多条栅线和所述多条数据线限定出多个子像素区域，多个所述子像素对应位于所述多个子像素区域内；所述子像素包括像素电极和公共电极。
可选的，所述阵列基板包括多个触控子区域，所述触控电极单元一一对应位于所述触控子区域；每个所述触控子区域对应多个所述子像素区域；
位于同一个所述触控子区域的多个子像素的公共电极相耦接，且相耦接的所述多个公共电极复用为该触控子区域中的触控电极单元。
可选的，所述阵列基板还包括：第一钝化层；沿背离所述基底的方向，所述公共电极所在层、所述第一钝化层、所述触控信号线所在层、所述像素电极所在层依次设置；
所述公共电极通过第一连接过孔与所述触控信号线耦接，所述第一连接过孔至少贯穿所述第一钝化层。
可选的，所述阵列基板还包括：第二钝化层；所述第二钝化层位于所述触控信号线所在层背离所述基底的一侧；
所述第一连接过孔包括第一部分和第二部分，所述第一部分贯穿所述第一钝化层、所述触控信号线所在层，以及所述第二钝化层，并将所述公共电极的至少部分裸露出来；所述第二部分贯穿所述第二钝化层，并将所述触控信号的至少部分裸露出来；
所述阵列基板还包括第一连接图形，所述第一连接图形在所述基底上的正投影覆盖所述第一连接过孔的所述第一部分和所述第二部分在所述基底上的正投影，以将所述公共电极和所述触控信号线耦接。
可选的，第一连接图形与所述像素电极同层设置且材料相同。
可选的，所述子像素还包括：驱动电路，所述驱动电路的输出电极的至少部分位于所述有机绝缘层靠近所述基底的一侧；
所述像素电极通过第二连接过孔与所述输出电极耦接，所述第二连接过孔至少贯穿所述有机绝缘层、所述第一钝化层和所述第二钝化层，以将所述 驱动电路的输出电极裸露出来，使所述像素电极与所述输出电极耦接。
可选的，所述驱动电路包括：驱动晶体管；所述第二连接过孔包括：第一子过孔和第二子过孔；所述第一子过孔贯穿所述有机绝缘层，所述第二子过孔贯穿所述第一钝化层和所述第二钝化层，所述第一子过孔在所述基底上的正投影包括所述第二子过孔在所述基底上的正投影；所述像素电极通过所述第二子过孔与所述输出电极耦接。
可选的，所述阵列基板还包括：辅助电极，所述辅助电极位于沿第一方向上相邻的两个所述子像素区域之间，并沿第二方向延伸；位于同一个所述触控子区域的多个公共电极通过所述辅助电极相耦接；
所述辅助电极的导电率大于所述公共电极的导电率。
可选的，所述辅助电极与所述栅线绝缘且同层同材料设置。
可选的，所述阵列基板还包括栅绝缘层、第三连接过孔、第二连接图形；所述栅绝缘层的至少部分位于所述辅助电极背离所述基底的一侧；所述第三连接过孔包括第三子过孔和第四子过孔，所述第三子过孔贯穿所述有机绝缘层；所述第四子过孔贯穿所述第二钝化层和所述第一钝化层，将所述辅助电极和所述公共电极裸露出来，所述第三子过孔在所述基底上的正投影包括所述第四子过孔在所述基底上的正投影；所述第二连接图形在所述基底上的投影覆盖所述第四子过孔，将所述辅助电极和所述公共电极耦接。
基于上述阵列基板的技术方案，本公开的第二方面提供一种显示装置，包括上述任意一种阵列基板。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1为本公开实施例提供的一种子像素的第一布局示意图；
图2为本公开实施例提供的阵列基板中，位于同一触控子区域中的多个 公共电极的布局示意图；
图3为本公开实施例提供的阵列基板中，位于不同触控子区域中的多个公共电极的布局示意图；
图4为本公开实施例提供的另一种子像素的第二布局示意图；
图5为图1或图4中沿A1A2方向的截面示意图；
图6为图1或图4中沿B1B2方向的截面示意图；
图7为图4中沿C1C2方向的截面示意图；
图8为本公开实施例提供的输出电极与像素电极连接示意图；
图9为本公开实施例提供的黑矩阵与触控信号线、数据线之间的位置关系示意图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
在本公开中，两结构“同层设置”是指二者是由同一个材料层形成的，故它们在层叠关系上处于相同层中，但并不代表它们与基底60间的距离相等，也不代表它们与基底60间的其它层结构完全相同。
在本公开中，“构图工艺”是指形成具有特定的图形的结构的步骤，其可为光刻工艺，光刻工艺包括形成材料层、涂布光刻胶、曝光、显影、刻蚀、光刻胶剥离等步骤中的一步或多步；当然，“构图工艺”也可为压印工艺、喷墨打印工艺等其它工艺。
以下将参照附图更详细地描述本公开。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。此外，在图中可能未示出某些公知的部分。
在下文中描述了本公开的许多特定的细节，例如部件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
本公开公开了一种阵列基板，将触控电极层和触控信号线31均集成在阵列基板的内部，从而使得在利用该阵列基板制作液晶显示面板时，该液晶显示面板能够将用于实现触控功能的触控电极层和触控信号线31集成在液晶显示面板的内部，以实现内嵌式触控(Full In Cell Touch)结构的液晶触控显示面板。Full In Cell Touch结构的液晶触控显示面板，将触控功能和显示功能整合在一起，不仅能够实现一站式无缝生产，而且具有集成化、轻薄、低成本、低功耗、高画质、可以实现多类触控(即Multi-Touch)等优势。
在将触控电极层和触控信号线31均集成在阵列基板的内部时，一般将触控信号线31与阵列基板中的数据线30并排设置在相邻子像素列之间的非开口区，而由于触控信号线31与数据线30同层同材料设置，因此需要加宽位于相同非开口区中的数据线30与触控信号线31之间的距离(目前位于相同非开口区中的数据线30与触控信号线31之间的距离一般在6.5μm以上)，以避免发生数据线30与触控信号线31短路的情况，但是这种方式会降低液晶显示面板的开口率，不利于液晶显示面板显示质量的提升。
基于上述问题的存在，本公开将触控信号线31与数据线30异层绝缘设置，从而无需再考虑数据线30与触控信号线31之间的短路问题，也即不必特别限制触控信号线31与数据线30在阵列基板所在平面上的间隔距离，从而可相对现有技术减小触控信号线31和数据线30对相邻子像素列之间的非开口区尺寸的限制，进而提高液晶显示面板的开口率。
请参阅图1至图9，本公开实施例提供一种阵列基板。该阵列基板包括：基底60；数据线30，设置在基底60上，并沿第一方向延伸；触控信号线31，设置在基底60上；触控信号线31的延伸方向与数据线30的延伸方向相同；数据线30与触控信号线31异层绝缘设置，且触控信号线31在基底60上的正投影与数据线30在基底60上的正投影至少部分重叠。
其中，示例性的，第一方向包括竖直方向，第二方向包括水平方向。
示例性的，触控信号线31可分别与阵列基板中相应的触控电极单元和后续绑定在阵列基板上的芯片耦接。在将阵列基板与对置基板61对盒形成液晶显示面板后，当在液晶显示面板的触控区域发生触控操作时，触控操作能够改变阵列基板中的触控电极单元上形成的触控信号，同时触控信号线31用于将触控单元上采集到的触控信号传输至芯片，芯片根据从各触控信号线31接收到的触控信号，判断触控的具体位置。
本公开中，在设置触控信号线31时，可设置触控信号线31与数据线30不再同层设置。通过此种设置方式，不需要考虑触控信号线31与数据线30之间的短路问题，使得触控信号线31与阵列基板中数据线30在基底60所在平面内的间距无需特别进行限制，触控信号线31与数据线30二者在基底60上的投影甚至可重叠。因此，本公开提供的此种设置方式可有效缩小子像素周边的非开口区的面积，从而可将阵列基板形成的液晶显示面板的像素开口率提升6％左右。
并且，现有技术中，在配向的过程中，摩擦布需要沿着与数据线30的延伸方向垂直的方向对配向膜进行摩擦，这样摩擦布在数据线30及触控信号线31附近进行摩擦时，在数据线30处需要爬坡，容易导致在数据线30附近出现较大的配向阴影(即Rubbing Shadow)区域(现有技术中配向阴影区域的宽度大约有6.5μm左右)，该区域容易产生漏光现象。因此，像素非开口区域需要在对盒后，需要由对置基板61上的黑矩阵图形进行遮挡。在将触控信号线31设置在非开口区的情况下，在将阵列基板与对置基板61对盒时，还需要从触控信号线31考虑对盒精度，还需要增加对置基板61上的黑矩阵图形的面积，也即会导致增加黑矩阵图形在垂直于数据线30延伸方向上的宽度，造成液晶显示面板的开口率的降低。而在本公开实施例提供的阵列基板中，通过设置触控信号线31在基底60上的正投影，与数据线30在基底60上的正投影均部分重叠，使得在将阵列基板与对置基板61对盒时，基于触控信号线31的因素所导致的对黑矩阵图形在垂直于数据线30延伸方 向上的宽度增加量减小，从而有效缩小了对置基板61上的黑矩阵图形的面积。
示例性的，阵列基板中，基底60的材质可根据实际需要进行选择，示例性的，可选用玻璃基底60，但不仅限于此。
示例性的，触控信号线31分别与阵列基板中相应的触控电极单元和后续绑定在阵列基板上的芯片耦接。在将阵列基板与对置基板61对盒形成液晶显示面板后，当在液晶显示面板的触控区域发生触控操作时，触控操作能够改变阵列基板中的触控电极单元上形成的触控信号，同时触控信号线31用于将触控单元上采集到的触控信号传输至芯片，芯片根据从各触控信号线31接收到的触控信号，判断触控的具体位置。
在一些实施例中，触控信号线31位于数据线30背离基底60方向的一侧。参见图5所示，触控信号线31所在层位于数据线30所在层上方，二者之间可通过绝缘层结构绝缘隔开。本公开实施例中，通过将触控信号线31设置在数据线30背离基底60方向的一侧(图5中触控信号线31位于数据线30上方)，在阵列基板与对置基板61进行对盒之后，触控信号线31位于数据线30与液晶层之间。同时，触控信号线31与数据线30在基底60上的正投影是具有交叠的，此时，触控信号线31可对数据线30具有一定的遮蔽作用，在一定程度上屏蔽数据线30电场，从而数据线30电场对液晶的影响，进而减弱对黑矩阵遮光作用的依赖，也即可有效缩小对置基板61上的黑矩阵图形的面积。
在一些实施例中，触控信号线31在基底60上的正投影完全覆盖数据线30在基底60上的正投影。参照图9所示，本公开实施例中，触控信号线31位于数据线30靠近背离基底60的一侧，也即在阵列基板与对置基板61对盒完成之后，触控信号线31位于数据线30朝向显示面板的发光面侧。当触控信号线31在基底60上的正投影完全覆盖数据线30在基底60上的正投影时，触控信号线31可实现对数据线30的完全包裹，从而可增大对数据线30 电场的屏蔽作用，削弱数据线30电场对液晶的影响。
进一步可选的，在一些实施例中，触控信号线31具有沿第一方向延伸的中心线；数据线30具有沿第一方向延伸的中心线；触控信号线31的中心线在基底60上的正投影与数据线30的中心线在基底60上的正投影完全重叠。参照图9所示，本公开实施例中，触控信号线31的中心与数据线30的中心重叠，此时触控信号线31可将信号线包裹住，且触控信号线31对信号线的包裹程度在第二方向上是相同的，从而有利于位于触控信号线31两侧的相邻两子像素的发光显示相同，保证显示面板的显示效果。
可选的，在一些实施例中，触控信号线31在第二方向上的尺寸大于数据线30在第二方向上的尺寸。也即，触控信号线31的宽度大于数据线30的宽度。参照图9所示，本公开实施例中，触控信号线31位于数据线30靠近背离基底60的一侧，也即在阵列基板与对置基板61对盒完成之后，触控信号线31位于数据线30朝向显示面板的发光面侧。当触控信号线31的宽度大于数据线30的宽度时，触控信号线31可实现对数据线30的完全包裹，从而可增大对数据线30电场的屏蔽作用，削弱数据线30电场对液晶的影响。
示例性的，子像素对应的开口区为该子像素实际的透光区域，子像素对应的非开口区为该子像素对应的非透光区域，相同尺寸的液晶显示面板中具有的开口区的面积越大，液晶显示面板的开口率越高，液晶显示面板的显示品质越好；非开口区位于开口区的周边。示例性的，阵列基板中，子像素对应的驱动电路位于该子像素对应的非开口区，阵列基板中包括的栅线10和数据线30也均位于非开口区。
示例性的，阵列基板包括第一层氧化铟锡层(1ITO层)和第二层氧化铟锡层(2ITO层)，1ITO层位于基底60和2ITO层之间，1ITO层包括公共电极20，2ITO层包括像素电极40。
在一些示例中，阵列基板还包括：多个触控电极单元，与触控信号线31对应耦接；触控电极单元所在层位于数据线30背离基底60方向的一侧；在 第二方向上相邻两个触控电极单元之间的间隙在基底60上的正投影与数据线30在基底60上的正投影交叠；第二方向垂直于第一方向。
示例性的，阵列基板包括的触控电极层可位于阵列基板的触控区域，触控电极层包括多个相互独立的触控电极单元，多个触控电极单元可呈阵列分布，但不仅限于此。触控区域可划分为多个触控子区域，触控电极单元一一对应位于触控子区域中。值得注意，触控区域的具体位置可根据实际需要设置，示例性的，触控区域与阵列基板在形成液晶显示面板后，该液晶显示面板的整个显示区域重合；或者设置触控区域位于显示区域内，且仅与显示区域中的指定区域重合。
示例性的，每个触控电极单元与对应一条触控信号线31耦接，触控信号线31远离触控电极单元的一端可与后续绑定在阵列基板上的芯片耦接。在将阵列基板与对置基板61对盒形成液晶显示面板后，当在液晶显示面板的触控区域发生触控操作时，触控操作能够改变阵列基板中的触控电极单元上形成的触控信号，同时触控信号线31用于将触控单元上采集到的触控信号传输至芯片，芯片根据从各触控信号线31接收到的触控信号，判断触控的具体位置。
触控信号线31分别与阵列基板中相应的触控电极单元和后续绑定在阵列基板上的芯片耦接。在将阵列基板与对置基板61对盒形成液晶显示面板后，当在液晶显示面板的触控区域发生触控操作时，触控操作能够改变阵列基板中的触控电极单元上形成的触控信号，同时触控信号线31用于将触控单元上采集到的触控信号传输至芯片，芯片根据从各触控信号线31接收到的触控信号，判断触控的具体位置。
在一些实施例中，触控电极单元所在层位于触控信号线31所在层与数据线30所在层之间。参照图9所示，本公开实施例中，在将阵列基板与对置基板61对盒完成形成液晶显示面板之后，触控电极单元及触控信号线31均位于数据线30靠近液晶显示面板发光面的一侧。触控信号线31与对应的 触控电极耦接，也即液晶显示面板在工作状态下，触控信号线31与触控电极的电场状态一致。此时，可利用触控电极及触控信号线31共同屏蔽数据线30电场，使得数据线30所在区域为暗区，从而减小对液晶显示面板中液晶偏转的不良影响，提升液晶显示面板的开口率。
可选的，在一些实施例中，触控电极单元在基底60上的正投影与触控信号线31在基底60上的正投影部分重叠。本公开实施例中，当触控电极单元与触控信号线31在基底60上的正投影重叠时，触控电极单元与触控信号线31共同实现对阵列基板中数据线30电场的整面屏蔽，从而能够完全屏蔽数据线30电场形成暗区，避免液晶显示面板在数据线30所在区域漏光。因此，通过此种设置方式，无需利用黑矩阵来对阵列基板的像素非开口区进行遮挡，从而提高提升液晶显示面板的开口率。
可选的，在一些实施例中，触控电极单元在基底60上的正投影与触控信号线31在基底60上的正投影的重叠部分，在第二方向上的长度为1.5～3微米。参照图9所示，在第二方向上，也即在触控信号线31的宽度方向上，触控电极单元与触控信号线31的重叠区域的宽度可包括1.5～3微米。具体的，在实际应用中，可根据显示面板的具体尺寸、子像素的具体大小相应调整确定该尺寸，例如，触控电极单元与触控信号线31的重叠区域的宽度可为2微米。
可选的，在一些实施例中，阵列基板还包括：有机绝缘层51，有机绝缘层51设置在数据线30所在层与触控电极单元在层之间。参照图5-6所示，在垂直于基底60的方向上，数据线30、有机绝缘层51以及触控信号线31沿远离基底60的方向依次层叠设置。
示例性的，有机绝缘层51的厚度较厚，具有平坦作用。
上述设置有机绝缘层51的至少部分位于触控信号线31和公共电极20之间，增加了触控信号线31与像素电极40之间的距离，有利于改善由像素电极40工艺波动导致的触控信号线31与像素电极40之间形成的左右侧电 场不对称的问题，从而改善了开口区透过率偏差，更好的解决了由透过率偏差导致的视觉上亮暗不一，视觉上形成黑污渍或者白污渍的不良，有效提升了产品的良率。
在一些实施例中，阵列基板还包括：多条栅线10、多条数据线30和多个子像素；多条栅线10和多条数据线30限定出多个子像素区域，多个子像素对应位于多个子像素区域内；子像素包括像素电极40和公共电极20。
示例性的，数据线30与栅线10交叉设置，示例性的，数据线30沿第一方向延伸，栅线10沿第二方向延伸。阵列基板可包括多条栅线10和多条数据线30，多条栅线10和多条数据线30交叉设置，在基底60上限定出呈阵列分布的多个子像素区域，多个子像素一一对应位于多个子像素区域内。
示例性的，多个子像素可包括沿第二方向排列的多个子像素列，每列子像素列中包括沿第一方向排列的多个子像素。
示例性的，阵列基板的触控区域设置有触控电极层，触控电极层包括多个相互独立的触控电极单元，多个触控电极单元可呈阵列分布，但不仅限于此。触控区域可划分为多个触控子区域，触控电极单元一一对应位于触控子区域中。值得注意，触控区域的具体位置可根据实际需要设置，示例性的，触控区域与阵列基板在形成液晶显示面板后，该液晶显示面板的整个显示区域重合；或者设置触控区域位于显示区域内，且仅与显示区域中的指定区域重合。
示例性的，每个触控电极单元与对应一条触控信号线31耦接，触控信号线31远离触控电极单元的一端可与后续绑定在阵列基板上的芯片耦接。在将阵列基板与对置基板61对盒形成液晶显示面板后，当在液晶显示面板的触控区域发生触控操作时，触控操作能够改变阵列基板中的触控电极单元上形成的触控信号，同时触控信号线31用于将触控单元上采集到的触控信号传输至芯片，芯片根据从各触控信号线31接收到的触控信号，判断触控的具体位置。
示例性的，在设置触控信号线31时，可设置触控信号线31与数据线30在基底60上异层绝缘设置，其触控信号线31在基底60上的正投影，与阵列基板上数据线30在基底60上的正投影均重叠；这种设置方式不需要考虑触控信号线31与数据线30之间的短路问题，使得触控信号线31与阵列基板中数据线30在基底60所在平面内的间距无需特别进行限制，触控信号线31与数据线30二者在基底60上的投影甚至可重叠。因此，本公开提供的此种设置方式可有效缩小子像素周边的非开口区的面积，从而可将阵列基板形成的液晶显示面板的像素开口率提升6％左右。
并且，现有技术中，在配向的过程中，摩擦布需要沿着与数据线30的延伸方向垂直的方向对配向膜进行摩擦，这样摩擦布在数据线30及触控信号线31附近进行摩擦时，在数据线30处需要爬坡，容易导致在数据线30附近出现较大的配向阴影(即Rubbing Shadow)区域(现有技术中配向阴影区域的宽度大约有6.5μm左右)，该区域容易产生漏光现象。因此，像素非开口区域需要在对盒后，需要由对置基板61上的黑矩阵图形进行遮挡。在将触控信号线31设置在非开口区的情况下，在将阵列基板与对置基板61对盒时，还需要从触控信号线31考虑对盒精度，还需要增加对置基板61上的黑矩阵图形的面积，也即会导致增加黑矩阵图形在垂直于数据线30延伸方向上的宽度，造成液晶显示面板的开口率的降低。而在本公开实施例提供的阵列基板中，通过设置触控信号线31在基底60上的正投影，与数据线30在基底60上的正投影均部分重叠，使得在将阵列基板与对置基板61对盒时，基于触控信号线31的因素所导致的对黑矩阵图形在垂直于数据线30延伸方向上的宽度增加量减小，从而有效缩小了对置基板61上的黑矩阵图形的面积。
示例性的，子像素包括像素电极40和公共电极20，像素电极40和公共电极20沿垂直于基底60的方向相对设置，像素电极40与驱动电路耦接，接收驱动电路提供的电信号。像素电极40和公共电极20共同形成驱动电场， 以驱动液晶显示面板中的液晶偏转，实现液晶显示面板的显示功能。
在一些实施例中，阵列基板包括多个触控子区域，触控电极单元一一对应位于触控子区域；每个触控子区域对应多个子像素区域；位于同一个触控子区域的多个子像素的公共电极20相耦接，且相耦接的多个公共电极20复用为该触控子区域中的触控电极单元。
本公开实施例提供的阵列基板中，可将位于同一个触控子区域中的公共电极20复用为该触控子区域中的触控电极单元，从而无需在阵列基板中额外制作触控电极单元。并且，位于同一个触控子区域中的公共电极20均耦接在一起，使得公共电极20的电阻较低，产生的损耗较小，因此，在将位于同一个触控子区域中的公共电极20复用为该触控子区域中的触控电极单元时，使得该触控电极单元的电阻较低，从而有效降低了触控信号线31上的损耗，提升了触控灵敏度，整体上提升产品竞争力及附加价值(即触控功能)。
示例性的，参照图1和图2所示，本公开实施例中，位于同一个触控子区域中的多个公共电极20可通过连接部耦接在一起。具体的，在位于同一个触控子区域中的多个公共电极20中，沿第二方向(行方向)排列的多个公共电极20通过位于相邻公共电极20之间的第一连接部21连接，可连接为一体结构；沿第二方向排列的多个公共电极20之间可通过第二连接部22连接。同时，参见图3所示，在第二方向上，位于不同触控子区域中公共电极20之间不设置第一连接部21，从而使公共电极20之间断开；在第一方向上，位于不同触控子区域中的公共电极20与第二连接部22之间断开连接，从而实现公共电极20之间的断开。示例性的，公共电极20可通过第一连接部21与触控信号线31耦接。具体的，第一连接部21在基底上的正投影覆盖第一连接过孔Via1的第一部分在基底上的正投影重叠，且第一连接过孔Via1的第一部分将第一连接部21裸露出来；第一连接过孔Via1的第二部分在基底上的正投影与触控信号线31的部分图形在基底上的正投影重叠，并 将该部分触控信号线31裸露出来。
示例性的，第一连接部21及第二连接部22可与公共电极20同层设置，且材料相同。也即，第一连接部21、第二连接部22及公共电极20可在同一次构图工艺中形成，从而简化阵列基板的制作工艺流程，降低阵列基板的制备成本。
在将位于同一个触控子区域中的公共电极20复用为该触控子区域中的触控电极单元的情况下，在利用阵列基板形成液晶显示面板后，利用该液晶显示面板实现触控显示功能的具体过程如下：
在触控阶段，触控信号线31向所耦接的公共电极20(也即触控电极单元)提供触控信号，当在液晶显示面板的触控区域发生触控操作时，触控操作发生位置处的触控电极单元对应的触控信号会发生变化，触控电极单元将该变化的触控信号通过对应的触控信号线31传输至芯片，该芯片基于该变化的触控信号判断触控操作发生的具体位置。
在显示阶段，触控信号线31向所耦接的公共电极20提供显示需要的公共电极20信号，同时阵列基板中的子像素驱动电路为对应的像素电极40提供驱动信号，从而使得在像素电极40和公共电极20之间产生驱动液晶偏转的电场，进而使得液晶显示面板实现显示功能。
在一些实施例中，阵列基板还包括：第一钝化层52；沿背离基底60的方向，公共电极20所在层、第一钝化层52、触控信号线31所在层、像素电极40所在层依次设置；公共电极20通过第一连接过孔Via1与触控信号线31耦接，第一连接过孔Via1至少贯穿第一钝化层52。作为一种实施方式，直接在第一钝化层52中形成第一连接过孔Via1，触控信号线31可直接通过第一连接过孔Via1与公共电极20连接。
在一些实施例中，阵列基板还包括：第二钝化层53；第二钝化层53位于触控信号线31所在层背离基底60的一侧；第一连接过孔Via1包括第一部分和第二部分，第一部分贯穿第一钝化层52、触控信号线31所在层，以 及第二钝化层53，并将公共电极20的至少部分裸露出来；第二部分贯穿第二钝化层53，并将触控信号的至少部分裸露出来；阵列基板还包括第一连接图形42，第一连接图形42在基底60上的正投影覆盖第一连接过孔Via1的第一部分和第二部分在基底60上的正投影，以将公共电极20和触控信号线31耦接。参见图5所示，第二钝化层53的至少部分位于触控信号线31与像素电极40之间。本实施例中，触控信号线31可通过第一连接图形42与公共电极20连接。其中，第一连接图形42在基底60上的正投影覆盖第一连接过孔Via1的第一部分以及第二部分在基底60上的正投影。本公开实施例中，可在阵列基板的制备过程中，通过一次构图工艺一次刻蚀第一钝化层52和第二钝化层53，去除位于至少部分公共电极20上方(对应第一过孔的第一部分)的第一钝化层52和第二钝化层53，以及去除位于至少部分触控信号线31(对应第一过孔的第二部分)的第二钝化层53，形成贯穿第一钝化层52和第二钝化层53的第一过孔，将公共电极20的至少部分和触控信号线31的至少部分裸露出来。也就是，基于此种设置方式，可省去对第一钝化层52的单独刻蚀步骤，节省一道掩膜工艺，从而简化阵列基板的制作工艺流程，节约阵列基板的制作成本。
在一些实施例中，第一连接图形42与像素电极40同层设置且材料相同。将第一连接图形42与像素电极40同层同材料设置，使得第一连接图形42与像素电极40能够在同一次构图工艺中形成，有利于简化阵列基板的制作工艺流程，降低阵列基板的制作成本。参照图5所示，第一连接图形42通过第一过孔的第一部分和第二部分将公共电极20和对应触控信号线31耦接。
在一些实施例中，子像素还包括：驱动电路，驱动电路的输出电极33的至少部分位于有机绝缘层51靠近基底60的一侧；像素电极40通过第二连接过孔Via2与输出电极33耦接，第二连接过孔Via2至少贯穿有机绝缘层51、第一钝化层52和第二钝化层53，以将驱动电路的输出电极33裸露出来， 使像素电极40与输出电极33耦接。
示例性的，驱动电路包括薄膜晶体管，薄膜晶体管的栅极12与相应的栅线10耦接，薄膜晶体管的输入电极与相应的数据线30耦接，薄膜晶体管的输出电极33作为驱动电路的输出电极33，输出电极33与像素电极40耦接。示例性的，输出电极33包括薄膜晶体管的源极32。
示例性的，输出电极33与数据线30和触控信号线31同层同材料设置。沿远离基底60的方向，栅绝缘层50，输出电极33，有机绝缘层51，公共电极20，第一钝化层52和像素电极40依次层叠设置。
在一些实例中，驱动电路包括：驱动晶体管；第二连接过孔Via2包括：第一子过孔和第二子过孔；第一子过孔贯穿有机绝缘层51，第二子过孔贯穿第一钝化层52和第二钝化层53，第一子过孔在基底60上的正投影包括第二子过孔在基底60上的正投影；像素电极40通过第二子过孔与输出电极33耦接。
示例性的，形成有机绝缘层51后，进行一次构图工艺，在有机绝缘层51上形成开孔，并在开孔中继续刻蚀栅绝缘层50，进而形成贯穿有机绝缘层51和栅绝缘层50的第一子过孔。然后形成第一钝化层52，进行下一次构图工艺，对第一钝化层52进行构图形成贯穿第一钝化层52的第二子过孔。需要说明，第一钝化层52的一部分位于第一子过孔内，对该一部分进行刻蚀，形成第二子过孔，第一子过孔在基底60上的正投影包围第二子过孔在基底60上的正投影，形成套孔。然后形成像素电极40，像素电极40通过第一子过孔和第二子过孔与输出电极33耦接。
值得注意，在设置第一子过孔在基底60上的正投影包围第二子过孔在基底60上的正投影的情况下，若开孔的边界在基底60上的正投影与输出电极33在基底60上的正投影不交叠，后续继续刻蚀栅绝缘层50时，会产生过刻的问题，即开孔暴露的输出电极33的边缘下面的栅绝缘层50会被刻蚀形成倒角(Undercut)，使输出电极33的边缘处下面的栅绝缘层50出现向输 出电极33下方凹陷的凹口，导致后续形成的像素电极40容易在凹口处断裂，从而导致像素电极40与驱动电路之间发生断路，驱动电路无法向像素电极40提供信号。
上述实施例提供的显示基板中，通过设置第一子过孔的边界在基底60上的正投影与输出电极33在基底60上的正投影至少部分重叠，使得第一子过孔的边界的至少部分能够位于输出电极33上，进而可以控制第二子过孔的边界的至少部分能够位于输出电极33上，这样能够避免像素电极40在输出电极33的边界处完全断开，从而保证了像素电极40与输出电极33良好的连接性能。
在一些实施例中，参照图4所示，阵列基板还包括：辅助电极13，辅助电极13位于沿第一方向上相邻的两个子像素区域之间，并沿第二方向延伸；位于同一个触控子区域的多个公共电极20通过辅助电极13相耦接；辅助电极13的导电率大于公共电极20的导电率。本公开实施例中，可在相邻子像素区域之间的非开口区设置辅助电极13，并将辅助电极13与公共电极20耦接，从而使得位于同一个触控子区域中的公共电极20的电阻较低，有效降低触控信号线31上的损耗，提升了触控灵敏度，整体上提升产品竞争力及附加价值(即触控功能)。
示例性的，公共电极20的材料可包括ITO，辅助电极13的材料可包括导电金属。通常ITO方块电阻为30Ω/方块，导电金属方块电阻为0.01Ω/方块，也即导电金属的电阻率远低于ITO的电阻率。如此一来，通过令同一个触控子区域中的公共电极20通过辅助电极13耦接，能够大大降低阵列基板中公共电极20整体的电阻，提高同一触控子区域中公共电极20的电阻均一性。
示例性的，参照图7所示，阵列基板还包括栅绝缘层50、第三连接过孔Via3、第二连接图形43；栅绝缘层50的至少部分位于辅助电极13背离基底60的一侧；第三连接过孔Via3包括第三子过孔和第四子过孔，第三子过孔 贯穿有机绝缘层51；第四子过孔贯穿第二钝化层53和第一钝化层52，将辅助电极13和公共电极20裸露出来，第三子过孔在基底60上的正投影包括第四子过孔在基底60上的正投影；第二连接图形43在基底60上的投影覆盖第四子过孔，将辅助电极13和公共电极20耦接。
示例性的，多个子像素包括多个红色子像素，多个绿色子像素和多个蓝色子像素。至少一个红色子像素(R)、至少一个绿色子像素(G)和至少一个蓝色子像素(B)构成一个像素单元。可选的，本公开实施例提供的阵列基板中，第三连接过孔Via3可设置在蓝色子像素区域中，对整体透过率无影响，以23.8FIC(Full In Cell)显示面板为例，开口率为64％(RG)、62.9％(B)，之前常规产品开口率为50.6％，开口率提升26.4％，同理透过率也会提升20％以上。
示例性的，辅助电极13与栅线10绝缘且同层同材料设置。将辅助电极13与栅线10同层同材料设置，使得辅助电极13与栅线10能够在同一次构图工艺中形成，有利于简化阵列基板的制作工艺流程，降低阵列基板的制作成本。
在利用上述实施例提供的阵列基板制作液晶显示面板时，一般包括如下过程：
先制作阵列基板和对置基板61，其中阵列基板上形成有驱动电路层、公共电极20层、像素电极40层和第一配向膜，驱动电路层包括与液晶显示面板中包括的子像素一一对应的驱动电路，以及用于为驱动电路提供各种信号的信号线，这些信号线包括多条栅线10和多条数据线30，栅线10和数据线30交叉设置，限定出多个子像素；像素电极40层包括与子像素一一对应的像素电极40，每一个像素电极40均与对应的驱动电路中的驱动晶体管的输出电极33电连接；第一配向膜覆盖驱动电路层、公共电极20层和像素电极40层，利用摩擦布对该第一配向膜进行配向，以形成具有固定方向沟槽的第一配向层；对置基板61上形成有与子像素一一对应的色阻单元，位于各色 阻单元周边的黑矩阵图形，以及覆盖色阻单元和黑矩阵图形的第二配向膜，利用摩擦布对该第二配向膜进行配向，以形成具有固定方向沟槽的第二配向层。
在制作完第一配向层和第二配向层之后，将阵列基板和对置基板61对盒，对盒后第一配向层和第二配向层均位于盒内，且在垂直于阵列基板的基底60的方向上，色阻单元与对应的子像素的开口区正对，黑矩阵图形能够遮挡各子像素周边的非开口区。
最后在由阵列基板和对置基板61形成的液晶盒内注入液晶分子，液晶分子能够按照第一配向层和第二配向层中的沟槽方向有序排列。
为了提升液晶显示面板的透过率，本公开中在制作液晶显示面板时，会将液晶显示面板采用不同的显示模式，常用的显示模式包括高级超维场转换技术(英文：Advanced Super Dimension Switch，以下简称ADS)显示模式，在一示例中，该ADS显示模式中，将液晶显示面板包括的各像素电极40采用狭缝41设计，并设置狭缝41的延伸方向与数据线30的延伸方向垂直。
在上述ADS显示模式中，为了保证液晶显示面板正常的显示功能，需要设置配向层中沟槽的延伸方向与狭缝41的延伸方向相同，即在配向的过程中，摩擦布需要沿着与数据线30的延伸方向垂直的方向对配向膜进行摩擦，这样摩擦布在数据线30附近进行摩擦时，在数据线30处需要爬坡，容易导致在数据线30附近出现较大的配向阴影(即Rubbing Shadow)区域，而由于该区域容易产生漏光现象，因此该区域需要在对盒后，需要由对置基板61上的黑矩阵图形进行遮挡，从而导致增加了黑矩阵图形在垂直于数据线30延伸方向上的宽度，降低液晶显示面板的开口率。
基于上述问题的存在，本公开的公开人经研究发现，可通过改变狭缝41的延伸的方向，使狭缝41的延伸方向与数据线30的延伸方向相同，并使配向层配向后的沟槽方向与数据线30的延伸方向相同，这样在配向的过程中，就能够避免在数据线30附近形成配向阴影区域，从而减小了用于遮挡数据 线30的黑矩阵图形在垂直于数据线30延伸方向上的宽度，有效提升了液晶显示面板的开口率。
如图1和图4所示，在一些实施例中，像素电极40具有多个狭缝41，狭缝41的至少部分沿第一方向延伸。
示例性的，每个子像素均包括像素电极40，该像素电极40可具体采用氧化铟锡材料制作，且在制作过程中，可通过构图工艺形成多个狭缝41，并使得狭缝41的延伸方向与数据线30的延伸方向相同，实现竖向ADS(即H-ADS)设计。每个像素电极40均与对应的子像素驱动电路中的驱动晶体管的输出电极33电连接，接收由驱动晶体管提供的驱动信号。
在阵列基板上形成配向层的过程包括：
先在阵列基板设置有像素电极40的一侧制作配向材料薄膜，然后利用摩擦布沿像素电极40中狭缝41的延伸方向(即数据线30的延伸方向)进行摩擦配向，形成具有沟槽的配向层，该沟槽的延伸方向与狭缝41的延伸方向相同。
根据上述阵列基板的具体结构可知，本公开实施例提供的阵列基板中，通过设置每个像素电极40中狭缝41的延伸方向与数据线30的延伸方向相同，使得在阵列基板上对配向材料薄膜配向的过程中，不会在数据线30的附近形成较大的Rubbing Shadow区域。如图9所示，这样在将上述实施例提供的阵列基板与对置基板61对盒形成液晶显示面板时，能够减小对置基板61中用于遮挡数据线30的黑矩阵图形BM在平行于基底60，且垂直于数据线30延伸方向上的宽度，从而有效提升了液晶显示面板的开口率。
示例性的，在阵列基板上对配向材料薄膜配向时，配向的方向与狭缝41的延伸方向之间形成的夹角在7°至11°之间，可以包括端点值。
示例性的，本公开实施例提供的阵列基板还包括黑矩阵图形BM。黑矩阵图形BM在基底60上的正投影覆盖触控信号线31在基底60上的正投影。
示例性的，在平行于基底60，且垂直于触控信号线31的延伸方向的方 向上，黑矩阵图形BM在基底60上的正投影的边界超出触控信号线31在基底60上的正投影的边界1.9微米至2.3微米，可以包括端点值。示例性的，如图9所示，超出2.1微米。
需要说明，图9中标记距离的数字的单位为微米。
更详细地说，当数据线30产生Rubbing Shadow区域，以及在将触控信号线31与对应的数据线30并排设置在非开口区时，数据线30处需要遮挡的区域在垂直于数据线30的延伸方向上的宽度能够达到8.5um左右，从而导致开口率会损失3％左右。因此，上述实施例提供的阵列基板中，通过设置像素电极40中的狭缝41的延伸方向与数据线30的延伸方向相同，以及将触控信号线31与数据线30在异层绝缘设置，且在基底60上的，同时避免了Rubbing Shadow区域的产生，以及从触控信号线31考虑对盒精度和短路情况的需要，从而缩小了数据线30处需要遮挡的区域在垂直于数据线30的延伸方向上的宽度，使得在将阵列基板形成液晶显示面板时，该液晶显示面板的像素开口率能够提升3％左右。
阵列基板按照上述方式布局，有利于提升阵列基板的工作稳定性，降低阵列基板在优先布局空间内的布局难度。
本公开实施例还提供了一种显示装置，包括上述实施例提供的阵列基板。
需要说明的是，显示装置可以为：液晶显示面板、电视、显示器、数码相框、手机、电子纸、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件等。
上述实施例提供的阵列基板中，将触控信号线31与数据线30异层绝缘设置，从而无需再考虑数据线30与触控信号线31之间的短路问题，也即不必特别限制触控信号线31与数据线30在阵列基板所在平面上的间隔距离，从而可相对现有技术减小触控信号线31和数据线30对相邻子像素列之间的非开口区尺寸的限制，进而提高液晶显示面板的开口率。并且，本公开实施 例提供的制备方法制作的阵列基板中，通过设置触控信号线31在基底60上的正投影，与数据线30在基底60上的正投影均部分重叠，使得在将阵列基板与对置基板61对盒时，基于触控信号线31的因素所导致的对黑矩阵图形在垂直于数据线30延伸方向上的宽度增加量减小，从而有效缩小了对置基板61上的黑矩阵图形的面积。
因此，本公开实施例提供的显示装置在包括上述阵列基板时同样具有上述有益效果，此处不再赘述。
本公开实施例还提供了一种阵列基板的制备方法，该制备方法包括：
在基底60上制作数据线30和触控信号线31；
数据线30沿第一方向延伸；
触控信号线31的延伸方向与数据线30的延伸方向相同；数据线30与触控信号线31异层绝缘设置，且触控信号线31在基底60上的正投影与数据线30在基底60上的正投影至少部分重叠。
采用本公开实施例提供的制备方法制作的阵列基板中，将触控信号线31与数据线30异层绝缘设置，从而无需再考虑数据线30与触控信号线31之间的短路问题，也即不必特别限制触控信号线31与数据线30在阵列基板所在平面上的间隔距离，从而可相对现有技术减小触控信号线31和数据线30对相邻子像素列之间的非开口区尺寸的限制，进而提高液晶显示面板的开口率。并且，本公开实施例提供的制备方法制作的阵列基板中，通过设置触控信号线31在基底60上的正投影，与数据线30在基底60上的正投影均部分重叠，使得在将阵列基板与对置基板61对盒时，基于触控信号线31的因素所导致的对黑矩阵图形在垂直于数据线30延伸方向上的宽度增加量减小，从而有效缩小了对置基板61上的黑矩阵图形的面积。
在一些实施例中，制备方法包括：
在基底60上制作栅线10和辅助电极13；辅助电极13和栅线10沿第二方向延伸；辅助电极13用于后续与公共电极20耦接，以减小公共电极20 的传输电阻。
更详细地说，在基底60上制作第一栅金属层，第一栅金属层包括沿远离基底60的方向依次层叠设置的第一钼金属层，第一铝金属层和第二钼金属层，第一钼金属层的厚度为
Figure PCTCN2022080085-appb-000001
第一铝金属层的厚度为
Figure PCTCN2022080085-appb-000002
第二钼金属层的厚度为
Figure PCTCN2022080085-appb-000003
对第一栅金属层进行构图工艺，该构图工艺依次包括镀膜、曝光、显影、湿刻等工艺，形成栅线10、辅助电极13。
在形成有栅线10和辅助电极13的基底60上制备驱动电路、数据线30。
更详细的说，本步骤中，先沉积整层的栅绝缘层50，栅绝缘层50覆盖栅线10及辅助电极13；栅绝缘层50的材料包括氮化硅。栅绝缘层50的厚度为
Figure PCTCN2022080085-appb-000004
通过SSM Mask工艺(即4Mask工艺)制作薄膜晶体管的有源层70和源漏金属层。有源层70的厚度为
Figure PCTCN2022080085-appb-000005
源漏金属层包括沿远离基底60的方向依次层叠设置的第三钼金属层，第二铝金属层和第四钼金属层，第三钼金属层的厚度为
Figure PCTCN2022080085-appb-000006
第二铝金属层的厚度为
Figure PCTCN2022080085-appb-000007
第四钼金属层的厚度为
Figure PCTCN2022080085-appb-000008
对源漏金属层进行构图工艺，该构图工艺依次包括镀膜、曝光、显影、湿刻等工艺，形成驱动电路的输入电极和输出电极33，以及数据线30。
在形成有驱动电路的基底60上制作有机绝缘层51，有机绝缘层51覆盖驱动电路的输出电极33和数据线30；
更详细的说，本公开实施例中，可采用氮化硅材料沉积形成一层缓冲层，缓冲层的厚度为
Figure PCTCN2022080085-appb-000009
采用有机树脂，在缓冲层背向基底60的一侧继续沉积整层的有机绝缘层51，有机绝缘层51的厚度为
Figure PCTCN2022080085-appb-000010
在一次构图工艺中形成第一子过孔和第三子过孔；第一子过孔贯穿有机绝缘层51，并暴露驱动电路的输出电极33的至少部分；第三子过孔贯穿有机绝缘层51，并暴露出上述辅助电极13。
更详细的说，本步骤中，对有机绝缘层51进行一次构图，形成贯穿有机绝缘层51和缓冲层的开孔，在开孔中继续刻蚀栅绝缘层50，进而形成贯 穿有机绝缘层51和栅绝缘层50的第一子过孔。
制作公共电极20；
更详细的说，本步骤中，可采用氧化铟锡材料，制作1ITO层，1ITO层的厚度为
Figure PCTCN2022080085-appb-000011
对1ITO层进行构图工艺，该构图工艺依次包括镀膜、曝光、显影、湿刻等工艺，形成公共电极20，公共电极20通过第三连接过孔Via3与对应的第一连接图形42耦接。
制作第一钝化层52，第一钝化层52覆盖公共电极20；
更详细的说，本步骤中，采用氮化硅材料，沉积形成整层的第一第一钝化层52。第一第一钝化层52的厚度为
Figure PCTCN2022080085-appb-000012
制作触控信号线31；
更详细的说，本步骤中，采用Mo材料，制作触控信号线31膜层(TPM)。触控信号线31膜层的厚度为
Figure PCTCN2022080085-appb-000013
对触控信号线31膜层进行构图工艺，该构图工艺依次包括镀膜、曝光、显影、湿刻等工艺，形成触控信号线31。其中，触控信号线31包括用于与1ITO层耦接的第一连接图形42。
制作第二钝好化层，第二钝化层53覆盖触控信号线31；
更详细的说，本步骤中，本步骤中，采用氮化硅材料，沉积形成整层的第二第一钝化层52。第二第一钝化层52的厚度为
Figure PCTCN2022080085-appb-000014
。
所第二钝化层53进行构图，形成第二子过孔、第四子过孔和第一连接过孔Via1；
更详细的说，本步骤中，对第二第一钝化层52进行一次构图工艺，对第二第一钝化层52进行构图形成贯穿第一钝化层52的第二子过孔、第四子过孔和第一连接过孔Via1。其中，第二子过孔贯穿所述第一钝化层52和所述第二钝化层53，所述第一子过孔在所述基底60上的正投影包括所述第二子过孔在所述基底60上的正投影。所述第四子过孔贯穿所述第二钝化层53和所述第一钝化层52，将所述辅助电极13和所述公共电极20裸露出来，所述第三子过孔在所述基底60上的正投影包括所述第四子过孔在所述基底60 上的正投影；第一连接过孔Via1包括第一部分和第二部分，第一部分贯穿所述第一钝化层52以及所述第二钝化层53，并将所述公共电极20的至少部分裸露出来；所述第二部分贯穿所述第二钝化层53，并将所述触控信号的至少部分裸露出来。
制作像素电极40和第一连接图形42和第二连接图形43，像素电极40通过第二连接过孔Via2与输出电极33耦接，第一连接图形42通过第一连接过孔Via1与对应的触控信号线31耦接，第二连接图形43通过所述第四子过孔将所述辅助电极13和所述公共电极20耦接。
更详细的说，本步骤中，采用氧化铟锡材料，制作2ITO层，2ITO层的厚度为
Figure PCTCN2022080085-appb-000015
对2ITO层进行构图工艺，该构图工艺依次包括镀膜、曝光、显影、湿刻等工艺，形成像素电极40、第二连接图形43和第一连接图形42，像素电极40通过第二连接过孔Via2(具体为第二子过孔)与驱动电路的输出电极33耦接，第一连接图形42通过第一连接过孔Via1将公共电极20与对应的触控信号线31耦接。第二连接图形43通过所述第四子过孔将所述辅助电极13和所述公共电极20耦接。
应当说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括要素的过程、方法、物品或者设备中还存在另外的相同要素。
依照本公开的实施例如上文，这些实施例并没有详尽叙述所有的细节，也不限制该公开仅为的具体实施例。显然，根据以上描述，可作很多的修改 和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本公开的原理和实际应用，从而使所属技术领域技术人员能很好地利用本公开以及在本公开基础上的修改使用。本公开仅受权利要求书及其全部范围和等效物的限制。

Claims (21)

  1. 一种阵列基板，包括：
    基底；
    数据线，设置在所述基底上，并沿第一方向延伸；
    触控信号线，设置在所述基底上；所述触控信号线的延伸方向与所述数据线的延伸方向相同；所述数据线与所述触控信号线异层绝缘设置，且所述触控信号线在所述基底上的正投影与所述数据线在基底上的正投影至少部分重叠。
  2. 根据权利要求1所述的阵列基板，其中，所述触控信号线位于所述数据线背离所述基底方向的一侧。
  3. 根据权利要求1所述的阵列基板，其中，所述触控信号线在所述基底上的正投影完全覆盖所述数据线在所述基底上的正投影。
  4. 根据权利要求3所述的阵列基板，其中，所述触控信号线具有沿所述第一方向延伸的中心线；所述数据线具有沿第一方向延伸的中心线；
    所述触控信号线的中心线在所述基底上的正投影与所述数据线的中心线在所述基底上的正投影完全重叠。
  5. 根据权利要求4所述的阵列基板，其中，所述触控信号线在第二方向上的尺寸大于所述数据线在所述第二方向上的尺寸；所述第二方向垂直于所述第一方向。
  6. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：多个触控电极单元，与所述触控信号线对应耦接；所述触控电极单元所在层位于所述数据线背离所述基底方向的一侧；
    在第二方向上相邻两个所述触控电极单元之间的间隙在所述基底上的正投影与所述数据线在所述基底上的正投影交叠；
    所述第二方向垂直于所述第一方向。
  7. 根据权利要求6所述的阵列基板，其中，所述触控电极单元所在层位于所述触控信号线所在层与所述数据线所在层之间。
  8. 根据权利要求6所述的阵列基板，其中，所述触控电极单元在所述基底上的正投影与所述触控信号线在所述基底上的正投影部分重叠。
  9. 根据权利要求8所述中的阵列基板，其中，所述触控电极单元在所述触控电极单元在所述基底上的正投影与所述触控信号线在所述基底上的正投影的重叠部分，在第二方向上的长度为1.5～3微米。
  10. 根据权利要求6所述的阵列基板，其中，所述阵列基板还包括：有机绝缘层，所述有机绝缘层设置在所述数据线所在层与所述触控电极单元所述在层之间。
  11. 根据权利要求10所述的阵列基板，其中，所述阵列基板还包括：
    多条栅线、多条数据线和多个所述子像素；所述多条栅线和所述多条数据线限定出多个子像素区域，多个所述子像素对应位于所述多个子像素区域内；所述子像素包括像素电极和公共电极。
  12. 根据权利要求11所述的阵列基板，其中，所述阵列基板包括多个触控子区域，所述触控电极单元一一对应位于所述触控子区域；每个所述触控子区域对应多个所述子像素区域；
    位于同一个所述触控子区域的多个子像素的公共电极相耦接，且相耦接 的所述多个公共电极复用为该触控子区域中的触控电极单元。
  13. 根据权利要求12所述的阵列基板，其中，所述阵列基板还包括：第一钝化层；沿背离所述基底的方向，所述公共电极所在层、所述第一钝化层、所述触控信号线所在层、所述像素电极所在层依次设置；
    所述公共电极通过第一连接过孔与所述触控信号线耦接，所述第一连接过孔至少贯穿所述第一钝化层。
  14. 根据权利要求13所述的阵列基板，其中，所述阵列基板还包括：第二钝化层；所述第二钝化层位于所述触控信号线所在层背离所述基底的一侧；
    所述第一连接过孔包括第一部分和第二部分，所述第一部分贯穿所述第一钝化层、所述触控信号线所在层，以及所述第二钝化层，并将所述公共电极的至少部分裸露出来；所述第二部分贯穿所述第二钝化层，并将所述触控信号的至少部分裸露出来；
    所述阵列基板还包括第一连接图形，所述第一连接图形在所述基底上的正投影覆盖所述第一连接过孔的所述第一部分和所述第二部分在所述基底上的正投影，以将所述公共电极和所述触控信号线耦接。
  15. 根据权利要求14所述的阵列基板，其中，第一连接图形与所述像素电极同层设置且材料相同。
  16. 根据权利要求13所述的阵列基板，其中，所述子像素还包括：驱动电路，所述驱动电路的输出电极的至少部分位于所述有机绝缘层靠近所述基底的一侧；
    所述像素电极通过第二连接过孔与所述输出电极耦接，所述第二连接过孔至少贯穿所述有机绝缘层、所述第一钝化层和所述第二钝化层，以将所述 驱动电路的输出电极裸露出来，使所述像素电极与所述输出电极耦接。
  17. 根据权利要求16所述的阵列基板，其中，所述驱动电路包括：驱动晶体管；所述第二连接过孔包括：第一子过孔和第二子过孔；所述第一子过孔贯穿所述有机绝缘层，所述第二子过孔贯穿所述第一钝化层和所述第二钝化层，所述第一子过孔在所述基底上的正投影包括所述第二子过孔在所述基底上的正投影；所述像素电极通过所述第二子过孔与所述输出电极耦接。
  18. 根据权利要求12所述的阵列基板，其中，所述阵列基板还包括：辅助电极，所述辅助电极位于沿第一方向上相邻的两个所述子像素区域之间，并沿第二方向延伸；位于同一个所述触控子区域的多个公共电极通过所述辅助电极相耦接；
    所述辅助电极的导电率大于所述公共电极的导电率。
  19. 根据权利要求18所述的阵列基板，其中，所述辅助电极与所述栅线绝缘且同层同材料设置。
  20. 根据权利要求18所述的阵列基板，其中，所述阵列基板还包括栅绝缘层、第三连接过孔、第二连接图形；所述栅绝缘层的至少部分位于所述辅助电极背离所述基底的一侧；所述第三连接过孔包括第三子过孔和第四子过孔，所述第三子过孔贯穿所述有机绝缘层；所述第四子过孔贯穿所述第二钝化层和所述第一钝化层，将所述辅助电极和所述公共电极裸露出来，所述第三子过孔在所述基底上的正投影包括所述第四子过孔在所述基底上的正投影；所述第二连接图形在所述基底上的投影覆盖所述第四子过孔，将所述辅助电极和所述公共电极耦接。
  21. 一种显示装置，包括如权利要求1～20中任一项所述的阵列基板。
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