WO2023028915A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2023028915A1
WO2023028915A1 PCT/CN2021/115954 CN2021115954W WO2023028915A1 WO 2023028915 A1 WO2023028915 A1 WO 2023028915A1 CN 2021115954 W CN2021115954 W CN 2021115954W WO 2023028915 A1 WO2023028915 A1 WO 2023028915A1
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WIPO (PCT)
Prior art keywords
sub
touch
metal
substrate
array substrate
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PCT/CN2021/115954
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English (en)
French (fr)
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WO2023028915A9 (zh
Inventor
王骁
尹晓峰
陈维涛
闫岩
马禹
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/115954 priority Critical patent/WO2023028915A1/zh
Priority to EP21955462.3A priority patent/EP4280037A4/en
Priority to CN202180002404.2A priority patent/CN116472514A/zh
Publication of WO2023028915A1 publication Critical patent/WO2023028915A1/zh
Publication of WO2023028915A9 publication Critical patent/WO2023028915A9/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04111—Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G06F3/04184—Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally

Definitions

  • the present disclosure relates to the technical field of touch display, and in particular, to an array substrate and a display device.
  • the Incell (embedded) touch screen embeds the touch electrode unit of the touch screen inside the liquid crystal display, which can reduce the thickness of the module and reduce the production cost.
  • the image quality and the ability to realize multi-touch (Multi-Touch) and other advantages are favored by consumers and panel manufacturers and become a new development direction in the future.
  • Embodiments of the present disclosure provide an array substrate and a display device, which can reduce defects of display products and improve the quality of display products.
  • An embodiment of the present disclosure provides an array substrate, including a base, and a plurality of gate lines extending along a first direction and a plurality of data lines extending along a second direction arranged on the base, the plurality of gate lines and The plurality of data lines intersect each other to define a plurality of sub-pixels; the array substrate further includes:
  • touch signal lines extending along the second direction, and the touch signal lines are arranged in the non-light-transmitting regions of the sub-pixels;
  • a plurality of touch electrodes insulated from each other, one of which is connected to at least one touch signal line;
  • a plurality of metal pattern units, a plurality of metal pattern units, one of the metal pattern units is set corresponding to one of the sub-pixels, and the metal pattern units are set in the non-transparent area of the corresponding sub-pixel, the metal pattern
  • the unit includes a first metal strip arranged on at least one side of the data line and extending along the second direction, the orthographic projection of the first metal strip on the substrate is the same as that of the touch signal line on the The overlapping area of the orthographic projection on the substrate is A, and the ratio of the overlapping area A to the orthographic projection area of the touch signal line on the substrate is greater than a threshold.
  • the size of the touch signal line is smaller than the size of the first metal strip.
  • the boundary of the orthographic projection of the first metal strip on the substrate exceeds the touch signal line on the substrate
  • the size of the boundary of the orthographic projection is 0.8-2.0 microns.
  • the touch signal line has a center line extending along the second direction; the first metal strip has a center line extending along the second direction; the touch signal line has a center line extending in the second direction.
  • the orthographic projection on the base completely overlaps the orthographic projection of the centerline of the first metal strip on the base.
  • the orthographic projection of the first metal strip on the substrate does not overlap with the orthographic projection of the data line on the substrate.
  • the boundary of the orthographic projection of the first metal strip on the base is the same as the orthographic projection of the data line on the base
  • the minimum distance between projected boundaries is 2.1-8 microns.
  • the metal pattern unit further includes a second metal strip, and the second metal strip includes:
  • a first sub-metal line disposed on at least one side of the gate line and extending along the first direction;
  • a second sub-metal line disposed on at least one side of the data line and extending along the second direction, wherein the first sub-metal line is connected to the second sub-metal line, and the second sub-metal line is connected to the second sub-metal line.
  • the sub-metal lines and the first metal strips are respectively disposed on opposite sides of the corresponding sub-pixels.
  • the first metal strip and the second metal strip are arranged on the same layer, and the first metal strip and the second metal strip in the same metal pattern unit are arranged on the second metal strip.
  • each of the touch electrodes includes a plurality of touch sub-electrodes, and the orthographic projection of the touch sub-electrodes on the substrate is the same as the orthographic projection of the gate lines and the data lines on the substrate. Project non-overlapping regions;
  • the first sub-metal wires between the plurality of metal pattern units are connected to the first sub-metal wires through the first bridge part provided on the same layer or different layer with the first metal strip.
  • Two openings, and at least one metal pattern unit is coupled to at least one of the touch sub-electrodes in the touch electrodes; among different touch electrodes, the first metal pattern unit between multiple metal pattern units Between the sub-metal wires, they are disconnected and not connected through the second opening;
  • the first metal strip and the second metal strip of at least one row of the metal pattern units arranged in the second direction pass through the same layer as the first metal strip Or the second bridging part arranged in different layers is connected to the first opening, and the first metal strip is coupled to the corresponding touch signal line; the adjacent touch signal lines in the second direction
  • the metal pattern units are not connected between the control electrodes.
  • At least one column of the first metal strips arranged in the second direction is coupled to the corresponding touch signal line, and all the touch electrodes corresponding to the The first metal strips are not coupled to the touch signal lines that do not correspond to the touch electrodes, so that the metal pattern units are not connected between adjacent touch electrodes in the second direction. connect;
  • At least two columns of the first metal strips arranged in the second direction are respectively connected to different touch signal lines, and the touch electrodes not corresponding to the touch electrodes
  • the first metal strip connected to the signal line is disconnected from the second metal strip in the touch electrode through the first opening, so that the adjacent touch electrodes in the second direction
  • the metal pattern units are not connected between the control electrodes.
  • each of the touch electrodes includes a plurality of touch sub-electrodes, and the orthographic projection of the touch sub-electrodes on the substrate is the same as the orthographic projection of the gate lines and the data lines on the substrate. Project non-overlapping regions;
  • the first sub-metal wires between the plurality of metal pattern units are connected to the first sub-metal wires through the first bridge part provided on the same layer or different layer with the first metal strip.
  • two openings, and at least one metal pattern unit is coupled to at least one of the touch sub-electrodes in the touch electrodes;
  • the first metal strip and the second metal strip in at least one row of the metal pattern units arranged in the second direction pass through the first metal strip
  • the second bridging portion arranged in the same layer or different layers connects the first opening, and the first metal strip between at least one row of the first metal strip and the second metal strip arranged in the second direction Once the port is disconnected, it will not be connected;
  • At least two rows of metal pattern units arranged in the second direction are respectively connected to different touch signal lines, between different touch electrodes, through the first Once the port is disconnected and not connected.
  • the first metal strip of one metal pattern unit and the second sub-metal line of the other metal pattern unit are located opposite to the same data line.
  • the boundary between the boundary of the orthographic projection on the base and the boundary of the orthographic projection of the data line on the base is the same.
  • the array substrate further includes a pixel electrode and a common electrode disposed in the sub-pixel, wherein the touch sub-electrode is multiplexed as the common electrode.
  • the boundary of the orthographic projection of the data line on the base and the pixel electrodes in two sub-pixels adjacent to the data line The distance between the boundaries of the orthographic projections on the substrate is equal; the boundary of the orthographic projection of the data line on the substrate and the distance between the common electrodes in the two sub-pixels adjacent to the data line on the substrate The distance between the boundaries of the orthographic projection is equal.
  • the array substrate further includes: an organic insulating layer; the touch signal line and the data line are arranged in the same layer and made of the same material, and the organic insulating layer is arranged on the layer where the data line is located and the layer where the data line is located. Between the layers where the touch electrodes are located.
  • the array substrate further includes: a gate insulating layer and a passivation layer;
  • the layer where the metal pattern unit is located the gate insulating layer, the layer where the touch signal line and the data line are located, the organic insulating layer, the layer where the touch control electrode is located, The passivation layer and the layer where the pixel electrode is located are sequentially arranged;
  • the touch electrode is coupled to the second metal strip through a first connection via hole, and the first connection via hole at least penetrates through the passivation layer, the organic insulating layer and the gate insulating layer;
  • the touch signal line is coupled to the first metal strip through a second connecting via hole, and the second connecting via hole at least penetrates through the passivation layer, the organic insulating layer and the gate insulating layer.
  • the first connection vias include first sub-vias and second sub-vias
  • the first sub-via penetrates through the passivation layer, exposing part of the touch electrode
  • the second sub-via hole penetrates through the organic insulating layer and the gate insulating layer, exposing a part of the second metal strip;
  • the array substrate further includes a first connection pattern, and the orthographic projection of the first connection pattern on the substrate covers the first sub-vias and the second self-vias of the first connection vias.
  • the orthographic projection on the substrate is used to couple the touch electrode and the second metal strip.
  • the first connection pattern and the pixel electrode are arranged in the same layer and made of the same material.
  • the second connection vias include third sub-vias and fourth sub-vias;
  • the third sub-via penetrates through the passivation layer and partially exposes the touch signal line;
  • the fourth sub-via penetrates through the organic insulating layer and the gate insulating layer, exposing part of the first metal strip;
  • the array substrate further includes a second connection pattern, and the orthographic projection of the second connection pattern on the substrate covers the third sub-via and the fourth sub-via of the second connection via.
  • the orthographic projection on the substrate is used to couple the touch signal line to the first metal strip.
  • the array substrate further includes: a driving circuit, at least part of an output electrode of the driving circuit is located on a side of the organic insulating layer close to the substrate;
  • the pixel electrode is coupled to the output electrode through a third connection via hole, and the third connection via hole at least penetrates through the organic insulating layer and the passivation layer to expose the output electrode of the driving circuit , coupling the pixel electrode to the output electrode.
  • the driving circuit includes: a driving transistor; the third connection via hole includes: a fifth sub-via hole and a sixth sub-via hole; the fifth sub-via hole penetrates through the organic insulating layer, and the The sixth sub-via penetrates through the passivation layer, the orthographic projection of the fifth sub-via on the substrate includes the orthographic projection of the sixth sub-via on the substrate; the pixel electrode passes through the The third connection via hole is coupled to the output electrode.
  • each of the pixel electrodes includes a plurality of slits extending along the second direction.
  • An embodiment of the present disclosure also provides a display device, including an array substrate and an opposite substrate, and a liquid crystal layer arranged between the array substrate and the opposite substrate, wherein the array substrate is An array substrate provided by an embodiment of the present disclosure.
  • the opposite substrate is provided with a black matrix
  • the orthographic projection of the black matrix on the array substrate is located in the non-transparent area of the sub-pixel, and is parallel to the base and perpendicular to the In the direction of the second direction, the distance between the boundary of the orthographic projection of the black matrix on the substrate and the boundary of the orthographic projection of the pixel electrodes in two sub-pixels adjacent to the black matrix on the substrate Equal; the distance between the boundary of the orthographic projection of the black matrix on the substrate and the boundary of the orthographic projection of the common electrodes in two sub-pixels adjacent to the black matrix on the substrate is equal.
  • the touch signal line and the data line are arranged in parallel, and the touch signal line is located in the non-light-transmitting area between adjacent sub-pixels, so that the touch signal line can be connected with the
  • the data lines are jointly covered by the black matrix on the opposite substrate, which can solve the problem of uneven electric field between the touch signal line and the left and right electrodes in the related art when the touch signal line is located in the middle of the sub-pixel, and reduce stain defects phenomenon;
  • the touch signal line can be at least partially covered by the metal pattern unit, and the metal pattern unit can also play a light-shielding effect, weakening the dependence on the black matrix light-shielding effect, thereby reducing the amount of light on the opposite substrate.
  • the graphic shading area of the black matrix is arranged in parallel, and the touch signal line is located in the non-light-transmitting area between adjacent sub-pixels, so that the touch signal line can be connected with the
  • the data lines are jointly covered by the black matrix on the opposite substrate, which can solve the problem of
  • FIG. 1 shows a schematic layout of sub-pixels in an array substrate provided by an embodiment of the present disclosure
  • FIG. 2 shows a schematic diagram of the positional relationship between the black matrix and the touch signal lines and data lines along the C1-C2 direction in FIG. 1;
  • FIG. 3 shows a schematic layout diagram of a plurality of metal pattern units located in the same touch sub-region and metal pattern units in different touch sub-regions in the array substrate provided by some embodiments of the present disclosure
  • Fig. 4 is a schematic cross-sectional view along the D1-D2 direction in Fig. 1;
  • Fig. 5 is a schematic cross-sectional view along the A1-A2 direction in Fig. 1;
  • Fig. 6 is a schematic cross-sectional view along the B1-B2 direction in Fig. 1;
  • FIG. 7 is a schematic diagram of a manufacturing process of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram showing the layout of multiple metal pattern units located in the same touch sub-region and metal pattern units in different touch sub-regions in the array substrate provided by other embodiments of the present disclosure
  • FIG. 9 shows a schematic layout diagram of a plurality of metal pattern units located in the same touch sub-region and metal pattern units in different touch sub-regions in an array substrate provided by other embodiments of the present disclosure.
  • two structures "set in the same layer” means that the two structures are formed by the same material layer, so they are in the same layer in the layered relationship, but it does not mean that the distance between them and the substrate is equal, and also It does not mean that they are exactly the same as other layer structures between the substrates.
  • patterning process refers to the step of forming a structure with a specific pattern, which can be a photolithography process.
  • the photolithography process includes forming a material layer, coating photoresist, exposing, developing, etching, photolithography, etc.
  • One or more steps in steps such as resist stripping; of course, the “patterning process” can also be other processes such as embossing process, inkjet printing process, etc.
  • Thin Film Transistor Thin Film Field Effect Transistor
  • the touch screen can be divided into four categories, which are resistive, capacitive, infrared, and surface acoustic wave.
  • the most widely used are resistive and capacitive. Since the capacitive type can realize the widest application of multi-type touch (Multi-Touch), their disadvantages are mainly high cost, relatively heavy, etc., and low cost, light and thin have become a new trend in the current touch field.
  • the capacitive scheme includes two methods of self-capacitance touch and mutual-capacitance touch.
  • the self-capacitance touch method is to divide the transparent conductive layer used as the common (VCOM) electrode on the array substrate into several squares as touch electrodes, and use one end of the touch signal line (Tx line) to communicate with the touch electrode through a via hole. The other end is connected to the drive integrated circuit.
  • VCOM common
  • Tx line touch signal line
  • the drive integrated circuit can determine the position of the touch point by detecting the fluctuation of the capacitance value, thereby realizing touch control. Function.
  • FIC capacitive touch screen pixels adopt the Tx In Dot design, that is, the Tx line is located in the middle of the sub-pixel, so there are the following problems: the pixel electrode in each sub-pixel includes multiple pixels There is a gap (Slit) between adjacent pixel grid bars, and the Tx line is in the middle of the pixel electrode gap, without blocking the black matrix (BM) on the color film substrate of the box.
  • the embodiments of the present disclosure provide an array substrate and a display device, which can reduce defects of display products and improve the quality of display products.
  • the array substrate provided by the embodiments of the present disclosure integrates touch electrodes and touch signal lines inside the array substrate, so that when the array substrate is used to manufacture a liquid crystal display panel, the liquid crystal display panel can be used to realize touch Functional touch electrodes and touch signal lines are integrated inside the liquid crystal display panel to realize a liquid crystal touch display panel with a full in cell touch (Full In Cell Touch) structure.
  • the liquid crystal touch display panel with Full In Cell Touch structure integrates touch function and display function, not only can realize one-stop seamless production, but also has the characteristics of integration, thinness, low cost, low power consumption and high image quality. , can realize multi-type touch (ie Multi-Touch) and other advantages.
  • an embodiment of the present disclosure provides an array substrate.
  • the array substrate provided by the embodiment of the present disclosure includes a substrate 100, a plurality of gate lines 200 extending in a first direction and a plurality of data lines 300 extending in a second direction arranged on the substrate 100, a plurality of gate lines 200 and a plurality of The data lines 300 cross each other to define a plurality of sub-pixels 400; the array substrate further includes:
  • a plurality of metal pattern units one metal pattern unit is arranged corresponding to one sub-pixel, and the metal pattern unit is arranged in the non-transparent area of the corresponding sub-pixel, and the metal pattern unit is arranged on at least one side of the data line and extends along the second direction
  • the first metal strip, the overlapping area of the orthographic projection of the first metal strip on the substrate and the orthographic projection of the touch signal line on the substrate is A, and the ratio of the overlapping area A to the orthographic projection area of the first metal strip on the substrate greater than the threshold.
  • the first direction includes a vertical direction
  • the second direction includes a horizontal direction
  • coupling is performed between at least part of the first metal strip and the touch signal line.
  • the coupling method between the first metal strip and the touch signal line can be, by overlapping a part of the first metal strip with a part of the touch signal line, and overlapping the touch signal line through a via hole in the overlapping area. Connect to achieve the purpose of connecting.
  • the overlapping area of the orthographic projection of the first metal strip on the substrate and the orthographic projection of the touch signal line on the substrate is B
  • the threshold value is the overlapping area B
  • the ratio of the orthographic projection area of the first metal strip on the substrate for example, the threshold value may be 5%-10%, 10-20%, or 30%-60%.
  • the overlapping area of the orthographic projection of the first metal strip on the substrate and the orthographic projection of the touch signal line on the substrate is A greater than the threshold value, that is to say, the first metal strip is In addition to overlapping with the touch signal line, there are other overlapping areas.
  • the touch signal lines 500 can be respectively coupled to the corresponding touch electrodes 600 in the array substrate and the chips subsequently bonded on the array substrate. After the array substrate and the opposite substrate are combined to form a liquid crystal display panel, when a touch operation occurs in the touch area of the liquid crystal display panel, the touch operation can change the touch signal formed on the touch electrode 600 in the array substrate.
  • the touch signal line 500 is used to transmit the touch signal collected on the touch unit to the chip, and the chip judges the specific position of the touch according to the touch signal received from each touch signal line 500 .
  • the opening area corresponding to the sub-pixel 400 is the actual light-transmitting area of the sub-pixel 400
  • the non-opening area corresponding to the sub-pixel 400 is the non-light-transmitting area corresponding to the sub-pixel 400.
  • Liquid crystals of the same size The larger the area of the opening area in the display panel, the higher the opening ratio of the liquid crystal display panel, and the better the display quality of the liquid crystal display panel; the non-opening area is located around the opening area.
  • the opening area corresponding to the sub-pixel 400 is the actual light-transmitting area of the sub-pixel 400
  • the non-opening area corresponding to the sub-pixel 400 is the non-light-transmitting area corresponding to the sub-pixel 400
  • the non-transparent area is located at the periphery of the light-transmissive area.
  • the driving circuit corresponding to the sub-pixel 400 is located in the non-transmissive area corresponding to the sub-pixel 400, and the gate line 200 and the data line 300 in the array substrate are also located in the non-transmissive area.
  • the touch signal line 500 can be set parallel to and adjacent to the data line 300, both of which are located in the non-light-transmitting area of the sub-pixel 400.
  • the touch electrode 600 can also be multiplexed as a common electrode (Vcom), and correspondingly, the touch signal line 500 can also be multiplexed as a common electrode line.
  • Vcom common electrode
  • the touch signal line 500 provides a touch driving signal to the touch electrode 600 and receives a touch feedback signal; in the display stage, the touch signal line 500 provides a Vcom signal to the touch electrode 600 to provide The signal required by the common electrode when displaying.
  • the touch electrodes 600 are multiplexed as common electrodes and the touch signal lines 500 are multiplexed as common electrode lines, the thickness of the array substrate is reduced, and when the array substrate is applied to a touch display panel, the size of the touch display panel is reduced. thickness of.
  • the touch electrodes 600 may also be electrically connected to the metal pattern units 700, that is to say, a resistor is connected in parallel to the touch electrodes 600. Therefore, the resistance of the touch electrode 600 can be reduced, and the load of the touch signal line 500 can be reduced, which is beneficial to the touch response.
  • the touch electrodes 600 are multiplexed as common electrodes, it is equivalent to reducing the resistance of the common electrodes.
  • the overlapping area of the orthographic projection of the first metal strip on the substrate and the orthographic projection of the touch signal line on the substrate is A
  • the ratio of the overlapping area A to the area of the orthographic projection of the touch signal line on the substrate is greater than a threshold
  • the first metal strip 710 also plays a light-shielding function, which reduces the dependence on the black matrix light-shielding effect to a certain extent, that is, can effectively reduce the area of the black matrix pattern on the opposite substrate, thereby increasing the aperture ratio.
  • the material of the base 100 can be selected according to actual needs, for example, a glass substrate can be selected, but not limited thereto.
  • the size of the touch signal line 500 is smaller than the size of the first metal strip 710 . That is to say, the width of the touch signal line 500 is smaller than the width of the first metal strip 710 .
  • the first metal strip 710 can be located on the side of the touch signal line 500 close to the substrate 100, that is, after the array substrate 10 and the opposite substrate 20 are aligned, the touch signal The wire 500 is located on the side of the first metal strip 710 facing the light-emitting surface of the display panel.
  • the width of the first metal strip 710 is greater than that of the touch signal line 500 , the first metal strip 710 can completely wrap the touch signal line 500 .
  • the boundary of the orthographic projection of the first metal strip 710 on the substrate 100 exceeds the boundary of the orthographic projection of the touch signal line 500 on the substrate 100.
  • the size of the boundary is 0.8-2.0 microns. Specifically, in practical applications, the size can be adjusted and determined according to the specific size of the display panel and the specific size of the sub-pixel 400. For example, the width of the overlapping area where the boundary of the first metal strip 710 exceeds the touch signal line 500 can be 0.95 microns.
  • the minimum distance between the touch signal line 500 and the data line 300 can be 4-6 microns, correspondingly, the first The minimum distance between the boundary of the orthographic projection of the metal strip 710 on the substrate and the boundary of the orthographic projection of the data line 300 on the substrate is 2.1-8 microns.
  • the size can be adjusted and determined according to the manufacturing process capability, the specific size of the display panel, and the specific size of the sub-pixel 400.
  • the minimum distance between the touch signal line 500 and the data line 300 can be 5.05 microns
  • the minimum distance between the first metal strip 710 and the data line 300 may be 4.1 microns.
  • the orthographic projection of the first metal strip 710 on the substrate 100 completely covers the orthographic projection of the touch signal line 500 on the substrate 100 .
  • the light-shielding effect on the touch signal lines 500 can be further increased.
  • the touch signal line 500 has a center line extending along the second direction; the first metal strip 710 has a center line extending along the second direction; the touch signal line 500 has a center line extending along the second direction;
  • the orthographic projection of the centerline on the substrate 100 completely overlaps the orthographic projection of the centerline of the first metal strip 710 on the substrate 100 .
  • the center of the touch signal line 500 overlaps with the center of the first metal strip 710.
  • the first metal strip 710 is equivalent to completely wrapping the touch signal line 500, and
  • the degree of wrapping of the touch signal line 500 by the first metal strip 710 is the same in the first direction, which is beneficial to the same luminous display of the adjacent two sub-pixels 400 located on both sides of the touch signal line 500, and ensures the display panel. display effect.
  • the orthographic projection of the metal pattern unit 700 on the substrate 100 does not overlap with the orthographic projection of the data line 300 on the substrate 100 . In this way, the influence of the metal pattern unit 700 on the electric field of the data line 300 can be avoided.
  • the array substrate 10 includes a first indium tin oxide layer (1ITO layer) and a second indium tin oxide layer (2ITO layer), the 1ITO layer is located between the substrate 100 and the 2ITO layer, and the 1ITO layer includes a common electrode 600, 2
  • the ITO layer includes the pixel electrode 620.
  • the touch electrode 600 can be located in the touch area of the array substrate 10, and the touch electrode 600 includes a plurality of independent sub-touch electrodes 610, and the plurality of touch electrodes 600 can be distributed in an array, or That is to say, the touch area can be divided into a plurality of touch sub-areas T, and the touch electrodes 600 are located in the touch sub-areas T in one-to-one correspondence. But it doesn't stop there.
  • Each touch electrode 600 includes a plurality of touch sub-electrodes 610, and the orthographic projection of the touch sub-electrodes 610 on the substrate 100 has no overlapping area with the orthographic projections of the gate lines 200 and data lines 300 on the substrate 100; the same touch electrode
  • Each touch sub-electrode 610 in 600 is connected together, and is connected with a corresponding touch signal line 500 , and different touch electrodes 600 are disconnected from each other without being connected.
  • the orthographic projections of the data lines 300 and the gate lines 200 on the substrate 100 have no overlapping area with the orthographic projections of the touch sub-electrodes 610 on the substrate 100, in this way, it is avoided that the touch electrodes 600 affect the data lines 300 and the gates. signal on line 200.
  • a plurality of touch sub-electrodes 610 in the touch electrode 600 are connected together through conductive wires made on the same layer as the touch electrode 600. Since the material of the touch electrode 600 is generally ITO or IZO, etc., Therefore, the resistance on the conductive line is large.
  • multiple touch sub-electrodes 610 in the same touch electrode 600 can be connected together through the metal pattern unit 700 and the touch signal line 500.
  • the metal pattern unit 700 The metal pattern unit 700 is electrically connected to the touch electrode 600 , and the resistance of the touch electrode 600 can be reduced because the resistance of the metal pattern unit 700 is lower than that of ITO or IZO.
  • the specific position of the touch area can be set according to actual needs.
  • the touch area overlaps with the entire display area of the array substrate 10 after the liquid crystal display panel is formed; or the touch area is located in the display area, And only coincide with the specified area in the display area. That is to say, for the multiple sub-pixels 400 on the array substrate 10, each sub-pixel 400 may be provided with a touch sub-electrode 610; A touch sub-electrode 610 is provided.
  • the metal pattern unit 700 can be fabricated separately, not on the same layer as the existing pattern layer on the array substrate 10 , or can be fabricated on the same layer as the existing pattern layer on the array substrate 10 .
  • the metal pattern unit 700 and the gate line 200 may be fabricated in the same layer, that is, the metal pattern unit 700 and the gate line 200 are made of the same layer and material.
  • the metal pattern unit 700 and the gate line 200 can be manufactured simultaneously, thereby simplifying the manufacturing process of the array substrate 10 .
  • the metal pattern unit 700 and the gate line 200 are of the same layer and material, the metal pattern unit 700 and the gate line 200 have no overlapping area.
  • the touch signal lines 500 are connected to reduce the resistance of the touch electrodes 600, and at the same time, it is necessary to realize the electrical connection between the touch sub-electrodes 610 in the same touch electrode 600 and the disconnection between different touch electrodes 600 .
  • the metal pattern unit 700 further includes a second metal strip 720
  • the second metal strip 720 includes: a first sub-metal line 721 and a second sub-metal line 722,
  • the first sub-metal line 721 is disposed on at least one side of the gate line and extends along the first direction;
  • the second sub-metal line 722 is disposed on at least one side of the data line and extends along the second direction, wherein the first sub-metal line 721 and The second sub-metal line 722 is connected, and the second sub-metal line 722 and the first metal strip 711 are separately disposed on opposite sides of the corresponding sub-pixel.
  • the metal pattern unit 700 includes a first metal strip 710 and a second metal strip 720, and the second metal strip 720 includes a first sub-metal line 721 and a second sub-metal line 722, so that the metal pattern unit 700 surrounds the sub-metal line
  • the opening area of the pixel is set so that the light-shielding function of the metal pattern unit 700 can be utilized, and even the black matrix 21 does not need to be set.
  • the first metal strip 710 and the second metal strip 720 are arranged on the same layer, and the first metal strip 710 and the second metal strip 720 in the same metal pattern unit 700 There are first openings 730 in two directions; there is a second opening 740 in the first direction between the two first sub-metal lines 721 of different metal pattern units 700 .
  • the first sub-metal lines 721 between a plurality of adjacent metal pattern units 700 along the first direction pass through the same layer as the first metal strip 710 Or the first bridge portion 741 arranged in different layers is connected to the second opening 740, and at least one metal pattern unit is coupled with at least one touch sub-electrode in the touch electrode; different touch controls adjacent to the first direction Among the electrodes, the first sub-metal wires 721 between the plurality of metal pattern units 700 are disconnected and not connected through the second opening 740;
  • the first metal strip 710 and the second metal strip 720 of at least one row of metal pattern units arranged in the second direction are connected by a second bridge arranged on the same layer or a different layer as the first metal strip 710.
  • the portion 742 is connected to the first opening 730, and the first metal strip 710 is coupled to the corresponding touch signal line 500; between adjacent touch electrodes 600 in the second direction, the metal pattern unit 700 is not connected.
  • the material of the common electrode may include ITO, and the material of the metal pattern unit 700 may include conductive metal.
  • the resistivity of conductive metal is much lower than that of ITO.
  • the multiple metal pattern units 700 located in the same touch sub-region T can be coupled together through bridges.
  • FIG. 3 shows a schematic layout diagram of a plurality of metal pattern units located in the same touch sub-region and metal pattern units in different touch sub-regions in the array substrate provided by some embodiments of the present disclosure.
  • the adjacent metal pattern units 700 arranged along the first direction (row direction) pass through the second A bridging portion 741 is connected, and the first bridging portion 741 is located between the first sub-metal lines of two adjacent metal pattern units, and may be arranged on the same layer as the first sub-metal lines, that is, two adjacent metal pattern units
  • the first bridging part 741 may also be arranged in a different layer from the first sub-metal line, and be connected through a via hole, so as to realize the same touch electrode connection in the row direction, while different touch electrodes
  • the metal pattern units 700 between the control sub-regions T are disconnected in the row direction through the first opening 730;
  • the first opening is connected between the first metal strip and the second metal strip 720 through the second bridging portion 742 arranged on the same layer or a different layer as the first metal strip, wherein the The second bridging portion 742 is located between the first sub-metal line 721 and the first metal strip 711 of the same metal pattern unit 700, and may be arranged on the same layer as the first sub-metal line, that is, the second bridge portion of two adjacent metal pattern units.
  • a sub-metal line is connected as a whole, or the second bridging portion 742 can also be arranged in a different layer from the first sub-metal line, connected through a via hole, and at least one column arranged in the second direction in the same touch sub-region T
  • the first metal strips can be respectively connected to the same touch signal line (that is, the touch signal line corresponding to the touch sub-area) through via holes (the circular dotted line area O in the figure is the position of the via hole), and There is no coupling between other non-corresponding touch signal lines (that is, touch signal lines that do not correspond to the touch sub-area), so that metal pattern units in the same touch sub-area can pass through in the column direction
  • the corresponding touch signal lines are connected, but in the column direction, because the first metal strip is only connected to the corresponding touch signal lines, but not connected to the non-corresponding touch signal lines, so that the adjacent ones in the second direction
  • the metal graphic units are not connected between the touch electrodes. .
  • the first bridging portion 741 and the second bridging portion 742 may not be fabricated on the same layer as the existing pattern layer on the array substrate 10, or may be fabricated on the same layer as the existing pattern layer on the array substrate 10.
  • the first bridging portion 741 and the second bridging portion 742 can be fabricated on the same layer as the gate line 200 . That is, the first bridging portion 741 and the second bridging portion 742 are of the same layer and material as the gate line 200 .
  • the metal pattern unit 700 and the gate line 200 can be manufactured simultaneously, thereby simplifying the manufacturing process of the array substrate 10 .
  • the first metal strip 710 and the second metal strip 720 in the metal pattern units in each touch sub-area are connected through the first connecting bridge provided on the same layer or different layers.
  • the strip 710 and the touch signal line 500 are not all connected through the via hole, only the touch signal line and the touch electrode corresponding to the touch sub-region where the first metal strip 710 is located are connected through the via hole.
  • the touch signal lines and the touch electrodes are not connected, that is, by controlling the on-off between the first metal strip 710 and different touch signal lines, the division of the touch electrodes in the column direction is realized.
  • the first metal strip 710 and the second The metal strips 720 are all connected; in some other embodiments, as shown in FIG. 9 , in a plurality of metal pattern units in the same touch sub-area, between the first metal strip and the second metal pattern unit of some metal pattern units connection, the first metal strip and the second metal strip of another part of the metal pattern unit are disconnected and not connected through the first opening 730 .
  • FIG. 8 shows a schematic layout diagram of a plurality of metal pattern units located in the same touch sub-region and metal pattern units in different touch sub-regions in the array substrate provided by other embodiments of the present disclosure.
  • the first sub-metal lines between the multiple metal pattern units are connected to the second openings through the first bridge part set on the same layer or different layer with the first metal strip.
  • at least one metal pattern unit is coupled to at least one touch sub-electrode in the touch electrode; in different touch electrodes, between the first sub-metal lines between a plurality of metal pattern units, through the second disconnection The port is disconnected and not connected;
  • At least two rows of first metal strips arranged in the second direction are respectively connected to different touch signal lines through via holes (the dotted circle area O in the figure is the via hole position), and are connected to different touch signal lines.
  • the first metal strip connected to the touch signal line not corresponding to the control electrode is disconnected from the second metal strip in the touch electrode through the first opening, so that the Between the adjacent touch electrodes, the metal pattern units are not connected.
  • the adjacent second metal strips 720 are connected in the row direction, and by controlling whether the second openings 740 are connected, the touch electrode segmentation in the row direction is realized;
  • the first metal strips 710 and the touch signal lines 500 are all connected through via holes. At this time, by controlling whether the first opening 730 is connected, the corresponding touch signal lines and touch control lines are realized.
  • the electrodes are connected, and the non-corresponding touch signal lines are not connected to the touch electrodes, so as to realize the partitioning of the touch electrodes in the column direction.
  • the first metal strip 710 of one metal pattern unit 700 and the first metal strip 710 of another metal pattern unit 700 are located on opposite sides of the same data line 300, and in a direction parallel to the substrate 100 and perpendicular to the second direction, the boundary of the orthographic projection on the substrate 100 is the same as that of the data line 300 on the substrate 100 The distance between the boundaries of the orthographic projection is the same.
  • the orthographic projections of the first sub-metal lines 721 and the second sub-metal lines 722 on the substrate 100 are projected by the corresponding black matrix 21 on the opposite substrate 20
  • the orthographic projection of the shading strip on the substrate 100 is completely covered.
  • the boundary of the orthographic projection of the black matrix 21 on the substrate 100 exceeds the boundary of the orthographic projection of the first metal strip 710 on the substrate 100 by 1 to 3
  • the size can be adjusted and determined according to the specific size of the display panel and the specific size of the sub-pixel 400.
  • the size of the boundary of the orthographic projection on the substrate 100 is 1.5 microns.
  • the size of the boundary of the orthographic projection of the black matrix 21 on the substrate 100 beyond the boundary of the orthographic projection of the second metal strip 720 on the substrate 100 is 1 ⁇ 3 microns.
  • the size can be adjusted and determined according to the specific size of the display panel and the specific size of the sub-pixel 400.
  • the boundary of the orthographic projection of the black matrix 21 on the substrate 100 exceeds
  • the size of the boundary of the orthographic projection on 100 is 1.5 microns.
  • the boundary of the orthographic projection of the data line 300 on the substrate 100 and the two sub-pixels 400 adjacent to the data line 300 The distance between the boundary of the orthographic projection of the pixel electrode 620 on the substrate 100 is equal; The distance between the boundaries of the orthographic projection on is equal.
  • the 1st ITO and 2nd ITO can be symmetrical with respect to the data line 300, that is, the distance between the left and right sides of the data line 300 and the electrodes is equal, so that the difference in parasitic capacitance between the data line 300 and the left and right electrodes can be reduced. bad.
  • the array substrate 10 further includes: an organic insulating layer 810; the touch signal line 500 and the data line 300 are arranged on the same layer and made of the same material, and the organic insulating layer 810 is arranged on the layer where the data line 300 is located and the touch electrode 600 between the layers.
  • the thickness of the organic insulating layer 810 is relatively thick, and has a flattening effect.
  • the above arrangement of at least part of the organic insulating layer 810 is located between the touch signal line 500 and the common electrode increases the distance between the touch signal line 500 and the pixel electrode 620, which is beneficial to improve the touch control caused by the process fluctuation of the pixel electrode 620.
  • the left and right electric fields formed between the signal line 500 and the pixel electrode 620 are asymmetrical, thereby improving the transmittance deviation of the opening area, and better solving the visually inconsistent brightness and darkness caused by the transmittance deviation.
  • the formation of black stains or white stains can effectively improve the yield of products.
  • the liquid crystal display panel is used to realize The specific process of the touch display function is as follows:
  • the touch signal line 500 provides a touch signal to the coupled common electrode (that is, the touch electrode 600).
  • the position where the touch operation occurs The touch signal corresponding to the touch electrode 600 unit at the location will change, and the touch electrode 600 unit transmits the changed touch signal to the chip through the corresponding touch signal line 500, and the chip judges the The specific position where the touch operation occurs;
  • the touch signal line 500 provides the common electrode signal required for display to the coupled common electrode, and at the same time, the sub-pixel 400 driving circuit in the array substrate 10 provides the corresponding pixel electrode 620 with The driving signal generates an electric field between the pixel electrode 620 and the common electrode to drive the deflection of the liquid crystal, so that the liquid crystal display panel realizes the display function.
  • the array substrate 10 further includes: a gate insulating layer (GI layer) 820 and a passivation layer 830; 820, the layer where the touch signal line 500 and the data line 300 are located, the organic insulating layer (ORG) 810, the layer where the touch electrode 600 is located, the passivation layer (PVX) 830, and the layer where the pixel electrode 620 is located are arranged in sequence; the touch electrode 600 passes through The first connection via hole Via1 is coupled to the metal pattern unit 700, the first connection via hole Via1 at least penetrates through the passivation layer 830, the organic insulating layer 810 and the gate insulation layer 820; the touch signal line 500 is connected to the metal pattern unit 700 through the second connection via hole Via2 The metal pattern units are coupled, and the second connection via hole Via2 at least penetrates the passivation layer 830 , the organic insulating layer 810 and the gate insulating layer 820 .
  • GI layer gate insulating layer
  • ORG organic insulating layer
  • the first connection via hole Via1 includes a first sub-via hole and a second sub-via hole; the first sub-via hole penetrates the passivation layer 830 and partially exposes the touch electrode 600; The sub via hole penetrates the organic insulating layer 810 and the gate insulating layer 820, and partially exposes the metal pattern unit 700; the array substrate 10 also includes a first connection pattern 910, and the orthographic projection of the first connection pattern 910 on the substrate 100 covers the first connection Orthographic projections of the first sub-via hole and the second sub-via hole Via1 on the substrate 100 are used to couple the touch electrode 600 and the metal pattern unit 700 .
  • the second connection via Via2 includes a third sub-via and a fourth sub-via;
  • the third sub-via hole penetrates the passivation layer 830, and partially exposes the touch signal line 500; the fourth sub-via hole penetrates the organic insulating layer 810 and the gate insulating layer 820, and partially exposes the metal pattern unit 700; the array substrate 10 also Including the second connection pattern 920, the orthographic projection of the second connection pattern 920 on the substrate 100 covers the orthographic projection of the third sub-via hole and the fourth sub-via hole of the second connection via hole Via2 on the substrate 100, so that the touch The signal line 500 is coupled to the metal pattern unit 700 .
  • the touch electrode 600 can be connected to the metal pattern through the first connection pattern 910 .
  • the orthographic projection of the first connection pattern 910 on the substrate 100 covers the orthographic projections of the first sub-via and the second sub-via of the first connection via Via1 on the substrate 100 .
  • a patterning process can be performed first to remove the via hole (the first sub-via hole corresponding to the first via hole) on the organic insulating layer 810, so as to expose some contacts.
  • the gate insulating layer 820 and passivation layer 830 above the metal pattern unit 700 can be removed at the same time to expose part of the metal pattern unit.
  • the separate etching step for the gate insulating layer 820 can be omitted, and a mask process can be saved, thereby simplifying the manufacturing process of the array substrate 10 and saving the manufacturing cost of the array substrate 10 .
  • both the first connection pattern 910 and the second connection pattern 920 can be arranged on the same layer as the pixel electrode 620 and made of the same material.
  • the first connection pattern 910, the second connection pattern 920 and the pixel electrode 620 are arranged on the same layer and the same material, so that the first connection pattern 910, the second connection pattern 920 and the pixel electrode 620 can be formed in the same patterning process, which is beneficial to simplify
  • the manufacturing process flow of the array substrate 10 reduces the manufacturing cost of the array substrate 10 .
  • the first connection pattern 910 and the second connection pattern 920 can also be made separately.
  • the array substrate 10 further includes: a driving circuit, at least part of the output electrode 840 of the driving circuit is located on the side of the organic insulating layer 810 close to the substrate 100 ; the pixel electrode 620 The output electrode 840 is coupled through the third connection via hole Via3, and the third connection via hole Via3 at least penetrates the organic insulating layer 810 and the passivation layer 830 to expose the output electrode 840 of the driving circuit, so that the pixel electrode 620 and the output electrode 840 coupling.
  • the driving circuit includes: a driving transistor; the third connection via Via3 includes: a fifth sub-via and a sixth sub-via; the fifth sub-via penetrates the organic insulating layer 810, and the sixth sub-via penetrates the passivation Layer 830 , the orthographic projection of the fifth sub-via on the substrate 100 includes the orthographic projection of the sixth sub-via on the substrate 100 ; the pixel electrode 620 is coupled to the output electrode 840 through the third connection via Via3 .
  • the gate of the thin film transistor is coupled to the corresponding gate line 200
  • the input electrode of the thin film transistor is coupled to the corresponding data line 300
  • the output electrode 840 of the thin film transistor is used as the output electrode 840 of the driving circuit
  • the output electrode 840 is connected to the The pixel electrode 620 is coupled.
  • the output electrode 840 includes a source of a thin film transistor.
  • the output electrode 840 and the data line 300 and the touch signal line 500 are provided in the same layer and material. As shown in FIGS. 1 to 9 , along the direction away from the substrate 100 , the gate insulating layer 820 , the output electrode 840 , the organic insulating layer 810 , the common electrode, the passivation layer 830 and the pixel electrode 620 are sequentially stacked.
  • a patterning process is performed to form an opening on the organic insulating layer 810 to form a fifth sub-via hole penetrating through the organic insulating layer 810 .
  • a passivation layer 830 is formed, and a next patterning process is performed to pattern the passivation layer 830 to form a sixth sub-via hole penetrating through the passivation layer 830 .
  • a part of the passivation layer 830 is located in the fifth sub-via, and the part is etched to form the sixth sub-via, and the orthographic projection of the fifth sub-via on the substrate 100 surrounds the sixth sub-via. Orthographic projection on the substrate 100, forming a trellis.
  • the pixel electrode 620 is formed, and the pixel electrode 620 is coupled to the output electrode 840 through the first sub-via hole and the second sub-via hole.
  • the orthographic projection of the boundary of the fifth sub-via on the substrate 100 and the orthographic projection of the output electrode 840 on the substrate 100 are at least partially overlapped so that at least part of the boundary of the fifth sub-via Part of it can be located on the output electrode 840, and then it can be controlled that at least part of the boundary of the sixth sub-via can be located on the output electrode 840, which can prevent the pixel electrode 62040 from being completely disconnected at the boundary of the output electrode 840, thereby ensuring the pixel electrode. 620 and the output electrode 840 have good connection performance.
  • a plurality of slits are provided on the pixel electrode.
  • the direction is the same, that is, during the alignment process, the orientation cloth needs to rub the alignment film along the direction perpendicular to the extension direction of the data line, so that when the orientation cloth rubs near the data line, it needs to climb a slope at the data line, which is easy
  • a large alignment shadow (Rubbing Shadow) area appears near the data line, and because this area is prone to light leakage, this area needs to be blocked by the black matrix pattern on the opposite substrate after the box is aligned, so that As a result, the width of the black matrix pattern in the direction perpendicular to the extension of the data lines is increased, and the aperture ratio of the liquid crystal display panel is reduced.
  • the discloser of the present disclosure has found through research that by changing the extending direction of the slit, the extending direction of the slit can be made to be the same as the extending direction of the data line, and the direction of the groove after the alignment layer is aligned is the same as that of the data line.
  • the extension direction of the data lines is the same, so that during the alignment process, an alignment shadow area can be avoided near the data lines, thereby reducing the width of the black matrix pattern used to block the data lines in the direction perpendicular to the extension direction of the data lines.
  • the aperture ratio of the liquid crystal display panel is effectively improved.
  • each pixel electrode 620 includes a plurality of slits 620a extending along the second direction.
  • the slit 620a extends along the second direction means that the slit 620a extends along the second direction as a whole.
  • the pixel electrode 620 includes one domain, in this case, the slit 620a is linear; in other embodiments, the pixel electrode 620 is divided into two domains, in this case, as shown in FIG. 1 , each slit 620a includes a first sub-slit and a second sub-slit, and the angle ⁇ between the first sub-slit and the second sub-slit is an obtuse angle.
  • the process of forming an alignment layer on an array substrate includes:
  • the direction in which the grooves extend is the same as the direction in which the slits extend.
  • the slit 620a extends along the second direction, when the alignment film is aligned with the alignment cloth, the alignment cloth moves along the second direction, so that during the alignment process of the alignment material film on the array substrate, no Larger Rubbing Shadow area. Since there is no light leakage problem caused by the Rubbing Shadow area, the width of the light-shielding strips in the pattern of the black matrix 21 along the first direction can be designed to be narrower, thereby effectively increasing the aperture ratio.
  • the pixel electrode since the second metal strip 720 is connected to the touch electrode through the first connection via hole Via1, in order to avoid the first connection via hole, the pixel electrode The shape is adaptable to have a notch, and correspondingly, the length of the slit 620a in the region corresponding to the notch along the second direction is smaller than the length of the slit 620a in other regions along the second direction.
  • the length of the slit is less than the length of the five slits on the side close to the first metal strip, and the upper ends and lower ends of the five slits on the side close to the first metal strip are aligned.
  • FIG. 1 shows a schematic layout of sub-pixels in an array substrate provided by an embodiment of the present disclosure.
  • the bends and turns in the traces are sharp corners.
  • the bending and steering parts of the wiring should be rounded.
  • the embodiment of the present disclosure also provides a display device, including an array substrate 10 and an opposite substrate 20 disposed opposite to each other, and a liquid crystal layer disposed between the array substrate 10 and the opposite substrate 20.
  • the array substrate 10 provides an embodiment of the present disclosure. array substrate 10.
  • the opposite substrate 20 is provided with a black matrix 21, the orthographic projection of the black matrix 21 on the array substrate is located in the non-light-transmitting area of the sub-pixel, and in a direction parallel to the base and perpendicular to the second direction, the black matrix is on the base
  • the boundary of the orthographic projection of the black matrix is equal to the distance between the boundary of the orthographic projection of the pixel electrodes in the two sub-pixels adjacent to the black matrix on the substrate; the boundary of the orthographic projection of the black matrix on the substrate is equal to that The distances between the boundaries of the orthographic projections of the common electrodes in the two sub-pixels on the substrate are equal.
  • the 1st ITO and 2nd ITO can be symmetrical with respect to the black matrix 21, that is, the distance between the left and right sides of the black matrix 21 and the electrodes is equal, so the blocking effect of the black matrix on the sub-pixel will be more conducive to the light transmittance of the sub-pixel Uniformity, that is to say, is conducive to the symmetry of the pixel.
  • the display device can be any product or component with a display function such as a liquid crystal display panel, a TV, a monitor, a digital photo frame, a mobile phone, an electronic paper, a tablet computer, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal display panel, a TV, a monitor, a digital photo frame, a mobile phone, an electronic paper, a tablet computer, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned array substrate 10 , and details will not be repeated here.
  • the embodiment of the present disclosure also provides a method for manufacturing the array substrate 10, the method includes:
  • Step S01 providing a substrate 100
  • Step S02 making a plurality of gate lines 200, a plurality of data lines 300, a plurality of touch signal lines 500, a plurality of touch electrodes 600, and a metal pattern unit 700 on the substrate 100, and the plurality of gate lines 200 are along the first direction Extending, a plurality of data lines 300 extending along the second direction, a plurality of gate lines 200 and a plurality of data lines 300 intersecting to define a plurality of sub-pixels 400; a plurality of touch signal lines 500 extending in a second direction, the touch signal lines 500 is arranged in the non-transmissive area between adjacent sub-pixels 400; a plurality of touch electrodes 600 are insulated from each other; 700 corresponds to one touch electrode 600, and the touch electrode 600 is coupled to the corresponding touch signal line 500 through the corresponding metal pattern unit 700, and the orthographic projection of the metal pattern unit 700 on the substrate 100 and the touch signal line 500 on the substrate The orthographic projections on 100 overlap at least partially.
  • the touch signal line 500 and the data line 300 are arranged in parallel, and the touch signal line 500 is located in the non-transparent area between the adjacent sub-pixels 400, so that the touch
  • the control signal line 500 and the data line 300 can be covered by the black matrix 21 on the opposite substrate 20, thereby solving the problem of the touch signal line 500 existing in the middle of the sub-pixel 400 in the related art.
  • the problem of uneven electric field between the electrodes can reduce the phenomenon of stains; and the touch electrode 600 is electrically connected to the touch signal line 500 through a metal pattern, which can reduce the resistance of the touch electrode 600 and effectively reduce the touch signal line 500.
  • the touch signal line 500 can be at least partially covered by the metal graphic unit, and the metal graphic unit can also play a light-shielding effect, weakening the dependence on the black matrix 21 light-shielding effect, thereby The pattern light-shielding area of the black matrix 21 on the opposite substrate 20 can be reduced.
  • step S02 specifically includes:
  • Step S021 fabricating the gate line 200 , the gate of the driving transistor and the metal pattern unit 700 on the substrate 100 ; the metal pattern unit 700 is used for subsequent coupling with the common electrode, so as to reduce the transmission resistance of the common electrode.
  • a first gate metal layer (Gate layer) is formed on the substrate 100, the first gate metal layer includes a first molybdenum metal layer, a first aluminum metal layer and a second molybdenum metal layer, the thickness of the first molybdenum metal layer is The thickness of the first aluminum metal layer is The thickness of the second molybdenum metal layer is A patterning process is performed on the first gate metal layer.
  • the patterning process sequentially includes processes such as coating, exposure, development, and wet etching to form gate lines 200 , gates and metal pattern units 700 .
  • the metal pattern unit 700 further includes a first bridge portion 741 and a second bridge portion 742 for coupling with each metal pattern unit 700 in the same touch sub-region T.
  • Step S022 preparing a driving circuit, a data line 300 and a touch signal line 500 on the substrate 100 formed with the gate line 200 and the metal pattern unit 700 .
  • this step firstly, a whole layer of gate insulating layer 820 is deposited, and the gate insulating layer 820 covers the gate line 200, the gate and the metal pattern unit 700; the material of the gate insulating layer 820 includes silicon nitride.
  • the thickness of the gate insulating layer 820 is
  • the active layer of the thin film transistor is fabricated.
  • the thickness of the active layer is
  • the source-drain metal layer includes the third molybdenum metal layer, the second aluminum metal layer and the fourth molybdenum metal layer that are stacked in sequence along the direction away from the substrate 100, the third molybdenum metal layer Thickness is The thickness of the second aluminum metal layer is The thickness of the fourth molybdenum metal layer is A patterning process is performed on the source-drain metal layer.
  • the patterning process sequentially includes processes such as coating, exposure, development, and wet etching to form the input electrode and output electrode 840 of the driving circuit, as well as the data line 300 and the touch signal line 500 .
  • Step S023 fabricating an organic insulating layer 810 on the substrate 100 on which the driving circuit is formed, the organic insulating layer 810 covering the output electrode 840 of the driving circuit, the data line 300 and the touch signal line 500;
  • a buffer layer may be formed by depositing silicon nitride material, and the thickness of the buffer layer is Using an organic resin, continue to deposit an entire layer of organic insulating layer 810 on the side of the buffer layer facing away from the substrate 100.
  • the thickness of the organic insulating layer 810 is
  • the second sub-via, the fourth sub-via and the fifth sub-via are formed on the organic insulating layer 810.
  • the second sub-via and the fourth sub-via penetrate the organic insulating layer 810 to expose at least Part of the metal pattern unit 700; the fourth sub-via and the third sub-via; the fifth sub-via penetrates the organic insulating layer 810 and exposes at least part of the output electrode 840 of the driving circuit.
  • Step S024 making a common electrode
  • indium tin oxide material can be used to make 1ITO layer, and the thickness of 1ITO layer is A patterning process is performed on the 1ITO layer, and the patterning process sequentially includes processes such as coating, exposure, development, and wet etching to form a common electrode.
  • Step S027 making a passivation layer 830, and the passivation layer 830 covers the common electrode;
  • silicon nitride material is used to deposit and form the passivation layer 830 of the entire layer.
  • the passivation layer 830 has a thickness of
  • a patterning process is performed on the passivation layer 830, and the passivation layer 830 is patterned to form the first sub-via hole, the third sub-via hole, and the sixth sub-via hole through the passivation layer 830.
  • the first sub-via penetrates the passivation layer 830 to partially expose the touch electrode 600
  • the third sub-via penetrates the passivation layer 830 to partially expose the touch signal line 500
  • the sixth sub-via penetrates
  • the orthographic projection of the fifth sub-via on the substrate 100 includes the orthographic projection of the sixth sub-via on the substrate 100 .
  • Step S027 making the pixel electrode 620, the first connection pattern 910 and the second connection pattern 920, the orthographic projection of the first connection pattern 910 on the substrate 100 covers the first sub-via and the second self-via of the first connection via Via1
  • the orthographic projection of the hole on the substrate 100 is used to couple the touch electrode 600 and the metal pattern unit;
  • the orthographic projection of the second connection pattern 920 on the substrate 100 covers the third sub-via hole and the fourth sub-hole of the second connection via hole Via2
  • the orthographic projection of the sub-vias on the substrate 100 is used to couple the touch signal line 500 with the metal pattern unit.
  • the material of indium tin oxide is used to make the 2ITO layer, and the thickness of the 2ITO layer is
  • the patterning process is performed on the 2ITO layer, and the patterning process includes coating, exposure, development, wet etching and other processes in sequence to form the pixel electrode 620 , the first connection pattern 910 and the second connection pattern 920 .

Abstract

本公开提供一种阵列基板及显示装置，该阵列基板包括沿第一方向延伸的多条栅线和沿第二方向延伸的多条数据线，多条栅线和多条数据线相互交叉限定出多个子像素；多条沿第二方向延伸的触控信号线，触控信号线设置在子像素的非透光区；相互绝缘的多个触控电极；多个金属图形单元，一个金属图形单元对应一个子像素设置，金属图形单元设置在子像素的非透光区，金属图形单元包括设置于数据线的至少一侧且沿第二方向延伸的第一金属条，第一金属条在基底上的正投影与触控信号线在基底上的正投影的重叠面积为A，重叠面积A与第一金属条在基底上的正投影面积的比值大于阈值。本公开的阵列基板及显示装置，可达到减少显示产品不良，提升显示产品品质的目的。

Description

阵列基板及显示装置 技术领域
本公开涉及触控显示技术领域，尤其涉及一种阵列基板及显示装置。
背景技术
随着显示技术的飞速发展，触摸屏的应用已经非常普及。其中，Incell(内嵌式)触摸屏将触摸屏的触控电极单元内嵌在液晶显示屏内部，可以减薄模组的厚度、降低制作成本，具有集成化、轻薄、低成本、低功耗、高画质、可以实现多类触控(Multi-Touch)等优势，受到消费者和面板厂商的青睐，成为未来新的发展方向。
发明内容
本公开实施例提供了一种阵列基板及显示装置，可达到减少显示产品不良，提升显示产品品质的目的。
本公开实施例所提供的技术方案如下：
本公开实施例提供了一种阵列基板，包括基底、及设置在所述基底上沿第一方向延伸的多条栅线和沿第二方向延伸的多条数据线，所述多条栅线和所述多条数据线相互交叉限定出多个子像素；所述阵列基板还包括：
多条沿所述第二方向延伸的触控信号线，所述触控信号线设置在所述子像素的非透光区；
相互绝缘的多个触控电极，一个所述触控电极对应的连接至少一根触控信号线；
多个金属图形单元，多个金属图形单元，一个所述金属图形单元对应一个所述子像素设置，且所述金属图形单元设置于对应的所述子像素的非透光区，所述金属图形单元包括设置于所述数据线的至少一侧且沿所述第二方向延伸的第一金属条，所述第一金属条在所述基底上的正投影与所述触控信号线在所述基底上的正投影的重叠面积为A，所述重叠面积A与所述触控信号线在所述基底上的正投影面积的比值大于阈值。
示例性的，在平行于所述基底且垂直于所述第二方向的方向上，所述触控信号线的尺寸小于所述第一金属条的尺寸。
示例性的，在平行于所述基底且垂直于所述第二方向的方向上，所述第一金属条在所述基底上的正投影的边界超出所述触控信号线在所述基底上的正投影的边界的尺寸为0.8～2.0微米。
示例性的，所述触控信号线具有沿所述第二方向延伸的中心线；所述第一金属条具有沿第二方向延伸的中心线；所述触控信号线的中心线在所述基底上的正投影与所述第一金属条的中心线在所述基底上的正投影完全重叠。
示例性的，所述第一金属条在所述基底上的正投影与所述数据线在所述基底上的正投影不重叠。
示例性的，在平行于所述基底且垂直于所述第二方向的方向上，所述第一金属条在所述基底上的正投影的边界与所述数据线在所述基底上的正投影的边界之间的最小距离为2.1～8微米。
示例性的，所述金属图形单元还包括第二金属条，所述第二金属条包括：
设置于所述栅线的至少一侧且沿所述第一方向延伸的第一子金属线；
及，设置于所述数据线的至少一侧且沿所述第二方向延伸的第二子金属线，其中所述第一子金属线与所述第二子金属线连接，且所述第二子金属线与所述第一金属条分设于对应的所述子像素的相对两侧。
示例性的，所述第一金属条与所述第二金属条同层设置，且同一所述金属图形单元中的所述第一金属条与所述第二金属条之间在所述第二方向上具有第一断开口；不同所述金属图形单元的两个所述第一子金属线之间在所述第一方向上具有第二断开口。
示例性的，每个所述触控电极包括多个触控子电极，所述触控子电极在所述基底上的正投影与所述栅线和所述数据线在所述基底上的正投影无重叠区域；
同一所述触控电极中，多个所述金属图形单元之间的所述第一子金属线之间通过与所述第一金属条同层或异层设置的第一桥接部连接所述第二断开口，且至少一个金属图形单元与该触控电极中的至少一个所述触控子电极藕接；不同所述触控电极中，多个所述金属图形单元之间的所述第一子金属线 之间，通过所述第二断开口断开而不连接；
同一所述触控电极中，在所述第二方向上排列的至少一列所述金属图形单元的所述第一金属条与所述第二金属条之间通过与所述第一金属条同层或异层设置的第二桥接部连接所述第一断开口，且所述第一金属条与对应的所述触控信号线藕接；在所述第二方向上的相邻所述触控电极之间，所述金属图形单元不连接。
示例性的，同一所述触控电极中，在所述第二方向上排列的至少一列所述第一金属条与对应的触控信号线藕接，且该触控电极所对应的所有所述第一金属条均和与该所述触控电极不对应的触控信号线不藕接，以使得在所述第二方向上的相邻所述触控电极之间，所述金属图形单元不连接；
或者，同一所述触控电极中，在所述第二方向上排列的至少两列所述第一金属条分别连接至不同的触控信号线，与该触控电极不对应的所述触控信号线所连接的第一金属条，通过所述第一断开口与该触控电极内的第二金属条之间断开不连接，以使在所述第二方向上的相邻所述触控电极之间，所述金属图形单元不连接。
示例性的，每个所述触控电极包括多个触控子电极，所述触控子电极在所述基底上的正投影与所述栅线和所述数据线在所述基底上的正投影无重叠区域；
同一所述触控电极中，多个所述金属图形单元之间的所述第一子金属线之间通过与所述第一金属条同层或异层设置的第一桥接部连接所述第二断开口，且至少一个金属图形单元与该触控电极中的至少一个所述触控子电极藕接；
且同一所述触控电极中，在所述第二方向上排列的至少一列所述金属图形单元中的所述第一金属条与所述第二金属条之间通过与所述第一金属条同层或异层设置的第二桥接部连接所述第一断开口，在所述第二方向上排列的至少一列所述第一金属条与所述第二金属条之间的所述第一断开口不连接；
同一所述触控电极中，在所述第二方向上排列的至少两列的所述金属图形单元分别连接至不同的触控信号线，不同的所述触控电极之间，通过所述第一断开口断开而不连接。
示例性的，相邻两个所述金属图形单元中，一个所述金属图形单元的第一金属条和另一个所述金属图形单元的第二子金属线，位于同一根所述数据线的相对两侧，并在平行于所述基底且垂直于所述第二方向的方向上，在所述基底上的正投影的边界与所述数据线在所述基底上的正投影的边界之间的距离相同。
示例性的，所述阵列基板还包括设置于所述子像素内的像素电极和公共电极，其中所述触控子电极复用为所述公共电极。
示例性的，在平行于所述基底且垂直于所述第二方向的方向上，所述数据线在所述基底上的正投影的边界和与该数据线相邻两个子像素内的像素电极在所述基底上的正投影的边界之间的距离相等；所述数据线在所述基底上的正投影的边界和与该数据线相邻两个子像素内的公共电极在所述基底上的正投影的边界之间的距离相等。
示例性的，所述阵列基板还包括：有机绝缘层；所述触控信号线与所述数据线同层且同材质设置，且所述有机绝缘层设置在所述数据线所在层与所述触控电极所在层之间。
示例性的，所述阵列基板还包括：栅绝缘层和钝化层；
沿背离所述基底的方向，所述金属图形单元所在层、所述栅绝缘层、所述触控信号线和所述数据线所在层、所述有机绝缘层、所述触控电极所在层、所述钝化层、所述像素电极所在层依次设置；
所述触控电极通过第一连接过孔与所述第二金属条耦接，所述第一连接过孔至少贯穿所述钝化层、所述有机绝缘层和所述栅绝缘层；
所述触控信号线通过第二连接过孔与所述第一金属条耦接，所述第二连接过孔至少贯穿所述钝化层、所述有机绝缘层和所述栅绝缘层。
示例性的，所述第一连接过孔包括第一子过孔和第二子过孔；
所述第一子过孔贯穿所述钝化层，将所述触控电极部分裸露出来；
所述第二子过孔贯穿所述有机绝缘层和所述栅绝缘层，将所述第二金属条部分裸露出来；
所述阵列基板还包括第一连接图形，所述第一连接图形在所述基底上的正投影覆盖所述第一连接过孔的所述第一子过孔和所述第二自过孔在所述基 底上的正投影，以将所述触控电极和所述第二金属条耦接。
示例性的，所述第一连接图形与所述像素电极同层设置且材料相同。
示例性的，所述第二连接过孔包括第三子过孔和第四子过孔；
所述第三子过孔贯穿所述钝化层，将所述触控信号线部分裸露出来；
所述第四子过孔贯穿所述有机绝缘层和所述栅绝缘层，将所述第一金属条部分裸露出来；
所述阵列基板还包括第二连接图形，所述第二连接图形在所述基底上的正投影覆盖所述第二连接过孔的所述第三子过孔和所述第四子过孔在所述基底上的正投影，以将所述触控信号线和所述第一金属条耦接。
示例性的，所述阵列基板还包括：驱动电路，所述驱动电路的输出电极的至少部分位于所述有机绝缘层靠近所述基底的一侧；
所述像素电极通过第三连接过孔与所述输出电极耦接，所述第三连接过孔至少贯穿所述有机绝缘层和所述钝化层，以将所述驱动电路的输出电极裸露出来，使所述像素电极与所述输出电极耦接。
示例性的，所述驱动电路包括：驱动晶体管；所述第三连接过孔包括：第五子过孔和第六子过孔；所述第五子过孔贯穿所述有机绝缘层，所述第六子过孔贯穿所述钝化层，所述第五子过孔在所述基底上的正投影包括所述第六子过孔在所述基底上的正投影；所述像素电极通过所述第三连接过孔与所述输出电极耦接。
示例性的，每个所述像素电极包括多个沿所述第二方向延伸的狭缝。
本公开实施例还提供一种显示装置，包括相对设置的阵列基板和对置基板、以及设置在所述阵列基板和所述对置基板之间的液晶层，其特征在于，所述阵列基板为本公开实施例提供的阵列基板。
示例性的，所述对置基板上设有黑矩阵，所述黑矩阵在所述阵列基板上的正投影位于所述子像素的非透光区，且在平行于所述基底且垂直于所述第二方向的方向上，所述黑矩阵在所述基底上的正投影的边界和与与黑矩阵相邻两个子像素内的像素电极在所述基底上的正投影的边界之间的距离相等；所述黑矩阵在所述基底上的正投影的边界和与与黑矩阵相邻两个子像素内的公共电极在所述基底上的正投影的边界之间的距离相等。
本公开实施例所带来的有益效果如下：
本公开实施例所提供的阵列基板及显示装置，将触控信号线与数据线平行设置，且触控信号线位于相邻子像素之间的非透光区，这样，触控信号线可以与数据线共同被对置基板上的黑矩阵所覆盖，从而可解决相关技术中触控信号线位于子像素中间时所存在的触控信号线与左右电极之间电场不均匀的问题，减少污渍不良现象；此外，所述触控信号线可被所述金属图形单元中至少部分覆盖，所述金属图形单元还可以起到遮光作用，减弱对黑矩阵遮光作用的依赖，从而可减少对置基板上黑矩阵的图形遮光面积。
附图说明
图1表示本公开实施例提供的一种阵列基板中子像素的布局示意图；
图2表示图1中沿C1-C2方向黑矩阵与触控信号线、数据线之间的位置关系示意图；
图3表示本公开一些实施例提供的阵列基板中，位于同一触控子区域中的多个金属图形单元以及不同触控子区域中金属图形单元的布局示意图；
图4为图1中沿D1-D2方向的截面示意图；
图5为图1中沿A1-A2方向的截面示意图；
图6为图1中沿B1-B2方向的截面示意图；
图7为本公开实施例提供的阵列基板的制造过程示意图；
图8表示本公开另一些实施例提供的阵列基板中，位于同一触控子区域中的多个金属图形单元以及不同触控子区域中金属图形单元的布局示意图；
图9表示本公开另一些实施例提供的阵列基板中，位于同一触控子区域中的多个金属图形单元以及不同触控子区域中金属图形单元的布局示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中，两结构“同层设置”是指二者是由同一个材料层形成的，故它们在层叠关系上处于相同层中，但并不代表它们与衬底间的距离相等，也不代表它们与衬底间的其它层结构完全相同。
在本公开中，“构图工艺”是指形成具有特定的图形的结构的步骤，其可为光刻工艺，光刻工艺包括形成材料层、涂布光刻胶、曝光、显影、刻蚀、光刻胶剥离等步骤中的一步或多步；当然，“构图工艺”也可为压印工艺、喷墨打印工艺等其它工艺。
以下将参照附图更详细地描述本公开。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。此外，在图中可能未示出某些公知的部分。
在下文中描述了本公开的许多特定的细节，例如部件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
在对本公开实施例所提供的阵列基板及显示装置进行详细说明之前，有必要对于相关技术进行以下说明：
在相关技术中，Thin Film Transistor(薄膜场效应晶体管)是指，液晶显示器上的每一液晶象素点都是由集成在其后的薄膜晶体管来驱动。按照触摸屏 的工作原理和传输信息的介质，可以把触摸屏分为四大类，它们分别是电阻式、电容感应式、红外线式以及表面声波式，应用广泛的有电阻式和电容式，其中投射式电容式由于可以实现多类触控(Multi-Touch)应用的最广泛，它们的缺点主要是成本较高、比较厚重等，而低成本、轻薄化成为当前触控领域的新趋势。
为了实现触控面板的薄型化和轻量化，将触控面板和液晶显示面板一体化的研究日渐盛行。其中将触控面板嵌入到液晶显示面板内部的内嵌式(In-Cell)触控方案受到人们的广泛关注。
In-Cell触控技术有电阻式、电容式和光学式三种。其中电容式方案包括自电容触控和互电容触控两种方式。自电容触控方式是，将阵列基板上用作公共(VCOM)电极的透明导电层分割成若干方块作为触控电极，利用触控信号线(Tx线)一端通过过孔和触控电极连通，另一端连接至驱动集成电路，当手指触碰阵列基板时，会引起相应位置处触控电极电容值的波动，驱动集成电路通过检测电容值的波动能够确定触碰点的位置，从而实现触控功能。
完全内嵌式(Full In-Cell，简称FIC)电容触控屏像素采用Tx In Dot的设计，即，Tx线位于子像素中间位置，这样存在以下问题：每个子像素内像素电极包括多个像素栅条，相邻像素栅条之间具有间隙(Slit)，Tx线在像素电极间隙的正中间，没有对盒彩膜基板上的黑矩阵(BM)遮挡，若Tx线左右两侧的像素栅条图案发生突变，则会导致Tx线到左右两侧的像素栅条图案的距离不等，从而导致Tx线左右两侧的电场不均，产生污渍不良。
为了解决上述问题，本公开实施例提供了一种阵列基板及显示装置，能够达到减少显示产品不良，提升显示产品品质的目的。
本公开实施例提供的阵列基板，将触控电极和触控信号线均集成在阵列基板的内部，从而使得在利用该阵列基板制作液晶显示面板时，该液晶显示面板能够将用于实现触控功能的触控电极和触控信号线集成在液晶显示面板的内部，以实现内嵌式触控(Full In Cell Touch)结构的液晶触控显示面板。Full In Cell Touch结构的液晶触控显示面板，将触控功能和显示功能整合在一起，不仅能够实现一站式无缝生产，而且具有集成化、轻薄、低成本、低功 耗、高画质、可以实现多类触控(即Multi-Touch)等优势。
请参阅图1至图9，本公开实施例提供一种阵列基板。
本公开实施例提供的阵列基板包括基底100、及设置在基底100上沿第一方向延伸的多条栅线200和沿第二方向延伸的多条数据线300，多条栅线200和多条数据线300相互交叉限定出多个子像素400；阵列基板还包括：
多条沿第二方向延伸的触控信号线(Tx线)500，触控信号线500设置在子像素400的非透光区；
相互绝缘的多个触控电极600，一个触控电极对应的连接至少一根触控信号线；
多个金属图形单元，一个金属图形单元对应一个子像素设置，且金属图形单元设置于对应的子像素的非透光区，金属图形单元包括设置于数据线的至少一侧且沿第二方向延伸的第一金属条，第一金属条在基底上的正投影与触控信号线在基底上的正投影的重叠面积为A，重叠面积A与第一金属条在基底上的正投影面积的比值大于阈值。
其中，示例性的，第一方向包括竖直方向，第二方向包括水平方向。
在一些实施例中，至少部分第一金属条与触控信号线之间进行藕接。
需要说明的是，第一金属条与触控信号线之间的藕接方式可以是，通过将第一金属条的一部分区域与触控信号线的一部分区域重叠，在该重叠区域通过过孔搭接而实现藕接目的。其中，在第一金属条与触控信号线藕接处，第一金属条在基底上的正投影与触控信号线在基底上的正投影的重叠面积为B，阈值即为重叠面积B与第一金属条在基底上的正投影面积的比值，例如阈值可以为5％～10％、10～20％或者30％～60％。这样，在本公开实施例中，第一金属条在基底上的正投影与触控信号线在基底上的正投影的重叠面积为A大于阈值，也就是说，第一金属条除了在藕接处与触控信号线重叠之外，还具有其他重叠区域。
示例性的，触控信号线500可分别与阵列基板中相应的触控电极600和后续绑定在阵列基板上的芯片耦接。在将阵列基板与对置基板对盒形成液晶显示面板后，当在液晶显示面板的触控区域发生触控操作时，触控操作能够 改变阵列基板中的触控电极600上形成的触控信号，同时触控信号线500用于将触控单元上采集到的触控信号传输至芯片，芯片根据从各触控信号线500接收到的触控信号，判断触控的具体位置。
本公开提供的阵列基板中，子像素400对应的开口区为该子像素400实际的透光区域，子像素400对应的非开口区为该子像素400对应的非透光区域，相同尺寸的液晶显示面板中具有的开口区的面积越大，液晶显示面板的开口率越高，液晶显示面板的显示品质越好；非开口区位于开口区的周边。
一种示例性的实施例中，示例性的，子像素400对应的开口区为该子像素400实际的透光区域，子像素400对应的非开口区为该子像素400对应的非透光区域，相同尺寸的液晶显示面板中具有的开口区的面积越大，液晶显示面板的开口率越高，液晶显示面板的显示品质越好；非透光区位于透光区的周边。
示例性的，本公开阵列基板中，子像素400对应的驱动电路位于该子像素400对应的非透光区，阵列基板中的栅线200和数据线300也均位于非透光区。在设置触控信号线500时，可设置触控信号线500与数据线300平行且相邻，均位于子像素400的非透光区，通过这种设置方式，可以实现通过对置基板上黑矩阵同时遮挡触控信号线500和数据线300的目的，且不会再存在触控信号线500位于像素电极交叠位置而导致其左右两侧电场不均的问题，从而改善污渍不良现象。
在一些实施例中，触控电极600还可以复用为公共电极(Vcom)，相应的，触控信号线500还可以复用为公共电极线。基于此，在触控阶段，触控信号线500向触控电极600提供触控驱动信号，并接收触控反馈信号；在显示阶段，触控信号线500向触控电极600提供Vcom信号，提供显示时公共电极需要的信号。当触控电极600复用为公共电极，触控信号线500复用为公共电极线时，减小了阵列基板的厚度，在阵列基板应用于触控显示面板时，减小了触控显示面板的厚度。
本公开一些实施例中，由于阵列基板上设有多个金属图形单元700，触控电极600也可以与金属图形单元700电连接，也就是说，相当于给触控电 极600并联了一个电阻，因而可以降低触控电极600的电阻，减小了触控信号线500的负载(load)，有利于触控响应。此外，在触控电极600复用为公共电极的情况下，相当于降低了公共电极的电阻。
并且，第一金属条在基底上的正投影与触控信号线在基底上的正投影的重叠面积为A，重叠面积A与触控信号线在基底上的正投影面积的比值大于阈值，这样，第一金属条710还起到一个遮光作用，在一定程度上减弱对黑矩阵遮光作用的依赖，也即可有效缩小对置基板上的黑矩阵图形的面积，从而可以提高开口率。
本公开提供的阵列基板中，基底100的材质可根据实际需要进行选择，示例性的，可选用玻璃衬底，但不仅限于此。
示例性的，在平行于基底100且垂直于第二方向的方向上，触控信号线500的尺寸小于第一金属条710的尺寸。也就是说，触控信号线500的宽度小于第一金属条710的宽度。参照图2所示，本公开实施例中，第一金属条710可以位于触控信号线500靠近基底100的一侧，也即在阵列基板10与对置基板20对盒完成之后，触控信号线500位于第一金属条710朝向显示面板的发光面侧。当第一金属条710的宽度大于触控信号线500的宽度时，第一金属条710可实现对触控信号线500的完全包裹。
请参考图2所示，在平行于基底100且垂直于第二方向的方向上，第一金属条710在基底100上的正投影的边界超出触控信号线500在基底100上的正投影的边界的尺寸为0.8～2.0微米。具体的，在实际应用中，可根据显示面板的具体尺寸、子像素400的具体大小相应调整确定该尺寸，例如，第一金属条710的边界超出触控信号线500的重叠区域的宽度可为0.95微米。
此外，请参考图2所示，在平行于基底100且垂直于第二方向的方向上，触控信号线500与数据线300之间的最小间距可以为4～6微米，相应的，第一金属条710在基底上的正投影的边界与数据线300在基底上的正投影的边界之间的最小距离为2.1～8微米。具体的，在实际应用中，可根据制作工艺能力、显示面板的具体尺寸、子像素400的具体大小相应调整确定该尺寸，例如，触控信号线500与数据线300之间的最小间距可以为5.05微米，第一 金属条710与数据线300之间的最小间距可以为4.1微米。
示例性的，第一金属条710在基底100上的正投影完全覆盖触控信号线500在基底100上的正投影。这样，可以进一步增大对触控信号线500的遮光作用，在设计对置基板上的黑矩阵21时甚至可无需考虑黑矩阵21对触控信号线500的遮挡，以进一步提升开口率。
此外，如图1所示，在一些实施例中，触控信号线500具有沿第二方向延伸的中心线；第一金属条710具有沿第二方向延伸的中心线；触控信号线500的中心线在基底100上的正投影与第一金属条710的中心线在基底100上的正投影完全重叠。参照图2所示，本公开实施例中，触控信号线500的中心与第一金属条710的中心重叠，此时第一金属条710相当于将触控信号线500可完全包裹住，且第一金属条710对触控信号线500的包裹程度在第一方向上是相同的，从而有利于位于触控信号线500两侧的相邻两子像素400的发光显示相同，保证显示面板的显示效果。
此外，请参考图2所示，金属图形单元700在基底100上的正投影与数据线300在基底100上的正投影不重叠。这样，可以避免金属图形单元700对数据线300的电场产生影响。
示例性的，阵列基板10包括第一层氧化铟锡层(1ITO层)和第二层氧化铟锡层(2ITO层)，1ITO层位于基底100和2ITO层之间，1ITO层包括公共电极600，2ITO层包括像素电极620。
考虑到若触控电极600与数据线300、栅线200在基底100上的正投影具有重叠区域，则触控电极600上的信号可能会影响数据线300和栅线200上的信号。因此，在一些实施例中，触控电极600可位于阵列基板10的触控区域，触控电极600包括多个相互独立的子触控电极610，多个触控电极600可呈阵列分布，也就是说，触控区域可划分为多个触控子区域T，触控电极600一一对应位于触控子区域T中。但不仅限于此。
每个触控电极600包括多个触控子电极610，触控子电极610在基底100上的正投影与栅线200和数据线300在基底100上的正投影无重叠区域；同一触控电极600中的各触控子电极610连接一起，并与对应的连接一根触控 信号线500，不同触控电极600之间相互断开而不连接。
由于数据线300和栅线200在基底100上的正投影均与触控子电极610在基底100上的正投影无重叠区域，这样一来，便避免了触控电极600影响数据线300和栅线200上的信号。
在此基础上，相关技术中触控电极600中多个触控子电极610通过与触控电极600同层制作的导电线连接在一起，由于触控电极600的材料一般为ITO或IZO等，因而导电线上的电阻较大，本公开实施例中，可通过金属图形单元700和触控信号线500将同一触控电极600中的多个触控子电极610连接在一起，金属图形单元700和触控电极600相互电连接，由于金属图形单元700的电阻小于ITO或IZO的电阻，因而可以减小触控电极600的电阻。
需要说明的是，触控区域的具体位置可根据实际需要设置，示例性的，触控区域与阵列基板10在形成液晶显示面板后的整个显示区域重合；或者设置触控区域位于显示区域内，且仅与显示区域中的指定区域重合。也就是说，针对阵列基板10上的多个子像素400，可以是每个子像素400均设置有触控子电极610；也可以是部分子像素400设置有触控子电极610，部分子像素400不设置触控子电极610。
还需要说明的是，金属图形单元700可以单独制作，不与阵列基板10上已有的图案层同层制作，也可以和阵列基板10上已有的图案层同层制作。例如，一些实施例中，如图1至图3所示，金属图形单元700可以与栅线200同层制作，即金属图形单元700与栅线200同层同材料。当金属图形单元700与栅线200同层同材料时，可以同时制作金属图形单元700和栅线200，从而简化了阵列基板10的制作工艺。
在金属图形单元700与栅线200同层同材料的情况下，金属图形单元700和栅线200无重叠区域，因此设计金属图形单元700时，金属图形单元700既要满足与触控电极600与触控信号线500连接以减少触控电极600的电阻的要求，同时又需要实现同一触控电极600中各触控子电极610之间的电连接，以及不同触控电极600之间的断开。
因此，在一些实施例中，如图1和图3所示，金属图形单元700还包括 第二金属条720，第二金属条720包括：第一子金属线721和第二子金属线722，第一子金属线721设置于栅线的至少一侧且沿第一方向延伸；第二子金属线722设置于数据线的至少一侧且沿第二方向延伸，其中第一子金属线721与第二子金属线722连接，且第二子金属线722与第一金属条711分设于对应的子像素的相对两侧。
采用上述方案，金属图形单元700包括第一金属条710和第二金属条720，第二金属条720又包括第一子金属线721和第二子金属线722，这样，金属图形单元700围绕子像素的开口区设置，从而可以利用金属图形单元700的遮光作用，甚至无需设置黑矩阵21。
在一些实施例中，如图3所示，第一金属条710与第二金属条720同层设置，且同一金属图形单元700中的第一金属条710与第二金属条720之间在第二方向上具有第一断开口730；不同金属图形单元700的两个第一子金属线721之间在第一方向上具有第二断开口740。
示例性的，如图3所示，同一触控电极600中，沿第一方向相邻的多个金属图形单元700之间的第一子金属线721之间通过与第一金属条710同层或异层设置的第一桥接部741连接第二断开口740，且至少一个金属图形单元与该触控电极中的至少一个触控子电极藕接；沿第一方向相邻的不同触控电极中，多个金属图形单元700之间的第一子金属线721之间，通过第二断开口740断开而不连接；
同一触控电极600中，在第二方向上排列的至少一列金属图形单元的第一金属条710与第二金属条720之间通过与第一金属条710同层或异层设置的第二桥接部742连接第一断开口730，且第一金属条710与对应的触控信号线500藕接；在第二方向上的相邻触控电极600之间，金属图形单元700不连接。
上述方案中，公共电极的材料可包括ITO，金属图形单元700的材料可包括导电金属。通常导电金属的电阻率远低于ITO的电阻率。这样，通过令同一个触控子区域T中的公共电极通过金属图形单元700来耦接，能够大大 降低阵列基板10中公共电极整体的电阻，提高同一触控子区域T中公共电极的电阻均一性。
此外，上述方案中，参照图1至图3，位于同一个触控子区域T中的多个金属图形单元之间700可通过桥接部耦接在一起。
具体的，图3表示本公开一些实施例提供的阵列基板中，位于同一触控子区域中的多个金属图形单元以及不同触控子区域中金属图形单元的布局示意图。如图3所示，一些实施例中，在位于同一个触控子区域T中的多个金属图形单元700中，沿第一方向(行方向)排列的相邻金属图形单元700之间通过第一桥接部741连接，该第一桥接部741位于相邻两个金属图形单元的第一子金属线之间，可以是与第一子金属线同层设置，即，相邻两个金属图形单元的第一子金属线连为一体，或者，第一桥接部741也可以是与第一子金属线异层设置，并通过过孔连接，从而实现在行方向上同一触控电极连接，而不同触控子区域T之间的金属图形单元700之间则通过第一断开口730在行方向上断开不连接；
在第二方向(即列方向)上，第一金属条与第二金属条720之间通过与第一金属条同层或异层设置的第二桥接部742连接第一断开口，其中该第二桥接部742位于同一金属图形单元700的第一子金属线721与第一金属条711之间，可以是与第一子金属线同层设置，即，相邻两个金属图形单元的第一子金属线连为一体，或者，第二桥接部742也可以是与第一子金属线异层设置，并通过过孔连接，且同一触控子区域T内在第二方向上排列的至少一列第一金属条可以分别与同一触控信号线(即与该触控子区域对应的触控信号线)之间通过过孔藕接(图中圆形虚线区域O即为过孔位置)，而与其他不对应的触控信号线(即与该触控子区域不对应的触控信号线)之间不藕接，从而实现同一触控子区域内的金属图形单元之间在列方向上通过对应的触控信号线连接，而在列方向上由于第一金属条仅与对应的触控信号线连接，而与不对应的触控信号线不连接，从而使得在第二方向上的相邻触控电极之间，金属图形单元不连接。。
示例性的，第一桥接部741与第二桥接部742可以不与阵列基板10上已 有的图案层同层制作，也可以和阵列基板10上已有的图案层同层制作。例如，第一桥接部741和第二桥接部742可以与栅线200同层制作。即第一桥接部741和第二桥接部742与栅线200同层同材料。当第一桥接部741与第二桥接部742与栅线200同层同材料时，可以同时制作金属图形单元700和栅线200，从而简化了阵列基板10的制作工艺。
需要说明的是，以上仅是一种示例，该示例性实施例中，是通过在行方向上，将相邻的第二金属条720之间连接，通过控制第二断开口740是否连接，实现在行方向上的触控电极分块；
而在列方向上，将各触控子区域内的金属图形单元中第一金属条710和第二金属条720之间均通过同层或异层设置的第一连接桥实现连接，第一金属条710与触控信号线500之间不全部通过过孔连接，仅在与该第一金属条710所在的触控子区域相对应的触控信号线和触控电极通过过孔连接，不对应的触控信号线和触控电极不连接，也就是，通过控制第一金属条710与不同触控信号线之间的通断，实现在列方向上的触控电极分块。
需要说明的是，在上述示例性的实施例中，如图所示，在一些实施例中，如图3所示，各触控子区域内的金属图形单元中第一金属条710和第二金属条720之间均连接；另一些实施例中，如图9所示，同一触控子区域内的多个金属图形单元中，一部分金属图形单元的第一金属条和第二金属条之间连接，另一部分金属图形单元的第一金属条和第二金属条之间通过第一断开口730断开不连接。
此外，图8表示本公开另一些实施例提供的阵列基板中，位于同一触控子区域中的多个金属图形单元以及不同触控子区域中金属图形单元的布局示意图。
如图8所示，同一触控电极中，多个金属图形单元之间的第一子金属线之间通过与第一金属条同层或异层设置的第一桥接部连接第二断开口，且至少一个金属图形单元与该触控电极中的至少一个触控子电极藕接；不同触控电极中，多个金属图形单元之间的第一子金属线之间，通过第二断开口断开而不连接；
同一触控电极中，在第二方向上排列的至少两列第一金属条分别通过过孔(图中虚线圆形区域O即为过孔位置)连接至不同的触控信号线，与该触控电极不对应的所述触控信号线所连接的第一金属条，通过第一断开口与该触控电极内的第二金属条之间断开不连接，以使在第二方向上的相邻所述触控电极之间，金属图形单元不连接。
上述实施例中，是在行方向上，相邻的第二金属条720之间连接，通过控制第二断开口740是否连接，实现在行方向上的触控电极分块；
在列方向上，第一金属条710与触控信号线500之间分别全部通过过孔连接，此时，通过控制第一断开口730是否连接，实现相对应的触控信号线和触控电极连接，不对应的触控信号线和触控电极不连接，以此实现在列方向上的触控电极分块。
此外，在一些示例性的实施例中，如图1至图3所示，相邻两个金属图形单元700中，一个金属图形单元700的第一金属条710和另一个金属图形单元700的第二子金属线722，位于同一根数据线300的相对两侧，并在平行于基底100且垂直于第二方向的方向上，在基底100上的正投影的边界与数据线300在基底100上的正投影的边界之间的距离相同。
并且，在一些实施例中，请参见图1至图3所示，第一子金属线721和第二子金属线722在基底100之上的正投影被对置基板20上对应的黑矩阵21的遮光条在基底100上的正投影完全覆盖。例如，在平行于基底100且垂直于第一方向的方向上，黑矩阵21在基底100上的正投影的边界超出第一金属条710在基底100上的正投影的边界的尺寸为1～3微米具体的，在实际应用中，可根据显示面板的具体尺寸、子像素400的具体大小相应调整确定该尺寸，例如，黑矩阵21在基底100上的正投影的边界超出第一金属条710在基底100上的正投影的边界的尺寸为1.5微米。
同样的，在平行于基底100且垂直于第一方向的方向上，黑矩阵21在基底100上的正投影的边界超出第二金属条720在基底100上的正投影的边界的尺寸为1～3微米。具体的，在实际应用中，可根据显示面板的具体尺寸、子像素400的具体大小相应调整确定该尺寸，例如，黑矩阵21在基底100上 的正投影的边界超出第二金属条720在基底100上的正投影的边界的尺寸为1.5微米。
此外，在本公开一些实施例中，在平行于基底100且垂直于第二方向的方向上，数据线300在基底100上的正投影的边界和与该数据线300相邻两个子像素400内的像素电极620在基底100上的正投影的边界之间的距离相等；数据线300在基底100上的正投影的边界和与该数据线300相邻两个子像素400内的公共电极在基底100上的正投影的边界之间的距离相等。
上述方案中，1st ITO与2nd ITO可以做到相对于数据线300对称，也就是，数据线300左右侧与电极距离相等，这样，可以减少数据线300与左右侧电极之间的寄生电容不同导致的不良。
此外，示例性的，阵列基板10还包括：有机绝缘层810；触控信号线500与数据线300同层且同材质设置，且有机绝缘层810设置在数据线300所在层与触控电极600所在层之间。
上述方案中，示例性的，有机绝缘层810的厚度较厚，具有平坦作用。上述设置有机绝缘层810的至少部分位于触控信号线500和公共电极之间，增加了触控信号线500与像素电极620之间的距离，有利于改善由像素电极620工艺波动导致的触控信号线500与像素电极620之间形成的左右侧电场不对称的问题，从而改善了开口区透过率偏差，更好的解决了由透过率偏差导致的视觉上亮暗不一，视觉上形成黑污渍或者白污渍的不良，有效提升了产品的良率。
在将位于同一个触控子区域T中的公共电极复用为该触控子区域T中的触控电极600的情况下，在利用阵列基板10形成液晶显示面板后，利用该液晶显示面板实现触控显示功能的具体过程如下：
在触控阶段，触控信号线500向所耦接的公共电极(也即触控电极600)提供触控信号，当在液晶显示面板的触控区域发生触控操作时，触控操作发生位置处的触控电极600单元对应的触控信号会发生变化，触控电极600单元将该变化的触控信号通过对应的触控信号线500传输至芯片，该芯片基于该变化的触控信号判断触控操作发生的具体位置；在显示阶段，触控信号线 500向所耦接的公共电极提供显示需要的公共电极信号，同时阵列基板10中的子像素400驱动电路为对应的像素电极620提供驱动信号，从而使得在像素电极620和公共电极之间产生驱动液晶偏转的电场，进而使得液晶显示面板实现显示功能。
此外，如图2所示，一些实施例中，阵列基板10还包括：栅绝缘层(GI层)820和钝化层830；沿背离基底100的方向，金属图形单元700所在层、栅绝缘层820、触控信号线500和数据线300所在层、有机绝缘层(ORG)810、触控电极600所在层、钝化层(PVX)830、像素电极620所在层依次设置；触控电极600通过第一连接过孔Via1与金属图形单元700耦接，第一连接过孔Via1至少贯穿钝化层830、有机绝缘层810和栅绝缘层820；触控信号线500通过第二连接过孔Via2与金属图形单元耦接，第二连接过孔Via2至少贯穿钝化层830、有机绝缘层810和栅绝缘层820。
请参见图4，示例性的，第一连接过孔Via1包括第一子过孔和第二子过孔；第一子过孔贯穿钝化层830，将触控电极600部分裸露出来；第二子过孔贯穿有机绝缘层810和栅绝缘层820，将金属图形单元700部分裸露出来；阵列基板10还包括第一连接图形910，第一连接图形910在基底100上的正投影覆盖第一连接过孔Via1的第一子过孔和第二子过孔在基底100上的正投影，以将触控电极600和金属图形单元700耦接。
示例性的，请参见图5，第二连接过孔Via2包括第三子过孔和第四子过孔；
第三子过孔贯穿钝化层830，将触控信号线500部分裸露出来；第四子过孔贯穿有机绝缘层810和栅绝缘层820，将金属图形单元700部分裸露出来；阵列基板10还包括第二连接图形920，第二连接图形920在基底100上的正投影覆盖第二连接过孔Via2的第三子过孔和第四子过孔在基底100上的正投影，以将触控信号线500和金属图形单元700耦接。
在上述方案中，触控电极600可通过第一连接图形910与金属图形连接。其中，第一连接图形910在基底100上的正投影覆盖第一连接过孔Via1的第一子过孔以及第二子过孔在基底100上的正投影。本公开实施例中，可在阵 列基板10的制备过程中，先进行一次构图工艺将有机绝缘层810上的过孔(对应第一过孔的第一子过孔)去掉，以暴露出来部分触控电极600；然后在进行另一次构图工艺制作钝化层830上过孔时，可将金属图形单元700上面的栅绝缘层820和钝化层830同时去掉，以暴露出来部分金属图形单元，这样，可省去对栅绝缘层820的单独刻蚀步骤，节省一道掩膜工艺，从而简化阵列基板10的制作工艺流程，节约阵列基板10的制作成本。
在一些实施例中，第一连接图形910、第二连接图形920均可以与像素电极620同层设置且材料相同。将第一连接图形910、第二连接图形920与像素电极620同层同材料设置，使得第一连接图形910、第二连接图形920与像素电极620能够在同一次构图工艺中形成，有利于简化阵列基板10的制作工艺流程，降低阵列基板10的制作成本。当然可以理解的是，第一连接图形910和第二连接图形920也可以是单独制作。
此外，一些示例性的实施例中，请参见图6所示，阵列基板10还包括：驱动电路，驱动电路的输出电极840的至少部分位于有机绝缘层810靠近基底100的一侧；像素电极620通过第三连接过孔Via3与输出电极840耦接，第三连接过孔Via3至少贯穿有机绝缘层810和钝化层830，以将驱动电路的输出电极840裸露出来，使像素电极620与输出电极840耦接。
示例性的，驱动电路包括：驱动晶体管；第三连接过孔Via3包括：第五子过孔和第六子过孔；第五子过孔贯穿有机绝缘层810，第六子过孔贯穿钝化层830，第五子过孔在基底100上的正投影包括第六子过孔在基底100上的正投影；像素电极620通过第三连接过孔Via3与输出电极840耦接。
上述方案中，薄膜晶体管的栅极与相应的栅线200耦接，薄膜晶体管的输入电极与相应的数据线300耦接，薄膜晶体管的输出电极840作为驱动电路的输出电极840，输出电极840与像素电极620耦接。示例性的，输出电极840包括薄膜晶体管的源极。
示例性的，输出电极840与数据线300和触控信号线500同层同材料设置。如图1至图9所示，沿远离基底100的方向，栅绝缘层820，输出电极840，有机绝缘层810，公共电极，钝化层830和像素电极620依次层叠设置。
示例性的，形成有机绝缘层810后，进行一次构图工艺，在有机绝缘层810上形成开孔，形成贯穿有机绝缘层810的第五子过孔。然后形成钝化层830，进行下一次构图工艺，对钝化层830进行构图形成贯穿钝化层830的第六子过孔。需要说明，钝化层830的一部分位于第五子过孔内，对该一部分进行刻蚀，形成第六子过孔，第五子过孔在基底100上的正投影包围第六子过孔在基底100上的正投影，形成套孔。然后形成像素电极620，像素电极620通过第一子过孔和第二子过孔与输出电极840耦接。
上述实施例提供的显示基板中，通过设置第五子过孔的边界在基底100上的正投影与输出电极840在基底100上的正投影至少部分重叠，使得第五子过孔的边界的至少部分能够位于输出电极840上，进而可以控制第六子过孔的边界的至少部分能够位于输出电极840上，这样能够避免像素电极62040在输出电极840的边界处完全断开，从而保证了像素电极620与输出电极840良好的连接性能。
在相关技术中，为了降低像素电极的电阻，像素电极上设置有多个狭缝(slit)，为了保证液晶显示面板正常的显示功能，需要设置配向层中沟槽的延伸方向与狭缝的延伸方向相同，即在配向的过程中，取向布需要沿着与数据线的延伸方向垂直的方向对配向膜进行摩擦，这样取向布在数据线附近进行摩擦时，在数据线处需要爬坡，容易导致在数据线附近出现较大的配向阴影(即Rubbing Shadow)区域，而由于该区域容易产生漏光现象，因此该区域需要在对盒后，需要由对置基板上的黑矩阵图形进行遮挡，从而导致增加了黑矩阵图形在垂直于数据线延伸方向上的宽度，降低液晶显示面板的开口率。
基于上述问题的存在，本公开的公开人经研究发现，可通过改变狭缝的延伸的方向，使狭缝的延伸方向与数据线的延伸方向相同，并使配向层配向后的沟槽方向与数据线的延伸方向相同，这样在配向的过程中，就能够避免在数据线附近形成配向阴影区域，从而减小了用于遮挡数据线的黑矩阵图形在垂直于数据线延伸方向上的宽度，有效提升了液晶显示面板的开口率。
可选的，如图1所示，每个像素电极620包括多个沿第二方向延伸的狭 缝620a。
此处，狭缝620a沿第二方向延伸指的是，狭缝620a整体上沿第二方向延伸。在一些实施例中，像素电极620包括一个畴，在此情况下，狭缝620a为直线状；在另一些实施例中，像素电极620划分两个畴，在此情况下，如图1所示，每条狭缝620a包括第一子狭缝和第二子狭缝，第一子狭缝和第二子狭缝的夹角θ为钝角。
在阵列基板上形成配向层的过程包括：
先在阵列基板设置有像素电极的一侧制作配向材料薄膜，然后利用取向布沿像素电极中狭缝的延伸方向(即数据线的延伸方向)进行摩擦配向，形成具有沟槽的配向层，该沟槽的延伸方向与狭缝的延伸方向相同。
由于狭缝620a沿第二方向延伸，利用取向布对取向薄膜进行取向时，取向布沿第二方向移动，使得在阵列基板上对配向材料薄膜配向的过程中，不会在数据线的附近形成较大的Rubbing Shadow区域。由于无Rubbing Shadow区域产生的漏光问题，因而黑矩阵21图案中遮光条沿第一方向的宽度可以设计的更窄，进而可以有效提高开口率。
如图1所示，在本公开一些实施例中，由于第二金属条720与触控电极之间通过第一连接过孔Via1连接，为了对该第一连接过孔处进行避让，像素电极的形状适应性的具有缺口，相应的，在缺口对应区域的狭缝620a沿第二方向的长度小于其他区域的狭缝620a沿第二方向的长度。以图1所示的具体实施例为例，一个像素电极中狭缝的数量可以有7个，其中靠近第二子金属线一侧的2个狭缝的上端对齐、下端对齐设置，这2个狭缝的长度小于靠近第一金属条的一侧5个狭缝的长度，靠近第一金属条的一侧5个狭缝的上端对齐、下端对齐设置。
当然，以上仅是示例，在实际应用中，对于狭缝的数量以及长度等不以此为限。
需要说明的是，图1表示本公开实施例提供的一种阵列基板中子像素的布局示意图，图中走线会存在弯折转向的部位，且图中在走线弯折转向位置为尖角，在实际产品由于制作工艺，走线弯折转向部位应为圆角过渡，这里 仅是为了画图方便未示意成圆角。
本公开实施例还提供一种显示装置，包括相对设置的阵列基板10和对置基板20、以及设置在阵列基板10和对置基板20之间的液晶层，阵列基板10为本公开实施例提供的阵列基板10。
对置基板20上设有黑矩阵21，黑矩阵21在阵列基板上的正投影位于子像素的非透光区，且在平行于基底且垂直于第二方向的方向上，黑矩阵在基底上的正投影的边界和与与黑矩阵相邻两个子像素内的像素电极在基底上的正投影的边界之间的距离相等；黑矩阵在基底上的正投影的边界和与与黑矩阵相邻两个子像素内的公共电极在基底上的正投影的边界之间的距离相等。
上述方案中，1st ITO与2nd ITO可以做到相对于黑矩阵21对称，也就是，黑矩阵21左右侧与电极距离相等，因此黑矩阵对子像素的遮挡效果会更有利于子像素透光率的均匀性，也就是说，有利于像素的对称性。
需要说明的是，显示装置可以为：液晶显示面板、电视、显示器、数码相框、手机、电子纸、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件等。
本公开实施例提供的显示装置在包括上述阵列基板10时同样具有上述有益效果，此处不再赘述。
本公开实施例还提供了一种阵列基板10的制备方法，该制备方法包括：
步骤S01、提供基底100；
步骤S02、在基底100上制作多条栅线200、多条数据线300、多条触控信号线500、多个触控电极600和金属图形单元700等，多条栅线200沿第一方向延伸、多条数据线300沿第二方向延伸，多条栅线200和多条数据线300相互交叉限定出多个子像素400；多条触控信号线500沿第二方向延伸，触控信号线500设置在相邻子像素400之间的非透光区；多个触控电极600相互绝缘；多个金属图形单元700设置在相邻子像素400之间的非透光区，一个金属图形单元700对应一个触控电极600，触控电极600通过对应的金属图形单元700与对应的触控信号线500藕接，且金属图形单元700在基底100上的正投影与触控信号线500在基底100上的正投影至少部分重叠。
本公开实施例所提供的阵列基板10的制造方法，将触控信号线500与数据线300平行设置，且触控信号线500位于相邻子像素400之间的非透光区，这样，触控信号线500可以与数据线300共同被对置基板20上的黑矩阵21所覆盖，从而可解决相关技术中触控信号线500位于子像素400中间时所存在的触控信号线500与左右电极之间电场不均匀的问题，减少污渍不良现象；并且，触控电极600与触控信号线500通过金属图形电连接，能够减少触控电极600的电阻，有效降低触控信号线500上的损耗，提升触控灵敏度，整体上提升产品品质；此外，触控信号线500可被金属图形单元至少部分覆盖，金属图形单元还可以起到遮光作用，减弱对黑矩阵21遮光作用的依赖，从而可减少对置基板20上黑矩阵21的图形遮光面积。
在一些实施例中，步骤S02具体包括：
步骤S021、在基底100上制作栅线200、驱动晶体管的栅极和金属图形单元700；金属图形单元700用于后续与公共电极耦接，以减小公共电极的传输电阻。
更详细地说，在基底100上制作第一栅金属层(Gate层)，第一栅金属层包括沿远离基底100的方向依次层叠设置的第一钼金属层，第一铝金属层和第二钼金属层，第一钼金属层的厚度为
Figure PCTCN2021115954-appb-000001
第一铝金属层的厚度为
Figure PCTCN2021115954-appb-000002
第二钼金属层的厚度为
Figure PCTCN2021115954-appb-000003
对第一栅金属层进行构图工艺，该构图工艺依次包括镀膜、曝光、显影、湿刻等工艺，形成栅线200、栅极和金属图形单元700。一些实施例中，金属图形单元700还包括用于与同一触控子区域T内各金属图形单元700之间耦接的第一桥接部741和第二桥接部742。
步骤S022、在形成有栅线200和金属图形单元700的基底100上制备驱动电路、数据线300和触控信号线500。
更详细的说，本步骤中，首先，沉积整层的栅绝缘层820，栅绝缘层820覆盖栅线200、栅极及金属图形单元700；栅绝缘层820的材料包括氮化硅。栅绝缘层820的厚度为
Figure PCTCN2021115954-appb-000004
然后，制作薄膜晶体管的有源层。有源层的厚度为
Figure PCTCN2021115954-appb-000005
然后，制作薄膜晶体管的源漏金属层，源漏金属层包括沿远离基底100 的方向依次层叠设置的第三钼金属层，第二铝金属层和第四钼金属层，第三钼金属层的厚度为
Figure PCTCN2021115954-appb-000006
第二铝金属层的厚度为
Figure PCTCN2021115954-appb-000007
第四钼金属层的厚度为
Figure PCTCN2021115954-appb-000008
对源漏金属层进行构图工艺，该构图工艺依次包括镀膜、曝光、显影、湿刻等工艺，形成驱动电路的输入电极和输出电极840，以及数据线300和触控信号线500。
步骤S023、在形成有驱动电路的基底100上制作有机绝缘层810，有机绝缘层810覆盖驱动电路的输出电极840和数据线300及触控信号线500；
更详细的说，本公开实施例中，可采用氮化硅材料沉积形成一层缓冲层，缓冲层的厚度为
Figure PCTCN2021115954-appb-000009
采用有机树脂，在缓冲层背向基底100的一侧继续沉积整层的有机绝缘层810，有机绝缘层810的厚度为
Figure PCTCN2021115954-appb-000010
在一次构图工艺中在有机绝缘层810上形成第二子过孔、第四子过孔和第五子过孔，第二子过孔和第四子过孔贯穿有机绝缘层810，以暴露至少部分金属图形单元700；第四子过孔和第三子过孔；第五子过孔贯穿有机绝缘层810，并暴露驱动电路的输出电极840的至少部分。
步骤S024、制作公共电极；
更详细的说，本步骤中，可采用氧化铟锡材料，制作1ITO层，1ITO层的厚度为
Figure PCTCN2021115954-appb-000011
对1ITO层进行构图工艺，该构图工艺依次包括镀膜、曝光、显影、湿刻等工艺，形成公共电极。
步骤S027、制作钝化层830，钝化层830覆盖公共电极；
更详细的说，本步骤中，采用氮化硅材料，沉积形成整层的钝化层830。钝化层830的厚度为
Figure PCTCN2021115954-appb-000012
更详细的说，本步骤中，对钝化层830进行一次构图工艺，对钝化层830进行构图形成贯穿钝化层830的第一子过孔、第三子过孔、第六子过孔。其中，第一子过孔贯穿钝化层830，以将触控电极600部分裸露出来，第三子过孔贯穿钝化层830，将触控信号线500部分裸露出来；第六子过孔贯穿钝化层830，第五子过孔在基底100上的正投影包括第六子过孔在基底100上的正投影。
步骤S027、制作像素电极620、第一连接图形910和第二连接图形920， 第一连接图形910在基底100上的正投影覆盖第一连接过孔Via1的第一子过孔和第二自过孔在基底100上的正投影，以将触控电极600和金属图形单元耦接；第二连接图形920在基底100上的正投影覆盖第二连接过孔Via2的第三子过孔和第四子过孔在基底100上的正投影，以将触控信号线500和金属图形单元耦接。
更详细的说，本步骤中，采用氧化铟锡材料，制作2ITO层，2ITO层的厚度为
Figure PCTCN2021115954-appb-000013
对2ITO层进行构图工艺，该构图工艺依次包括镀膜、曝光、显影、湿刻等工艺，形成像素电极620、第一连接图形910和第二连接图形920。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (23)

  1. 一种阵列基板，包括基底、及设置在所述基底上沿第一方向延伸的多条栅线和沿第二方向延伸的多条数据线，所述多条栅线和所述多条数据线相互交叉限定出多个子像素；其特征在于，所述阵列基板还包括：
    多条沿所述第二方向延伸的触控信号线，所述触控信号线设置在所述子像素的非透光区；
    相互绝缘的多个触控电极，一个所述触控电极对应的连接至少一根触控信号线；
    多个金属图形单元，一个所述金属图形单元对应一个所述子像素设置，且所述金属图形单元设置于对应的所述子像素的非透光区，所述金属图形单元包括设置于所述数据线的至少一侧且沿所述第二方向延伸的第一金属条，所述第一金属条在所述基底上的正投影与所述触控信号线在所述基底上的正投影的重叠面积为A，所述重叠面积A与所述第一金属条在所述基底上的正投影面积的比值大于阈值。
  2. 根据权利要求1所述的阵列基板，其特征在于，
    在平行于所述基底且垂直于所述第二方向的方向上，所述触控信号线的尺寸小于所述第一金属条的尺寸。
  3. 根据权利要求2所述的阵列基板，其特征在于，在平行于所述基底且垂直于所述第二方向的方向上，所述第一金属条在所述基底上的正投影的边界超出所述触控信号线在所述基底上的正投影的边界的尺寸为0.8～2.0微米。
  4. 根据权利要求3所述的阵列基板，其特征在于，所述触控信号线具有沿所述第二方向延伸的中心线；所述第一金属条具有沿第二方向延伸的中心线；所述触控信号线的中心线在所述基底上的正投影与所述第一金属条的中心线在所述基底上的正投影完全重叠。
  5. 根据权利要求1所述的阵列基板，其特征在于，所述第一金属条在所述基底上的正投影与所述数据线在所述基底上的正投影不重叠。
  6. 根据权利要求5所述的阵列基板，其特征在于，在平行于所述基底且垂直于所述第二方向的方向上，所述第一金属条在所述基底上的正投影的边 界与所述数据线在所述基底上的正投影的边界之间的最小距离为2.1～8微米。
  7. 根据权利要求1所述的阵列基板，其特征在于，
    所述金属图形单元还包括第二金属条，所述第二金属条包括：
    设置于所述栅线的至少一侧且沿所述第一方向延伸的第一子金属线；
    及，设置于所述数据线的至少一侧且沿所述第二方向延伸的第二子金属线，其中所述第一子金属线与所述第二子金属线连接，且所述第二子金属线与所述第一金属条分设于对应的所述子像素的相对两侧。
  8. 根据权利要求7所述的阵列基板，其特征在于，
    所述第一金属条与所述第二金属条同层设置，且同一所述金属图形单元中的所述第一金属条与所述第二金属条之间在所述第二方向上具有第一断开口；不同所述金属图形单元的两个所述第一子金属线之间在所述第一方向上具有第二断开口。
  9. 根据权利要求8所述的阵列基板，其特征在于，
    每个所述触控电极包括多个触控子电极，所述触控子电极在所述基底上的正投影与所述栅线和所述数据线在所述基底上的正投影无重叠区域；
    同一所述触控电极中，沿所述第一方向相邻的所述金属图形单元之间的所述第一子金属线之间通过与所述第一金属条同层或异层设置的第一桥接部连接所述第二断开口，且至少一个金属图形单元与该触控电极中的至少一个所述触控子电极藕接；沿所述第一方向相邻的不同所述触控电极中，多个所述金属图形单元之间的所述第一子金属线之间，通过所述第二断开口断开而不连接；
    同一所述触控电极中，在所述第二方向上排列的至少一列所述金属图形单元的所述第一金属条与所述第二金属条之间通过与所述第一金属条同层或异层设置的第二桥接部连接所述第一断开口，且所述第一金属条与对应的所述触控信号线藕接；在所述第二方向上的相邻所述触控电极之间，所述金属图形单元不连接。
  10. 根据权利要求9所述的阵列基板，其特征在于，
    同一所述触控电极中，在所述第二方向上排列的至少一列所述第一金属 条与对应的触控信号线藕接，且该触控电极所对应的所有所述第一金属条均和与该所述触控电极不对应的触控信号线不藕接，以使得在所述第二方向上的相邻所述触控电极之间，所述金属图形单元不连接；
    或者，同一所述触控电极中，在所述第二方向上排列的至少两列所述第一金属条分别连接至不同的触控信号线，与该触控电极不对应的所述触控信号线所连接的第一金属条，通过所述第一断开口与该触控电极内的第二金属条之间断开不连接，以使在所述第二方向上的相邻所述触控电极之间，所述金属图形单元不连接。
  11. 根据权利要求7所述的阵列基板，其特征在于，所述第一方向上相邻两个所述金属图形单元中，一个所述金属图形单元的第一金属条和另一个所述金属图形单元的第二子金属线，位于同一根所述数据线的相对两侧，并在平行于所述基底且垂直于所述第二方向的方向上，在所述基底上的正投影的边界与所述数据线在所述基底上的正投影的边界之间的距离相同。
  12. 根据权利要求9或10所述的阵列基板，其特征在于，所述阵列基板还包括设置于所述子像素内的像素电极和公共电极，其中所述触控子电极复用为所述公共电极。
  13. 根据权利要求12所述的阵列基板，其特征在于，
    在平行于所述基底且垂直于所述第二方向的方向上，所述数据线在所述基底上的正投影的边界和与该数据线相邻两个子像素内的像素电极在所述基底上的正投影的边界之间的距离相等；所述数据线在所述基底上的正投影的边界和与该数据线相邻两个子像素内的公共电极在所述基底上的正投影的边界之间的距离相等。
  14. 根据权利要求13所述的阵列基板，其特征在于，
    所述阵列基板还包括：有机绝缘层；所述触控信号线与所述数据线同层且同材质设置，且所述有机绝缘层设置在所述数据线所在层与所述触控电极所在层之间。
  15. 根据权利要求14所述的阵列基板，其特征在于，
    所述阵列基板还包括：栅绝缘层和钝化层；
    沿背离所述基底的方向，所述金属图形单元所在层、所述栅绝缘层、所述触控信号线和所述数据线所在层、所述有机绝缘层、所述触控电极所在层、所述钝化层、所述像素电极所在层依次设置；
    所述触控电极通过第一连接过孔与所述第二金属条耦接，所述第一连接过孔至少贯穿所述钝化层、所述有机绝缘层和所述栅绝缘层；
    所述触控信号线通过第二连接过孔与所述第一金属条耦接，所述第二连接过孔至少贯穿所述钝化层、所述有机绝缘层和所述栅绝缘层。
  16. 根据权利要求15所述的阵列基板，其特征在于，
    所述第一连接过孔包括第一子过孔和第二子过孔；
    所述第一子过孔贯穿所述钝化层，将所述触控电极部分裸露出来；
    所述第二子过孔贯穿所述有机绝缘层和所述栅绝缘层，将所述第二金属条部分裸露出来；
    所述阵列基板还包括第一连接图形，所述第一连接图形在所述基底上的正投影覆盖所述第一连接过孔的所述第一子过孔和所述第二自过孔在所述基底上的正投影，以将所述触控电极和所述第二金属条耦接。
  17. 根据权利要求16所述的阵列基板，其特征在于，所述第一连接图形与所述像素电极同层设置且材料相同。
  18. 根据权利要求16所述的阵列基板，其特征在于，
    所述第二连接过孔包括第三子过孔和第四子过孔；
    所述第三子过孔贯穿所述钝化层，将所述触控信号线部分裸露出来；
    所述第四子过孔贯穿所述有机绝缘层和所述栅绝缘层，将所述第一金属条部分裸露出来；
    所述阵列基板还包括第二连接图形，所述第二连接图形在所述基底上的正投影覆盖所述第二连接过孔的所述第三子过孔和所述第四子过孔在所述基底上的正投影，以将所述触控信号线和所述第一金属条耦接。
  19. 根据权利要求15所述的阵列基板，其特征在于，
    所述阵列基板还包括：驱动电路，所述驱动电路的输出电极的至少部分位于所述有机绝缘层靠近所述基底的一侧；
    所述像素电极通过第三连接过孔与所述输出电极耦接，所述第三连接过孔至少贯穿所述有机绝缘层和所述钝化层，以将所述驱动电路的输出电极裸露出来，使所述像素电极与所述输出电极耦接。
  20. 根据权利要求19所述的阵列基板，其特征在于，所述驱动电路包括：驱动晶体管；所述第三连接过孔包括：第五子过孔和第六子过孔；所述第五子过孔贯穿所述有机绝缘层，所述第六子过孔贯穿所述钝化层，所述第五子过孔在所述基底上的正投影包括所述第六子过孔在所述基底上的正投影；所述像素电极通过所述第三连接过孔与所述输出电极耦接。
  21. 根据权利要求12所述的阵列基板，其特征在于，
    每个所述像素电极包括多个沿所述第二方向延伸的狭缝。
  22. 一种显示装置，其特征在于，包括相对设置的阵列基板和对置基板、以及设置在所述阵列基板和所述对置基板之间的液晶层，其特征在于，所述阵列基板为如权利要求1至21任一项所述的阵列基板。
  23. 根据权利要求22所述的显示装置，其特征在于，
    所述对置基板上设有黑矩阵，所述黑矩阵在所述阵列基板上的正投影位于所述子像素的非透光区，且在平行于所述基底且垂直于所述第二方向的方向上，所述黑矩阵在所述基底上的正投影的边界和与黑矩阵相邻两个子像素内的像素电极在所述基底上的正投影的边界之间的距离相等；所述黑矩阵在所述基底上的正投影的边界和与与黑矩阵相邻两个子像素内的公共电极在所述基底上的正投影的边界之间的距离相等。
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