WO2017121144A1 - 移位寄存单元及驱动方法、栅极驱动电路和触控显示装置 - Google Patents

移位寄存单元及驱动方法、栅极驱动电路和触控显示装置 Download PDF

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Publication number
WO2017121144A1
WO2017121144A1 PCT/CN2016/099445 CN2016099445W WO2017121144A1 WO 2017121144 A1 WO2017121144 A1 WO 2017121144A1 CN 2016099445 W CN2016099445 W CN 2016099445W WO 2017121144 A1 WO2017121144 A1 WO 2017121144A1
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Prior art keywords
module
signal
terminal
pull
transistor
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PCT/CN2016/099445
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English (en)
French (fr)
Inventor
吴博
谭文
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US15/513,154 priority Critical patent/US10319452B2/en
Publication of WO2017121144A1 publication Critical patent/WO2017121144A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a shift register unit, a method of driving the shift register unit, a gate drive circuit, and a touch display device including the gate drive circuit.
  • the touch display panel has become the mainstream display terminal configuration, and the capacitive touch screen has an absolute advantage.
  • the capacitive touch screen integrates the touch panel with the display panel by adopting an In Cell scheme.
  • Time-division driving refers to a method of alternately displaying and touching in one frame time.
  • one frame time of the display device is divided into a plurality of alternate display phases and touch phases to improve the touch rate of the touch.
  • the display driving is paused, and the first node of the one-stage shift register unit that is suspended is always at a high level after the pre-charging of the previous stage, because the discharge module connected to the first node has an inherent leak.
  • the first node will leak through the discharge module and cannot maintain a high state.
  • the voltage of the first node (eg, the pull-up node) of the stage shift register unit is lower than the voltage of the first node of the other stage, which causes the signal voltage output by the gate drive circuit of the stage to be higher than other stages. To be low, a dark line will be produced when displayed.
  • the entire touch display process there are multiple times during which the display phase and the touch phase are alternately paused, and multiple dark lines appear on the display, causing a decrease in display effect or even a display failure.
  • An object of the present invention is to provide a shift register unit, a gate drive circuit, a touch display device including the gate drive circuit, and a shift register unit Method.
  • the touch display device does not have a dark line when displayed.
  • a shift register unit is provided, wherein the shift register unit is used in a touch display device, wherein the shift register unit includes a first signal input end, Two signal input terminals, input and reset modules, pull-up modules, pull-down modules, pull-down control modules, clock signal input terminals, first level input terminals, second level input terminals, first voltage terminals, second voltage terminals, Signal output, discharge module and leakage suppression module,
  • a first control end of the input and reset module is connected to the first signal input end, a second control end of the input and reset module is connected to the second signal input end, and the input and reset module
  • An input terminal is coupled to the first voltage terminal, a second input terminal of the input and reset module is coupled to the second voltage terminal, and an output of the input and reset module is coupled to the first node;
  • An input end of the pull-up module is connected to the clock signal input end, an output end of the pull-up module is connected to the signal output end, and a control end of the pull-up module is connected to the first node;
  • the control end of the pull-up module receives the effective voltage signal of the first node, the input end of the pull-up module is electrically connected to the signal output end;
  • the input end of the pull-down module is connected to the second level input end, the output end of the pull-down module is connected to the signal output end, and the control end of the pull-down module is connected to the second node;
  • the control end of the module receives the effective voltage signal of the second node, the input end of the pull-down module is electrically connected to the output end of the pull-down module;
  • a control end of the pull-down control module is connected to the first node, an output end of the pull-down control module is connected to the second node, and a first input end of the pull-down control module is connected to the first level Connected to the end, the second input end of the pull-down control module is connected to the second level input end; when the control end of the pull-down control module receives the valid voltage signal, the second level input end is The output end of the pull-down control module is turned on, and when the control terminal of the pull-down control module receives an invalid voltage signal, the first power is The flat input terminal is electrically connected to the output end of the pull-down control module;
  • An output end of the discharge module is connected to the first node, a control end of the discharge module is connected to the second node, and an input end of the discharge module is connected to an output end of the leakage suppression module;
  • the control terminal of the discharge module receives the effective voltage signal
  • the input end of the discharge module is electrically connected to the output end of the discharge module;
  • the leakage suppression module is capable of providing an effective voltage signal to an input end of the discharge module when the control terminal of the discharge module receives an invalid voltage signal, and the leakage suppression module is receivable at a control end of the discharge module When the effective voltage signal is reached, an invalid voltage signal is supplied to the input of the discharge module.
  • the discharge module includes a discharge transistor, a gate of the discharge transistor is formed as a control end of the discharge module, and a first electrode of the discharge transistor is formed as an output end of the discharge module, the discharge transistor The second pole is formed as an input of the discharge module.
  • the leakage suppression module includes a first leakage suppression transistor, a gate of the first leakage suppression transistor is connected to the first voltage terminal, and a first pole of the first leakage suppression transistor is formed as the leakage current The output of the suppression module, the second pole of the first leakage suppression transistor is connected to the second voltage terminal.
  • the leakage suppression module further includes a second leakage suppression transistor, a gate of the second leakage suppression transistor is connected to the second voltage terminal, and a first pole of the second drain suppression transistor is An input end of the discharge module is connected, and a second pole of the second leakage suppression transistor is connected to the first voltage end.
  • the pull-up module includes a pull-up transistor and a storage capacitor
  • a gate of the pull-up transistor is formed as a control terminal of the pull-up module
  • a first pole of the pull-up transistor is formed as the pull-up An input end of the module
  • a second pole of the pull-up transistor is formed as an output end of the pull-up module
  • a first end of the storage capacitor is connected to the first node
  • a second end of the storage capacitor is The output ends of the pull-up modules are connected.
  • the pull-down module includes a pull-down transistor, a gate of the pull-down transistor is formed as a control end of the pull-down module, a first pole of the pull-down transistor is formed as an output end of the pull-down module, and the pull-down transistor The second pole is formed as an input of the pull down module.
  • the pull-down control module includes a first control transistor, a second control transistor, a third control transistor, and a fourth control transistor, a gate and a first pole of the first control transistor and the first level input Connected to the end, the second pole of the first control transistor is connected to the gate of the second control transistor, the first pole of the second control transistor is connected to the first level input terminal, the second a second pole of the control transistor is formed as a control end of the pull-down control module, a gate of the third control transistor is formed as an output end of the pull-down control module, a first pole of the third control transistor is a second pole of the first control transistor is connected, a second pole of the third control transistor is connected to the second level input terminal, and a gate of the fourth control transistor is connected to the first node, A first pole of the fourth control transistor is coupled to the second node, and a second pole of the fourth control transistor is coupled to the second level input.
  • the reset and input module comprises a first reset and input transistor and a second reset and input transistor, a gate of the first reset and input transistor is connected to the first signal input, the first reset And a first pole of the input transistor is coupled to the first voltage terminal, a second pole of the first reset and input transistor is coupled to the first node, and a gate of the second reset and input transistor is The second signal input terminal is connected, the first pole of the second reset and input transistor is connected to the first node, and the second pole of the second reset and input transistor is connected to the second voltage terminal.
  • a gate driving circuit including a cascaded multi-stage shift register unit, and a duty cycle of the gate driving circuit includes an alternate display phase and touch
  • the multi-stage shift register unit is divided into a plurality of groups, each set of the shift register unit includes N shift register units, and each set of the shift register unit corresponds to one of the display stages, where N is a natural number, wherein, at least from the second group of the shift register units, at least a first stage shift register unit of each of the set of shift register units is the shift register unit provided by the present invention.
  • a touch display device includes a gate driving circuit and a touch driving circuit, and the touch driving circuit includes a plurality of outputs, wherein the gate The pole driving circuit is the above-mentioned gate driving circuit provided by the present invention, and the plurality of output ends of the touch driving circuit are divided into a plurality of groups, each of the output terminals includes M output terminals, and M is a natural number, each group The output corresponds to one of the described Touch phase.
  • a driving method of a shift register unit is provided, wherein the shift register unit includes the above-described shift register unit provided by the present invention, and the drive method is performed when performing forward scan Each cycle includes:
  • a charging phase providing an effective voltage signal to the first signal input terminal, providing an invalid voltage signal to the second signal input terminal, providing an effective voltage signal to the first voltage terminal, and providing an invalidity to the second voltage terminal a voltage signal, providing an invalid voltage signal to the clock signal input terminal;
  • an output stage providing an invalid voltage signal to the first signal input, providing an invalid voltage signal to the second signal input, providing an effective voltage signal to the first voltage terminal, and providing the second voltage terminal An invalid voltage signal, providing an effective voltage signal to the clock signal input terminal;
  • an output pull-down phase providing an effective voltage signal to the second signal input terminal, providing an invalid voltage signal to the first signal input terminal, and providing an effective voltage signal to the first voltage terminal to the second voltage Providing an invalid voltage signal to provide an invalid voltage signal to the clock signal input; or
  • Each cycle of the driving method includes:
  • a charging phase providing an invalid voltage signal to the first signal input terminal, providing an effective voltage signal to the second signal input terminal, providing an invalid voltage signal to the first voltage terminal, and providing an effective voltage to the second voltage terminal a voltage signal, providing an invalid voltage signal to the clock signal input terminal;
  • an output pull-down phase providing an effective voltage signal to the first signal input terminal, providing an invalid voltage signal to the second signal input terminal, and providing an invalid voltage signal to the first voltage terminal to the second voltage
  • the terminal provides an active voltage signal to provide an invalid voltage signal to the clock signal input.
  • the leakage suppression module provides an effective signal to the discharge module during the touch phase, and the effective signal is transmitted to the first node. Therefore, during the touch phase, the first node does not leak through the discharge module, thereby ensuring The output stage after the end of the touch phase can maintain the first node at a high level and further ensure a normal output in the output stage, thereby avoiding defects such as dark lines when the display device including the shift register unit performs display .
  • FIG. 1 is a schematic structural diagram of a shift register unit provided by the present invention.
  • FIG. 2 is a schematic diagram of a preferred embodiment of a shift register unit provided by the present invention.
  • FIG. 3 is a timing chart of signals when the shift register unit provided in FIG. 2 is forward-scanned;
  • FIG. 4 is a timing chart of signals when the shift register unit provided in FIG. 2 is reversely scanned;
  • FIG. 5 is a schematic diagram of a gate driving circuit provided by the present invention.
  • FIG. 6 is a signal timing diagram of a forward driving of a gate driving circuit provided by the present invention.
  • Fig. 7 is a timing chart showing signals in the reverse scanning of the gate driving circuit provided by the present invention.
  • a shift register unit is provided, wherein the shift register unit is used in a touch display device, and each duty cycle of the shift register unit includes a charging phase, a touch phase, and an output phase.
  • the output pull-down phase as shown in FIG. 1, the shift register unit includes a first signal input terminal OUT_N-1, a second signal input terminal OUT_N+1, an input and reset module 600, a pull-up module 100, and a pull-down module.
  • a clock signal input terminal CK a first level input terminal Vdd, a second level input terminal Vss, a first voltage terminal CN, a second voltage terminal CNB, a signal output terminal OUT, a discharge module 400, a leakage suppression module 500, and Pull down control module 300.
  • the first control terminal of the input and reset module 600 is connected to the first signal input terminal OUT_N-1, and the second control terminal of the input and reset module 600 is connected to the second signal input terminal OUT_N+1.
  • the first input end of the reset module 600 is connected to the first voltage terminal CN, the second input end of the input and reset module 600 is connected to the second voltage terminal CNB, and the output end of the input and reset module 600 is connected to the first node PU.
  • the first voltage terminal CN is electrically connected to the output terminal of the input and reset module 600;
  • the second voltage terminal CNB is turned on with the output terminal of the input and reset module 600.
  • the first voltage terminal CN and the second voltage terminal CNB provide an effective voltage signal or an invalid voltage signal as required.
  • the voltage signal provided by the CNB is described.
  • the input end of the pull-up module 100 is connected to the clock signal input terminal CK, the output end of the pull-up module 100 is connected to the signal output terminal OUT, and the control end of the pull-up module 100 is connected to the first node PU.
  • the control terminal of the pull-up module 100 receives the effective voltage signal of the first node PU, the input end of the pull-up module 100 is turned on with the signal output terminal OUT.
  • the input end of the pull-down module 200 is connected to the second level input terminal Vss, the output end of the pull-down module 200 is connected to the signal output end OUT, and the control end of the pull-down module 200 and the The two-node PD is connected.
  • the control terminal of the pull-down module 200 receives the effective voltage signal of the second node PD, the input end of the pull-down module 200 is turned on with the output end of the pull-down module 200.
  • the control end of the pull-down control module 300 is connected to the first node PU, and the output end of the pull-down control module 300 is connected to the second node PD.
  • the first input end of the pull-down control module 300 is connected to the first level input terminal Vdd, and the pull-down control module is connected.
  • the second input of 300 is coupled to the second level input terminal Vss.
  • the output end of the discharge module 400 is connected to the first node PU, the control end of the discharge module 400 is connected to the second node PD, and the input end of the discharge module 400 is connected to the output end of the leakage suppression module 500.
  • the connection point is NET1, when the discharge module When the control terminal of 400 receives the effective voltage signal, the input terminal of the discharge module 400 is electrically connected to the output terminal of the discharge module 400.
  • the leakage suppression module 500 can provide an effective voltage signal to the input terminal of the discharge module 400 when the control terminal of the discharge module 400 receives the invalid voltage signal, and the leakage suppression module 500 can receive the effective voltage signal when the control terminal of the discharge module 400 receives the effective voltage signal.
  • An invalid voltage signal is supplied to the input of the discharge module 400.
  • the leakage suppression module 500 By the setting of the leakage suppression module 500, it can be ensured that the first node PU maintains a high level in the output phase, and further ensures a normal output in the output phase, thereby preventing display on the display device including the shift register unit Defects such as dark lines appear.
  • the shift register unit provided by the present invention is used in a gate driving circuit, and the gate driving circuit is used in a touch display device.
  • a scan signal is provided to the touch display device by a gate driving circuit including the shift register unit.
  • one of the first signal input terminal OUT_N-1 and the second signal input terminal OUT_N+1 serves as a control signal input terminal of the shift register unit, and the other is used as The reset signal input terminal of the shift register unit.
  • the first signal input terminal OUT_N-1 is a control signal input terminal
  • the second signal input terminal OUT_N+1 is a reset signal input terminal.
  • the first voltage terminal CN provides an effective voltage signal
  • the second voltage terminal The CNB provides an invalid voltage signal during the charging phase, the output phase, and the output pull-down phase.
  • the first signal input terminal OUT_N-1 is a reset signal input terminal
  • the second signal input terminal OUT_N+1 is a control signal input terminal.
  • the first voltage terminal CN provides an invalid voltage signal in the charging phase, the output phase, and the output pull-down phase
  • the second voltage terminal CNB provides an effective voltage signal.
  • the first level input terminal Vdd provides an effective voltage signal at least in each sub-phase of the display phase, and the second level input terminal Vss always provides an invalid voltage signal.
  • the first signal input terminal OUT_N-1 is a control signal input terminal
  • the second signal input terminal OUT_N+1 is a reset signal input terminal
  • the first voltage terminal CN Providing an effective voltage signal
  • the second voltage terminal CNB provides an invalid voltage signal during the charging phase, the output phase, and the output pull-down phase
  • the first signal input terminal OUT_N-1 is a reset signal input terminal
  • the second signal input terminal is a control signal input terminal
  • the first voltage terminal CN provides an invalid voltage signal in the charging phase, the output phase and the output pull-down phase
  • the second voltage terminal CNB provides an effective voltage signal.
  • the effective voltage signal outputted by the shift register unit in the output stage is input by the clock signal input terminal CK.
  • the shift register unit provided by the present invention is used in a touch display device.
  • One frame time of the display device includes a display phase and a touch phase.
  • the charging phase, the output phase, and the output pull-down phase in the duty cycle of the shift register unit belong to a sub-phase of the display phase.
  • the touch phase is interspersed between the respective sub-stages of the display phase.
  • the touch driving signal and the touch sensing signal are provided to the display device, and the output of the shift register unit has no output.
  • Each duty cycle of the driving method includes:
  • Charging phase t1 providing an effective voltage signal to the first signal input terminal OUT_N-1, and providing an invalid voltage signal to the second signal input terminal OUT_N+1, to the first voltage terminal CN
  • An effective voltage signal is supplied, an invalid voltage signal is supplied to the second voltage terminal CNB, and an invalid voltage signal is supplied to the clock signal input terminal CK.
  • the first voltage terminal CN is turned on with the output of the input and reset module 600, thereby charging the first node PU with the effective voltage signal provided by the first voltage terminal CN. Since the first node PU receives the valid voltage signal at this time, the pull-down control module 300 outputs an invalid voltage signal to the second node PD.
  • the signal output terminal OUT outputs an invalid voltage signal during the charging phase t1.
  • the control terminal of the discharge module 400 receives the invalid voltage signal of the second node PD, and therefore, the input terminal and the output terminal of the discharge module 400 are disconnected, and therefore, the first node PU is not The potential affects.
  • the leakage suppression module 500 supplies an effective voltage signal to the input terminal of the discharge module 400.
  • the effective voltage signal provided by the leakage suppression module 500 is transmitted to the output end of the discharge module 400 (ie, the first node PU), so that the first The potential of the node PU causes an influence.
  • Touch phase t2 providing an invalid voltage signal to the first signal input terminal OUT_N-1, providing an invalid voltage signal to the second signal input terminal OUT_N+1, and providing an effective voltage signal to the first voltage terminal CN to the second voltage terminal CNB
  • An effective voltage signal is supplied to provide an invalid voltage signal to the clock signal input terminal CK.
  • the potential of the first node PU is maintained at the level of the charging phase t1. Therefore, the pull-down control module 300 outputs an invalid voltage signal to the second node PD. Since the clock signal input terminal CK inputs an invalid voltage signal, the signal output terminal OUT outputs an invalid voltage signal during the touch phase t2.
  • the control terminal of the discharge module 400 receives the invalid voltage signal of the second node PD, and therefore, the input terminal and the output terminal of the discharge module 400 are disconnected, and therefore, the first node PU is not The potential affects.
  • the leakage suppression module 500 supplies an effective voltage signal to the input terminal of the discharge module. If a leakage phenomenon occurs between the input terminal and the output terminal of the discharge module 400, the effective voltage signal provided by the leakage suppression module 500 is transmitted to the output end of the discharge module 400 (ie, the first node PU), so that the first The potential of the node PU causes an influence.
  • the touch driving signal line is scanned by the touch driving circuit. In the embodiment shown in FIG. 3, the touch driving signal is shown. Lines Tx1, Tx2, Tx3, Tx4.
  • Output phase t3 providing an invalid voltage signal to the first signal input terminal OUT_N-1, providing an invalid voltage signal to the second signal input terminal OUT_N+1, providing an effective voltage signal to the first voltage terminal CN, and providing the second voltage terminal CNB
  • the invalid voltage signal provides an effective voltage signal to the clock signal input terminal CK.
  • the first node PU in the output stage t3, can maintain an effective voltage signal, so that the input end of the pull-up module 100 can be turned on with the signal output terminal OUT to output the input through the clock signal input terminal CK. Effective voltage signal.
  • the control terminal of the pull-down control module 300 receives the valid voltage signal.
  • the second level input terminal Vss is turned on with the output terminal of the pull-down control module 300 to maintain the inactive level state of the second node PD. Therefore, the input terminal of the pull-down module 200 is disconnected from the output terminal so as not to affect the normal output of the shift register unit.
  • the output pull-down phase t4 provides an effective voltage signal to the second signal input terminal OUT_N+1, provides an invalid voltage signal to the first signal input terminal OUT_N-1, and supplies an effective voltage signal to the first voltage terminal CN to the second voltage terminal.
  • the CNB provides an invalid voltage signal and supplies an invalid voltage signal to the clock signal input terminal CK.
  • the output terminal of the input and reset module 600 is turned on with the second voltage terminal CNB, and accordingly, the output terminal of the pull-down control module 300 is caused.
  • a level input terminal Vdd is turned on.
  • the second node PD Since the first level input terminal Vdd provides an effective voltage signal, the second node PD receives the effective voltage signal, so that the input terminal and the output terminal of the pull-down module 200 can be controlled to be turned on, so that the signal output terminal OUT outputs an invalid voltage signal. At the same time, since the second node PD is an effective voltage signal, the input end and the output end of the discharge module 400 are turned on. At this stage, the leakage suppression module 500 provides an invalid voltage signal to the input of the discharge module 400, thereby discharging the first node PU.
  • the touch phase is before the output stage, and during the touch phase, the leakage suppression module 500 provides an effective voltage signal to the input of the discharge module 400. Therefore, even during the touch phase discharge
  • the leakage of the module 400 also does not affect the potential of the first node PU, thereby ensuring that the first node PU still maintains a valid voltage signal in the output phase and further ensures a normal output in the output phase, thereby avoiding including A defect such as a dark line appears when the display device of the shift register unit performs display.
  • the "effective voltage signal” means that the voltage signal of the module that receives the effective voltage signal is turned on
  • the "invalid voltage signal” refers to the voltage signal that can control the module that receives the invalid voltage signal to be turned off.
  • a high-level signal is an effective voltage signal, and a low-level signal is an invalid voltage signal;
  • a low-level signal is an effective voltage signal, and a high-level signal is an inactive voltage. signal.
  • all the transistors in the shift register unit are N-type transistors. Therefore, the effective voltage signal refers to a high level signal, and the invalid voltage signal refers to a low level signal.
  • the clock signal input by the clock signal input terminal CK is a pulse signal, and the clock signal input terminal CK should be ensured in the shift register unit.
  • the output stage outputs a valid clock signal (which enables the thin film transistor on the gate line connected to the output of the shift register unit), and the pull-up module 100 functions in the output stage.
  • the clock signal is output as an output signal to the signal output terminal OUT.
  • the signal input to the clock signal input terminal CK is always an invalid voltage signal, so that the potential of the signal output terminal OUT is not affected.
  • the discharge module 400 may include a discharge transistor T3, the gate of which is formed as a control terminal of the discharge module 400, and with the second node PD Connected; the first pole of the discharge transistor T3 is formed as an output end of the discharge module 400, and is connected to the first node PU; the second pole of the discharge transistor T3 is formed as an input end of the discharge module 400, and the output of the leakage suppression module 500 Connected to the end. Accordingly, the leakage suppression module 500 can provide an invalid voltage signal at other stages than the touch phase.
  • the second node PD is at the level of the effective voltage signal, and therefore, the discharge transistor T3 is turned on, and therefore, the leakage suppression module 500 is disabled.
  • the generated invalid voltage signal can be delivered to the first node PU through the discharge transistor T3, so that the potential of the first node PU can be pulled down to an inactive level during the output pull-down phase.
  • the specific structure of the leakage suppression module 500 is not particularly limited as long as it can realize an effective voltage signal to the discharge module 400 during the touch phase without affecting other working phases of the shift register unit.
  • the leakage suppression module 500 may include a first leakage suppression transistor T1.
  • the gate of the first leakage suppression transistor T1 is connected to the first voltage terminal CN, and the first leakage suppression is performed.
  • the first pole of the transistor T1 is formed as an output end of the leakage suppression module 500, and is connected to the input end of the discharge module 400 (ie, the second pole of the discharge transistor T3), and the second drain and the second pole of the first leakage suppression transistor T1
  • the voltage terminals CNB are connected.
  • the leakage suppression module 500 provided in this embodiment is applicable to a shift register unit that performs only forward scanning.
  • the effective voltage signal is always supplied to the first voltage terminal CN, the effective voltage signal is supplied to the second voltage terminal CNB during the touch phase, and the invalid voltage signal is supplied to the second voltage terminal CNB at other stages. Since the first voltage terminal CN provides an effective voltage signal, the first leakage suppressing transistor T1 is always turned on during forward scanning.
  • an invalid voltage signal can be provided to the input of the discharge module 400 to ensure that the shift register unit operates normally during the display phase.
  • an effective voltage signal can be supplied to the input of the discharge module 400 to prevent leakage of the first node PU.
  • the leakage suppression module 500 may further include a second leakage suppression transistor T2. As shown in FIG. 2, the gate of the second leakage suppressing transistor T2 is connected to the second voltage terminal CNB, the first pole of the second leakage suppressing transistor T2 is connected to the input terminal of the discharging module 400, and the second leakage suppressing transistor T2 is The second pole is connected to the first voltage terminal CN.
  • the voltage signal supplied to the first voltage terminal CN during forward scanning is different from the voltage signal supplied to the first voltage terminal CN during reverse scanning; the voltage signal supplied to the second voltage terminal CNB during forward scanning. It is different from the voltage signal supplied to the second voltage terminal CNB during reverse scanning.
  • the effective voltage signal is always supplied to the first voltage terminal CN, and the effective voltage signal is supplied to the second voltage terminal CNB during the touch phase.
  • An invalid voltage signal is supplied to the second voltage terminal CNB.
  • the effective voltage signal is always supplied to the second voltage terminal CNB, the effective voltage signal is supplied to the first voltage terminal CN during the touch phase, and the remaining voltage signal is supplied to the first voltage terminal CN.
  • the leakage suppression module 500 of the structure shown in Fig. 2 will be described in detail later.
  • the pull-up module 100 includes a pull-up transistor T4 and a storage capacitor C,
  • the gate of the pull-up transistor T4 is formed as a control terminal of the pull-up module 100, and is connected to the first node PU.
  • the first pole of the pull-up transistor T4 is formed as an input terminal of the pull-up module 100, and the second pull-up transistor T4 The pole is formed as an output of the pull up module 100.
  • the first end of the storage capacitor C is connected to the first node PU, and the second end of the storage capacitor C is connected to the output end of the pull-up module 100.
  • the pull-up transistor T4 When the effective voltage signal is supplied to the first node PU, the pull-up transistor T4 is turned on, and the clock signal input from the clock signal input terminal CK is the output signal of the signal output terminal OUT. When the invalid voltage signal is supplied to the first node PU, the pull-up transistor T4 is turned off.
  • the storage capacitor C can be charged.
  • the storage capacitor C can maintain the first node PU at an active level.
  • the pull-down module 200 includes a pull-down transistor T11, and a pull-down transistor T11.
  • the gate is formed as a control terminal of the pull-down module 200, and is connected to the second node PD.
  • the first pole of the pull-down transistor T11 is formed as an output end of the pull-down module 200, and the second pole of the pull-down transistor T11 is formed as an input end of the pull-down module 200. .
  • the pull-down transistor T11 When the effective voltage signal is supplied to the second node PD, the pull-down transistor T11 is turned on, and the low-level signal input through the second level input terminal Vss is output to the signal output terminal OUT, so that the signal output terminal OUT output can be invalidated. Voltage signal.
  • the pull-down control module 300 includes a first control transistor T7, a second control transistor T8, a third control transistor T9, and a fourth control transistor T10.
  • the gate and the first pole of the first control transistor T7 are connected to the first level input terminal Vdd
  • the second pole of the first control transistor T7 is connected to the gate of the second control transistor T8, and the second control transistor T8
  • the first pole is connected to the first level input terminal Vdd
  • the second pole of the second control transistor T8 is formed as the control terminal of the pull-down control module 300, and is connected to the second node PD
  • the gate of the third control transistor T9 is formed.
  • the output terminal of the control module 300 is pulled down and connected to the first node PU
  • the first pole of the third control transistor T9 is connected to the second pole of the first control transistor T7
  • the second pole and the second pole of the third control transistor T9 are connected.
  • the level input terminal Vss is connected, the gate of the fourth control transistor T10 is connected to the first node PU, the first pole of the fourth control transistor T10 is connected to the second node PD, and the second pole and the second of the fourth control transistor T10 are connected.
  • the level input terminals Vss are connected.
  • reset and input module 600 includes a first reset and input transistor T5 and a second reset and input transistor T6. As shown in the figure, the gate of the first reset and input transistor T5 is connected to the first signal input terminal OUT_N-1, and the first reset and the first pole of the input transistor T5 are connected to the first voltage terminal CN, the first reset and The second pole of the input transistor T5 is coupled to the first node PU.
  • the second reset and input transistor T6 has a gate connected to the second signal input terminal OUT_N+1, the second reset and input transistor T6 has a first pole connected to the first node PU, and the second reset and the second transistor of the input transistor T6 Connected to the second voltage terminal CNB.
  • the definitions of the first voltage terminal CN and the second voltage terminal CNB are the same as above, that is, when the gate driving circuit including the shift register unit performs forward scanning, input through the first voltage terminal CN
  • the signal is always an effective voltage signal
  • the signal input through the second voltage terminal CNB is an effective voltage signal in the touch phase
  • the remaining phase is an invalid voltage signal
  • the gate driving circuit including the shift register unit is reversed During scanning, the signal input through the first voltage terminal CN is an effective voltage signal in the touch phase, and the remaining phase is an invalid voltage signal
  • the signal input through the second voltage terminal CNB is always an effective voltage signal.
  • the first signal input terminal OUT_N-1 is connected to the output terminal of the shift register unit of the previous stage, and the second signal input terminal OUT_N+1 is connected to the output terminal of the shift register unit of the next stage.
  • the signal input by the first signal input terminal OUT_N-1 is a high level signal during forward scanning
  • the signal input by the second signal input terminal OUT_N+1 is a low level signal
  • the first reset and the input transistor T5 are turned on.
  • the high level signal input by the first voltage terminal CN is sent to the first node PU through the first reset and input transistor T5.
  • the signal input by the first signal input terminal OUT_N-1 is a low level signal during reverse scanning
  • the signal input by the second signal input terminal OUT_N+1 is a high level signal
  • the second reset and the input transistor T6 are turned on.
  • the high level signal input by the second voltage terminal CNB is sent to the first node PU through the second reset and input transistor T6.
  • each transistor is an N-type transistor, and therefore, the high level signal is an effective voltage signal and the low level signal is an invalid voltage signal.
  • FIG. 3 Shown in Figure 3 is a timing diagram of the various input signals during forward scanning.
  • one duty cycle of a shift register unit includes a charging phase t1, a touch phase t2, an output phase t3, and an output pull-down phase t4.
  • the input signal of the high level is input through the first signal input terminal OUT_N-1
  • the clock signal input through the clock signal input terminal CK is a low level signal
  • the first voltage terminal CN inputs a high level signal
  • the second voltage terminal CNB inputs a low level signal. Therefore, the first reset and input transistor T5 are turned on, the second reset, and the input transistor T6 are turned off.
  • the high level signal input by the first voltage terminal CN will charge the storage capacitor C. Meanwhile, at this stage, the first leakage suppressing transistor T1 is turned on, and the second leak suppressing transistor T2 is turned off to deliver the low level signal to the second electrode of the discharge transistor T3.
  • the first control transistor T7 of the pull-down control module 300 is turned on, the third control transistor T9 is turned on, and the fourth control transistor T10 is turned on.
  • the second control transistor is caused by the voltage division of the first control transistor T7 and the third control transistor T9. T8 deadline.
  • the first node PU is at a high level, causing the pull-up transistor T4 to be turned on. Since the clock signal is a low level signal, the output terminal OUT outputs a low level signal.
  • the conduction of the fourth control transistor T10 transmits a low level signal input by the second level input terminal Vss to the second node PD, so that the pull-down crystal
  • the body tube T11 is cut off.
  • the clock signal input through the clock signal input terminal CK is still a low level signal
  • the signal input through the first signal input terminal OUT_N-1 is a low level, and is input through the second signal input terminal OUT_N+1.
  • the signal is also low.
  • the first reset and input transistor T5, the second reset and the input transistor T6 are both turned off, and the first control transistor T7 is turned on. Since the signal input by the second voltage terminal CNB is a high level signal during the touch phase, the first leakage suppression transistor T1 and the second leakage suppression transistor T2 are both turned on, and the high level signal is sent to the discharge transistor T3. Thereby, it can be ensured that the first node PU does not leak through the discharge transistor T3.
  • the third control transistor T9 Since the first node PU is a high level signal, the third control transistor T9 is turned on. The voltage division of the first control transistor T7 and the third control transistor T9 causes the second control transistor T8 to be turned off, and the conduction of the fourth control transistor T10 causes the second node PD to remain in a low state.
  • the clock signal is a low level signal, therefore, OUT outputs a low level signal.
  • the touch driving signal lines are scanned by the touch driving circuit. In the embodiment shown in FIG. 3, the touch driving signal lines Tx1, Tx2, Tx3, and Tx4 are shown.
  • the clock signal jumps to a high level signal
  • the signal input through the first voltage terminal CN is a high level signal
  • the signal input through the second voltage terminal CNB is a low level signal, and is input through the first signal.
  • the signal input to the terminal OUT_N-1 is low
  • the signal input through the second signal input terminal OUT_N+1 is also low.
  • the first reset and input transistor T5, the second reset and the input transistor T6 are both turned off, and the first control transistor T7 is turned on. Therefore, the potential of the first node PU jumps to a higher potential under the bootstrap action of the storage capacitor C, so that the pull-up transistor T4 is turned on, so that the output terminal OUT outputs a high level signal.
  • the first leakage suppressing transistor T1 is turned on, and the second leakage suppressing transistor T2 is turned off, and therefore, the second extremely low level voltage of the discharging transistor T3.
  • the conduction of the third control transistor T9 causes the third control transistor T9 to form a voltage dividing action with the first control transistor T7, so that the second control transistor T8 is turned off.
  • the fourth control transistor T10 is turned on to maintain the low state of the second node PD, thereby ensuring the turn-off of the pull-down transistor T11.
  • the clock signal jumps to a low level signal
  • the signal input through the first voltage terminal CN is a high level signal
  • the signal input through the second voltage terminal CNB The signal is a low level signal
  • the signal input through the first signal input terminal OUT_N-1 is a low level
  • the signal input through the second signal input terminal OUT_N+1 is a high level signal. Therefore, the second reset and input transistor T6 are turned on, and the first node PU potential is pulled low by the low level signal input through the second voltage terminal CNB.
  • the first leakage suppressing transistor T1 is turned on, and the second leakage suppressing transistor T2 is turned off, so that the second extremely low level voltage of the discharging transistor T3.
  • the third control transistor T9 and the fourth control transistor T10 are both turned off.
  • the conduction of the first control transistor T7 causes the second control transistor T8 to also be turned on, thereby pulling up the second node PD potential to a high level.
  • the conduction of the discharge transistor T3 causes the first node PU to be further pulled down, and the pull-down transistor T11 is turned on so that the signal output terminal OUT is pulled down to a low level. At this point, one duty cycle of one shift register unit ends.
  • FIG. 4 Shown in Figure 4 is a timing diagram of the various input signals during reverse scanning.
  • one duty cycle of a shift register unit includes a charging phase t1, a touch phase t2, an output phase t3, and an output pull-down phase t4.
  • the input signal of the high level is input through the second signal input terminal OUT_N+1, and the clock signal input through the clock signal input terminal CK is a low level signal, and the signal input through the first signal input terminal OUT_N-1
  • the first voltage terminal CN inputs a low level signal
  • the second voltage terminal CNB inputs a high level signal. Therefore, the first reset and input transistor T5 are turned off, the second reset, and the input transistor T6 are turned on, The high level signal input by the second voltage terminal CNB will charge the storage capacitor C.
  • the second leakage suppressing transistor T2 is turned on, and the first leakage suppressing transistor T1 is turned off to deliver a low level signal to the second electrode of the discharge transistor T3.
  • the first control transistor T7 of the pull-down control module 300 is turned on, the third control transistor T9 is turned on, and the fourth control transistor T10 is turned on.
  • the second control transistor is caused by the voltage division of the first control transistor T7 and the third control transistor T9. T8 deadline.
  • the first node PU is at a high level, causing the pull-up transistor T4 to be turned on. Since the clock signal is a low level signal, the output terminal OUT outputs a low level signal.
  • the conduction of the fourth control transistor T10 transmits the low level signal input from the second level input terminal Vss to the second node PD, so that the pull-down transistor T11 is turned off.
  • the clock signal input through the clock signal input terminal CK is still For the low level signal, the signal input through the first signal input terminal OUT_N-1 is low level, and the signal input through the second signal input terminal OUT_N+1 is also low level, the first reset and input transistor T5, the first The two reset and input transistors T6 are both turned off, and the first control transistor T7 is turned on. Since the signal input by the first voltage terminal CN in the touch phase is a high level signal, the first leakage suppressing transistor T1 and the second leakage suppressing transistor T2 are both turned on, and the high level signal is sent to the discharging transistor T3. The second pole can thereby ensure that the first node PU does not leak through the discharge transistor T3.
  • the third control transistor T9 Since the first node PU is a high level signal, the third control transistor T9 is turned on. The voltage division of the first control transistor T7 and the third control transistor T9 causes the second control transistor T8 to be turned off, and the conduction of the fourth control transistor T10 causes the second node PD to remain in a low state.
  • the clock signal is a low level signal, so the output terminal OUT outputs a low level signal.
  • the touch driving signal lines are scanned by the touch driving circuit. In the embodiment shown in FIG. 3, the touch driving signal lines Tx1, Tx2, Tx3, and Tx4 are shown.
  • the clock signal jumps to a high level signal
  • the signal input through the first voltage terminal CN is a low level signal
  • the signal input through the second voltage terminal CNB is a high level signal, and is input through the first signal.
  • the signal input by the terminal OUT_N-1 is low level
  • the signal input through the second signal input terminal OUT_N+1 is also low level
  • the first reset and input transistor T5, the second reset and the input transistor T6 are both turned off, first The control transistor T7 is turned on. Therefore, the potential of the first node PU jumps to a higher potential under the bootstrap action of the storage capacitor C, so that the pull-up transistor T4 is turned on, so that the output terminal OUT outputs a high level signal.
  • the first leakage suppressing transistor T1 is turned off, and the second leakage suppressing transistor T2 is turned on, and therefore, the second extremely low level voltage of the discharging transistor T3.
  • the conduction of the third control transistor T9 causes the third control transistor T9 to form a voltage dividing action with the first control transistor T7, so that the second control transistor T8 is turned off.
  • the fourth control transistor T10 is turned on to maintain the low state of the second node PD, thereby ensuring the turn-off of the pull-down transistor T11.
  • the clock signal jumps to a low level signal
  • the signal input through the first voltage terminal CN is a low level signal
  • the signal input through the second voltage terminal CNB is a high level signal
  • the signal input by the signal input terminal OUT_N-1 is at a high level
  • the signal input through the second signal input terminal OUT_N+1 is a low level signal. Therefore,
  • the first reset and the input transistor T5 are turned on, and the first node PU potential is pulled low through the low level signal input by the first voltage terminal CN.
  • the first leakage suppression transistor T1 is turned off, and the second leakage suppression transistor T2 is turned on, so that the second extremely low level voltage of the discharge transistor T3.
  • the third control transistor T9 and the fourth control transistor T10 are both turned off.
  • the conduction of the first control transistor T7 causes the second control transistor T8 to also be turned on, thereby pulling up the second node PD potential to a high level.
  • the conduction of the discharge transistor T3 causes the first node PU to be further pulled down, and the pull-down transistor T11 is turned on so that the signal output terminal OUT is pulled down to a low level. At this point, one duty cycle of one shift register unit ends.
  • a gate driving circuit including a cascaded multi-stage shift register unit, a duty cycle of the gate driving circuit including an alternate display phase and touch
  • the multi-stage shift register unit is divided into a plurality of groups, each group of shift register units includes N shift register units, and each group of shift register units corresponds to one display stage, wherein at least from the second group of shift registers At the beginning of the unit, at least the first stage shift register unit of each group of shift register units is the above-described shift register unit provided by the present invention.
  • FIG. 5 Shown in Figure 5 is a preferred embodiment of the gate drive circuit provided by the present invention. It is easily understood that when the multi-stage shift register unit is cascaded, the output signal of the shift register unit of the previous stage is the input signal of the shift register unit of the next stage.
  • the gate driving circuit further includes a clock signal line, a high level signal line, a start signal line STV, a low level signal line, a first level signal line, and a second level signal line, and the clock
  • the signal line is connected to the clock signal input end of each shift register unit, and the high level signal line is connected to the first level input end of each shift register unit, and the start signal line STV is selectively shifted with the first stage.
  • the forward signal input end of the bit register unit and the reverse signal input end of the last stage shift register unit are connected (connected to the forward signal input end of the first stage shift register unit in the forward scan, and in the reverse scan The reverse signal input end of the last stage shift register unit is connected), the first level signal line is connected to the first level input end of each shift register unit, and the second level signal line and each stage shift register The second level input terminals of the unit are connected, and the low level signal lines are connected to the second level input terminals of the shift register units of each stage.
  • the first stage shift register unit of each group of shift register units is charged before the start of the touch phase, and the output is started after the end of the touch phase, due to the first stage shift register
  • the unit includes a leakage suppression module. Therefore, during the entire touch phase, the first node of the first-stage shift register unit does not leak, thereby ensuring that a stable scan signal is output after the end of the touch phase, thereby avoiding the appearance of a dark line. .
  • the number of the above-described shift register units provided in the present invention provided in the gate drive circuit is not particularly limited.
  • the number of the above-described shift register units provided by the present invention provided in the gate drive circuit may be one less than the number of groups of shift register units.
  • N is 4.
  • the gate driving circuit may include three shift register units having leakage suppression modules.
  • the three shift register units having the leakage suppression module are the first stage shift register unit of the second group shift register unit, the first stage shift register unit of the third group shift register unit, and the fourth group shift The first stage shift register unit of the bit register unit.
  • all of the shift register units are the above-described shift register units provided by the present invention.
  • m-level shift register units are shown, which are respectively connected to m gate lines of a display device.
  • OUTPUT_1 represents the first gate line
  • OUTPUT_2 represents the second gate line
  • OUTPUT_n-1 represents the n-1th gate line
  • OUTPUT_m-1 represents the m-1th gate line
  • OUTPUT_m represents the mth gate line.
  • FIG. 6 is a timing diagram of respective signals during operation of the gate driving circuit provided by the present invention.
  • FIG. 7 is a timing diagram of respective signals during operation of the gate driving circuit provided by the present invention.
  • Gate1, Gate2, Gate3, Gate4, Gate5, Gate6, Gate7, and Gate8 respectively represent a first gate line, a second gate line, a third gate line, a fourth gate line, and a first Five grid lines, a sixth grid line, a seventh grid line, and an eighth grid line.
  • Tx1, Tx2, Tx3, Tx4, Tx5, Tx6, Tx7, and Tx8 respectively represent a first touch scan line, a second touch scan line, a third touch scan line, and a fourth touch scan line, The fifth touch scan line, the sixth touch scan line, the seventh touch scan line, and the eighth touch scan line.
  • each group of shift register units includes four shift register units, and shifts corresponding to the first gate line Gate1, the second gate line Gate2, the third gate line Gate3, and the fourth gate line Gate4
  • the register units belong to the same group, and the scan signals are sequentially outputted in the display stage Display1; the shift register units corresponding to the fifth gate line Gate5, the sixth gate line Gate6, the seventh gate line Gate7, and the eighth gate line Gate8 belong to the same group.
  • the display signal is sequentially outputted in the display phase Display2.
  • the shift register unit corresponding to at least the fifth gate line Gate5 is a shift register unit including the leakage suppression module provided by the present invention.
  • each group of shift register units includes four shift register units, a first gate line Gate1, a second gate line Gate2, a third gate line Gate3, and a fourth.
  • the shift register units corresponding to the gate gate Gate4 belong to the same group, and the scan signals are sequentially outputted in the display phase Display2; the fifth gate line Gate5, the sixth gate line Gate6, the seventh gate line Gate7, and the eighth gate line Gate8
  • the corresponding shift register units belong to the same group, and the display signals are sequentially outputted in the display stage Display1.
  • at least the shift register unit corresponding to the fourth gate line Gate4 is the shift register unit including the leakage suppression module provided by the present invention.
  • a touch display device includes a gate driving circuit and a touch driving circuit, wherein the gate driving circuit is the gate provided by the present invention.
  • the driving circuit the plurality of output ends of the touch driving circuit are divided into multiple groups, and each of the output terminals includes M output ends, and each group of output ends corresponds to one touch phase.
  • M and N may be the same or different. In the specific embodiment shown in Figures 6 and 7, both M and N are four.
  • the corresponding four output ends are a group corresponding to the fifth touch scan line Tx5, the sixth touch scan line Tx6, the seventh touch scan line Tx7, and the eighth touch scan line Tx8.
  • the output is a group.
  • the first touch scan line Tx1, the second touch scan line Tx2, the third touch scan line Tx3, and the fourth touch respectively output four touch scan signals, in the touch stage Touch2, the fifth touch scan line Tx5, the sixth touch scan line Tx6, and the seventh touch scan line Tx7.
  • the four output terminals corresponding to the eighth touch scan line Tx8 respectively output four touch scan signals.
  • a driving method of a shift register unit wherein the shift register unit is the above-described shift register unit provided by the present invention.
  • each cycle of the driving method includes:
  • a charging phase providing an effective voltage signal to the first signal input terminal, providing an invalid voltage signal to the second signal input terminal, providing an effective voltage signal to the first voltage terminal, and providing an invalidity to the second voltage terminal a voltage signal, providing an invalid voltage signal to the clock signal input terminal;
  • an output stage providing an invalid voltage signal to the first signal input, providing an invalid voltage signal to the second signal input, providing an effective voltage signal to the first voltage terminal, and providing the second voltage terminal An invalid voltage signal, providing an effective voltage signal to the clock signal input terminal;
  • an output pull-down phase providing an effective voltage signal to the second signal input terminal, providing an invalid voltage signal to the first signal input terminal, and providing an effective voltage signal to the first voltage terminal to the second voltage
  • the terminal provides an invalid voltage signal, and an invalid voltage signal is supplied to the clock signal input terminal.
  • each cycle of the driving method includes:
  • a charging phase providing an invalid voltage signal to the first signal input terminal, providing an effective voltage signal to the second signal input terminal, providing an invalid voltage signal to the first voltage terminal, and providing an effective voltage to the second voltage terminal a voltage signal, providing an invalid voltage signal to the clock signal input terminal;
  • an output stage providing an invalid voltage signal to the first signal input, providing an invalid voltage signal to the second signal input, providing an invalid voltage signal to the first voltage terminal, and providing the second voltage terminal An effective voltage signal, providing an effective voltage signal to the clock signal input terminal;
  • an output pull-down phase providing an effective voltage signal to the first signal input terminal, providing an invalid voltage signal to the second signal input terminal, and providing an invalid voltage signal to the first voltage terminal to the second voltage
  • the terminal provides an active voltage signal to provide an invalid voltage signal to the clock signal input.

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Abstract

本发明提供一种移位寄存单元，所述移位寄存单元包括第一信号输入端、第二信号输入端、输入及复位模块、上拉模块、下拉模块、下拉控制模块、时钟信号输入端、第一电平输入端、第二电平输入端、第一电压端、第二电压端、信号输出端、放电模块和漏电抑制模块。本发明还提供一种栅极驱动电路、一种触控显示装置和一种移位寄存单元的驱动方法。所述触控显示装置在进行显示时不会出现暗线现象。

Description

移位寄存单元及驱动方法、栅极驱动电路和触控显示装置 技术领域
本发明涉及显示技术领域，具体地，涉及一种移位寄存单元、该移位寄存单元的驱动方法、一种栅极驱动电路和一种包括该栅极驱动电路的触控显示装置。
背景技术
目前，触控显示面板已经成为主流显示终端配置，电容式触摸屏占绝对优势。为减小盒厚，电容式触摸屏通过采用嵌入式(In Cell)方案，使得触控面板与显示面板一体化。
通常，利用分时驱动的方法驱动所述触控显示装置进行显示。分时驱动是指在一帧画面时间内，交替进行显示和触控的方法。在使用具有栅极驱动电路的阵列基板制作嵌入式触摸屏时，为提高触控效果，将显示装置的一帧时间分为多个交替进行的显示阶段和触控阶段，提高触控的报点率。在触控阶段中，显示驱动暂停，暂停的那一级移位寄存单元的第一节点，在前一级预充电后一直处于高电平，由于与第一节点相连的放电模块存在固有的漏电流，在触控扫描阶段，第一节点会通过放电模块漏电，无法保持高电平状态。在恢复显示阶段时，此级移位寄存单元的第一节点(例如，上拉节点)电压比其他级的第一节点电压要低，会导致该级栅极驱动电路输出的信号电压比其他级要低，在显示时会产生一条暗线。在整个触控显示过程中有多次显示阶段与触控阶段交替暂停的时间，在显示屏上会出现多条暗线，造成显示效果的下降甚至显示故障。
因此，如何避免显示时出现暗线成为本领域亟待解决的技术问题。
发明内容
本发明的目的在于提供一种移位寄存单元、一种栅极驱动电路、一种包括该栅极驱动电路的触控显示装置和一种移位寄存单元的驱 动方法。所述触控显示装置在显示时不会出现暗线。
为了实现上述目的，作为本发明的一个方面，提供一种移位寄存单元，所述移位寄存单元用于触控显示装置中，其中，所述移位寄存单元包括第一信号输入端、第二信号输入端、输入及复位模块、上拉模块、下拉模块、下拉控制模块、时钟信号输入端、第一电平输入端、第二电平输入端、第一电压端、第二电压端、信号输出端、放电模块和漏电抑制模块，
所述输入及复位模块的第一控制端与所述第一信号输入端相连，所述输入及复位模块的第二控制端与所述第二信号输入端相连，所述输入及复位模块的第一输入端与所述第一电压端相连，所述输入及复位模块的第二输入端与所述第二电压端相连，所述输入及复位模块的输出端与第一节点相连；当所述第一信号输入端接收到有效电压信号且所述第二信号输入端接收到无效电压信号时，所述第一电压端与所述输入及复位模块的输出端导通，当所述第一信号输入端接收到无效电压信号且所述第二信号输入端接收到有效电压信号时，所述第二电压端与所述输入及复位模块的输出端导通；
所述上拉模块的输入端与所述时钟信号输入端相连，所述上拉模块的输出端与所述信号输出端相连，所述上拉模块的控制端与所述第一节点相连；当所述上拉模块的控制端接收到所述第一节点的有效电压信号时，所述上拉模块的输入端与所述信号输出端导通；
所述下拉模块的输入端与所述第二电平输入端相连，所述下拉模块的输出端与所述信号输出端相连，所述下拉模块的控制端与第二节点相连；当所述下拉模块的控制端接收到所述第二节点的有效电压信号时，所述下拉模块的输入端与所述下拉模块的输出端导通；
所述下拉控制模块的控制端与所述第一节点相连，所述下拉控制模块的输出端与所述第二节点相连，所述下拉控制模块的第一输入端与所述第一电平输入端相连，所述下拉控制模块的第二输入端与所述第二电平输入端相连；当所述下拉控制模块的控制端接收到有效电压信号时，将所述第二电平输入端与所述下拉控制模块的输出端导通，当所述下拉控制模块的控制端接收到无效电压信号时，将所述第一电 平输入端与所述下拉控制模块的输出端导通；
所述放电模块的输出端与所述第一节点相连，所述放电模块的控制端与所述第二节点相连，所述放电模块的输入端与所述漏电抑制模块的输出端相连；当所述放电模块的控制端接收到有效电压信号时，所述放电模块的输入端与所述放电模块的输出端导通；
所述漏电抑制模块能够在所述放电模块的控制端接收到无效电压信号时，向所述放电模块的输入端提供有效电压信号，并且所述漏电抑制模块能够在所述放电模块的控制端接收到有效电压信号时，向所述放电模块的输入端提供无效电压信号。
优选地，所述放电模块包括放电晶体管，所述放电晶体管的栅极形成为所述放电模块的控制端，所述放电晶体管的第一极形成为所述放电模块的输出端，所述放电晶体管的第二极形成为所述放电模块的输入端。
优选地，所述漏电抑制模块包括第一漏电抑制晶体管，所述第一漏电抑制晶体管的栅极与所述第一电压端相连，所述第一漏电抑制晶体管的第一极形成为所述漏电抑制模块的输出端，所述第一漏电抑制晶体管的第二极与所述第二电压端相连。
优选地，所述漏电抑制模块还包括第二漏电抑制晶体管，所述第二漏电抑制晶体管的栅极与所述第二电压端相连，所述第二漏抑制电晶体管的第一极与所述放电模块的输入端相连，所述第二漏电抑制晶体管的第二极与所述第一电压端相连。
优选地，所述上拉模块包括上拉晶体管和存储电容，所述上拉晶体管的栅极形成为所述上拉模块的控制端，所述上拉晶体管的第一极形成为所述上拉模块的输入端，所述上拉晶体管的第二极形成为所述上拉模块的输出端，所述存储电容的第一端与所述第一节点相连，所述存储电容的第二端与所述上拉模块的输出端相连。
优选地，所述下拉模块包括下拉晶体管，所述下拉晶体管的栅极形成为所述下拉模块的控制端，所述下拉晶体管的第一极形成为所述下拉模块的输出端，所述下拉晶体管的第二极形成为所述下拉模块的输入端。
优选地，所述下拉控制模块包括第一控制晶体管、第二控制晶体管、第三控制晶体管和第四控制晶体管，所述第一控制晶体管的栅极和第一极与所述第一电平输入端相连，所述第一控制晶体管的第二极与所述第二控制晶体管的栅极相连，所述第二控制晶体管的第一极与所述第一电平输入端相连，所述第二控制晶体管的第二极形成为所述下拉控制模块的控制端，所述第三控制晶体管的栅极形成为所述下拉控制模块的输出端，所述第三控制晶体管的第一极与所述第一控制晶体管的第二极相连，所述第三控制晶体管的第二极与所述第二电平输入端相连，所述第四控制晶体管的栅极与所述第一节点相连，所述第四控制晶体管的第一极与所述第二节点相连，所述第四控制晶体管的第二极与所述第二电平输入端相连。
优选地，所述复位及输入模块包括第一复位及输入晶体管和第二复位及输入晶体管，所述第一复位及输入晶体管的栅极与所述第一信号输入端相连，所述第一复位及输入晶体管的第一极与所述第一电压端相连，所述第一复位及输入晶体管的第二极与所述第一节点相连，所述第二复位及输入晶体管的栅极与所述第二信号输入端相连，所述第二复位及输入晶体管的第一极与所述第一节点相连，所述第二复位及输入晶体管的第二极与所述第二电压端相连。
作为本发明的还一个方面，提供一种栅极驱动电路，所述栅极驱动电路包括级联的多级移位寄存单元，所述栅极驱动电路的工作周期包括交替进行的显示阶段和触控阶段，多级所述移位寄存单元被划分为多组，每组所述移位寄存单元包括N个移位寄存单元，每组所述移位寄存单元对应一个所述显示阶段，N为自然数，其中，至少从第二组所述移位寄存单元开始，每组所述移位寄存单元中的至少第一级移位寄存单元为本发明所提供的上述移位寄存单元。
作为本发明的再一个方面，提供一种触控显示装置，所述触控显示装置包括栅极驱动电路和触控驱动电路，所述触控驱动电路包括多个输出端，其中，所述栅极驱动电路为本发明所提供的上述栅极驱动电路，所述触控驱动电路的多个输出端被划分为多组，每组所述输出端包括M个输出端，M为自然数，每组所述输出端对应一个所述 触控阶段。
作为本发明的又一个方面，提供一种移位寄存单元的驱动方法，其中，所述移位寄存单元包括本发明所提供的上述移位寄存单元，在执行正向扫描时，所述驱动方法的每个周期都包括：
充电阶段：向所述第一信号输入端提供有效电压信号，向所述第二信号输入端提供无效电压信号，向所述第一电压端提供有效电压信号，向所述第二电压端提供无效电压信号，向所述时钟信号输入端提供无效电压信号；
在触控阶段：向所述第一信号输入端提供无效电压信号，向所述第二信号输入端提供无效电压信号，向所述第一电压端提供有效电压信号，向所述第二电压端提供有效电压信号，向所述时钟信号输入端提供无效电压信号；
在输出阶段：向所述第一信号输入端提供无效电压信号，向所述第二信号输入端提供无效电压信号，向所述第一电压端提供有效电压信号，向所述第二电压端提供无效电压信号，向所述时钟信号输入端提供有效电压信号；
在输出拉低阶段：向所述第二信号输入端提供有效电压信号，向所述第一信号输入端提供无效电压信号，向所述第一电压端提供有效电压信号，向所述第二电压端提供无效电压信号，向所述时钟信号输入端提供无效电压信号；或者
在执行反向扫描时，所述驱动方法的每个周期都包括：
充电阶段：向所述第一信号输入端提供无效电压信号，向所述第二信号输入端提供有效电压信号，向所述第一电压端提供无效电压信号，向所述第二电压端提供有效电压信号，向所述时钟信号输入端提供无效电压信号；
在触控阶段：向所述第一信号输入端提供无效电压信号，向所述第二信号输入端提供无效电压信号，向所述第一电压端提供有效电压信号，向所述第二电压端提供有效电压信号，向所述时钟信号输入端提供无效电压信号；
在输出阶段：向所述第一信号输入端提供无效电压信号，向所 述第二信号输入端提供无效电压信号，向所述第一电压端提供无效电压信号，向所述第二电压端提供有效电压信号，向所述时钟信号输入端提供有效电压信号；
在输出拉低阶段：向所述第一信号输入端提供有效电压信号，向所述第二信号输入端提供无效电压信号，向所述第一电压端提供无效电压信号，向所述第二电压端提供有效电压信号，向所述时钟信号输入端提供无效电压信号。
在本发明中，漏电抑制模块在触控阶段向放电模块提供有效信号，且该有效信号被传递至第一节点，因此，在触控阶段，第一节点不会通过放电模块漏电，从而可以确保在触控阶段结束后的输出阶段能够将第一节点保持高电平，并进一步确保输出阶段中正常的输出，从而可以避免在包括所述移位寄存单元的显示装置进行显示时出现暗线等缺陷。
附图说明
附图是用来提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。在附图中：
图1是本发明所提供的移位寄存单元的结构示意图；
图2是本发明所提供的移位寄存单元的优选实施方式的示意图；
图3是图2中所提供的移位寄存单元正向扫描时的信号时序图；
图4是图2中所提供的移位寄存单元反向扫描时的信号时序图；
图5是本发明所提供的栅极驱动电路的示意图；
图6是本发明所提供的栅极驱动电路的正向扫描时的信号时序图；
图7是本发明所提供的栅极驱动电路的反向扫描时的信号时序图。
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理 解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
作为本发明的一个方面，提供一种移位寄存单元，所述移位寄存单元用于触控显示装置中，所述移位寄存单元的每个工作周期包括充电阶段、触控阶段、输出阶段和输出拉低阶段，如图1所示，所述移位寄存单元包括第一信号输入端OUT_N-1、第二信号输入端OUT_N+1、输入及复位模块600、上拉模块100、下拉模块200、时钟信号输入端CK、第一电平输入端Vdd、第二电平输入端Vss、第一电压端CN、第二电压端CNB、信号输出端OUT、放电模块400、漏电抑制模块500和下拉控制模块300。
如图1中所示，输入及复位模块600的第一控制端与第一信号输入端OUT_N-1相连，输入及复位模块600的第二控制端与第二信号输入端OUT_N+1相连，输入及复位模块600的第一输入端与第一电压端CN相连，输入及复位模块600的第二输入端与第二电压端CNB相连，输入及复位模块600的输出端与第一节点PU相连。当第一信号输入端OUT_N-1接收到有效电压信号且第二信号输入端OUT_N+1接收到无效电压信号时，第一电压端CN与输入及复位模块600的输出端导通；当第一信号输入端OUT_N-1接收到无效电压信号且第二信号输入端OUT_N+1接收到有效电压信号时，第二电压端CNB与输入及复位模块600的输出端导通。
第一电压端CN和第二电压端CNB按照需求提供有效电压信号或无效电压信号，下文中稍后将结合本发明的移位寄存单元的工作原理对如何选择第一电压端CN和第二电压端CNB提供的电压信号进行描述。
上拉模块100的输入端与时钟信号输入端CK相连，上拉模块100的输出端与信号输出端OUT相连，上拉模块100的控制端与第一节点PU相连。当上拉模块100的控制端接收到第一节点PU的有效电压信号时，上拉模块100的输入端与信号输出端OUT导通。
下拉模块200的输入端与第二电平输入端Vss相连，下拉模块200的输出端与信号输出端OUT相连，下拉模块200的控制端与第 二节点PD相连。当下拉模块200的控制端接收到第二节点PD的有效电压信号时，下拉模块200的输入端与下拉模块200的输出端导通。
下拉控制模块300的控制端与第一节点PU相连，下拉控制模块300的输出端与第二节点PD相连，下拉控制模块300的第一输入端与第一电平输入端Vdd相连，下拉控制模块300的第二输入端与第二电平输入端Vss相连。当下拉控制模块300的控制端接收到有效电压信号时，第二电平输入端Vss与下拉控制模块300的输出端导通；当下拉控制模块300的控制端接收到无效电压信号时，第一电平输入端Vdd与下拉控制模块300的输出端导通。
放电模块400的输出端与第一节点PU相连，放电模块400的控制端与第二节点PD相连，放电模块400的输入端与漏电抑制模块500的输出端相连，连接点为NET1，当放电模块400的控制端接收到有效电压信号时，放电模块400的输入端与放电模块400的输出端导通。
漏电抑制模块500能够在放电模块400的控制端接收到无效电压信号时向放电模块400的输入端提供有效电压信号，并且，漏电抑制模块500能够在放电模块400的控制端接收到有效电压信号时向放电模块400的输入端提供无效电压信号。
通过漏电抑制模块500的设置，可以确保在输出阶段中，第一节点PU保持高电平，并进一步确保输出阶段中正常的输出，从而可以避免在包括所述移位寄存单元的显示装置进行显示时出现暗线等缺陷。
本发明所提供的移位寄存单元用于栅极驱动电路中，而所述栅极驱动电路用于触控显示装置中。利用包括所述移位寄存单元的栅极驱动电路为触控显示装置提供扫描信号。
在本发明所提供的移位寄存单元中，第一信号输入端OUT_N-1和第二信号输入端OUT_N+1中的一者用作移位寄存单元的控制信号输入端，另一者用作该移位寄存单元的复位信号输入端。
当所述显示装置只能执行正向扫描时，第一信号输入端OUT_N-1为控制信号输入端，第二信号输入端OUT_N+1为复位信号输入端。此时，第一电压端CN提供有效电压信号，第二电压端 CNB在充电阶段、输出阶段和输出拉低阶段提供无效电压信号。
当所述显示装置只能执行反向扫描时，第一信号输入端OUT_N-1为复位信号输入端，第二信号输入端OUT_N+1为控制信号输入端。此时，第一电压端CN在充电阶段、输出阶段和输出拉低阶段提供无效电压信号，第二电压端CNB提供有效电压信号。第一电平输入端Vdd至少在显示阶段的各个子阶段提供有效电压信号，第二电平输入端Vss始终提供无效电压信号。
当所述显示装置能够执行双向扫描时，在正向扫描时，第一信号输入端OUT_N-1为控制信号输入端，第二信号输入端OUT_N+1为复位信号输入端，第一电压端CN提供有效电压信号，第二电压端CNB在充电阶段、输出阶段和输出拉低阶段提供无效电压信号；在反向扫描时，第一信号输入端OUT_N-1为复位信号输入端，第二信号输入端OUT_N+1为控制信号输入端，第一电压端CN在充电阶段、输出阶段和输出拉低阶段提供无效电压信号，第二电压端CNB提供有效电压信号。
由于上拉模块100的输入端与时钟信号输入端CK相连，因此，移位寄存单元在输出阶段输出的有效电压信号是由时钟信号输入端CK输入的。
如上文中所述，本发明所提供的移位寄存单元用于触控显示装置中。显示装置的一帧时间包括显示阶段和触控阶段。移位寄存单元的工作周期中的充电阶段、输出阶段和输出拉低阶段属于显示阶段的子阶段。由此可知，在本发明所使用的显示装置中，触控阶段是穿插在显示阶段的各个子阶段之间的。在触控阶段，向显示装置提供触控驱动信号和触控感应信号，并且移位寄存单元的输出端无输出。
下面结合本发明所提供的显示装置的驱动方法对所述移位寄存单元的工作原理进行说明。
图3中所示的是执行正向扫描时，各个信号的时序图。所述驱动方法的每个工作周期都包括：
充电阶段t1：向第一信号输入端OUT_N-1提供有效电压信号，向第二信号输入端OUT_N+1提供无效电压信号，向第一电压端CN 提供有效电压信号，向第二电压端CNB提供无效电压信号，向时钟信号输入端CK提供无效电压信号。在此阶段，第一电压端CN与输入及复位模块600的输出端导通，从而利用第一电压端CN提供的有效电压信号向第一节点PU充电。由于第一节点PU此时接收到了有效电压信号，下拉控制模块300向第二节点PD输出无效电压信号。由于时钟信号输入端CK输入的是无效电压信号，因此，在充电阶段t1，信号输出端OUT输出无效电压信号。与此同时，放电模块400的控制端收到的是第二节点PD的无效电压信号，因此，放电模块400的输入端与输出端之间是断开的，因此，不会对第一节点PU的电位造成影响。鉴于此时放电模块400的控制端接收到无效电压信号，因此，漏电抑制模块500向放电模块400的输入端提供有效电压信号。如果放电模块400的输入端与输出端之间出现漏电现象，那么漏电抑制模块500提供的有效电压信号被传输至放电模块400的输出端(即，第一节点PU)，从而不会对第一节点PU的电位造成影响。
触控阶段t2：向第一信号输入端OUT_N-1提供无效电压信号，向第二信号输入端OUT_N+1提供无效电压信号，向第一电压端CN提供有效电压信号，向第二电压端CNB提供有效电压信号，向时钟信号输入端CK提供无效电压信号。在移位寄存单元中，第一节点PU的电位被保持在充电阶段t1的水平。因此，下拉控制模块300向第二节点PD输出无效电压信号。由于时钟信号输入端CK输入的是无效电压信号，因此，在触控阶段t2，信号输出端OUT输出无效电压信号。与此同时，放电模块400的控制端收到的是第二节点PD的无效电压信号，因此，放电模块400的输入端与输出端之间是断开的，因此，不会对第一节点PU的电位造成影响。鉴于此时放电模块400的控制端接收到无效电压信号，因此，漏电抑制模块500向放电模块的输入端提供有效电压信号。如果放电模块400的输入端与输出端之间出现漏电现象，那么漏电抑制模块500提供的有效电压信号被传输至放电模块400的输出端(即，第一节点PU)，从而不会对第一节点PU的电位造成影响。在触控阶段t2，通过触控驱动电路对触控驱动信号线进行扫描，在图3中所示的实施方式中，示出了触控驱动信 号线Tx1、Tx2、Tx3、Tx4。
输出阶段t3：向第一信号输入端OUT_N-1提供无效电压信号，向第二信号输入端OUT_N+1提供无效电压信号，向第一电压端CN提供有效电压信号，向第二电压端CNB提供无效电压信号，向时钟信号输入端CK提供有效电压信号。在移位寄存单元中，在输出阶段t3中，第一节点PU可以保持有效电压信号，从而可以将上拉模块100的输入端与信号输出端OUT导通，以输出通过时钟信号输入端CK输入的有效电压信号。在此阶段，下拉控制模块300的控制端接收到有效电压信号，因此，第二电平输入端Vss与所述下拉控制模块300的输出端导通，维持第二节点PD的无效电平状态，因此，下拉模块200的输入端与输出端断开，从而不会影响到移位寄存单元的正常输出。
输出拉低阶段t4，向第二信号输入端OUT_N+1提供有效电压信号，向第一信号输入端OUT_N-1提供无效电压信号，向第一电压端CN提供有效电压信号，向第二电压端CNB提供无效电压信号，向时钟信号输入端CK提供无效电压信号。在此阶段，由于第二信号输入端OUT_N+1提供有效电压信号，因此，输入及复位模块600的输出端与第二电压端CNB导通，相应地，导致下拉控制模块300的输出端与第一电平输入端Vdd导通。由于第一电平输入端Vdd提供有效电压信号，因此，第二节点PD接收到有效电压信号，从而可以控制下拉模块200的输入端与输出端导通，使得信号输出端OUT输出无效电压信号。同时，由于第二节点PD为有效电压信号，因此，放电模块400的输入端与输出端导通。在此阶段，漏电抑制模块500向放电模块400的输入端提供无效电压信号，从而对第一节点PU放电。
反向扫描时的工作原理与正向扫描时的工作原理类似，这里不再赘述。
如上文中所述，在本发明所提供的移位寄存单元的工作过程中，触控阶段位于输出阶段之前，在触控阶段中，漏电抑制模块500向放电模块400的输入端提供有效电压信号。因此，即便在触控阶段放电 模块400漏电也不会影响到第一节点PU的电位，从而可以确保输出阶段中，第一节点PU仍然保持有效电压信号，并进一步确保输出阶段中的正常的输出，从而可以避免在包括所述移位寄存单元的显示装置进行显示时出现暗线等缺陷。
在本发明中，“有效电压信号”是指，能够控制接收该有效电压信号的模块开启的电压信号，而“无效电压信号”则是指能够控制接收该无效电压信号的模块关闭的电压信号。
例如，对于N型晶体管而言，高电平信号为有效电压信号，低电平信号为无效电压信号；对于P型晶体管而言，低电平信号为有效电压信号，高电平信号为无效电压信号。
在本发明所提供的一种具体实施方式中，移位寄存单元中所有的晶体管均为N型晶体管，因此，有效电压信号是指高电平信号，无效电压信号是指低电平信号。
本领域技术人员应当理解的是，在本发明中，在触控阶段之外的其他阶段，时钟信号输入端CK输入的时钟信号为脉冲信号，应当确保时钟信号输入端CK在移位寄存单元的输出阶段输出一个有效的时钟信号(该有效时钟信号能够开启与所述移位寄存单元的输出端相连的栅线上的薄膜晶体管)，而上拉模块100的作用则是在输出阶段将有效的时钟信号作为输出信号输出至信号输出端OUT。在触控阶段，时钟信号输入端CK输入的信号始终为无效电压信号，从而不会对信号输出端OUT的电位造成影响。
为了简化所述移位寄存单元的结构，优选地，如图2所示，放电模块400可以包括放电晶体管T3，放电晶体管T3的栅极形成为放电模块400的控制端，并且与第二节点PD相连；放电晶体管T3的第一极形成为放电模块400的输出端，并与第一节点PU相连；放电晶体管T3的第二极形成为放电模块400的输入端，并与漏电抑制模块500的输出端相连。相应地，漏电抑制模块500能够在所述触控阶段之外的其他阶段提供无效电压信号。
如上文中所述，在输出拉低阶段t4，第二节点PD为有效电压信号的电平，因此，放电晶体管T3导通，因此，漏电抑制模块500输 出的无效电压信号可以通过放电晶体管T3传递至第一节点PU，从而可以在输出拉低阶段将第一节点PU的电位下拉为无效电平。
在本发明中，对漏电抑制模块500的具体结构并没有特殊的限制，只要能够实现在触控阶段向放电模块400提供有效电压信号、且不影响移位寄存单元的其他工作阶段即可。
作为本发明的一种优选实施方式，如图2所示，漏电抑制模块500可以包括第一漏电抑制晶体管T1，第一漏电抑制晶体管T1的栅极与第一电压端CN相连，第一漏电抑制晶体管T1的第一极形成为漏电抑制模块500的输出端，并与放电模块400的输入端(即，放电晶体管T3的第二极)相连，第一漏电抑制晶体管T1的第二极与第二电压端CNB相连。
本实施例所提供的漏电抑制模块500适用于仅执行正向扫描的移位寄存单元。始终向第一电压端CN提供有效电压信号，在触控阶段向第二电压端CNB提供有效电压信号，在其他阶段向第二电压端CNB提供无效电压信号。由于第一电压端CN提供有效电压信号，因此，在正向扫描时，第一漏电抑制晶体管T1是始终导通的。在显示阶段的各个子阶段中，可以向放电模块400的输入端提供无效电压信号，以确保移位寄存单元在显示阶段正常工作。在触控阶段，可以向放电模块400的输入端提供有效电压信号，防止第一节点PU漏电。
为了使得所述移位寄存单元适用于反向扫描，优选地，漏电抑制模块500还可以包括第二漏电抑制晶体管T2。如图2中所示，第二漏电抑制晶体管T2的栅极与第二电压端CNB相连，第二漏电抑制晶体管T2的第一极与放电模块400的输入端相连，第二漏电抑制晶体管T2的第二极与第一电压端CN相连。
需要指出的是，正向扫描时向第一电压端CN提供的电压信号不同于反向扫描时向第一电压端CN提供的电压信号；正向扫描时向第二电压端CNB提供的电压信号不同于反向扫描时向第二电压端CNB提供的电压信号。
具体地，在正向扫描时，始终向第一电压端CN提供有效电压信号，在触控阶段向第二电压端CNB提供有效电压信号，其余阶段 向第二电压端CNB提供无效电压信号。在反向扫描时，始终向第二电压端CNB提供有效电压信号，在触控阶段向第一电压端CN提供有效电压信号，其余阶段向第一电压端CN提供无效电压信号。
因此，在正向扫描时，第一漏电抑制晶体管T1始终导通，第二漏电抑制晶体管T2始终截止。在反向扫描时，第一漏电抑制晶体管T1始终截止，第二漏电抑制晶体管T2始终导通。下文中稍后将详细介绍图2中所示结构的漏电抑制模块500的工作原理。
在本发明中对上拉模块100的具体结构也没有特殊的要求，为了简化移位寄存单元的结构，优选地，如图2所示，上拉模块100包括上拉晶体管T4和存储电容C，上拉晶体管T4的栅极形成为上拉模块100的控制端，并与第一节点PU相连，上拉晶体管T4的第一极形成为上拉模块100的输入端，上拉晶体管T4的第二极形成为上拉模块100的输出端。存储电容C的第一端与第一节点PU相连，存储电容C的第二端与上拉模块100的输出端相连。
当向第一节点PU提供有效电压信号时，上拉晶体管T4导通，从时钟信号输入端CK输入的时钟信号为信号输出端OUT的输出信号。当向第一节点PU提供无效电压信号时，上拉晶体管T4截止。在充电阶段，可以向存储电容C充电，在触控阶段，存储电容C可以维持第一节点PU处于有效电平状态。
同样地，在本发明中对下拉模块200的具体结构也没有特殊的限定，为了简化移位寄存单元的结构，优选地，如图2所示，下拉模块200包括下拉晶体管T11，下拉晶体管T11的栅极形成为下拉模块200的控制端，并与第二节点PD相连，下拉晶体管T11的第一极形成为下拉模块200的输出端，下拉晶体管T11的第二极形成为下拉模块200的输入端。
当向第二节点PD提供有效电压信号时，下拉晶体管T11导通，并将通过第二电平输入端Vss输入的低电平信号输出至信号输出端OUT，从而可以使得信号输出端OUT输出无效电压信号。
在本公开中，对下拉控制模块300的具体结构也没有特殊的限制。例如，图2中示出了下拉控制模块300的一种优选实施方式。如 图2中所示，下拉控制模块300包括第一控制晶体管T7、第二控制晶体管T8、第三控制晶体管T9和第四控制晶体管T10。具体地，第一控制晶体管T7的栅极和第一极与第一电平输入端Vdd相连，第一控制晶体管T7的第二极与第二控制晶体管T8的栅极相连，第二控制晶体管T8的第一极与第一电平输入端Vdd相连，第二控制晶体管T8的第二极形成为下拉控制模块300的控制端，并与第二节点PD相连，第三控制晶体管T9的栅极形成为下拉控制模块300的输出端，并与第一节点PU相连，第三控制晶体管T9的第一极与第一控制晶体管T7的第二极相连，第三控制晶体管T9的第二极与第二电平输入端Vss相连，第四控制晶体管T10的栅极与第一节点PU相连，第四控制晶体管T10的第一极与第二节点PD相连，第四控制晶体管T10的第二极与第二电平输入端Vss相连。
在本公开中，对复位及输入模块600的具体结构也不做限制，只要能够起到在充电阶段向第一节点PU充电、在输出拉低阶段对第一节点PU进行放电即可。在图2所示的优选实施方式中，复位及输入模块600包括第一复位及输入晶体管T5和第二复位及输入晶体管T6。如图中所示，第一复位及输入晶体管T5的栅极与第一信号输入端OUT_N-1相连，第一复位及输入晶体管T5的第一极与第一电压端CN相连，第一复位及输入晶体管T5的第二极与第一节点PU相连。第二复位及输入晶体管T6的栅极与第二信号输入端OUT_N+1相连，第二复位及输入晶体管T6的第一极与第一节点PU相连，第二复位及输入晶体管T6的第二极与第二电压端CNB相连。
此处，对第一电压端CN和第二电压端CNB的限定与上文中相同，即：当包括所述移位寄存单元的栅极驱动电路进行正向扫描时，通过第一电压端CN输入的信号始终为有效电压信号，通过所述第二电压端CNB输入的信号在触控阶段为有效电压信号，其余阶段为无效电压信号；当包括所述移位寄存单元的栅极驱动电路反向扫描时，通过第一电压端CN输入的信号在触控阶段为有效电压信号，其余阶段为无效电压信号，通过第二电压端CNB输入的信号始终为有效电压信号。
第一信号输入端OUT_N-1与上一级移位寄存单元的输出端相连，第二信号输入端OUT_N+1与下一级移位寄存单元的输出端相连。当正向扫描时，第一信号输入端OUT_N-1输入的信号为高电平信号时，第二信号输入端OUT_N+1输入的信号为低电平信号，第一复位及输入晶体管T5导通，第一电压端CN输入的高电平信号通过第一复位及输入晶体管T5输送至第一节点PU。
当反向扫描时，第一信号输入端OUT_N-1输入的信号为低电平信号时，第二信号输入端OUT_N+1输入的信号为高电平信号，第二复位及输入晶体管T6导通，第二电压端CNB输入的高电平信号通过第二复位及输入晶体管T6输送至第一节点PU。
下面结合图3和图4描述图2中所提供的移位寄存单元的工作过程。在图2中所示的实施方式中，各个晶体管均是N型晶体管，因此，高电平信号为有效电压信号，低电平信号为无效电压信号。
图3中所示的是正向扫描时各个输入信号的时序图。如图3中可以看出，一个移位寄存单元的一个工作周期包括充电阶段t1、触控阶段t2、输出阶段t3和输出拉低阶段t4。
在充电阶段t1，高电平的输入信号通过第一信号输入端OUT_N-1输入，通过时钟信号输入端CK输入的时钟信号为低电平信号，通过第二信号输入端OUT_N+1输入的信号为低电平信号，第一电压端CN输入高电平信号，第二电压端CNB输入低电平信号，因此，第一复位及输入晶体管T5导通、第二复位及输入晶体管T6截止，通过第一电压端CN输入的高电平信号将对存储电容C进行充电。同时，在此阶段，第一漏电抑制晶体管T1导通，第二漏电抑制晶体管T2截止，以将低电平信号输送至放电晶体管T3的第二极。下拉控制模块300的第一控制晶体管T7导通、第三控制晶体管T9导通、第四控制晶体管T10导通，由于第一控制晶体管T7和第三控制晶体管T9的分压，导致第二控制晶体管T8截止。第一节点PU为高电平，导致上拉晶体管T4导通，由于时钟信号为低电平信号，因此输出端OUT输出低电平信号。第四控制晶体管T10的导通将第二电平输入端Vss输入的低电平信号传输至第二节点PD，使得下拉晶 体管T11截止。
在触控阶段t2，通过时钟信号输入端CK输入的时钟信号仍然为低电平信号，通过第一信号输入端OUT_N-1输入的信号为低电平，通过第二信号输入端OUT_N+1输入的信号也为低电平。第一复位及输入晶体管T5、第二复位及输入晶体管T6均截止，第一控制晶体管T7导通。由于在触控阶段第二电压端CNB输入的信号为高电平信号，因此，第一漏电抑制晶体管T1和第二漏电抑制晶体管T2均导通，并将高电平信号输送至放电晶体管T3，从而可以确保第一节点PU不会通过放电晶体管T3漏电。由于第一节点PU为高电平信号，因此，第三控制晶体管T9导通。第一控制晶体管T7和第三控制晶体管T9的分压作用导致第二控制晶体管T8截止，第四控制晶体管T10的导通使得第二节点PD持续保持低电平状态。在触控阶段，时钟信号为低电平信号，因此，OUT输出低电平信号。在触控阶段，通过触控驱动电路对触控驱动信号线进行扫描，在图3中所示的实施方式中，示出了触控驱动信号线Tx1、Tx2、Tx3、Tx4。
在输出阶段t3，时钟信号跳变为高电平信号，通过第一电压端CN输入的信号为高电平信号，通过第二电压端CNB输入的信号为低电平信号，通过第一信号输入端OUT_N-1输入的信号为低电平，通过第二信号输入端OUT_N+1输入的信号也为低电平。第一复位及输入晶体管T5、第二复位及输入晶体管T6均截止，第一控制晶体管T7导通。因此，第一节点PU的电位在存储电容C的自举作用下跳变为更高的电位，使得上拉晶体管T4导通，以使得输出端OUT输出高电平信号。在此阶段，第一漏电抑制晶体管T1导通，第二漏电抑制晶体管T2截止，因此，放电晶体管T3的第二极为低电平电压。同样，第三控制晶体管T9的导通使得第三控制晶体管T9与第一控制晶体管T7形成分压作用，使得第二控制晶体管T8截止。第四控制晶体管T10导通，维持第二节点PD的低电平状态，从而确保下拉晶体管T11的截止。
在输出拉低阶段t4，时钟信号跳变为低电平信号，通过第一电压端CN输入的信号为高电平信号，通过第二电压端CNB输入的信 号为低电平信号，通过第一信号输入端OUT_N-1输入的信号为低电平，通过第二信号输入端OUT_N+1输入的信号为高电平信号。因此，第二复位及输入晶体管T6导通，通过第二电压端CNB输入的低电平信号将第一节点PU电位拉低。第一漏电抑制晶体管T1导通，第二漏电抑制晶体管T2截止，使得放电晶体管T3的第二极为低电平电压。由于第一节点PU电位被拉低，因此，第三控制晶体管T9和第四控制晶体管T10均截止。第一控制晶体管T7的导通使得第二控制晶体管T8也导通，从而将第二节点PD电位上拉至高电平。放电晶体管T3的导通使得第一节点PU进一步被下拉，下拉晶体管T11导通使得信号输出端OUT被下拉至低电平。至此，一个移位寄存单元的一个工作周期结束。
图4中所示的是反向扫描时各个输入信号的时序图。如图4中可以看出，一个移位寄存单元的一个工作周期包括充电阶段t1、触控阶段t2、输出阶段t3和输出拉低阶段t4。
在充电阶段t1，高电平的输入信号通过第二信号输入端OUT_N+1输入，通过时钟信号输入端CK输入的时钟信号为低电平信号，通过第一信号输入端OUT_N-1输入的信号为低电平信号，第一电压端CN输入低电平信号，第二电压端CNB输入高电平信号，因此，第一复位及输入晶体管T5截止、第二复位及输入晶体管T6导通，通过第二电压端CNB输入的高电平信号将对存储电容C进行充电。同时，在此阶段，第二漏电抑制晶体管T2导通，第一漏电抑制晶体管T1截止，以将低电平信号输送至放电晶体管T3的第二极。下拉控制模块300的第一控制晶体管T7导通、第三控制晶体管T9导通、第四控制晶体管T10导通，由于第一控制晶体管T7和第三控制晶体管T9的分压，导致第二控制晶体管T8截止。第一节点PU为高电平，导致上拉晶体管T4导通，由于时钟信号为低电平信号，因此输出端OUT输出低电平信号。第四控制晶体管T10的导通将第二电平输入端Vss输入的低电平信号传输至第二节点PD，使得下拉晶体管T11截止。
在触控阶段t2，通过时钟信号输入端CK输入的时钟信号仍然 为低电平信号，通过第一信号输入端OUT_N-1输入的信号为低电平，通过第二信号输入端OUT_N+1输入的信号也为低电平，第一复位及输入晶体管T5、第二复位及输入晶体管T6均截止，第一控制晶体管T7导通。由于在触控阶段第一电压端CN输入的信号为高电平信号，因此，第一漏电抑制晶体管T1和第二漏电抑制晶体管T2均导通，并将高电平信号输送至放电晶体管T3的第二极，从而可以确保第一节点PU不会通过放电晶体管T3漏电。由于第一节点PU为高电平信号，因此，第三控制晶体管T9导通。第一控制晶体管T7和第三控制晶体管T9的分压作用导致第二控制晶体管T8截止，第四控制晶体管T10的导通使得第二节点PD持续保持低电平状态。在触控阶段，时钟信号为低电平信号，因此，输出端OUT输出低电平信号。在触控阶段，通过触控驱动电路对触控驱动信号线进行扫描，在图3中所示的实施方式中，示出了触控驱动信号线Tx1、Tx2、Tx3、Tx4。
在输出阶段t3，时钟信号跳变为高电平信号，通过第一电压端CN输入的信号为低电平信号，通过第二电压端CNB输入的信号为高电平信号，通过第一信号输入端OUT_N-1输入的信号为低电平，通过第二信号输入端OUT_N+1输入的信号也为低电平，第一复位及输入晶体管T5、第二复位及输入晶体管T6均截止，第一控制晶体管T7导通。因此，第一节点PU的电位在存储电容C的自举作用下跳变为更高的电位，使得上拉晶体管T4导通，以使得输出端OUT输出高电平信号。在此阶段，第一漏电抑制晶体管T1截止，第二漏电抑制晶体管T2导通，因此，放电晶体管T3的第二极为低电平电压。同样，第三控制晶体管T9的导通使得第三控制晶体管T9与第一控制晶体管T7形成分压作用，使得第二控制晶体管T8截止。第四控制晶体管T10导通，维持第二节点PD的低电平状态，从而确保下拉晶体管T11的截止。
在输出拉低阶段t4，时钟信号跳变为低电平信号，通过第一电压端CN输入的信号为低电平信号，通过第二电压端CNB输入的信号为高电平信号，通过第一信号输入端OUT_N-1输入的信号为高电平，通过第二信号输入端OUT_N+1输入的信号为低电平信号。因此， 第一复位及输入晶体管T5导通，通过第一电压端CN输入的低电平信号将第一节点PU电位拉低。第一漏电抑制晶体管T1截止，第二漏电抑制晶体管T2导通，使得放电晶体管T3的第二极为低电平电压。由于第一节点PU电位被拉低，因此，第三控制晶体管T9和第四控制晶体管T10均截止。第一控制晶体管T7的导通使得第二控制晶体管T8也导通，从而将第二节点PD电位上拉至高电平。放电晶体管T3的导通使得第一节点PU进一步被下拉，下拉晶体管T11导通使得信号输出端OUT被下拉至低电平。至此，一个移位寄存单元的一个工作周期结束。
作为本发明的另一个方面，提供一种栅极驱动电路，所述栅极驱动电路包括级联的多级移位寄存单元，所述栅极驱动电路的工作周期包括交替进行的显示阶段和触控阶段，多级移位寄存单元被划分为多组，每组移位寄存单元包括N个移位寄存单元，每组移位寄存单元对应一个显示阶段，其中，至少从第二组移位寄存单元开始，每组移位寄存单元的至少第一级移位寄存单元为本发明所提供的上述移位寄存单元。
图5中所示的是本发明所提供的栅极驱动电路的一种优选实施方式。容易理解的是，当多级移位寄存单元级联时，上一级移位寄存单元的输出信号是下一级移位寄存单元的输入信号。
容易理解的是，所述栅极驱动电路还包括时钟信号线、高电平信号线、起始信号线STV、低电平信号线、第一电平信号线和第二电平信号线，时钟信号线与各级移位寄存单元的时钟信号输入端相连，高电平信号线与各级移位寄存单元的第一电平输入端相连，起始信号线STV选择性地与第一级移位寄存单元的正向信号输入端以及最后一级移位寄存单元的反向信号输入端相连(正向扫描时与第一级移位寄存单元的正向信号输入端相连，反向扫描时与最后一级移位寄存单元的反向信号输入端相连)，第一电平信号线与各级移位寄存单元的第一电平输入端相连，第二电平信号线与各级移位寄存单元的第二电平输入端相连，低电平信号线与各级移位寄存单元的第二电平输入端相连。
从第二组移位寄存单元开始，每组移位寄存单元的第一级移位寄存单元是在触控阶段开始之前进行充电、触控阶段结束之后才开始输出，由于第一级移位寄存单元包括漏电抑制模块，因此，在整个触控阶段中，第一级移位寄存单元的第一节点不会漏电，从而可以确保在触控阶段结束后输出稳定的扫描信号，避免显示暗线的出现。
在本发明中，对栅极驱动电路中设置的本发明所提供的上述移位寄存单元的个数并不做特殊的限定。例如，栅极驱动电路中设置的本发明所提供的上述移位寄存单元的个数可为移位寄存单元的组数减一。
在本发明中，对N的具体数值没有特殊的规定，在本发明所提供的实施方式中，N为4。
例如，如果所述栅极驱动电路包括4组移位寄存单元，那么，该栅极驱动电路可以包括3个具有漏电抑制模块的移位寄存单元。这3个具有漏电抑制模块的移位寄存单元分别为第2组移位寄存单元的第一级移位寄存单元、第3组移位寄存单元的第一级移位寄存单元和第4组移位寄存单元的第一级移位寄存单元。
为了便于制造，优选地，所有移位寄存单元均为本发明所提供的上述移位寄存单元。
在图5中，示出了m级移位寄存单元，该m极移位寄存单元分别与显示装置的m条栅线相连。OUTPUT_1表示第一条栅线，OUTPUT_2表示第二条栅线，OUTPUT_n-1表示第n-1条栅线，OUTPUT_m-1表示第m-1条栅线，OUTPUT_m表示第m条栅线。
图6所示的是本发明所提供的栅极驱动电路在工作时各个信号的时序图。图7所示的是本发明所提供的栅极驱动电路在工作时各个信号的时序图。
在图6和图7中，Gate1、Gate2、Gate3、Gate4、Gate5、Gate6、Gate7、Gate8分别代表第一条栅线、第二条栅线、第三条栅线、第四条栅线、第五条栅线、第六条栅线、第七条栅线、第八条栅线。Tx1、Tx2、Tx3、Tx4、Tx5、Tx6、Tx7、Tx8分别代表第一条触控扫描线、第二条触控扫描线、第三条触控扫描线、第四条触控扫描线、 第五条触控扫描线、第六条触控扫描线、第七条触控扫描线、第八条触控扫描线。
在图6中，每组移位寄存单元包括四个移位寄存单元，第一条栅线Gate1、第二条栅线Gate2、第三条栅线Gate3、第四条栅线Gate4对应的移位寄存单元属于同一组，在显示阶段Display1依次输出扫描信号；第五条栅线Gate5、第六条栅线Gate6、第七条栅线Gate7、第八条栅线Gate8对应的移位寄存单元属于同一组，在显示阶段Display2依次输出扫描信号。至少第五条栅线Gate5对应的移位寄存单元为本发明所提供的包括漏电抑制模块的移位寄存单元。
与图6中相同的是，在图7中，每组移位寄存单元包括四个移位寄存单元，第一条栅线Gate1、第二条栅线Gate2、第三条栅线Gate3、第四条栅线Gate4对应的移位寄存单元属于同一组，在显示阶段Display2依次输出扫描信号；第五条栅线Gate5、第六条栅线Gate6、第七条栅线Gate7、第八条栅线Gate8对应的移位寄存单元属于同一组，在显示阶段Display1依次输出扫描信号。与图6中不同的是，至少第四条栅线Gate4对应的移位寄存单元为本发明所提供的包括漏电抑制模块的移位寄存单元。
作为本发明的另一个方面，提供一种触控显示装置，所述触控显示装置包括栅极驱动电路和触控驱动电路，其中，所述栅极驱动电路为本发明所提供的上述栅极驱动电路，所述触控驱动电路的多个输出端被划分为多组，每组所述输出端包括M个输出端，每组输出端对应一个触控阶段。
在本发明中，M和N的数值可以相同也可以不同。在图6和图7中所示的具体实施方式中，M和N均为4。
在图6和图7所示的实施方式中，分别与第一条触控扫描线Tx1、第二条触控扫描线Tx2、第三条触控扫描线Tx3、第四条触控扫描线Tx4对应的四个输出端为一组，分别与第五条触控扫描线Tx5、第六条触控扫描线Tx6、第七条触控扫描线Tx7、第八条触控扫描线Tx8对应的四个输出端为一组。在触控阶段Touch1，第一条触控扫描线Tx1、第二条触控扫描线Tx2、第三条触控扫描线Tx3、第四条触控 扫描线Tx4对应的四个输出端分别输出四个触控扫描信号，在触控阶段Touch2，第五条触控扫描线Tx5、第六条触控扫描线Tx6、第七条触控扫描线Tx7、第八条触控扫描线Tx8对应的四个输出端分别输出四个触控扫描信号。
作为本发明的还一个方面，提供一种移位寄存单元的驱动方法，其中，所述移位寄存单元为本发明所提供的上述移位寄存单元。
当进行正向扫描时，所述驱动方法的每个周期都包括：
充电阶段：向所述第一信号输入端提供有效电压信号，向所述第二信号输入端提供无效电压信号，向所述第一电压端提供有效电压信号，向所述第二电压端提供无效电压信号，向所述时钟信号输入端提供无效电压信号；
在触控阶段：向所述第一信号输入端提供无效电压信号，向所述第二信号输入端提供无效电压信号，向所述第一电压端提供有效电压信号，向所述第二电压端提供有效电压信号，向所述时钟信号输入端提供无效电压信号；
在输出阶段：向所述第一信号输入端提供无效电压信号，向所述第二信号输入端提供无效电压信号，向所述第一电压端提供有效电压信号，向所述第二电压端提供无效电压信号，向所述时钟信号输入端提供有效电压信号；
在输出拉低阶段：向所述第二信号输入端提供有效电压信号，向所述第一信号输入端提供无效电压信号，向所述第一电压端提供有效电压信号，向所述第二电压端提供无效电压信号，向所述时钟信号输入端提供无效电压信号。
当进行反向扫描时，所述驱动方法的每个周期都包括：
充电阶段：向所述第一信号输入端提供无效电压信号，向所述第二信号输入端提供有效电压信号，向所述第一电压端提供无效电压信号，向所述第二电压端提供有效电压信号，向所述时钟信号输入端提供无效电压信号；
在触控阶段：向所述第一信号输入端提供无效电压信号，向所述第二信号输入端提供无效电压信号，向所述第一电压端提供有效电 压信号，向所述第二电压端提供有效电压信号，向所述时钟信号输入端提供无效电压信号；
在输出阶段：向所述第一信号输入端提供无效电压信号，向所述第二信号输入端提供无效电压信号，向所述第一电压端提供无效电压信号，向所述第二电压端提供有效电压信号，向所述时钟信号输入端提供有效电压信号；
在输出拉低阶段：向所述第一信号输入端提供有效电压信号，向所述第二信号输入端提供无效电压信号，向所述第一电压端提供无效电压信号，向所述第二电压端提供有效电压信号，向所述时钟信号输入端提供无效电压信号。
上文中已经详细解释了利用所述驱动方法驱动所述显示装置的原理和有益效果，这里不再赘述。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (11)

  1. 一种移位寄存单元，所述移位寄存单元用于触控显示装置中，其特征在于，所述移位寄存单元包括第一信号输入端、第二信号输入端、输入及复位模块、上拉模块、下拉模块、下拉控制模块、时钟信号输入端、第一电平输入端、第二电平输入端、第一电压端、第二电压端、信号输出端、放电模块和漏电抑制模块，
    所述输入及复位模块的第一控制端与所述第一信号输入端相连，所述输入及复位模块的第二控制端与所述第二信号输入端相连，所述输入及复位模块的第一输入端与所述第一电压端相连，所述输入及复位模块的第二输入端与所述第二电压端相连，所述输入及复位模块的输出端与第一节点相连；当所述第一信号输入端接收到有效电压信号且所述第二信号输入端接收到无效电压信号时，所述第一电压端与所述输入及复位模块的输出端导通，当所述第一信号输入端接收到无效电压信号且所述第二信号输入端接收到有效电压信号时，所述第二电压端与所述输入及复位模块的输出端导通；
    所述上拉模块的输入端与所述时钟信号输入端相连，所述上拉模块的输出端与所述信号输出端相连，所述上拉模块的控制端与所述第一节点相连；当所述上拉模块的控制端接收到所述第一节点的有效电压信号时，所述上拉模块的输入端与所述信号输出端导通；
    所述下拉模块的输入端与所述第二电平输入端相连，所述下拉模块的输出端与所述信号输出端相连，所述下拉模块的控制端与第二节点相连；当所述下拉模块的控制端接收到所述第二节点的有效电压信号时，所述下拉模块的输入端与所述下拉模块的输出端导通；
    所述下拉控制模块的控制端与所述第一节点相连，所述下拉控制模块的输出端与所述第二节点相连，所述下拉控制模块的第一输入端与所述第一电平输入端相连，所述下拉控制模块的第二输入端与所述第二电平输入端相连；当所述下拉控制模块的控制端接收到有效电压信号时，将所述第二电平输入端与所述下拉控制模块的输出端导通，当所述下拉控制模块的控制端接收到无效电压信号时，将所述第一电 平输入端与所述下拉控制模块的输出端导通；
    所述放电模块的输出端与所述第一节点相连，所述放电模块的控制端与所述第二节点相连，所述放电模块的输入端与所述漏电抑制模块的输出端相连；当所述放电模块的控制端接收到有效电压信号时，所述放电模块的输入端与所述放电模块的输出端导通；
    所述漏电抑制模块能够在所述放电模块的控制端接收到无效电压信号时，向所述放电模块的输入端提供有效电压信号，并且所述漏电抑制模块能够在所述放电模块的控制端接收到有效电压信号时，向所述放电模块的输入端提供无效电压信号。
  2. 根据权利要求1所述的移位寄存单元，其特征在于，所述放电模块包括放电晶体管，所述放电晶体管的栅极形成为所述放电模块的控制端，所述放电晶体管的第一极形成为所述放电模块的输出端，所述放电晶体管的第二极形成为所述放电模块的输入端。
  3. 根据权利要求1所述的移位寄存单元，其特征在于，所述漏电抑制模块包括第一漏电抑制晶体管，所述第一漏电抑制晶体管的栅极与所述第一电压端相连，所述第一漏电抑制晶体管的第一极形成为所述漏电抑制模块的输出端，所述第一漏电抑制晶体管的第二极与所述第二电压端相连。
  4. 根据权利要求3所述的移位寄存单元，其特征在于，所述漏电抑制模块还包括第二漏电抑制晶体管，所述第二漏电抑制晶体管的栅极与所述第二电压端相连，所述第二漏抑制电晶体管的第一极与所述放电模块的输入端相连，所述第二漏电抑制晶体管的第二极与所述第一电压端相连。
  5. 根据权利要求1至4中任意一项所述的移位寄存单元，其特征在于，所述上拉模块包括上拉晶体管和存储电容，所述上拉晶体管的栅极形成为所述上拉模块的控制端，所述上拉晶体管的第一极形成 为所述上拉模块的输入端，所述上拉晶体管的第二极形成为所述上拉模块的输出端，所述存储电容的第一端与所述第一节点相连，所述存储电容的第二端与所述上拉模块的输出端相连。
  6. 根据权利要求1至4中任意一项所述的移位寄存单元，其特征在于，所述下拉模块包括下拉晶体管，所述下拉晶体管的栅极形成为所述下拉模块的控制端，所述下拉晶体管的第一极形成为所述下拉模块的输出端，所述下拉晶体管的第二极形成为所述下拉模块的输入端。
  7. 根据权利要求1至4中任意一项所述的移位寄存单元，其特征在于，所述下拉控制模块包括第一控制晶体管、第二控制晶体管、第三控制晶体管和第四控制晶体管，所述第一控制晶体管的栅极和第一极与所述第一电平输入端相连，所述第一控制晶体管的第二极与所述第二控制晶体管的栅极相连，所述第二控制晶体管的第一极与所述第一电平输入端相连，所述第二控制晶体管的第二极形成为所述下拉控制模块的控制端，所述第三控制晶体管的栅极形成为所述下拉控制模块的输出端，所述第三控制晶体管的第一极与所述第一控制晶体管的第二极相连，所述第三控制晶体管的第二极与所述第二电平输入端相连，所述第四控制晶体管的栅极与所述第一节点相连，所述第四控制晶体管的第一极与所述第二节点相连，所述第四控制晶体管的第二极与所述第二电平输入端相连。
  8. 根据权利要求7所述的移位寄存单元，其特征在于，所述复位及输入模块包括第一复位及输入晶体管和第二复位及输入晶体管，所述第一复位及输入晶体管的栅极与所述第一信号输入端相连，所述第一复位及输入晶体管的第一极与所述第一电压端相连，所述第一复位及输入晶体管的第二极与所述第一节点相连，所述第二复位及输入晶体管的栅极与所述第二信号输入端相连，所述第二复位及输入晶体管的第一极与所述第一节点相连，所述第二复位及输入晶体管的第二 极与所述第二电压端相连。
  9. 一种栅极驱动电路，所述栅极驱动电路包括级联的多级移位寄存单元，所述栅极驱动电路的工作周期包括交替进行的显示阶段和触控阶段，多级所述移位寄存单元被划分为多组，每组所述移位寄存单元包括N个移位寄存单元，每组所述移位寄存单元对应一个所述显示阶段，N为自然数，其特征在于，至少从第二组所述移位寄存单元开始，每组所述移位寄存单元中的至少第一级移位寄存单元为权利要求1至8中任意一项所述的移位寄存单元。
  10. 一种触控显示装置，所述触控显示装置包括栅极驱动电路和触控驱动电路，所述触控驱动电路包括多个输出端，其特征在于，所述栅极驱动电路为权利要求9所述的栅极驱动电路，所述触控驱动电路的多个输出端被划分为多组，每组所述输出端包括M个输出端，M为自然数，每组所述输出端对应一个所述触控阶段。
  11. 一种如权利要求1所述移位寄存单元的驱动方法，其特征在于，
    当执行正向扫描时，所述驱动方法的每个周期都包括：
    充电阶段：向所述第一信号输入端提供有效电压信号，向所述第二信号输入端提供无效电压信号，向所述第一电压端提供有效电压信号，向所述第二电压端提供无效电压信号，向所述时钟信号输入端提供无效电压信号；
    在触控阶段：向所述第一信号输入端提供无效电压信号，向所述第二信号输入端提供无效电压信号，向所述第一电压端提供有效电压信号，向所述第二电压端提供有效电压信号，向所述时钟信号输入端提供无效电压信号；
    在输出阶段：向所述第一信号输入端提供无效电压信号，向所述第二信号输入端提供无效电压信号，向所述第一电压端提供有效电压信号，向所述第二电压端提供无效电压信号，向所述时钟信号输入 端提供有效电压信号；
    在输出拉低阶段：向所述第二信号输入端提供有效电压信号，向所述第一信号输入端提供无效电压信号，向所述第一电压端提供有效电压信号，向所述第二电压端提供无效电压信号，向所述时钟信号输入端提供无效电压信号；
    当执行反向扫描时，所述驱动方法的每个周期都包括：
    充电阶段：向所述第一信号输入端提供无效电压信号，向所述第二信号输入端提供有效电压信号，向所述第一电压端提供无效电压信号，向所述第二电压端提供有效电压信号，向所述时钟信号输入端提供无效电压信号；
    在触控阶段：向所述第一信号输入端提供无效电压信号，向所述第二信号输入端提供无效电压信号，向所述第一电压端提供有效电压信号，向所述第二电压端提供有效电压信号，向所述时钟信号输入端提供无效电压信号；
    在输出阶段：向所述第一信号输入端提供无效电压信号，向所述第二信号输入端提供无效电压信号，向所述第一电压端提供无效电压信号，向所述第二电压端提供有效电压信号，向所述时钟信号输入端提供有效电压信号；
    在输出拉低阶段：向所述第一信号输入端提供有效电压信号，向所述第二信号输入端提供无效电压信号，向所述第一电压端提供无效电压信号，向所述第二电压端提供有效电压信号，向所述时钟信号输入端提供无效电压信号。
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