WO2019148970A1 - 移位寄存器单元、驱动移位寄存器单元的方法、栅极驱动电路和触控显示装置 - Google Patents

移位寄存器单元、驱动移位寄存器单元的方法、栅极驱动电路和触控显示装置 Download PDF

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Publication number
WO2019148970A1
WO2019148970A1 PCT/CN2018/120249 CN2018120249W WO2019148970A1 WO 2019148970 A1 WO2019148970 A1 WO 2019148970A1 CN 2018120249 W CN2018120249 W CN 2018120249W WO 2019148970 A1 WO2019148970 A1 WO 2019148970A1
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Prior art keywords
transistor
node
register unit
shift register
source
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PCT/CN2018/120249
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English (en)
French (fr)
Inventor
王珍
孙建
黄飞
乔赟
詹小舟
张寒
秦文文
丛乐乐
王争奎
张建军
刘鹏
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/478,088 priority Critical patent/US10943554B2/en
Publication of WO2019148970A1 publication Critical patent/WO2019148970A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2354/00—Aspects of interface with display user
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit and a driving method thereof, a GOA circuit, and a touch display device.
  • the GOA Gate Driver on Array
  • touch display panels In a common touch display panel, there may be a problem that the output voltage of the output transistor of the shift register is insufficient. This may cause a display exception to occur.
  • a shift register unit includes a first input circuit configured to conduct a first control voltage terminal with a first node in response to an active potential of the first signal input, and a second input circuit configured to be responsive to the second signal An effective potential of the input terminal, the second control voltage terminal is electrically connected to the first node; and an output circuit configured to transmit the first effective clock signal to the signal output end in response to the effective potential of the second node; the first control a circuit configured to conduct the first voltage terminal to the third node in response to the effective potential of the first node, and further configured to be responsive to the second invalid clock signal and the inactive potential of the first node, The third node is maintained at a first potential; a second control circuit configured to conduct the first node and the first voltage terminal in response to an effective potential of the third node, and to The signal output is electrically coupled to the first voltage terminal; and the anti-leakage circuit is configured to conduct the first node and the second node in response to an effective
  • the first control circuit is configured to pass the second valid clock signal to the third node and to charge from the second valid clock signal in response to a second valid clock signal And storing, in response to the second invalid clock signal and the invalid potential of the first node, outputting the stored charge to the third node, leaving the third node at the first Potential.
  • the first potential is different from the potential of the first voltage terminal.
  • the anti-leakage circuit includes a first transistor, a gate of the first transistor is coupled to the second voltage terminal, and one of source and drain of the first transistor is coupled to the first node And the other of the source and drain of the first transistor is connected to the second node.
  • the first input circuit includes a second transistor, a gate of the second transistor is coupled to the first signal input terminal, and one of source and drain electrodes of the second transistor is coupled to the first One of the control voltage terminals, and the other of the source and drain electrodes of the second transistor is connected to the first node.
  • the second input circuit includes a third transistor, a gate of the third transistor is coupled to the second signal input terminal, and one of a source and a drain of the third transistor is coupled to the first One node, and the other of the source and drain of the third transistor is connected to the second control voltage terminal.
  • the output circuit includes a fourth transistor and a first capacitor.
  • a gate of the fourth transistor is coupled to the second node, and one of source and drain of the fourth transistor is configured to receive the first valid clock signal, and in a source drain of the fourth transistor The other is connected to the signal output.
  • One end of the first capacitor is connected to the second node, and the other end of the first capacitor is connected to the signal output end.
  • the first control circuit includes a fifth transistor, a sixth transistor, and a second capacitor.
  • One of the source and the drain of the fifth transistor and the gate are configured to receive the second valid clock signal or the second invalid clock signal, and another one of the source and the drain of the fifth transistor Said third node.
  • a gate of the sixth transistor is connected to the first node, one of source and drain of the sixth transistor is connected to the third node, and another one of the source and the drain of the sixth transistor is connected The first voltage terminal is described.
  • One end of the second capacitor is connected to the third node, and the other end of the second capacitor is connected to the first voltage end.
  • the first control circuit further includes a seventh transistor.
  • a gate of the seventh transistor is connected to the signal output terminal, one of a source and a drain of the seventh transistor is connected to the third node, and another one of the source and the drain of the seventh transistor is connected The first voltage terminal is described.
  • the second control circuit includes an eighth transistor and a ninth transistor.
  • a gate of the eighth transistor is connected to the third node, one of source and drain of the eighth transistor is connected to the first node, and another one of the source and the drain of the eighth transistor is connected The first voltage terminal is described.
  • a gate of the ninth transistor is connected to the third node, one of source and drain of the ninth transistor is connected to the signal output terminal, and another one of the source and the drain of the ninth transistor is connected The first voltage terminal is described.
  • the first input circuit, the second input circuit, the output circuit, the first control circuit, the second control circuit, and the anti-leakage circuit each comprise a transistor Gate transistor.
  • the transistors are all N-type transistors or both are P-type transistors.
  • a method of driving a shift register unit as described in an embodiment of the present disclosure includes, during a display phase, controlling a voltage of the second voltage terminal of the shift register unit to be a first voltage, such that the anti-leakage circuit of the shift register unit turns the first node The second node is turned on; and, in the touch phase, controlling a voltage of the second voltage terminal of the shift register unit to be a second voltage, such that the anti-leakage circuit of the shift register unit The first node is disconnected from the second node.
  • the method further includes: controlling, at the touch phase, a voltage of a first control voltage terminal and a second control voltage terminal of the shift register unit to be at a high potential to cause the shifting The potential of the first node of the register unit is maintained during the touch phase.
  • a gate driving circuit includes N cascaded shift register units as described in embodiments of the present disclosure, N being an integer greater than or equal to two.
  • N shift register units are provided in the N shift register units:
  • a first signal input end of the m-th stage shift register unit is coupled to a signal output end of the m-1th stage shift register unit, wherein m is an integer and 2 ⁇ m ⁇ N, and
  • the second signal input of the nth stage shift register unit is coupled to the signal output of the n+1th stage shift register unit, where n is an integer and 1 ⁇ n ⁇ N.
  • the first signal input of the first stage shift register unit is configured to receive a positive scan input signal
  • the second signal input of the Nth stage shift register unit is configured to receive the reverse scan input signal
  • a touch display device includes a gate driving circuit according to an embodiment of the present disclosure.
  • Figure 1 schematically shows the circuit structure of the associated 8T2C shift register unit
  • FIG. 2 schematically shows the structure of a gate driving circuit formed using the shift register unit of FIG. 1;
  • FIG. 3 is a view schematically showing a timing control diagram of the gate driving circuit of FIG. 2 in a forward scan
  • FIG. 4 schematically shows characteristic curves of transistors having normal characteristics (OK) and abnormal characteristics (NG);
  • FIG. 5 schematically shows a structural block diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 6 schematically shows a structural block diagram of a shift register unit according to another embodiment of the present disclosure
  • FIG. 7 schematically illustrates a circuit structure of a shift register unit according to an embodiment of the present disclosure
  • FIG. 8 schematically illustrates a circuit configuration of a shift register unit according to another embodiment of the present disclosure
  • FIG. 9 schematically illustrates a timing control diagram of a gate driving circuit in a touch phase according to an embodiment of the present disclosure
  • FIG. 10 schematically shows the structure of a gate driving circuit formed using a shift register unit of an embodiment of the present disclosure.
  • GOA Gate Driver on Array
  • the gate driving integrated circuit portion can be omitted to reduce the product cost from both the material cost and the manufacturing process.
  • a gate drive circuit integrated on an array substrate using GOA technology is also referred to as a GOA circuit or a shift register circuit.
  • Each shift register in the gate drive circuit is also referred to as a shift register unit.
  • the shift register circuit includes a number of shift register units. Each shift register unit corresponds to a gate line. Specifically, the output end of each shift register unit is connected to a gate line, and the output end of one shift register unit is connected to the input end of the next shift register unit.
  • Fig. 1 schematically shows the circuit structure of an associated 8T2C shift register unit.
  • the 8T2C shift register unit means that the shift register unit includes eight transistors and two capacitors.
  • the shift register unit has two input signal terminals STV and RESET and two control voltage terminals CN, CNB.
  • the shift register unit is configured to receive the first valid clock signal or the first invalid clock signal and to receive the second valid clock signal or the second invalid clock signal.
  • the shift register unit may be understood to include a first clock signal terminal CK and a second clock signal terminal CKB, wherein the first clock signal terminal CK is configured to receive the first valid clock signal or An invalid clock signal, and the second clock signal terminal CKB is configured to receive the second valid clock signal or the second invalid clock signal.
  • the first clock signal terminal CK is at a high potential.
  • the shift register unit receives the first invalid clock signal the first clock signal terminal CK is at a low potential.
  • the shift register unit receives the second valid clock signal
  • the second clock signal terminal CKB is at a high potential.
  • the second clock signal terminal CKB When the shift register unit receives the second invalid clock signal, the second clock signal terminal CKB is at a low potential. In the non-touch phase, when the first clock signal terminal CK is at a low potential, the second clock signal terminal CKB is at a high potential. When the first clock signal terminal CK is at a high potential, the second clock signal terminal CKB is at a low potential. Therefore, in this case, the signal received by the first clock signal terminal CK and the signal received by the second clock signal terminal CKB are complementary signals. VGL is a DC low level signal.
  • the control voltage terminal CN and the control voltage terminal CNB are a pair of control voltage terminals for implementing forward and reverse scanning.
  • FIG. 2 schematically shows the structure of a gate driving circuit formed using the shift register unit of FIG. 1.
  • the gate drive circuit can implement positive and negative sweeps. Specifically, if CN is high level and CNB is low level, the gate driving circuit realizes forward scanning, and at this time, STV is a signal input end of forward scanning. If CN is low and CNB is high, the gate drive circuit performs a reverse scan, at which point RESET is the signal input of the reverse scan. As shown in FIG. 2, the STV of the one-stage (for example, the N-th stage) shift register unit is connected to the output terminal OUT of the upper stage (for example, the N-1th stage) shift register unit, and the stage shift register unit The RESET is connected to the output of the next stage (eg, the N+1th stage) shift register unit.
  • the STV of the one-stage (for example, the N-th stage) shift register unit is connected to the output terminal OUT of the upper stage (for example, the N-1th stage) shift register unit, and the stage shift register unit
  • the RESET is connected to the output of the next stage (eg, the N+1th stage
  • FIG. 3 schematically shows a timing control diagram of the gate driving circuit of FIG. 2 in forward scanning.
  • Fig. 4 schematically shows characteristic curves of transistors having normal characteristics (OK) and abnormal characteristics (NG).
  • OUT_N signal
  • the display panel enters the touch phase
  • the touch phase ends, the display panel enters the display phase again, and the N+1th shift register unit continues to output.
  • OUT_N+1 signal As shown in FIG. 3, in the touch phase, the second node PU_N+1 of the N+1th stage shift register unit is at a high level, CN is at a high level, and CNB is at a low level. Therefore, the second node PU will leak through the transistor T2.
  • the gate-source voltage of the transistor T2 is 0V
  • the source-drain voltage is a high-low voltage difference.
  • the magnitude of the leakage current I ds is on the order of 1 ⁇ E ⁇ 10 (also can be recorded as 1E-10). ).
  • the second node PU_N+1 of the N+1th shift register unit can still maintain a high level, so that after the touch phase is over, the pixel is not charged insufficiently.
  • the amplitude of the second node PU_N+1 of the (N+1)th shift register unit is lowered (as shown at 03 of FIG. 3)
  • the transistor T3 cannot be completely turned on, which causes the output voltage of the OUT_N+1 terminal to be insufficient (as shown at 02 of FIG. 3), which may cause the pixel to be insufficiently charged and display abnormality.
  • the first-order shift register unit that needs to be activated after the touch stage is completed by the touch display panel is terminated by the second node PU during the touch phase. After that, there is a problem that the output voltage is insufficient due to the shift register unit of the stage, resulting in insufficient charging of the pixel and display abnormality.
  • FIG. 5 schematically shows a structural block diagram of a shift register unit according to an embodiment of the present disclosure.
  • the shift register unit includes a first signal input terminal INPUT1, a first control voltage terminal CN, a second signal input terminal INPUT2, a second control voltage terminal CNB, a signal output terminal OUT, a first voltage terminal VGL, and a second voltage terminal V2.
  • each of the above ports does not imply that the shift register unit in accordance with the present disclosure necessarily includes a physical port.
  • the shift register unit further includes a first input circuit 10, a second input circuit 20, an output circuit 30, a first control circuit 40, a second control circuit 50, and a leakage resistant circuit 60.
  • the first input circuit 10 is connected to the first signal input terminal INPUT1, the first node PUCN and the first control voltage terminal CN.
  • the first input circuit 10 is configured to turn on the first control voltage terminal CN and the first node PUCN in response to the effective potential of the first signal input terminal INPUT1, that is, to make the potential of the first node PUCN and the first control voltage terminal CN
  • the potential is the same.
  • effective potential refers to a potential applied to the gate of a transistor that turns the transistor on, even if the source and drain are conducting.
  • the second input circuit 20 is connected to the second signal input terminal INPUT2, the first node PUCN and the second control voltage terminal CNB, and the second input circuit 20 is configured to respond to the effective potential of the second signal input terminal INPUT2, and the second control voltage terminal
  • the CNB is turned on with the first node PUCN, that is, the potential of the first node PUCN is made the same as the potential of the second control voltage terminal CNB.
  • the output circuit 30 is connected to the second node PU and the signal output terminal OUT.
  • the output circuit 30 is configured to conduct the first clock signal terminal CK and the signal output terminal OUT in response to the effective potential of the second node PU, that is, to transmit the first valid clock signal from the first clock signal terminal CK to the signal. Output OUT.
  • the first control circuit 40 is connected to the first node PUCN, the first voltage terminal VGL, and the third node PD.
  • the first control circuit 40 is configured to conduct the first voltage terminal VGL and the third node PD in response to the effective potential of the first node PUCN such that the potential of the first voltage terminal VGL is the same as the potential of the third node PD.
  • the first control circuit 40 is further configured to maintain the third node PD at a first potential in response to the second invalid clock signal and the inactive potential of the first node, the first potential being different from the potential of the first voltage terminal VGL.
  • the first control circuit 40 is configured to store the charge from the second valid clock signal in response to the second valid clock signal, and deliver the second valid clock signal to the third node PD, so that the third node PD
  • the potential is equal to the potential of the second active clock signal (ie, the potential of the second clock signal terminal CKB), and is also configured to release the stored charge from the second valid clock signal to the third node PD.
  • invalid potential refers to a potential applied to the gate of a transistor that turns the transistor off, even if the source and drain are turned off.
  • FIG. 6 schematically shows a structural block diagram of a shift register unit according to another embodiment of the present disclosure.
  • the first control circuit 40 is further connected to the signal output terminal OUT, and is further configured to turn on the first voltage terminal VGL and the third node PD in response to the effective potential of the signal output terminal OUT.
  • the potential of the third node PD is made the same as the potential of the first voltage terminal VGL.
  • the second control circuit 50 is connected to the third node PD, the first node PUCN, the first voltage terminal VGL, and the signal output terminal OUT.
  • the second control circuit 50 is configured to make the first node PUCN and the signal output terminal OUT both conductive with the first voltage terminal VGL in response to the effective potential of the third node PD, that is, the first node PUCN and the signal output terminal OUT The potential is pulled down to the first voltage terminal VGL.
  • the anti-leakage circuit 60 connects the first node PUCN, the second voltage terminal V2, and the second node PU.
  • the anti-leakage circuit 60 is configured to conduct the first node PUCN and the second node PU in response to an effective potential of the second voltage terminal V2.
  • the shift register unit provided by the embodiment of the present disclosure can control the anti-leakage circuit 60 of the shift register unit in the display phase of the display panel such that the first node PUCN and the second node PU are turned on, thereby causing the potential of the first node PUCN and the first node The potentials of the two-node PUs are equal, so that the output voltage of the stage shift register unit is normal for normal display. Moreover, in the touch phase, the anti-leakage circuit 60 of the shift register unit is in an off state, so that the first node PUCN is disconnected from the second node PU, so that the leakage of the first node PUCN does not cause during the touch phase.
  • Leakage occurs in the second node PU to avoid leakage of the second node PU in the touch phase, thereby preventing the output voltage of the first stage shift register unit that needs to be started after the end of the touch phase is insufficient, resulting in insufficient pixel charging. A problem such as an exception is displayed.
  • FIG. 7 and 8 schematically illustrate circuit configurations of a shift register unit according to two embodiments of the present disclosure, respectively.
  • the specific structure of the circuit of the shift register unit provided by the embodiment of the present disclosure will be exemplified in conjunction with FIG. 7 and FIG. 8 .
  • the anti-leakage circuit 60 includes a first transistor T1, the gate of the first transistor T1 is connected to the second voltage terminal V2, one of the source and drain electrodes is connected to the first node PUCN, and the other of the source and drain electrodes is connected to the second. Node PU.
  • the first input circuit 10 includes a second transistor T2.
  • the gate of the second transistor T2 is connected to the first signal input terminal INPUT1, one of the source and drain electrodes is connected to the first control voltage terminal CN, and the other of the source and drain electrodes is connected to the first node PUCN.
  • the second input circuit 20 includes a third transistor T3.
  • the gate of the third transistor T3 is connected to the second signal input terminal INPUT2, one of the source and drain electrodes is connected to the second control voltage terminal CNB, and the other of the source and drain electrodes is connected to the first node PUCN.
  • the output circuit 30 includes a fourth transistor T4 and a first capacitor C1.
  • the gate of the fourth transistor T4 is coupled to the second node PU, one of the source and the drain is configured to receive the first valid clock signal or the first invalid clock signal, and the other of the source and drain is coupled to the signal output terminal OUT.
  • One end of the first capacitor C1 is connected to the second node PU, and the other end is connected to the signal output terminal OUT.
  • the first control circuit 40 includes a fifth transistor T5, a sixth transistor T6, and a second capacitor C1.
  • One of the source and drain of the fifth transistor T5 and the gate are configured to receive the second valid clock signal or the second invalid clock signal, and the other of the source and drain electrodes is connected to the third node PD.
  • the gate of the sixth transistor T6 is connected to the first node PUCN, one of the source and drain electrodes is connected to the third node PD, and the other of the source and drain electrodes is connected to the first voltage terminal VGL.
  • One end of the second capacitor C1 is connected to the third node PD, and the other end is connected to the first voltage terminal VGL.
  • the second control circuit 50 includes an eighth transistor T8 and a ninth transistor T9.
  • the gate of the eighth transistor T8 is connected to the third node PD, one of the source and drain electrodes is connected to the first node PUCN, and the other of the source and drain electrodes is connected to the first voltage terminal VGL.
  • the gate of the ninth transistor T9 is connected to the third node PD, one of the source and the drain is connected to the signal output terminal OUT, and the other of the source and the drain is connected to the first voltage terminal VGL.
  • the first control circuit 40 further includes a seventh transistor T7.
  • the gate of the seventh transistor T7 is connected to the signal output terminal OUT, one of the source and the drain is connected to the third node PD, and the other of the source and the drain is connected to the first voltage terminal VGL.
  • the present disclosure does not limit the mentioned transistor as a single transistor, which may be a series connection of a plurality of transistors.
  • the term "nth transistor” includes a transistor as an example in FIGS. 7 and 8.
  • the transistors may be P-type transistors or both N-type transistors.
  • the term “one of the source and drain” is specifically a source
  • the term “the other of the source and drain” is specifically a drain.
  • the expression "one of the source and drain of the first transistor is connected to the first node, and the other of the source and drain of the first transistor is connected to the second node" can be understood as A source of the first transistor is coupled to the first node, and a drain of the first transistor is coupled to the second node.
  • the term "one of the source and drain” is a drain
  • the term "the other of the source and drain” is a source.
  • each transistor is an N-type transistor will be described.
  • the above transistor may be a double gate transistor or a single gate transistor.
  • the leakage current of a single-gate transistor is larger than that of a double-gate transistor, making the stability of the shift register unit poor. Since the shift register unit of the embodiment of the present disclosure has strong anti-leakage capability to the second node PU during the touch phase, when each transistor in the embodiment is a single gate transistor, the single gate transistor can be avoided. The problem of poor stability of the shift register unit caused by a large leakage current.
  • the wiring space of the shift register unit can be reduced, thereby achieving a narrower border of the touch display panel.
  • the wiring space can also be reduced by proportionally reducing the width and length of the transistor, thereby achieving a narrow border of the touch display panel. This embodiment of the present disclosure does not limit this.
  • the gate driving circuit formed by the shift register unit provided by the embodiment of the present disclosure can implement bidirectional scanning of the gate line. Specifically, when the first control voltage terminal CN outputs a constant high level, and the second control voltage terminal CNB outputs a constant low level, the gate driving circuit can scan forward. When the first control voltage terminal CN outputs a constant low level, and the second control voltage terminal CNB outputs a constant high level, the gate driving circuit can scan backward.
  • Each transistor in the shift register unit is an N-type transistor.
  • the voltage of the second voltage terminal V2 of the shift register unit is controlled to be a valid first voltage, so that the anti-leakage circuit 60 of the shift register unit is in the first node PUCN and the first node.
  • the display phase includes an input phase, an output phase, and a reset phase.
  • the first voltage is a high level signal, and under the control of the second voltage terminal V2, the first transistor T1 is turned on, and the potential of the first node PUCN is the same as the potential of the second node PU.
  • the charge of the first node PUCN is transferred to the second node PU through the first transistor T1, and the charge is stored by the first capacitor C1.
  • the second valid clock signal ie, the effective potential of the second clock signal terminal CKB
  • the fifth transistor T5 is turned on
  • the second clock signal terminal CKB is turned on with the third node PD
  • the second valid clock signal is passed through the fifth
  • the transistor T5 is delivered to the third node PD.
  • the sixth transistor T6 is turned on, and the low potential of the first voltage terminal VGL is transferred to the third node PD through the sixth transistor T6.
  • the third node PD can be made low.
  • the eighth transistor T8 and the ninth transistor T9 are turned off.
  • the third transistor T3 is turned off in response to the inactive potential of the second signal input terminal INPUT2.
  • the fourth transistor T4 In response to the effective potential of the second node PU, the fourth transistor T4 is turned on, and the first invalid clock signal is transmitted to the signal output terminal OUT through the fourth transistor T4. Therefore, at the input stage, the signal output terminal OUT does not output a gate scan signal.
  • the first valid clock signal is transmitted as a gate scan signal through the fourth transistor T4 to the signal output terminal OUT for scanning the gate line connected to the signal output terminal OUT. Furthermore, under the bootstrap action of the first capacitor C1, the potential of the second node PU and the first node PUCN is further increased.
  • the fifth transistor T5 is turned off.
  • the sixth transistor T6 is turned on, the third node PD is turned on with the first voltage terminal VGL, and the high potential of the third node PD is pulled down to the low potential of the first voltage terminal VGL.
  • the seventh transistor T7 when the output signal of the signal output terminal OUT is at a high level, the seventh transistor T7 is turned on. This further ensures that the third node PD is at a low level, thereby enhancing the output drive capability of the shift register unit.
  • the second input circuit 20 pulls down the potential of the second node PU to the second control voltage terminal CNB.
  • the first control circuit 40 stores the charge of the second valid clock signal. Under the control of the second valid clock signal, the charge from the second valid clock signal is output to the third node PD, or the stored charge is discharged to the third node PD, so that the third node remains at a different voltage from the first voltage terminal VGL The first potential of the potential. Under the control of the first potential of the third node PD, the second control circuit 50 pulls down the potential of the first node PUCN and the signal output terminal OUT to the first voltage terminal VGL.
  • the second transistor T2 in response to the inactive potential of the first signal input terminal INPUT1, the second transistor T2 is turned off.
  • the third transistor T3 is turned on, so that the second control voltage terminal CNB is turned on with the first node PUCN, so that the potential of the first node is equal to the low voltage of the second control voltage terminal CNB. level.
  • the first transistor T1 is turned on, and the low level of the first node PUCN is transferred to the second node PU.
  • the sixth transistor T6 is turned off in response to the inactive potential of the first node PUCN.
  • the fourth transistor T4 is turned off.
  • the fifth transistor T5 is turned on, the second valid clock signal is passed through the fifth transistor T5 to the third node PD, and the second capacitor C2 stores the charge from the second clock valid signal.
  • the eighth transistor T8 and the ninth transistor T9 are turned on. Through the eighth transistor T8, the potentials of the first node PUCN and the second node PU are both pulled down to the low level of the first voltage terminal VGL. Through the ninth transistor T9, the potential of the signal output terminal OUT is pulled down to the low level of the first voltage terminal VGL.
  • the third transistor T3 is turned off.
  • the second clock signal terminal CKB is turned on with the third node PD
  • the second valid clock signal is transmitted to the third node PD through the fifth transistor T5
  • the second capacitor C2 is from the first The charge of the two active clock signals is stored.
  • the second capacitor C2 may output the stored charge to the third node PD such that the third node PD remains at a high level.
  • the eighth transistor T8 is turned on, and the potential of the first node PUCN can be pulled down to the low level of the first voltage terminal VGL through the eighth transistor T8.
  • the first control circuit 40 and the second control circuit 50 repeat the process.
  • the above is the working process of the shift register unit during the display phase.
  • the working process of the shift register unit in the touch phase will be described.
  • the signals of the first clock signal terminal CK and the second clock signal terminal CKB are both invalid signals (ie, the shift register unit receives the first invalid clock signal and the second invalid clock signal), and thus at this stage The medium shift register unit does not output a gate scan signal.
  • FIG. 9 schematically illustrates a timing control diagram of a gate driving circuit in a touch phase according to an embodiment of the present disclosure.
  • FIG. 10 schematically shows the structure of a gate driving circuit formed using a shift register unit of an embodiment of the present disclosure.
  • the voltage of the second voltage terminal V2 of the shift register unit is controlled to be a second voltage different from the first voltage.
  • the first voltage is the effective voltage that turns transistor T1 on. Therefore, the second voltage is an inactive voltage, so that the anti-leakage circuit 60 of the shift register unit is in an off state, the first node PUCN is disconnected from the second node PU, and the potential of the first node PUCN cannot be transmitted to the second node PU.
  • the third transistor T3 is in an on state, the first node PUCN_N+1 is turned on with the low voltage VGL first voltage terminal, and the first node PUCN_N+1 is leaked through the third transistor T3. Since the second voltage terminal V2 is low, the first node PUCN_N+1 and the second node PU_N+1 are not turned on, and the potential of the first node PUCN_N+1 cannot be transmitted to the second node PU_N+1, so the first node PUCN_N Leakage of +1 does not cause leakage of the second node PU_N+1 during the touch phase, so that the second node PU_N+1 can remain high (as shown at 03 of FIG. 9).
  • the RS (N+1)-stage shift register unit can normally output the OUT_N+1 signal (as shown at 02 of FIG. 9), thereby avoiding the second node PU_N in the touch phase. Leakage occurs in +1, which prevents the output voltage of the RS (N+1)-stage shift register unit from being insufficient after the end of the touch phase, resulting in insufficient pixel charging and display abnormality.
  • the principle that the first node PUCN_N+1 leaks through the third transistor T3 during the touch phase is the same as the principle that the second node PU in the shift register unit shown in FIG. 1 leaks through the transistor T2 during the touch phase.
  • the first transistor T1 is turned on under the control of the second voltage terminal V2.
  • the potential of the second node PU_N+1 may be instantaneously lowered.
  • the fourth transistor T4 may be insufficiently opened, resulting in insufficient output voltage of the signal output terminal OUT, thereby causing insufficient pixel charging and display abnormality.
  • the gate-source voltage of the third transistor T3 is at a low level, and the source-drain voltage is about 0V.
  • the magnitude of the drain current Ids is on the order of 1 ⁇ E -11 .
  • the first node PUCN_N+1 does not generate leakage, so after the touch phase, the first node PUCN_N+1 can still Keep it high so that there is no pixel charging.
  • the potential reduction of the first node PUCN_N+1 during the touch phase can be reduced, so that after the end of the touch phase, when the first node PUCN_N+1 and the second node PU_N+1 are turned on, the second node
  • the potential of PU_N+1 is not significantly lowered, so that the fourth transistor T4 can be fully turned on, so that the output voltage of the signal output terminal OUT is sufficient, thereby further reducing the probability of occurrence of insufficient pixel charging.
  • the shift register unit shown in FIG. 7 does not include the seventh transistor T8 as compared with the shift register unit shown in FIG. This is advantageous in reducing the wiring space of the shift register unit and achieving a narrower border.
  • a method of driving a shift register unit comprising the steps described below.
  • the voltage of the second voltage terminal V2 of the shift register unit is controlled to be a first voltage such that the anti-leakage circuit 60 of the shift register unit is in conducting the first node PUCN and the second node PU.
  • the voltage of the second voltage terminal V2 of the shift register unit is controlled to be a second voltage, so that the anti-leakage circuit 60 of the shift register unit disconnects the first node PUCN from the second node PU.
  • the first transistor T1 included in the anti-leakage circuit 60 is N-type
  • the first voltage is at a high level, so that the first transistor T1 is turned on in the display phase.
  • the second voltage is at a low level to turn off the first transistor T1 in the touch phase.
  • the first transistor T1 is of the P type
  • the first voltage is at a low level to turn on the first transistor T1 in the display phase.
  • the second voltage is at a high level to turn off the first transistor T1 in the touch phase.
  • the display phase includes an input phase, an output phase, a reset phase, and other non-output phases. The working process of the shift register unit in each stage of the display phase has been described in detail above, and will not be described here.
  • the leakage of the first node PUCN does not cause the second node PU to leak, so that the second node PU can maintain a high level, thereby avoiding contact In the control phase, the second node PU leaks, which prevents the output voltage of the RS (N+1)-stage shift register unit from being insufficient after the end of the touch phase, resulting in insufficient pixel charging and display abnormality.
  • the method of driving the shift register unit further includes: controlling, during the touch phase, a voltage of the first control voltage terminal CN and the second control voltage terminal CNB of the shift register unit to be a high level signal to reduce The leakage current of the first node PUCN of the shift register unit during the touch phase.
  • the leakage current of the first node PUCN during the touch phase can be reduced, so that after the end of the touch phase, when the first node PUCN and the second node PU are turned on, the second node PU maintains a high potential.
  • the output voltage of the signal output terminal OUT is sufficient, thereby further reducing the probability of occurrence of insufficient pixel charging.
  • a gate driving circuit includes a positive scan signal input terminal STV1, a reverse scan signal input terminal STV2, and N cascaded shift register units according to an embodiment of the present disclosure, and N is an integer greater than or equal to 2.
  • the first signal input terminal INPUT1 of the first stage shift register unit is connected to the positive scan signal input terminal STV1 of the gate drive circuit, and is configured to be in an initial stage.
  • a positive scan input signal (ie, a start signal) is received.
  • the first signal input terminal of the m-th stage shift register unit is coupled to the signal output terminal of the m-1th stage shift register unit, where m is an integer and 2 ⁇ m ⁇ N.
  • the second signal input of the nth stage shift register unit is coupled to the signal output of the n+1th stage shift register unit, where n is an integer and 1 ⁇ n ⁇ N.
  • the second input terminal INPUT2 of the last stage shift register unit ie, the shift register unit of the Nth stage
  • Signal ie, reset signal
  • the start signal of the positive scan signal input terminal STV1 may be reset as the reset signal to the last stage shift register unit RS(x), or the reset signal may be input to the inverse scan signal input terminal STV2.
  • the clock signal clock1 of the first clock signal terminal CK and the clock signal clock2 of the second clock signal terminal CKB are complementary (ie, when the shift register unit subsequently receives the first valid clock signal, it simultaneously receives the second invalid clock signal; The bit register unit then receives the first invalid clock signal while it receives the second valid clock signal) and exchanges the order once every one stage of the shift register unit.
  • the gate driving circuit provided by the embodiment of the present disclosure enters the touch phase after outputting a signal at the signal output end of the nth stage shift register unit in an image frame.
  • the anti-leakage circuit 60 that controls the n+1th stage shift register unit is in a state in which the first node PUCN and the second node PU are disabled, so that the n+1th stage shift register unit can be reduced.
  • the leakage of the second node PU can further reduce the output voltage shortage of the n+1th stage shift register unit, resulting in insufficient pixel charging and a probability of display abnormality.
  • a touch display device including a gate driving circuit according to an embodiment of the present disclosure.
  • the touch display device has the same structure and advantageous effects as the gate driving circuit provided in the foregoing embodiment, and details are not described herein again.
  • the touch display device may specifically include at least a liquid crystal display device and an organic light emitting diode display device.
  • the touch display device can be any product or component having a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.

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Abstract

一种移位寄存器单元（RS1…RS(x)）、驱动移位寄存器单元（RS1…RS(x)）的方法、栅极驱动电路和触控显示装置，移位寄存器单元（RS1…RS(x)）包括第一信号输入端（INPUT1）、第一控制电压端（CN）、第二信号输入端（INPUT2）、第二控制电压端（CNB）、信号输出端（OUT）、第一电压端（VGL）和第二电压端（V2），移位寄存器单元（RS1…RS(x)）还包括第一输入电路（10）、第二输入电路（20）、输出电路（30）、抗漏电电路（60）、第一控制电路（40）和第二控制电路（50），抗漏电电路（60）配置成响应于第二电压端（V2）的有效电位，将第一节点（PUCN）与第二节点（PU）导通。

Description

移位寄存器单元、驱动移位寄存器单元的方法、栅极驱动电路和触控显示装置
相关申请的交叉引用
本申请主张于2018年1月31日提交的中国专利申请No.201810100925.1的优先权，其全部内容通过引用结合于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器单元及其驱动方法、GOA电路、触控显示装置。
背景技术
阵列基板行驱动(GOA，即Gate Driver on Array)是可以应用到触控显示面板的重要技术。在常见的触控显示面板中，可能出现移位寄存器的输出晶体管的输出电压不足的问题。这可能导致出现显示异常。
发明内容
根据本公开的一方面，提供一种移位寄存器单元。该移位寄存器单元包括第一输入电路，其配置成响应于第一信号输入端的有效电位，将第一控制电压端与第一节点导通；第二输入电路，其配置成响应于第二信号输入端的有效电位，将第二控制电压端与所述第一节点导通；输出电路，其配置成响应于第二节点的有效电位，将第一有效时钟信号传递至信号输出端；第一控制电路，其配置成响应于所述第一节点的有效电位，将第一电压端与第三节点导通，并且还配置成响应于第二无效时钟信号和所述第一节点的无效电位，将所述第三节点保持在第一电位；第二控制电路，其配置成响应于所述第三节点的有效电位，将所述第一节点与所述第一电压端导通，并将所述信号输出端与所述第一电压端导通；以及抗漏电电路，其配置成响应于第二电压端的有效电位，将所述第一节点与所述第二节点导通。
在一些实施例中，所述第一控制电路配置成响应于第二有效时钟信号，将所述第二有效时钟信号传递至所述第三节点，并对来自所述第二有效时钟信号的电荷进行存储；以及，响应于所述第二无效时钟信号和所述第一节点的无效电位，将存储的所述电荷输出至所述第三节点，使所述第三节点保持在所述第一电位。
在一些实施例中，所述第一电位与所述第一电压端的电位不同。
在一些实施例中，所述抗漏电电路包括第一晶体管，所述第一晶体管的栅极连接所述第二电压端，所述第一晶体管的源漏极中的一个连接所述第一节点，并且所述第一晶体管的源漏极中的另一个连接所述第二节点。
在一些实施例中，所述第一输入电路包括第二晶体管，所述第二晶体管的栅极连接所述第一信号输入端，所述第二晶体管的源漏极中的一个连接所述第一控制电压端，并且所述第二晶体管的源漏极中的另一个连接所述第一节点。
在一些实施例中，所述第二输入电路包括第三晶体管，所述第三晶体管的栅极连接所述第二信号输入端，所述第三晶体管的源漏极中的一个连接所述第一节点，并且所述第三晶体管的源漏极中的另一个连接所述第二控制电压端。
在一些实施例中，所述输出电路包括第四晶体管和第一电容。所述第四晶体管的栅极连接所述第二节点，所述第四晶体管的源漏极中的一个配置成接收所述第一有效时钟信号，并且所述第四晶体管的源漏极中的另一个连接所述信号输出端。所述第一电容的一端连接所述第二节点，并且所述第一电容的另一端连接所述信号输出端。
在一些实施例中，所述第一控制电路包括第五晶体管、第六晶体管和第二电容。所述第五晶体管的源漏极中的一个和栅极配置成接收所述第二有效时钟信号或所述第二无效时钟信号，并且所述第五晶体管的源漏极中的另一个连接所述第三节点。所述第六晶体管的栅极连接所述第一节点，所述第六晶体管的源漏极中的一个连接所述第三节点，并且所述第六晶体管的源漏极中的另一个连接所述第一电压端。所述第二电容的一端连接所述第三节点，并且所述第二电容的另一端连接所述第一电压端。
在一些实施例中，所述第一控制电路还包括第七晶体管。所述第七晶体管的栅极连接所述信号输出端，所述第七晶体管的源漏极中的一个连接所述第三节点，并且所述第七晶体管的源漏极中的另一个连接所述第一电压端。
在一些实施例中，所述第二控制电路包括第八晶体管和第九晶体管。所述第八晶体管的栅极连接所述第三节点，所述第八晶体管的源 漏极中的一个连接所述第一节点，并且所述第八晶体管的源漏极中的另一个连接所述第一电压端。所述第九晶体管的栅极连接所述第三节点，所述第九晶体管的源漏极中的一个连接所述信号输出端，并且所述第九晶体管的源漏极中的另一个连接所述第一电压端。
在一些实施例中，所述第一输入电路、所述第二输入电路、所述输出电路、所述第一控制电路、所述第二控制电路和所述抗漏电电路各自包括的晶体管为单栅极晶体管。
在一些实施例中，所述晶体管均为N型晶体管或者均为P型晶体管。
根据本公开的另一方面，提供了一种驱动如本公开实施例所述的移位寄存器单元的方法。所述方法包括：在显示阶段，控制所述移位寄存器单元的所述第二电压端的电压为第一电压，使得所述移位寄存器单元的所述抗漏电电路将所述第一节点与所述第二节点导通；以及，在触控阶段，控制所述移位寄存器单元的所述第二电压端的电压为第二电压，使得所述移位寄存器单元的所述抗漏电电路将所述第一节点与所述第二节点断开。
在一些实施例中，所述方法还包括：在所述触控阶段，控制所述移位寄存器单元的第一控制电压端和第二控制电压端的电压均为高电位，以使所述移位寄存器单元的所述第一节点的电位在所述触控阶段得到保持。
根据本公开的又一方面，提供了一种栅极驱动电路。该栅极驱动电路包括N个级联的如本公开实施例所述的移位寄存器单元，N为大于或等于2的整数。在所述N个移位寄存器单元中：
第m级移位寄存器单元的第一信号输入端与第m-1级移位寄存器单元的信号输出端相连接，其中m为整数且2≤m≤N，并且
第n级移位寄存器单元的第二信号输入端与第n+1级移位寄存器单元的信号输出端相连接，其中n为整数且1≤n＜N。
在一些实施例中，第1级移位寄存器单元的第一信号输入端配置成接收正扫描输入信号，且第N级移位寄存器单元的第二信号输入端配置成接收反扫描输入信号
根据本公开的再一方面，提供了一种触控显示装置。该触控显示装置包括根据本公开实施例所述的栅极驱动电路。
附图说明
本公开的这些和其它方面将从下文描述的实施例而显而易见，并且将参考附图以示例性方式予以进一步阐释，在附图中：
图1示意性地示出了相关的8T2C移位寄存器单元的电路结构；
图2示意性地示出了利用图1的移位寄存器单元形成的栅极驱动电路的结构；
图3示意性地示出了图2的栅极驱动电路在正向扫描时的时序控制图；
图4示意性地示出了特性正常(OK)和特性不正常(NG)的晶体管的特性曲线；
图5示意性地示出了根据本公开实施例的移位寄存器单元的结构框图；
图6示意性地示出了根据本公开另一实施例的移位寄存器单元的结构框图；
图7示意性地示出了根据本公开实施例的移位寄存器单元的电路结构；
图8示意性地示出了根据本公开另一实施例的移位寄存器单元的电路结构；
图9示意性地示出了根据本公开实施例的栅极驱动电路在触控阶段的时序控制图；以及
图10示意性地示出了利用本公开实施例的移位寄存器单元形成的栅极驱动电路的结构。
具体实施方式
下面将参照附图更详细地描述本公开的若干个实施例以便使得本领域技术人员能够实现本公开。然而，本公开可以体现为许多不同的形式并且不应被解释为局限于本文所阐述的实施例。相反，提供这些实施例以使得本公开全面且完整，并将充分地向本领域技术人员传达本公开的范围。所述实施例并不限定本公开。此外，在对附图中所示的特定实施例的详细描述中使用的术语并非旨在限定本公开。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
近年来，触控显示面板的发展呈现出了高集成度，低成本的发展 趋势。一项非常重要的技术就是阵列基板行驱动(GOA，Gate Driver on Array)的技术量产化。通过利用GOA技术将栅极驱动电路集成在显示面板的阵列基板上，可以省掉栅极驱动集成电路部分，以便从材料成本和制作工艺两方面降低产品成本。这种利用GOA技术集成在阵列基板上的栅极驱动电路也称为GOA电路或移位寄存器电路。栅极驱动电路中的每个移位寄存器也称移位寄存器单元。移位寄存器电路包括若干个移位寄存器单元。每一移位寄存器单元对应一条栅线。具体的，每一移位寄存器单元的输出端连接一条栅线，且一个移位寄存器单元的输出端连接下一个移位寄存器单元的输入端。
图1示意性地示出了相关的8T2C移位寄存器单元的电路结构。需要说明的是，8T2C移位寄存器单元是指，该移位寄存器单元中包括八个晶体管和两个电容。该移位寄存器单元具有两个输入信号端STV以及RESET和两个控制电压端CN、CNB。移位寄存器单元配置成接收第一有效时钟信号或第一无效时钟信号，以及接收第二有效时钟信号或第二无效时钟信号。在一些实施例中，可以将根据本公开的移位寄存器单元理解为包含第一时钟信号端CK和第二时钟信号端CKB，其中第一时钟信号端CK配置成接收第一有效时钟信号或第一无效时钟信号，且第二时钟信号端CKB配置成接收第二有效时钟信号或第二无效时钟信号。当移位寄存器单元接收第一有效时钟信号时，第一时钟信号端CK处于高电位。当移位寄存器单元接收第一无效时钟信号时，第一时钟信号端CK处于低电位。当移位寄存器单元接收第二有效时钟信号时，第二时钟信号端CKB处于高电位。当移位寄存器单元接收第二无效时钟信号时，第二时钟信号端CKB处于低电位。在非触控阶段中，当第一时钟信号端CK处于低电位时，第二时钟信号端CKB处于高电位。当第一时钟信号端CK处于高电位时，第二时钟信号端CKB处于低电位。因此，在这种情况下，第一时钟信号端CK接收的信号和第二时钟信号端CKB接收的信号为互补信号。VGL为直流低电平信号。控制电压端CN和控制电压端CNB为实现正反扫的一对控制电压端。图2示意性地示出了利用图1的移位寄存器单元形成的栅极驱动电路的结构。该栅极驱动电路可以实现正反扫。具体的，若CN为高电平且CNB为低电平，则栅极驱动电路实现正向扫描，此时STV为正向扫描的信号输入端。若CN为低电平且CNB为高电平，则栅极驱动电 路实现反向扫描，此时RESET为反向扫描的信号输入端。如图2所示，一级(例如，第N级)移位寄存器单元的STV连接上一级(例如，第N-1级)移位寄存器单元的输出端OUT，且该级移位寄存器单元的RESET连接下一级(例如，第N+1级)移位寄存器单元的输出端。
图3示意性地示出了图2的栅极驱动电路在正向扫描时的时序控制图。图4示意性地示出了特性正常(OK)和特性不正常(NG)的晶体管的特性曲线。参照图2，第N级移位寄存器单元在输出OUT_N信号后，显示面板进入触控阶段，并且在触控阶段结束后，显示面板再次进入显示阶段，第N+1级移位寄存器单元继续输出OUT_N+1信号。如图3所示，在触控阶段，第N+1级移位寄存器单元的第二节点PU_N+1为高电平，CN为高电平，CNB为低电平。因此，第二节点PU会通过晶体管T2发生漏电。
具体的，晶体管T2的栅源电压为0V，源漏电压为高低电平的电压差。根据图4，若移位寄存器单元中的晶体管的特性正常，则当栅源电压V gs＝0V时，漏电流I ds的量级为1×E -10量级(也可记为1E-10)。对于特性正常的晶体管，经过触控阶段后，第N+1级移位寄存器单元的第二节点PU_N+1仍能保持高电平，因此触控阶段结束后，不会导致像素充电不足。若移位寄存器单元中晶体管特性不正常，当栅源电压V gs＝0V时，漏电流I ds的量级为1×E -5量级。在这种情况下，如图3所示，在触控阶段中，第N+1级移位寄存器单元的第二节点PU_N+1的幅值降低(如图3的03处所示)，因此触控阶段结束后，晶体管T3不能完全打开，从而导致OUT_N+1端的输出电压不足(如图3的02处所示)，进而易导致像素充电不足，出现显示异常。
需要说明的是，本领域中，当晶体管的漏电流I ds的量级大于1×E -5量级时，经过触控阶段后，如图3所示，会导致Touch阶段结束后需要启动的那一级移位寄存器单元(即第N+1级移位寄存器单元)的第二节点PU_N+1的幅值降低，导致像素充电不足。
综上所述，对于常见的触控显示面板在触控阶段结束后需要启动的那一级移位寄存器单元，由于它的第二节点PU在触控阶段会发生漏电，因此在触控阶段结束后，该级移位寄存器单元会存在输出电压不足的问题，导致像素充电不足，出现显示异常。
为了解决上述问题，本公开实施例提供一种移位寄存器单元。图5 示意性地示出了根据本公开实施例的移位寄存器单元的结构框图。该移位寄存器单元包括第一信号输入端INPUT1、第一控制电压端CN、第二信号输入端INPUT2、第二控制电压端CNB、信号输出端OUT、第一电压端VGL、第二电压端V2。应理解，上述各端口并非表示根据本公开的移位寄存器单元一定包括实体端口。在一些实施例中，它们可以表示移位寄存器电源中的某电路的某节点，经过该节点可以接收到电信号或将移位寄存器单元的某部分电路连通到某电位。该移位寄存器单元还包括第一输入电路10、第二输入电路20、输出电路30、第一控制电路40、第二控制电路50和抗漏电电路60。
第一输入电路10连接第一信号输入端INPUT1、第一节点PUCN和第一控制电压端CN。第一输入电路10配置成响应于第一信号输入端INPUT1的有效电位，将第一控制电压端CN与第一节点PUCN导通，即，使第一节点PUCN的电位与第一控制电压端CN的电位相同。术语“有效电位”是指施加在晶体管栅极的、且使晶体管导通、即使源极和漏极导通的电位。
第二输入电路20连接第二信号输入端INPUT2、第一节点PUCN和第二控制电压端CNB，第二输入电路20配置成响应于第二信号输入端INPUT2的有效电位，将第二控制电压端CNB与第一节点PUCN导通，即，使第一节点PUCN的电位与第二控制电压端CNB的电位相同。
输出电路30连接第二节点PU以及信号输出端OUT。输出电路30配置成响应于第二节点PU的有效电位，将第一时钟信号端CK与信号输出端OUT导通，即，将来自于第一时钟信号端CK的第一有效时钟信号传递到信号输出端OUT。
第一控制电路40连接第一节点PUCN、第一电压端VGL和第三节点PD。第一控制电路40配置成响应于第一节点PUCN的有效电位，将第一电压端VGL与第三节点PD导通，使得第一电压端VGL的电位与第三节点PD的电位相同。第一控制电路40还配置成响应于第二无效时钟信号和第一节点的无效电位，使得第三节点PD保持第一电位，第一电位与第一电压端VGL的电位不同。具体的，第一控制电路40配置成响应于第二有效时钟信号，对来自于第二有效时钟信号的电荷进行存储，并将第二有效时钟信号传递至第三节点PD，使第三节点PD的电位等于第二有效时钟信号的电位(即第二时钟信号端CKB的电 位)，并且还配置成将存储的来自于第二有效时钟信号的电荷释放至第三节点PD。术语“无效电位”是指施加在晶体管栅极的、且使晶体管截止、即使源极和漏极断开的电位。
图6示意性地示出了根据本公开另一实施例的移位寄存器单元的结构框图。可选的，如图6所示，第一控制电路40还连接信号输出端OUT，并且还配置成响应于信号输出端OUT的有效电位，将第一电压端VGL与第三节点PD导通，使得第三节点PD的电位与第一电压端VGL的电位相同。
第二控制电路50连接第三节点PD、第一节点PUCN、第一电压端VGL和信号输出端OUT。第二控制电路50配置成响应于第三节点PD的有效电位，使第一节点PUCN和信号输出端OUT都与第一电压端VGL导通，即，将第一节点PUCN和信号输出端OUT的电位下拉至第一电压端VGL。
抗漏电电路60连接第一节点PUCN、第二电压端V2和第二节点PU。抗漏电电路60配置成响应于第二电压端V2的有效电位，将第一节点PUCN与第二节点PU导通。
本公开实施例提供的移位寄存器单元在显示面板的显示阶段可以控制移位寄存器单元的抗漏电电路60使得第一节点PUCN与第二节点PU导通，从而使第一节点PUCN的电位与第二节点PU的电位相等，以使得该级移位寄存器单元的输出电压正常，以便进行正常显示。并且，在触控阶段，使移位寄存器单元的抗漏电电路60处于截止状态，使得第一节点PUCN与第二节点PU断开，从而在触控阶段期间，第一节点PUCN的漏电不会导致第二节点PU发生漏电，以避免触控阶段中第二节点PU发生漏电，进而可以阻止触控阶段结束后需要启动的那一级移位寄存器单元出现输出电压不足，而导致像素充电不足，出现显示异常等问题。
图7和图8分别示意性地示出了根据本公开的两个实施例的移位寄存器单元的电路结构。以下结合图7和图8对本公开实施例提供的移位寄存器单元的电路的具体结构进行举例说明。
参照图7，抗漏电电路60包括第一晶体管T1，第一晶体管T1的栅极连接第二电压端V2，源漏极中的一个连接第一节点PUCN，源漏极中的另一个连接第二节点PU。第一输入电路10包括第二晶体管T2。 第二晶体管T2的栅极连接第一信号输入端INPUT1，源漏极中的一个连接第一控制电压端CN，源漏极中的另一个连接第一节点PUCN。第二输入电路20包括第三晶体管T3。第三晶体管T3的栅极连接第二信号输入端INPUT2，源漏极中的一个连接第二控制电压端CNB，源漏极中的另一个连接第一节点PUCN。输出电路30包括第四晶体管T4和第一电容C1。第四晶体管T4的栅极连接第二节点PU，源漏极中的一个配置成接收第一有效时钟信号或第一无效时钟信号，源漏极中的另一个连接信号输出端OUT。第一电容C1的一端连接第二节点PU，另一端连接信号输出端OUT。第一控制电路40包括第五晶体管T5、第六晶体管T6和第二电容C1。第五晶体管T5的源漏极中的一个和栅极配置成接收第二有效时钟信号或第二无效时钟信号，源漏极中的另一个连接第三节点PD。第六晶体管T6的栅极连接第一节点PUCN，源漏极中的一个连接第三节点PD，源漏极中的另一个连接第一电压端VGL。第二电容C1的一端连接第三节点PD，另一端连接第一电压端VGL。第二控制电路50包括第八晶体管T8和第九晶体管T9。第八晶体管T8的栅极连接第三节点PD，源漏极中的一个连接第一节点PUCN，源漏极中的另一个连接第一电压端VGL。第九晶体管T9的栅极连接第三节点PD，源漏极中的一个连接信号输出端OUT，源漏极中的另一个连接第一电压端VGL。
在另一实施例中，参照图8，第一控制电路40还包括第七晶体管T7。第七晶体管T7的栅极连接信号输出端OUT，源漏极中的一个连接第三节点PD，源漏极中的另一个连接第一电压端VGL。
需要说明的是，本公开不将所提到的晶体管限定为单个晶体管，其可以是多个晶体管的串联。图7和图8中以术语“第n晶体管”包括一个晶体管为例进行示意。在本公开的实施例中，上述晶体管可以均为P型晶体管或者均为N型晶体管。当上述晶体管均为P型晶体管时，术语“源漏极中的一个”具体为源极，术语“源漏极中的另一个”具体为漏极。例如，当第一晶体管为P型晶体管时，表述“第一晶体管的源漏极中的一个连接第一节点，并且第一晶体管的源漏极中的另一个连接第二节点”可被理解为第一晶体管的源极连接所述第一节点，并且第一晶体管的漏极连接第二节点。当上述晶体管均为N型晶体管时，术语“源漏极中的一个”为漏极，并且术语“源漏极中的另一个” 为源极。本公开实施例以各晶体管为N型晶体管为例进行说明。
上述晶体管可以为双栅极晶体管，也可以为单栅极晶体管。通常单栅极晶体管的漏电流比双栅极晶体管的漏电流大，使得移位寄存器单元的稳定性较差。由于本公开实施例的移位寄存器单元在触控阶段对第二节点PU的抗漏电能力较强，因此当本实施例中的各晶体管均为单栅极晶体管时，可以避免单栅极晶体管的漏电流较大所导致的移位寄存器单元的稳定性差的问题。
另外，当上述各晶体管均为单栅极晶体管时，可以减小移位寄存器单元的布线空间，从而实现触控显示面板的更窄边框。另一方面，也可以通过等比例减小晶体管的宽和长等方式来减小布线空间，从而实现触控显示面板的窄边框。本公开实施例对此不做限定。
此外，本公开实施例提供的移位寄存器单元构成的栅极驱动电路可以实现对栅线的双向扫描。具体的，当第一控制电压端CN输出恒定的高电平，且第二控制电压端CNB输出恒定的低电平时，栅极驱动电路可以正向扫描。当第一控制电压端CN输出恒定的低电平，且第二控制电压端CNB输出恒定的高电平时，栅极驱动电路可以反向扫描。
以下对图7和图8的移位寄存器单元用于正向扫描时的具体工作过程进行说明，移位寄存器单元中各晶体管为N型晶体管。该移位寄存器单元用于正向扫描时，CN＝1，CNB＝0。“1”为高电平，“0”为低电平。
一图像帧内，在显示阶段，控制该移位寄存器单元的第二电压端V2的电压为有效的第一电压，以使该移位寄存器单元的抗漏电电路60处于允许第一节点PUCN与第二节点PU导通的状态。显示阶段包括输入阶段、输出阶段和复位阶段。
具体的，上述第一电压为高电平信号，在第二电压端V2的控制下，第一晶体管T1导通，第一节点PUCN的电位与第二节点PU的电位相同。
在输入阶段中，响应于第一信号输入端INPUT1的有效电位，第一控制电压端CN与第二节点PU导通。此时第一控制电压端CN的电位与第二节点PU的电位相同。具体的，INPUT1＝1，INPUT2＝0，CKB＝1，CK＝0，PD＝0，OUT＝0，PUCN＝PU＝1。在此情况下，响应于第一信号输入端INPUT1的有效电位，第二晶体管T2导通，第一控制电压端 CN的高电平通过第二晶体管T2传递至第一节点PUCN。并且，响应于第二电压端V2的有效电位，第一节点PUCN的电荷通过第一晶体管T1传递至第二节点PU，并通过第一电容C1对该电荷进行存储。响应于第二有效时钟信号(即，第二时钟信号端CKB的有效电位)，第五晶体管T5导通，第二时钟信号端CKB与第三节点PD导通，第二有效时钟信号通过第五晶体管T5传递至第三节点PD。响应于第一节点PUCN的有效电位，第六晶体管T6导通，第一电压端VGL的低电位通过第六晶体管T6传递至第三节点PD。通过设置第五晶体管T5和第六晶体管T6的尺寸比例，例如设置第六晶体管T6的宽长比大于第五晶体管T5的宽长比，可以使第三节点PD为低电平。响应于第三节点PD的无效电位，第八晶体管T8、第九晶体管T9截止。响应于第二信号输入端INPUT2的无效电位，第三晶体管T3截止。
响应于第二节点PU的有效电位，第四晶体管T4导通，第一无效时钟信号通过第四晶体管T4传递至信号输出端OUT。因此，在输入阶段，信号输出端OUT不输出栅极扫描信号。
在输出阶段，响应于第二节点PU的有效电位，输出电路30将第一时钟信号端CK的信号作为栅极扫描信号输出至信号输出端OUT。具体的，INPUT1＝0，INPUT2＝0，CKB＝0，CK＝1，PD＝0，OUT＝1，PUCN＝PU＝1。由于第一信号输入端INPUT1输出低电平，因此第二晶体管T2处于截止状态。第一电容C1将存储的电荷用于对第二节点PU进行充电以维持第二节点PU的电位，使得第四晶体管T4保持导通状态。在此情况下，第一有效时钟信号作为栅极扫描信号通过第四晶体管T4传递至信号输出端OUT，以用于对与该信号输出端OUT相连接的栅线进行扫描。此外，在第一电容C1的自举作用下，第二节点PU和第一节点PUCN的电位进一步升高。
此外，响应于第二无效时钟信号，第五晶体管T5截止。响应于第一节点PUCN的有效电位，第六晶体管T6导通，第三节点PD与第一电压端VGL导通，第三节点PD的高电位下拉至第一电压端VGL的低电位。
在第一控制电路还包括第七晶体管T7的实施例中，当信号输出端OUT的输出信号为高电平时，第七晶体管T7导通。这进一步保证了第三节点PD为低电平，进而增强了移位寄存器单元的输出驱动能力。
在复位阶段中，响应于第二信号输入端INPUT2的有效电位，第二输入电路20将第二节点PU的电位下拉至第二控制电压端CNB。第一控制电路40对第二有效时钟信号的电荷进行存储。在第二有效时钟信号的控制下，来自于第二有效时钟信号的电荷输出至第三节点PD，或者存储的电荷释放至第三节点PD，使得第三节点保持在不同于第一电压端VGL的电位的第一电位。在第三节点PD的第一电位的控制下，第二控制电路50将第一节点PUCN和信号输出端OUT的电位下拉至第一电压端VGL。具体的，INPUT1＝0，INPUT2＝1，CKB＝1，CK＝0，OUT＝0，PUCN＝PU＝0，PD＝1。在此情况下，响应于第一信号输入端INPUT1的无效电位，第二晶体管T2截止。响应于第二信号输入端INPUT2的有效电位，第三晶体管T3导通，从而第二控制电压端CNB与第一节点PUCN导通，使得第一节点的电位等于第二控制电压端CNB的低电平。并且，响应于第二电压端的有效电位，第一晶体管T1导通，第一节点PUCN的低电平被传递至第二节点PU。响应于第一节点PUCN的无效电位，第六晶体管T6截止。响应于第二节点PU的无效电位，第四晶体管T4截止。响应于第二有效时钟信号，第五晶体管T5导通，第二有效时钟信号通过第五晶体管T5传递至第三节点PD，第二电容C2对来自于第二时钟有效信号的电荷进行存储。响应于第三节点PD的有效电位，第八晶体管T8和第九晶体管T9导通。通过第八晶体管T8，第一节点PUCN和第二节点PU的电位都下拉至第一电压端VGL的低电平。通过第九晶体管T9，信号输出端OUT的电位下拉至第一电压端VGL的低电平。
接下来，在下一图像帧之前，响应于第二信号输入端INPUT2的无效电位，第三晶体管T3截止。当接收到第二有效时钟信号时，第二时钟信号端CKB与第三节点PD导通，第二有效时钟信号通过第五晶体管T5传递至第三节点PD，且第二电容C2对来自于第二有效时钟信号的电荷进行存储。当接收到第二无效时钟信号时，第二电容C2可以将存储的电荷输出至第三节点PD，以使得该第三节点PD保持高电平。从而在下一图像帧之前，响应于第三节点PD的有效电位，第八晶体管T8导通，第一节点PUCN的电位可以通过第八晶体管T8被下拉至第一电压端VGL的低电平。第一控制电路40和第二控制电路50重复该过程。
以上是移位寄存器单元在显示阶段的工作过程。接下来对移位寄存器单元在触控阶段的工作过程进行说明。在触控阶段中，第一时钟信号端CK和第二时钟信号端CKB的信号均为无效信号(即，移位寄存器单元接收第一无效时钟信号和第二无效时钟信号)，因此在该阶段中移位寄存器单元不输出栅极扫描信号。
图9示意性地示出了根据本公开实施例的栅极驱动电路在触控阶段的时序控制图。图10示意性地示出了利用本公开实施例的移位寄存器单元形成的栅极驱动电路的结构。如图9所示，在触控阶段，控制移位寄存器单元的第二电压端V2的电压为不同于第一电压的第二电压。如前所述，第一电压为使晶体管T1导通的有效电压。因此，第二电压为无效电压，使得移位寄存器单元的抗漏电电路60处于截止状态，第一节点PUCN与第二节点PU断开，第一节点PUCN的电位无法传递至第二节点PU。晶体管为N型时第二电压为低电平信号。在第二电压端V2的控制下，第一晶体管T1截止，第一节点PUCN的电位不能传递至第二节点PU。具体的，若移位寄存器单元为触控阶段后需要启动的那一级移位寄存器单元(即图10中的第RS(N+1)级移位寄存器单元)，则在触控阶段，CN＝1，CNB＝0，INPUT1＝0，INPUT2＝0，(PUCN_N+1)＝1，(PU_N+1)＝1，PD＝0，CK＝0，CKB＝0。
在此情况下，第三晶体管T3处于导通状态，第一节点PUCN_N+1与低电位的VGL第一电压端导通，第一节点PUCN_N+1会通过第三晶体管T3漏电。由于第二电压端V2为低电位，第一节点PUCN_N+1与第二节点PU_N+1不导通，第一节点PUCN_N+1的电位不能传递至第二节点PU_N+1，因此第一节点PUCN_N+1的漏电在触控阶段不会导致第二节点PU_N+1发生漏电，从而第二节点PU_N+1可以保持高电平(如图9的03处所示)。因此在触控阶段结束后，第RS(N+1)级移位寄存器单元可以正常输出OUT_N+1信号(如图9的02处所示)，从而可以避免在触控阶段中第二节点PU_N+1发生漏电，进而可以防止触控阶段结束后第RS(N+1)级移位寄存器单元出现输出电压不足，导致像素充电不足，从而出现显示异常等问题。
第一节点PUCN_N+1在触控阶段通过第三晶体管T3漏电的原理与图1所示的移位寄存器单元中第二节点PU在触控阶段通过晶体管T2漏电的原理相同。当第一节点PUCN_N+1在触控阶段的漏电现象较 为严重时，在触控阶结束后，第一晶体管T1在第二电压端V2的控制下导通。第一节点PUCN_N+1的低电位传递至第二节点PU_N+1时，可能会瞬间降低第二节点PU_N+1的电位。在第二节点PU_N+1的低电位的影响下，第四晶体管T4可能打开不充分，从而导致信号输出端OUT的输出电压不足，进而导致像素充电不足，出现显示异常。
为了避免该问题，在一些实施例中，在触控阶段，如图9所示，控制移位寄存器单元的第一控制电压端CN和第二控制电压端CNB的电压为高电平信号(即CN＝CNB＝1，如图9的01处所示)，以减少移位寄存器单元的第一节点PUCN在触控阶段的漏电。在此情况下，第三晶体管T3的栅源电压为低电平，源漏电压为0V左右。根据图4，若移位寄存器单元中的晶体管的特性正常，则当栅源电压V gs为低电平时，漏电流I ds的量级为1×E -11量级。即使移位寄存器单元中的晶体管的特性不正常，由于第二控制电压端CNB为高电位，第一节点PUCN_N+1不会产生漏电，因此经过触控阶段后，第一节点PUCN_N+1仍能保持高电平，从而不会出现像素充电不足。
这样一来，可以减小第一节点PUCN_N+1在触控阶段的电位降低，从而在触控阶段结束后，当第一节点PUCN_N+1与第二节点PU_N+1导通时，第二节点PU_N+1的电位不会显著降低，从而可以使得第四晶体管T4打开充分，使得信号输出端OUT的输出电压充足，进而进一步降低发生像素充电不足的几率。
需要说明的是，当该移位寄存器单元用于反向扫描时，该移位寄存器单元的工作原理以及避免触控阶段结束后需要启动的那一级移位寄存器单元发生像素充电不足的原理与正向扫描时的原理相同，本公开对此不再赘述。
此外，图7所示的移位寄存器单元和图8所示的移位寄存器单元相比不包括第七晶体管T8。这有利于减小移位寄存器单元的布线空间，实现更窄边框。
根据本公开的另一方面，提供一种驱动移位寄存器单元的方法，包括下述步骤。在显示阶段，控制移位寄存器单元的第二电压端V2的电压为第一电压，使得该移位寄存器单元的抗漏电电路60处于将第一节点PUCN与第二节点PU导通。这使得在第二节点PU的控制下，该移位寄存器单元可以正常输出栅极扫描信号。在触控阶段，控制移位 寄存器单元的第二电压端V2的电压为第二电压，使得移位寄存器单元的抗漏电电路60将第一节点PUCN与第二节点PU断开。
需要说明的是，当抗漏电电路60包含的第一晶体管T1为N型时，第一电压为高电平，以使得显示阶段中第一晶体管T1导通。第二电压为低电平，以使得触控阶段中第一晶体管T1截止。当第一晶体管T1为P型时，第一电压为低电平，以使得显示阶段中第一晶体管T1导通。第二电压为高电平，以使得触控阶段中第一晶体管T1截止。显示阶段包括输入阶段、输出阶段、复位阶段和其他非输出阶段。上面已对显示阶段的各阶段中移位寄存器单元的工作过程进行了详细的说明，此处不再赘述。
由于在触控阶段，第一节点PUCN与第二节点PU断开，因此第一节点PUCN的漏电不会导致第二节点PU发生漏电，从而第二节点PU可以保持高电平，从而可以避免触控阶段中第二节点PU发生漏电，进而可以阻止触控阶段结束后第RS(N+1)级移位寄存器单元发生输出电压不足，导致像素充电不足，出现显示异常等问题。
在一些实施例中，驱动移位寄存器单元的方法还包括：在触控阶段，控制移位寄存器单元的第一控制电压端CN和第二控制电压端CNB的电压为高电平信号，以减少该移位寄存器单元的第一节点PUCN在触控阶段的漏电流。在此情况下，可以减小第一节点PUCN在触控阶段的漏电流，从而在触控阶段结束后，当第一节点PUCN与第二节点PU导通时，第二节点PU保持高电位，信号输出端OUT的输出电压充足，进而进一步降低发生像素充电不足的几率。
根据本公开的又一方面，提供一种栅极驱动电路。如图10所示，该栅极驱动电路包括正扫描信号输入端STV1、反扫描信号输入端STV2以及N个级联的根据本公开实施例的移位寄存器单元，N为大于或等于2的整数。在所述N个级联的移位寄存器单元中，第一级移位寄存器单元的第一信号输入端INPUT1连接所述栅极驱动电路的正扫描信号输入端STV1，并配置成在起始阶段接收正扫描输入信号(即，起始信号)。第m级移位寄存器单元的第一信号输入端与第m-1级移位寄存器单元的信号输出端相连接，其中m为整数且2≤m≤N。第n级移位寄存器单元的第二信号输入端与第n+1级移位寄存器单元的信号输出端相连接，其中n为整数且1≤n＜N。最后一级移位寄存器单元(即， 第N级的移位寄存器单元)的第二输入端INPUT2连接所述栅极驱动电路的反扫描信号输入端STV2，并配置成在复位阶段接收反扫描输入信号(即，复位信号)。
需要说明的是，可以将正扫描信号输入端STV1的起始信号作为复位信号对最后一级移位寄存器单元RS(x)进行复位，也可以单独向反扫描信号输入端STV2输入复位信号。第一时钟信号端CK的时钟信号clock1和第二时钟信号端CKB的时钟信号clock2互补(即，当移位寄存器单元接着收第一有效时钟信号时，其同时接收第二无效时钟信号；当移位寄存器单元接着收第一无效时钟信号时，其同时接收第二有效时钟信号)，并每经过一级移位寄存器单元交换一次顺序。
本公开实施例提供的栅极驱动电路，在一图像帧内，在第n级移位寄存器单元的信号输出端输出信号后，进入触控阶段。在触控阶段中，控制第n+1级移位寄存器单元的抗漏电电路60处于禁止第一节点PUCN与第二节点PU导通的状态，从而可以减小第n+1级移位寄存器单元的第二节点PU的漏电，进而可以降低第n+1级移位寄存器单元发生输出电压不足，导致像素充电不足，出现显示异常的几率。
根据本公开的再一方面，提供一种触控显示装置，包括根据本公开实施例的栅极驱动电路。该触控显示装置具有与前述实施例提供的栅极驱动电路相同的结构和有益效果，此处不再赘述。
需要说明的是，触控显示装置具体至少可以包括液晶显示装置和有机发光二极管显示装置。例如，该触控显示装置可以为液晶显示器、液晶电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。通过研究附图、公开内容和所附权利要求，本领域技术人员在实践所要求保护的发明时，可以理解和达成对所公开实施例的其它变型。权利要求中，词语“包括”不排除其它元素或步骤，并且不定冠词“一”不排除复数。在互不相同的从属权利要求中列举某些措施的纯粹事实并不 表示这些措施的组合不能用于获利。权利要求中的任何附图标记不应解释为限制范围。

Claims (18)

  1. 一种移位寄存器单元，包括：
    第一输入电路，其配置成响应于第一信号输入端的有效电位，将第一控制电压端与第一节点导通；
    第二输入电路，其配置成响应于第二信号输入端的有效电位，将第二控制电压端与所述第一节点导通；
    输出电路，其配置成响应于第二节点的有效电位，将第一有效时钟信号传递至信号输出端；
    第一控制电路，其配置成响应于所述第一节点的有效电位，将第一电压端与第三节点导通，并且还配置成响应于第二无效时钟信号和所述第一节点的无效电位，将所述第三节点保持在第一电位；
    第二控制电路，其配置成响应于所述第三节点的有效电位，将所述第一节点与所述第一电压端导通，并将所述信号输出端与所述第一电压端导通；以及
    抗漏电电路，其配置成响应于第二电压端的有效电位，将所述第一节点与所述第二节点导通。
  2. 根据权利要求1所述的移位寄存器单元，其中所述第一控制电路配置成：
    响应于第二有效时钟信号，将所述第二有效时钟信号传递至所述第三节点，并对来自所述第二有效时钟信号的电荷进行存储；以及
    响应于所述第二无效时钟信号和所述第一节点的无效电位，将存储的所述电荷输出至所述第三节点，使所述第三节点保持在所述第一电位。
  3. 根据权利要求1所述的移位寄存器单元，其中所述第一电位与所述第一电压端的电位不同。
  4. 根据权利要求1所述的移位寄存器单元，其中所述抗漏电电路包括第一晶体管，所述第一晶体管的栅极连接所述第二电压端，所述第一晶体管的源漏极中的一个连接所述第一节点，并且所述第一晶体管的源漏极中的另一个连接所述第二节点。
  5. 根据权利要求1所述的移位寄存器单元，其中所述第一输入电路包括第二晶体管，所述第二晶体管的栅极连接所述第一信号输入端， 所述第二晶体管的源漏极中的一个连接所述第一控制电压端，并且所述第二晶体管的源漏极中的另一个连接所述第一节点。
  6. 根据权利要求1所述的移位寄存器单元，其中所述第二输入电路包括第三晶体管，所述第三晶体管的栅极连接所述第二信号输入端，所述第三晶体管的源漏极中的一个连接所述第一节点，并且所述第三晶体管的源漏极中的另一个连接所述第二控制电压端。
  7. 根据权利要求1所述的移位寄存器单元，其中所述第一输入电路包括第二晶体管，所述第二晶体管的栅极连接所述第一信号输入端，所述第二晶体管的源漏极中的一个连接所述第一控制电压端，并且所述第二晶体管的源漏极中的另一个连接所述第一节点；并且
    所述第二输入电路包括第三晶体管，所述第三晶体管的栅极连接所述第二信号输入端，所述第三晶体管的源漏极中的一个连接所述第一节点，并且所述第三晶体管的源漏极中的另一个连接所述第二控制电压端。
  8. 根据权利要求1所述的移位寄存器单元，其中所述输出电路包括第四晶体管和第一电容；其中
    所述第四晶体管的栅极连接所述第二节点，所述第四晶体管的源漏极中的一个配置成接收所述第一有效时钟信号，并且所述第四晶体管的源漏极中的另一个连接所述信号输出端；并且
    所述第一电容的一端连接所述第二节点，并且所述第一电容的另一端连接所述信号输出端。
  9. 根据权利要求2所述的移位寄存器单元，其中所述第一控制电路包括第五晶体管、第六晶体管和第二电容；其中
    所述第五晶体管的源漏极中的一个和栅极配置成接收所述第二有效时钟信号或所述第二无效时钟信号，并且所述第五晶体管的源漏极中的另一个连接所述第三节点；
    所述第六晶体管的栅极连接所述第一节点，所述第六晶体管的源漏极中的一个连接所述第三节点，并且所述第六晶体管的源漏极中的另一个连接所述第一电压端；并且
    所述第二电容的一端连接所述第三节点，并且所述第二电容的另一端连接所述第一电压端。
  10. 根据权利要求9所述的移位寄存器单元，其中所述第一控制电 路还包括第七晶体管，所述第七晶体管的栅极连接所述信号输出端，所述第七晶体管的源漏极中的一个连接所述第三节点，并且所述第七晶体管的源漏极中的另一个连接所述第一电压端。
  11. 根据权利要求1所述的移位寄存器单元，其中所述第二控制电路包括第八晶体管和第九晶体管；其中
    所述第八晶体管的栅极连接所述第三节点，所述第八晶体管的源漏极中的一个连接所述第一节点，并且所述第八晶体管的源漏极中的另一个连接所述第一电压端；并且
    所述第九晶体管的栅极连接所述第三节点，所述第九晶体管的源漏极中的一个连接所述信号输出端，并且所述第九晶体管的源漏极中的另一个连接所述第一电压端。
  12. 根据权利要求1所述的移位寄存器单元，其中所述第一输入电路、所述第二输入电路、所述输出电路、所述第一控制电路、所述第二控制电路和所述抗漏电电路各自包括的晶体管为单栅极晶体管。
  13. 根据权利要求12所述的移位寄存器单元，其中所述晶体管均为N型晶体管或者均为P型晶体管。
  14. 一种驱动如权利要求1-13中的任意一项所述的移位寄存器单元的方法，包括：
    在显示阶段，控制所述移位寄存器单元的所述第二电压端的电压为第一电压，使得所述移位寄存器单元的所述抗漏电电路将所述第一节点与所述第二节点导通；以及
    在触控阶段，控制所述移位寄存器单元的所述第二电压端的电压为第二电压，使得所述移位寄存器单元的所述抗漏电电路将所述第一节点与所述第二节点断开。
  15. 根据权利要求14所述的方法，还包括：
    在所述触控阶段，控制所述移位寄存器单元的第一控制电压端和第二控制电压端的电压均为高电位，以使所述移位寄存器单元的所述第一节点的电位在所述触控阶段得到保持。
  16. 一种栅极驱动电路，包括N个级联的如权利要求1-13中的任意一项所述的移位寄存器单元，N为大于或等于2的整数；其中，在所述N个移位寄存器单元中：
    第m级移位寄存器单元的第一信号输入端与第m-1级移位寄存器 单元的信号输出端相连接，其中m为整数且2≤m≤N，并且
    第n级移位寄存器单元的第二信号输入端与第n+1级移位寄存器单元的信号输出端相连接，其中n为整数且1≤n＜N。
  17. 如权利要求16所述的栅极驱动电路，其中第1级移位寄存器单元的第一信号输入端配置成接收正扫描输入信号，且第N级移位寄存器单元的第二信号输入端配置成接收反扫描输入信号。
  18. 一种触控显示装置，包括如权利要求16所述的栅极驱动电路。
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