WO2020191597A1 - 移位寄存器、其驱动方法、栅极驱动电路及显示装置 - Google Patents

移位寄存器、其驱动方法、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2020191597A1
WO2020191597A1 PCT/CN2019/079589 CN2019079589W WO2020191597A1 WO 2020191597 A1 WO2020191597 A1 WO 2020191597A1 CN 2019079589 W CN2019079589 W CN 2019079589W WO 2020191597 A1 WO2020191597 A1 WO 2020191597A1
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WIPO (PCT)
Prior art keywords
transistor
signal
terminal
coupled
gate
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PCT/CN2019/079589
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English (en)
French (fr)
Inventor
商广良
刘利宾
郑灿
陈义鹏
殷新社
史世明
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN201980000375.9A priority Critical patent/CN112041920A/zh
Priority to US16/651,816 priority patent/US11170682B2/en
Priority to EP19861299.6A priority patent/EP3951765B1/en
Priority to PCT/CN2019/079589 priority patent/WO2020191597A1/zh
Publication of WO2020191597A1 publication Critical patent/WO2020191597A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a shift register, a driving method thereof, a gate driving circuit, and a display device.
  • GOA Gate Driver on Array, array substrate row drive
  • TFT Thin Film Transistor, thin film transistor
  • the gate drive circuit is usually composed of multiple cascaded shift registers.
  • the output of the shift register is unstable, which may cause display abnormalities.
  • the input circuit is configured to be respectively coupled to the input signal terminal and the second clock signal terminal;
  • a first transistor, the first pole of the first transistor is coupled to the output terminal of the input circuit; and the first transistor is a double-gate transistor; wherein the first gate of the first transistor is configured In order to be coupled to the first reference signal terminal, the second gate of the first transistor is configured to be coupled to the first threshold control signal terminal;
  • the output circuit is configured to be respectively coupled to the first clock signal terminal and the signal output terminal, and the control terminal of the output circuit is coupled to the second pole of the first transistor.
  • the input circuit includes: a second transistor of a single gate type
  • the gate of the second transistor is configured to be coupled to the second clock signal terminal
  • the first electrode of the second transistor is configured to be coupled to the input signal terminal
  • the second transistor of the second transistor is configured to be coupled to the input signal terminal.
  • the two poles are coupled to the first pole of the first transistor.
  • the second gate of the first transistor is coupled to the gate of the second transistor; or,
  • the second gate of the first transistor is coupled to the first electrode of the second transistor.
  • the input circuit includes: a double gate type second transistor; wherein the first gate of the second transistor is configured to be coupled to the second clock signal terminal , The second gate of the second transistor is configured to be coupled to the second threshold adjustment signal terminal, the first electrode of the second transistor is configured to be coupled to the input signal terminal, and the second transistor The second electrode of is coupled to the first electrode of the first transistor.
  • the second gate of the second transistor is coupled to the first gate of the second transistor; or,
  • the second gate of the second transistor is coupled to the first electrode of the second transistor.
  • the second gate of the first transistor is coupled to the first gate of the second transistor; or,
  • the second gate of the first transistor is coupled to the first electrode of the second transistor.
  • the shift register further includes: a fifth transistor, a sixth transistor, a seventh transistor, and a first capacitor;
  • the gate of the fifth transistor is configured to be coupled to the second clock signal terminal, the first electrode of the fifth transistor is configured to be coupled to the first reference signal terminal, and the fifth transistor The second electrode of is coupled to the gate of the seventh transistor;
  • the gate of the sixth transistor is coupled to the first electrode of the first transistor, the first electrode of the sixth transistor is configured to be coupled to the second clock signal terminal, and the The second electrode is coupled to the gate of the seventh transistor;
  • a first pole of the seventh transistor is configured to be coupled to the second reference signal terminal, and a second pole of the seventh transistor is coupled to the signal output terminal;
  • the first terminal of the first capacitor is coupled to the gate of the seventh transistor, and the second terminal of the first capacitor is configured to be coupled to the second reference signal terminal.
  • the shift register further includes: a pull-up control circuit; wherein the first control terminal of the pull-up control circuit is configured to be coupled to the first clock signal terminal , The second control terminal of the pull-up control circuit is coupled to the gate of the seventh transistor, the input terminal of the pull-up control circuit is configured to be coupled to the second reference signal terminal, and the upper The output terminal of the pull control circuit is coupled with the first pole of the first transistor.
  • the pull-up control circuit includes: a third transistor and a single-gate fourth transistor;
  • the gate of the third transistor is configured to be coupled to the first clock signal terminal, the first pole of the third transistor is coupled to the first pole of the first transistor, and the The second electrode is coupled to the first electrode of the fourth transistor;
  • the gate of the fourth transistor is coupled to the gate of the seventh transistor, and the second electrode of the fourth transistor is configured to be coupled to the second reference signal terminal.
  • the pull-up control circuit includes: a third transistor and a fourth transistor of a double gate type
  • the gate of the third transistor is configured to be coupled to the first clock signal terminal, the first pole of the third transistor is coupled to the first pole of the first transistor, and the The second electrode is coupled to the first electrode of the fourth transistor;
  • the first gate of the fourth transistor is coupled to the gate of the seventh transistor, the second gate of the fourth transistor is configured to be coupled to the third threshold adjustment signal terminal, and the fourth transistor The second pole of is configured to be coupled to the second reference signal terminal.
  • the second gate of the fourth transistor is coupled to the gate of the seventh transistor.
  • the second gate of the fourth transistor is coupled to the gate of the fifth transistor.
  • the output circuit includes: an eighth transistor and a second capacitor;
  • the gate of the eighth transistor is coupled to the second electrode of the first transistor, the first electrode of the eighth transistor is configured to be coupled to the first clock signal terminal, and the The second pole is coupled to the signal output terminal;
  • the first terminal of the second capacitor is coupled with the second terminal of the first transistor, and the second terminal of the second capacitor is coupled with the signal output terminal.
  • the first threshold control signal terminal is configured to receive a signal having at least a level opposite to that of the first reference signal terminal;
  • the second threshold control signal terminal is configured to receive at least a signal having a level opposite to that of the first reference signal terminal;
  • the third threshold control signal terminal is configured to receive at least a signal having a level opposite to that of the first reference signal terminal.
  • At least one of the first threshold regulation signal terminal, the second threshold regulation signal terminal, and the third threshold regulation signal terminal is configured to receive the signal terminal associated with the second clock signal The timing of the end is the same clock signal.
  • At least one of the first threshold regulation signal terminal, the second threshold regulation signal terminal, and the third threshold regulation signal terminal is configured to receive a fixed voltage signal.
  • the embodiment of the present disclosure also provides a gate driving circuit, including a plurality of cascaded shift registers described above;
  • the input signal terminal of the first-pole shift register is configured to be coupled to the frame trigger signal terminal;
  • the input signal terminal of the next stage shift register is configured to be coupled to the signal output terminal of the previous stage shift register.
  • an embodiment of the present disclosure also provides a display device, including the above-mentioned gate driving circuit.
  • an embodiment of the present disclosure also provides a driving method of the above shift register, including:
  • the input circuit controls the signal level of the first pole of the first transistor according to the signals from the input signal terminal and the second clock signal terminal; the first transistor is turned on; the output The circuit responds to the signal of the second pole of the first transistor to provide the signal of the first clock signal terminal to the signal output terminal;
  • the threshold voltage of the first transistor moves in response to the signal at the first threshold regulation signal terminal, and the first transistor is turned off; the output circuit responds to the signal at the second pole of the first transistor, The signal of the first clock signal terminal is provided to the signal output terminal; wherein the signal of the first threshold value control signal terminal is opposite to the signal of the first reference signal terminal.
  • the input stage further includes: the fifth transistor responds to the signal of the second clock signal terminal and provides the signal of the first reference signal terminal to the gate of the seventh transistor;
  • the sixth transistor responds to the signal of the first pole of the first transistor and provides the signal of the second clock signal terminal to the gate of the seventh transistor;
  • the seventh transistor responds to the signal of the seventh transistor The signal of the gate provides the signal of the second reference signal terminal to the signal output terminal;
  • the driving method further includes:
  • the input circuit controls the signal level of the first pole of the first transistor according to the signals of the input signal terminal and the second clock signal terminal; the first transistor connects the input circuit and The output circuit is turned on; the fifth transistor responds to the signal of the second clock signal terminal to provide the signal of the first reference signal terminal to the gate of the seventh transistor; the seventh transistor responds to the The signal of the gate of the seventh transistor provides the signal of the second reference signal terminal to the signal output terminal.
  • the threshold voltage of the second transistor moves in response to the signal of the second threshold regulating signal terminal, the second transistor is turned off; the threshold voltage of the fourth transistor is in response to The third threshold regulates the movement of the signal at the signal terminal, and the fourth transistor is turned off.
  • Figure 1 is a schematic diagram of the structure of a shift register in the related art
  • FIG. 2 is a signal timing diagram of the shift register shown in FIG. 1;
  • Fig. 3a is a simulation diagram corresponding to the signal output terminal of the shift register shown in Fig. 1;
  • FIG. 3b is a simulation diagram corresponding to the first pull-up node of the shift register shown in FIG. 1;
  • FIG. 4a is one of the structural schematic diagrams of the shift register provided by the embodiment of the disclosure.
  • 4b is the second structural diagram of the shift register provided by the embodiment of the disclosure.
  • FIG. 5a is one of signal timing diagrams provided by an embodiment of the disclosure.
  • FIG. 5b is the second signal timing diagram provided by an embodiment of the disclosure.
  • Fig. 6 is a simulation diagram corresponding to the signal output terminal of the shift register shown in Fig. 4b;
  • FIG. 7 is the third structural diagram of a shift register provided by an embodiment of the disclosure.
  • FIG. 8 is the third signal timing diagram provided by an embodiment of the disclosure.
  • FIG. 9a is the fourth structural diagram of a shift register provided by an embodiment of the disclosure.
  • Fig. 9b is a simulation diagram corresponding to the signal output terminal of the shift register shown in Fig. 9a;
  • FIG. 9c is a simulation diagram corresponding to the first pull-up node of the shift register shown in FIG. 9a;
  • FIG. 10a is the fourth signal timing diagram provided by an embodiment of the disclosure.
  • FIG. 10b is the fifth signal timing diagram provided by an embodiment of the disclosure.
  • FIG. 10c is the sixth of the signal timing diagram provided by an embodiment of the disclosure.
  • FIG. 12 is the seventh signal timing diagram provided by the embodiments of the disclosure.
  • FIG. 13 is a sixth structural diagram of a shift register provided by an embodiment of the disclosure.
  • FIG. 14a is a seventh structural diagram of a shift register provided by an embodiment of the disclosure.
  • FIG. 14b is the eighth of the signal timing diagram provided by the embodiments of the disclosure.
  • 16 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the disclosure.
  • FIG. 17 is a schematic structural diagram of a display device provided by an embodiment of the disclosure.
  • the shift register may include transistors M01 to M08 and capacitors C01 to C02.
  • the signal timing diagram corresponding to the shift register shown in FIG. 1 is shown in FIG. 2.
  • the transistor M02 and the transistor M05 are turned on under the control of the signal at the clock signal terminal CK.
  • the turned-on transistor M05 provides the low-level signal of the signal terminal VSS to the pull-down node PD, making the signal of the pull-down node PD a low-level signal to control the transistor M04 and the transistor M07 to conduct, and the transistor M03 is at the clock signal terminal CKB Cut off under the control of the signal.
  • the turned-on transistor M07 provides the high-level signal of the signal terminal VDD to the signal output terminal OP, so that the signal output terminal OP outputs a high-level signal.
  • the turned-on transistor M02 provides the low-level signal of the input signal terminal IP to the second pull-up node PU_2, so that the signal of the second pull-up node PU_2 is a low-level signal.
  • the transistor M06 is turned on under the control of the signal of the second pull-up node PU_2 to provide the low-level signal of the clock signal terminal CK to the pull-down node PD.
  • the transistor M01 Since the transistor M01 satisfies V gs01 ⁇ V th01 , the transistor M01 is turned on; wherein, at this time, the pole of the transistor M01 connected to the first pull-up node PU_1 serves as the source, and V gs01 represents the gap between the gate and the source of the transistor M01 V th01 represents the threshold voltage of transistor M01.
  • the turned-on transistor M01 turns on the second pull-up node PU_2 and the first pull-up node PU_1, so that the signal of the first pull-up node PU_1 is a low-level signal to control the transistor M08 to turn on.
  • the turned-on transistor M08 provides the high-level signal of the clock signal terminal CKB to the signal output terminal OP, so that the signal output terminal OP outputs a high-level signal.
  • the voltage of the low-level signal of the first pull-up node PU_1 may be the same as the voltage of the signal of the signal terminal VSS. Due to the threshold voltage of the transistor M01, there may be a first pull-up. The voltage of the low-level signal of the node PU_1 is less than the voltage of the low-level signal of the second pull-up node PU_2.
  • the specific voltage can be designed and determined according to the actual application environment, which is not limited here.
  • the transistor M02 and the transistor M05 are turned off under the control of the high-level signal of the clock signal terminal CK, and the transistor M03 is also turned off under the control of the high-level signal of the clock signal terminal CKB. .
  • the first pull-up node PU_1 is maintained as a low-level signal under the action of the capacitor C01.
  • the pole with a higher voltage can be used as the source of the transistor.
  • the transistor M01 is electrically connected to the second pull-up node PU_2 at this stage One of the poles is used as its source, so that the transistor M01 can satisfy V gs01 ⁇ V th01 , so the transistor M01 is turned on, so that the signal of the second pull-up node PU_2 is a low-level signal.
  • the transistor M06 is turned on under the control of the signal of the second pull-up node PU_2 to provide the high-level signal of the clock signal terminal CKB to the pull-down node PD so that the signal of the pull-down node PD is a high-level signal to control the transistor M04 And transistor M07 is off.
  • the transistor M08 is turned on under the control of the signal of the first pull-up node PU_1 to provide the high-level signal of the clock signal terminal CKB to the signal output terminal OP, so that the signal output terminal OP outputs a high-level signal.
  • the transistor M02 and the transistor M05 are turned off under the control of the high-level signal at the clock signal terminal CK, and the first pull-up node PU_1 is maintained as a low-level signal under the action of the capacitor C01 to control the transistor M08 to turn on , Thereby providing the low-level signal of the clock signal terminal CKB to the signal output terminal OP. Due to the action of the capacitor C01, the level of the first pull-up node PU_1 is further pulled down to control the transistor M08 to be fully turned on as much as possible to provide the low-level signal of the clock signal terminal CKB to the signal output terminal OP, The signal output terminal OP outputs a low-level signal.
  • FIGS. 3a and 3b show.
  • Fig. 3a is a simulation diagram of the signal output by the signal output terminal OP of the shift register shown in Fig. 1 under the control of the signal shown in Fig. 2.
  • 3b is a simulation diagram of the signal of the first pull-up node PU_1 in the shift register shown in FIG. 1 under the control of the signal shown in FIG. 2.
  • the abscissa represents time
  • the ordinate represents voltage.
  • FIG. 4a Some shift registers, as shown in FIG. 4a, which may include:
  • the input circuit 10 is configured to be respectively coupled to the input signal terminal IP and the second clock signal terminal CK2;
  • the first transistor M1, the first pole of the first transistor M1 is coupled to the output terminal of the input circuit 10; and the first transistor M1 is a double-gate transistor; wherein, the first gate of the first transistor M1 is configured to A reference signal terminal VREF1 is coupled, and the second gate of the first transistor M1 is configured to be coupled to the first threshold control signal terminal VS1;
  • the output circuit 20 is configured to be respectively coupled to the first clock signal terminal CK1 and the signal output terminal OP, and the control terminal of the output circuit 20 is coupled to the second pole of the first transistor M1.
  • the first transistor is configured as a double-gate transistor, wherein the first gate of the first transistor receives the first reference signal terminal, and the second gate of the first transistor receives the first reference signal terminal.
  • the threshold adjustment signal terminal can make the first transistor conduct in the input phase, the reset phase, and the reset hold phase. And, at least in the output stage, the signal value of the regulation signal terminal of the first threshold regulation threshold voltage V th1 of the first transistor, the threshold voltage V th1 of the first transistor is moved, so that the first transistor is turned off in the output stage as much as possible ,
  • the signal level of the first pull-up node can be kept stable, and the influence of leakage on the signal of the first pull-up node can be avoided. Therefore, the stability of the signal output by the signal output terminal is improved, which is beneficial to be applied to a display device driven by low frequency, and is beneficial to reduce power consumption.
  • the first pull-up node PU_1 is between the control terminal of the output circuit 20 and the second pole of the first transistor M1.
  • the second pull-up node PU_2 is located between the output terminal of the input circuit 10 and the first pole of the first transistor M1.
  • the first pull-up node PU_1 and the second pull-up node PU_2 are virtual nodes in the shift register. These two nodes are only for the convenience of describing the structure of the shift register and the transmission of signals. The specific structure of the shift register and the signal transmission can be determined according to the coupling mode between each transistor in the shift register and the capacitor.
  • the input circuit 10 is configured to control the signal level of the second pull-up node PU_2 according to the input signal terminal IP and the second clock signal terminal CK2. In this way, the signal of the input signal terminal IP can be input through the input circuit 10.
  • the output circuit 20 is configured to provide the signal of the first clock signal terminal CK1 to the signal output terminal OP in response to the signal of the first pull-up node PU_1. In this way, the signal of the first clock signal terminal CK1 can be output through the output circuit 20.
  • the second pull-up node PU_2 is coupled to the first pull-up node PU_1 through the first transistor M1.
  • the first pole of the first transistor M1 is coupled to the second pull-up node PU_2, and the second pole of the first transistor M1 is coupled to the first pull-up node PU_2.
  • PU_1 is coupled.
  • the input circuit 10 may include: a single-gate second transistor M2; wherein the gate of the second transistor M2 is configured to be coupled to the second clock signal terminal CK2, and the second transistor M2
  • the first pole is configured to be coupled to the input signal terminal IP
  • the second pole of the second transistor M2 is coupled to the first pole of the first transistor M1, that is, the second pole of the second transistor M2 and the second pull-up node PU_2 Coupling.
  • the signal of the input signal terminal IP can be provided to the first pole of the first transistor M1 (ie, the second pull-up node PU_2) to control the signal level of the first pole (ie, the second pull-up node PU_2) of the first transistor M1.
  • the shift register may further include: a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and a first capacitor C1;
  • the gate of the fifth transistor M5 is configured to be coupled to the second clock signal terminal CK2, the first pole of the fifth transistor M5 is configured to be coupled to the first reference signal terminal VREF1, and the second pole of the fifth transistor M5 is coupled to The gate of the seventh transistor M7 (ie the pull-down node PD) is coupled;
  • the gate of the sixth transistor M6 is coupled to the first pole (ie, the second pull-up node PU_2) of the first transistor M1, the first pole of the sixth transistor M6 is configured to be coupled to the second clock signal terminal CK2,
  • the second electrode of the six transistor M6 is coupled to the gate of the seventh transistor M7 (ie the pull-down node PD);
  • the first pole of the seventh transistor M7 is configured to be coupled to the second reference signal terminal VREF2, and the second pole of the seventh transistor M7 is coupled to the signal output terminal OP;
  • the first terminal of the first capacitor C1 is coupled to the gate of the seventh transistor M7 (ie, the pull-down node PD), and the second terminal of the first capacitor C1 is configured to be coupled to the second reference signal terminal VREF2.
  • the signal of the first reference signal terminal VREF1 can be provided to the gate of the seventh transistor M7 (ie the pull-down node PD) .
  • the sixth transistor M6 is in the on state under the control of the signal of the first pole of the first transistor M1 (ie the second pull-up node PU_2), it can provide the signal of the second clock signal terminal CK2 to the seventh transistor M7.
  • Gate ie, pull down node PD).
  • the seventh transistor M7 When the seventh transistor M7 is in the on state under the control of the signal of its gate (ie the pull-down node PD), it can provide the signal of the second reference signal terminal VREF2 to the signal output terminal OP for coupling.
  • the first capacitor C1 can store the signal input to the gate of the seventh transistor M7 (ie, the pull-down node PD) and the signal of the second reference signal terminal VREF2, and keep it stable.
  • the shift register may further include a pull-up control circuit 30.
  • the first control terminal of the pull-up control circuit 30 is configured to be coupled to the first clock signal terminal CK1
  • the second control terminal of the pull-up control circuit 30 is coupled to the gate of the seventh transistor M7
  • the input terminal of 30 is configured to be coupled to the second reference signal terminal VREF2
  • the output terminal of the pull-up control circuit 30 is coupled to the first pole of the first transistor M1.
  • the pull-up control circuit 30 is configured to respond to the signals of the first clock signal terminal CK1 and the gate of the seventh transistor M7 (ie the pull-down node PD) to provide the signal of the second reference signal terminal VREF2 to the first transistor M1.
  • the first pole ie, the second pull-up node PU_2).
  • the pull-up control circuit 30 may include: a third transistor M3 and a single-gate fourth transistor M4; wherein the gate of the third transistor M3 is configured to A clock signal terminal CK1 is coupled, the first pole of the third transistor M3 is coupled to the first pole of the first transistor M1 (ie the second pull-up node PU_2), and the second pole of the third transistor M3 is coupled to the fourth transistor M4 The first pole is coupled.
  • the gate of the fourth transistor M4 is coupled to the gate of the seventh transistor M7 (ie, the pull-down node PD), and the second pole of the fourth transistor M4 is configured to be coupled to the second reference signal terminal VREF2.
  • the fourth transistor M4 when the fourth transistor M4 is in the on state under the control of the signal of the gate of the seventh transistor M7 (ie, the pull-down node PD), it can provide the signal of the second reference signal terminal VREF2 to the fourth transistor M4. One pole.
  • the third transistor M3 When the third transistor M3 is in the on state under the control of the signal of the first clock signal terminal CK1, the first pole of the first transistor M1 (ie, the second pull-up node PU_2) can be connected to the first pole of the fourth transistor M4. Conduction.
  • the output circuit 20 may include: an eighth transistor M8 and a second capacitor C2; wherein the gate of the eighth transistor M8 and the first transistor M1 The two poles (ie, the first pull-up node PU_1) are coupled, the first pole of the eighth transistor M8 is configured to be coupled to the first clock signal terminal CK1, and the second pole of the eighth transistor M8 is coupled to the signal output terminal OP .
  • the first terminal of the second capacitor C2 is coupled to the second terminal of the first transistor M1 (ie, the first pull-up node PU_1), and the second terminal of the second capacitor C2 is coupled to the signal output terminal OP.
  • the eighth transistor M8 when the eighth transistor M8 is in the conducting state under the control of the signal of the second pole of the first transistor M1 (ie the first pull-up node PU_1), it can provide the signal of the first clock signal terminal CK1 to the signal output End OP.
  • the second capacitor C2 can store and stabilize the signal input to the second pole (ie, the first pull-up node PU_1) of the first transistor M1 and the signal input to the signal output terminal OP, as well as the first transistor M1.
  • the two poles ie, the first pull-up node PU_1 are in a floating state, the stability of the voltage difference between the first pull-up node PU_1 and the signal output terminal OP can be maintained.
  • the first electrode of the transistor can be used as its source and the second electrode can be used as its drain; or, the first electrode can be used as its drain and the second electrode can be used as its source. No specific distinction is made here.
  • the transistor mentioned in the above-mentioned embodiments of the present disclosure may be a TFT, or a Metal Oxide Semiconductor (MOS) field effect transistor (MOS), which is not limited herein.
  • MOS Metal Oxide Semiconductor
  • all transistors may be P-type transistors.
  • the P-type transistor is turned on when the voltage difference V gs between its gate and its source and its threshold voltage V th satisfy the relationship V gs ⁇ V th .
  • the first transistor M1 may be a P-type transistor, and the relationship between the voltage difference V gs1 between the gate and source of the first transistor M1 and its threshold voltage V th1 satisfies the formula: V gs1 ⁇ V th1 through.
  • the transistor is a P-type transistor as an example for description.
  • the transistor is an N-type transistor
  • the design principle is the same as that of the present disclosure, and it also falls within the protection scope of the present disclosure.
  • the N-type transistor is turned on when the voltage difference V gs between its gate and its source and its threshold voltage V th satisfy the relationship V gs >V th .
  • the first transistor M1 may be an N-type transistor, and the first transistor M1 is turned on when the voltage difference V gs1 between its gate and its source and its threshold voltage V th1 satisfy the formula: V gs1 >V th1 .
  • a gate insulating layer is arranged between the gate of the transistor and the active layer.
  • the thickness of the gate insulating layer can be adjusted to determine the dominant gate in the dual-gate transistor.
  • the thickness of the gate insulating layer can be adjusted so that the first gate of the first transistor is dominant, and the first transistor M1 is connected to its source (ie, the first gate).
  • V gs1 represents the voltage difference between the first gate and the source of the first transistor M1 as an example.
  • the first threshold regulating signal terminal is configured to receive a signal having at least the opposite level of the signal of the first reference signal terminal VREF1.
  • the signal of the first reference signal terminal VREF1 is a low-level signal
  • the signal of the second reference signal terminal VREF2 It is a high-level signal
  • the first threshold regulating signal terminal VS1 is configured to receive a signal with at least a high-level signal
  • the effective pulse signal of the input signal terminal IP when the effective pulse signal of the input signal terminal IP is a high-level signal, the signal of the first reference signal terminal VREF1 is a high-level signal, and the second reference signal terminal VREF2 The signal of is a low-level signal, and the first threshold regulating signal terminal VS1 is configured to receive a signal having at least a low-level signal.
  • the effective pulse signal of the input signal terminal IP refers to a low-level signal input to the second transistor M2 within a frame time to control the shift register to perform output work.
  • the P-type transistor is turned off under the action of a high-level signal, and turned on under the action of a low-level signal.
  • the N-type transistor is turned on under the action of a high-level signal, and cut off under the action of a low-level signal.
  • 1 represents a high-level signal
  • 0 represents a low-level signal
  • 1 and 0 are logic levels, which are only used to better explain the specific working process of the embodiments of the present disclosure. It is not the voltage applied to the gate of each transistor during implementation.
  • the four stages of the input phase T1, the output phase T2, the reset phase T3, and the reset hold phase T4 in the signal timing diagram shown in FIG. 5a are selected. It should be noted that the signal timing diagram shown in FIG. 5a is only the working process of a certain shift register in the current frame. The working process of the shift register in other frames is basically the same as the working process in the current frame, and will not be repeated here.
  • the turned-on fifth transistor M5 can provide the low-level signal of the first reference signal terminal VREF1 to the pull-down node PD, so that the signal of the pull-down node PD is a low-level signal to control the conduction of the fourth transistor M4 and the seventh transistor M7 through.
  • the turned-on seventh transistor M7 provides the high-level signal of the second reference signal terminal VREF2 to the signal output terminal OP, so that the signal output terminal OP outputs a high-level signal.
  • the turned-on second transistor M2 can provide the low-level signal of the input signal terminal IP to the second pull-up node PU_2, so that the signal of the second pull-up node PU_2 is a low-level signal.
  • the sixth transistor M6 is turned on under the control of the signal of the second pull-up node PU_2 to provide the low-level signal of the second clock signal terminal CK2 to the pull-down node PD, and further make the signal of the pull-down node PD a low-level signal .
  • the signal of the first pull-up node PU_1 is a high-level signal, so in the current frame, a pole of the first transistor M1 connected to the first pull-up node PU_1 serves as a source.
  • the turned-on first transistor M1 conducts the second pull-up node PU_2 and the first pull-up node PU_1, so that the signal of the first pull-up node PU_1 can be a low-level signal in time to control the eighth transistor M8 to turn on .
  • the turned-on eighth transistor M8 provides the high-level signal of the first clock signal terminal CK1 to the signal output terminal OP, so that the signal output terminal OP outputs a high-level signal.
  • the signal is a low-level signal to control the sixth transistor M6 to turn on.
  • the turned-on sixth transistor M6 provides the high-level signal of the second clock signal terminal CK2 to the pull-down node PD, so that the signal of the pull-down node PD is a high-level signal to control the fourth transistor M4 and the seventh transistor M7 to be turned off .
  • the eighth transistor M8 is turned on under the control of the signal of the first pull-up node PU_1 to provide the high-level signal of the first clock signal terminal CK1 to the signal output terminal OP, so that the signal output terminal OP outputs a high-level signal .
  • the second transistor M2 and the fifth transistor M5 are both turned off, and the first pull-up node PU_1 is maintained as a low-level signal under the action of the second capacitor C2 to control the eighth transistor M8 to be turned on, thereby
  • the low-level signal of the first clock signal terminal CK1 is provided to the signal output terminal OP, so that the signal output terminal OP outputs a low-level signal.
  • the level of the first pull-up node PU_1 is further pulled down to control the eighth transistor M8 to be fully turned on as much as possible to provide the low-level signal of the first clock signal terminal CK1 To the signal output terminal OP, the signal output terminal OP outputs a low-level signal.
  • the voltage of the low-level signal of the first pull-up node PU_1 may be lower than the voltage of the low-level signal of the second pull-up node PU_2. Therefore, at this stage Among them, one electrode of the first transistor M1 electrically connected to the second pull-up node PU_2 serves as its source.
  • the V th1 of the first transistor M1 can be shifted to the left, the gate voltage of the first transistor M1 is the voltage of the low-level signal, and the source voltage of the first transistor M1 is the voltage of the low-level signal, so
  • the first transistor M1 can not satisfy V gs1 ⁇ V th1 , so that the first transistor M1 is turned off, so that the level of the first pull-up node PU_1 can be kept stable, and the level of the first pull-up node PU_1 can be prevented from rising due to leakage. High causes the output of the signal output terminal OP to be unstable.
  • the signal of the pull-down node PD can be maintained as a high-level signal, thereby controlling both the fourth transistor M4 and the seventh transistor M7 to be turned off, so as to avoid adverse effects on the signal output by the signal output terminal OP.
  • the second transistor M2 and the fifth transistor M5 are both turned on.
  • the turned-on second transistor M2 can provide the high-level signal of the input signal terminal IP to the second pull-up node PU_2, so that the signal of the second pull-up node PU_2 is a high-level signal to control the sixth transistor M6 to turn off.
  • the first transistor M1 is electrically connected to the second pull-up node PU_2 as its source, and the first transistor M1 is turned on when V gs1 ⁇ V th1 is satisfied, so that the second pull-up node PU_2 and the second pull-up node PU_2 are turned on.
  • a pull-up node PU_1 is turned on to control the eighth transistor M8 to turn off.
  • the turned-on seventh transistor M7 provides the high-level signal of the second reference signal terminal VREF2 to the signal output terminal OP, so that the signal output terminal OP outputs a high-level signal.
  • the first transistor M1 is electrically connected to the second pull-up node PU_2 as its source, and the first transistor M1 is turned on when V gs1 ⁇ V th1 is satisfied, so that the second pull-up node PU_2 and the second pull-up node PU_2 are turned on.
  • a pull-up node PU_1 is turned on to control the eighth transistor M8 to turn off.
  • the turned-on seventh transistor M7 provides the high-level signal of the second reference signal terminal VREF2 to the signal output terminal OP, so that the signal output terminal OP outputs a high-level signal.
  • the buffering stage there are buffer stages between the input stage T1 and the output stage T2, between the output stage T2 and the reset stage T3, and between the reset stage T3 and the reset holding stage T4.
  • the characteristics of the transistors in the shift register can be stabilized to enter the next working stage after stabilization, and this can also avoid the rising edge of the signal at the first clock signal terminal CK1 and the second clock signal
  • the falling edge of the signal at the terminal CK2 is aligned, and the falling edge of the signal at the first clock signal terminal CK1 is prevented from being aligned with the rising edge of the signal at the second clock signal terminal CK2, thereby improving the stability of the shift register.
  • the embodiment of the present disclosure also provides other signal timing diagrams of the shift register, as shown in FIG. 5b, which is modified for the implementation shown in FIG. 5a.
  • FIG. 5b which is modified for the implementation shown in FIG. 5a.
  • the following only describes the differences between this embodiment and the embodiment of the shift register shown in FIG. 4a, and the similarities are not repeated here.
  • the first threshold regulating signal terminal VS1 adopts the same signal as the input signal terminal IP.
  • the first threshold control signal terminal VS1 and the input signal terminal IP can be input into the shift register using different signal lines.
  • the same signal line may be used to input the first threshold value control signal terminal VS1 and the input signal terminal IP into the shift register, thereby reducing the number of signal lines.
  • the turned-on fifth transistor M5 can provide the low-level signal of the first reference signal terminal VREF1 to the pull-down node PD, so that the signal of the pull-down node PD is a low-level signal to control the conduction of the fourth transistor M4 and the seventh transistor M7 through.
  • the turned-on seventh transistor M7 provides the high-level signal of the second reference signal terminal VREF2 to the signal output terminal OP, so that the signal output terminal OP outputs a high-level signal.
  • the turned-on second transistor M2 can provide the low-level signal of the input signal terminal IP to the second pull-up node PU_2, so that the signal of the second pull-up node PU_2 is a low-level signal.
  • the sixth transistor M6 is turned on under the control of the signal of the second pull-up node PU_2 to provide the low-level signal of the second clock signal terminal CK2 to the pull-down node PD, and further make the signal of the pull-down node PD a low-level signal .
  • the signal of the first pull-up node PU_1 is a high-level signal, so in the current frame, a pole of the first transistor M1 connected to the first pull-up node PU_1 serves as a source.
  • the turned-on first transistor M1 conducts the second pull-up node PU_2 and the first pull-up node PU_1, so that the signal of the first pull-up node PU_1 can be a low-level signal in time to control the eighth transistor M8 to turn on .
  • the turned-on eighth transistor M8 provides the high-level signal of the first clock signal terminal CK1 to the signal output terminal OP, so that the signal output terminal OP outputs a high-level signal.
  • the turned-on sixth transistor M6 provides the high-level signal of the second clock signal terminal CK2 to the pull-down node PD, so that the signal of the pull-down node PD is a high-level signal to control the fourth transistor M4 and the seventh transistor M7 to be turned off .
  • the eighth transistor M8 is turned on under the control of the signal of the first pull-up node PU_1 to provide the high-level signal of the first clock signal terminal CK1 to the signal output terminal OP, so that the signal output terminal OP outputs a high-level signal .
  • the second transistor M2 and the fifth transistor M5 are both turned off, and the first pull-up node PU_1 is maintained as a low-level signal under the action of the second capacitor C2 to control the eighth transistor M8 to be turned on, thereby
  • the low-level signal of the first clock signal terminal CK1 is provided to the signal output terminal OP, so that the signal output terminal OP outputs a low-level signal.
  • the level of the first pull-up node PU_1 is further pulled down to control the eighth transistor M8 to be fully turned on as much as possible to provide the low-level signal of the first clock signal terminal CK1 To the signal output terminal OP, the signal output terminal OP outputs a low-level signal.
  • the voltage of the low-level signal of the first pull-up node PU_1 may be lower than the voltage of the low-level signal of the second pull-up node PU_2. Therefore, at this stage Among them, one electrode of the first transistor M1 electrically connected to the second pull-up node PU_2 serves as its source.
  • the V th1 of the first transistor M1 can be shifted to the left, and the gate of the first transistor M1 is the voltage of the low-level signal, and the source voltage of the first transistor M1 is the voltage of the low-level signal, so
  • the first transistor M1 can not satisfy V gs1 ⁇ V th1 , so that the first transistor M1 is turned off as much as possible, so that the level of the first pull-up node PU_1 can be kept stable, and the electric leakage of the first pull-up node PU_1 can be avoided.
  • a situation in which the output of the signal output terminal OP is unstable due to a flat rise.
  • the signal of the pull-down node PD can be maintained as a high-level signal, thereby controlling both the fourth transistor M4 and the seventh transistor M7 to be turned off, so as to avoid adverse effects on the signal output by the signal output terminal OP.
  • the second transistor M2 and the fifth transistor M5 are both turned on.
  • the turned-on second transistor M2 can provide the high-level signal of the input signal terminal IP to the second pull-up node PU_2, so that the signal of the second pull-up node PU_2 is a high-level signal to control the sixth transistor M6 to turn off.
  • the gate of the first transistor M1 is a low-level signal voltage
  • the source voltage of the first transistor M1 is a high-level signal voltage
  • the turned-on fifth transistor M5 provides the low-level signal of the first reference signal terminal VREF1 to the pull-down node PD, so that the signal of the pull-down node PD is a low-level signal to control the fourth transistor M4 and the seventh transistor M7 to conduct through.
  • CK1 1
  • the third transistor M3 is turned off.
  • the turned-on seventh transistor M7 provides the high-level signal of the second reference signal terminal VREF2 to the signal output terminal OP, so that the signal output terminal OP outputs a high-level signal.
  • one pole of the first transistor M1 electrically connected to the second pull-up node PU_2 serves as its source.
  • the V th1 of the first transistor M1 can be shifted to the left.
  • the gate of the first transistor M1 is a low-level signal voltage
  • the source voltage of the first transistor M1 is a high-level signal voltage, so that the first transistor M1 can be turned on when V gs1 ⁇ V th1 is satisfied, so that The second pull-up node PU_2 and the first pull-up node PU_1 are turned on to control the eighth transistor M8 to turn off.
  • the turned-on seventh transistor M7 provides the high-level signal of the second reference signal terminal VREF2 to the signal output terminal OP, so that the signal output terminal OP outputs a high-level signal.
  • the embodiments of the present disclosure provide other shift registers, as shown in FIG. 4b, which are modified from the implementation shown in FIG. 4a. The following only describes the differences between this embodiment and the embodiment of the shift register shown in FIG. 4a, and the similarities are not repeated here.
  • the second gate of the first transistor M1 can be coupled to the first electrode of the second transistor M2 to further reduce the space occupied by the signal line.
  • the signal timing diagram corresponding to the shift register shown in FIG. 4b is shown in FIG. 5b, and the working process of the shift register shown in FIG. 4b can be referred to the signal timing of the shift register shown in FIG. 4a in FIG. 5b. The working process under the figure will not be repeated here.
  • the second gate of the first transistor M1 may be coupled to the gate of the second transistor M2 to further reduce the space occupied by the signal line, which is not limited here. .
  • the signal output from the signal output terminal OP of the shift register shown in FIG. 4b is simulated according to the signal timing diagram shown in FIG. 5b, and the simulation diagram is shown in FIG. 6.
  • the abscissa represents time
  • the ordinate represents voltage.
  • the signal output terminal OP can output a signal stably, thereby avoiding the problem of instability caused by the leakage of the first pull-up node PU_1.
  • the embodiments of the present disclosure provide other shift registers, as shown in FIG. 7, which are modified from the embodiment shown in FIG. 4a. The following only describes the differences between this embodiment and the embodiment of the shift register shown in FIG. 4a, and the similarities are not repeated here.
  • the input circuit 10 may also include: a double-gate second transistor M2; wherein, the first gate of the second transistor M2 is configured to The two clock signal terminals CK2 are coupled, the second gate of the second transistor M2 is configured to be coupled to the second threshold adjustment signal terminal VS2, and the first pole of the second transistor M2 is configured to be coupled to the input signal terminal IP, The second pole of the second transistor M2 is coupled to the first pole of the first transistor M1 (ie, the second pull-up node PU_2).
  • the second threshold control signal terminal VS2 is configured to receive at least a signal having a level opposite to that of the first reference signal terminal VREF1.
  • part of the signal of the second threshold control signal terminal VS2 may be opposite to the level of the signal of the first reference signal terminal VREF1, and the remaining part of the signal of the second threshold control signal terminal VS2 may be the same as the first reference signal terminal VS2.
  • the signal levels of the reference signal terminal VREF1 are the same.
  • the thickness of the gate insulating layer can be adjusted to make the first gate of the second transistor dominate, and the second transistor M2 is at its gate (ie, the first gate
  • V gs2 represents the voltage difference between the first gate and the source of the second transistor M2 as an example.
  • the pull-up control circuit 30 may also include: a third transistor M3 and a double-gate fourth transistor M4; wherein the gate of the third transistor M3 Is configured to be coupled to the first clock signal terminal CK1, the first pole of the third transistor M2 is coupled to the first pole of the first transistor M1 (ie the second pull-up node PU_2), and the second pole of the third transistor M3 It is coupled to the first pole of the fourth transistor M4.
  • the first gate of the fourth transistor M4 is coupled to the gate of the seventh transistor M7 (ie the pull-down node PD), the second gate of the fourth transistor M4 is configured to be coupled to the third threshold control signal terminal VS3, The second pole of the four-transistor M4 is configured to be coupled to the second reference signal terminal VREF2.
  • the third threshold control signal terminal VS3 is configured to receive at least a signal having a level opposite to that of the first reference signal terminal VREF1.
  • part of the signal of the third threshold control signal terminal VS3 may be opposite to the level of the first reference signal terminal VREF1
  • the remaining part of the signal of the third threshold control signal terminal VS3 may be the same as the first reference signal terminal VS3.
  • the level of the terminal VREF1 is the same.
  • the thickness of the gate insulating layer can be adjusted so that the first gate of the fourth transistor is dominant, and the fourth transistor M4 is at its gate (ie, the first gate When the relationship between the voltage difference between V gs4 and its source V gs4 and its threshold voltage V th4 satisfies the formula V gs4 ⁇ V th4 , it is turned on.
  • V gs4 represents the voltage difference between the first gate and the source of the fourth transistor M4 as an example.
  • the four stages of the input phase T1, the output phase T2, the reset phase T3, and the reset hold phase T4 in the signal timing diagram shown in FIG. 8 are selected.
  • the turned-on seventh transistor M7 provides the high-level signal of the second reference signal terminal VREF2 to the signal output terminal OP, so that the signal output terminal OP outputs a high-level signal.
  • the threshold voltage V th2 of the second transistor M2 can be shifted to the right, so that the second transistor M2 is completely turned on as much as possible, so as to accelerate the supply of the low-level signal of the input signal terminal IP to During the charging process of the second pull-up node PU_2, the signal of the second pull-up node PU_2 becomes a low-level signal as quickly as possible.
  • the sixth transistor M6 is turned on under the control of the signal of the second pull-up node PU_2 to provide the low-level signal of the second clock signal terminal CK2 to the pull-down node PD, and further make the signal of the pull-down node PD a low-level signal .
  • the V th1 of the first transistor M1 can be shifted to the right, so that the first transistor M1 satisfies V gs1 ⁇ V th1 , so that the first transistor M1 is completely turned on as much as possible.
  • the turned-on first transistor M1 conducts the second pull-up node PU_2 and the first pull-up node PU_1, so that the signal of the first pull-up node PU_1 can be a low-level signal in time to control the eighth transistor M8 to turn on .
  • the turned-on eighth transistor M8 provides the high-level signal of the first clock signal terminal CK1 to the signal output terminal OP, so that the signal output terminal OP outputs a high-level signal.
  • the signal of the second pull-up node PU_2 can be a low-level signal to control the conduction of the sixth transistor M6.
  • the turned-on sixth transistor M6 provides the high-level signal of the second clock signal terminal CK2 to the pull-down node PD, so that the signal of the pull-down node PD is a high-level signal to control the fourth transistor M4 and the seventh transistor M7 to be turned off .
  • the eighth transistor M8 is turned on under the control of the signal of the first pull-up node PU_1 to provide the high-level signal of the first clock signal terminal CK1 to the signal output terminal OP, so that the signal output terminal OP outputs a high-level signal .
  • the first pull-up node PU_1 is maintained as a low-level signal under the action of the second capacitor C2 to control the conduction of the eighth transistor M8, so as to provide the low-level signal of the first clock signal terminal CK1 to the signal output terminal OP,
  • the signal output terminal OP outputs a low-level signal. Due to the function of the second capacitor C2, the level of the first pull-up node PU_1 is further pulled down to control the eighth transistor M8 to be fully turned on as much as possible, so as to provide the low-level signal of the first clock signal terminal CK1 to The signal output terminal OP makes the signal output terminal OP output a low-level signal.
  • the voltage of the low-level signal of the first pull-up node PU_1 may be lower than the voltage of the low-level signal of the second pull-up node PU_2, therefore, In this stage, one electrode of the first transistor M1 electrically connected to the second pull-up node PU_2 serves as its source.
  • the V th1 of the first transistor M1 can be shifted to the left, and the gate of the first transistor M1 is the voltage of the low-level signal, and the source voltage of the first transistor M1 is the voltage of the low-level signal, so
  • the first transistor M1 can not satisfy V gs1 ⁇ V th1 , so that the first transistor M1 is turned off, so that the level of the first pull-up node PU_1 can be kept stable, and the level of the first pull-up node PU_1 can be prevented from rising due to leakage. High, which results in unstable output of the signal output terminal OP.
  • the threshold voltage of the second transistor M2 can be shifted to the left, and the second transistor M2 can be turned off as much as possible to avoid the leakage of the second transistor M2 on the second pull-up node PU_2. Leakage affects the holding time of the low-level signal of the second pull-up node PU_2.
  • the threshold voltage of the fourth transistor M4 can be shifted to the left, so that the fourth transistor M4 is completely cut off as much as possible to avoid leakage of the fourth transistor M4 As for the leakage of the second pull-up node PU_2, the holding time of the low-level signal of the second pull-up node PU_2 is extended.
  • the sixth transistor M6 provides the high-level signal of the second clock signal terminal CK2 to the pull-down node PD under the control of the signal of the second pull-up node PU_2, so as to control the seventh transistor M7 to turn off and avoid output to the signal output terminal OP. The signal is adversely affected.
  • the second transistor M2 and the fifth transistor M5 are both turned on.
  • the turned-on second transistor M2 can provide the high-level signal of the input signal terminal IP to the second pull-up node PU_2, so that the signal of the second pull-up node PU_2 is a high-level signal to control the sixth transistor M6 to turn off.
  • the gate of the first transistor M1 is a low-level signal voltage
  • the source voltage of the first transistor M1 is a high-level signal voltage
  • the first transistor M1 can be turned on when V gs1 ⁇ V th1 is satisfied, so that The second pull-up node PU_2 and the first pull-up node PU_1 are turned on to control the eighth transistor M8 to turn off.
  • the turned-on fifth transistor M5 provides the low-level signal of the first reference signal terminal VREF1 to the pull-down node PD, so that the signal of the pull-down node PD is a low-level signal to control the seventh transistor M7 to turn on.
  • the second transistor M2 and the fifth transistor M5 are both turned off, and the signal of the pull-down node PD can be maintained as a low-level signal due to the function of the first capacitor C1, and the seventh transistor M7 is controlled to be turned on to turn on
  • the high-level signal of the second reference signal terminal VREF2 is provided to the signal output terminal OP, so that the signal output terminal OP outputs a high-level signal.
  • the turned-on third transistor M3 and the fourth transistor M4 can timely provide the high-level signal of the second reference signal terminal VREF2 to the second pull-up node PU_2, and timely control the signal of the second pull-up node PU_2 to be high ,
  • the sixth transistor M6 is controlled to be turned off.
  • one pole of the first transistor M1 electrically connected to the second pull-up node PU_2 serves as its source.
  • VS1 1
  • the V th1 of the first transistor M1 can be shifted to the left.
  • the gate of the first transistor M1 is a low-level signal voltage
  • the source voltage of the first transistor M1 is a high-level signal voltage, so that the first transistor M1 can be turned on when V gs1 ⁇ V th1 is satisfied, so that The second pull-up node PU_2 and the first pull-up node PU_1 are turned on to control the eighth transistor M8 to turn off.
  • the embodiments of the present disclosure provide further shift registers, as shown in FIG. 9a, which are modified from the implementation shown in FIG. The following describes only the differences between this embodiment and the embodiment of the shift register shown in FIG. 7, and the similarities are not repeated here.
  • the second gate of the first transistor M1 may be coupled to the first electrode of the second transistor M2.
  • the first threshold regulating signal terminal and the input signal terminal can be set to receive the same signal, that is, the second gate of the first transistor M1 receives the signal of the input signal terminal IP, so as to further reduce the space occupied by the signal line.
  • the same signal line can be used to input signals to the first threshold control signal terminal and the input signal terminal.
  • the second gate of the second transistor M2 may be coupled to the first electrode of the second transistor M2.
  • the second threshold regulating signal terminal and the input signal terminal can be set to receive the same signal, that is, the second gate of the second transistor M2 receives the signal of the input signal terminal IP, so as to further reduce the space occupied by the signal line.
  • the same signal line can be used to input signals to the second threshold control signal terminal and the input signal terminal.
  • the first threshold regulating signal terminal and the second threshold regulating signal terminal may be set to receive the same signal.
  • the second gate of the first transistor M1 can be coupled to the second gate of the second transistor M2 to both receive the signal of the input signal terminal IP.
  • the signals of the third threshold control signal terminal and the pull-down node can be set to the same signal.
  • the second gate of the fourth transistor M4 can be coupled to the gate of the seventh transistor M7 (ie, the pull-down node PD).
  • the working process of the shift register shown in Fig. 9a can be referred to the working process of the shift register shown in Fig. 7, which will not be repeated here.
  • the signal output by the signal output terminal OP of the shift register shown in FIG. 9a and the signal of the first pull-up node PU_1 are also simulated, as shown in FIG. 9b and FIG. 9c.
  • the abscissa represents time
  • the ordinate represents voltage.
  • 9a to 9c, in the output stage T2 the signal output terminal OP can output a signal stably, thereby avoiding the problem of instability caused by the leakage of the first pull-up node PU_1.
  • the embodiments of the present disclosure provide further signal timing diagrams of shift registers, as shown in FIG. 10a and FIG. 10b, which are modified from the embodiment shown in FIG. 8. The following only describes the differences between this embodiment and the embodiment of the shift register shown in FIG. 8, and the similarities are not repeated here.
  • the first threshold value regulating signal terminal VS1 may be configured as a clock signal.
  • the second threshold value regulating signal terminal VS2 may be configured as a clock signal.
  • the third threshold value regulating signal terminal VS3 may be configured as a clock signal.
  • the first threshold value regulating signal terminal VS1 and the second threshold value regulating signal terminal VS2 may be configured to receive The same signal.
  • the first threshold value regulating signal terminal VS1 and the third threshold value regulating signal terminal VS3 may be configured to receive The same signal.
  • the first threshold value regulating signal terminal VS1, the second threshold value regulating signal terminal VS2, and the third threshold value The control signal terminal VS3 is configured to receive the same signal. In this way, the same signal line can be used to input a clock signal to the first threshold value regulating signal terminal VS1, the second threshold value regulating signal terminal VS2 and the third threshold value regulating signal terminal VS3.
  • the working process of the shift register provided by the embodiment of the present disclosure will be described below in conjunction with the signal timing diagram shown in FIG. 10b. Specifically, the four stages of the input phase T1, the output phase T2, the reset phase T3, and the reset hold phase T4 in the signal timing diagram shown in FIG. 10b are selected.
  • the working process of this stage can be referred to the working process of the shift register in the output stage T2 shown in FIG. 7, which will not be repeated here.
  • the first transistor M1 can be turned on in time to provide the high-level signal of the second pull-up node PU_2 to the first pull-up node PU_1, To control the eighth transistor M8 to turn off.
  • the embodiments of the present disclosure provide further signal timing diagrams of shift registers, as shown in FIG. 10c, which are modified from the implementation shown in FIG. 8. The following only describes the differences between this embodiment and the embodiment of the shift register shown in FIG. 8, and the similarities are not repeated here.
  • the first threshold regulating signal terminal VS1 may be configured as a clock signal with the same timing as the second clock signal terminal CK2. In this way, the timing of the second clock signal terminal CK2 can be directly used to input the clock signal to the first threshold control signal terminal VS1.
  • the second threshold control signal terminal VS2 can be configured as a clock signal with the same timing as the second clock signal terminal CK2. In this way, the timing of the second clock signal terminal CK2 can be directly used to input the clock signal to the second threshold control signal terminal VS2.
  • the third threshold control signal terminal VS3 may be configured as a clock signal with the same timing as the second clock signal terminal CK2. In this way, the timing of the second clock signal terminal CK2 can be directly used to input the clock signal to the third threshold control signal terminal VS3.
  • the working process of the shift register shown in FIG. 8 under the signal timing diagram shown in FIG. 10c can be referred to the working process of the shift register shown in FIG. 8 under the signal timing diagram shown in FIG. 10b. I won't repeat them here.
  • the embodiments of the present disclosure provide further shift registers, as shown in FIG. 11, which are modified from the implementation shown in FIG. The following describes only the differences between this embodiment and the embodiment of the shift register shown in FIG. 7, and the similarities are not repeated here.
  • the first threshold regulating signal terminal and the second clock signal terminal can be set to the same clock signal.
  • the first threshold control signal terminal is the second clock signal terminal CK2.
  • the second gate of the first transistor M1 is coupled to the first gate of the second transistor M2, so that the second gate of the first transistor M1 receives the signal of the second clock signal terminal CK2. In this way, the same signal line can be used to input signals to the first threshold control signal terminal and the second clock signal terminal.
  • the second threshold control signal terminal and the second clock signal terminal can be set to the same clock signal.
  • the second threshold control signal terminal is the second clock signal terminal CK2.
  • the second gate of the second transistor M2 is coupled to the first gate of the second transistor M2, so that the second gate of the second transistor M2 receives the signal of the second clock signal terminal CK2. In this way, the same signal line can be used to input signals to the first threshold control signal terminal and the second clock signal terminal.
  • the third threshold control signal terminal and the second clock signal terminal can be set to the same clock signal.
  • the second gate of the fourth transistor M4 is coupled to the gate of the fifth transistor M5.
  • the second gate of the fourth transistor M4 can also be coupled to the first gate of the second transistor M2. So that the second gate of the fourth transistor M4 receives the signal of the second clock signal terminal CK2. In this way, the same signal line can be used to input signals to the first threshold control signal terminal and the second clock signal terminal.
  • the working process after the input phase T1 and before the output phase T2 can also refer to the working process of the shift register shown in FIG. 7 after the input phase T1 and before the output phase T2, which will not be repeated here.
  • the first transistor M1 can be turned on in time, and the high-level signal of the second pull-up node PU_2 can be provided to the first upper
  • the node PU_1 is pulled to make the signal of the first pull-up node PU_1 a high level signal, and the eighth transistor M8 is controlled to be turned off in time.
  • the embodiments of the present disclosure provide further shift registers, as shown in FIG. 13, which are modified from the embodiment shown in FIG. 11.
  • the following describes only the differences between this embodiment and the embodiment of the shift register shown in FIG. 11, and the similarities are not repeated here.
  • the signals of the third threshold control signal terminal and the pull-down node may be the same signal.
  • the second gate of the fourth transistor M4 is coupled to the gate of the seventh transistor M7 (ie, the pull-down node PD).
  • the four phases of the input phase T1, the output phase T2, the reset phase T3, and the reset hold phase T4 in the signal timing diagram shown in FIG. 12 are selected.
  • the working process after the input phase T1 and before the output phase T2 can also refer to the working process of the shift register shown in FIG. 7 after the input phase T1 and before the output phase T2, which will not be repeated here.
  • the first transistor M1 can be turned on in time, and the high-level signal of the second pull-up node PU_2 can be provided to the first upper
  • the node PU_1 is pulled to make the signal of the first pull-up node PU_1 a high level signal, and the eighth transistor M8 is controlled to be turned off in time.
  • the embodiment of the present disclosure provides further shift registers, as shown in FIG. 14a, which are modified with respect to the implementation of the signal timing diagram shown in FIG. 8. The following only describes the differences between this embodiment and the signal timing diagram shown in FIG. 8, and the similarities are not repeated here.
  • the first threshold value regulating signal terminal VS1 may be set to receive a fixed voltage signal, for example, set to a DC fixed voltage signal with a first voltage value to ensure The first transistor M1 can be completely cut off as much as possible in the output phase T2, so as to reduce the influence of the leakage current on the leakage current of the first pull-up node PU_1.
  • the first transistor M1 is a P-type transistor
  • the first threshold adjustment signal terminal VS1 may be set to receive a high-level fixed voltage signal.
  • the first voltage value can be set according to the actual application.
  • the first voltage value can be set to a high voltage to reduce leakage and ensure the stability of the output of the shift register, so that the shift register will not work abnormally.
  • the first voltage value can be set to 0V or negative voltage to ensure the response of the shift register speed.
  • the above-mentioned first voltage value can be designed and determined according to the actual application environment, which is not limited here.
  • the first threshold adjustment signal terminal VS1 may be set to receive a low-level fixed voltage signal. Further, when the display device adopts different refresh frequencies, the first voltage value can be set according to actual applications, which is not limited here.
  • the second threshold value regulating signal terminal VS2 may also be set to receive a fixed voltage signal, for example, set to a DC fixed voltage signal with a second voltage value to ensure that the second transistor M2 can In the output stage T2, it can be completely cut off as much as possible to reduce the leakage impact of the leakage current on the second pull-up node PU_2.
  • the second transistor M2 is a P-type transistor
  • the second threshold adjustment signal terminal VS2 can be set to receive a high-level fixed voltage signal.
  • the second voltage value can be set according to the actual application.
  • the second voltage value can be set to a high voltage to reduce leakage and ensure the stability of the output of the shift register, so that the shift register will not work abnormally.
  • the second voltage value can be set to 0V or negative voltage to ensure the response of the shift register speed.
  • the above-mentioned second voltage value can be designed and determined according to the actual application environment, which is not limited here.
  • the second threshold adjustment signal terminal VS2 can be set to receive a low-level fixed voltage signal.
  • the second voltage value can be set according to actual applications, which is not limited here.
  • the third threshold control signal terminal VS3 may also be set to receive a fixed voltage signal, for example, set to a DC fixed voltage signal with a third voltage value to ensure that the fourth transistor M4 can In the output stage T2, it can be completely cut off as much as possible to reduce the leakage impact of the leakage current on the second pull-up node PU_2.
  • the fourth transistor M4 is a P-type transistor
  • the third threshold adjustment signal terminal VS3 can be set to receive a high-level fixed voltage signal.
  • the third voltage value can be set according to the actual application.
  • the third voltage value can be set to a high voltage to reduce leakage and ensure the stability of the output of the shift register, so that the shift register will not work abnormally.
  • the third voltage value can be set to 0V or negative voltage to ensure the response of the shift register speed.
  • the above-mentioned third voltage value can be designed and determined according to the actual application environment, which is not limited here.
  • the third threshold adjustment signal terminal VS3 can be set to receive a low-level fixed voltage signal. Further, when the display device adopts different refresh frequencies, the third voltage value can be set according to actual applications, which is not limited here.
  • the second threshold value regulating signal terminal VS2 and the first threshold value regulating signal terminal VS1 may be set to receive the same signal.
  • the second gate of the first transistor M1 is coupled to the second gate of the second transistor M2 so as to both receive the signal of the first threshold adjustment signal terminal VS1, so as to use a signal line to the first The second gate of the transistor M1 and the second gate of the second transistor M2 input signals.
  • the third threshold value regulating signal terminal VS3 and the first threshold value regulating signal terminal VS1 may also be set to receive the same signal.
  • the second gate of the first transistor M1 is coupled to the second gate of the fourth transistor M4 so as to both receive the signal of the first threshold adjustment signal terminal VS1, so as to use a signal line to the first The second gate of the transistor M1 and the second gate of the fourth transistor M4 input signals.
  • the third threshold regulating signal terminal VS3, the second threshold regulating signal terminal VS2, and the first threshold regulating signal terminal VS1 can also be set to receive the same signal.
  • the second gate of the first transistor M1, the second gate of the second transistor M2, and the second gate of the fourth transistor M4 are coupled so as to all receive the signal of the first threshold control signal terminal VS1.
  • one signal line is used to input signals to the second gate of the first transistor M1, the second gate of the second transistor M2, and the second gate of the fourth transistor M4.
  • the turned-on seventh transistor M7 provides the high-level signal of the second reference signal terminal VREF2 to the signal output terminal OP, so that the signal output terminal OP outputs a high-level signal.
  • the signal of the pull-up node PU_2 is a low-level signal.
  • the first reference signal VREF is a low-level signal and the signal of the first pull-up node PU_1 is a high-level signal
  • the first transistor M1 satisfies V gs1 ⁇ V th1 , so that the first transistor M1 is turned on.
  • the working process at this stage can be referred to the working process in the input stage T1 in FIG. 8, which is not repeated here.
  • the working process after the input phase T1 and before the output phase T2 can also be referred to the working process after the input phase T1 and before the output phase T2 in FIG. 88, which will not be repeated here.
  • the working process at this stage can be referred to the working process in the output stage T2 in FIG. 8, which is not repeated here.
  • the embodiments of the present disclosure also provide the above-mentioned driving method of the shift register, which, as shown in FIG. 15, may include:
  • the input circuit controls the signal level of the first pole of the first transistor according to the signals from the input signal terminal and the second clock signal terminal; the first transistor is turned on; the output circuit responds to the second pole of the first transistor The signal of the first clock signal terminal is provided to the signal output terminal;
  • the threshold voltage of the first transistor moves in response to the signal at the first threshold regulation signal terminal, and the first transistor is turned off; the output circuit responds to the signal at the second pole of the first transistor to provide the signal at the first clock signal terminal To the signal output terminal; wherein the level of the signal at the first threshold regulation signal terminal is opposite to the signal at the first reference signal terminal.
  • the threshold voltage of the second transistor moves in response to the signal from the second threshold regulating signal terminal, and the second transistor is turned off; the threshold voltage of the fourth transistor is in response to the third threshold.
  • the signal at the control signal terminal moves, and the fourth transistor is turned off.
  • the S100 input stage may further include: the fifth transistor responds to the signal of the second clock signal terminal and provides the signal of the first reference signal terminal to the seventh transistor
  • the sixth transistor responds to the signal of the first pole of the first transistor and provides the signal of the second clock signal terminal to the gate of the seventh transistor
  • the seventh transistor responds to the signal of the gate of the seventh transistor to The signal from the two reference signal terminals is provided to the signal output terminal.
  • the driving method may further include:
  • the input circuit controls the signal level of the first pole of the first transistor according to the signals of the input signal terminal and the second clock signal terminal; the first transistor turns on the input circuit and the output circuit; the fifth transistor responds to The signal of the second clock signal terminal provides the signal of the first reference signal terminal to the gate of the seventh transistor; the seventh transistor provides the signal of the second reference signal terminal to the signal output terminal in response to the signal of the gate of the seventh transistor.
  • the driving method may further include:
  • the first capacitor holds the signal of the gate of the seventh transistor; the seventh transistor provides the signal of the second reference signal terminal to the signal output terminal in response to the signal of its gate; the pull-up control circuit responds to the first clock The signal from the signal terminal and the gate of the seventh transistor provides the signal from the second reference signal terminal to the second pull-up node.
  • the driving principle and specific implementation of the driving method are the same as the principles and implementations of the shift register in the foregoing embodiment. Therefore, the driving method can be implemented with reference to the specific implementation of the shift register in the foregoing embodiment. Repeat it again.
  • embodiments of the present disclosure also provide a gate driving circuit, as shown in FIG. 16, including any of the above-mentioned shift registers SR(1), SR(2)... SR(n-1), SR(n)...SR(N-1), SR(N) (a total of N shift registers, 1 ⁇ n ⁇ N); among them, the first stage shift register SR(1)
  • the input signal terminal IP of is configured to be coupled to the frame trigger signal terminal STV;
  • the input signal terminal IP of the next stage shift register SR(n) is configured to be coupled to the signal output terminal OP of the previous stage shift register SR(n-1).
  • each shift register in the above-mentioned gate driving circuit is the same in function and structure as the above-mentioned shift register of the present disclosure, and the repetition is not repeated here.
  • the gate driving circuit may be configured in a liquid crystal display panel, or may be configured in an electroluminescent display panel, which is not limited here.
  • the first reference signal terminal VREF1 of the shift register SR(n) of each stage is coupled to the same DC signal terminal vdd, and each The second reference signal terminals VREF2 of the stage shift register SR(n) are both coupled to the same DC signal terminal vss.
  • the first clock signal terminal CK1 of the 2k-1 stage shift register and the second clock signal of the 2k stage shift register are both coupled to the same clock terminal, that is, the first clock terminal ck1; the second clock signal terminal CK2 of the 2k-1 stage shift register and the first clock signal terminal CK1 of the 2k stage shift register are both connected to the same clock terminal That is, the second clock terminal ck2 is coupled; where k is a positive integer.
  • the first threshold control signal terminal when configured to receive a clock signal with the same timing as the second clock signal terminal signal, the first threshold control signal terminal of the 2k-1 stage shift register and the 2k stage shift
  • the first threshold control signal terminal of the register is coupled to the same clock terminal, that is, the third clock terminal ck3; the first threshold control signal terminal of the 2k-1 stage shift register and the first threshold control signal of the 2k stage shift register
  • Both terminals are coupled to the same clock terminal, that is, the fourth clock terminal ck4.
  • the third threshold control signal terminal when configured to receive a clock signal with the same timing as the second clock signal terminal signal, the third threshold control signal terminal of the 2k-1 stage shift register and the 2k stage shift
  • the third threshold control signal terminal of the register is all coupled to the same clock terminal, that is, the fifth clock terminal ck5; the third threshold control signal terminal of the 2k-1 stage shift register and the third threshold control signal of the 2k stage shift register
  • Both terminals are coupled to the same clock terminal, that is, the sixth clock terminal ck6.
  • embodiments of the present disclosure also provide a display device, including the above-mentioned gate driving circuit provided by the embodiments of the present disclosure.
  • the principle of the display device to solve the problem is similar to that of the aforementioned shift register. Therefore, the implementation of the display device can refer to the aforementioned implementation of the shift register, and the repetition is not repeated here.
  • the above-mentioned display device provided by the embodiment of the present disclosure may be a mobile phone as shown in FIG. 17.
  • the above-mentioned display device provided by the embodiment of the present disclosure may also be any product or component with display function, such as a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.
  • the other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.
  • the shift register, the driving method, the gate driving circuit, and the display device provided by the embodiments of the present disclosure are provided by configuring the first transistor as a double-gate transistor, wherein the first gate of the first transistor receives the first reference signal terminal , The second gate of the first transistor receives the first threshold adjustment signal terminal, which can make the first transistor conduct during the input phase, the reset phase, and the reset hold phase.
  • the signal value of the regulation signal terminal of the first threshold regulation threshold voltage V th1 of the first transistor, the threshold voltage V th1 of the first transistor is moved, so that the first transistor is turned off in the output stage as much as possible .
  • the signal level of the first pull-up node can be kept stable, and the influence of leakage on the signal of the first pull-up node can be avoided. Therefore, the stability of the signal output by the signal output terminal is improved, which is beneficial to be applied to a display device driven by low frequency, and is beneficial to reduce power consumption.

Abstract

公开了一种移位寄存器、其驱动方法、栅极驱动电路及显示装置，包括：输入电路（10），被配置为分别与输入信号端（IP）以及第二时钟信号端(CK2)耦接；第一晶体管(M1)，第一晶体管(M1)的第一极与输入电路的输出端(PU2)耦接；且第一晶体管(M1)为双栅型晶体管；其中，第一晶体管(M1)的第一栅极被配置为与第一参考信号端(VREF1)耦接，第一晶体管(M1)的第二栅极被配置为与第一阈值调控信号端(VS1)耦接；输出电路，被配置为分别与第一时钟信号端(CK1)以及信号输出端(OP)耦接，且输出电路(OP)的控制端与第一晶体管(M1)的第二极耦接。

Description

移位寄存器、其驱动方法、栅极驱动电路及显示装置 技术领域
本公开涉及显示技术领域，特别涉及移位寄存器、其驱动方法、栅极驱动电路及显示装置。
背景技术
随着显示技术的飞速发展，显示装置越来越向着高集成度和低成本的方向发展。其中，GOA(Gate Driver on Array，阵列基板行驱动)技术将TFT(Thin Film Transistor，薄膜晶体管)栅极驱动电路集成在显示装置的阵列基板上以形成对显示装置的扫描驱动。其中，栅极驱动电路通常由多个级联的移位寄存器构成。然而，移位寄存器输出不稳定，会导致显示异常。
发明内容
本公开实施例提供的移位寄存器，包括：
输入电路，被配置为分别与输入信号端以及第二时钟信号端耦接；
第一晶体管，所述第一晶体管的第一极与所述输入电路的输出端耦接；且所述第一晶体管为双栅型晶体管；其中，所述第一晶体管的第一栅极被配置为与第一参考信号端耦接，所述第一晶体管的第二栅极被配置为与第一阈值调控信号端耦接；
输出电路，被配置为分别与第一时钟信号端以及信号输出端耦接，且所述输出电路的控制端与所述第一晶体管的第二极耦接。
可选地，在本公开实施例中，所述输入电路包括：单栅型的第二晶体管；
所述第二晶体管的栅极被配置为与所述第二时钟信号端耦接，所述第二晶体管的第一极被配置为与所述输入信号端耦接，所述第二晶体管的第二极与所述第一晶体管的第一极耦接。
可选地，在本公开实施例中，所述第一晶体管的第二栅极与所述第二晶 体管的栅极耦接；或者，
所述第一晶体管的第二栅极与所述第二晶体管的第一极耦接。
可选地，在本公开实施例中，所述输入电路包括：双栅型的第二晶体管；其中，所述第二晶体管的第一栅极被配置为与所述第二时钟信号端耦接，所述第二晶体管的第二栅极被配置为与第二阈值调控信号端耦接，所述第二晶体管的第一极被配置为与所述输入信号端耦接，所述第二晶体管的第二极与所述第一晶体管的第一极耦接。
可选地，在本公开实施例中，所述第二晶体管的第二栅极与所述第二晶体管的第一栅极耦接；或者，
所述第二晶体管的第二栅极与所述第二晶体管的第一极耦接。
可选地，在本公开实施例中，所述第一晶体管的第二栅极与所述第二晶体管的第一栅极耦接；或者，
所述第一晶体管的第二栅极与所述第二晶体管的第一极耦接。
可选地，在本公开实施例中，所述移位寄存器还包括：第五晶体管、第六晶体管、第七晶体管以及第一电容；
所述第五晶体管的栅极被配置为与所述第二时钟信号端耦接，所述第五晶体管的第一极被配置为与所述第一参考信号端耦接，所述第五晶体管的第二极与所述第七晶体管的栅极耦接；
所述第六晶体管的栅极与所述第一晶体管的第一极耦接，所述第六晶体管的第一极被配置为与所述第二时钟信号端耦接，所述第六晶体管的第二极与所述第七晶体管的栅极耦接；
所述第七晶体管的第一极被配置为与所述第二参考信号端耦接，所述第七晶体管的第二极与所述信号输出端耦接；
所述第一电容的第一端与所述第七晶体管的栅极耦接，所述第一电容的第二端被配置为与所述第二参考信号端耦接。
可选地，在本公开实施例中，所述移位寄存器还包括：上拉控制电路；其中，所述上拉控制电路的第一控制端被配置为与所述第一时钟信号端耦接， 所述上拉控制电路的第二控制端与所述第七晶体管的栅极耦接，所述上拉控制电路的输入端被配置为与所述第二参考信号端耦接，所述上拉控制电路的输出端与所述第一晶体管的第一极耦接。
可选地，在本公开实施例中，所述上拉控制电路包括：第三晶体管和单栅型的第四晶体管；
所述第三晶体管的栅极被配置为与所述第一时钟信号端耦接，所述第三晶体管的第一极与所述第一晶体管的第一极耦接，所述第三晶体管的第二极与所述第四晶体管的第一极耦接；
所述第四晶体管的栅极与所述第七晶体管的栅极耦接，所述第四晶体管的第二极被配置为与所述第二参考信号端耦接。
可选地，在本公开实施例中，所述上拉控制电路包括：第三晶体管和双栅型的第四晶体管；
所述第三晶体管的栅极被配置为与所述第一时钟信号端耦接，所述第三晶体管的第一极与所述第一晶体管的第一极耦接，所述第三晶体管的第二极与所述第四晶体管的第一极耦接；
所述第四晶体管的第一栅极与所述第七晶体管的栅极耦接，所述第四晶体管的第二栅极被配置为与第三阈值调控信号端耦接，所述第四晶体管的第二极被配置为与所述第二参考信号端耦接。
可选地，在本公开实施例中，所述第四晶体管的第二栅极与所述第七晶体管的栅极耦接；或者，
所述第四晶体管的第二栅极与所述第五晶体管的栅极耦接。
可选地，在本公开实施例中，所述输出电路包括：第八晶体管和第二电容；
所述第八晶体管的栅极与所述第一晶体管的第二极耦接，所述第八晶体管的第一极被配置为与所述第一时钟信号端耦接，所述第八晶体管的第二极与所述信号输出端耦接；
所述第二电容的第一端与所述第一晶体管的第二极耦接，所述第二电容 的第二端与所述信号输出端耦接。
可选地，在本公开实施例中，所述第一阈值调控信号端被配置为接收至少具有与所述第一参考信号端的信号的电平相反的信号；
第二阈值调控信号端被配置为接收至少具有与所述第一参考信号端的信号的电平相反的信号；
第三阈值调控信号端被配置为接收至少具有与所述第一参考信号端的信号的电平相反的信号。
可选地，在本公开实施例中，所述第一阈值调控信号端、第二阈值调控信号端以及第三阈值调控信号端中的至少一个信号端被配置为接收与所述第二时钟信号端的时序相同的时钟信号。
可选地，在本公开实施例中，所述第一阈值调控信号端、第二阈值调控信号端以及第三阈值调控信号端中的至少一个信号端被配置为接收固定电压信号。
相应地，本公开实施例还提供了栅极驱动电路，包括多个级联的上述移位寄存器；
第一极移位寄存器的输入信号端被配置为与帧触发信号端耦接；
每相邻两个移位寄存器中，下一级移位寄存器的输入信号端被配置为与上一级移位寄存器的信号输出端耦接。
相应地，本公开实施例还提供了显示装置，包括上述栅极驱动电路。
相应地，本公开实施例还提供了上述移位寄存器的驱动方法，包括：
输入阶段，所述输入电路根据所述输入信号端与所述第二时钟信号端的信号，控制所述第一晶体管的第一极的信号的电平；所述第一晶体管导通；所述输出电路响应于所述第一晶体管的第二极的信号，将第一时钟信号端的信号提供给信号输出端；
输出阶段，所述第一晶体管的阈值电压响应于所述第一阈值调控信号端的信号进行移动，所述第一晶体管截止；所述输出电路响应于所述第一晶体管的第二极的信号，将第一时钟信号端的信号提供给信号输出端；其中，所 述第一阈值调控信号端的信号与所述第一参考信号端的信号的电平相反。
可选地，在本公开实施例中，所述输入阶段还包括：第五晶体管响应于所述第二时钟信号端的信号，将所述第一参考信号端的信号提供给第七晶体管的栅极；第六晶体管响应于所述第一晶体管的第一极的信号，将所述第二时钟信号端的信号提供给所述第七晶体管的栅极；所述第七晶体管响应于所述第七晶体管的栅极的信号将第二参考信号端的信号提供给所述信号输出端；
在所述输出阶段之后，所述驱动方法还包括：
复位阶段，所述输入电路根据所述输入信号端与所述第二时钟信号端的信号，控制所述第一晶体管的第一极的信号的电平；所述第一晶体管将所述输入电路和所述输出电路导通；所述第五晶体管响应于所述第二时钟信号端的信号，将所述第一参考信号端的信号提供给第七晶体管的栅极；所述第七晶体管响应于所述第七晶体管的栅极的信号将第二参考信号端的信号提供给所述信号输出端。
可选地，在本公开实施例中，在所述输出阶段，第二晶体管的阈值电压响应于第二阈值调控信号端的信号进行移动，所述第二晶体管截止；第四晶体管的阈值电压响应于第三阈值调控信号端的信号进行移动，所述第四晶体管截止。
附图说明
图1为相关技术中的移位寄存器的结构示意图；
图2为图1所示的移位寄存器的信号时序图；
图3a为对应图1所示的移位寄存器的信号输出端的仿真模拟图；
图3b为对应图1所示的移位寄存器的第一上拉节点的仿真模拟图；
图4a为本公开实施例提供的移位寄存器的结构示意图之一；
图4b为本公开实施例提供的移位寄存器的结构示意图之二；
图5a为本公开实施例提供的信号时序图之一；
图5b为本公开实施例提供的信号时序图之二；
图6为对应图4b所示的移位寄存器的信号输出端的仿真模拟图；
图7为本公开实施例提供的移位寄存器的结构示意图之三；
图8为本公开实施例提供的信号时序图之三；
图9a为本公开实施例提供的移位寄存器的结构示意图之四；
图9b为对应图9a所示的移位寄存器的信号输出端的仿真模拟图；
图9c为对应图9a所示的移位寄存器的第一上拉节点的仿真模拟图；
图10a为本公开实施例提供的信号时序图之四；
图10b为本公开实施例提供的信号时序图之五；
图10c为本公开实施例提供的信号时序图之六；
图11为本公开实施例提供的移位寄存器的结构示意图之五；
图12为本公开实施例提供的信号时序图之七；
图13为本公开实施例提供的移位寄存器的结构示意图之六；
图14a为本公开实施例提供的移位寄存器的结构示意图之七；
图14b为本公开实施例提供的信号时序图之八；
图15为本公开实施例提供的驱动方法的流程图；
图16为本公开实施例提供的栅极驱动电路的结构示意图；
图17为本公开实施例提供的显示装置的结构示意图。
具体实施方式
为了使本公开的目的，技术方案和优点更加清楚，下面结合附图，对本公开实施例提供的移位寄存器、其驱动方法、栅极驱动电路及显示装置的具体实施方式进行详细地说明。应当理解，下面所描述的优选实施例仅是为了说明和解释本公开，并不是为了限定本公开。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
如图1所示，移位寄存器可以包括晶体管M01～M08以及电容C01～C02。 图1所示的移位寄存器对应的信号时序图，如图2所示。在输入阶段t1中，晶体管M02和晶体管M05在时钟信号端CK的信号的控制下导通。导通的晶体管M05将信号端VSS的低电平信号提供给下拉节点PD，使下拉节点PD的信号为低电平信号，以控制晶体管M04和晶体管M07导通，并且晶体管M03在时钟信号端CKB的信号的控制下截止。导通的晶体管M07将信号端VDD的高电平信号提供给信号输出端OP，使信号输出端OP输出高电平的信号。并且，导通的晶体管M02将输入信号端IP的低电平信号提供给第二上拉节点PU_2，使第二上拉节点PU_2的信号为低电平信号。晶体管M06在第二上拉节点PU_2的信号的控制下导通，以将时钟信号端CK的低电平信号提供给下拉节点PD。由于晶体管M01满足V gs01<V th01，使得晶体管M01导通；其中，此时晶体管M01与第一上拉节点PU_1连接的一极作为源极，V gs01代表晶体管M01的栅极与源极之间的电压差，V th01代表晶体管M01的阈值电压。导通的晶体管M01将第二上拉节点PU_2与第一上拉节点PU_1导通，从而使第一上拉节点PU_1的信号为低电平信号，以控制晶体管M08导通。导通的晶体管M08将时钟信号端CKB的高电平信号提供给信号输出端OP，使信号输出端OP输出高电平的信号。需要说明的是，在实际应用中，第一上拉节点PU_1的低电平信号的电压可以与信号端VSS的信号的电压相同，由于晶体管M01的阈值电压的原因，因此可以有第一上拉节点PU_1的低电平信号的电压小于第二上拉节点PU_2的低电平信号的电压。当然，具体电压可以根据实际应用环境来设计确定，在此不作限定。
在输入阶段t1之后，且在输出阶段t2之前，晶体管M02和晶体管M05在时钟信号端CK的高电平信号的控制下截止，晶体管M03在时钟信号端CKB的高电平信号的控制下也截止。则第一上拉节点PU_1在电容C01的作用下保持为低电平信号，一般电压较高的一极可以作为晶体管的源极，因此，此阶段中晶体管M01与第二上拉节点PU_2电连接的一极作为其源极，使得晶体管M01可以满足V gs01<V th01，因此晶体管M01导通，使得第二上拉节点PU_2的信号为低电平信号。晶体管M06在第二上拉节点PU_2的信号的控制 下导通，以将时钟信号端CKB的高电平信号提供给下拉节点PD，使下拉节点PD的信号为高电平信号，以控制晶体管M04和晶体管M07截止。晶体管M08在第一上拉节点PU_1的信号的控制下导通，以将时钟信号端CKB的高电平信号提供给信号输出端OP，使信号输出端OP输出高电平的信号。
在输出阶段t2中，晶体管M02和晶体管M05在时钟信号端CK高电平信号的控制下截止，第一上拉节点PU_1在电容C01的作用下保持为低电平信号，以控制晶体管M08导通，从而将时钟信号端CKB的低电平信号提供给信号输出端OP。由于电容C01的作用下，使第一上拉节点PU_1的电平进一步拉低，以控制晶体管M08可以尽可能完全导通，以将时钟信号端CKB的低电平信号提供给信号输出端OP，使信号输出端OP输出低电平的信号。
然而，在输出阶段t2中，由于晶体管M01长时间漏电积累，则导致被进一步下拉的第一上拉节点PU_1的电平出现漏电的情况，使第一上拉节点PU_1的电平上升，从而导致晶体管M08打开不完全，进而导致信号输出端OP输出的信号出现异常。尤其是在显示装置采用较低刷新频率(如1Hz)的驱动情况下，由于晶体管M01、M02和M04长时间漏电积累，使PU_2、PU_1电平均会上升，从而导致信号输出端OP输出的信号出现异常。
并且，还根据图2所示的信号时序图，对图1所示的移位寄存器的信号输出端OP输出的信号和第一上拉节点PU_1的信号进行仿真模拟，如图3a与图3b所示。图3a为图1所示的移位寄存器在图2所示的信号的控制下，信号输出端OP输出的信号的仿真模拟图。图3b为图1所示的移位寄存器在图2所示的信号的控制下，第一上拉节点PU_1的信号的仿真模拟图。其中，横坐标代表时间，纵坐标代表电压。结合图3a与图3b可知，在输出阶段t2中，第一上拉节点PU_1的电平出现漏电的情况，导致第一上拉节点PU_1的电平上升，从而导致信号输出端OP输出的信号的电平也出现上升情况，进而导致信号输出端OP输出的信号出现异常。并且，由于漏电的影响，使得上述移位寄存器不利于应被配置为低频(例如1Hz)驱动的显示装置中。
基于此，本公开实施例提供了一些移位寄存器，如图4a所示，可以包括：
输入电路10，被配置为分别与输入信号端IP以及第二时钟信号端CK2耦接；
第一晶体管M1，第一晶体管M1的第一极与输入电路10的输出端耦接；且第一晶体管M1为双栅型晶体管；其中，第一晶体管M1的第一栅极被配置为与第一参考信号端VREF1耦接，第一晶体管M1的第二栅极被配置为与第一阈值调控信号端VS1耦接；
输出电路20，被配置为分别与第一时钟信号端CK1以及信号输出端OP耦接，且输出电路20的控制端与第一晶体管M1的第二极耦接。
本公开实施例提供的移位寄存器，通过将第一晶体管设置为双栅型晶体管，其中，第一晶体管的第一栅极接收第一参考信号端，第一晶体管的第二栅极接收第一阈值调控信号端，可以使第一晶体管在输入阶段、复位阶段以及复位保持阶段导通。并且，可以至少在输出阶段中，通过第一阈值调控信号端的信号调控第一晶体管的阈值电压V th1，使第一晶体管的阈值电压V th1移动，以使第一晶体管在输出阶段尽可能的截止，可以保持第一上拉节点的信号的电平稳定，避免漏电对第一上拉节点的信号影响。从而提高信号输出端输出的信号的稳定性，进而有利于应用于低频驱动的显示装置中，有利于降低功耗。
在具体实施时，如图4a所示，第一上拉节点PU_1处于输出电路20的控制端与第一晶体管M1的第二极之间。第二上拉节点PU_2处于输入电路10的输出端与第一晶体管M1的第一极之间。需要说明的是，第一上拉节点PU_1和第二上拉节点PU_2是移位寄存器中的虚拟节点，这两个节点仅是为了方便对移位寄存器的结构和信号的传输进行描述，而针对移位寄存器的具体结构和信号的传输，可以根据移位寄存器中的各晶体管与电容之间的耦接方式来进行确定。
在具体实施时，在本公开实施例中，如图4a所示，输入电路10被配置为根据输入信号端IP与第二时钟信号端CK2，控制第二上拉节点PU_2的信号的电平。这样可以通过输入电路10将输入信号端IP的信号输入。输出电路 20，被配置为响应于第一上拉节点PU_1的信号将第一时钟信号端CK1的信号提供给信号输出端OP。这样可以通过输出电路20将第一时钟信号端CK1的信号输出。并且，第二上拉节点PU_2通过第一晶体管M1与第一上拉节点PU_1耦接。
在具体实施时，在本公开实施例中，如图4a所示，第一晶体管M1的第一极与第二上拉节点PU_2耦接，第一晶体管M1的第二极与第一上拉节点PU_1耦接。
具体地，在具体实施时，输入电路10可以包括：单栅型的第二晶体管M2；其中，第二晶体管M2的栅极被配置为与第二时钟信号端CK2耦接，第二晶体管M2的第一极被配置为与输入信号端IP耦接，第二晶体管M2的第二极与第一晶体管M1的第一极耦接，即第二晶体管M2的第二极与第二上拉节点PU_2耦接。进一步地，第二晶体管M2在第二时钟信号端CK2的信号的控制下处于导通状态时，可以将输入信号端IP的信号提供给第一晶体管M1的第一极(即第二上拉节点PU_2)，以控制第一晶体管M1的第一极(即第二上拉节点PU_2)的信号的电平。
在具体实施时，在本公开实施例中，如图4a所示，移位寄存器还可以包括：第五晶体管M5、第六晶体管M6、第七晶体管M7以及第一电容C1；
第五晶体管M5的栅极被配置为与第二时钟信号端CK2耦接，第五晶体管M5的第一极被配置为与第一参考信号端VREF1耦接，第五晶体管M5的第二极与第七晶体管M7的栅极(即下拉节点PD)耦接；
第六晶体管M6的栅极与第一晶体管M1的第一极(即第二上拉节点PU_2)耦接，第六晶体管M6的第一极被配置为与第二时钟信号端CK2耦接，第六晶体管M6的第二极与第七晶体管M7的栅极(即下拉节点PD)耦接；
第七晶体管M7的第一极被配置为与第二参考信号端VREF2耦接，第七晶体管M7的第二极与信号输出端OP耦接；
第一电容C1的第一端与第七晶体管M7的栅极(即下拉节点PD)耦接，第一电容C1的第二端被配置为与第二参考信号端VREF2耦接。
进一步地，第五晶体管M5在第二时钟信号端CK2的信号的控制下处于导通状态时，可以将第一参考信号端VREF1的信号提供给第七晶体管M7的栅极(即下拉节点PD)。第六晶体管M6在第一晶体管M1的第一极(即第二上拉节点PU_2)的信号的控制下处于导通状态时，可以将第二时钟信号端CK2的信号提供给第七晶体管M7的栅极(即下拉节点PD)。第七晶体管M7在其栅极(即下拉节点PD)的信号的控制下处于导通状态时，可以将第二参考信号端VREF2的信号提供给信号输出端OP耦接。第一电容C1可以将输入到第七晶体管M7的栅极(即下拉节点PD)的信号和第二参考信号端VREF2的信号进行存储，以及保持稳定。
在具体实施时，在本公开实施例中，如图4a所示，移位寄存器还可以包括：上拉控制电路30。其中，上拉控制电路30的第一控制端被配置为与第一时钟信号端CK1耦接，上拉控制电路30的第二控制端与第七晶体管M7的栅极耦接，上拉控制电路30的输入端被配置为与第二参考信号端VREF2耦接，上拉控制电路30的输出端与第一晶体管M1的第一极耦接。该上拉控制电路30被配置为响应于第一时钟信号端CK1和第七晶体管M7的栅极(即下拉节点PD)的信号，将第二参考信号端VREF2的信号提供给第一晶体管M1的第一极(即第二上拉节点PU_2)。
具体地，在具体实施时，如图4a所示，上拉控制电路30可以包括：第三晶体管M3和单栅型的第四晶体管M4；其中，第三晶体管M3的栅极被配置为与第一时钟信号端CK1耦接，第三晶体管M3的第一极与第一晶体管M1的第一极(即第二上拉节点PU_2)耦接，第三晶体管M3的第二极与第四晶体管M4的第一极耦接。第四晶体管M4的栅极与第七晶体管M7的栅极(即下拉节点PD)耦接，第四晶体管M4的第二极被配置为与第二参考信号端VREF2耦接。
进一步地，第四晶体管M4在第七晶体管M7的栅极(即下拉节点PD)的信号的控制下处于导通状态时，可以将第二参考信号端VREF2的信号提供给第四晶体管M4的第一极。第三晶体管M3在第一时钟信号端CK1的信号 的控制下处于导通状态时，可以将第一晶体管M1的第一极(即第二上拉节点PU_2)与第四晶体管M4的第一极导通。
在具体实施时，在本公开实施例中，如图4a所示，输出电路20可以包括：第八晶体管M8和第二电容C2；其中，第八晶体管M8的栅极与第一晶体管M1的第二极(即第一上拉节点PU_1)耦接，第八晶体管M8的第一极被配置为与第一时钟信号端CK1耦接，第八晶体管M8的第二极与信号输出端OP耦接。第二电容C2的第一端与第一晶体管M1的第二极(即第一上拉节点PU_1)耦接，第二电容C2的第二端与信号输出端OP耦接。
进一步地，第八晶体管M8在第一晶体管M1的第二极(即第一上拉节点PU_1)的信号的控制下处于导通状态时，可以将第一时钟信号端CK1的信号提供给信号输出端OP。第二电容C2可以将输入到第一晶体管M1的第二极(即第一上拉节点PU_1)的信号和输入到信号输出端OP的信号进行存储与保持稳定，以及在第一晶体管M1的第二极(即第一上拉节点PU_1)处于浮空状态时，可以保持第一上拉节点PU_1与信号输出端OP之间电压差的稳定性。
在具体实施时，根据信号的流通方向，上述晶体管的第一极可以作为其源极，第二极可以作为其漏极；或者，第一极作为其漏极，第二极作为其源极，在此不作具体区分。
需要说明的是，本公开上述实施例中提到的晶体管可以是TFT，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Semiconductor)，在此不作限定。
为了简化制备工艺，在具体实施时，在本公开实施例中，如图4a所示，所有晶体管可以均为P型晶体管。其中，P型晶体管在其栅极与其源极之间的电压差V gs与其阈值电压V th满足关系V gs<V th时导通。例如，第一晶体管M1可以为P型晶体管，则第一晶体管M1在其栅极与其源极之间的电压差V gs1与其阈值电压V th1之间的关系满足公式：V gs1<V th1时导通。当然，在本公开实施例中，仅是以晶体管为P型晶体管为例进行说明的，对于晶体管为N型晶 体管的情况，设计原理与本公开相同，也属于本公开保护的范围。并且，N型晶体管在其栅极与其源极之间的电压差V gs与其阈值电压V th满足关系V gs>V th时导通。例如第一晶体管M1可以为N型晶体管，第一晶体管M1在其栅极与其源极之间的电压差V gs1与其阈值电压V th1之间的关系满足公式：V gs1>V th1时导通。
一般晶体管的栅极和有源层之间会设置栅绝缘层，在具体实施时，可以通过调整栅绝缘层的厚度来确定双栅型晶体管中占主导地位的栅极。例如，在本公开实施例中，可以通过调整栅绝缘层的厚度，以使第一晶体管的第一栅极占主导地位，则第一晶体管M1在其栅极(即第一栅极)与其源极之间的电压差V gs1与其阈值电压V th1之间的关系满足公式V gs1<V th1时导通。下面均以V gs1代表第一晶体管M1的第一栅极与其源极之间的电压差为例进行说明。
为了使第一晶体管M1的阈值电压V th1可以移动，在具体实施时，第一阈值调控信号端被配置为接收至少具有与第一参考信号端VREF1的信号的电平相反的信号。
在具体实施时，在本公开实施例中，在输入信号端IP的有效脉冲信号为低电平信号时，第一参考信号端VREF1的信号为低电平信号，第二参考信号端VREF2的信号为高电平信号，第一阈值调控信号端VS1被配置为接收至少具有高电平信号的信号。或者，在具体实施时，在本公开实施例中，在输入信号端IP的有效脉冲信号为高电平信号时，第一参考信号端VREF1的信号为高电平信号，第二参考信号端VREF2的信号为低电平信号，第一阈值调控信号端VS1被配置为接收至少具有低电平信号的信号。需要说明的是，结合图5a所示，输入信号端IP的有效脉冲信号指的是一帧时间内输入到第二晶体管M2的低电平信号，以控制该移位寄存器进行以为输出工作。
进一步的，在具体实施时，P型晶体管在高电平信号作用下截止，在低电平信号作用下导通。N型晶体管在高电平信号作用下导通，在低电平信号作用下截止。
以上仅是举例说明本公开实施例提供的移位寄存器的具体结构，在具体 实施时，上述各电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
下面以图4a所示的移位寄存器为例，结合图5a所示的信号时序图对本公开实施例提供的上述移位寄存器的工作过程作以描述。下述描述中以1表示高电平信号，0表示低电平信号，需要说明的是，1和0是逻辑电平，其仅是为了更好的解释本公开实施例的具体工作过程，而不是在具体实施时施加在各晶体管的栅极上的电压。
具体地，选取如图5a所示的信号时序图中的输入阶段T1、输出阶段T2、复位阶段T3以及复位保持阶段T4四个阶段。需要说明的是，图5a所示的信号时序图仅是某一个移位寄存器在当前帧中的工作过程。该移位寄存器在其他帧中的工作过程分别与该当前帧中的工作过程基本相同，在此不作赘述。
在输入阶段T1中，IP＝0，CK1＝1，CK2＝0，VS1＝0。
由于CK1＝1，因此第三晶体管M3截止。由于CK2＝0，因此第二晶体管M2和第五晶体管M5均导通。导通的第五晶体管M5可以将第一参考信号端VREF1的低电平信号提供给下拉节点PD，使下拉节点PD的信号为低电平信号，以控制第四晶体管M4和第七晶体管M7导通。导通的第七晶体管M7将第二参考信号端VREF2的高电平信号提供给信号输出端OP，使信号输出端OP输出高电平的信号。导通的第二晶体管M2可以将输入信号端IP的低电平信号提供给第二上拉节点PU_2，使第二上拉节点PU_2的信号为低电平信号。第六晶体管M6在第二上拉节点PU_2的信号的控制下导通，以将第二时钟信号端CK2的低电平信号提供给下拉节点PD，进一步使下拉节点PD的信号为低电平信号。由于VS1＝0，可以使第一晶体管M1的V th1右移，从而使第一晶体管M1满足V gs1<V th1，以使第一晶体管M1尽可能的完全导通；其中，由于上一帧中，第一上拉节点PU_1的信号为高电平信号，因此当前帧中第一晶体管M1与第一上拉节点PU_1连接的一极作为源极。导通的第一晶体管M1将第二上拉节点PU_2与第一上拉节点PU_1导通，从而可以及时使第一上拉节点PU_1的信号为低电平信号，以控制第八晶体管M8导通。导通的第八晶 体管M8将第一时钟信号端CK1的高电平信号提供给信号输出端OP，使信号输出端OP输出高电平的信号。
在输入阶段T1之后，且在输出阶段T2之前，由于CK2＝1，因此第二晶体管M2和第五晶体管M5均截止。由于CK1＝1，因此第三晶体管M3也截止。因此，第二上拉节点PU_2与第一上拉节点PU_1处于浮空状态，则第一上拉节点PU_1在第二电容C2的作用下保持为低电平信号。并且，由于第一晶体管M1的阈值电压V th1的原因，因此可以有第一上拉节点PU_1的低电平信号的电压小于第二上拉节点PU_2的低电平信号的电压，因此，此阶段中，第一晶体管M1与第二上拉节点PU_2电连接的一极作为其源极。由于VS1＝0，可以使第一晶体管M1的V th1右移，从而使第一晶体管M1满足V gs1<V th1，以使第一晶体管M1尽可能的完全导通，使第二上拉节点PU_2的信号为低电平信号，以控制第六晶体管M6导通。导通的第六晶体管M6将第二时钟信号端CK2的高电平信号提供给下拉节点PD，使下拉节点PD的信号为高电平信号，以控制第四晶体管M4和第七晶体管M7均截止。第八晶体管M8在第一上拉节点PU_1的信号的控制下导通，以将第一时钟信号端CK1的高电平信号提供给信号输出端OP，使信号输出端OP输出高电平的信号。
在输出阶段T2中，IP＝1，CK1＝0，CK2＝1，VS1＝1。
由于CK2＝1，因此第二晶体管M2和第五晶体管M5均截止，则第一上拉节点PU_1在第二电容C2的作用下保持为低电平信号，以控制第八晶体管M8导通，从而将第一时钟信号端CK1的低电平信号提供给信号输出端OP，使信号输出端OP输出低电平的信号。由于第二电容C2的作用下，使第一上拉节点PU_1的电平进一步拉低，以控制第八晶体管M8可以尽可能完全导通，以将第一时钟信号端CK1的低电平信号提供给信号输出端OP，使信号输出端OP输出低电平的信号。并且，由于第一晶体管M1的阈值电压V th1的原因，因此可以有第一上拉节点PU_1的低电平信号的电压小于第二上拉节点PU_2的低电平信号的电压，因此，此阶段中，第一晶体管M1与第二上拉节点PU_2电连接的一极作为其源极。由于VS1＝1，可以使第一晶体管M1的V th1左移， 第一晶体管M1的栅极电压为低电平信号的电压，第一晶体管M1的源极电压为低电平信号的电压，从而可以使第一晶体管M1不能满足V gs1<V th1，以使第一晶体管M1截止，从而可以保持第一上拉节点PU_1的电平稳定，避免由于漏电导致第一上拉节点PU_1的电平升高导致的信号输出端OP输出不稳定的情况。并且，由于第一电容C1的作用，可以保持下拉节点PD的信号为高电平信号，从而控制第四晶体管M4和第七晶体管M7均截止，避免对信号输出端OP输出的信号造成不利影响。
在复位阶段T3中，IP＝1，CK1＝1，CK2＝0，VS1＝0。
由于CK2＝0，因此第二晶体管M2和第五晶体管M5均导通。导通的第二晶体管M2可以将输入信号端IP的高电平信号提供给第二上拉节点PU_2，使第二上拉节点PU_2的信号为高电平信号，以控制第六晶体管M6截止。并且，此阶段中，第一晶体管M1与第二上拉节点PU_2电连接的一极作为其源极，第一晶体管M1满足V gs1<V th1而导通，使得第二上拉节点PU_2与第一上拉节点PU_1导通，以控制第八晶体管M8截止。导通的第五晶体管M5将第一参考信号端VREF1的低电平信号提供给下拉节点PD，使下拉节点PD的信号为低电平信号，以控制第四晶体管M4和第七晶体管M7均导通。并且，由于CK1＝1，因此第三晶体管M3截止。导通的第七晶体管M7将第二参考信号端VREF2的高电平信号提供给信号输出端OP，使信号输出端OP输出高电平的信号。
在复位保持阶段T4中，IP＝1，CK1＝0，CK2＝1，VS1＝0。
由于CK2＝1，因此第二晶体管M2和第五晶体管M5均截止，则由于第一电容C1的作用可以将下拉节点PD的信号保持为低电平信号，以控制第四晶体管M4和第七晶体管M7均导通。由于CK1＝0，因此第三晶体管M3导通。导通的第三晶体管M3和第四晶体管M4可以将第二参考信号端VREF2的高电平信号提供给第二上拉节点PU_2，使第二上拉节点PU_2的信号为高电平，以控制第六晶体管M6截止。并且，此阶段中，第一晶体管M1与第二上拉节点PU_2电连接的一极作为其源极，第一晶体管M1满足V gs1<V th1而导通，使 得第二上拉节点PU_2与第一上拉节点PU_1导通，以控制第八晶体管M8截止。导通的第七晶体管M7将第二参考信号端VREF2的高电平信号提供给信号输出端OP，使信号输出端OP输出高电平的信号。
在复位保持阶段T4之后，一直重复执行复位阶段T3和复位保持阶段T4的工作过程，直至输入信号端IP的信号电平再次变为低电平时为止。
需要说明的是，在输入阶段T1与输出阶段T2之间、输出阶段T2与复位阶段T3之间、复位阶段T3与复位保持阶段T4之间分别具有缓冲阶段。在缓冲阶段中，可以使移位寄存器中的晶体管的特性进行稳定，以在稳定后进入下一个工作阶段，并且，这样还可以避免第一时钟信号端CK1的信号的上升沿和第二时钟信号端CK2的信号的下降沿对齐，以及避免第一时钟信号端CK1的信号的下降沿和第二时钟信号端CK2的信号的上升沿对齐，从而可以提高移位寄存器的稳定性。
需要说明的是，在实际应用中，上述各信号的具体电压值可以根据实际应用环境来设计确定，在此不作限定。
本公开实施例还提供了移位寄存器的另一些信号时序图，如图5b所示，其针对图5a所示的实施方式进行了变形。下面仅说明本实施例与图4a所示的移位寄存器的实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，如图5b所示，第一阈值调控信号端VS1采用与输入信号端IP相同的信号。其中，第一阈值调控信号端VS1和输入信号端IP可以采用不同的信号线输入到移位寄存器中。或者，也可以采用同一条信号线将第一阈值调控信号端VS1和输入信号端IP输入到移位寄存器中，从而减少信号线的设置。
下面以图4a所示的移位寄存器为例，结合图5b所示的信号时序图对本公开实施例提供的上述移位寄存器的工作过程作以描述。具体地，选取如图5b所示的信号时序图中的输入阶段T1、输出阶段T2、复位阶段T3以及复位保持阶段T4四个阶段。
在输入阶段T1中，IP＝0，CK1＝1，CK2＝0，VS1＝0。
由于CK1＝1，因此第三晶体管M3截止。由于CK2＝0，因此第二晶体管M2和第五晶体管M5均导通。导通的第五晶体管M5可以将第一参考信号端VREF1的低电平信号提供给下拉节点PD，使下拉节点PD的信号为低电平信号，以控制第四晶体管M4和第七晶体管M7导通。导通的第七晶体管M7将第二参考信号端VREF2的高电平信号提供给信号输出端OP，使信号输出端OP输出高电平的信号。导通的第二晶体管M2可以将输入信号端IP的低电平信号提供给第二上拉节点PU_2，使第二上拉节点PU_2的信号为低电平信号。第六晶体管M6在第二上拉节点PU_2的信号的控制下导通，以将第二时钟信号端CK2的低电平信号提供给下拉节点PD，进一步使下拉节点PD的信号为低电平信号。由于VS1＝0，可以使第一晶体管M1的V th1右移，从而使第一晶体管M1满足V gs1<V th1，以使第一晶体管M1尽可能的完全导通；其中，由于上一帧中，第一上拉节点PU_1的信号为高电平信号，因此当前帧中第一晶体管M1与第一上拉节点PU_1连接的一极作为源极。导通的第一晶体管M1将第二上拉节点PU_2与第一上拉节点PU_1导通，从而可以及时使第一上拉节点PU_1的信号为低电平信号，以控制第八晶体管M8导通。导通的第八晶体管M8将第一时钟信号端CK1的高电平信号提供给信号输出端OP，使信号输出端OP输出高电平的信号。
在输入阶段T1之后，且在输出阶段T2之前，由于CK2＝1，因此第二晶体管M2和第五晶体管M5均截止。由于CK1＝1，因此第三晶体管M3也截止。因此，第二上拉节点PU_2与第一上拉节点PU_1处于浮空状态，则第一上拉节点PU_1在第二电容C2的作用下保持为低电平信号。并且，由于第一晶体管M1的阈值电压V th1的原因，因此可以有第一上拉节点PU_1的低电平信号的电压小于第二上拉节点PU_2的低电平信号的电压，因此，此阶段中，第一晶体管M1与第二上拉节点PU_2电连接的一极作为其源极。由于VS1＝1，可以使第一晶体管M1的V th1左移，从而使第一晶体管M1不能满足V gs1<V th1，以使第一晶体管M1截止。由于晶体管的耦合电容，可以使第二上拉节点PU_2的信号为低电平信号，以控制第六晶体管M6导通。导通的第六晶体管M6将 第二时钟信号端CK2的高电平信号提供给下拉节点PD，使下拉节点PD的信号为高电平信号，以控制第四晶体管M4和第七晶体管M7均截止。第八晶体管M8在第一上拉节点PU_1的信号的控制下导通，以将第一时钟信号端CK1的高电平信号提供给信号输出端OP，使信号输出端OP输出高电平的信号。
在输出阶段T2中，IP＝1，CK1＝0，CK2＝1，VS1＝1。
由于CK2＝1，因此第二晶体管M2和第五晶体管M5均截止，则第一上拉节点PU_1在第二电容C2的作用下保持为低电平信号，以控制第八晶体管M8导通，从而将第一时钟信号端CK1的低电平信号提供给信号输出端OP，使信号输出端OP输出低电平的信号。由于第二电容C2的作用下，使第一上拉节点PU_1的电平进一步拉低，以控制第八晶体管M8可以尽可能完全导通，以将第一时钟信号端CK1的低电平信号提供给信号输出端OP，使信号输出端OP输出低电平的信号。并且，由于第一晶体管M1的阈值电压V th1的原因，因此可以有第一上拉节点PU_1的低电平信号的电压小于第二上拉节点PU_2的低电平信号的电压，因此，此阶段中，第一晶体管M1与第二上拉节点PU_2电连接的一极作为其源极。由于VS1＝1，可以使第一晶体管M1的V th1左移，并且，第一晶体管M1的栅极为低电平信号的电压，第一晶体管M1的源极电压为低电平信号的电压，从而可以使第一晶体管M1不能满足V gs1<V th1，以使第一晶体管M1尽可能截止，从而可以保持第一上拉节点PU_1的电平稳定，避免由于漏电导致第一上拉节点PU_1的电平升高导致的信号输出端OP输出不稳定的情况。并且，由于第一电容C1的作用，可以保持下拉节点PD的信号为高电平信号，从而控制第四晶体管M4和第七晶体管M7均截止，避免对信号输出端OP输出的信号造成不利影响。
在复位阶段T3中，IP＝1，CK1＝1，CK2＝0，VS1＝1。
由于CK2＝0，因此第二晶体管M2和第五晶体管M5均导通。导通的第二晶体管M2可以将输入信号端IP的高电平信号提供给第二上拉节点PU_2，使第二上拉节点PU_2的信号为高电平信号，以控制第六晶体管M6截止。并且，此阶段中，第一晶体管M1与第二上拉节点PU_2电连接的一极作为其源 极，虽然VS1＝1，可以使第一晶体管M1的V th1左移。然而，第一晶体管M1的栅极为低电平信号的电压，第一晶体管M1的源极电压为高电平信号的电压，则可以使得第一晶体管M1满足V gs1<V th1而导通，使得第二上拉节点PU_2与第一上拉节点PU_1导通，以控制第八晶体管M8截止。导通的第五晶体管M5将第一参考信号端VREF1的低电平信号提供给下拉节点PD，使下拉节点PD的信号为低电平信号，以控制第四晶体管M4和第七晶体管M7均导通。并且，由于CK1＝1，因此第三晶体管M3截止。导通的第七晶体管M7将第二参考信号端VREF2的高电平信号提供给信号输出端OP，使信号输出端OP输出高电平的信号。
在复位保持阶段T4中，IP＝1，CK1＝0，CK2＝1，VS1＝1。
由于CK2＝1，因此第二晶体管M2和第五晶体管M5均截止，则由于第一电容C1的作用可以将下拉节点PD的信号保持为低电平信号，以控制第四晶体管M4和第七晶体管M7均导通。由于CK1＝0，因此第三晶体管M3导通。导通的第三晶体管M3和第四晶体管M4可以将第二参考信号端VREF2的高电平信号提供给第二上拉节点PU_2，使第二上拉节点PU_2的信号为高电平，以控制第六晶体管M6截止。并且，此阶段中，第一晶体管M1与第二上拉节点PU_2电连接的一极作为其源极，虽然VS1＝1，可以使第一晶体管M1的V th1左移。然而，第一晶体管M1的栅极为低电平信号的电压，第一晶体管M1的源极电压为高电平信号的电压，则可以使得第一晶体管M1满足V gs1<V th1而导通，使得第二上拉节点PU_2与第一上拉节点PU_1导通，以控制第八晶体管M8截止。导通的第七晶体管M7将第二参考信号端VREF2的高电平信号提供给信号输出端OP，使信号输出端OP输出高电平的信号。
在复位保持阶段T4之后，一直重复执行复位阶段T3和复位保持阶段T4的工作过程，直至输入信号端IP的信号电平再次变为低电平时为止。
本公开实施例提供了另一些移位寄存器，如图4b所示，其针对图4a所示的实施方式进行了变形。下面仅说明本实施例与图4a所示的移位寄存器的实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，如图4b所示，可以使第一晶体管M1的第二栅极与第二晶体管M2的第一极耦接，以进一步减少信号线的占用空间。并且，图4b所示的移位寄存器对应的信号时序图如图5b所示，图4b所示的移位寄存器的工作过程可以参见图4a所示的移位寄存器在图5b所示的信号时序图下的工作过程，在此不作赘述。或者，在具体实施时，在本公开实施例中，也可以使第一晶体管M1的第二栅极与第二晶体管M2的栅极耦接，以进一步减少信号线的占用空间，在此不作限定。
并且，还根据图5b所示的信号时序图，对图4b所示的移位寄存器的信号输出端OP输出的信号进行仿真模拟，仿真模拟图如图6所示。其中，横坐标代表时间，纵坐标代表电压。结合图4b、图5b以及图6可知，在输出阶段T2中，信号输出端OP可以稳定的输出信号，从而避免了由于第一上拉节点PU_1的漏电导致的不稳定的问题。
本公开实施例提供了另一些移位寄存器，如图7所示，其针对图4a所示的实施方式进行了变形。下面仅说明本实施例与图4a所示的移位寄存器的实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，如图7所示，输入电路10也可以包括：双栅型的第二晶体管M2；其中，第二晶体管M2的第一栅极被配置为与第二时钟信号端CK2耦接，第二晶体管M2的第二栅极被配置为与第二阈值调控信号端VS2耦接，第二晶体管M2的第一极被配置为与输入信号端IP耦接，第二晶体管M2的第二极与第一晶体管M1的第一极(即第二上拉节点PU_2)耦接。
在具体实施时，在本公开实施例中，第二阈值调控信号端VS2被配置为接收至少具有与第一参考信号端VREF1的电平相反的信号。例如，如图8所示，第二阈值调控信号端VS2的部分信号可以与第一参考信号端VREF1的信号的电平相反，并且，第二阈值调控信号端VS2的其余部分信号可以与第一参考信号端VREF1的信号的电平相同。
在具体实施时，在本公开实施例中，可以通过调整栅绝缘层的厚度，以 使第二晶体管的第一栅极占主导地位，则第二晶体管M2在其栅极(即第一栅极)与其源极之间的电压差V gs2与其阈值电压V th2之间的关系满足公式V gs2<V th2时导通。下面均以V gs2代表第二晶体管M2的第一栅极与其源极之间的电压差为例进行说明。
在具体实施时，在本公开实施例中，如图7所示，上拉控制电路30也可以包括：第三晶体管M3和双栅型的第四晶体管M4；其中，第三晶体管M3的栅极被配置为与第一时钟信号端CK1耦接，第三晶体管M2的第一极与第一晶体管M1的第一极(即第二上拉节点PU_2)耦接，第三晶体管M3的第二极与第四晶体管M4的第一极耦接。第四晶体管M4的第一栅极与第七晶体管M7的栅极(即下拉节点PD)耦接，第四晶体管M4的第二栅极被配置为与第三阈值调控信号端VS3耦接，第四晶体管M4的第二极被配置为与第二参考信号端VREF2耦接。
在具体实施时，在本公开实施例中，第三阈值调控信号端VS3被配置为接收至少具有与第一参考信号端VREF1的信号的电平相反的信号。例如，如图8所示，第三阈值调控信号端VS3的部分信号可以与第一参考信号端VREF1的电平相反，并且，第三阈值调控信号端VS3的其余部分信号可以与第一参考信号端VREF1的电平相同。
在具体实施时，在本公开实施例中，可以通过调整栅绝缘层的厚度，以使第四晶体管的第一栅极占主导地位，则第四晶体管M4在其栅极(即第一栅极)与其源极之间的电压差V gs4与其阈值电压V th4之间的关系满足公式V gs4<V th4时导通。下面均以V gs4代表第四晶体管M4的第一栅极与其源极之间的电压差为例进行说明。
下面以图7所示的移位寄存器为例，结合图8所示的信号时序图对本公开实施例提供的上述移位寄存器的工作过程作以描述。
具体地，选取如图8所示的信号时序图中的输入阶段T1、输出阶段T2、复位阶段T3以及复位保持阶段T4四个阶段。
在输入阶段T1中，IP＝0，CK1＝1，CK2＝0，VS1＝0，VS2＝0，VS3＝0。
由于CK1＝1，因此第三晶体管M3截止。由于CK2＝0，因此第五晶体管M5导通，以将第一参考信号端VREF1的低电平信号提供给下拉节点PD，使下拉节点PD的信号为低电平信号，以控制第七晶体管M7导通。导通的第七晶体管M7将第二参考信号端VREF2的高电平信号提供给信号输出端OP，使信号输出端OP输出高电平的信号。由于CK2＝0，VS2＝0，使第二晶体管M2的阈值电压V th2可以右移，以使第二晶体管M2尽可能的完全导通，以加速将输入信号端IP的低电平信号提供给第二上拉节点PU_2的充电过程，使第二上拉节点PU_2的信号尽可能快的为低电平信号。第六晶体管M6在第二上拉节点PU_2的信号的控制下导通，以将第二时钟信号端CK2的低电平信号提供给下拉节点PD，进一步使下拉节点PD的信号为低电平信号。由于VS1＝0，可以使第一晶体管M1的V th1右移，从而使第一晶体管M1满足V gs1<V th1，以使第一晶体管M1尽可能的完全导通。导通的第一晶体管M1将第二上拉节点PU_2与第一上拉节点PU_1导通，从而可以及时使第一上拉节点PU_1的信号为低电平信号，以控制第八晶体管M8导通。导通的第八晶体管M8将第一时钟信号端CK1的高电平信号提供给信号输出端OP，使信号输出端OP输出高电平的信号。
在输入阶段T1之后，且在输出阶段T2之前，由于CK2＝1，因此第五晶体管M5均截止。由于CK1＝1，因此第三晶体管M3也截止。由于VS1＝1以及CK2＝1，可以使第二晶体管M2的V th2左移，从而使第二晶体管M2不能满足V gs2<V th2而尽可能截止。则第一上拉节点PU_1在第二电容C2的作用下保持为低电平信号。并且，由于第一晶体管M1的阈值电压V th1的原因，因此可以有第一上拉节点PU_1的低电平信号的电压小于第二上拉节点PU_2的低电平信号的电压，因此，此阶段中，第一晶体管M1与第二上拉节点PU_2电连接的一极作为其源极。由于VS1＝1，可以使第一晶体管M1的V th1左移，从而使第一晶体管M1不能满足V gs1<V th1，以使第一晶体管M1截止。由于晶体管的耦合电容，可以使第二上拉节点PU_2的信号为低电平信号，以控制第六晶体管M6导通。导通的第六晶体管M6将第二时钟信号端CK2的高电平 信号提供给下拉节点PD，使下拉节点PD的信号为高电平信号，以控制第四晶体管M4和第七晶体管M7均截止。第八晶体管M8在第一上拉节点PU_1的信号的控制下导通，以将第一时钟信号端CK1的高电平信号提供给信号输出端OP，使信号输出端OP输出高电平的信号。
在输出阶段T2中，IP＝1，CK1＝0，CK2＝1，VS1＝1，VS2＝1，VS3＝1。
由于CK2＝1，因此第五晶体管M5截止。第一上拉节点PU_1在第二电容C2的作用下保持为低电平信号，以控制第八晶体管M8导通，从而将第一时钟信号端CK1的低电平信号提供给信号输出端OP，使信号输出端OP输出低电平的信号。由于第二电容C2的作用，使第一上拉节点PU_1的电平进一步拉低，以控制第八晶体管M8可以尽可能完全导通，以将第一时钟信号端CK1的低电平信号提供给信号输出端OP，使信号输出端OP输出低电平的信号。并且，并且，由于第一晶体管M1的阈值电压V th1的原因，因此可以有第一上拉节点PU_1的低电平信号的电压小于第二上拉节点PU_2的低电平信号的电压，因此，此阶段中，第一晶体管M1与第二上拉节点PU_2电连接的一极作为其源极。由于VS1＝1，可以使第一晶体管M1的V th1左移，并且，第一晶体管M1的栅极为低电平信号的电压，第一晶体管M1的源极电压为低电平信号的电压，从而可以使第一晶体管M1不能满足V gs1<V th1，以使第一晶体管M1截止，从而可以保持第一上拉节点PU_1的电平稳定，避免由于漏电导致第一上拉节点PU_1的电平升高，而导致的信号输出端OP输出不稳定的情况。并且，由于CK2＝1，VS2＝1，使第二晶体管M2的阈值电压可以左移，可以使第二晶体管M2尽可能的完全截止，以避免第二晶体管M2漏电对第二上拉节点PU_2的漏电影响，延长第二上拉节点PU_2的低电平信号的保持时间。并且，由于VS3＝1以及下拉节点PD的信号为高电平信号，因此可以使第四晶体管M4的阈值电压左移，从而使第四晶体管M4尽可能的完全截止，以避免第四晶体管M4漏电对第二上拉节点PU_2的漏电影响，延长第二上拉节点PU_2的低电平信号的保持时间。第六晶体管M6在第二上拉节点PU_2的信号的控制下将第二时钟信号端CK2的高电平信号提供给下拉节点PD，以控 制第七晶体管M7截止，避免对信号输出端OP输出的信号造成不利影响。
在复位阶段T3中，IP＝1，CK1＝1，CK2＝0，VS1＝1，VS2＝1，VS3＝0。
由于CK2＝0，因此第二晶体管M2和第五晶体管M5均导通。导通的第二晶体管M2可以将输入信号端IP的高电平信号提供给第二上拉节点PU_2，使第二上拉节点PU_2的信号为高电平信号，以控制第六晶体管M6截止。并且，此阶段中，第一晶体管M1与第二上拉节点PU_2电连接的一极作为其源极，虽然VS1＝1，可以使第一晶体管M1的V th1左移。然而，第一晶体管M1的栅极为低电平信号的电压，第一晶体管M1的源极电压为高电平信号的电压，则可以使得第一晶体管M1满足V gs1<V th1而导通，使得第二上拉节点PU_2与第一上拉节点PU_1导通，以控制第八晶体管M8截止。导通的第五晶体管M5将第一参考信号端VREF1的低电平信号提供给下拉节点PD，使下拉节点PD的信号为低电平信号，以控制第七晶体管M7导通。导通的第七晶体管M7将第二参考信号端VREF2的高电平信号提供给信号输出端OP，使信号输出端OP输出高电平的信号。并且，由于CK1＝1，因此第三晶体管M3截止。
在复位保持阶段T4中，IP＝1，CK1＝0，CK2＝1，VS1＝1，VS2＝1，VS3＝0。
由于CK2＝1，因此第二晶体管M2和第五晶体管M5均截止，则由于第一电容C1的作用可以将下拉节点PD的信号保持为低电平信号，控制第七晶体管M7导通，以将第二参考信号端VREF2的高电平信号提供给信号输出端OP，使信号输出端OP输出高电平的信号。由于VS3＝0以及下拉节点PD的信号为低电平信号，以控制第四晶体管M4尽可能完全导通。由于CK1＝0，因此第三晶体管M3导通。导通的第三晶体管M3和第四晶体管M4可以及时将第二参考信号端VREF2的高电平信号提供给第二上拉节点PU_2，以及时控制第二上拉节点PU_2的信号为高电平，控制第六晶体管M6截止。并且，此阶段中，第一晶体管M1与第二上拉节点PU_2电连接的一极作为其源极，虽然VS1＝1，可以使第一晶体管M1的V th1左移。然而，第一晶体管M1的栅极为低电平信号的电压，第一晶体管M1的源极电压为高电平信号的电压，则可以使得第一晶体管M1满足V gs1<V th1而导通，使得第二上拉节点PU_2与第 一上拉节点PU_1导通，以控制第八晶体管M8截止。
在复位保持阶段T4之后，一直重复执行复位阶段T3和复位保持阶段T4的工作过程，直至输入信号端IP的信号的电平再次变为高电平时为止。
本公开实施例提供了又一些移位寄存器，如图9a所示，其针对图7所示的实施方式进行了变形。下面仅说明本实施例与图7所示的移位寄存器的实施例的区别之处，其相同之处在此不作赘述。
为了减少传输信号的信号线，在具体实施时，在本公开实施例中，如图9a所示，可以使第一晶体管M1的第二栅极与第二晶体管M2的第一极耦接。这样可以将第一阈值调控信号端与输入信号端设置为接收同一信号，即第一晶体管M1的第二栅极接收输入信号端IP的信号，以进一步减少信号线的占用空间。这样可以采用同一信号线向第一阈值调控信号端与输入信号端输入信号。
为了减少传输信号的信号线，在具体实施时，在本公开实施例中，如图9a所示，可以使第二晶体管M2的第二栅极与第二晶体管M2的第一极耦接。这样可以使第二阈值调控信号端与输入信号端设置为接收同一信号，即第二晶体管M2的第二栅极接收输入信号端IP的信号，以进一步减少信号线的占用空间。这样可以采用同一信号线向第二阈值调控信号端与输入信号端输入信号。
为了减少传输信号的信号线，在具体实施时，在本公开实施例中，可以使第一阈值调控信号端和第二阈值调控信号端设置为接收同一信号。如图9a所示，可以使第一晶体管M1的第二栅极与第二晶体管M2的第二栅极耦接，以均接收输入信号端IP的信号。
为了减少传输信号的信号线，在具体实施时，在本公开实施例中，可以使第三阈值调控信号端与下拉节点的信号设置为同一信号。如图9a所示，可以使第四晶体管M4的第二栅极与第七晶体管M7的栅极(即下拉节点PD)耦接。
在具体实施时，图9a所示的移位寄存器的工作过程可以参见图7所示的 移位寄存器的工作过程，在此不作赘述。并且，还对图9a所示的移位寄存器的信号输出端OP输出的信号和第一上拉节点PU_1的信号进行仿真模拟，如图9b与图9c所示。其中，横坐标代表时间，纵坐标代表电压。结合图9a至9c可知，在输出阶段T2中，信号输出端OP可以稳定的输出信号，从而避免了由于第一上拉节点PU_1的漏电导致的不稳定的问题。
本公开实施例提供了又一些移位寄存器的信号时序图，如图10a与图10b所示，其针对图8所示的实施方式进行了变形。下面仅说明本实施例与图8所示的移位寄存器的实施例的区别之处，其相同之处在此不作赘述。
为了减少传输信号的信号线，在具体实施时，在本公开实施例中，如图10a与图10b所示，第一阈值调控信号端VS1可以被配置为时钟信号。
为了减少传输信号的信号线，在具体实施时，在本公开实施例中，如图10a与图10b所示，第二阈值调控信号端VS2可以被配置为时钟信号。
为了减少传输信号的信号线，在具体实施时，在本公开实施例中，如图10与图10b所示，第三阈值调控信号端VS3可以被配置为时钟信号。
进一步地，为了减少传输信号的信号线，在具体实施时，在本公开实施例中，如图10a所示，可以使第一阈值调控信号端VS1和第二阈值调控信号端VS2被配置为接收同一信号。
进一步地，为了减少传输信号的信号线，在具体实施时，在本公开实施例中，如图10a所示，可以使第一阈值调控信号端VS1和第三阈值调控信号端VS3被配置为接收同一信号。
进一步地，为了减少传输信号的信号线，在具体实施时，在本公开实施例中，如图10a所示，可以使第一阈值调控信号端VS1、第二阈值调控信号端VS2和第三阈值调控信号端VS3被配置为接收同一信号。这样可以采用同一信号线向第一阈值调控信号端VS1、第二阈值调控信号端VS2和第三阈值调控信号端VS3输入时钟信号。
下面以图7所示的移位寄存器为例，结合图10b所示的信号时序图对本公开实施例提供的上述移位寄存器的工作过程作以描述。具体地，选取如图 10b所示的信号时序图中的输入阶段T1、输出阶段T2、复位阶段T3以及复位保持阶段T4四个阶段。
在输入阶段T1中，IP＝0，CK1＝1，CK2＝0，VS1＝0，VS2＝0，VS3＝0。该阶段的工作过程可以参见图7所示的移位寄存器在输入阶段T1中的工作过程，在此不作赘述。
在输入阶段T1之后，且在输出阶段T2之前，也可以参见图7所示的移位寄存器在输入阶段T1之后且在输出阶段T2之前的工作过程，在此不作赘述。
在输出阶段T2中，IP＝1，CK1＝0，CK2＝1，VS1＝1，VS2＝1，VS3＝1。该阶段的工作过程可以参见图7所示的移位寄存器在输出阶段T2中的工作过程，在此不作赘述。
在复位阶段T3中，IP＝1，CK1＝1，CK2＝0，VS1＝0，VS2＝0，VS3＝0。由于CK2＝0，VS2＝0，使第二晶体管M2的阈值电压V th2可以右移，以使第二晶体管M2尽可能的完全导通，以加速将输入信号端IP的高电平信号提供给第二上拉节点PU_2的充电过程，使第二上拉节点PU_2的信号尽可能快的为高电平信号。由于VS1＝0以及第一参考信号端VREF1为低电平信号，因此，第一晶体管M1可以及时导通，以将第二上拉节点PU_2的高电平信号提供给第一上拉节点PU_1，以控制第八晶体管M8截止。该阶段的其余工作过程可以参见图7所示的移位寄存器在复位阶段T3中的工作过程，在此不作赘述。
在复位保持阶段T4中，IP＝1，CK1＝0，CK2＝1，VS1＝1，VS2＝1，VS3＝1。虽然，由于VS3＝1，可以使第四晶体管M4的V th4左移，然而，第四晶体管M4的栅极为低电平信号的电压，第四晶体管M4的源极电压为高电平信号的电压，则可以使得第四晶体管M4满足V gs4<V th4而导通。该阶段的其余工作过程可以参见图7所示的移位寄存器在复位保持阶段T4中的工作过程，在此不作赘述。
在复位保持阶段T4之后，一直重复执行复位阶段T3和复位保持阶段T4的工作过程，直至输入信号端IP的信号的电平再次变为高电平时为止。
本公开实施例提供了又一些移位寄存器的信号时序图，如图10c所示，其针对图8所示的实施方式进行了变形。下面仅说明本实施例与图8所示的移位寄存器的实施例的区别之处，其相同之处在此不作赘述。
为了减少运算量，在具体实施时，在本公开实施例中，如图10c所示，第一阈值调控信号端VS1可以被配置为与第二时钟信号端CK2的时序相同的时钟信号。这样可以直接采用第二时钟信号端CK2的时序以向第一阈值调控信号端VS1输入时钟信号。
为了减少运算量，在具体实施时，在本公开实施例中，如图10c所示，第二阈值调控信号端VS2可以被配置为与第二时钟信号端CK2的时序相同的时钟信号。这样可以直接采用第二时钟信号端CK2的时序以向第二阈值调控信号端VS2输入时钟信号。
为了减少运算量，在具体实施时，在本公开实施例中，如图10c所示，第三阈值调控信号端VS3可以被配置为与第二时钟信号端CK2的时序相同的时钟信号。这样可以直接采用第二时钟信号端CK2的时序以向第三阈值调控信号端VS3输入时钟信号。
在具体实施时，图8所示的移位寄存器在图10c所示的信号时序图下的工作过程可以参见图8所示的移位寄存器在图10b所示的信号时序图下的工作过程，在此不作赘述。
本公开实施例提供了又一些移位寄存器，如图11所示，其针对图7所示的实施方式进行了变形。下面仅说明本实施例与图7所示的移位寄存器的实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，可以使第一阈值调控信号端与第二时钟信号端设置为同一时钟信号。如图11与图12所示，第一阈值调控信号端为第二时钟信号端CK2。第一晶体管M1的第二栅极与第二晶体管M2的第一栅极耦接，以使第一晶体管M1的第二栅极接收第二时钟信号端CK2的信号。这样可以采用同一信号线向第一阈值调控信号端与第二时钟信号端输入信号。
在具体实施时，在本公开实施例中，可以使第二阈值调控信号端与第二时钟信号端设置为同一时钟信号。如图11与图12所示，第二阈值调控信号端为第二时钟信号端CK2。第二晶体管M2的第二栅极与第二晶体管M2的第一栅极耦接，以使第二晶体管M2的第二栅极接收第二时钟信号端CK2的信号。这样可以采用同一信号线向第一阈值调控信号端与第二时钟信号端输入信号。
在具体实施时，在本公开实施例中，可以使第三阈值调控信号端与第二时钟信号端设置为同一时钟信号。如图11与图12所示，第四晶体管M4的第二栅极与第五晶体管M5的栅极耦接。当然，也可以使第四晶体管M4的第二栅极与第二晶体管M2的第一栅极耦接。以使第四晶体管M4的第二栅极接收第二时钟信号端CK2的信号。这样可以采用同一信号线向第一阈值调控信号端与第二时钟信号端输入信号。
下面以图11所示的移位寄存器为例，结合图12所示的信号时序图对本公开实施例提供的上述移位寄存器的工作过程作以描述。
在输入阶段T1，IP＝0，CK1＝1，CK2＝0。该阶段的工作过程可以参见图7所示的移位寄存器在输入阶段T1中的工作过程，在此不作赘述。
在输入阶段T1之后且在输出阶段T2之前的工作过程，也可以参见图7所示的移位寄存器在输入阶段T1之后且在输出阶段T2之前的工作过程，在此不作赘述。
输出阶段T2，IP＝1，CK1＝0，CK2＝1。该阶段的工作过程可以参见图7所示的移位寄存器在输出阶段T2中的工作过程，在此不作赘述。
复位阶段T3，IP＝1，CK1＝1，CK2＝0。由于CK2＝0，因此第二晶体管M2可以尽可能的完全导通，以及时将输入信号端IP的高电平信号提供给第二上拉节点PU_2，使第二上拉节点PU_2的信号为高电平信号，以及时控制第六晶体管M6截止。并且，由于CK2＝0，且第一参考信号端VREF1为低电平信号，则第一晶体管M1可以及时导通，以及时将第二上拉节点PU_2的高电平的信号提供给第一上拉节点PU_1，使第一上拉节点PU_1的信号为高电 平信号，以及时控制第八晶体管M8截止。该阶段的其余工作过程可以参见图7所示的移位寄存器在复位阶段T3中的工作过程，在此不作赘述。
在复位保持阶段T4，IP＝1，CK1＝0，CK2＝1，虽然，由于CK2＝1，可以使第四晶体管M4的V th4左移，然而，第四晶体管M4的栅极(即第一栅极)为低电平信号的电压，第四晶体管M4的源极(即与第二参考信号端VREF2耦接的一极)电压为高电平信号的电压，则可以使得第四晶体管M4满足V gs4<V th4而导通。该阶段的其余工作过程可以参见图7所示的移位寄存器在复位保持阶段T4中的工作过程，在此不作赘述。
本公开实施例提供了又一些移位寄存器，如图13所示，其针对图11所示的实施方式进行了变形。下面仅说明本实施例与图11所示的移位寄存器的实施例的区别之处，其相同之处在此不作赘述。
为了减少传输信号的信号线，在具体实施时，在本公开实施例中，可以使第三阈值调控信号端与下拉节点的信号为同一信号。如图13所示，第四晶体管M4的第二栅极与第七晶体管M7的栅极(即下拉节点PD)耦接。
下面以图13所示的移位寄存器为例，结合图12所示的信号时序图对本公开实施例提供的上述移位寄存器的工作过程作以描述。
具体地，选取如图12所示的信号时序图中的输入阶段T1、输出阶段T2、复位阶段T3以及复位保持阶段T4四个阶段。
在输入阶段T1，IP＝0，CK1＝1，CK2＝0。该阶段的工作过程可以参见图7所示的移位寄存器在输入阶段T1中的工作过程，在此不作赘述。
在输入阶段T1之后且在输出阶段T2之前的工作过程，也可以参见图7所示的移位寄存器在输入阶段T1之后且在输出阶段T2之前的工作过程，在此不作赘述。
输出阶段T2，IP＝1，CK1＝0，CK2＝1。该阶段的工作过程可以参见图7所示的移位寄存器在输出阶段T2中的工作过程，在此不作赘述。
复位阶段T3，IP＝1，CK1＝1，CK2＝0。由于CK2＝0，因此第二晶体管M2可以尽可能的完全导通，以及时将输入信号端IP的高电平信号提供给第 二上拉节点PU_2，使第二上拉节点PU_2的信号为高电平信号，以及时控制第六晶体管M6截止。并且，由于CK2＝0，且第一参考信号端VREF1为低电平信号，则第一晶体管M1可以及时导通，以及时将第二上拉节点PU_2的高电平的信号提供给第一上拉节点PU_1，使第一上拉节点PU_1的信号为高电平信号，以及时控制第八晶体管M8截止。该阶段的其余工作过程可以参见图7所示的移位寄存器在复位阶段T3中的工作过程，在此不作赘述。
在复位保持阶段T4，IP＝1，CK1＝0，CK2＝1。该阶段的工作过程可以参见图7所示的移位寄存器在复位保持阶段T4中的工作过程，在此不作赘述。
本公开实施例提供了又一些移位寄存器，如图14a所示，其针对图8所示的信号时序图的实施方式进行了变形。下面仅说明本实施例与图8所示的信号时序图的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，如图14b所示，可以将第一阈值调控信号端VS1设置为接收固定电压信号，例如设置为具有第一电压值的直流固定电压信号，以保证第一晶体管M1在输出阶段T2中可以尽可能的完全截止，以降低漏电流对第一上拉节点PU_1的漏电影响。具体地，在第一晶体管M1为P型晶体管时，可以将第一阈值调控信号端VS1设置接收高电平的固定电压信号。进一步地，在显示装置采用不同的刷新频率时，可以根据实际应用设置第一电压值，例如显示装置采用较低的刷新频率时，由于移位寄存器工作在较低的刷新频率(例如1Hz)或保持状态时，可以将第一电压值设置为高压，以减少漏电，确保移位寄存器输出稳定性，从而移位寄存器不会工作异常。或者，显示装置采用较高的刷新频率时，由于移位寄存器工作在较高的刷新频率(例如60Hz、120Hz)时，可以将第一电压值设置为0V或负压，确保移位寄存器的响应速度。当然，上述第一电压值可以根据实际应用环境来设计确定，在此不作限定。
在具体实施时，在第一晶体管M1为N型晶体管时，可以将第一阈值调控信号端VS1设置为接收低电平的固定电压信号。进一步地，在显示装置采用不同的刷新频率时，可以根据实际应用设置第一电压值，在此不作限定。
在具体实施时，在本公开实施例中，也可以将第二阈值调控信号端VS2设置为接收固定电压信号，例如设置为具有第二电压值的直流固定电压信号，以保证第二晶体管M2可以在输出阶段T2中可以尽可能的完全截止，以降低漏电流对第二上拉节点PU_2的漏电影响。具体地，在第二晶体管M2为P型晶体管时，可以将第二阈值调控信号端VS2设置为接收高电平的固定电压信号。进一步地，在显示装置采用不同的刷新频率时，可以根据实际应用设置第二电压值，例如显示装置采用较低的刷新频率时，由于移位寄存器工作在较低的刷新频率(例如1Hz)或保持状态时，可以将第二电压值设置为高压，以减少漏电，确保移位寄存器输出稳定性，从而移位寄存器不会工作异常。或者，显示装置采用较高的刷新频率时，由于移位寄存器工作在较高的刷新频率(例如60Hz、120Hz)时，可以将第二电压值设置为0V或负压，确保移位寄存器的响应速度。当然，上述第二电压值可以根据实际应用环境来设计确定，在此不作限定。
在具体实施时，在第二晶体管M2为N型晶体管时，可以将第二阈值调控信号端VS2设置为接收低电平的固定电压信号。进一步地，在显示装置采用不同的刷新频率时，可以根据实际应用设置第二电压值，在此不作限定。
在具体实施时，在本公开实施例中，也可以将第三阈值调控信号端VS3设置为接收固定电压信号，例如设置为具有第三电压值的直流固定电压信号，以保证第四晶体管M4可以在输出阶段T2中可以尽可能的完全截止，以降低漏电流对第二上拉节点PU_2的漏电影响。具体地，在第四晶体管M4为P型晶体管时，可以将第三阈值调控信号端VS3设置为接收高电平的固定电压信号。进一步地，在显示装置采用不同的刷新频率时，可以根据实际应用设置第三电压值，例如显示装置采用较低的刷新频率时，由于移位寄存器工作在较低的刷新频率(例如1Hz)或保持状态时，可以将第三电压值设置为高压，以减少漏电，确保移位寄存器输出稳定性，从而移位寄存器不会工作异常。或者，显示装置采用较高的刷新频率时，由于移位寄存器工作在较高的刷新频率(例如60Hz、120Hz)时，可以将第三电压值设置为0V或负压，确保移 位寄存器的响应速度。当然，上述第三电压值可以根据实际应用环境来设计确定，在此不作限定。
在具体实施时，在第四晶体管M4为N型晶体管时，可以将第三阈值调控信号端VS3设置为接收低电平的固定电压信号。进一步地，在显示装置采用不同的刷新频率时，可以根据实际应用设置第三电压值，在此不作限定。
进一步地，为了减低传输信号的信号线，在具体实施时，在本公开实施例中，可以将第二阈值调控信号端VS2与第一阈值调控信号端VS1设置为接收同一信号。例如，图14a所示，第一晶体管M1的第二栅极与第二晶体管M2的第二栅极耦接，以均接收第一阈值调控信号端VS1的信号，以采用一条信号线向第一晶体管M1的第二栅极与第二晶体管M2的第二栅极输入信号。
进一步地，为了减低传输信号的信号线，在具体实施时，在本公开实施例中，也可以将第三阈值调控信号端VS3与第一阈值调控信号端VS1设置为接收同一信号。例如，图14a所示，第一晶体管M1的第二栅极与第四晶体管M4的第二栅极耦接，以均接收第一阈值调控信号端VS1的信号，以采用一条信号线向第一晶体管M1的第二栅极与第四晶体管M4的第二栅极输入信号。
进一步地，在具体实施时，在本公开实施例中，也可以将第三阈值调控信号端VS3、第二阈值调控信号端VS2以及第一阈值调控信号端VS1设置为接收同一信号。例如，图14a所示，第一晶体管M1的第二栅极、第二晶体管M2的第二栅极以及第四晶体管M4的第二栅极耦接，以均接收第一阈值调控信号端VS1的信号，以采用一条信号线向第一晶体管M1的第二栅极、第二晶体管M2的第二栅极以及第四晶体管M4的第二栅极输入信号。
下面以图14a所示的移位寄存器为例，结合图14b所示的信号时序图对本公开实施例提供的上述移位寄存器的工作过程作以描述。
具体地，选取如图14b所示的信号时序图中的输入阶段T1、输出阶段T2、复位阶段T3以及复位保持阶段T4四个阶段。
在输入阶段T1，IP＝0，CK1＝1，CK2＝0，VS1＝1。由于CK1＝1，因此第三晶体管M3截止。由于CK2＝0，因此第五晶体管M5导通，以将第一参考 信号端VREF1的低电平信号提供给下拉节点PD，使下拉节点PD的信号为低电平信号，以控制第七晶体管M7导通。导通的第七晶体管M7将第二参考信号端VREF2的高电平信号提供给信号输出端OP，使信号输出端OP输出高电平的信号。虽然由于VS1＝1，可以使第二晶体管M2的V th2左移，然而，由于CK2＝0并且IP＝0，因此第二晶体管M2还是会使第二上拉节点PU_2进行放电，以使第二上拉节点PU_2的信号为低电平信号。虽然由于VS1＝1，可以使第一晶体管M1的V th1左移，然而，由于第一参见信号VREF为低电平信号，并且，第一上拉节点PU_1的信号为高电平信号，从而使第一晶体管M1满足V gs1<V th1，以使第一晶体管M1导通。该阶段的工作过程可以参见图8在输入阶段T1中的工作过程，在此不作赘述。
在输入阶段T1之后且在输出阶段T2之前的工作过程，也可以参见图88在输入阶段T1之后且在输出阶段T2之前的工作过程，在此不作赘述。
输出阶段T2，IP＝1，CK1＝0，CK2＝1，VS1＝1。该阶段的工作过程可以参见图8在输出阶段T2中的工作过程，在此不作赘述。
复位阶段T3，IP＝1，CK1＝1，CK2＝0，VS1＝1。该阶段的其余工作过程可以参见图8在复位阶段T3中的工作过程，在此不作赘述。
复位保持阶段T4，IP＝1，CK1＝0，CK2＝1，VS1＝1。虽然，由于VS3＝1，可以使第四晶体管M4的V th4左移，然而，第四晶体管M4的栅极为低电平信号的电压，第四晶体管M4的源极电压为高电平信号的电压，则可以使得第四晶体管M4满足V gs4<V th4而导通。该阶段的其余工作过程可以参见图8在复位保持阶段T4中的工作过程，在此不作赘述。
基于同一发明构思，本公开实施例还提供了上述移位寄存器的驱动方法，其中，如图15所示，可以包括：
S100、输入阶段，输入电路根据输入信号端与第二时钟信号端的信号，控制第一晶体管的第一极的信号的电平；第一晶体管导通；输出电路响应于第一晶体管的第二极的信号，将第一时钟信号端的信号提供给信号输出端；
S200、输出阶段，第一晶体管的阈值电压响应于第一阈值调控信号端的 信号进行移动，第一晶体管截止；输出电路响应于第一晶体管的第二极的信号，将第一时钟信号端的信号提供给信号输出端；其中，第一阈值调控信号端的信号与第一参考信号端的信号的电平相反。
在具体实施时，在本公开实施例中，在输出阶段，第二晶体管的阈值电压响应于第二阈值调控信号端的信号进行移动，第二晶体管截止；第四晶体管的阈值电压响应于第三阈值调控信号端的信号进行移动，第四晶体管截止。
在具体实施时，在本公开实施例中，如图15所示，S100输入阶段，还可以包括：第五晶体管响应于第二时钟信号端的信号，将第一参考信号端的信号提供给第七晶体管的栅极；第六晶体管响应于第一晶体管的第一极的信号，将第二时钟信号端的信号提供给第七晶体管的栅极；第七晶体管响应于第七晶体管的栅极的信号将第二参考信号端的信号提供给信号输出端。
在具体实施时，在本公开实施例中，如图15所示，在输出阶段S200之后，驱动方法还可以包括：
S300、复位阶段，输入电路根据输入信号端与第二时钟信号端的信号，控制第一晶体管的第一极的信号的电平；第一晶体管将输入电路和输出电路导通；第五晶体管响应于第二时钟信号端的信号，将第一参考信号端的信号提供给第七晶体管的栅极；第七晶体管响应于第七晶体管的栅极的信号将第二参考信号端的信号提供给信号输出端。
在具体实施时，在本公开实施例中，在复位阶段S300之后，驱动方法还可以包括：
复位保持阶段，第一电容保持第七晶体管的栅极的信号；第七晶体管响应于其栅极的信号，将第二参考信号端的信号提供给信号输出端；上拉控制电路响应于第一时钟信号端和第七晶体管的栅极的信号，将第二参考信号端的信号提供给第二上拉节点。
其中，该驱动方法的驱动原理和具体实施方式与上述实施例移位寄存器的原理和实施方式相同，因此，该驱动方法可参见上述实施例中移位寄存器的具体实施方式进行实施，在此不再赘述。
基于同一发明构思，本公开实施例还提供了栅极驱动电路，如图16所示，包括级联的多个本公开实施例提供的上述任意移位寄存器SR(1)、SR(2)…SR(n-1)、SR(n)…SR(N-1)、SR(N)(共N个移位寄存器，1≤n≤N)；其中，第一级移位寄存器SR(1)的输入信号端IP被配置为与帧触发信号端STV耦接；
每相邻两个移位寄存器中，下一级移位寄存器SR(n)的输入信号端IP被配置为与上一级移位寄存器SR(n-1)的信号输出端OP耦接。
具体地，上述栅极驱动电路中的每个移位寄存器的具体结构与本公开上述移位寄存器在功能和结构上均相同，重复之处不再赘述。该栅极驱动电路可以应被配置为液晶显示面板中，也可以应被配置为电致发光显示面板中，在此不作限定。
具体地，在本公开实施例提供的上述栅极驱动电路中，如图16所示，各级移位寄存器SR(n)的第一参考信号端VREF1均与同一直流信号端vdd耦接，各级移位寄存器SR(n)的第二参考信号端VREF2均与同一直流信号端vss耦接。
具体地，在本公开实施例提供的上述栅极驱动电路中，如图16所示，第2k-1级移位寄存器的第一时钟信号端CK1和第2k级移位寄存器的第二时钟信号端CK2均与同一时钟端即第一时钟端ck1耦接；第2k-1级移位寄存器的第二时钟信号端CK2和第2k级移位寄存器的第一时钟信号端CK1均与同一时钟端即第二时钟端ck2耦接；其中，k为正整数。
具体地，在第一阈值调控信号端被配置为接收与第二时钟信号端信号的时序相同的时钟信号时，第2k-1级移位寄存器的第一阈值调控信号端和第2k级移位寄存器的第一阈值调控信号端均与同一时钟端即第三时钟端ck3耦接；第2k-1级移位寄存器的第一阈值调控信号端和第2k级移位寄存器的第一阈值调控信号端均与同一时钟端即第四时钟端ck4耦接。
具体地，在第三阈值调控信号端被配置为接收与第二时钟信号端信号的时序相同的时钟信号时，第2k-1级移位寄存器的第三阈值调控信号端和第2k 级移位寄存器的第三阈值调控信号端均与同一时钟端即第五时钟端ck5耦接；第2k-1级移位寄存器的第三阈值调控信号端和第2k级移位寄存器的第三阈值调控信号端均与同一时钟端即第六时钟端ck6耦接。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述栅极驱动电路。该显示装置解决问题的原理与前述移位寄存器相似，因此该显示装置的实施可以参见前述移位寄存器的实施，重复之处在此不再赘述。
在具体实施时，本公开实施例提供的上述显示装置可以为如图17所示的手机。当然，本公开实施例提供的上述显示装置也可以为平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的移位寄存器、其驱动方法、栅极驱动电路及显示装置，通过将第一晶体管设置为双栅型晶体管，其中，第一晶体管的第一栅极接收第一参考信号端，第一晶体管的第二栅极接收第一阈值调控信号端，可以使第一晶体管在输入阶段、复位阶段以及复位保持阶段导通。并且，可以至少在输出阶段中，通过第一阈值调控信号端的信号调控第一晶体管的阈值电压V th1，使第一晶体管的阈值电压V th1移动，以使第一晶体管在输出阶段尽可能的截止，可以保持第一上拉节点的信号的电平稳定，避免漏电对第一上拉节点的信号影响。从而提高信号输出端输出的信号的稳定性，进而有利于应用于低频驱动的显示装置中，有利于降低功耗。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (20)

  1. 一种移位寄存器，其中，包括：
    输入电路，被配置为分别与输入信号端以及第二时钟信号端耦接；
    第一晶体管，所述第一晶体管的第一极与所述输入电路的输出端耦接；且所述第一晶体管为双栅型晶体管；其中，所述第一晶体管的第一栅极被配置为与第一参考信号端耦接，所述第一晶体管的第二栅极被配置为与第一阈值调控信号端耦接；
    输出电路，被配置为分别与第一时钟信号端以及信号输出端耦接，且所述输出电路的控制端与所述第一晶体管的第二极耦接。
  2. 如权利要求1所述的移位寄存器，其中，所述输入电路包括：单栅型的第二晶体管；
    所述第二晶体管的栅极被配置为与所述第二时钟信号端耦接，所述第二晶体管的第一极被配置为与所述输入信号端耦接，所述第二晶体管的第二极与所述第一晶体管的第一极耦接。
  3. 如权利要求2所述的移位寄存器，其中，所述第一晶体管的第二栅极与所述第二晶体管的栅极耦接；或者，
    所述第一晶体管的第二栅极与所述第二晶体管的第一极耦接。
  4. 如权利要求1所述的移位寄存器，其中，所述输入电路包括：双栅型的第二晶体管；其中，所述第二晶体管的第一栅极被配置为与所述第二时钟信号端耦接，所述第二晶体管的第二栅极被配置为与第二阈值调控信号端耦接，所述第二晶体管的第一极被配置为与所述输入信号端耦接，所述第二晶体管的第二极与所述第一晶体管的第一极耦接。
  5. 如权利要求4所述的移位寄存器，其中，所述第二晶体管的第二栅极与所述第二晶体管的第一栅极耦接；或者，
    所述第二晶体管的第二栅极与所述第二晶体管的第一极耦接。
  6. 如权利要求4或5所述的移位寄存器，其中，所述第一晶体管的第二 栅极与所述第二晶体管的第一栅极耦接；或者，
    所述第一晶体管的第二栅极与所述第二晶体管的第一极耦接。
  7. 如权利要求1-6任一项所述的移位寄存器，其中，所述移位寄存器还包括：第五晶体管、第六晶体管、第七晶体管以及第一电容；
    所述第五晶体管的栅极被配置为与所述第二时钟信号端耦接，所述第五晶体管的第一极被配置为与所述第一参考信号端耦接，所述第五晶体管的第二极与所述第七晶体管的栅极耦接；
    所述第六晶体管的栅极与所述第一晶体管的第一极耦接，所述第六晶体管的第一极被配置为与所述第二时钟信号端耦接，所述第六晶体管的第二极与所述第七晶体管的栅极耦接；
    所述第七晶体管的第一极被配置为与所述第二参考信号端耦接，所述第七晶体管的第二极与所述信号输出端耦接；
    所述第一电容的第一端与所述第七晶体管的栅极耦接，所述第一电容的第二端被配置为与所述第二参考信号端耦接。
  8. 如权利要求7所述的移位寄存器，其中，所述移位寄存器还包括：上拉控制电路；其中，所述上拉控制电路的第一控制端被配置为与所述第一时钟信号端耦接，所述上拉控制电路的第二控制端与所述第七晶体管的栅极耦接，所述上拉控制电路的输入端被配置为与所述第二参考信号端耦接，所述上拉控制电路的输出端与所述第一晶体管的第一极耦接。
  9. 如权利要求8所述的移位寄存器，其中，所述上拉控制电路包括：第三晶体管和单栅型的第四晶体管；
    所述第三晶体管的栅极被配置为与所述第一时钟信号端耦接，所述第三晶体管的第一极与所述第一晶体管的第一极耦接，所述第三晶体管的第二极与所述第四晶体管的第一极耦接；
    所述第四晶体管的栅极与所述第七晶体管的栅极耦接，所述第四晶体管的第二极被配置为与所述第二参考信号端耦接。
  10. 如权利要求8所述的移位寄存器，其中，所述上拉控制电路包括： 第三晶体管和双栅型的第四晶体管；
    所述第三晶体管的栅极被配置为与所述第一时钟信号端耦接，所述第三晶体管的第一极与所述第一晶体管的第一极耦接，所述第三晶体管的第二极与所述第四晶体管的第一极耦接；
    所述第四晶体管的第一栅极与所述第七晶体管的栅极耦接，所述第四晶体管的第二栅极被配置为与第三阈值调控信号端耦接，所述第四晶体管的第二极被配置为与所述第二参考信号端耦接。
  11. 如权利要求10所述的移位寄存器，其中，所述第四晶体管的第二栅极与所述第七晶体管的栅极耦接；或者，
    所述第四晶体管的第二栅极与所述第五晶体管的栅极耦接。
  12. 如权利要求1-11任一项所述的移位寄存器，其中，所述输出电路包括：第八晶体管和第二电容；
    所述第八晶体管的栅极与所述第一晶体管的第二极耦接，所述第八晶体管的第一极被配置为与所述第一时钟信号端耦接，所述第八晶体管的第二极与所述信号输出端耦接；
    所述第二电容的第一端与所述第一晶体管的第二极耦接，所述第二电容的第二端与所述信号输出端耦接。
  13. 如权利要求7-11任一项所述的移位寄存器，其中，所述第一阈值调控信号端被配置为接收至少具有与所述第一参考信号端的信号的电平相反的信号；
    第二阈值调控信号端被配置为接收至少具有与所述第一参考信号端的信号的电平相反的信号；
    第三阈值调控信号端被配置为接收至少具有与所述第一参考信号端的信号的电平相反的信号。
  14. 如权利要求13所述的移位寄存器，其中，所述第一阈值调控信号端、第二阈值调控信号端以及第三阈值调控信号端中的至少一个信号端被配置为接收与所述第二时钟信号端的时序相同的时钟信号。
  15. 如权利要求13所述的移位寄存器，其中，所述第一阈值调控信号端、第二阈值调控信号端以及第三阈值调控信号端中的至少一个信号端被配置为接收固定电压信号。
  16. 一种栅极驱动电路，其中，包括多个级联的如权利要求1-15任一项所述的移位寄存器；
    第一极移位寄存器的输入信号端被配置为与帧触发信号端耦接；
    每相邻两个移位寄存器中，下一级移位寄存器的输入信号端被配置为与上一级移位寄存器的信号输出端耦接。
  17. 一种显示装置，其中，包括如权利要求16所述的栅极驱动电路。
  18. 一种如权利要求1-15任一项所述的移位寄存器的驱动方法，其中，包括：
    输入阶段，所述输入电路根据所述输入信号端与所述第二时钟信号端的信号，控制所述第一晶体管的第一极的信号的电平；所述第一晶体管导通；所述输出电路响应于所述第一晶体管的第二极的信号，将第一时钟信号端的信号提供给信号输出端；
    输出阶段，所述第一晶体管的阈值电压响应于所述第一阈值调控信号端的信号进行移动，所述第一晶体管截止；所述输出电路响应于所述第一晶体管的第二极的信号，将第一时钟信号端的信号提供给信号输出端；其中，所述第一阈值调控信号端的信号与所述第一参考信号端的信号的电平相反。
  19. 如权利要求18所述的驱动方法，其中，所述输入阶段还包括：第五晶体管响应于所述第二时钟信号端的信号，将所述第一参考信号端的信号提供给第七晶体管的栅极；第六晶体管响应于所述第一晶体管的第一极的信号，将所述第二时钟信号端的信号提供给所述第七晶体管的栅极；所述第七晶体管响应于所述第七晶体管的栅极的信号将第二参考信号端的信号提供给所述信号输出端；
    在所述输出阶段之后，所述驱动方法还包括：
    复位阶段，所述输入电路根据所述输入信号端与所述第二时钟信号端的 信号，控制所述第一晶体管的第一极的信号的电平；所述第一晶体管将所述输入电路和所述输出电路导通；所述第五晶体管响应于所述第二时钟信号端的信号，将所述第一参考信号端的信号提供给第七晶体管的栅极；所述第七晶体管响应于所述第七晶体管的栅极的信号将第二参考信号端的信号提供给所述信号输出端。
  20. 如权利要求18或19所述的驱动方法，其中，在所述输出阶段，第二晶体管的阈值电压响应于第二阈值调控信号端的信号进行移动，所述第二晶体管截止；第四晶体管的阈值电压响应于第三阈值调控信号端的信号进行移动，所述第四晶体管截止。
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