WO2023206196A1 - 驱动电路及其驱动方法、显示装置 - Google Patents

驱动电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2023206196A1
WO2023206196A1 PCT/CN2022/089751 CN2022089751W WO2023206196A1 WO 2023206196 A1 WO2023206196 A1 WO 2023206196A1 CN 2022089751 W CN2022089751 W CN 2022089751W WO 2023206196 A1 WO2023206196 A1 WO 2023206196A1
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WIPO (PCT)
Prior art keywords
transistor
signal input
input terminal
electrically connected
signal
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PCT/CN2022/089751
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English (en)
French (fr)
Inventor
张杨
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/089751 priority Critical patent/WO2023206196A1/zh
Priority to CN202280000923.XA priority patent/CN117321673A/zh
Priority to US18/022,452 priority patent/US20240265889A1/en
Publication of WO2023206196A1 publication Critical patent/WO2023206196A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation

Definitions

  • the present application relates to the field of display technology, and in particular, to a driving circuit, a driving method thereof, and a display device.
  • Gate Driver On Array is a technology that integrates a gate drive circuit on an array substrate.
  • the gate drive circuit includes multiple shift registers, each shift register corresponding to a row of gate lines. Multiple shift registers sequentially output scan signals.
  • an embodiment of the present application provides a driving circuit including a plurality of cascaded shift registers, where the shift registers include:
  • An input module electrically connected to the scan signal input end of the shift register and the first node respectively, and configured to charge the first node when receiving a scan signal from the scan signal input end;
  • the output module is electrically connected to the first clock signal input end of the shift register, the first node and the signal output end of the shift register respectively, and is configured to be controlled by the voltage of the first node. , output a scanning signal from the signal output terminal according to the first clock signal input from the first clock signal input terminal;
  • a pull-up module is electrically connected to the first node and the signal output terminal respectively, and is configured to pull up the voltage of the first node;
  • An adjustment module electrically connected to the scan signal input end, the signal output end and the first node respectively, and configured to pull down the voltage of the first node when a bootstrap action occurs in the adjustment module;
  • the pull-down module is electrically connected to the pull-down control signal input terminal of the shift register, the first power signal input terminal of the shift register and the first node respectively, and is configured to pull down the voltage of the first node. ;
  • a reset module is electrically connected to the pull-down module, the reset signal input terminal and the signal output terminal of the shift register respectively, and is configured to reset the driving circuit.
  • the input module includes a first transistor, the control electrode of the first transistor and the first electrode of the first transistor are both electrically connected to the scan signal input terminal, and the third A second terminal of a transistor is electrically connected to the first node.
  • the input module includes a first transistor, a control electrode of the first transistor is electrically connected to the scan signal input terminal, and a first electrode of the first transistor is connected to the shift
  • the second power signal input terminal of the register is electrically connected, and the second pole of the first transistor is electrically connected to the first node.
  • the output module includes a third transistor, a control electrode of the third transistor is electrically connected to the first node, and a first electrode of the third transistor is connected to the first clock.
  • the signal input terminal is electrically connected, and the second pole of the third transistor is electrically connected to the signal output terminal.
  • the reset module includes a second transistor and a fourth transistor, and the control electrode of the second transistor and the control electrode of the fourth transistor are respectively electrically connected to the reset signal input terminal;
  • the first pole of the second transistor is electrically connected to the first node, the second pole of the second transistor is electrically connected to the first power signal input terminal; the first pole of the fourth transistor is electrically connected to the first node.
  • the signal output terminal is electrically connected, and the second pole of the fourth transistor is electrically connected to the first power signal input terminal.
  • the pull-down module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor;
  • the first pole of the fifth transistor, the first pole of the eighth transistor and the control pole of the eighth transistor are all electrically connected to the pull-down control signal input terminal, and the control pole of the fifth transistor is electrically connected to the pull-down control signal input terminal.
  • the second electrode of the eighth transistor is electrically connected, the second electrode of the fifth transistor, the first electrode of the sixth transistor, the control electrode of the ninth transistor, and the control electrode of the tenth transistor are all Electrically connected to the second node, the second pole of the sixth transistor, the second pole of the seventh transistor, the second pole of the ninth transistor, and the second pole of the tenth transistor are all connected to the second node.
  • the first power signal input terminal is electrically connected, the control electrode of the sixth transistor, the control electrode of the seventh transistor, and the first electrode of the ninth transistor are all electrically connected to the first node, and the The first electrode of the seventh transistor is electrically connected to the control electrode of the fifth transistor, and the first electrode of the tenth transistor is electrically connected to the signal output terminal.
  • the pull-down control signal input terminal includes a second clock signal input terminal or a second power signal input terminal
  • the pull-down control signal input terminal includes a second clock signal input terminal
  • the second clock signal input to the second clock signal input terminal has the same period as the first clock signal input to the first clock signal input terminal. And the phase is opposite;
  • the pull-down control signal input terminal includes a second power signal input terminal
  • the input signals of the first power signal input terminal and the second power signal input terminal have opposite polarities.
  • the pull-up module includes a first capacitor, a first electrode of the first capacitor is electrically connected to the first node, and a second electrode of the first capacitor is electrically connected to the signal The output terminals are electrically connected.
  • the adjustment module includes an eleventh transistor, a twelfth transistor, a thirteenth transistor and a second capacitor;
  • the first pole of the eleventh transistor, the first pole of the twelfth transistor and the control pole of the twelfth transistor are all electrically connected to the scan signal input terminal, and the control pole of the eleventh transistor
  • the second pole of the twelfth transistor and the first pole of the thirteenth transistor are all electrically connected to the third node, and the second pole of the eleventh transistor is connected to the first pole of the second capacitor.
  • the electrodes are electrically connected, the second electrode of the second capacitor and the second pole of the thirteenth transistor are both electrically connected to the first node, and the control electrode of the thirteenth transistor is electrically connected to the signal output terminal. connect.
  • the input module includes a first transistor
  • the output module includes a third transistor
  • the reset module includes a second transistor and a fourth transistor
  • the pull-up module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor
  • the adjustment module includes an eleventh transistor, a twelfth transistor and a thirteenth transistor
  • each transistor is an N-type transistor
  • the first clock signal includes a first level signal and a second level signal
  • the voltage of the first level signal is the same as the voltage of the first DC power signal input by the first power signal input terminal.
  • the voltage of the first level signal is smaller than the voltage of the second level signal.
  • the driving circuit when the driving circuit includes a second power signal input terminal, the voltage of the second DC power signal input by the second power signal input terminal is a positive voltage, and the first power supply The voltage of the first DC power signal input at the signal input terminal is a negative voltage.
  • the current value in the eighth transistor is greater than that in the fifth transistor. current value.
  • embodiments of the present application provide a display device, including the driving circuit as described above.
  • embodiments of the present application provide a driving method, which is applied to driving the driving circuit as described above.
  • the method includes:
  • the scan signal output by the shift register of the previous stage is input to the scan signal input end
  • the first clock signal is input to the first clock signal input end
  • the second level signal is input to the pull-down control signal input end
  • the second level signal is input to the pull-down control signal input end.
  • the first power signal input terminal inputs the first DC power signal
  • the second level signal is input to the first clock signal input terminal, the first level signal is input to the pull-down control signal input terminal, and the first DC power signal is input to the first power signal input terminal;
  • the reset signal is input to the reset signal input terminal, and the first DC power signal is input to the first power signal input terminal.
  • inputting a second level signal to the pull-down control signal input terminal includes:
  • a second DC power supply signal is input to the pull-down control signal input terminal, wherein the voltage of the second DC power supply signal is a positive voltage, and the voltage of the first DC power supply signal is a negative voltage.
  • inputting a second level signal to the pull-down control signal input terminal includes inputting a second clock signal to the pull-down control signal input terminal, wherein the first clock signal and the third level signal are input to the pull-down control signal input terminal.
  • the first clock signal and the second clock signal each include a first level signal and a second level signal, and the voltage of the first level signal is the same as the voltage of the first DC power supply signal, so The voltage of the first level signal is smaller than the voltage of the second level signal.
  • Figure 1 Figure 7 and Figure 8 are schematic structural diagrams of three driving circuits provided by embodiments of the present application.
  • Figure 2 is a schematic diagram of the cascade relationship between shift registers according to an embodiment of the present application.
  • FIG. 3 is a timing diagram of the drive circuit shown in Figure 1;
  • FIGS 4 to 6 are schematic diagrams of the driving principle of the driving circuit in Figure 1 under the driving timing sequence in Figure 3;
  • FIG. 9 is a flow chart of a driving method for a driving circuit provided by an embodiment of the present application.
  • the source and drain of the transistor are symmetrical, the source and drain can be interchanged.
  • one of the source electrode and the drain electrode of the transistor is called a first electrode, and the other of the source electrode and the drain electrode is called a second electrode.
  • the term "electrical connection” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.
  • the LCD panel is composed of a vertical and horizontal array pixel matrix.
  • the gate drive circuit outputs the gate scan signal and scans and accesses each pixel line by line.
  • the gate drive circuit is used to generate the gate scan voltage of the pixel, GOA.
  • GOA Gate Driver On Array, array substrate row drive
  • Each GOA unit acts as a shift register to transfer the scanning signal to the next GOA unit in sequence, turning it on row by row.
  • the transistor switch completes the data signal input of the pixel unit.
  • the high level (Vgh) of the scanning signal needs to reach a voltage of more than 25V; at the same time, the capacitor boost module of the existing GOA circuit can enable some key nodes of the GOA internal circuit
  • the voltage is greater than or equal to double the high level (Vgh) voltage, reaching more than 50V.
  • the embodiment of the present application provides a driving circuit, including multiple cascaded shift registers (GOA units) as shown in Figure 2, wherein for the first-stage shift register (GOA unit 1), it can be based on The STV signal and clock signal (including CLK and CLKB) output the first scanning signal G[1]; the first scanning signal G[1] output by the first-stage shift register is used as the input signal of the second-stage shift register ( Input), and the output signal G[2] of the second-stage shift register serves as the reset signal (Reset) of the first-stage shift register.
  • the STV signal and clock signal including CLK and CLKB
  • the scan signal output by the previous stage shift register is used as the input signal of the subsequent stage shift register
  • the scan signal output by the subsequent stage shift register is used as the input signal of the previous stage shift register.
  • the second stage and subsequent shift registers (GOA unit 2, GOA unit 3...GOA unit N) output the scanning signal of the current stage shift register based on the scanning signal output by the previous stage shift register and the received clock signal. , wherein the output end of a shift register is electrically connected to a gate line to input a corresponding scanning signal into the gate line.
  • the shift register includes:
  • the input module 1 is electrically connected to the scan signal input terminal Input of the shift register and the first node PU respectively, and is configured to charge the first node PU when receiving the scan signal from the scan signal input terminal Input;
  • the output module 2 is electrically connected to the first clock signal input terminal CLK of the shift register, the first node PU and the signal output terminal Output of the shift register respectively, and is configured to control the voltage of the first node PU according to the first
  • a first clock signal is input from a clock signal input terminal CLK, and a scanning signal G[N] is output from the signal output terminal Output;
  • the pull-up module 3 is electrically connected to the first node PU and the signal output terminal Output respectively, and is configured to pull up the voltage of the first node PU;
  • the adjustment module 4 is electrically connected to the scanning signal input terminal Input, the signal output terminal Output and the first node PU respectively, and is configured to pull down the voltage of the first node PU when the bootstrap action of the adjustment module 4 occurs;
  • the pull-down module 5 is respectively connected to the pull-down control signal input terminal of the shift register (for example, including the second clock signal input terminal CLKB in Figure 1 or the second power supply signal input terminal VDD in Figure 7) and the first power supply of the shift register.
  • the signal input terminal VSS is electrically connected to the first node PU and is configured to pull down the voltage of the first node PU;
  • the reset module 6 is electrically connected to the pull-down module 5 and the reset signal input terminal Reset and the signal output terminal Output of the shift register respectively, and is configured to reset the driving circuit.
  • first node PU as well as the second node PD and the third node PB in the following are only defined for the convenience of describing the circuit structure.
  • the first node PU, the second node PD and the third node PB are not an actual circuit unit. .
  • the input module 1 is electrically connected to the scan signal input terminal Input of the shift register and the first node PU respectively.
  • the input module 1 is electrically connected to the scan signal input terminal Input, the first node PU and the second power signal input terminal VDD of the shift register respectively.
  • the pull-down module 5 is electrically connected to the second clock signal input terminal CLKB of the shift register, the first power signal input terminal VSS of the shift register and the first node PU respectively.
  • the pull-down module 5 is electrically connected to the second power signal input terminal VDD of the shift register, the first power signal input terminal VSS of the shift register and the first node PU respectively.
  • the scanning signal can be output in sequence to Control the pixels in the array substrate to scan line by line; on the other hand, during the driving process of the driving circuit, after the pull-up module 3 pulls up the voltage of the first node PU, and when the pull-up module 3 bootstraps, the first The voltage of the node PU continues to rise, and the adjustment module 4 can discharge the scan signal input terminal Input to lower the voltage of the first node PU, thereby preventing the voltage of the first node PU from being too high, and thereby avoiding the voltage connection with the first node PU.
  • the connected devices have problems with reduced lifespan or unstable performance due to excessive voltage, which improves the stability of the drive circuit.
  • the input module 1 includes a first transistor M1.
  • the control electrode of the first transistor M1 and the first electrode of the first transistor M1 are both electrically connected to the scan signal input terminal Input.
  • the second pole of the first transistor M1 is electrically connected to the first node PU.
  • the input module 1 includes a first transistor M1 , a control electrode of the first transistor M1 is electrically connected to the scan signal input terminal Input, and a first electrode of the first transistor M1 is connected to the shift input terminal.
  • the second power signal input terminal VDD of the bit register is electrically connected, and the second pole of the first transistor M1 is electrically connected to the first node PU.
  • the output module 2 includes a third transistor M3.
  • the control electrode of the third transistor M3 is electrically connected to the first node PU.
  • the first electrode of the third transistor M3 is electrically connected to the first node PU.
  • the clock signal input terminal CLK is electrically connected, and the second pole of the third transistor M3 is electrically connected to the signal output terminal Output.
  • the reset module 6 includes a second transistor M2 and a fourth transistor M4.
  • the control electrode of the second transistor M2 and the control electrode of the fourth transistor M4 are respectively electrically connected to the reset signal input terminal Reset;
  • the first pole of the second transistor M2 is electrically connected to the first node PU, the second pole of the second transistor M2 is electrically connected to the first power signal input terminal VSS; the first pole of the fourth transistor M4 is electrically connected to the signal output terminal Output. , the second pole of the fourth transistor M4 is electrically connected to the first power signal input terminal VSS.
  • the pull-down module 5 includes a fifth transistor M5 , a sixth transistor M6 , a seventh transistor M7 , an eighth transistor M8 , a ninth transistor M9 and a tenth transistor. M10;
  • the first pole of the fifth transistor M5, the first pole of the eighth transistor M8, and the control pole of the eighth transistor M8 are all connected to the pull-down control signal input terminal (for example, including the second clock signal input terminal CLKB in Figure 1 or the second clock signal input terminal CLKB in Figure 7
  • the second power signal input terminal VDD is electrically connected
  • the control electrode of the fifth transistor M5 is electrically connected to the second electrode of the eighth transistor M8, the second electrode of the fifth transistor M5, the first electrode of the sixth transistor M6, and the
  • the control electrodes of the ninth transistor M9 and the control electrode of the tenth transistor M10 are both electrically connected to the second node PD.
  • the second electrode of the sixth transistor M6, the second electrode of the seventh transistor M7, and the second electrode of the ninth transistor M9 , and the second electrode of the tenth transistor M10 are all electrically connected to the first power signal input terminal VSS.
  • the control electrode of the sixth transistor M6, the control electrode of the seventh transistor M7, and the first electrode of the ninth transistor M9 are all electrically connected to the first power signal input terminal VSS.
  • One node PU is electrically connected
  • the first pole of the seventh transistor M7 is electrically connected to the control pole of the fifth transistor M5
  • the first pole of the tenth transistor M10 is electrically connected to the signal output terminal Output.
  • the pull-down control signal input terminal includes the second clock signal input terminal CLKB in Figure 1 or the second power signal input terminal VDD in Figure 7;
  • the pull-down control signal input terminal includes the second clock signal input terminal CLKB, as shown in FIG. 3 , the second clock signal CLKB signal input by the second clock signal input terminal and the first clock signal input by the first clock signal input terminal
  • the signal CLK signal has the same period and opposite phase
  • the pull-down control signal input terminal includes the second power signal input terminal VDD
  • the input signals of the first power signal input terminal VSS and the second power signal input terminal VDD have opposite polarities.
  • the first power signal input terminal VSS inputs a DC power signal with a negative voltage
  • the second power signal input terminal VDD inputs a DC power signal with a positive voltage
  • the pull-up module 3 includes a first capacitor C1 , a first electrode of the first capacitor C1 is electrically connected to the first node PU, and a second electrode of the first capacitor C1 is electrically connected to the first node PU.
  • the signal output terminal Output is electrically connected.
  • the adjustment module 4 includes an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13 and a second capacitor C2;
  • the first pole of the eleventh transistor M11, the first pole of the twelfth transistor M12, and the control pole of the twelfth transistor M12 are all electrically connected to the scan signal input terminal Input.
  • the second pole of the transistor M12 and the first pole of the thirteenth transistor M13 are both electrically connected to the third node PB.
  • the second pole of the eleventh transistor M11 is electrically connected to the first electrode of the second capacitor C2.
  • the second capacitor C2 The second electrode of the transistor M13 and the second pole of the thirteenth transistor M13 are both electrically connected to the first node PU, and the control pole of the thirteenth transistor M13 is electrically connected to the signal output terminal Output.
  • the above-mentioned transistor may be a thin film transistor or a metal oxide semiconductor field effect transistor, which is not limited herein.
  • the driving circuit provided in the embodiment of the present application is explained by taking the above-mentioned transistors as N-type transistors as an example.
  • all the above-mentioned transistors can also be P-type transistors.
  • the design principle is similar to that of the present invention, and it also falls within the scope of protection of the present invention.
  • the N-type transistor is turned on at a high level and turned off at a low level; the P-type transistor is turned on at a low level and turned off at a high level.
  • the input module 1 includes a first transistor M1
  • the output module 2 includes a third transistor M3
  • the reset module 6 includes a second transistor M2 and a fourth transistor M4
  • the pull-up module 5 includes a fifth transistor M5.
  • the adjustment module 4 includes an eleventh transistor M11, a twelfth transistor M12 and a thirteenth transistor M13; in each When the transistors are all N-type transistors, the first clock signal CLK signal includes a first level signal and a second level signal, and the voltage of the first level signal is equal to the first DC input from the first power signal input terminal VSS.
  • the power supply signal VSS signal has the same voltage, and the voltage of the first level signal is smaller than the voltage of the second level signal.
  • the first level is a low level (for example, the voltage is Vgl), and the second level is a high level (for example, the voltage is Vgh).
  • the low-level signal in the first clock signal CLK signal has the same voltage as the first DC power supply signal VSS signal.
  • the second DC power signal VDD signal input by the second power signal input terminal VDD is The voltage is a positive voltage
  • the voltage of the first DC power signal VSS signal input to the first power signal input terminal VSS is a negative voltage.
  • the pull-down control signal input terminal includes a second power signal input terminal VDD.
  • the first pole of the first transistor M1 in the input module 1 is electrically connected to the second power signal input terminal VDD.
  • the pull-down control signal input terminal includes the second power signal input terminal VDD or the second clock signal input terminal CLKB;
  • the pull-down control signal input terminal includes the second clock signal input terminal CLKB
  • the second clock signal CLKB signal input by the second clock signal input terminal CLKB and the third clock signal CLKB signal input by the first clock signal input terminal CLK A clock signal CLK signal has the same period and opposite phase.
  • the current value in the eighth transistor M8 is greater than the fifth transistor M5 the current value in .
  • the seventh transistor M7 since the seventh transistor M7 is turned on, the low-level signal input from the first power signal input terminal VSS controls the fifth transistor M5 to be turned off through the seventh transistor M7, thereby preventing the voltage of the second node PD from being pulled up.
  • the mark “H” represents that the input signal is a high-level signal
  • the mark “L” represents that the input signal is a low-level signal.
  • the middle mark G[N-1] represents that the input is the scanning signal G[N-1] output by the upper-level shift register. It can be understood that the input scanning signal G[N-1] output by the upper-level shift register is The ports are all scanning signal input terminals Input.
  • the mark G[N] represents the output terminal Output of this stage shift register, and the output scanning signal is.
  • the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12 and the thirteenth transistor M13 are all N-type transistors.
  • the driving circuit shown in Figure 1 as an example, combined with the input of each port in this case The signal timing, the working principle of the drive circuit provided in this embodiment will be introduced in detail. It should be noted that in Figures 4 to 6, the transistor turning off is marked by " ⁇ ”, and the transistor turning on is marked by " ⁇ ".
  • Figure 3 shows the timing diagram of the signals input (or input) to each port during one working cycle.
  • the scan signal input terminal Input inputs a high level signal H
  • the first clock signal input terminal CLK inputs a low level signal L
  • the second clock signal input terminal CLK inputs a low level signal L.
  • the clock signal input terminal CLKB inputs a high-level signal H
  • the reset signal input terminal Reset inputs a low-level signal L
  • the first power signal input terminal VSS inputs a low-level signal L.
  • the first transistor M1 is turned on, and the scanning signal
  • the input terminal Input inputs a high-level signal H to charge the first node PU through the first transistor M1.
  • the first node PU is high-level and the voltage is Vgh.
  • the third transistor M3 is turned on, and the first clock signal input terminal CLK passes The third transistor M3 transmits the low-level signal L to the signal output terminal Output, and the signal output terminal Output outputs the low-level signal Low; the eleventh transistor M11 and the twelfth transistor M12 are turned on, and the thirteenth transistor M13 is turned off. , the third node PB is high level, and the voltage is Vgh; the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are turned on, the second transistor M2, the fourth transistor M4 and the ninth transistor M9 and the tenth transistor M10 are turned off.
  • the actual throughput of the eighth transistor M8 is The current is greater than the current through the fifth transistor M5.
  • the first power signal input terminal VSS inputs a low level signal L to control the fifth transistor M5 through the seventh transistor M7, so that the voltage of the second node PD is not affected by the second clock signal.
  • the input terminal CLKB inputs a high-level signal H and pulls it high, but it is still in a low-level state.
  • the scan signal input terminal Input inputs a low level signal L
  • the first clock signal input terminal CLK inputs a high level signal H
  • the second clock signal input terminal CLK inputs a high level signal H.
  • the clock signal input terminal CLKB inputs a low-level signal L
  • the reset signal input terminal Reset inputs a low-level signal L
  • the first power signal input terminal VSS inputs a low-level signal L.
  • the first node PU maintains the previous stage.
  • the first transistor M1 is turned off
  • the second transistor M2, the ninth transistor M9, the fifth transistor M5, the eighth transistor M8, the fourth transistor M4 and the tenth transistor M10 are turned off
  • the seventh transistor M7 is turned on, and the first clock signal input terminal CLK transmits the high-level signal H to the signal output terminal Output through the third transistor M3.
  • the voltage of the signal output terminal Output jumps and changes from the low level in the previous stage. becomes the high level at this time, an induced voltage difference is generated at the first node PU of the first storage capacitor C1.
  • the voltage of the first node PU continues to increase, and the voltage The value tends from Vgh to 2Vgh.
  • the thirteenth transistor M13 Under the control of the high-level signal at the signal output terminal Output (G[N] is high level at this time), the thirteenth transistor M13 is turned on, and the low-level signal input at the scanning signal input terminal Input Under the control of the flat signal (G[N-1] is low level at this time), the twelfth transistor M12 is quickly turned off, and the third node PB discharges to the first power signal input terminal VSS through the thirteenth transistor M13.
  • the voltage of node PB is pulled down from high level to low level, and the current passing through the eleventh transistor M11 gradually becomes smaller until it is cut off.
  • the scanning signal input terminal Input input The low level signal (G[N-1] is low level at this time) can be transmitted to an electrode of the second capacitor C2 through the eleventh transistor M11, causing the second capacitor C2 to generate an induction at the first node PU
  • the voltage difference due to the bootstrap effect of the second capacitor C2, causes the voltage of the first node PU to be pulled down.
  • the voltage value of the first node PU increases.
  • Vth threshold voltage
  • the scan signal input terminal Input inputs a low level signal L
  • the first clock signal input terminal CLK inputs a low level signal L
  • the second clock signal input terminal CLK inputs a low level signal L.
  • the clock signal input terminal CLKB inputs a high-level signal H
  • the reset signal input terminal Reset inputs a high-level signal H
  • the first power signal input terminal VSS inputs a low-level signal L.
  • the second transistor M2 and the fourth transistor M4 The fifth transistor M5 and the eighth transistor M8 are turned on, the ninth transistor M9 and the tenth transistor M10 are turned on, and the voltage at the first node PU and the voltage of the signal output terminal Output are both pulled low and reset.
  • the driving timing provided in this embodiment is only one case using the circuit structure diagram shown in Figure 1 as an example.
  • the circuit structure diagrams shown in Figures 7 and 8 the The timing can also be adjusted accordingly and is not limited here.
  • each transistor may also be a P-type transistor.
  • each transistor is a P-type transistor, its specific timing is in reverse phase with the timing in FIG. 3 .
  • An embodiment of the present application provides a display device including the driving circuit as described above.
  • the above-mentioned display device can be an LCD (Liquid Crystal Display), as well as any product or component with a display function such as a television, a digital camera, a mobile phone, a tablet computer, etc. including these display devices.
  • the above-mentioned display device has the characteristics of good picture brightness uniformity, good display effect, and high product quality.
  • Embodiments of the present application provide a driving method, which is applied to driving the driving circuit as described above.
  • the method includes:
  • the first stage T1 i.e. input stage
  • the scan signal output by the previous stage shift register to the scan signal input terminal Input input the first clock signal to the first clock signal input terminal CLK
  • pull down the control signal input terminal For example, including the second clock signal input terminal CLKB in Figure 1 or the second power signal input terminal VDD in Figure 7) input the second level signal, and input the first DC power signal to the first power signal input terminal VSS;
  • the step of inputting a second level signal to the pull-down control signal input terminal includes: S9011: inputting a second clock signal CLKB signal to the pull-down control signal input terminal, where the first clock signal and the second level signal are input to the pull-down control signal input terminal.
  • the clock signals have the same period and opposite phases;
  • the scan signal input terminal Input inputs a high-level signal H
  • the first clock signal input terminal CLK inputs a low-level signal L
  • the second clock signal input terminal CLKB inputs a high-level signal H
  • the reset signal input terminal Reset inputs a low-level signal L
  • the first power signal input terminal VSS inputs a low-level signal L.
  • the first transistor M1 is turned on, and the scan signal input terminal Input inputs a high-level signal H to charge the first node PU through the first transistor M1.
  • One node PU is high level, and the voltage value is Vgh
  • the third transistor M3 is turned on, the first clock signal input terminal CLK transmits the low level signal L to the signal output terminal Output through the third transistor M3, and the signal output terminal Output outputs Low level signal Low; the eleventh transistor M11 and the twelfth transistor M12 are turned on, and the thirteenth transistor M13 is turned off.
  • the third node PB is high level, and the voltage value is Vgh; the fifth transistor M5, The sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are turned on, and the second transistor M2, the fourth transistor M4, the ninth transistor M9 and the tenth transistor M10 are turned off.
  • the eighth transistor M8 and the ninth transistor The size ratio of the transistor M9, and by designing the size ratio of the eighth transistor M8 and the fifth transistor M5, make the actual current passing through the eighth transistor M8 larger than the current passing through the fifth transistor M5.
  • the first power signal input terminal VSS input The low-level signal L can control the fifth transistor M5 through the seventh transistor M7, so that the voltage of the second node PD is not pulled high by the high-level signal H input to the second clock signal input terminal CLKB and remains in a low-level state.
  • the second stage T2 i.e., the output stage
  • the second level signal is input to the first clock signal input terminal CLK
  • the first level signal is input to the pull-down control signal input terminal
  • the second level signal is input to the first power signal input terminal VSS.
  • the step of inputting a second level signal to the pull-down control signal input terminal includes: S9011: inputting a second clock signal CLKB signal to the pull-down control signal input terminal, where the first clock signal and the second level signal are input to the pull-down control signal input terminal.
  • the clock signals have the same period and opposite phases;
  • the scan signal input terminal Input inputs a low-level signal L
  • the first clock signal input terminal CLK inputs a high-level signal H
  • the second clock signal input terminal CLKB inputs a low-level signal L
  • the reset signal input terminal Reset inputs a low-level signal L
  • the first power signal input terminal VSS inputs the low-level signal L.
  • the first node PU maintains the voltage Vgh of the previous stage
  • the first transistor M1 is turned off
  • the second transistor M2, the ninth transistor M9, and the fifth transistor M5, the eighth transistor M8, the fourth transistor M4, and the tenth transistor M10 are turned off
  • the third transistor M3, the sixth transistor M6, and the seventh transistor M7 are turned on
  • the first clock signal input terminal CLK outputs a signal through the third transistor M3.
  • the terminal Output transmits a high-level signal H, and the voltage of the signal output terminal Output jumps and changes from the low level in the previous stage to the high level at this time, generating a voltage at the first node PU of the first storage capacitor C1.
  • the induced voltage difference due to the bootstrapping effect of the first storage capacitor C1, causes the voltage of the first node PU to continue to increase, and the voltage tends from Vgh to 2Vgh, under the control of the signal output terminal Output high level signal G[N] , the thirteenth transistor M13 is turned on, and under the control of the low-level signal input from the scanning signal input terminal Input (G[N-1] is low level at this time), the twelfth transistor M12 is quickly turned off, and the third node PB discharges to the first power signal input terminal VSS through the thirteenth transistor M13, and the voltage of the third node PB is pulled low. At this time, the eleventh transistor M11 is pulled low from high level to low level.
  • the passing current gradually becomes smaller until it is cut off.
  • the eleventh transistor M11 When there is current passing through the eleventh transistor M11, the low-level signal input to the scanning signal input terminal Input (G[N-1] is low level at this time) can pass through the eleventh transistor M11.
  • the eleventh transistor M11 is transmitted to an electrode of the second capacitor C2, causing the second capacitor C2 to generate an induced voltage difference at the first node PU. Due to the bootstrapping effect of the second capacitor C2, the voltage of the first node PU is Pulled down, finally, under the joint action of the first capacitor C1 and the second capacitor C2, the voltage of the first node PU rises to about 1.5Vgh, which avoids the transistor whose gate is electrically connected to the first node PU due to excessive voltage.
  • the problem of threshold voltage (Vth) drift caused thereby improves the performance stability of the transistor in the drive circuit and increases the service life of the transistor.
  • the reset signal is input to the reset signal input terminal Reset, and the first DC power signal is input to the first power signal input terminal VSS.
  • the scan signal input terminal Input inputs a low-level signal L
  • the first clock signal input terminal CLK inputs a low-level signal L
  • the second clock signal input terminal CLKB inputs a high-level signal H
  • the reset signal input terminal Reset inputs a high-level signal H
  • the first power signal input terminal VSS inputs a low level signal L.
  • the second transistor M2 and the fourth transistor M4 are turned on
  • the fifth transistor M5 and the eighth transistor M8 are turned on
  • the ninth transistor M9 and the tenth transistor M9 are turned on.
  • the transistor M10 is turned on, and the voltage at the first node PU and the voltage at the signal output terminal Output are both pulled low to reset.
  • Embodiments of the present application provide a driving method for a driving circuit.
  • scanning signals can be output sequentially to control the progressive scanning of pixels in an array substrate;
  • the adjustment module 4 can discharge the scan signal input terminal Input to Pull down the voltage of the first node PU, thereby preventing the voltage of the first node PU from being too high, thereby avoiding the problem of reduced life or unstable performance of the device electrically connected to the first node PU due to excessive voltage, and improving the driving circuit stability.
  • the driving timing of this driving method is simple and easy to implement.
  • the step of inputting a second level signal to the pull-down control signal input terminal includes:
  • inputting a second level signal to the pull-down control signal input terminal includes inputting a second clock signal CLKB signal to the pull-down control signal input terminal, where the first clock signal CLK signal and the second clock signal CLKB When the signals have the same period and opposite phases,
  • the first clock signal CLK signal and the second clock signal CLKB signal both include a first level signal (low level signal) and a second level signal (high level signal).
  • the voltage of the first level signal is the same as the first direct level signal.
  • the voltage of the current power signal VSS signal is the same, and the voltage of the first level signal is smaller than the voltage of the second level signal.

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Abstract

本申请提供了一种驱动电路及其驱动方法、显示装置，涉及显示技术领域，该驱动电路包括输入模块、输出模块、上拉模块、调节模块、下拉模块和复位模块，在上拉模块拉高第一节点的电压后，且上拉模块发生自举作用时，第一节点的电压持续升高，调节模块能够对扫描信号输入端放电，以拉低第一节点的电压，从而避免第一节点的电压过大，进而避免了与第一节点电连接的器件因电压过大造成寿命降低或性能不稳定的问题，提高了驱动电路的稳定性。

Description

驱动电路及其驱动方法、显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种驱动电路及其驱动方法、显示装置。
背景技术
阵列基板行驱动(Gate Driver On Array，简称GOA)是一种将栅极驱动电路集成于阵列基板上的技术，栅极驱动电路包括多个移位寄存器，每个移位寄存器对应一行栅线，多个移位寄存器依次输出扫描信号。随着显示技术的快速发展，栅极驱动电路的技术趋于成熟，行业内对栅极驱动电路中移位寄存器的性能要求也越来越高。
发明内容
本申请的实施例采用如下技术方案：
第一方面，本申请的实施例提供了一种驱动电路，包括多个级联的移位寄存器，所述移位寄存器包括：
输入模块，分别与所述移位寄存器的扫描信号输入端和第一节点电连接，被配置为在接收到所述扫描信号输入端的扫描信号时，向所述第一节点充电；
输出模块，分别与所述移位寄存器的第一时钟信号输入端、所述第一节点和所述移位寄存器的信号输出端电连接，被配置为在所述第一节点的电压的控制下，根据所述第一时钟信号输入端输入的第一时钟信号，从所述信号输出端输出扫描信号；
上拉模块，分别与所述第一节点和所述信号输出端电连接，被配置为拉高所述第一节点的电压；
调节模块，分别与所述扫描信号输入端、所述信号输出端和所述第一节点电连接，被配置为在所述调节模块发生自举作用时拉低所述第一节点的电压；
下拉模块，分别与所述移位寄存器的下拉控制信号输入端、所述移位寄存器的第一电源信号输入端和所述第一节点电连接，被配置为拉低所述第一节点的电压；
复位模块，分别与所述下拉模块、所述移位寄存器的复位信号输入端和所述信号输出端电连接，被配置为对所述驱动电路进行复位。
在本申请的一些实施例中，所述输入模块包括第一晶体管，所述第一晶体管的控制极和所述第一晶体管的第一极均与所述扫描信号输入端电连接，所述第一晶体管的第二极与所述第一节点电连接。
在本申请的一些实施例中，所述输入模块包括第一晶体管，所述第一晶体管的控制极与所述扫描信号输入端电连接，所述第一晶体管的第一极与所述移位寄存器的第二电源信号输入端电连接，所述第一晶体管的第二极与所述第一节点电连接。
在本申请的一些实施例中，所述输出模块包括第三晶体管，所述第三晶体管的控制极与所述第一节点电连接，所述第三晶体管的第一极与所述第一时钟信号输入端电连接，所述第三晶体管的第二极与所述信号输出端电连接。
在本申请的一些实施例中，所述复位模块包括第二晶体管和第四晶体管，所述第二晶体管的控制极和所述第四晶体管的控制极分别与所述复位信号输入端电连接；
所述第二晶体管的第一极与所述第一节点电连接，所述第二晶体管的第二极与所述第一电源信号输入端电连接；所述第四晶体管的第一极与所述信号输出端电连接，所述第四晶体管的第二极与所述第一电源信号输入端电连接。
在本申请的一些实施例中，所述下拉模块包括第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管和第十晶体管；
所述第五晶体管的第一极、所述第八晶体管的第一极以及所述第八晶体管的控制极均与所述下拉控制信号输入端电连接，所述第五晶体管的控制极与所述第八晶体管的第二极电连接，所述第五晶体管的第二极、所述第六晶体管的第一极、所述第九晶体管的控制极、以及所述第十晶体管的控制极均与第二节点电连接，所述第六晶体管的第二极、所述第七晶体管的第二极、所述第九晶体管的第二极、以及所述第十晶体管的第二极均与所述第一电源信号输入端电连接，所述第六晶体管的控制极、所述第七晶体管的控制极、以及所述第九晶体管的第一极均与所述第一节点电连接，所述第七晶体管的第一极与所述第五晶体管的控制极电连接，所述第十晶体管的第一极与所述信号输出端电连接。
在本申请的一些实施例中，所述下拉控制信号输入端包括第二时钟信号输入端或第二电源信号输入端；
在所述下拉控制信号输入端包括第二时钟信号输入端的情况下，所述第二时钟信号输入端输入的第二时钟信号与所述第一时钟信号输入端输入的第一时钟信号的周期相同且相位相反；
在所述下拉控制信号输入端包括第二电源信号输入端的情况下，所述第一电源信号输入端和所述第二电源信号输入端的输入的信号的极性相反。
在本申请的一些实施例中，所述上拉模块包括第一电容器，所述第一电容器的第一电极与所述第一节点电连接，所述第一电容器的第二电极与所述信号输出端电连接。
在本申请的一些实施例中，所述调节模块包括第十一晶体管、第十二晶体管、第十三晶体管和第二电容器；
所述第十一晶体管的第一极、所述第十二晶体管的第一极和所述第十二晶体管的控制极均与所述扫描信号输入端电连接，所述第十一晶体管的控制极、所述第十二晶体管的第二极和所述第十三晶体管的第一极均与第三节点电连接，所述第十一晶体管的第二极与所述第二电容器的第一电极电连接，所述第二电容器的第二电极和所述第十三晶体管的第二极均与所述第一节点电连接，所述第十三晶体管的控制极与所述信号输出端电连接。
在本申请的一些实施例中，所述输入模块包括第一晶体管，所述输出模块包括第三晶体管，所述复位模块包括第二晶体管和第四晶体管，所述上拉模块包括第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管和第十晶体管；所述调节模块包括第十一晶体管、第十二晶体管和第十三晶体管；各晶体管均为N型晶体管；
其中，所述第一时钟信号包括第一电平信号和第二电平信号，所述第一电平信号的电压与所述第一电源信号输入端输入的第一直流电源信号的电压相同，所述第一电平信号的电压小于所述第二电平信号的电压。
在本申请的一些实施例中，在所述驱动电路包括第二电源信号输入端的情况下，所述第二电源信号输入端输入的第二直流电源信号的电压为正电压，所述第一电源信号输入端输入的第一直流电源信号的电压为 负电压。
在本申请的一些实施例中，在所述下拉模块中的所述第五晶体管和所述第八晶体管同时导通的情况下，所述第八晶体管中的电流值大于所述第五晶体管中的电流值。
第二方面，本申请的实施例提供了一种显示装置，包括如上所述的驱动电路。
第三方面，本申请的实施例提供了一种驱动方法，应用于驱动如上所述的驱动电路，所述方法包括：
第一阶段，向扫描信号输入端输入上一级所述移位寄存器输出的扫描信号，向第一时钟信号输入端输入第一时钟信号，向下拉控制信号输入端输入第二电平信号，向第一电源信号输入端输入第一直流电源信号；
第二阶段，向第一时钟信号输入端输入所述第二电平信号，向下拉控制信号输入端输入所述第一电平信号，向第一电源信号输入端输入第一直流电源信号；
第三阶段，向复位信号输入端输入复位信号，向第一电源信号输入端输入第一直流电源信号。
在本申请的一些实施例中，所述向下拉控制信号输入端输入第二电平信号包括：
向所述下拉控制信号输入端输入第二时钟信号，其中，所述第一时钟信号和所述第二时钟信号的周期相同且相位相反；
或者，
向所述下拉控制信号输入端输入第二直流电源信号，其中，所述第二直流电源信号的电压为正电压，所述第一直流电源信号的电压为负电压。
在本申请的一些实施例中，所述向下拉控制信号输入端输入第二电平信号包括向所述下拉控制信号输入端输入第二时钟信号，其中，所述第一时钟信号和所述第二时钟信号的周期相同且相位相反的情况下，
所述第一时钟信号和所述第二时钟信号均包括第一电平信号和第二电平信号，所述第一电平信号的电压与所述第一直流电源信号的电压相同，所述第一电平信号的电压小于所述第二电平信号的电压。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1、图7和图8为本申请实施例提供的三种驱动电路的结构示意图；
图2为本申请实施例提供一种移位寄存器之间的级联关系示意图；
图3为图1中所示的驱动电路的时序图；
图4-图6为图1中的驱动电路在图3中的驱动时序下的驱动原理示意图；
图9为本申请的实施例提供的一种驱动电路的驱动方法的流程图。
具体实施例
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本发明的实施例中，由于晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在本公开实施例中，将晶体管的源极和漏极中的一个称为第一极，将源极和漏极中的另一个称为第二极。
在本发明的实施例中，术语“电连接”可以是指两个组件直接电连接，也可以是指两个组件之间经由一个或多个其他组件电连接。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语 “包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例”、“特定示例”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本申请的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在本申请的实施例中，采用“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分，仅为了清楚描述本申请实施例的技术方案，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
液晶显示面板由垂直和水平阵列式像素矩阵组成，在显示过程中通过栅极驱动电路输出栅极扫描信号，逐行扫描访问各像素；栅极驱动电路用于产生像素的栅极扫描电压，GOA(Gate Driver On Array，阵列基板行驱动)是一种将栅极驱动电路集成于阵列基板上的技术，每个GOA单元作为一个移位寄存器将扫描信号依次传递给下一GOA单元，逐行开启晶体管开关，完成像素单元的数据信号输入。
为了充分打开像素中的晶体管，保证像素电极的充电率，扫描信号的高电平(Vgh)需要达到25V电压以上；同时现有GOA电路的电容升压模块，能够使GOA内部电路的一些关键节点电压大于或等于双倍的高电平(Vgh)的电压，达到50V以上，而晶体管在这么高电压下工作，特性容易变化，产生阈值电压(Vth)漂移，从而使GOA单元在面板长时显示过程中稳定性变差，干扰正常扫描信号的输出，且使用寿命缩短。
本申请的实施例提供了一种驱动电路，包括如图2所示的多个级联的移位寄存器(GOA单元)，其中，对于第一级的移位寄存器(GOA单元1)，可以根据STV信号和时钟信号(包括CLK和CLKB)，输出第一扫描信号G[1]；第一级的移位寄存器输出的第一扫描信号G[1]作为第二级移位寄存器的输入信号(Input)，且第二级移位寄存器的输出信号G[2]作为第一级的移位寄存器的复位信号(Reset)。依次类推，对于第二级及其之后的移位寄存器，前一级的移位寄存器输出的扫描信号作为后一级的移位寄存器的输入信号，后一级移位寄存器输出的扫描 信号作为前一级移位寄存器的复位信号。第二级及其之后的移位寄存器(GOA单元2、GOA单元3…GOA单元N)根据上一级移位寄存器输出的扫描信号以及接收到的时钟信号，输出本级移位寄存器的扫描信号，其中，一个移位寄存器的输出端电连接一条栅线，以向栅线中输入相应的扫描信号。
在本申请的一些实施例中，参考图1所示，移位寄存器包括：
输入模块1，分别与移位寄存器的扫描信号输入端Input和第一节点PU电连接，被配置为在接收到扫描信号输入端Input的扫描信号时，向第一节点PU充电；
输出模块2，分别与移位寄存器的第一时钟信号输入端CLK、第一节点PU和移位寄存器的信号输出端Output电连接，被配置为在第一节点PU的电压的控制下，根据第一时钟信号输入端CLK输入的第一时钟信号，从信号输出端Output输出扫描信号G[N]；
上拉模块3，分别与第一节点PU和信号输出端Output电连接，被配置为拉高第一节点PU的电压；
调节模块4，分别与扫描信号输入端Input、信号输出端Output和第一节点PU电连接，被配置为在调节模块4发生自举作用时拉低第一节点PU的电压；
下拉模块5，分别与移位寄存器的下拉控制信号输入端(例如包括图1中的第二时钟信号输入端CLKB或图7中的第二电源信号输入端VDD)、移位寄存器的第一电源信号输入端VSS和第一节点PU电连接，被配置为拉低第一节点PU的电压；
复位模块6，分别与下拉模块5、移位寄存器的复位信号输入端Reset和信号输出端Output电连接，被配置为对驱动电路进行复位。
这里对于上述输入模块1、输出模块2、上拉模块3、调节模块4、下拉模块5以及复位模块6中包括的具体的电路结构不做限定，只要满足相应功能均在本申请的实施例提供的驱动电路保护的范围内。
上述第一节点PU、以及后文中的第二节点PD和第三节点PB只是为了便于描述电路结构而定义的，第一节点PU、第二节点PD和第三节点PB并不是一个实际的电路单元。
在示例性的实施例中，参考图1所示，输入模块1分别与移位寄存器的扫描信号输入端Input和第一节点PU电连接。
在示例性的实施例中，参考图8所述，输入模块1分别与移位寄存器的扫描信号输入端Input、第一节点PU和第二电源信号输入端VDD电连接。
在示例性的实施例中，参考图1所示，下拉模块5分别与移位寄存器的第二时钟信号输入端CLKB、移位寄存器的第一电源信号输入端VSS和第一节点PU电连接。
在示例性的实施例中，参考图7所示，下拉模块5分别与移位寄存器的第二电源信号输入端VDD、移位寄存器的第一电源信号输入端VSS和第一节点PU电连接。
在本申请的实施例提供的驱动电路中，通过输入模块1、输出模块2、上拉模块3、调节模块4、下拉模块5以及复位模块6的相互配合，一方面，能够依次输出扫描信号以控制阵列基板中的像素逐行扫描；另一方面，在驱动电路的驱动过程中，在上拉模块3拉高第一节点PU的电压后，且上拉模块3发生自举作用时，第一节点PU的电压继续升高，调节模块4能够对扫描信号输入端Input放电，以拉低第一节点PU的电压，从而避免第一节点PU的电压过大，进而避免了与第一节点PU电连接的器件因电压过大造成寿命降低或性能不稳定的问题，提高了驱动电路的稳定性。
在本申请的一些实施例中，参考图1所示，输入模块1包括第一晶体管M1，第一晶体管M1的控制极和第一晶体管M1的第一极均与扫描信号输入端Input电连接，第一晶体管M1的第二极与第一节点PU电连接。
在本申请的一些实施例中，参考图8所示，输入模块1包括第一晶体管M1，第一晶体管M1的控制极与扫描信号输入端Input电连接，第一晶体管M1的第一极与移位寄存器的第二电源信号输入端VDD电连接，第一晶体管M1的第二极与第一节点PU电连接。
在本申请的一些实施例中，参考图1所示，输出模块2包括第三晶体管M3，第三晶体管M3的控制极与第一节点PU电连接，第三晶体管M3的第一极与第一时钟信号输入端CLK电连接，第三晶体管M3的第二极与信号输出端Output电连接。
在本申请的一些实施例中，复位模块6包括第二晶体管M2和第四晶体管M4，第二晶体管M2的控制极和第四晶体管M4的控制极分别 与复位信号输入端Reset电连接；
第二晶体管M2的第一极与第一节点PU电连接，第二晶体管M2的第二极与第一电源信号输入端VSS电连接；第四晶体管M4的第一极与信号输出端Output电连接，第四晶体管M4的第二极与第一电源信号输入端VSS电连接。
在本申请的一些实施例中，参考图1或图7所示，下拉模块5包括第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第九晶体管M9和第十晶体管M10；
第五晶体管M5的第一极、第八晶体管M8的第一极以及第八晶体管M8的控制极均与下拉控制信号输入端(例如包括图1中的第二时钟信号输入端CLKB或图7中的第二电源信号输入端VDD)电连接，第五晶体管M5的控制极与第八晶体管M8的第二极电连接，第五晶体管M5的第二极、第六晶体管M6的第一极、第九晶体管M9的控制极、以及第十晶体管M10的控制极均与第二节点PD电连接，第六晶体管M6的第二极、第七晶体管M7的第二极、第九晶体管M9的第二极、以及第十晶体管M10的第二极均与第一电源信号输入端VSS电连接，第六晶体管M6的控制极、第七晶体管M7的控制极、以及第九晶体管M9的第一极均与第一节点PU电连接，第七晶体管M7的第一极与第五晶体管M5的控制极电连接，第十晶体管M10的第一极与信号输出端Output电连接。
在本申请的一些实施例中，下拉控制信号输入端包括图1中的第二时钟信号输入端CLKB或图7中的第二电源信号输入端VDD；
在下拉控制信号输入端包括第二时钟信号输入端CLKB的情况下，参考图3所示，第二时钟信号输入端输入的第二时钟信号CLKB信号与第一时钟信号输入端输入的第一时钟信号CLK信号的周期相同且相位相反；
在下拉控制信号输入端包括第二电源信号输入端VDD的情况下，第一电源信号输入端VSS和第二电源信号输入端VDD的输入的信号的极性相反。
示例性的，第一电源信号输入端VSS输入具有负电压的直流电源信号，第二电源信号输入端VDD输入具有正电压的直流电源信号。
在本申请的一些实施例中，参考图1所示，上拉模块3包括第一电 容器C1，第一电容器C1的第一电极与第一节点PU电连接，第一电容器C1的第二电极与信号输出端Output电连接。
在本申请的一些实施例中，参考图1所示，调节模块4包括第十一晶体管M11、第十二晶体管M12、第十三晶体管M13和第二电容器C2；
第十一晶体管M11的第一极、第十二晶体管M12的第一极和第十二晶体管M12的控制极均与扫描信号输入端Input电连接，第十一晶体管M11的控制极、第十二晶体管M12的第二极和第十三晶体管M13的第一极均与第三节点PB电连接，第十一晶体管M11的第二极与第二电容器C2的第一电极电连接，第二电容器C2的第二电极和第十三晶体管M13的第二极均与第一节点PU电连接，第十三晶体管M13的控制极与信号输出端Output电连接。
在示例性的实施例中，上述晶体管可以是薄膜晶体管，也可以是金属氧化物半导体场效应管，在此不作限定。
在示例性的实施例中，为了制作工艺统一，且便于后续电路的驱动方法更简单，本申请的实施例提供的驱动电路以上述各晶体管均为N型晶体管为例进行说明。
当然，上述所有晶体管也可以均为P型晶体管，上述晶体管为P型晶体管的情况，设计原理与本发明类似，也属于本发明保护的范围。
需要说明的是，N型晶体管在高电平下导通，在低电平下截止；P型晶体管在低电平下导通，在高电平下截止。
在本申请的一些实施例中，输入模块1包括第一晶体管M1，输出模块2包括第三晶体管M3，复位模块6包括第二晶体管M2和第四晶体管M4，上拉模块5包括第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第九晶体管M9和第十晶体管M10；调节模块4包括第十一晶体管M11、第十二晶体管M12和第十三晶体管M13；在各晶体管均为N型晶体管的情况下，第一时钟信号CLK信号包括第一电平信号和第二电平信号，第一电平信号的电压与第一电源信号输入端VSS输入的第一直流电源信号VSS信号的电压相同，第一电平信号的电压小于第二电平信号的电压。
示例性的，第一电平为低电平(例如电压为Vgl)，第二电平为高电平(例如电压为Vgh)。
示例性的，第一时钟信号CLK信号中的低电平信号与第一直流电 源信号VSS信号的电压相同。
在本申请的一些实施例中，参考图7或图8所示，在驱动电路包括第二电源信号输入端VDD的情况下，第二电源信号输入端VDD输入的第二直流电源信号VDD信号的电压为正电压，第一电源信号输入端VSS输入的第一直流电源信号VSS信号的电压为负电压。
示例性的，参考图7，下拉控制信号输入端包括第二电源信号输入端VDD。
示例性的，参考图8所示，输入模块1中的第一晶体管M1的第一极与第二电源信号输入端VDD电连接。
在本申请的一些实施例中，下拉控制信号输入端包括第二电源信号输入端VDD或第二时钟信号输入端CLKB；
参考图8所示，在下拉控制信号输入端包括第二时钟信号输入端CLKB的情况下，第二时钟信号输入端CLKB输入的第二时钟信号CLKB信号与第一时钟信号输入端CLK输入的第一时钟信号CLK信号的周期相同且相位相反。
在本申请的一些实施例中，参考图4所示，在下拉模块5中的第五晶体管M5和第八晶体管M8同时导通的情况下，第八晶体管M8中的电流值大于第五晶体管M5中的电流值。此时，由于第七晶体管M7导通，第一电源信号输入端VSS输入的低电平信号经过第七晶体管M7控制第五晶体管M5截止，从而避免第二节点PD的电压被拉高。
需要说明的是，在图4-图7中标记“H”代表输入的信号为高电平信号，标记“L”代表输入的为低电平信号，另外，本申请的实施例提供的附图中标记G[N-1]代表输入的为上一级移位寄存器输出的扫描信号G[N-1]，可以理解，输入上一级移位寄存器输出的扫描信号G[N-1]的端口均为扫描信号输入端Input，标记G[N]代表本级移位寄存器的输出端Output，且输出的扫描信号为。
下面以第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4，第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第九晶体管M9、第十晶体管M10、第十一晶体管M11、第十二晶体管M12和第十三晶体管M13为均为N型晶体管为例，以图1中所示的驱动电路的结构为例，结合在此情况下各端口输入的信号时序，对本实施例提供的驱动电路的工作原理就那些详细介绍。需要说明的是， 图4至图6中，晶体管截止通过“×”标记，晶体管导通通过“√”标记。
图3示出了在一个工作周期内各端口输入(或输入)的信号的时序图。
在第一阶段，如图3中所示的输入阶段T1，参考图4所示，扫描信号输入端Input输入高电平信号H，第一时钟信号输入端CLK输入低电平信号L，第二时钟信号输入端CLKB输入高电平信号H，复位信号输入端Reset输入低电平信号L，第一电源信号输入端VSS输入低电平信号L，此时，第一晶体管M1导通，扫描信号输入端Input输入高电平信号H通过第一晶体管M1对第一节点PU充电，第一节点PU为高电平，且电压为Vgh，第三晶体管M3导通，第一时钟信号输入端CLK通过第三晶体管M3向信号输出端Output传输低电平信号L，信号输出端Output输出低电平信号Low；第十一晶体管M11和第十二晶体管M12导通，第十三晶体管M13截止，此时，第三节点PB为高电平，且电压为Vgh；第五晶体管M5、第六晶体管M6、第七晶体管M7和第八晶体管M8导通，第二晶体管M2、第四晶体管M4、第九晶体管M9和第十晶体管M10截止，此时，通过设计第八晶体管M8和第九晶体管M9的大小比例，再通过设计第八晶体管M8和第五晶体管M5的大小比例，使得实际通过第八晶体管M8的电流大于通过第五晶体管M5的电流，这样，第一电源信号输入端VSS输入低电平信号L可以通过第七晶体管M7控制第五晶体管M5，使得第二节点PD的电压不被第二时钟信号输入端CLKB输入高电平信号H拉高，仍处于低电平状态。
在第二阶段，如图3中所示的输出阶段T2，参考图5所示，扫描信号输入端Input输入低电平信号L，第一时钟信号输入端CLK输入高电平信号H，第二时钟信号输入端CLKB输入低电平信号L，复位信号输入端Reset输入低电平信号L，第一电源信号输入端VSS输入低电平信号L，此时，第一节点PU维持上一阶段的电压Vgh，第一晶体管M1截止，第二晶体管M2、第九晶体管M9、第五晶体管M5、第八晶体管M8、第四晶体管M4和第十晶体管M10截止，第三晶体管M3、第六晶体管M6和第七晶体管M7导通，第一时钟信号输入端CLK通过第三晶体管M3向信号输出端Output传输高电平信号H，信号输出端Output的电压发生跳变，并从上一阶段的低电平变为此时的高电平，在 第一存储电容器C1第一节点PU处产生一个感应电压差，由于第一存储电容器C1的自举作用，使得第一节点PU的电压继续升高，且电压值从Vgh趋向于2Vgh，在信号输出端Output高电平信号的控制下(G[N]此时为高电平)，第十三晶体管M13导通，在扫描信号输入端Input输入的低电平信号的控制下(G[N-1]此时为低电平)，第十二晶体管M12迅速截止，第三节点PB通过第十三晶体管M13向第一电源信号输入端VSS放电，第三节点PB的电压从高电平拉低为低电平，第十一晶体管M11中通过的电流逐渐变小，直到截止，在第十一晶体管M11中有电流通过时，扫描信号输入端Input输入的低电平信号(G[N-1]此时为低电平)能够通过第十一晶体管M11传输到第二电容器C2的一个电极上，导致第二电容器C2在第一节点PU处产生一个感应电压差，由于第二电容器C2的自举作用，使得第一节点PU的电压被拉低，最终，在第一电容器C1和第二电容器C2的共同作用下，第一节点PU的电压值升高至1.5Vgh左右，避免了栅极与第一节点PU电连接的晶体管由于电压过大产生的阈值电压(Vth)漂移的问题，从而提高了驱动电路中晶体管的性能稳定性，提高了晶体管的使用寿命。
在第三阶段，如图3中所示的复位阶段T3，参考图6所示，扫描信号输入端Input输入低电平信号L，第一时钟信号输入端CLK输入低电平信号L，第二时钟信号输入端CLKB输入高电平信号H，复位信号输入端Reset输入高电平信号H，第一电源信号输入端VSS输入低电平信号L，此时，第二晶体管M2和第四晶体管M4导通，第五晶体管M5和第八晶体管M8导通，第九晶体管M9和第十晶体管M10导通，第一节点PU处的电压和信号输出端Output的电压均被拉低复位。
需要说明的是，为了驱动时序简单，本实施例提供的驱动时序仅是以图1所示的电路结构图为例的其中一种情况，对于图7和图8所示的电路结构图，其时序还可以相应调整，这里不进行限定。
进一步需要说明的是，本实施例提供的各晶体管并不限于采用N型晶体管，实际应用中，各晶体管还可以为P型晶体管。在各晶体管均为P型晶体管的情况下，其具体时序与图3中的时序的相位相反。
本申请的实施例提供了一种显示装置，包括如上所述的驱动电路。
上述显示装置可以是LCD(Liquid Crystal Display，液晶显示器)， 以及包括这些显示装置的电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件。上述显示装置具有画面亮度均匀性好、显示效果好、产品质量高的特点。
本申请的实施例提供了一种驱动方法，应用于驱动如上所述的驱动电路，该方法包括：
S901、第一阶段T1(即输入阶段)，向扫描信号输入端Input输入上一级移位寄存器输出的扫描信号，向第一时钟信号输入端CLK输入第一时钟信号，向下拉控制信号输入端(例如包括图1中的第二时钟信号输入端CLKB或图7中的第二电源信号输入端VDD)输入第二电平信号，向第一电源信号输入端VSS输入第一直流电源信号；
在示例性的实施例中，向下拉控制信号输入端输入第二电平信号这一步骤包括：S9011、向下拉控制信号输入端输入第二时钟信号CLKB信号，其中，第一时钟信号和第二时钟信号的周期相同且相位相反；
图1中所示的驱动电路在第一阶段T1的具体驱动方法如下：
扫描信号输入端Input输入高电平信号H，第一时钟信号输入端CLK输入低电平信号L，第二时钟信号输入端CLKB输入高电平信号H，复位信号输入端Reset输入低电平信号L，第一电源信号输入端VSS输入低电平信号L，此时，第一晶体管M1导通，扫描信号输入端Input输入高电平信号H通过第一晶体管M1对第一节点PU充电，第一节点PU为高电平，且电压值为Vgh，第三晶体管M3导通，第一时钟信号输入端CLK通过第三晶体管M3向信号输出端Output传输低电平信号L，信号输出端Output输出低电平信号Low；第十一晶体管M11和第十二晶体管M12导通，第十三晶体管M13截止，此时，第三节点PB为高电平，且电压值为Vgh；第五晶体管M5、第六晶体管M6、第七晶体管M7和第八晶体管M8导通，第二晶体管M2、第四晶体管M4、第九晶体管M9和第十晶体管M10截止，此时，通过设计第八晶体管M8和第九晶体管M9的大小比例，再通过设计第八晶体管M8和第五晶体管M5的大小比例，使得实际通过第八晶体管M8的电流大于通过第五晶体管M5的电流，这样，第一电源信号输入端VSS输入低电平信号L可以通过第七晶体管M7控制第五晶体管M5，使得第二节点PD的电压不被第二时钟信号输入端CLKB输入高电平信号H拉高，仍处于低 电平状态。
S902、第二阶段T2(即输出阶段)，向第一时钟信号输入端CLK输入第二电平信号，向下拉控制信号输入端输入第一电平信号，向第一电源信号输入端VSS输入第一直流电源信号；
在示例性的实施例中，向下拉控制信号输入端输入第二电平信号这一步骤包括：S9011、向下拉控制信号输入端输入第二时钟信号CLKB信号，其中，第一时钟信号和第二时钟信号的周期相同且相位相反；
图1中所示的驱动电路在第二阶段T2的具体驱动方法如下：
扫描信号输入端Input输入低电平信号L，第一时钟信号输入端CLK输入高电平信号H，第二时钟信号输入端CLKB输入低电平信号L，复位信号输入端Reset输入低电平信号L，第一电源信号输入端VSS输入低电平信号L，此时，第一节点PU维持上一阶段的电压Vgh，第一晶体管M1截止，第二晶体管M2、第九晶体管M9、第五晶体管M5、第八晶体管M8、第四晶体管M4和第十晶体管M10截止，第三晶体管M3、第六晶体管M6和第七晶体管M7导通，第一时钟信号输入端CLK通过第三晶体管M3向信号输出端Output传输高电平信号H，信号输出端Output的电压发生跳变，并从上一阶段的低电平变为此时的高电平，在第一存储电容器C1第一节点PU处产生一个感应电压差，由于第一存储电容器C1的自举作用，使得第一节点PU的电压继续升高，且电压从Vgh趋向于2Vgh，在信号输出端Output高电平信号G[N]的控制下，第十三晶体管M13导通，在扫描信号输入端Input输入的低电平信号(此时G[N-1]为低电平)的控制下，第十二晶体管M12迅速截止，第三节点PB通过第十三晶体管M13向第一电源信号输入端VSS放电，第三节点PB的电压拉低，此时第十一晶体管M11从高电平拉低为低电平，第十一晶体管M11中通过的电流逐渐变小，直到截止，在第十一晶体管M11中有电流通过时，扫描信号输入端Input输入的低电平信号(此时G[N-1]为低电平)能够通过第十一晶体管M11传输到第二电容器C2的一个电极上，导致第二电容器C2在第一节点PU处产生一个感应电压差，由于第二电容器C2的自举作用，使得第一节点PU的电压被拉低，最终，在第一电容器C1和第二电容器C2的共同作用下，第一节点PU的电压升高至1.5Vgh左右，避免了栅极与第一节点PU电连接的晶体管由于电压过大产生的阈值电压(Vth)漂移的问题， 从而提高了驱动电路中晶体管的性能稳定性，提高了晶体管的使用寿命。
S903、第三阶段T3(即复位阶段)，向复位信号输入端Reset输入复位信号，向第一电源信号输入端VSS输入第一直流电源信号。
图1中所示的驱动电路在第三阶段T3的具体驱动方法如下：
扫描信号输入端Input输入低电平信号L，第一时钟信号输入端CLK输入低电平信号L，第二时钟信号输入端CLKB输入高电平信号H，复位信号输入端Reset输入高电平信号H，第一电源信号输入端VSS输入低电平信号L，此时，第二晶体管M2和第四晶体管M4导通，第五晶体管M5和第八晶体管M8导通，第九晶体管M9和第十晶体管M10导通，第一节点PU处的电压和信号输出端Output的电压均被拉低复位。
本申请的实施例提供了一种驱动电路的驱动方法，通过该驱动方法，一方面，能够依次输出扫描信号以控制阵列基板中的像素逐行扫描；另一方面，在驱动电路的驱动过程中，在上拉模块3拉高第一节点PU的电压后，且上拉模块3发生自举作用时，第一节点PU的电压继续升高，调节模块4能够对扫描信号输入端Input放电，以拉低第一节点PU的电压，从而避免第一节点PU的电压过大，进而避免了与第一节点PU电连接的器件因电压过大造成寿命降低或性能不稳定的问题，提高了驱动电路的稳定性。该驱动方法驱动时序简单、易实现。
在本申请的一些实施例中，向下拉控制信号输入端输入第二电平信号这一步骤包括：
S9011、向下拉控制信号输入端输入第二时钟信号CLKB信号，其中，第一时钟信号和第二时钟信号的周期相同且相位相反；
或者，
S9012、向下拉控制信号输入端输入第二直流电源信号VDD信号，其中，第二直流电源信号的电压为正电压，第一直流电源信号的电压为负电压。
在本申请的一些实施例中，向下拉控制信号输入端输入第二电平信号包括向下拉控制信号输入端输入第二时钟信号CLKB信号，其中，第一时钟信号CLK信号和第二时钟信号CLKB信号的周期相同且相位相反的情况下，
第一时钟信号CLK信号和第二时钟信号CLKB信号均包括第一电 平信号(低电平信号)和第二电平信号(高电平信号)，第一电平信号的电压与第一直流电源信号VSS信号的电压相同，第一电平信号的电压小于第二电平信号的电压。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种驱动电路，其中，包括多个级联的移位寄存器，所述移位寄存器包括：
    输入模块，分别与所述移位寄存器的扫描信号输入端和第一节点电连接，被配置为在接收到所述扫描信号输入端的扫描信号时，向所述第一节点充电；
    输出模块，分别与所述移位寄存器的第一时钟信号输入端、所述第一节点和所述移位寄存器的信号输出端电连接，被配置为在所述第一节点的电压的控制下，根据所述第一时钟信号输入端输入的第一时钟信号，从所述信号输出端输出扫描信号；
    上拉模块，分别与所述第一节点和所述信号输出端电连接，被配置为拉高所述第一节点的电压；
    调节模块，分别与所述扫描信号输入端、所述信号输出端和所述第一节点电连接，被配置为在所述调节模块发生自举作用时拉低所述第一节点的电压；
    下拉模块，分别与所述移位寄存器的下拉控制信号输入端、所述移位寄存器的第一电源信号输入端和所述第一节点电连接，被配置为拉低所述第一节点的电压；
    复位模块，分别与所述下拉模块、所述移位寄存器的复位信号输入端和所述信号输出端电连接，被配置为对所述驱动电路进行复位。
  2. 根据权利要求1所述的驱动电路，其中，所述输入模块包括第一晶体管，所述第一晶体管的控制极和所述第一晶体管的第一极均与所述扫描信号输入端电连接，所述第一晶体管的第二极与所述第一节点电连接。
  3. 根据权利要求1所述的驱动电路，其中，所述输入模块包括第一晶体管，所述第一晶体管的控制极与所述扫描信号输入端电连接，所述第一晶体管的第一极与所述移位寄存器的第二电源信号输入端电连接，所述第一晶体管的第二极与所述第一节点电连接。
  4. 根据权利要求1所述的驱动电路，其中，所述输出模块包括第三晶体管，所述第三晶体管的控制极与所述第一节点电连接，所述第三晶体管的第一极与所述第一时钟信号输入端电连接，所述第三晶体管的 第二极与所述信号输出端电连接。
  5. 根据权利要求1所述的驱动电路，其中，所述复位模块包括第二晶体管和第四晶体管，所述第二晶体管的控制极和所述第四晶体管的控制极分别与所述复位信号输入端电连接；
    所述第二晶体管的第一极与所述第一节点电连接，所述第二晶体管的第二极与所述第一电源信号输入端电连接；所述第四晶体管的第一极与所述信号输出端电连接，所述第四晶体管的第二极与所述第一电源信号输入端电连接。
  6. 根据权利要求1所述的驱动电路，其中，所述下拉模块包括第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管和第十晶体管；
    所述第五晶体管的第一极、所述第八晶体管的第一极以及所述第八晶体管的控制极均与所述下拉控制信号输入端电连接，所述第五晶体管的控制极与所述第八晶体管的第二极电连接，所述第五晶体管的第二极、所述第六晶体管的第一极、所述第九晶体管的控制极、以及所述第十晶体管的控制极均与第二节点电连接，所述第六晶体管的第二极、所述第七晶体管的第二极、所述第九晶体管的第二极、以及所述第十晶体管的第二极均与所述第一电源信号输入端电连接，所述第六晶体管的控制极、所述第七晶体管的控制极、以及所述第九晶体管的第一极均与所述第一节点电连接，所述第七晶体管的第一极与所述第五晶体管的控制极电连接，所述第十晶体管的第一极与所述信号输出端电连接。
  7. 根据权利要求6所述的驱动电路，其中，所述下拉控制信号输入端包括第二时钟信号输入端或第二电源信号输入端；
    在所述下拉控制信号输入端包括第二时钟信号输入端的情况下，所述第二时钟信号输入端输入的第二时钟信号与所述第一时钟信号输入端输入的第一时钟信号的周期相同且相位相反；
    在所述下拉控制信号输入端包括第二电源信号输入端的情况下，所述第一电源信号输入端和所述第二电源信号输入端的输入的信号的极性相反。
  8. 根据权利要求1所述的驱动电路，其中，所述上拉模块包括第一电容器，所述第一电容器的第一电极与所述第一节点电连接，所述第一电容器的第二电极与所述信号输出端电连接。
  9. 根据权利要求1所述的驱动电路，其中，所述调节模块包括第十一晶体管、第十二晶体管、第十三晶体管和第二电容器；
    所述第十一晶体管的第一极、所述第十二晶体管的第一极和所述第十二晶体管的控制极均与所述扫描信号输入端电连接，所述第十一晶体管的控制极、所述第十二晶体管的第二极和所述第十三晶体管的第一极均与第三节点电连接，所述第十一晶体管的第二极与所述第二电容器的第一电极电连接，所述第二电容器的第二电极和所述第十三晶体管的第二极均与所述第一节点电连接，所述第十三晶体管的控制极与所述信号输出端电连接。
  10. 根据权利要求1-9中任一项所述的驱动电路，其中，所述输入模块包括第一晶体管，所述输出模块包括第三晶体管，所述复位模块包括第二晶体管和第四晶体管，所述上拉模块包括第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管和第十晶体管；所述调节模块包括第十一晶体管、第十二晶体管和第十三晶体管；各晶体管均为N型晶体管；
    其中，所述第一时钟信号包括第一电平信号和第二电平信号，所述第一电平信号的电压与所述第一电源信号输入端输入的第一直流电源信号的电压相同，所述第一电平信号的电压小于所述第二电平信号的电压。
  11. 根据权利要求10所述的驱动电路，其中，在所述驱动电路包括第二电源信号输入端的情况下，所述第二电源信号输入端输入的第二直流电源信号的电压为正电压，所述第一电源信号输入端输入的第一直流电源信号的电压为负电压。
  12. 根据权利要求6所述的驱动电路，其中，在所述下拉模块中的所述第五晶体管和所述第八晶体管同时导通的情况下，所述第八晶体管中的电流值大于所述第五晶体管中的电流值。
  13. 一种显示装置，其中，包括如权利要求1-12中任一项所述的驱动电路。
  14. 一种驱动方法，其中，应用于驱动如权利要求1-12中任一项所述的驱动电路，所述方法包括：
    第一阶段，向扫描信号输入端输入上一级所述移位寄存器输出的扫描信号，向第一时钟信号输入端输入第一时钟信号，向下拉控制信号输 入端输入第二电平信号，向第一电源信号输入端输入第一直流电源信号；
    第二阶段，向第一时钟信号输入端输入所述第二电平信号，向下拉控制信号输入端输入所述第一电平信号，向第一电源信号输入端输入第一直流电源信号；
    第三阶段，向复位信号输入端输入复位信号，向第一电源信号输入端输入第一直流电源信号。
  15. 根据权利要求14所述的驱动方法，其中，所述向下拉控制信号输入端输入第二电平信号包括：
    向所述下拉控制信号输入端输入第二时钟信号，其中，所述第一时钟信号和所述第二时钟信号的周期相同且相位相反；
    或者，向所述下拉控制信号输入端输入第二直流电源信号，其中，所述第二直流电源信号的电压为正电压，所述第一直流电源信号的电压为负电压。
  16. 根据权利要求15所述的驱动方法，其中，所述向下拉控制信号输入端输入第二电平信号包括向所述下拉控制信号输入端输入第二时钟信号，其中，所述第一时钟信号和所述第二时钟信号的周期相同且相位相反的情况下，
    所述第一时钟信号和所述第二时钟信号均包括第一电平信号和第二电平信号，所述第一电平信号的电压与所述第一直流电源信号的电压相同，所述第一电平信号的电压小于所述第二电平信号的电压。
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