WO2022198502A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2022198502A1
WO2022198502A1 PCT/CN2021/082769 CN2021082769W WO2022198502A1 WO 2022198502 A1 WO2022198502 A1 WO 2022198502A1 CN 2021082769 W CN2021082769 W CN 2021082769W WO 2022198502 A1 WO2022198502 A1 WO 2022198502A1
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WIPO (PCT)
Prior art keywords
transistor
capacitor
electrode
clock signal
transfer electrode
Prior art date
Application number
PCT/CN2021/082769
Other languages
English (en)
French (fr)
Inventor
卢江楠
商广良
刘利宾
韩龙
冯宇
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180000576.6A priority Critical patent/CN115398527B/zh
Priority to EP21932130.4A priority patent/EP4123634A4/en
Priority to CN202211385609.6A priority patent/CN115798413B/zh
Priority to PCT/CN2021/082769 priority patent/WO2022198502A1/zh
Publication of WO2022198502A1 publication Critical patent/WO2022198502A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels

Definitions

  • At least one embodiment of the present disclosure relates to a display substrate and a display device.
  • a pixel array of a liquid crystal display panel or an organic light emitting diode (Organic Light Emitting Diode, OLED) display panel usually includes multiple rows of gate lines and multiple columns of data lines arranged across the gate lines.
  • the driving of the gate lines can be realized by a bonded integrated driving circuit.
  • the gate line driver circuit can also be directly integrated on the thin film transistor array substrate to form GOA (Gate driver On Array) to drive the gate lines. .
  • a GOA including a plurality of cascaded shift register units can be used to provide on-off voltage signals (scanning signals) for a plurality of rows of gate lines of a pixel array, so as to control, for example, the plurality of rows of gate lines to be turned on sequentially, and simultaneously controlled by the data lines
  • a data signal is provided to the pixel units of the corresponding row in the pixel array, so as to form a grayscale voltage required for displaying each grayscale of an image in each pixel unit, thereby displaying a frame of image.
  • At least one embodiment of the present disclosure relates to a display substrate and a display device.
  • At least one embodiment of the present disclosure provides a display substrate, including: a base substrate; a shift register unit, a first clock signal line and a first power supply line disposed in a peripheral area of the base substrate, the shift register The unit includes a charge pump circuit, the first clock signal line is configured to provide a first clock signal to the shift register unit, the first power supply line is configured to provide a first supply voltage to the shift register unit , the charge pump circuit includes a first capacitor, a first transistor and a second capacitor, the charge pump circuit is electrically connected to the first input node and the first node respectively, and the first plate of the first capacitor is connected to the The first clock signal line is connected to the first clock signal line, the second plate of the first capacitor is connected to the first input node, the first plate of the second capacitor is connected to the first power line, and the second capacitor is connected to the first power line.
  • the second plate is connected to the first node, the gate of the first transistor is connected to the first pole or the second pole of the first transistor, and the first capacitor is connected to the base plate.
  • the orthographic projection is adjacent to the orthographic projection of the first transistor on the base substrate, and the orthographic projection of the second capacitor on the base substrate is the same as the orthographic projection of the first transistor on the base substrate. Projections are adjacent.
  • the charge pump circuit is configured to, during a first period of time, under the control of the first clock signal provided by the first clock signal line, the first input
  • the potential of the node is converted from a first voltage signal to a second voltage signal, and the second voltage signal is transmitted to the first node, and is configured to maintain the potential of the first node for a second period of time.
  • the polarity of the first voltage signal is the same as the polarity of the second voltage signal, and the absolute value of the voltage value of the second voltage signal is greater than that of the first voltage signal The absolute value of the voltage value.
  • the display substrate further includes a first transfer electrode and a second transfer electrode; the gate electrode of the first transistor and the first electrode of the first transistor pass through the first transfer electrode. connecting electrodes to form a diode structure, the first end of the first transfer electrode is connected to the first electrode of the first transistor, and the second end of the first transfer electrode is connected to the gate of the first transistor.
  • the first end of the second transfer electrode is connected to the second electrode of the first transistor, the second end of the second transfer electrode is connected to the second plate of the second capacitor,
  • the first electrode of the first transistor is connected to the active layer of the first transistor through a first via hole, and the orthographic projection of the channel of the first transistor on the base substrate is connected to the first via hole.
  • the orthographic projections of the holes on the base substrate do not overlap.
  • the first transfer electrode is connected to the gate of the first transistor through a second via hole, and the channel of the first transistor is on the base substrate
  • the orthographic projection of the second via hole does not overlap with the orthographic projection of the second via hole on the base substrate.
  • a height of the second via hole in a direction perpendicular to the base substrate is smaller than a height of the first via hole in a direction perpendicular to the base substrate.
  • the first via hole penetrates the first insulating layer, the second insulating layer and the third insulating layer, and the second via hole penetrates the second insulating layer and the third insulating layer Insulation.
  • the orthographic projection of the channel of the first transistor on the base substrate and the orthographic projection of the gate of the first transistor on the base substrate overlap.
  • the capacitance value of the first capacitor is greater than or equal to the capacitance value of the second capacitor.
  • the capacitance value of the first capacitor is less than or equal to ten times the capacitance value of the second capacitor.
  • the capacitance value of the second capacitor ranges from 0.01pF to 2pF.
  • At least one of the first capacitor and the second capacitor is a structure in which three capacitors are connected in parallel, and the structure in which the three capacitors are connected in parallel includes the first part of the second plate, the third The second portion of the diode plate, the first portion of the first electrode plate, and the second portion of the first electrode plate.
  • the first portion of the second electrode plate and the second portion of the second electrode plate are connected through a third via hole, and the first portion of the first electrode plate and the second electrode plate are connected through a third via hole.
  • the second part of a pole plate is connected through a transition part, the third via hole and the transition part are located on opposite sides of the structure of the three capacitors in parallel, and the first part of the second pole plate , the first part of the first pole plate, the second part of the second pole plate, and the second part of the first pole plate are arranged in order to form the structure of the three capacitors in parallel, the transfer
  • the second portion and the second portion of the second plate are located on the same layer and insulated from each other.
  • the orthographic projection of the second electrode plate of the first capacitor on the base substrate and the orthographic projection of the first electrode of the first transistor on the base substrate partially overlap, and the orthographic projection of the second electrode plate of the second capacitor on the base substrate partially overlaps the orthographic projection of the second electrode of the first transistor on the base substrate.
  • the display substrate further includes a first wire and a third transfer electrode; the first end of the first wire is connected to the first clock signal wire, and the first end of the first wire is connected to the first clock signal wire.
  • the two ends are connected to the first end of the third transfer electrode, and the second end of the third transfer electrode is connected to the first plate of the first capacitor.
  • the display substrate further includes a fourth transfer electrode and a fifth transfer electrode
  • the charge pump circuit further includes a second transistor
  • the first end of the fourth transfer electrode is connected to the gate of the second transistor
  • the first end of the fourth transfer electrode is connected to the second plate of the first capacitor
  • the first end of the fifth transfer electrode is connected to the second electrode of the first capacitor.
  • the first pole of the second transistor is connected to the first pole
  • the second end of the fifth transfer electrode is connected to the first wire
  • the first wire is connected to the first clock signal line
  • the second end of the second transistor is connected to the first wire.
  • the second pole is connected to the third transfer electrode.
  • the first clock signal line extends along the first direction on the base substrate, and the first capacitor, the first transistor and the second capacitor are are arranged in sequence in the second direction, and the first direction intersects with the second direction.
  • the display substrate further includes a sixth transition electrode, a seventh transition electrode, an eighth transition electrode, a ninth transition electrode, a tenth transition electrode, and an eleventh transition electrode , a second clock signal line, and a second power supply line;
  • the second clock signal line is configured to provide a second clock signal to the shift register unit, and the second power supply line is configured to supply the shift register
  • the unit provides a second power supply voltage
  • the shift register unit further includes a first node control transistor, a first output transistor, a second output transistor and a third capacitor; the gate of the first output transistor is connected to the second capacitor
  • the second pole of the first output transistor is electrically connected through the sixth transition electrode, the first pole of the first output transistor is electrically connected to the first power line through the seventh transition electrode, and the first output transistor
  • the second pole of the transistor is electrically connected to the drive signal output terminal through the eighth transition electrode;
  • the gate of the second output transistor is electrically connected to the first plate of the third capacitor through the ninth transition electrode , the first
  • the orthographic projection of the third capacitor on the base substrate is adjacent to the orthographic projection of the second output transistor on the base substrate.
  • the second power supply line and the first power supply line are arranged on two sides of the shift register unit.
  • the second clock signal line and the second power supply line are located on the same side of the shift register unit, or, the second clock signal line and the first power supply The lines are on the same side of the shift register cell.
  • the display substrate further includes a twelfth transition electrode, a thirteenth transition electrode, a fourteenth transition electrode, and a third clock signal line;
  • the third clock signal line is is configured to provide a third clock signal to the shift register unit,
  • the shift register unit further includes a first control transistor, a second control transistor and a first isolation transistor;
  • the gate of the first control transistor is connected to the The second clock signal line is electrically connected, the first electrode of the first control transistor is electrically connected to the input end through the twelfth switching electrode;
  • the gate of the second control transistor is electrically connected to the third clock signal line electrically connected, the first electrode of the second control transistor and the second electrode of the first control transistor are electrically connected through the thirteenth transfer electrode, and the second electrode of the second control transistor is electrically connected to the first electrode of the first control transistor.
  • the second electrode of an isolation transistor is electrically connected through the fourteenth transfer electrode, and the first electrode of the first isolation transistor and the second electrode plate of the first capacitor are electrically connected through the fourth transfer electrode , the gate of the first isolation transistor is electrically connected to the first power line.
  • the first control transistor and the second clock signal line are located on the same side of the second output transistor, or the first control transistor and the second clock signal line Lines are located on opposite sides of the second output transistor.
  • the center line connecting the first control transistor, the second control transistor, and the first isolation transistor forms an acute triangle.
  • the second control transistor, the first control transistor, the second output transistor, and the second clock signal line are sequentially arranged along the second direction.
  • the second control transistor, the second capacitor, the first control transistor, the second output transistor, and the second clock signal line are along the second direction in order.
  • the display substrate further includes a fifteenth transfer electrode, a sixteenth transfer electrode, a seventeenth transfer electrode, and an eighteenth transfer electrode;
  • the shift register unit further includes a third control transistor, a fourth control transistor and a second isolation transistor; the gate of the third control transistor is electrically connected to the third clock signal line, and the first pole of the third control transistor is connected to the first The power line is electrically connected through the fifteenth transfer electrode; the gate of the fourth control transistor is electrically connected with the second pole of the second control transistor, and the first pole of the fourth control transistor is electrically connected with the The third clock signal line is electrically connected through the seventeenth switching electrode, and the second pole of the fourth control transistor and the second pole of the third control transistor are electrically connected through the sixteenth switching electrode;
  • the gate of the second isolation transistor is electrically connected to the first power supply line, and the first pole of the second isolation transistor and the second pole of the fourth control transistor are electrically connected through the sixteenth switching electrode. connected, and the second pole of the second isolation
  • the third control transistor, the fourth control transistor, and the second isolation transistor are sequentially arranged along the second direction, and the third control transistor is on the substrate
  • the orthographic projection on the substrate is adjacent to the orthographic projection of the fourth control transistor on the base substrate
  • the orthographic projection of the second isolation transistor on the base substrate is adjacent to the orthographic projection of the fourth control transistor on the base substrate.
  • the orthographic projections on the base substrate are adjacent.
  • the display substrate further includes a connection trace and a nineteenth transfer electrode
  • the shift register unit further includes a fifth control transistor, a sixth control transistor, a seventh control transistor, and a fourth control transistor. capacitor; the first pole of the fourth capacitor is electrically connected to the eighteenth transfer electrode, and the gate of the fifth control transistor and the first plate of the fourth capacitor pass through the eighteenth turn
  • the first electrode of the fifth control transistor is electrically connected to the second electrode of the fourth capacitor through the nineteenth transfer electrode, and the second electrode of the fifth control transistor is electrically connected to the second electrode of the fourth capacitor.
  • the first clock signal line is electrically connected through the fifth transfer electrode; the gate of the sixth control transistor is electrically connected with the first clock signal line through the fifth transfer electrode, and the sixth control transistor is electrically connected with the first clock signal line through the fifth transfer electrode.
  • the first electrode of the transistor is electrically connected to the second electrode plate of the fourth capacitor through the nineteenth transfer electrode, and the second electrode of the sixth control transistor is connected to the first electrode plate of the third capacitor through the
  • the ninth transfer electrode is electrically connected; the gate of the seventh control transistor and the second pole of the second control transistor are electrically connected through the connection wiring and the fourteenth transfer electrode, and the The first pole of the seventh control transistor and the second power line are electrically connected through the eleventh transfer electrode, and the second pole of the seventh control transistor and the gate of the second output transistor pass through the The ninth transfer electrode is electrically connected; the gate of the first node control transistor is connected to the second plate of the fourth capacitor.
  • the orthographic projection of the fifth control transistor on the base substrate is adjacent to the orthographic projection of the fourth capacitor on the base substrate
  • the sixth control transistor The orthographic projection of the transistor on the base substrate is adjacent to the orthographic projection of the fourth capacitor on the base substrate.
  • the center of the fourth capacitor, the center of the fifth control transistor, and the center of the sixth control transistor form an obtuse triangle or an acute triangle.
  • the fifth control transistor and the sixth control transistor are arranged along the second direction, and the fifth control transistor and the sixth control transistor are located in the fourth capacitor on the same side.
  • the first capacitor and the third capacitor are arranged in the first direction
  • the second capacitor and the fourth capacitor are arranged in the second direction
  • the second capacitor is located between the first capacitor and the third capacitor
  • the fourth capacitor is located between the first capacitor and the third capacitor.
  • the distance between the third capacitor and the second capacitor in the second direction is greater than the distance between the first capacitor and the second capacitor in the second direction. the distance in the second direction.
  • At least one embodiment of the present disclosure further provides a display device including any of the above-mentioned display substrates.
  • FIG. 1A is a schematic diagram of an overall circuit structure of a display panel.
  • FIG. 1B is a schematic diagram of a shift register unit.
  • FIG. 1C is a signal timing diagram when the shift register unit shown in FIG. 1B operates.
  • FIG. 2A is a schematic diagram of a shift register unit.
  • FIG. 2B is a circuit diagram of a shift register unit.
  • FIG. 2C is a signal timing diagram when the shift register unit shown in FIG. 2B operates.
  • FIG. 3 is a schematic diagram of a layout of the shift register unit shown in FIG. 2B in a display substrate.
  • 4 to 12 are plan views of wirings or vias in each layer of the display substrate shown in FIG. 3 .
  • FIG. 13 to 19 are plan views of a plurality of film layers in the display substrate shown in FIG. 3 .
  • FIG. 20A is a cross-sectional view taken along line A-B of FIG. 3 .
  • 20B is a cross-sectional view of FIG. 3 along lines E1-F1, E2-F2, E3-F3, or E4-F4.
  • FIG. 21 is a schematic diagram illustrating the arrangement positions of each connection trace, transfer electrode, and wire in the display substrate shown in FIG. 3 .
  • FIG. 22 is a schematic diagram of a layout of the shift register unit shown in FIG. 2B in the display substrate.
  • 23 to 29 are plan views of wirings or vias in each layer of the display substrate shown in FIG. 22 .
  • 30 to 37 are plan views of a plurality of film layers in the display substrate shown in FIG. 22 .
  • FIG. 38 is a cross-sectional view taken along line A-B of FIG. 22 .
  • FIG. 39 is a cross-sectional view along line E1-F1, E2-F2, or E4-F4 of FIG. 22 .
  • FIG. 40 is a cross-sectional view taken along line E3-F3 of FIG. 22 .
  • FIG. 41 is a schematic diagram illustrating the arrangement positions of each connection trace, transfer electrode, and wire in the display substrate shown in FIG. 22 .
  • FIG. 42 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • FIG. 1A is a schematic diagram of an overall circuit structure of a display panel.
  • the rectangular box pointed to by reference numeral 101 represents the overall outline of the display panel; the display panel 101 includes a display area (ie, a pixel array area) 102 and a peripheral area 106 located around the display area 102 .
  • the display area 102 includes pixel units 103 arranged in an array; the peripheral area 106 includes a scan drive shift register unit 104, and a plurality of cascaded scan drive shift register units 104 form a gate drive circuit (Gate GOA) for sending
  • the pixel units 103 arranged in an array in the display area 102 of the display panel 101 provide, for example, gate scan signals shifted row by row; the peripheral area 106 also includes a light emission control shift register unit 105, a plurality of cascaded light emission control shift register units.
  • the bit register unit 105 constitutes a light-emitting control driving circuit array (EM GOA), which is used to provide, for example, a light-emitting control signal shifted row by row to the pixel units 103 arranged in the array in the display area 102 of the display panel 101, that is, for outputting The gate drive circuit of the light emission control signal.
  • EM GOA light-emitting control driving circuit array
  • the output signal output by the output circuit of one shift register unit 104 is correspondingly output to two rows of pixel units 103 , and embodiments of the present disclosure include but are not limited to this.
  • each pixel unit 103 may include pixel circuits and light-emitting elements with circuit structures such as 7T1C, 8T2C, or 4T1C in the art.
  • the light-emitting element may be, for example, an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED).
  • OLED organic light-emitting diode
  • QLED quantum dot light-emitting diode
  • Oxide semiconductors have ultra-low leakage characteristics to meet this demand.
  • FIG. 1B is a schematic diagram of a shift register unit.
  • FIG. 1C is a signal timing diagram when the shift register unit shown in FIG. 1B operates.
  • the working process of the shift register unit includes 6 stages, namely the first stage PS1, the second stage PS2, the third stage PS3, the fourth stage PS4, the fifth stage PS5 and the sixth stage PS6 .
  • the first stage PS1 is the input stage
  • the second stage PS2 is the output stage
  • the third stage PS3 is the reset stage
  • the fourth stage PS4 is the first holding period
  • the fifth stage PS5 is the second holding period
  • the sixth stage PS6 is the third holding time period. That is, the fourth stage PS4, the fifth stage PS5, and the sixth stage PS6 constitute the holding stage.
  • FIG. 1C is a signal timing diagram when the shift register unit shown in FIG. 1B operates.
  • the working process of the shift register unit includes 6 stages, namely the first stage PS1, the second stage PS2, the third stage PS3, the fourth stage PS4, the fifth stage PS5 and the sixth
  • the shift register unit adopts a 10T3C (capacitor C1-capacitor C3) structure with ten transistors (T1-T10) and three capacitors.
  • this structure is used for OLED light emission control switch EM, the effect of reset delay can be ignored, but when used for switching control of oxide thin film transistors in display substrates fabricated by LTPO process, it will seriously affect the charging time of pixel units.
  • the data lines of AMOLED are shared, and the pixel units are charged row by row, and the GOA provides the switch signal of the pixel unit. In order to prevent data mischarging, the data signal can only be changed to the data of the next row after the switch is closed, that is, after the GOA output is reset.
  • the pixel unit cannot be effectively charged during the time waiting for the GOA to reset.
  • the total time available for each row of pixel units is determined. The faster the GOA resets, the longer the pixel charging time. On the contrary, the pixel charging time is shorter, because the reset step delay may reach 2 lines of time. as long as.
  • the first pole of the transistor T1 in the first-stage shift register unit is connected to the input end EI, and the input end EI is configured to be connected to the trigger signal line to The trigger signal is received as an input signal, and the first pole of the transistor T1 in the other shift register units is electrically connected to the output end EOUT of the previous shift register unit to receive the output end of the previous shift register unit.
  • the output signal output by EOUT is used as the input signal, thereby realizing the shift output to provide the pixel units 103 arranged in an array in the display area 102 of the display panel 101 with, for example, a light-emitting control signal shifted row by row.
  • the shift register unit further includes a clock signal terminal CK and a clock signal terminal CB.
  • one of the clock signal terminal CK and the clock signal terminal CB is configured to provide the first clock signal
  • the other one of the clock signal terminal CK and the clock signal terminal CB is configured to provide the second clock signal.
  • the first clock signal and the second clock signal may adopt pulse signals with a duty cycle greater than 50%, and the difference between the two may be, for example, by half a period.
  • VGL represents the first power supply line and the first power supply voltage provided by the first power supply line
  • VGH represents the second power supply line and the second power supply voltage provided by the second power supply line
  • the second power supply voltage is greater than the first power supply voltage.
  • the second power supply voltage is a DC high level
  • the first power supply voltage is a DC low level
  • N1, N2, N3 and N4 respectively represent the first node, the second node, the third node and the fourth node in the circuit diagram .
  • the first power supply voltage VGL may be VSS
  • the second power supply voltage VGH may be VDD.
  • FIG. 1B shows the semiconductor layer LY0, the first conductive layer LY1 and the second conductive layer LY2.
  • the semiconductor layer LY0 includes the active layers of the respective transistors
  • the first conductive layer LY1 includes the source and drain electrodes of the respective transistors
  • the second conductive layer LY2 includes various connection lines.
  • the charge pump circuit is introduced into the de-noising module, so that the de-noising module can be continuously turned on in the hold phase, and the noise interference can be removed in time, thereby ensuring the stability of the GOA output and improving the stability of the driving circuit and display.
  • the denoising module includes a charge pump circuit and a denoising transistor.
  • the denoising transistor includes a first output transistor T10.
  • FIG. 2A is a schematic diagram of a shift register unit.
  • FIG. 2B is a circuit diagram of a shift register unit.
  • FIG. 2C is a signal timing diagram when the shift register unit shown in FIG. 2B operates. The working process of the shift register unit will be briefly introduced below with reference to FIGS. 2A to 2C .
  • the shift register unit 100 includes a charge pump circuit 11 .
  • the charge pump circuit 11 is electrically connected to the first input node P11, the first clock signal terminal CB, and the first node P1, respectively, and is configured to be in a first period of time, the first clock signal provided at the first clock signal terminal CB is Under the control, the potential of the first input node P11 is converted from a first voltage signal to a second voltage signal, and the second voltage signal is transmitted to the first node P1, and is configured to maintain the first node P1 for a second period of time the potential. That is, during the second time period, the potential of the first node P1 is maintained as the second voltage signal.
  • the polarity of the first voltage signal is the same as the polarity of the second voltage signal, and the absolute value of the voltage value of the second voltage signal is greater than the absolute value of the voltage value of the first voltage signal.
  • the voltage signal of the first input node P11 may be adjusted to be the first voltage signal.
  • the first time period is the first holding time period
  • the second time period is the second holding time period.
  • the voltage signal of the first input node P11 may be the first voltage signal.
  • the first time period is the first holding time period
  • the second time period is the third holding time period.
  • FIG. 2C shows the first voltage signal V01 and the second voltage signal V02.
  • the charge pump is a structure similar to a water pump in the circuit. It mainly realizes the redistribution of charges through capacitors, clocks, and diode rectification structures to achieve the purpose of boosting (or decreasing).
  • a shift register unit containing the charge pump circuit 11 can pull down or raise the potential of the first node P1 sufficiently during the hold phase through the charge pump circuit 11, so that in the hold phase, the first output transistor controlled by the first node P1 It is kept turned on, so that the potential of the driving signal output by the shift register unit can not be affected by noise interference in the holding stage.
  • the polarity of the first voltage signal is the same as the polarity of the second voltage signal means: when the first voltage signal is a positive voltage signal, the second voltage signal is a positive voltage signal; when the first voltage signal is a negative voltage signal, the second voltage signal is a negative voltage signal.
  • the absolute value of the voltage value of the second voltage signal is greater than the absolute value of the voltage value of the first voltage signal means: when the first voltage signal is a positive voltage signal, the voltage value of the second voltage signal is greater than the voltage of the first voltage signal value; when the first voltage signal is a negative voltage signal, the voltage value of the second voltage signal is smaller than the voltage value of the second voltage signal.
  • the charge pump structure 11 can further lower or raise the potential of the first node P1 in the hold phase.
  • the charge pump circuit can convert the first voltage
  • the potential pump of the signal is 2-3 times lower, but not limited to this.
  • the shift register unit 100a includes 14 transistors T1-T14 and 4 capacitors (a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4).
  • FIG. 2B shows the first pole a and the second pole b of each transistor, and the first pole a and the second pole b of each capacitor.
  • T1-T14 shown in the figures are simplified as transistors T1-T14.
  • each transistor can be named Define, for example, the transistor T1 is called the second control transistor T1, the transistor T2 is called the fourth control transistor T2, the transistor T3 is called the third control transistor T3, the transistor T4 is called the second transistor T4, and the transistor T5 is called the second control transistor T4.
  • the transistor T5 It is called the first transistor T5, the transistor T6 is called the fifth control transistor T6, the transistor T7 is called the sixth control transistor T7, the transistor T8 is called the seventh control transistor T8, and the transistor T9 is called the second output transistor T9 , the transistor T10 is called the first output transistor T10, the transistor T11 is called the first node control transistor T11, the transistor T12 is called the first control transistor T12, the transistor T13 is called the first isolation transistor T13, and the transistor T14 is called As the second isolation transistor T14.
  • the first pole of the first control transistor T12 in the first-stage shift register unit 100a is connected to the input terminal EI, and the input terminal EI is configured to be connected to the trigger signal line
  • the receiving trigger signal is used as the input signal
  • the first pole of the first control transistor T12 in the shift register unit 100a of other levels is electrically connected to the output end EOUT of the shift register unit 100a of the previous stage to receive the shift register unit 100a of the previous stage.
  • the output signal output by the output terminal EOUT of the bit register unit 100a is used as an input signal, thereby realizing a shift output to provide the pixel units 103 arranged in an array in the display area 102 of the display panel 101 to provide, for example, a line-by-line shift light emission control Signal.
  • the shift register unit 100a further includes a first clock signal terminal CB and a second clock signal terminal CB2.
  • the first clock signal terminal CB is connected to the first clock signal line or the second clock signal line to receive the first clock signal.
  • the first clock signal line provides the first clock signal;
  • the second clock signal line A first clock signal is provided; it depends on the actual situation, which is not limited by the embodiments of the present disclosure.
  • the second clock signal terminal CB2 is connected to the second clock signal line or the first clock signal line to receive the second clock signal.
  • the first clock signal terminal CB is connected to the first clock signal line to receive the first clock signal
  • the second clock signal terminal CB2 is connected to the second clock signal line to receive the second clock signal.
  • the first clock signal and the second clock signal may adopt pulse signals with a duty cycle greater than 50%, and the two may differ by half a cycle, for example.
  • the shift register unit further includes a third clock signal terminal CK and a fourth clock signal terminal CK2 (not shown in FIG. 2B ).
  • the third clock signal terminal CK shown in FIG. 2B may be replaced by the fourth clock signal terminal CK2 in the shift register unit at the next stage of the shift register unit shown in FIG. 2B .
  • the third clock signal terminal CK is connected to the third clock signal line or the fourth clock signal line to receive the third clock signal.
  • the third clock signal line provides the third clock signal; when the third clock signal end CK is connected to the fourth clock signal line, the fourth clock signal line A third clock signal is provided; it depends on the actual situation, which is not limited by the embodiments of the present disclosure.
  • the fourth clock signal terminal CK2 is connected to the third clock signal line or the fourth clock signal line to receive the fourth clock signal.
  • the third clock signal terminal CK is connected to the third clock signal line to receive the third clock signal
  • the fourth clock signal terminal CK2 is connected to the fourth clock signal line to receive the fourth clock signal.
  • the third clock signal and the fourth clock signal may adopt pulse signals with a duty ratio greater than 50%, and the two may differ by half a period, for example.
  • VGL represents the first power supply line and the first power supply voltage provided by the first power supply line
  • VGH represents the second power supply line and the second power supply voltage provided by the second power supply line
  • the first power supply voltage is greater than the second power supply voltage.
  • the first power supply voltage is a DC high level
  • the second power supply voltage is a DC low level.
  • P31, P11, P1, P2, P12, P13, and P32 respectively represent the first isolation node, first input node, first node, second node, second input node, third input node, and a second isolated node. That is, FIG.
  • the shift register unit 100 a includes a charge pump circuit 11 , a first isolation node control subcircuit 41 , a first isolation subcircuit 42 , a first tank circuit 31 , a first node control circuit 12 , and a second isolation node Node control subcircuit 32 , second isolation subcircuit 40 , second input node control subcircuit 33 , second node control subcircuit 34 , and output circuit 30 .
  • the charge pump circuit 11 includes a first clock signal terminal CB, a first capacitor C1, a first transistor T5 and a second capacitor C2.
  • the first plate of the first capacitor C1 is connected to the first clock signal terminal CB, and the second plate of the first capacitor C1 is connected to the first input node P11.
  • the first pole of the first transistor T5 is connected to the first input node P11, and the second pole of the first transistor T5 is connected to the first node P1.
  • the gate of the first transistor T5 is connected to the first electrode or the second electrode of the first transistor T5 to form a diode-connected triode.
  • the first plate of the second capacitor C2 is connected to the first power line VGL, and the second plate of the second capacitor C2 is connected to the first node P1.
  • the charge pump circuit 11 further includes a second transistor T4.
  • the gate of the second transistor T4 is electrically connected to the first input node P11
  • the first pole of the second transistor T4 is electrically connected to the first clock signal terminal CB
  • the second pole of the second transistor T4 is electrically connected to the first terminal of the first capacitor C1
  • the plates are electrically connected.
  • the charge pump circuit 11 may not include the second transistor T4.
  • the first clock signal terminal CB is connected to the first plate of the first capacitor C1. .
  • the output circuit 30 is respectively connected to the first node P1, the second node P2, the first power supply line VGL, the second clock signal terminal CB2 and the output terminal EOUT, and the output circuit 30 is configured to be at the first node P1 Under the control of the potential of the second node P2, the first power supply voltage is output to the output terminal EOUT for reset, and under the control of the potential of the second node P2, the second clock signal is output to the output terminal EOUT to output a valid driving signal .
  • the output circuit 30 includes a first output transistor T10 and a second output transistor T9.
  • the gate of the first output transistor T10 is electrically connected to the first node P1
  • the first pole of the first output transistor T10 is electrically connected to the first power supply line VGL
  • the second pole of the first output transistor T10 is electrically connected to the driving signal output terminal EOUT. connect.
  • the gate of the second output transistor T9 is electrically connected to the second node P2, the first pole of the second output transistor T9 is electrically connected to the driving signal output terminal EOUT, and the second pole of the second output transistor T9 is electrically connected to the second clock signal terminal CB2 electrical connection.
  • the first output transistor T10 is a p-type transistor, and the first voltage signal is a negative voltage signal; or, the first output transistor T10 is an n-type transistor, and the first voltage signal is a positive voltage signal.
  • the first voltage signal when the first output transistor is a p-type transistor, the first voltage signal may be a negative voltage signal, and the charge pump circuit 11 may further pull down the potential of the first node P1; when the first output transistor is an n-type transistor, the first voltage signal may be a negative voltage signal.
  • a voltage signal may be a positive voltage signal, and the charge pump circuit 11 may further increase the potential of the first node P1; but not limited thereto.
  • the working process of the shift register unit includes 6 stages, namely the first stage PS1, the second stage PS2, the third stage PS3, the fourth stage PS4, the fifth stage PS5 and the sixth stage PS6 .
  • the first stage PS1 is the input stage
  • the second stage PS2 is the output stage
  • the third stage PS3 is the reset stage
  • the fourth stage PS4 is the first holding period
  • the fifth stage PS5 is the second holding period
  • the sixth stage PS6 is the third holding time period. That is, the fourth stage PS4, the fifth stage PS5, and the sixth stage PS6 constitute the holding stage.
  • a working cycle of the shift register unit may include an input stage, an output stage, a reset stage and a hold stage which are set in sequence.
  • the input terminal provides an input signal; in the output stage, the shift register The unit outputs a valid drive signal; in the reset stage, the drive signal is reset so that the shift register unit outputs an invalid drive signal; in the hold stage, the shift register unit needs to keep outputting the invalid drive signal.
  • the driving signal output by the shift register unit is output to the gate of the transistor of the pixel circuit.
  • the transistor receiving the driving signal output by the shift register unit is an n-type transistor
  • the potential of the valid driving signal is a high voltage
  • the potential of the invalid driving signal is a high voltage
  • the potential of the driving signal is a low voltage.
  • the transistor receiving the driving signal output from the shift register unit is a p-type transistor
  • the potential of the valid driving signal is a low voltage
  • the potential of the invalid driving signal is a high voltage.
  • the first tank circuit 31 is respectively connected to the second node P2 and the second clock signal terminal CB2, and the first tank circuit 31 is configured to control the potential of the second node P2.
  • the first tank circuit 31 is configured to maintain the potential of the second node P2 during the hold phase.
  • the first tank circuit 31 includes a third capacitor C3, the first plate of the third capacitor C3 is electrically connected to the second node P2, and the second plate of the third capacitor C3 is connected to the second clock The signal terminal CB2 is connected.
  • the first isolation node control sub-circuit 41 is respectively electrically connected to the second clock signal terminal CB2, the third clock signal terminal CK, the input terminal EI and the first isolation node P31, and is configured to operate at the second clock signal Under the control of the third clock signal of the sum signal, the input signal of the input terminal EI is transmitted to the first isolation node P31.
  • the first isolated node control sub-circuit 41 includes a first control transistor T12 and a second control transistor T1.
  • the gate of the first control transistor T12 is electrically connected to the second clock signal terminal CB2
  • the first pole of the first control transistor T12 is electrically connected to the input terminal EI
  • the gate of the second control transistor T1 is electrically connected to the second clock signal terminal CB2.
  • the three clock signal terminals CK are electrically connected, the first pole of the second control transistor T1 is electrically connected to the second pole of the first control transistor T12, and the second pole of the second control transistor T1 is electrically connected to the first isolation node P31.
  • the input end EI is connected to the trigger signal line to receive the trigger signal; when the shift register unit is other than the first-stage shift register unit When the shift register unit is one stage, the input terminal EI is connected to the output terminal EOUT of the previous stage shift register unit.
  • the first isolated node control sub-circuit 41 may include only the first control transistor T12 or only the second control transistor T1. For example, arranging the first control transistor T12 and the second control transistor T1 can help to reduce leakage current.
  • the first isolation sub-circuit 42 is electrically connected to the first power supply line VGL, the first isolation node P31 and the first input node P11 respectively, and is configured to control the first isolation node P31 and the first input node P11 connection between. For example, setting the first isolation sub-circuit 42 can reduce the leakage of the first input node P11 to the first isolation node P31, that is, the potential of the first isolation node P31 can be maintained when the potential of the first input node P11 changes, so as to Improve the response speed of the drive signal output.
  • the first isolation sub-circuit 42 includes a first isolation transistor T13. As shown in FIG.
  • the gate of the first isolation transistor T13 is electrically connected to the first power supply line VGL
  • the first pole of the first isolation transistor T13 is electrically connected to the first input node P11
  • the second pole of the first isolation transistor T13 is electrically connected It is electrically connected to the first isolation node P31.
  • setting the first isolation transistor T13 can reduce the leakage of the first input node P11 to the first isolation node P31, so that the response speed of the output of the driving signal is faster.
  • the first isolation subcircuit 42 may not be provided, that is, the first isolation transistor T13 may not be provided. In this case, the first isolation node P31 and the first input node P11 are the same node.
  • the second node control sub-circuit 34 is electrically connected to the first clock signal terminal CB, the second input node P12, the second node P2, the first isolation node P31, and the second power line VGH, respectively.
  • the node control sub-circuit 34 is configured to turn on or off the connection between the second input node P12 and the second node P2 under the control of the first clock signal, and is used for the control of the potential of the first isolation node P31 , the second power supply voltage is written into the second node P2 to control the potential of the second node P2.
  • the second node control sub-circuit 34 includes a sixth control transistor T7 and a seventh control transistor T8.
  • the gate of the sixth control transistor T7 is electrically connected to the first clock signal terminal CB
  • the first electrode of the sixth control transistor T7 is electrically connected to the second input node P12
  • the second gate of the sixth control transistor T7 is electrically connected to the second input node P12.
  • the pole is electrically connected to the second node P2.
  • the gate of the seventh control transistor T8 is electrically connected to the first isolation node P31
  • the first pole of the seventh control transistor T8 is electrically connected to the second power supply line VGH
  • the second pole of the seventh control transistor T8 is electrically connected to the second node P2.
  • the sixth control transistor T7 can prevent the leakage of electricity to the second input node P12, isolate the influence of the fourth capacitor C4 on the second node P2, and enhance the second clock signal provided by the second clock signal terminal CB2 to the second node P2.
  • the coupling effect of so that when the potential of the second clock signal decreases, the potential of the second node P2 can be lower, thereby speeding up the discharge speed of the second output transistor T9 to the output terminal EOUT.
  • the second input node control sub-circuit 33 is electrically connected to the third input node P13, the second input node P12 and the first clock signal terminal CB, respectively, and the second input node control sub-circuit 33 is configured to The first clock signal is written into the second input node P12 under the control of the potential of the three-input node P13, and is configured to control the potential of the second input node P12 according to the potential of the third input node P13.
  • the second input node control sub-circuit 33 includes a fifth control transistor T6 and a fourth capacitor C4. As shown in FIG.
  • the gate of the fifth control transistor T6 is electrically connected to the third input node P13
  • the first electrode of the fifth control transistor T6 is electrically connected to the second input node P12
  • the second electrode of the fifth control transistor T6 is electrically connected It is electrically connected to the first clock signal terminal CB.
  • the first plate of the fourth capacitor C4 is electrically connected to the third input node P13
  • the second plate of the fourth capacitor C4 is electrically connected to the second input node P12.
  • the second isolation node control sub-circuit 32 is respectively connected to the first isolation node P31 , the second isolation node P32 , the third clock signal terminal CK and the first power supply line VGL, and is configured to operate at the first isolation node Under the control of the potential of the node P31 and the third clock signal, the first power supply voltage or the third clock signal is input to the second isolation node P32 to control the potential of the second isolation node P32.
  • the second isolated node control sub-circuit 32 includes a third control transistor T3 and a fourth control transistor T2.
  • the gate of the third control transistor T3 is electrically connected to the third clock signal terminal CK
  • the first electrode of the third control transistor T3 is electrically connected to the first power line VGL
  • the second terminal of the third control transistor T3 is electrically connected to the first power line VGL.
  • the pole is electrically connected to the second isolation node P32.
  • the gate of the fourth control transistor T2 is electrically connected to the first isolation node P31
  • the first electrode of the fourth control transistor T2 is electrically connected to the third clock signal terminal CK
  • the second gate of the fourth control transistor T2 is electrically connected to the third clock signal terminal CK.
  • the pole is electrically connected to the second isolation node P32.
  • the second isolation sub-circuit 40 is respectively connected to the second isolation node P32, the third input node P13, and the first power supply line VGL, and is configured to control the second isolation node P32 and the third input node P13 connection between.
  • the provision of the second isolation sub-circuit 40 can prevent the leakage of electricity from the third input node P13 to the second isolation node P32, and isolate the influence of the fourth capacitor C4 on the second isolation node P32.
  • the second isolation sub-circuit 40 includes a second isolation transistor T14.
  • the gate of the second isolation transistor T14 is electrically connected to the first power supply line VGL
  • the first pole of the second isolation transistor T14 is electrically connected to the second isolation node P32
  • the second pole of the second isolation transistor T14 is electrically connected to the second isolation node P32. It is electrically connected to the third input node P13. Setting the second isolation transistor T14 can reduce the leakage of the third input node P13 to the second isolation node P32, so that the response speed of the output of the driving signal is faster.
  • the second isolation sub-circuit 40 may not be provided, that is, the second isolation transistor T14 may not be provided. In this case, the second isolation node P32 and the third input node P13 are the same node.
  • the first node control circuit 12 is electrically connected to the second input node P12, the second power supply line VGH, and the first node P1, respectively, and is configured to be controlled by the potential of the second input node P12, The second power supply voltage is written into the first node P1 to control the potential of the first node P1.
  • the first node control circuit 12 includes a first node control transistor T11. As shown in FIG.
  • the gate of the first node control transistor T11 is electrically connected to the second input node P12
  • the first electrode of the first node control transistor T11 is electrically connected to the second power line VGH
  • the first node control transistor T11 is electrically connected to the second power line VGH.
  • the second pole is electrically connected to the first node P1.
  • the transistors in the shift register unit 100a shown in FIG. 2B are all illustrated by taking P-type transistors as an example, that is, each transistor is turned on when the gate is connected to a low level (on-level), and is turned on when the gate is connected to a low level (on-level). It is cut off when it enters a high level (cut-off level).
  • the first electrode of the transistor may be the source electrode and the second electrode of the transistor may be the drain electrode.
  • the shift register unit includes, but is not limited to, the arrangement in FIG. 2B.
  • each transistor in the shift register unit 100a can also use N-type transistors or a mixture of P-type transistors and N-type transistors.
  • the port polarities of the transistors can be connected according to the port polarities of the corresponding transistors in the embodiments of the present disclosure.
  • the transistors used in the shift register unit can all be thin film transistors or field effect transistors or other switching devices with the same characteristics. channel region) using semiconductor materials, such as polysilicon (such as low temperature polysilicon or high temperature polysilicon), amorphous silicon, indium gallium tin oxide (IGZO), etc., while the gate, source, drain, etc. use metal materials, such as metal aluminum or aluminum alloy.
  • semiconductor materials such as polysilicon (such as low temperature polysilicon or high temperature polysilicon), amorphous silicon, indium gallium tin oxide (IGZO), etc.
  • the gate, source, drain, etc. use metal materials, such as metal aluminum or aluminum alloy.
  • the source and drain of the transistor used here may be symmetrical in structure, so the source and drain of the transistor may be indistinguishable in structure.
  • one pole is directly described as the first pole, and the other pole is the second pole.
  • the electrode plate of the capacitor may be a metal electrode or one of the electrode plates may be a semiconductor material (eg, doped polysilicon).
  • the material of the electrode plate of the capacitor in the embodiment of the present disclosure is described by taking metal as an example.
  • FIG. 2C is a signal timing diagram and a schematic diagram of potential waveforms of each node when the shift register unit 100a shown in FIG. 2B operates.
  • the working process of the shift register unit will be described in detail below with reference to FIG. 2B and FIG. 2C .
  • the working principle of the shift register unit of the N+2th stage is used for description, and the working principles of the shift register units of the other stages are similar to them, and will not be repeated here.
  • the working process of the shift register unit includes 6 stages, namely the first stage PS1, the second stage PS2, the third stage PS3, the fourth stage PS4, the fifth stage PS5 and the sixth stage PS6
  • Figure 2C shows the timing waveforms of the various signals in each stage.
  • the first stage PS1 is the input stage
  • the second stage PS2 is the output stage
  • the third stage PS3 is the reset stage
  • the fourth stage PS4 is the first holding period
  • the fifth stage PS5 is the second holding period
  • the sixth stage PS6 is the third holding time period. That is, the fourth stage PS4, the fifth stage PS5, and the sixth stage PS6 constitute the holding stage.
  • the third clock signal terminal CK provides a low voltage
  • the first clock signal terminal CB provides a high voltage
  • the second clock signal terminal CB2 provides a low voltage
  • the input terminal EI provides a high voltage
  • the first clock signal terminal CB provides a low voltage.
  • a control transistor T12 and a second control transistor T1 are turned on, the first isolation transistor T13 is turned on, the potential of the first input node P11 is a high voltage, the potential of the first isolation node P31 is a high voltage, the first transistor T5 and the second transistor T4 are turned off; the fourth control transistor T2 is turned off, the third control transistor T3 is turned on, the second isolation transistor T14 is turned on, the potential of the second isolation node P32 is a low voltage, the potential of the third input node P13 is a low voltage, the fifth The control transistor T6 is turned on, the potential of the second input node P12 is a high voltage, the sixth control transistor T7 is turned off, the seventh control transistor T8 is turned off, the first node control transistor T11 is turned off, the potential of the first node P1 is maintained at a low voltage, and the first node control transistor T11 is turned off.
  • the potential of the two nodes P2 is maintained at a high voltage
  • the first output transistor T10 is turned on
  • the third clock signal terminal CK provides a high voltage
  • the first clock signal terminal CB provides a low voltage
  • the second clock signal terminal CB2 provides a high voltage
  • the input terminal EI provides When the voltage is low, the first control transistor T12 and the second control transistor T1 are both turned off.
  • the potential of the first input node P11 is maintained at a high voltage, the first isolation transistor T13 is turned on, and the first isolation node
  • the potential of P31 is a high voltage
  • the second transistor T4 is turned off, the first transistor T5 is turned off, the fourth control transistor T2 is turned off, the third control transistor T3 is turned off, the potential of the second isolation node P32 is maintained at a low voltage, and the second isolation node
  • the transistor T14 is turned off, the potential of the third input node P13 is further pulled down by the fourth capacitor C4, the fifth control transistor T6 is turned on, the potential of the second input node P12 is low voltage, the sixth control transistor T7 is turned on, and the seventh control transistor T8 is turned off, the first node control transistor T11 is turned on, the potential of the first node P1 is a high voltage, the potential of the second node P2 is a low voltage, the second output transistor T9 is turned on, the first output transistor T10 is turned off, and the
  • the third clock signal terminal CK provides a low voltage
  • the first clock signal terminal CB provides a high voltage
  • the second clock signal terminal CB2 provides a low voltage
  • the input terminal EI provides a low voltage
  • the first clock signal terminal CB provides a low voltage.
  • a control transistor T12 and a second control transistor T1 are both turned on, the potential of the first input node P11 is pulled down, the first isolation transistor T13 is turned on, the potential of the first isolation node P31 is pulled down, the fourth control transistor T2 is turned on, and the first isolation transistor T1 is turned on.
  • the second transistor T4 is turned on, the first transistor T5 is turned on, the potential of the first node P1 is pulled down; the first output transistor T10 is turned on; the third control transistor T3 is turned on, the potential of the second isolation node P32 is a low voltage, and the second isolation transistor T14 is turned on, the fifth control transistor T6 is turned on, the potential of the third input node P13 and the potential of the second input node P12 are pulled high, the sixth control transistor T7 is turned off, the first node control transistor T11 is turned off; the seventh control transistor T8 is turned on, the potential of the second node P2 is a high voltage, the second output transistor T9 is turned off, and the output terminal EOUT outputs a low voltage.
  • the third clock signal terminal CK provides a high voltage
  • the first clock signal terminal CB provides a low voltage
  • the second clock signal terminal CB2 provides a high voltage
  • the input terminal EI provides a low voltage
  • the first clock signal terminal CB provides a high voltage.
  • a control transistor T12 and a second control transistor T1 are both turned off, the second transistor T4 is turned on, the first clock signal terminal CB pulls down the potential of the first input node P11 through the first capacitor C1, the first isolation transistor T13 is turned off, the first The potential of the isolation node P31 is maintained at a low voltage, and the first transistor T5 is turned on, so that the potential of the first node P1 is pulled down and maintained below VSS+Vth, where Vth is the threshold voltage of the first output transistor T10, so that the first The output transistor T10 is turned on, so that the potential of the driving signal output by the output terminal EOUT is maintained at VSS, which is not affected by noise interference; the third control transistor T3 is turned off, the fourth control transistor T2 is turned on, and the potential of the second isolation node P32 is high voltage, the second isolation transistor T14 is turned on, the potential of the third input node P13 is a high voltage, the fifth control transistor T6 is turned off, the potential of the second input node P12 is
  • the third clock signal terminal CK provides a low voltage
  • the first clock signal terminal CB provides a high voltage
  • the second clock signal terminal CB2 provides a low voltage
  • the input terminal EI provides a low voltage
  • the first clock signal terminal CB provides a low voltage.
  • a control transistor T12 and a second control transistor T1 are both turned on, the potential of the first input node P11 is a low voltage, the first isolation transistor T13 is turned on, the second transistor T4 is turned on, and the first clock signal provided by the first clock signal terminal CB The potential increases, so that the potential of the first input node P11 is pulled up through the first capacitor C1, and the first transistor T5 is turned off, which does not affect the potential of the first node P1.
  • the potential is maintained to be lower than VSS+Vth, and Vth is the threshold voltage of the first output transistor T10, so that the first output transistor T10 is turned on, so that the potential of the driving signal output by the output terminal EOUT is maintained at VSS, which is not affected by noise interference;
  • the third control transistor T3 is turned on, the fourth control transistor T2 is turned on, the potential of the second isolation node P32 is low voltage, the second isolation transistor T14 is turned on, the potential of the third input node P13 is low voltage, the fifth control transistor T6 is turned on, the first The potential of the second input node P12 is a high voltage, the first node control transistor T11 is turned off, the sixth control transistor T7 is turned off, the seventh control transistor T8 is turned on, the potential of the second node P2 is a high voltage, and the second output transistor T9 is turned off break.
  • the third clock signal terminal CK provides a high voltage
  • the first clock signal terminal CB provides a low voltage
  • the second clock signal terminal CB2 provides a high voltage
  • the input terminal EI provides a low voltage
  • the first clock signal terminal CB provides a high voltage.
  • a control transistor T12 and a second control transistor T1 are both turned off, the potential of the first input node P11 is maintained at a low voltage, the second transistor T4 is turned on, and the first clock signal terminal CB pulls down the first input node P11 through the first capacitor C1.
  • the first transistor T5 is turned on, so that the potential of the first node P1 is maintained below VSS+Vth, Vth is the threshold voltage of the first output transistor T10, so that the first output transistor T10 is turned on, thereby making the output terminal EOUT output
  • the potential of the driving signal is maintained at VSS and is not affected by noise interference;
  • the first isolation transistor T13 is turned off, the potential of the first isolation node P31 is maintained at a low voltage, the third control transistor T3 is turned off, the fourth control transistor T2 is turned on, and the second control transistor T2 is turned on.
  • the potential of the isolation node P32 is a high voltage
  • the second isolation transistor T14 is turned on
  • the potential of the third input node P13 is a high voltage
  • the fifth control transistor T6 is turned off
  • the potential of the second input node P12 is a high voltage
  • the first node controls the transistor T11 is turned off
  • the sixth control transistor T7 is turned on
  • the seventh control transistor T8 is turned on
  • the potential of the second node P2 is a high voltage
  • the second output transistor T9 is turned off.
  • the potential of the first node P1 can be maintained below VSS+Vth, where Vth is the threshold voltage of the first output transistor T10, so that the first output transistor T10 is turned on, thereby maintaining the potential of the driving signal output by the output terminal EOUT It is VSS and is not affected by noise interference.
  • the first input node P11 is at a low level VSS
  • the transistor T1 and the transistor T12 are used to initialize the first input node P11 to be VSS
  • the first capacitor C1 and the second transistor T4 It is used to further lower the potential of the first input node P11 at the falling edge of the first clock signal, save the low level to the first node P1 through the first transistor T5 of the diode structure, and store charges through the second capacitor C2 to maintain the potential.
  • FIG. 2C shows the first voltage signal V01 and the second voltage signal V02.
  • the polarities of the first voltage signal V01 and the second voltage signal V02 are the same, and the absolute value of the voltage value of the second voltage signal V02 is greater than the absolute value of the voltage value of the first voltage signal V01.
  • FIG. 3 is a schematic diagram of a layout of the shift register unit 100a shown in FIG. 2B in the display substrate.
  • the display substrate includes a base substrate 10 , a shift register unit 100aa disposed on the base substrate 10 , a first power supply line VGL, a second power supply line VGH, and a plurality of clock signal lines.
  • the plurality of clock signal lines include a first clock signal line ECB, a second clock signal line ECB2, a third clock signal line ECK, and a fourth clock signal line ECK2 shown in the figure, and may also include a trigger signal line (in the figure not shown).
  • the shift register unit 100aa is a light emission control shift register unit.
  • a first power supply line VGL, a second power supply line VGH, and a plurality of clock signal lines extend along the first direction Y on the base substrate 10 , and are configured to respectively supply a first power supply voltage, a second power supply voltage and a plurality of clock signals (eg, the above-mentioned first power supply voltage) to the shift register unit 100aa clock signal, second clock signal, etc.).
  • the first power supply line VGL is configured to provide a first power supply voltage to the shift register unit 100aa
  • the second power supply line VGH is configured to provide a second power supply voltage to the shift register unit 100aa
  • the first clock signal line ECB and the The two clock signal lines ECB2 are configured to supply the first clock signal or the second clock signal to the shift register unit 100aa, respectively.
  • the first power supply voltage is lower than the second power supply voltage, for example, the first power supply voltage is a DC low level, and the second power supply voltage is a DC high level.
  • the first clock signal line ECB is used to provide the first clock signal to the shift register unit 100aa
  • the second clock signal line ECB2 is used to provide the second clock signal to the shift register unit 100aa as follows: examples to illustrate, the embodiments of the present disclosure include, but are not limited to.
  • the first clock signal line ECB may also provide the shift register unit 100aa with the second clock signal
  • the second clock signal line ECB2 may provide the shift register unit 100aa with the first clock signal.
  • the disclosed embodiments are not limited in this regard.
  • the third clock signal is provided to the shift register unit 100aa by the third clock signal line ECK
  • the fourth clock signal is provided to the shift register unit 100aa by the fourth clock signal line ECK2 as follows:
  • the third clock signal line ECK may also provide a fourth clock signal to the shift register unit 100aa
  • the fourth The clock signal line ECK2 provides a third clock signal to the shift register unit 100aa, which is not limited by the embodiment of the present disclosure.
  • first power supply line VGL, the second power supply line VGH and the plurality of clock signal lines may extend along the first direction Y and be arranged parallel to each other, or may cross a certain angle (for example, less than or equal to 20°).
  • the disclosed embodiments are not limited in this regard.
  • the base substrate 10 may be made of glass, plastic, quartz or other suitable materials, which are not limited by the embodiments of the present disclosure.
  • the display substrate 1 includes a display area 102 (eg, the display area 102 may also be referred to as a pixel array area) and a peripheral area 106 on at least one side of the pixel array area.
  • the shift register unit 100aa provided by the embodiment of the present disclosure may be the light-emitting control shift register unit 105 shown in FIG. 1A , for example, the above-mentioned first power supply line VGL, second power supply line VGH, multiple clock signal lines and shift registers
  • the register unit 100aa is located on the peripheral area 106 of the base substrate 10 and is located on one side of the base substrate 10 (as shown in FIG.
  • FIG. 1A between the display area 102 and the side of the base substrate 10), for example, as shown in FIG. 1A As shown, it is located on the left side of the base substrate 10 , of course, it can also be located on the right side or both left and right sides of the base substrate 10 , which is not limited by the embodiment of the present disclosure.
  • the orthographic projection of the first power supply line VGL on the base substrate 10 and the orthographic projection of the plurality of clock signal lines on the base substrate 10 are located at the position of the shift register unit 100aa on the base substrate 10
  • the side of the orthographic projection away from the display area 102 is located on the left side of the shift register unit 100aa shown in FIG. 3 .
  • the second power supply line VGH is located on the side of the orthographic projection of the shift register unit 100aa on the base substrate 10 close to the display area 102, for example, in the second direction X, located on the right side of the shift register unit 100aa shown in FIG. 3 side.
  • the orthographic projection of the first power supply line VGL on the base substrate 10 is located on the clock signal line (including the first clock signal line ECB, the second clock signal line ECB2, the third clock signal line ECK and the third clock signal line Between the orthographic projection of the four clock signal lines ECK2) on the base substrate 10 and the orthographic projection of the shift register unit 100aa on the base substrate 10.
  • the second clock signal line ECB2, the fourth clock signal line ECK2, the first clock signal line ECB, and the third clock signal line ECK are sequentially arranged on the base substrate 10 from left to right along the second direction X.
  • the above-mentioned multiple clock signal lines may further include trigger signal lines for providing trigger signals.
  • the orthographic projection of the trigger signal line on the base substrate 10 may be located on the side of the orthographic projection of the second clock signal line ECB2 on the base substrate 10 away from the orthographic projection of the shift register unit 100aa on the base substrate 10, That is, the trigger signal line, the second clock signal line ECB2, the fourth clock signal line ECK2, the first clock signal line ECB, and the third clock signal line ECK go from left to right in the second direction X on the base substrate 10 Set in sequence.
  • the included angle between the first direction Y and the second direction X is between 70° and 90°, inclusive.
  • the included angle between the first direction Y and the second direction X is 70°, 75°, 85°, 90°, or 80°, etc.
  • the specific value of the included angle can be set according to the actual situation. No restrictions apply.
  • the display area 102 includes a plurality of pixel units 103 arranged in an array.
  • each of the plurality of pixel units 103 includes a pixel circuit, and may further include, for example, a light-emitting element (not shown in the figure).
  • the light emitting element includes an organic light emitting diode, but is not limited thereto.
  • a plurality of cascaded shift register units 100aa constitute an emission control driving circuit array (EM GOA).
  • the output terminals EOUT of the plurality of shift register units 100aa are respectively connected with the light-emitting control signal terminals of the pixel circuits in each row of the pixel array area to provide output signals (eg, light-emitting control signals) to the pixel circuits in each row, so as to realize driving The light-emitting element emits light.
  • the pixel circuit may be a pixel circuit including circuit structures such as 7T1C, 2T1C, 4T2C, and 8T2C in the art, and details are not described herein again.
  • stage shift register unit 100aa in the gate driving circuit is shown in FIG. 3 .
  • the first clock signal terminal CB (shown in FIG. 2B ) of the first stage shift register unit (not shown in the figure) is connected to the third clock signal line ECK to receive the first clock signal, and the first stage shifts
  • the second clock signal terminal CB2 of the register unit is connected to the fourth clock signal line ECK2 to receive the second clock signal, and the third clock signal terminal CK (as shown in FIG.
  • the line ECB is connected to receive the third clock signal
  • the fourth clock signal terminal CK2 of the first stage shift register unit and the fourth clock signal line ECB2 are connected to receive the fourth clock signal
  • the trigger signal line (not shown in the figure) is connected to receive the trigger signal
  • the first clock signal terminal CB of the second stage shift register unit (not shown in the figure) is connected to the first clock signal line ECB to receive the first clock signal
  • the second clock signal terminal CB2 of the second stage shift register unit is connected to the second clock signal line ECB2 to receive the second clock signal
  • the third clock signal of the second stage shift register unit (not shown in the figure)
  • the terminal CK is connected to the third clock signal line ECK to receive the third clock signal
  • the fourth clock signal terminal CK2 of the second-stage shift register unit is connected to the fourth clock signal line ECK2 to receive the fourth clock signal; and so on, As shown in FIG.
  • the first clock signal terminal CB of the Kth (K is an even number greater than or equal to 2) stage shift register unit 100aa is connected to the first clock signal line ECB to receive the first clock signal, and the Kth
  • the second clock signal terminal CB2 of the stage shift register unit is connected to the second clock signal line ECB2 to receive the second clock signal
  • the third clock signal terminal CK of the Kth stage shift register unit (not shown in the figure) is connected to the second clock signal line ECB2.
  • the three clock signal lines ECK are connected to receive the third clock signal
  • the fourth clock signal terminal CK2 of the Kth stage shift register unit is connected to the fourth clock signal line ECK2 to receive the fourth clock signal
  • the K+1th stage shift register The first clock signal terminal CB of the unit is connected to the third clock signal line ECK to receive the first clock signal
  • the second clock signal terminal CB2 of the K+1 stage shift register unit is connected to the fourth clock signal line ECK2 to receive the first clock signal.
  • Two clock signals, the third clock signal terminal CK (as shown in FIG.
  • connection manner of the shift register units at all levels and the clock signal line may also adopt other connection manners in the art, which are not limited by the embodiments of the present disclosure.
  • the input terminal EI of the first-stage shift register unit is connected to the trigger signal line to receive the trigger signal as the input signal
  • the input terminal of the second-stage shift register unit is connected to the upper-stage shift register unit (ie, the first-stage shift register unit)
  • the output end EOUT of the shift register unit) is connected, and the input ends of the other shift register units are connected in a similar manner.
  • Kth K is an even number greater than or equal to 2
  • stage shift register unit 100aa as an example for description, which is not limited by the embodiments of the present disclosure.
  • the embodiment of the present disclosure only schematically shows four clock signal lines (a first clock signal line ECB, a second clock signal line ECB2, a third clock signal line ECK, and a fourth clock signal line ECK2)
  • the display substrate provided by the embodiments of the present disclosure may further include more than 6 or 8 clock signal lines, which are not limited by the embodiments of the present disclosure.
  • the connection relationship between the shift register unit 100aa and the clock signal lines in the display substrate also changes accordingly. The conventional design will not be repeated here.
  • FIG. 4 to 12 are plan views of wirings or vias in each layer of the display substrate shown in FIG. 3 .
  • 13 to 19 are plan views of a plurality of film layers in the display substrate shown in FIG. 3 .
  • FIG. 20A is a cross-sectional view taken along line A-B of FIG. 3 .
  • 20B is a cross-sectional view of FIG. 3 along lines E1-F1, E2-F2, E3-F3, or E4-F4.
  • FIG. 21 is a schematic diagram illustrating the arrangement positions of each connection trace, transfer electrode, and wire in the display substrate shown in FIG. 3 .
  • FIG. 4 is a plan view of an active layer of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 4 is a plan view of an active layer of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 5 is a plan view of a first conductive layer of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 6 is at least one embodiment of the present disclosure.
  • FIG. 7 is a distribution diagram of via holes penetrating a third insulating layer (second interlayer insulating layer) of a display substrate according to at least one embodiment of the disclosure
  • FIG. 8 is a distribution diagram of the via holes penetrating the first insulating layer of the display substrate provided by at least one embodiment of the present disclosure
  • FIG. 9 is a plan view of the third conductive layer of the display substrate provided by at least one embodiment of the present disclosure
  • FIG. 10 is a schematic diagram of the present disclosure.
  • FIG. 12 is a plan view of a fourth conductive layer of a display substrate according to at least one embodiment of the present disclosure.
  • 13 is a schematic view of stacking a semiconductor layer LY0 of a display substrate and a via hole passing through the interlayer insulating layer ILD (the first insulating layer IL1 , the second insulating layer IL2 and the third insulating layer IL3 ) according to at least one embodiment of the present disclosure .
  • FIG. 14 is a schematic view of a stack of via holes penetrating the interlayer insulating layer ILD and the first conductive layer LY1 of the display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of stacking a semiconductor layer LY0, a via hole penetrating the interlayer insulating layer ILD, and a third conductive layer LY3 of a display substrate according to at least one embodiment of the present disclosure.
  • 16 is a schematic diagram of a stack of a first conductive layer LY1, a via hole penetrating the interlayer insulating layer ILD, and a third conductive layer LY3 of a display substrate provided by at least one embodiment of the present disclosure.
  • 17 is a schematic view of a stack of the second conductive layer LY2 of the display substrate and the via hole penetrating the second interlayer insulating layer ILD2 provided by at least one embodiment of the present disclosure.
  • 18 is a schematic diagram of a stack of the second conductive layer LY2, the via hole penetrating the second interlayer insulating layer ILD2, and the third conductive layer LY3 of the display substrate according to at least one embodiment of the present disclosure.
  • 19 is a schematic diagram of a stack of the third conductive layer LY3, the via hole in the fourth insulating layer, and the via hole in the fifth insulating layer of the display substrate according to at least one embodiment of the present disclosure.
  • the single-layer structure and the stacked structure of the display substrate provided by at least one embodiment of the present disclosure will be described in detail below with reference to FIGS. 3 to 21 .
  • the insulating layers of the display substrate include a first insulating layer IL1 , a second insulating layer IL2 , a third insulating layer IL3 , a fourth insulating layer IL4 , a fifth insulating layer IL5 and the like.
  • the first insulating layer IL1 (as shown in FIG. 20A ) is located between the semiconductor layer LY0 shown in FIG. 4 and the first conductive layer LY1 shown in FIG. 5
  • the second insulating layer IL2 (as shown in FIG. 20A ) is located between the semiconductor layer LY0 shown in FIG. 4 and the first conductive layer LY1 shown in FIG. 5 .
  • the third insulating layer IL3 (shown in FIG. 20A ) is located in the second conductive layer shown in FIG. 6 . between the layer LY2 and the third conductive layer LY3 shown in FIG. 9 .
  • the fourth insulating layer IL4 (shown in FIG. 20B ) is located between the third conductive layer LY3 shown in FIG. 9 and the fourth conductive layer LY4 shown in FIG. 12 .
  • FIG. 20B shows the fifth insulating layer IL5.
  • the via hole shown in FIG. 7 is a via hole passing through the third insulating layer IL3.
  • FIG. 8 is a via hole penetrating one or several layers of the first insulating layer IL1 , the second insulating layer IL2 and the third insulating layer IL3 .
  • FIG. 20B shows the sixth insulating layer IL6.
  • the sixth insulating layer IL6 is located on the fourth conductive layer LY4 for protecting the fourth conductive layer LY4.
  • the first insulating layer IL1 includes a first gate insulating layer GI1
  • the second insulating layer IL2 includes a first interlayer insulating layer ILD1
  • the third insulating layer IL3 includes a second interlayer insulating layer ILD2
  • the fourth insulating layer IL4 includes a passivation
  • the fifth insulating layer IL5 includes the first planarizing layer PLN1
  • the sixth insulating layer IL6 includes the second planarizing layer PLN2.
  • the first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, the fourth insulating layer IL4, the fifth insulating layer IL5 and the sixth insulating layer IL6 are all made of insulating materials.
  • the materials of the first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3 and the fourth insulating layer IL4 may include inorganic insulating materials such as SiNx, SiOx, SiNxOy, etc., or other suitable materials;
  • the fifth insulating layer Materials of the layer IL5 and the sixth insulating layer IL6 include organic insulating materials such as organic resin, or other suitable materials, which are not limited in the embodiments of the present disclosure.
  • the thicknesses of the fifth insulating layer IL5 and the sixth insulating layer IL6 are larger, and the thickness of each of the fifth insulating layer IL5 and the sixth insulating layer IL6 is larger than that of the first insulating layer IL1, the second insulating layer IL2, the third insulating layer Thickness of each of layer IL3 and fourth insulating layer IL4.
  • the display substrate shown in FIG. 3 takes the layout design of the K-th shift register unit in the light-emitting control driving circuit array and the first power supply line, the second power supply line and the clock signal line connected thereto as an example.
  • layout implementation of other shift register units at all levels may refer to the layout shown in FIG. 3 , which will not be repeated here.
  • other suitable layouts may also be used, which are not limited by the embodiments of the present disclosure.
  • layout of the shift register units of the other light-emitting control driving circuit arrays at all levels may also refer to the layout shown in FIG. 3 , or other suitable layouts may also be used, which are not limited in the embodiments of the present disclosure.
  • each transistor may be referred to by its abbreviation to simplify the description.
  • the active layers A1-A14 of the transistors T1 to T14 of the shift register unit 100aa shown in FIG. 3 may refer to the pattern of the semiconductor layer LY0 shown in FIG. 4 .
  • the semiconductor layer LY0 may be formed by patterning a semiconductor material.
  • the semiconductor layer LY0 may include a short rod-shaped portion or a portion having a curved or bent shape, so as to be used to fabricate the active layers A1 of the above transistors T1 to T14 -A14.
  • the active layer of each transistor may include a source region, a drain region, and a channel region between the source region and the drain region.
  • the channel region has semiconducting properties; the source and drain regions flank the channel region and may be doped with impurities and thus have conductivity.
  • the source region is a part of the active layer, and the metal electrode (for example, located in the third conductive layer LY3) in contact with the source region corresponds to the source (or the first electrode) of the transistor; the drain region is A part of the active layer, the metal electrode in contact with the drain region (for example, located in the third conductive layer LY3) corresponds to the drain (or called the second electrode) of the transistor.
  • the source region is connected to its corresponding metal electrode (source) through vias penetrating the first insulating layer IL1, the second insulating layer IL2 and the third insulating layer IL3, and the drain region is connected to its corresponding metal electrode (source) through the first insulating layer IL1, the The via holes of the second insulating layer IL2 and the third insulating layer IL3 are connected to their corresponding metal electrodes (drains).
  • the transfer electrodes located in the third conductive layer are metal electrodes. At least a portion of the via electrode serves as a source or drain of the transistor.
  • the material of the semiconductor layer LY0 may include oxide semiconductor, organic semiconductor or amorphous silicon, polysilicon, etc.
  • the oxide semiconductor includes metal oxide semiconductor (eg, indium gallium zinc oxide (IGZO)), and the polysilicon includes low temperature polysilicon or high temperature polysilicon.
  • IGZO indium gallium zinc oxide
  • Polysilicon, etc. are not limited in the embodiments of the present disclosure.
  • the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities, which are not limited in the embodiments of the present disclosure.
  • first and second electrodes of each transistor may also be located in other conductive layers, and connected to their corresponding active layers through via holes in the insulating layer between them and the semiconductor layer , which is not limited by the embodiments of the present disclosure.
  • FIG. 5 shows the first conductive layer LY1 of the display substrate.
  • the first conductive layer LY1 is disposed on the first insulating layer IL1 so as to be insulated from the semiconductor layer LY0.
  • the first conductive layer LY1 may include the second plates C1b, C2b, C3b, C4b of the first capacitor C1 to the fourth capacitor C4, the gates G1-G14 of the transistor T1 to the transistor T14, and various connecting lines (eg, , connecting traces L1-L5) and wires (eg, wires M1, M2, and M3) for connecting with signal wires or transfer electrodes in the third conductive layer LY3.
  • Conductor M1, Conductor M2 and Conductor M3 are all independent graphics. As shown in FIG.
  • the gates G1-G14 of the transistors T1 to T14 are the parts enclosed by a circle or an oval dotted circle, that is, the semiconductor layer structure of each transistor and the electrodes or traces in the first conductive layer LY1 overlapping parts.
  • the second electrode plates C1b, C2b, C3b, and C4b of the first capacitor C1 to the fourth capacitor C4 respectively include the first portions C1b1 and C2b1 of the second electrode plate C1b of the first capacitor C1 to the fourth capacitor C4. , C3b1, C4b1.
  • the gate G5 of the transistor T5, the connection line L1, the first part C1b1 of the second plate C1b of the first capacitor C1, the connection line L2, and the gate G4 of the transistor T4 are connected and integrated form.
  • the first portion C4b1 of the second plate C4b of the fourth capacitor C4 , the connecting line L3 , and the gate G11 of the transistor T11 are connected and formed integrally.
  • the connection line L4 , the gate G12 of the transistor T12 , and the first portion C3b1 of the second plate C3b of the third capacitor C3 are connected and formed integrally.
  • the connection line L5, the gate G2 of the transistor T2, and the gate G8 of the transistor T8 are integrally formed.
  • FIG. 6 shows the second conductive layer LY2 of the display substrate.
  • the second conductive layer LY2 includes the first plates C1a, C2a, C3a, C4a of the first capacitor C1 to the fourth capacitor C4 and the output terminal EOUT1.
  • the first plates C1a, C2a, C3a, and C4a of the first capacitor C1 to the fourth capacitor C4 include the first part C1a1 of the first plate C1a, the first part C2a1 of the first plate C2a, and the first part of the first plate C3a C3a1, the first portion C4a1 of the first plate C4a.
  • the output terminal EOUT1 located in the second conductive layer LY2 can be used to provide output signals to the pixel units in the display area; and in some other embodiments of the present disclosure, the shift register unit
  • the output signal of the output terminal EOUT1 of 100aa can also be provided by electrodes located in other layers, that is, the output terminal EOUT1 can also be arranged in other layers different from the second conductive layer LY2, for example, can be arranged in the first conductive layer LY1 , which is not limited by the embodiments of the present disclosure.
  • FIG. 7 shows the distribution of via holes in the third insulating layer IL3 of the display substrate.
  • the via hole shown in FIG. 7 is a via hole passing through the third insulating layer IL3.
  • FIG. 8 shows the distribution of via holes in the second insulating layer IL2 of the display substrate.
  • the via holes shown in FIG. 8 are via holes penetrating the third insulating layer IL3 , the second insulating layer IL2 , the first insulating layer IL1 , and the via holes penetrating the third insulating layer IL3 and the second insulating layer IL2 .
  • FIG. 9 shows the third conductive layer LY3 of the display substrate, and the third conductive layer LY3 includes a plurality of signal lines (for example, a first clock signal line ECB, a second clock signal line ECB2, a third clock signal line ECK, a third clock signal line Four clock signal lines ECK2), a first power line VGL, a second power line VGH and so on.
  • a first clock signal line ECB for example, a first clock signal line ECB, a second clock signal line ECB2, a third clock signal line ECK, a third clock signal line Four clock signal lines ECK2
  • FIG. 9 shows the first part ECBa of the first clock signal line ECB, the first part ECB2a of the second clock signal line ECB2, the first part ECKa of the third clock signal line ECK, the first part ECK2a of the fourth clock signal line ECK2, the A first portion VGLa of a power supply line VGL, a first portion VGHa of a second power supply line VGH, a second portion C1b2 of the second plate C1b of the first capacitor C1, and a second portion C2b2 of the second plate C2b of the second capacitor C2 , the second portion C3b2 of the second plate C3b of the third capacitor C3, and the second portion C4b2 of the second plate C4b of the fourth capacitor C4.
  • the third conductive layer LY3 also includes transfer electrodes ET1-ET14, transfer electrodes ET5a, transfer electrodes ETI, transfer electrodes ETa, transfer electrodes ETb that connect the respective transistors, capacitors and signal lines. , transfer electrode ETc and transfer electrode ETd, etc.
  • the transfer electrode ETI may be connected to the input terminal EI located in the fourth conductive layer LY4 through a via structure.
  • the input terminal EI may also be referred to as an input line.
  • the input terminal EI of the shift register unit 100aa may also be located in other layers, for example, may be located in the third conductive layer LY3 to be directly connected to the transition electrode ETI.
  • the transfer electrode ETI may be integrally formed with the input end EI, for example, the transfer electrode ETI includes the input end EI, which is not limited by the embodiments of the present disclosure.
  • FIG. 10 shows the distribution of via holes in the fourth insulating layer IL4 (passivation layer PVX) of the display substrate.
  • FIG. 11 shows the distribution of via holes in the fifth insulating layer IL5 (the first planarization layer PLN1 ) of the display substrate.
  • the area of the via hole in the fifth insulating layer IL5 (first planarization layer PLN1 ) is larger than the area of the via hole in the fourth insulating layer IL4 (passivation layer PVX) at the corresponding position , so as to facilitate the connection between the elements in the third conductive layer LY3 and the elements in the fourth conductive layer LY4, and reduce the distance between the two opposite pole plates of the capacitor, so as to increase the capacitance.
  • the area of the via hole H0 penetrating the fifth insulating layer IL5 is larger than the area of the via hole H22 penetrating the fourth insulating layer IL4, so as to reduce the distance between the first electrode plate Ca and the second electrode plate Cb, Increase the capacity. Further, in the case where the capacitors are connected in parallel, the distance between the second portion Ca2 of the first electrode plate Ca and the second portion Cb2 of the second electrode plate Cb can be reduced to increase the capacitance.
  • FIG. 12 shows the fourth conductive layer LY4 of the display substrate.
  • the fourth conductive layer LY4 includes the second portions C1a2, C2a2, C3a2 and C4a2 of the first plates of the first capacitor C1 to the fourth capacitor C4, the second portion ECBb of the first clock signal line ECB, and the second clock signal line ECB2
  • the output terminal EOUT2 can be used to connect to the input terminal EI of the shift register unit of the next stage, so as to provide an input signal for the input terminal EI of the shift register unit of the next stage. It should be noted that the output end EOUT2 may also be located in other conductive layers.
  • the input end EI is used to receive the output signal of the output end of the shift register unit of the previous stage as the input signal of the input end of the shift register unit of the present stage.
  • the transfer electrode ET5 is connected to the second pole of the transistor T5 and is integrally formed, and the second pole of the transistor T5 is connected to the active layer A5 of the transistor T5 through a via hole. .
  • at least a part of the transition electrode ET5 serves as the second pole of the transistor T5.
  • the transfer electrode ET5 is connected to the active layer A5 of the transistor T5 through a via hole.
  • the second portion C1b2 of the second electrode C1b of the first capacitor C1 is connected to the active layer A5 of the transistor T5 through the first via hole H1, and the second portion C1b2 of the second electrode C1b of the first capacitor C1 passes through the second via hole H2 Connected to the gate G5 of the transistor T5.
  • the second portion C1b2 of the second pole C1b of the first capacitor C1 may also be referred to as a conductive portion CP.
  • the first electrode of the first transistor is connected to the active layer of the first transistor T5 through the first via hole H1.
  • the second pole of the transistor T11 is connected to the transfer electrode ET11 and is integrally formed, and the second pole of the transistor T11 is connected to the active layer A11 of the transistor T11 through a via hole .
  • the transfer electrode ET11 is connected to the active layer A11 of the transistor T11 through a via hole. In other words, at least a part of the transition electrode ET11 serves as the second electrode of the transistor T11.
  • the transfer electrode ET11, the transfer electrode ET5, and the second portion C1b2 of the second electrode C1b of the first capacitor C1 are connected and formed integrally.
  • the input terminal EI is connected to the transfer electrode ETI through a via hole, and the transfer electrode ETI is connected to the first pole of the transistor T12 and is integrally formed. At least a portion of the contact electrode ETI serves as the first electrode of the transistor T12.
  • the first electrode of the transistor T12 is connected to the active layer A12 through a via hole.
  • the transfer electrode ET12 is connected to and integrally formed with the second pole of the transistor T12 and is connected to and integrally formed with the first pole of the transistor T1, in other words, at least a part of the transfer electrode ET12 serves as the second pole of the transistor T12 and the transfer electrode At least a portion of ET12 serves as the first pole of transistor T1.
  • the first electrode of the transistor T1 is connected to the active layer A1 of the transistor T1 through a via hole, and the transfer electrode ET1 is connected to the second electrode of the transistor T1 and is integrally formed and connected to the second electrode of the transistor T13 and is integrally formed, in other words , at least a part of the transition electrode ET1 acts as the second pole of the transistor T1 and at least a part of the transition electrode ET1 acts as the second pole of the transistor T13.
  • the transfer electrode ET1 is connected to the connection line L5 through a via hole.
  • one end of the wire M1 is connected to the first part ECBa of the first clock signal wire ECB through a via hole, and the other end of the wire M1 is connected to the transfer electrode ET6 through the via hole, and the transfer The other end of the electrode ET6 is connected to the active layer A4 of the transistor T4 through a via hole.
  • the transfer electrode ET6 is connected to the first pole of the transistor T6 and formed integrally, and is connected to the first pole of the transistor T4 and formed integrally. In other words, at least a part of the transfer electrode ET6 serves as the first pole of the transistor T6 and at least a part of the transfer electrode ET6 serves as the first pole of the transistor T4.
  • the transfer electrode ET4 is connected to the active layer A4 of the transistor T4 through a via hole, and the transfer electrode ET4 is connected to the second pole of the transistor T4 and is integrally formed. In other words, at least a part of the transition electrode ET4 serves as the second pole of the transistor T4.
  • the transfer electrode ETd is connected with the active layer A6 of the transistor T6 and the active layer A7 of the transistor T7 through the via hole, and the transfer electrode ETd is connected with the second part C4b2 of the second plate C4b of the fourth capacitor C4 and is integrally formed,
  • the second portion C4b2 of the second plate C4b of the fourth capacitor C4 is connected to the first electrode of the transistor T6 and is integrally formed, and is connected to the first electrode of the transistor T7 and is integrally formed.
  • the second portion C4b2 of the second plate C4b of the fourth capacitor C4 acts as the first pole of the transistor T6 and at least a portion of the second portion C4b2 of the second plate C4b of the fourth capacitor C4 acts as a transistor The first pole of T7.
  • the second portion C1b2 of the second electrode plate C1b of the first electrode C1 is connected to the transition electrode ET4 through a via hole.
  • the transition electrode ETb is connected to the second power line VGH and is integrally formed.
  • One end of the wire M2 is connected to the transfer electrode ETb through the via hole, and the other end of the wire M2 is connected to the transfer electrode ET8 through the via hole.
  • the transfer electrode ET8 is connected to the first pole of the transistor T8 and formed integrally, and is connected to the first pole of the transistor T11 and formed integrally. In other words, at least a part of the transfer electrode ET8 serves as the first pole of the transistor T8 and at least a part of the transfer electrode ET8 serves as the first pole of the transistor T11.
  • one end of the wire M3 is connected to the first power supply line VGL; the other end of the wire M3 is connected to the transfer electrode ET3, and then to the gate of the transistor T14 G14 is connected so that the gate G14 of the transistor T14 is connected to the first power supply line VGL.
  • the transfer electrode ET3 is connected to the second electrode of the transistor T3 and formed integrally. In other words, at least a part of the transition electrode ET3 serves as the second pole of the transistor T3.
  • one end of the transfer electrode ET7 is connected to the gate G9 of the transistor T9 through a via hole.
  • the other end of the transfer electrode ET7 is One end is connected to the active layer A7 of the transistor T7, the other end of the transfer electrode ET7 is connected to the active layer A8 of the transistor T8 through a via hole, and the transfer electrode ET7 is connected to the second pole of the transistor T7 and is integrally formed with the transistor T8.
  • the second poles are connected and integrally formed.
  • at least a part of the transfer electrode ET7 serves as the second pole of the transistor T7 and at least a part of the transfer electrode ET7 serves as the second pole of the transistor T8.
  • the transfer electrode ET13 is connected to the gate G4 of the transistor T4 through a via hole, and the transfer electrode ET13 is connected to the first pole of the transistor T13 and is integrally formed. .
  • at least a part of the transition electrode ET13 serves as the first electrode of the transistor T13.
  • the first end of the transfer electrode ET13 is connected to the gate G4 of the transistor T4 through a via hole.
  • the gate G12 of the transistor T12 is connected to the first part ECB2a of the second clock signal line ECB2 through a via hole, and the gate G1 of the transistor T1 passes through the via hole It is connected to the first part ECKa of the third clock signal line ECK, the connecting line M1 is connected to the first part ECBa of the first clock signal line ECB through the via hole, and the gate G13 of the transistor T13 is connected to the first power supply line VGL through the via hole.
  • a part of VGLa is connected.
  • the transfer electrode ETc is connected to the first portion VGLa of the first power supply line VGL and is integrally formed.
  • the transfer electrode ETc is connected to the first electrode of the transistor T10 and is integrally formed.
  • the transfer electrode ETc serves as the first electrode of the transistor T10.
  • the transfer electrode ET10 is connected to the second pole of the transistor T10 and formed integrally, and is connected to the first pole of the transistor T9 and formed integrally.
  • at least a part of the transfer electrode ET10 serves as the second pole of the transistor T10 and at least a part of the transfer electrode ET10 serves as the first pole of the transistor T9.
  • the transfer electrode ET9 is connected to the second portion C3b2 of the second electrode C3b of the third capacitor C3 and formed integrally.
  • the transfer electrode ET9 is connected to the second pole of the transistor T9 and formed integrally.
  • at least a part of the transition electrode ET9 serves as the second pole of the transistor T9.
  • the second part C3b2 (transfer electrode ET9 ) is connected to the first part C3b1 of the second pole C3b of the third capacitor C3 through a via hole, and is further connected to the second clock signal line ECB2.
  • one end of the transfer electrode ET14 is connected to the active layer A3 of the transistor T3 through a via hole, and the other end of the transfer electrode ET14 is connected to the transistor through a via hole.
  • the active layer A2 of T2 and the active layer A14 of the transistor T14 are connected.
  • the transfer electrode ET14 is connected to the second electrode of the transistor T2 and is integrally formed, and is connected to the first electrode of the transistor T14 and is integrally formed. In other words, at least a part of the transfer electrode ET14 serves as the second pole of the transistor T2 and at least a part of the transfer electrode ET14 serves as the first pole of the transistor T14.
  • one end of the transfer electrode ET2 is connected to the active layer A2 of the transistor T2 through a via hole, and the other end of the transfer electrode ET2 is connected to the transistor through a via hole.
  • the gate G3 of T3 is connected to the first part ECKa of the third clock signal line ECK through the gate G3.
  • the transfer electrode ET2 is connected to the first electrode of the transistor T2 and is integrally formed. In other words, at least a part of the transition electrode ET2 serves as the first pole of the transistor T2.
  • one end of the transfer electrode ET3 is connected to the gate G14 of the transistor T14, and the other end of the transfer electrode ET3 is connected to the gate G1 of the transistor T1, And further connected to the first portion VGLa of the first power line VGL.
  • the transfer electrode ETa is connected to the gate G6 of the transistor T6 through the via hole, and the transfer electrode ETa is connected to the active layer A14 of the transistor T14 through the via hole connected, and the transfer electrode ETa is connected to the second electrode of the transistor T14 and formed integrally. In other words, at least a part of the transit electrode ETa serves as the second electrode of the transistor T14.
  • the second portion C2b2 of the second plate C2b of the second capacitor C2 is connected to the gate G10 of the transistor T10 through a via hole.
  • the first portion C1a1 of the first plate C1a of the first capacitor C1 is connected to the transfer electrode ET4 through a via hole.
  • the first portion C2a1 of the first plate C2a of the second capacitor C2 is connected to the transfer electrode ETc through a via hole.
  • the first portion C3a1 of the first plate C3a of the third capacitor C3 is connected to the transfer electrode ET7 through a via hole.
  • the first portion C4a1 of the first plate C4a of the fourth capacitor C4 is connected to the transfer electrode ETa through a via hole.
  • the transfer electrode ET1 or the connection trace L5 can be used as the first isolation node P31 , the transfer electrode ET13 or the gate G4 of the transistor T4 or
  • the second plate of the first capacitor C1 can be used as the first input node P11
  • the transfer electrode ET14 can be used as the second isolation node P32
  • the transfer electrode ETa can be used as the third input node P13
  • the transfer electrode ET7 can be used as the second node P2
  • the transfer electrode ET5 (transfer electrode ET11), the second plate C2b of the second capacitor C2 or the gate G10 of the transistor T10 can be used as the first node P1
  • the transfer electrode ETd can be used as the second input node P12.
  • the output terminal EOUT1 may have two end portions that respectively provide output signals to the pixel units 103 in two adjacent rows of the display area 102 , for example, the two end portions are arranged side by side in the first direction Y.
  • the output terminal EOUT2 is used to provide an output signal to the next-stage shift register unit as an input signal of the next-stage shift register unit.
  • the output terminal EOUT2 can be connected to the input terminal EI of the next-stage shift register unit.
  • the charge pump circuit 11 includes a first capacitor C1 , a first transistor T5 and a second capacitor C2 .
  • the first electrode plate of the first capacitor C1 is connected to the first clock signal line ECB, and the second electrode plate of the first capacitor C1 is connected to the first electrode of the first transistor T5.
  • the first plate of the second capacitor C2 is connected to the first power supply line VGL, the second plate of the second capacitor C2 is connected to the second electrode of the first transistor T5, and the gate of the first transistor T5 is connected to the second electrode of the first transistor T5.
  • the first pole or the second pole is connected.
  • the orthographic projection of the first capacitor C1 on the base substrate 10 is adjacent to the orthographic projection of the first transistor T5 on the base substrate 10
  • the orthographic projection of the second capacitor C2 on the base substrate 10 It is adjacent to the orthographic projection of the first transistor T5 on the base substrate 10 .
  • the first capacitor C1 and the first transistor T5 are adjacent to each other
  • the second capacitor C2 and the first transistor T5 are disposed adjacent to each other, which facilitates the layout of the shift register unit and reduces the frame of the display substrate.
  • the orthographic projection of the first capacitor C1 on the base substrate 10 partially overlaps with the orthographic projection of the first transistor T5 on the base substrate 10 , and the orthographic projection of the second capacitor C2 on the base substrate 10 overlaps.
  • the projection partially overlaps the orthographic projection of the first transistor T5 on the base substrate 10 .
  • the adjacent arrangement of elements means that no other elements are arranged between the elements.
  • the adjacent arrangement of elements means that the elements are directly connected, and not indirectly connected through other elements.
  • Elements of embodiments of the present disclosure include capacitors and transistors.
  • the element A and the element B are adjacent means that there are no other elements A and other elements B between the two elements.
  • adjacent capacitors and transistors means that there are no other capacitors and no other transistors between the capacitor and the transistor.
  • the fact that element A and element B are adjacent means that the two elements do not have other capacitances or other transistors between them.
  • element A includes a capacitor or transistor
  • element B includes a capacitor or transistor.
  • the first capacitor C1 and the second capacitor C2 are arranged around the first transistor T5. This arrangement can improve the density of typesetting, which is beneficial to narrow borders.
  • both the first capacitor C1 and the second capacitor C2 are located to the left of the first transistor T5.
  • both the first capacitor C1 and the second capacitor C2 are located to the right of the first transistor T5.
  • one of the first capacitor C1 and the second capacitor C2 is located to the left of the first transistor T5, and the other of the first capacitor C1 and the second capacitor C2 is located to the right of the first transistor T5.
  • one of the first capacitor C1 and the second capacitor C2 is located on the upper side of the first transistor T5, and the other one of the first capacitor C1 and the second capacitor C2 is located on the lower side of the first transistor T5.
  • the orthographic projection of the second plate C1b of the first capacitor C1 on the base substrate 10 and the first transistor T5 partially overlaps, and the orthographic projection of the second electrode plate C2b of the second capacitor C2 on the base substrate 10 and the second electrode of the first transistor T5 on the base substrate
  • the orthographic projections on 10 partially overlap.
  • the second portion C1b2 of the second plate C1b of the first capacitor C1 is connected to the active layer A5 of the first transistor T5, and the second portion C1b2 of the second plate C2b of the second capacitor C2 is connected to the active layer A5 of the first transistor T5.
  • the two parts C2b2 are connected to the active layer A5 of the first transistor T5.
  • the second portion C1b2 of the second plate C1b of the first capacitor C1 also serves as the first electrode of the first transistor T5, and the second portion C2b2 of the second plate C2b of the second capacitor C2 also serves as the second electrode of the first transistor T5. pole.
  • the second portion C1b2 of the second electrode plate C1b of the first capacitor C1 is connected to the first electrode of the first transistor T5 and formed integrally, and the second portion C2b2 of the second electrode plate C2b of the second capacitor C2 is connected to the first electrode of the first transistor T5.
  • the second electrodes of a transistor T5 are connected and integrally formed.
  • the capacitance value of the first capacitor C1 is greater than or equal to the capacitance value of the second capacitor C2.
  • the capacitance value of the first capacitor C1 is less than or equal to ten times the capacitance value of the second capacitor C2.
  • the capacitance value of the first capacitor C1 is four to six times that of the second capacitor C2.
  • the capacitance value of the second capacitor C2 is in the range of 0.01pF-2pF, and the second capacitor C2 within this value range is conducive to the setting of the capacitance values of the first capacitor C1 and the second capacitor C2, and is conducive to the realization of the first capacitor C1 and the second capacitor C2.
  • the first clock signal line ECB extends along the first direction Y on the base substrate 10 , and the first capacitor C1 , the first transistor T5 and the second capacitor C2 are arranged in sequence along the second direction X cloth.
  • the first direction Y intersects the second direction X.
  • the first direction Y and the second direction X are directions parallel to the main surface of the base substrate 10 , and the main surface of the base substrate 10 is the surface on which various film layers are formed.
  • the gate of the first transistor T5 is connected to the first electrode of the first transistor T5 through the conductive portion CP to form a diode structure.
  • the conductive portion CP is connected to the active layer A5 of the first transistor T5 through the first via hole H1 .
  • the orthographic projection of the channel CNL of the first transistor T5 on the base substrate 10 does not overlap with the orthographic projection of the first via hole H1 on the base substrate 10 to avoid the formation of the via hole during the process of forming the via hole.
  • Destructing the channel of the first transistor T5 can effectively realize the unidirectional current flow function of the diode-connected first transistor T5, and effectively remove the noise interference in the holding stage.
  • the conductive portion CP is the second portion C1b2 of the second electrode plate C1b of the first capacitor C1 .
  • the conductive portion CP is connected to the gate G5 of the first transistor T5 through the second via hole H2.
  • the orthographic projection of the channel CNL of the first transistor T5 on the base substrate 10 is the same as the second via hole H2.
  • the orthographic projections of the hole H2 on the base substrate 10 do not overlap.
  • the height h2 of the second via hole H2 in the direction perpendicular to the base substrate 10 is smaller than the height h1 of the first via hole H1 in the direction perpendicular to the base substrate 10 .
  • the first via hole H1 penetrates the third insulating layer IL3 , the second insulating layer IL2 , and the first insulating layer IL1
  • the second via hole H2 penetrates the third insulating layer IL3 and the second insulating layer IL2 .
  • the orthographic projection of the channel CNL of the first transistor T5 on the base substrate 10 partially overlaps the orthographic projection of the gate G5 of the first transistor T5 on the base substrate 10 .
  • the portion of the active layer A5 covered by the gate G5 is the channel CNL.
  • the channel CNL of the first transistor T5 includes a first channel CNL1 and a second channel CNL2, and
  • FIG. 20A shows the first gate G51 overlapping the first channel CNL1 of the first transistor T5 and the first gate G51 overlapping with the first channel CNL1 of the first transistor T5.
  • the second gate G52 of the second channel CNL2 of T5 overlaps.
  • the first gate G51 and the second gate G52 are both connected to the connecting wire L1 and formed integrally.
  • the orthographic projection of the second transistor T4 on the base substrate 10 partially overlaps the orthographic projection of the first capacitor C1 on the base substrate 10 .
  • the orthographic projection of the second transistor T4 on the base substrate 10 is adjacent to the orthographic projection of the first capacitor C1 on the base substrate 10 .
  • the second transistor T4 is disposed adjacent to the first capacitor C1, so as to reduce the occupied area of the charge pump circuit and reduce the frame of the display substrate.
  • the second transistor T4, the first capacitor C1, the first transistor T5, and the second capacitor C2 are arranged in sequence in the second direction X, so as to facilitate the connection between the charge pump circuit and other structures
  • the arrangement of the structure and other structures is beneficial to improve the layout density and reduce the frame of the display substrate.
  • the second clock signal line ECB2 extends along the first direction Y on the base substrate 10
  • the third clock signal line ECK extends along the first direction Y on the base substrate 10
  • the fourth clock signal line ECK extends along the first direction Y on the base substrate 10 .
  • the line ECK2 extends in the first direction Y on the base substrate 10
  • the first power supply line VGL extends in the first direction Y on the base substrate 10
  • the second power supply line VGH extends in the first direction on the base substrate 10 Y extension.
  • the via holes H01 , H02 , H03 and H04 in the fifth insulating layer IL5 are respectively connected with the first electrode plates of the first capacitor C1 to the fourth capacitor C4 .
  • the shapes and areas of the second portions C1a2, C2a2, C3a2 and C4a2 are approximately the same, so that the orthographic projections of the second portions of the first electrode plates of the first capacitors C1 to the fourth capacitors C4 on the substrate completely fall into the
  • the via hole in the fifth insulating layer IL5 is in the orthographic projection on the base substrate, so as to reduce the distance between the plates of the capacitor, increase the capacitance, and facilitate the first capacitor C1 to the fourth capacitor C4.
  • the connection of the second part of the plate to the transition electrode ET (refer to FIG. 20B ).
  • the dielectric layer between the second part of the first plate of the first capacitor C1 to the fourth capacitor C4 and the second part of the second plate of the first capacitor C1 to the fourth capacitor C4 does not include the fifth insulation Layer IL5 (refer to FIG. 20B ).
  • the signal line may be in the form of two parts located in different layers in parallel to reduce the resistance of the signal line, the first part ECBa and the second part ECBb connected in parallel to form the first clock signal line ECB, the first part ECB2a and the second part ECB2b are connected in parallel to form the second clock signal line ECB2, the first part ECKa and the second part ECKb are connected in parallel to form the third clock signal line ECK, the first part ECK2a and the The second part ECK2b is connected in parallel to form the fourth clock signal line ECK2.
  • the first part VGLa and the second part VGLb are connected in parallel to form the first power supply line VGL, and the first part VGHa and the second part VGHb are connected in parallel to form the second power supply line VGH.
  • the two parts of the signal line can be connected by arranging via holes at corresponding positions through the insulating layer between the two parts.
  • a plurality of signal lines, a first power supply line VGL, a second power supply line VGH, and at least one via shown in FIG. 8 are connected to the transistors and capacitors in the remaining layers that need to be connected to it.
  • the transistors and capacitors may also be connected through at least one via hole, or bridged through a transfer electrode, which will not be repeated here.
  • the material of the first conductive layer LY1, the second conductive layer LY2, the third conductive layer LY3, and the fourth conductive layer LY4 includes metal.
  • the material of the third conductive layer LY3 may include titanium, titanium alloy, aluminum, aluminum alloy, copper, copper alloy, or any other suitable composite material, which is not limited in the embodiments of the present disclosure.
  • the material of the fourth conductive layer LY4 may have the same selection range as the material of the third conductive layer LY3, but is not limited thereto.
  • the material of the first conductive layer LY1 includes molybdenum, nickel, molybdenum alloy, nickel alloy, and the like.
  • the selection range of the material of the second conductive layer LY2 and the material of the first conductive layer LY1 is the same, but not limited thereto.
  • the active layer A9 of the transistor T9 and the The active layer A10 of the transistor T10 has an integrated structure
  • the active layer A2 of the transistor T2 and the active layer A14 of the transistor T14 have an integrated structure
  • the active layer A6 of the transistor T6 and the active layer A7 of the transistor T7 have an integrated structure.
  • the active layers of the transistors can also be arranged separately.
  • the gate G12 of the transistor T12 is connected to the first portion C3b1 of the second plate C3b of the third capacitor C3 through a connection line L4 .
  • the gate G12 of the transistor T12, the first portion C3b1 of the second plate C3b of the third capacitor C3, and the connecting line L4 are integrated into a structure.
  • the gate G11 of the transistor T11 and the first part C4b1 of the second plate C4b of the fourth capacitor C4 are connected through the connection line L3, for example, the gate G11 of the transistor T11, the connection line L3 and the second pole of the fourth capacitor C4
  • the first portion C4b1 of the plate C4b is of one-piece structure.
  • the fourth control transistor T2 includes a first gate G21 and a second gate G22, both of which are connected to the connection
  • the wiring L5 is located on one side of the gate G2 of the fourth control transistor T2 and extends along the second direction X, and the connection wiring L5 is connected to the gate G8 of the seventh control transistor T8.
  • the gate G2 of the fourth control transistor T2 forms a "U"-shaped structure, thereby enhancing the stability of the fourth control transistor T2 and improving the performance of the fourth control transistor T2. For example, as shown in FIG.
  • the active layer A8 of the transistor T8 has a “U”-shaped structure, so that the transistor T8 has a double gate structure.
  • the active layer A11 of the transistor T11 has a “U”-shaped structure, so that the transistor T11 has a double gate structure.
  • the active layer of the fourth control transistor T2 has a "U"-shaped structure
  • the gate of the fourth control transistor T2 has a "one"-shaped structure overlapping with the "U"-shaped active layer, so that The double gate structure is formed, as long as the arrangement of other structures is not affected and the width of the shift register unit is increased too much, which is not limited by the embodiments of the present disclosure.
  • a single gate may also overlap with the active layer of the fourth control transistor T2, which is not limited by the embodiment of the present disclosure.
  • the wire M1 extends in the second direction X
  • the wire M2 extends in the first direction Y
  • the wire M3 extends in the second direction X.
  • the gate G11 of the transistor T11 is connected to the first portion C4b1 of the second plate C4b of the fourth capacitor C4 through the connection line L3, and the gate of the transistor T11 G11, the connecting line L3 and the first portion C4b1 of the second plate C4b of the fourth capacitor C4 are integrated into one structure.
  • the gate G4 of the transistor T4 is connected to the first portion C1b1 of the first plate C1b of the first capacitor through the connection line L2, and the gate G4 of the transistor T4 .
  • the connecting line L2 and the first portion C1b1 of the first plate C1b of the first capacitor are integrated into one structure.
  • the gate G4 of the transistor T4, the gate of the transistor T5, the connection line L2, the connection line L1 and the first portion C1b1 of the first plate C1b of the first capacitor are integrated into one structure.
  • the gate of the second output transistor T9 is a comb-like structure, so as to improve the stability of the second output transistor T9 .
  • the extension direction of the active layer A4 of the second transistor T4 intersects with the extension direction of the active layer A5 of the first transistor T5, so as to facilitate the extension of the first transistor T5 and the second transistor T4. Placement is conducive to reducing the occupied area of the charge pump circuit, improving the layout density, and reducing the size of the shift register unit to reduce the frame.
  • the active layer A4 of the second transistor T4 extends along the first direction Y
  • the active layer A5 of the first transistor T5 extends along the second direction X.
  • the active layer A1 of the second control transistor T1 extends along the first direction Y
  • the active layer A12 of the first control transistor T12 extends along the first direction Y.
  • the active layer A13 of the first isolation transistor T13 extends along the first direction Y
  • the active layer A1 is located between the active layer A12 and the active layer A13.
  • the active layer A12 , the active layer A1 and the active layer A13 are sequentially arranged along the first direction Y.
  • the active layer A12, the active layer A1, and the active layer A13 are located on the same straight line.
  • the active layer A2 the active layer A14, the active layer A6 and the active layer A7 all extend along the second direction X, and the active layer A3 and the active layer A7 extend along the second direction X.
  • the layers A4 all extend along the first direction Y.
  • the via hole H041 , the via hole H031 , the via hole H021 and the via hole H011 are respectively the via holes penetrating the fourth insulating layer IL4 (passivation layer PVX), the via holes H04 , via hole H03 , via hole H02 and via hole H01 are via holes penetrating through the fifth insulating layer IL5 (the first planarization layer PLN1 ), respectively.
  • the fourth insulating layer IL4 passivation layer PVX
  • the via holes H04 , via hole H03 , via hole H02 and via hole H01 are via holes penetrating through the fifth insulating layer IL5 (the first planarization layer PLN1 ), respectively.
  • the fifth insulating layer IL5 the first planarization layer PLN1
  • the via hole H041 and the via hole H04 overlap and pass through
  • the via hole H031 and the via hole H03 overlap and pass through
  • the via hole H021 and the via hole H02 overlap and pass through
  • the via hole H011 and the via hole H01 overlap and pass through, so as to reduce the distance between the plates of the capacitor, Increase the capacitance and facilitate the setting of the capacitor's plate.
  • the first capacitor C1 , the second capacitor C2 , the third capacitor C3 , and the fourth capacitor C4 adopt the same structure, and all adopt a structure in which three capacitors are connected in parallel.
  • the capacitor C includes a first electrode plate Ca and a second electrode plate Cb
  • the first electrode plate Ca includes a first portion Ca1 and a second portion Ca2
  • the second electrode plate Cb includes a first portion Cb1 and a second portion Cb2
  • the first part Ca1 and the second part Ca2 are connected through the transition electrode ET
  • the first part Cb1 and the second part Cb2 are connected.
  • the third direction Z is a direction perpendicular to the base substrate 10 .
  • the third direction Z is perpendicular to the first direction Y and is perpendicular to the second direction X.
  • the first direction Y and the second direction X are directions parallel to the main surface of the base substrate, and the third direction Z is a direction perpendicular to the main surface of the base substrate.
  • the main surface of the base substrate can be made of various surface of the element.
  • the first portion Cb1 and the first portion Ca1 face each other to form a capacitor
  • the first portion Ca1 and the second portion Cb2 face each other to form a capacitor
  • the second portion Cb2 and the second portion Ca2 face each other to form a capacitor.
  • This arrangement is beneficial to increase the capacitance, reduce the area occupied by the capacitance, and is beneficial to realize the narrow frame of the display substrate.
  • FIG. 20B only schematically shows the structure of three capacitors connected in parallel, and the insulating layer disposed between the electrode plates of the capacitors may include at least one insulating layer.
  • the second portion Ca2 is connected to the transfer electrode ET through the via hole H22 passing through the fourth insulating layer IL4, and the transfer electrode ET is connected to the first portion Ca1 through the via hole H21 passing through the third insulating layer IL3.
  • the second portion Cb2 is connected to the first portion Cb1 through the via hole H23 penetrating the third insulating layer IL3 and the second insulating layer IL2.
  • the first electrode plate Ca shown in FIG. 20B is the first electrode plate C1a
  • the first portion Ca1 shown in FIG. 20B is the first portion C1a1.
  • the second portion Ca2 shown in Fig. 20B is the second portion C1a2
  • the second electrode plate Cb shown in Fig. 20B is the second electrode plate C1b
  • the first portion Cb1 shown in Fig. 20B is the is the first part C1b1, the second part Cb2 shown in FIG. 20B is the second part C1b2
  • the transfer electrode ET shown in FIG. 20B is the transfer electrode ET4, which can also be called the transfer part or the first transfer department.
  • the first electrode plate Ca shown in FIG. 20B is the first electrode plate C2a
  • the first portion Ca1 shown in FIG. 20B is the first portion C2a1
  • FIG. 20B The second portion Ca2 shown is the second portion C2a2. 12 and 20B
  • the second polar plate Cb shown in FIG. 20B is the second polar plate C2b
  • the first part Cb1 shown in FIG. 20B is the first part C2b1
  • the second part Cb2 shown in FIG. 20B is the In the second part C2b2
  • the transfer electrode ET shown in FIG. 20B is the transfer electrode ETc, and may also be referred to as a transfer portion or a second transfer portion.
  • the first plate Ca shown in FIG. 20B is the first plate C3a
  • the first portion Ca1 shown in FIG. 20B is the first portion C3a1
  • FIG. 20B The second portion Ca2 shown is the second portion C3a2. 12 and 20B
  • the second pole plate Cb shown in FIG. 20B is the second pole plate C3b
  • the first part Cb1 shown in FIG. 20B is the first part C3b1
  • the second part Cb2 shown in FIG. 20B is the In the second part C3b2
  • the transfer electrode ET shown in FIG. 20B is the transfer electrode ET7, and may also be referred to as a transfer portion or a third transfer portion.
  • the first electrode plate Ca shown in FIG. 20B is the first electrode plate C4a
  • the first portion Ca1 shown in FIG. 20B is the first portion C4a1
  • FIG. 20B The second portion Ca2 shown is the second portion C4a2. 12 and 20B
  • the second pole plate Cb shown in FIG. 20B is the second pole plate C4b
  • the first part Cb1 shown in FIG. 20B is the first part C4b1
  • the second part Cb2 shown in FIG. 20B is the In the second portion C4b2
  • the transfer electrode ET shown in FIG. 20B is the transfer electrode ETa, and may also be referred to as a transfer portion or a fourth transfer portion.
  • At least one of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 is a structure in which three capacitors are connected in parallel.
  • the first part, the second part of the second plate, the first part of the first plate, and the second part of the first plate, the first part of the second plate and the second part of the second plate pass through the third pass
  • the holes (via holes H23) are connected, the first part of the first electrode plate and the second part of the first electrode plate are connected through the transfer electrode ET, and the third via hole (via hole H23) and the transfer electrode ET are respectively located in three capacitors.
  • the first part of the second pole plate, the first part of the first pole plate, the second part of the second pole plate, and the second part of the first pole plate are arranged successively to form three capacitors
  • the transfer electrode ET and the second part of the second electrode plate are located on the same layer and insulated from each other.
  • the first portion of the second electrode plate, the first portion of the first electrode plate, the second portion of the second electrode plate, and the second portion of the first electrode plate are formed in sequence.
  • the transition electrode ET and the second portion Cb2 of the second electrode plate Cb are located on the same layer and spaced apart from each other to be insulated from each other.
  • the gate of the first output transistor T10 is electrically connected to the second portion C2b2 of the second electrode C2b of the second capacitor C2, and the first electrode of the first output transistor T10 is electrically connected to the first power supply
  • the first portion VGLa of the line VGL is electrically connected
  • the second pole of the first output transistor T10 is electrically connected to the driving signal output terminal.
  • the gate of the second output transistor T9 is electrically connected to the first portion C3a1 of the first plate C3a of the third capacitor C3 through the transfer electrode ET7.
  • the first pole of the second output transistor T9 is electrically connected to the driving signal output terminal EOUT1 through a via hole
  • the second pole of the second output transistor T9 is electrically connected to the second pole of the third capacitor C3
  • the first portion C3b1 of the pole plate C3b is connected through the transition electrode ET9, and further connected to the connecting wire L4, and further electrically connected to the second clock signal wire ECB2.
  • the first portion C3b1 of the second plate C3b of the third capacitor C3 is electrically connected to the first portion ECB2a of the second clock signal line ECB2.
  • the orthographic projection of the third capacitor C3 on the base substrate is adjacent to the orthographic projection of the second output transistor T9 on the base substrate.
  • the third capacitor C3 is disposed adjacent to the second output transistor T9 to facilitate signal transmission.
  • the area of the second portion Ca2 of the first electrode plate Ca is smaller than or equal to the area of the via hole H0 penetrating the fifth insulating layer IL5 to minimize the distance between the electrode plates of the capacitor , increase the capacity.
  • the orthographic projection of the second portion Ca2 of the first electrode plate Ca on the base substrate 10 completely falls within the orthographic projection of the via hole H0 penetrating the fifth insulating layer IL5 on the base substrate 10 .
  • the shift register unit 100aa further includes a first control transistor T12, a second control transistor T1 and a first isolation transistor T13; the gate of the first control transistor T12 is connected to the second clock signal line ECB2 is electrically connected through a via hole, and the first pole of the first control transistor T12 is electrically connected to the input terminal EI through the transfer electrode ETI; the gate of the second control transistor T1 is electrically connected to the third clock signal line ECK through a via hole, and the third The first pole of the two control transistors T1 and the second pole of the first control transistor T12 are electrically connected through the transition electrode ET12, and the second pole of the second control transistor T1 and the second pole of the first isolation transistor T13 are electrically connected through the transition electrode ET1 Electrical connection, the first pole of the first isolation transistor T13 and the second plate of the first capacitor C1 are electrically connected through the transfer electrode ET13, and the gate of the first isolation transistor T13 and the first part VGLa of the
  • the first control transistor T12 is arranged close to the second clock signal line ECB2, the orthographic projection of the first control transistor T12 on the base substrate and the second clock signal line ECB2 on the base substrate
  • the orthographic projection on the second output transistor T9 is on the same side as the orthographic projection of the second output transistor T9 on the base substrate.
  • the first control transistor T12 and the second clock signal line ECB2 are located on the same side of the second output transistor T9.
  • both the first control transistor T12 and the second clock signal line ECB2 are located on the left side of the second output transistor T9.
  • the orthographic projection of the second clock signal line ECB2 on the base substrate, the orthographic projection of the first control transistor T12 on the base substrate, and the orthographic projection of the second output transistor T9 on the base substrate are along the second direction X in order.
  • the second clock signal line ECB2 , the first control transistor T12 , and the second output transistor T9 are sequentially arranged along the second direction X.
  • the second clock signal line ECB2 , the first control transistor T12 , the first capacitor C1 , the second capacitor C2 , and the second output transistor T9 are sequentially arranged along the second direction X.
  • the second clock signal line ECB2 , the first control transistor T12 , the fourth capacitor C4 , the third capacitor C3 , and the second output transistor T9 are sequentially arranged along the second direction X.
  • the shift register unit 100aa further includes a third control transistor T3, a fourth control transistor T2 and a second isolation transistor T14.
  • the gate of the third control transistor T3 is electrically connected to the third clock signal line ECK through a via hole, and the first electrode of the third control transistor T3 and the first power supply line VGL are connected to the transfer electrode ET3 (as shown in FIG. 16 ) and a wire M3 is electrically connected, and the second pole of the third control transistor T3 is electrically connected to the second pole of the fourth control transistor T2 through the transfer electrode ET14 (as shown in FIG. 16 ); the gate of the fourth control transistor T2 is connected to the connecting line L5 is electrically connected to the transfer electrode ET1.
  • the connection trace L5 and/or the transfer electrode ET1 can be used as the first isolation node P31.
  • the first pole of the fourth control transistor T2 is connected to the third clock signal line ECK by switching
  • the connection electrode ET2 and the gate of the third control transistor T3 are electrically connected, the second pole of the fourth control transistor T2 and the second pole of the third control transistor T3 are electrically connected through the transfer electrode ET14; the gate of the second isolation transistor T14 It is electrically connected with the first power supply line VGL through the transfer electrode ET3 and the wire M3, the first pole of the second isolation transistor T14 is electrically connected with the second pole of the fourth control transistor T2 through the transfer electrode ET14, and the second isolation transistor T14 is electrically connected.
  • the second pole is connected to the transition electrode ETa.
  • the shift register unit 100aa further includes a fifth control transistor T6 , a sixth control transistor T7 , a seventh control transistor T8 and a fourth capacitor C4 .
  • the first electrode plate of the fourth capacitor C4 is electrically connected to the transfer electrode ETa, and further connected to the second electrode of the second isolation transistor T14.
  • the gate G6 of the fifth control transistor T6 is electrically connected to the first plate C4a of the fourth capacitor C4 (the first part C4a1 and the second part C4a2 of the first plate C4a) through the transfer electrode ETa, and the fifth control transistor T6 is electrically connected.
  • the first pole is electrically connected with the second plate C4b of the fourth capacitor C4 through the transfer electrode ETd
  • the second pole of the fifth control transistor T6 is electrically connected with the first clock signal line ECB through the transfer electrode ET6 and the wire M1
  • the gate G7 of the six control transistors T7 is electrically connected to the first clock signal line ECB through the transfer electrode ET6 and the wire M1, and the first pole of the sixth control transistor T7 and the second plate of the fourth capacitor C4 pass through the transfer electrode ETd.
  • the second pole of the sixth control transistor T7 is electrically connected to the first plate C3a of the third capacitor C3 through the transfer electrode ET7; the gate G8 of the seventh control transistor T8 is connected to the wire L5 and the transfer electrode ET1 It is electrically connected to the second pole of the second control transistor T1, the first pole of the seventh control transistor T8 is electrically connected to the second power supply line VGH through the transfer electrode ET8, the wire M2 and the transfer electrode ETb, and the seventh control transistor T8
  • the second electrode is electrically connected to the first electrode plate C3a of the third capacitor C3 through the transfer electrode ET7.
  • the fourth capacitor C4 is disposed adjacent to the fifth control transistor T6 and the sixth control transistor T7 .
  • the orthographic projection of the fourth capacitor C4 on the substrate is adjacent to the orthographic projection of the fifth control transistor T6 on the substrate, and the orthographic projection of the fourth capacitor C4 on the substrate is adjacent to the orthographic projection of the sixth control transistor T7 on the substrate.
  • the orthographic projections on the substrate are adjacent.
  • the fourth capacitor C4 is disposed close to the fifth control transistor T6 and the sixth control transistor T7 to facilitate signal transmission.
  • the connection between the fourth capacitor C4 and the center of the fifth control transistor T6 and the sixth control transistor T7 forms an obtuse triangle.
  • the center of the fourth capacitor C4 includes the center of the first electrode plate C4a or the center of the second electrode plate C4b of the fourth capacitor C4.
  • the center of the fifth control transistor T6 includes the center of the active layer A6, and the center of the sixth control transistor T7 includes the center of the active layer A7.
  • the center of the transistor may refer to the center of the active layer of the transistor, and the center of the capacitor may refer to the center of any electrode plate thereof.
  • the center of an element may refer to the geometric center of the element.
  • the fifth control transistor T6 and the sixth control transistor T7 are arranged along the second direction X, and the fifth control transistor T6 and the sixth control transistor T7 are located on the same side of the fourth capacitor C4 .
  • the fifth control transistor T6 and the sixth control transistor T7 are located on the lower side of the fourth capacitor C4.
  • the connection line L4 is located on the upper side of the fourth capacitor C4, then the fifth control transistor T6 and the sixth control transistor T7, and the connection line L4 are respectively arranged on opposite sides of the fourth capacitor C4.
  • the fifth control transistor T6 and the sixth control transistor T7 are both located between the seventh control transistor T8 and the fourth capacitor C4.
  • the fifth control transistor T6 , the sixth control transistor T7 and the seventh control transistor T8 are located in the area surrounded by the first capacitor C1 , the second capacitor C2 and the fourth capacitor C4 .
  • the fifth control transistor T6, the sixth control transistor T7 and the seventh control transistor T8 are located in the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 within the surrounding area.
  • the first capacitor C1 and the third capacitor C3 are arranged in the second direction X
  • the second capacitor C2 and the fourth capacitor C4 are arranged in the first direction Y
  • the second capacitor C2 is located in the first capacitor
  • the fourth capacitor C4 is located between the first capacitor C1 and the third capacitor C3.
  • the first transistor T5 is set between the first capacitor C1 and the second capacitor C2, and the third capacitor C3 to the second capacitor C2
  • the distance in the second direction X is smaller than the distance in the second direction X between the first capacitor C1 to the second capacitor C2.
  • the distance between the third capacitor C3 and the fourth capacitor C4 in the second direction X is greater than the distance between the first capacitor C1 and the fourth capacitor C4 in the second direction X on the distance.
  • FIG. 22 is a schematic diagram of a layout of the shift register unit 100a shown in FIG. 2B in the display substrate.
  • 23 to 29 are plan views of wirings or vias in each layer of the display substrate shown in FIG. 22 .
  • 30 to 37 are plan views of a plurality of film layers in the display substrate shown in FIG. 22 .
  • FIG. 38 is a cross-sectional view taken along line A-B of FIG. 22 .
  • FIG. 39 is a cross-sectional view along line E1-F1, E2-F2, or E4-F4 of FIG. 22 .
  • FIG. 40 is a cross-sectional view taken along line E3-F3 of FIG. 22 .
  • FIG. 41 is a schematic diagram illustrating the arrangement positions of each connection trace, transfer electrode, and wire in the display substrate shown in FIG. 22 .
  • 23 is a plan view of an active layer of a display substrate provided by at least one embodiment of the disclosure
  • FIG. 24 is a plan view of a first conductive layer of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 25 is at least one embodiment of the present disclosure A plan view of the provided second conductive layer of the display substrate, FIG.
  • FIG. 26 is a distribution diagram of via holes penetrating at least one of the first insulating layer, the second insulating layer and the third insulating layer of the display substrate provided by at least one embodiment of the present disclosure
  • 27 is a plan view of a third conductive layer of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 28 is a view of a via hole penetrating through the fourth insulating layer and the fifth insulating layer of the display substrate provided by at least one embodiment of the present disclosure.
  • Distribution diagram, FIG. 29 is a distribution diagram of via holes penetrating through the fourth insulating layer (the first planarization layer) of the display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 30 is a schematic view of stacking a semiconductor layer LY0 of a display substrate and a via hole penetrating through an interlayer insulating layer ILD (a first insulating layer IL1 , a second insulating layer IL2 and a third insulating layer IL3 ) according to at least one embodiment of the present disclosure .
  • 31 is a schematic view of a stack of a first conductive layer LY1 of a display substrate and a via hole passing through an interlayer insulating layer ILD according to at least one embodiment of the present disclosure.
  • 32 is a schematic view of a stack of the second conductive layer LY2 of the display substrate and the via hole penetrating through the interlayer insulating layer ILD according to at least one embodiment of the present disclosure.
  • 33 is a schematic view of a stack of a semiconductor layer LY0, a via hole penetrating the interlayer insulating layer ILD, and a third conductive layer LY3 of a display substrate according to at least one embodiment of the present disclosure.
  • 34 is a schematic view of stacking the first conductive layer LY1 , the via hole penetrating the interlayer insulating layer ILD, and the third conductive layer LY3 of the display substrate according to at least one embodiment of the present disclosure.
  • 35 is a schematic diagram of a stack of the second conductive layer LY2, the via hole penetrating the interlayer insulating layer ILD, and the third conductive layer LY3 of the display substrate provided by at least one embodiment of the present disclosure.
  • 36 is a schematic view of a stack of a fourth conductive layer LY4 of a display substrate, and via holes penetrating through the fourth insulating layer and the fifth insulating layer according to at least one embodiment of the present disclosure.
  • 37 is a schematic diagram of a stack of a third conductive layer LY3, via holes penetrating the fourth insulating layer and the fifth insulating layer, and a fourth conductive layer LY4 of a display substrate according to at least one embodiment of the present disclosure.
  • a part of the clock signal line and the first power supply line VGL are located on one side of the shift register unit 100ab, and the other part of the clock signal line and the second power supply line VGH are located on the other side of the shift register unit 100aa.
  • the first control transistor T12 is close to or in phase with Adjacent to the second output transistor T9, the first control transistor T12 and the second clock signal line ECB2 are located on opposite sides of the second output transistor T9.
  • the orthographic projection of the first control transistor T12 on the base substrate and the orthographic projection of the second clock signal line ECB2 on the base substrate are located on opposite sides of the orthographic projection of the second output transistor T9 on the base substrate.
  • the first control transistor T12 , the second output transistor T9 , and the second clock signal line ECB2 are sequentially arranged along the second direction X.
  • the orthographic projection of the first control transistor T12 on the base substrate, the orthographic projection of the second output transistor T9 on the base substrate, and the orthographic projection of the second clock signal line ECB2 on the base substrate The projections are arranged in sequence along the second direction X. For example, as shown in FIG.
  • the orthographic projection of the second control transistor T1 on the base substrate, the orthographic projection of the first control transistor T12 on the base substrate, the orthographic projection of the second output transistor T9 on the base substrate, And the orthographic projections of the second clock signal lines ECB2 on the base substrate are sequentially arranged along the second direction X.
  • the orthographic projection of the second control transistor T1 on the base substrate, the orthographic projection of the second capacitor C2 on the base substrate, the orthographic projection of the first control transistor T12 on the base substrate, the The orthographic projections of the two output transistors T9 on the base substrate and the orthographic projections of the second clock signal line ECB2 on the base substrate are sequentially arranged along the second direction X.
  • the center line connecting the first control transistor T12 , the second control transistor T1 and the first isolation transistor T13 forms an acute triangle.
  • a line connecting the center of the first control transistor T12, the center of the first node control transistor T11, and the center of the seventh control transistor T8 forms an acute triangle.
  • the center of the orthographic projection of the first control transistor T12 on the base substrate, the center of the orthographic projection of the first node control transistor T11 on the base substrate, and the seventh control transistor T8 on the substrate The center of the orthographic projection on the substrate forms an acute triangle.
  • the first control transistor T12, the first node control transistor T11, and the seventh control transistor T8 are disposed adjacent to each other.
  • the orthographic projection of the first control transistor T12 on the base substrate, the orthographic projection of the first node control transistor T11 on the base substrate, and the orthographic projection of the seventh control transistor T8 on the base substrate are disposed adjacent to each other.
  • the orthographic projection of the first control transistor T12 on the base substrate is located between the orthographic projection of the second output transistor T9 on the base substrate and the orthographic projection of the first node control transistor T11 on the base substrate between.
  • the orthographic projection of the first node control transistor T11 on the base substrate and the orthographic projection of the seventh control transistor T8 on the base substrate are arranged along the first direction Y, and the first node control transistor T11 is at The orthographic projection on the base substrate and the orthographic projection of the second output transistor T9 on the base substrate are arranged along the second direction X.
  • the orthographic projection of the third capacitor C3 on the base substrate is located between the orthographic projection of the second output transistor T9 on the base substrate and the orthographic projection of the second power line VGH on the base substrate .
  • the display substrate shown in FIG. 22 does not use a two-layer metal structure in parallel for each clock signal line, the first power supply line VGL, and the second power supply line VGL, and the first capacitor C1 ,
  • the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are not connected in parallel with three capacitors.
  • the first conductive layer LY1 is provided with wires M1 and M2, and compared with the display substrate shown in FIG. 3, the first conductive layer LY1 is not provided with wires M3.
  • the third conductive layer LY3 is provided with a transfer electrode ET3m, a transfer electrode ET0, and a transfer electrode ET121.
  • the transfer electrode ET1 is connected to the first electrode of the first transistor T5 and formed integrally.
  • the transfer electrode ET5a serves as the first pole of the first transistor T5.
  • the transfer electrode ET3m is equivalent to integrating the functions of the transfer electrode ET3 and the wire M3 in the display substrate shown in FIG. 3 .
  • the transfer electrode ETbm is equivalent to integrating the functions of the transfer electrode ETb and the wire M2 in the display substrate shown in FIG. 3 .
  • the transfer electrode ET0 is connected to the transfer electrode ET121 through the transfer electrode ET122.
  • the first end of the transfer electrode ET122 is connected to the transfer electrode ET121
  • the second end of the transfer electrode ET122 is connected to the transfer electrode ET0.
  • the transfer electrode ET121 is connected to and integrally formed with the second pole of the first control transistor T12, in other words, at least a part of the transfer electrode ET121 serves as the second pole of the first control transistor T12.
  • the transition electrode ET0 is connected to and integrally formed with the first pole of the transistor T1, in other words, at least a part of the transition electrode ET0 serves as the first pole of the transistor T1.
  • the transfer electrode ET0 , the transfer electrode ET121 and the transfer electrode ET122 in the display substrate shown in FIG. 22 may have the same functions as the transfer electrode ET12 in the display substrate shown in FIG. 3 .
  • the second power supply line VGH is connected to the transfer electrode ET8 through the transfer electrode ETbm.
  • the capacitors shown in FIG. 22 (including the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4) all adopt the manner in which the first electrode plate and the second electrode plate are oppositely arranged with an insulating layer interposed therebetween.
  • form. 32 and 35 show the first electrode plate C1a of the first capacitor C1, the first electrode plate C2a of the second capacitor C2, the second electrode plate C3b of the third capacitor C3, and the first electrode plate of the fourth capacitor C4 Plate C4a.
  • 31 shows the second electrode plate C1b of the first capacitor C1, the second electrode plate C2b of the second capacitor C2, the first electrode plate C31 of the third capacitor C3, and the second electrode plate C4b of the fourth capacitor C4.
  • first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 in the display substrate shown in FIG. The first part Ca1 and the second part Ca2 of the first pole plate Ca of the capacitor in the shown display substrate are replaced by the first pole plate Ca, and the first part Cb1 and the second part Cb2 of the second pole plate Cb are replaced by the second pole plate Ca.
  • the plate Cb can be used.
  • the first plate C1a of the first capacitor C1 is connected to the transfer electrode ET4 through a via hole
  • the first plate C2a of the second capacitor C2 is connected to the transfer electrode ETc through a via hole
  • the third capacitor The second plate C3b of C3 is connected to the second clock signal line ECB2 through a via hole
  • the first plate C4a of the fourth capacitor C4 is connected to the transfer electrode ETa through a via hole.
  • the second electrode plate C3b of the third capacitor C3 is connected to the transfer electrode ET9 through a via hole.
  • the output terminal EOUT1 is connected to the transfer electrode ET10 through a via hole.
  • connection methods and functions of the remaining transfer electrodes shown in FIG. 34 reference may be made to the connection methods and functions of the respective transfer electrodes shown in FIG. 3 .
  • the position of the transistor T12 is adjusted in the display substrate shown in FIG. 22, and part of the wiring design is adjusted.
  • the gate G12 of the transistor T12 and the transfer electrode ET9 pass through the via hole. connected to the second electrode plate C3b of the third capacitor C3, and further connected to the second clock signal line ECB2.
  • the transfer electrode ET5a may also be referred to as a conductive portion CP
  • FIG. 38 shows the gate G5 of the first transistor T5 and the channel CNL of the first transistor T5.
  • the gate G5 and the channel CNL of the first transistor T5 partially overlap in the third direction Z.
  • the third direction Z is a direction perpendicular to the base substrate 10 .
  • the gate of the first transistor T5 is connected to the first electrode of the first transistor T5 through the conductive portion CP (transfer electrode ET5 a ) to form a diode structure.
  • the conductive portion CP is connected to the active layer A5 of the first transistor T5 through the first via hole H1.
  • the orthographic projection of the channel CNL of the first transistor T5 on the base substrate 10 does not overlap with the orthographic projection of the first via hole H1 on the base substrate 10 to avoid the formation of via holes During the process, the channel of the first transistor T5 is destroyed, which can effectively realize the unidirectional current flow function of the diode-connected first transistor T5, and effectively remove the noise interference in the holding stage.
  • the conductive portion CP is connected to the gate G5 of the first transistor T5 through the second via hole H2, and the orthographic projection of the channel CNL of the first transistor T5 on the base substrate 10 is connected to the second via hole H2.
  • the orthographic projections of the hole H2 on the base substrate 10 do not overlap, so as to avoid damaging the channel of the first transistor T5 during the process of forming the via hole.
  • the capacitor C includes the first pole plate Ca and the second pole plate Cb, the transfer electrode ET01 is connected to the first pole plate Ca, the transfer electrode ET02 is connected to the second pole plate Cb, and the second pole plate Cb is located in the second conductive layer LY2, the first electrode plate Ca is located in the first conductive layer LY1, and the transfer electrode ET01 and the transfer electrode ET02 are located in the second conductive layer LY3.
  • the first electrode plate Ca and the second electrode plate Cb are disposed opposite to each other with a dielectric layer sandwiched therebetween to form a capacitor, and the capacitor C can be at least one of the first capacitor C1, the second capacitor C2 and the fourth capacitor C4.
  • the first electrode plate Ca is the first electrode plate C1a
  • the second electrode plate Cb is the second electrode plate C1b
  • the transfer electrode ET01 is the transfer electrode ET4
  • the transfer electrode ET02 is the transfer electrode ET5a.
  • the first electrode plate Ca is the first electrode plate C2a
  • the second electrode plate Cb is the second electrode plate C2b
  • the transfer electrode ET01 is the transfer electrode ETc
  • the transfer electrode ET02 is the transfer electrode ET5.
  • the first pole plate Ca is the first pole plate C4a
  • the second pole plate Cb is the second pole plate C4b
  • the transfer electrode ET01 is the transfer electrode ETa
  • the transfer electrode ET02 is the transfer electrode ETd.
  • the first electrode plate C1a, the first electrode plate C2a and the first electrode plate C4a are located in the second conductive layer LY2, the second electrode The plate C1b, the second plate C2b and the second plate C4b are located in the first conductive layer LY1.
  • the first electrode plate C3a is located on the first conductive layer LY1
  • the second electrode plate C3b is located on the second conductive layer LY2.
  • the first electrode plate C3a and the second electrode plate C3b face each other with a dielectric layer interposed therebetween, thereby forming a capacitor.
  • the second pole plate C1b, the second pole plate C2b, the first pole plate C3a and the second pole plate C4b are located in the first conductive layer LY1; the first pole plate C1a, the first pole plate C2a, the second electrode plate C3b and the first electrode plate C4a are located on the second conductive layer LY2.
  • the orthographic projection of the first capacitor C1 on the base substrate 10 and the orthographic projection of the first transistor T5 on the base substrate 10 partially overlap, and the second capacitor C2 is on the base substrate 10
  • the orthographic projection of the first transistor T5 partially overlaps the orthographic projection of the first transistor T5 on the base substrate 10 .
  • the fourth capacitor C4 and the centers of the fifth control transistor T6 and the sixth control transistor T7 form an acute triangle.
  • the third control transistor T3 , the fourth control transistor T2 and the second isolation transistor T14 are arranged in sequence along the second direction X, and the third control transistor T3 is located on the base substrate.
  • the orthographic projection on the substrate is adjacent to the orthographic projection of the fourth control transistor T2 on the base substrate
  • the orthographic projection of the second isolation transistor T14 on the base substrate is adjacent to the orthographic projection of the fourth control transistor T2 on the base substrate .
  • the display substrate further includes a gate driving circuit (not shown in the figure) and a trigger signal line.
  • the trigger signal line is configured to provide a trigger signal to the gate driving circuit, and the orthographic projection of the trigger signal line on the base substrate 10 is located at a position where the orthographic projection of the second clock signal line ECB2 on the base substrate 10 is far from the display area 102 . side.
  • the gate driving circuit is the aforementioned light-emitting control driving circuit array (EM GOA), which includes a plurality of cascaded shift register units 100aa or a plurality of cascaded shift register units 100ab, so that one by one The row outputs a light-emitting control signal.
  • EM GOA light-emitting control driving circuit array
  • the trigger signal line is connected to the first pole of the transistor T12 of the first stage shift register unit of the gate driving circuit to provide the trigger signal.
  • the line width of the traces in each layer is, for example, generally 3 microns, and the spacing between traces in the same layer is, for example, greater than 3 microns.
  • the wiring spacing is related to the accuracy of the exposure machine, for example, the higher the accuracy of the exposure machine, the smaller the spacing can be, which can be determined according to the actual situation, which is not limited by the embodiments of the present disclosure.
  • necessary spacing must be left between the traces on the same layer to avoid wire adhesion, signal short circuit, and the like in the actual process.
  • the distance between the orthographic projection of each trace of the first conductive layer LY1 on the base substrate 10 and the orthographic projection of each trace of the second conductive layer LY2 on the base substrate 10 is, for example, generally 1.5 ⁇ m, for example , the gate of the transistor in the first conductive layer LY1 should exceed its active layer on the semiconductor layer LY0 by, for example, more than 2 microns. For example, as shown in FIG.
  • the "U"-shaped double gate of the transistor T2 in the first direction Y is beyond the active layer of the transistor T2 on both sides of the active layer of the transistor T2, for example, more than 2 microns, for example, not
  • the length of the portion overlapping with the active layer of the transistor T2 in the first direction Y is 2 micrometers or more, which is not limited by the embodiment of the present disclosure.
  • the distance between the orthographic projection of the active layer of each transistor on the semiconductor layer LY0 on the base substrate 10 and the orthographic projection of each gate wiring on the first conductive layer LY1 on the base substrate 10 is 1.5 above microns, so that channel effects can be avoided between the gate traces and the active layers of the respective transistors on the semiconductor layer LY0.
  • the distance between the orthographic projection of the semiconductor layer LY0 on the base substrate 10 and the orthographic projection of the second conductive layer LY2 on the base substrate 10 may be unlimited, for example, may be overlapped.
  • a certain distance is reserved as far as possible between the traces of different layers (the distance is smaller than the distance between the traces of the same layer), so that unnecessary overlap can be reduced, so as to reduce or avoid excessive parasitic capacitance. Large harassment.
  • the width of each trace of the third conductive layer LY3 should cover (for example, completely cover) its corresponding via hole, for example, it may exceed the size of the via hole (for example, the diameter of the via hole) by more than 1 micron, for example , the size of the via hole is 2.0 micrometers to 2.5 micrometers, and the width of each trace of the third conductive layer LY3 surrounding the via hole is 4 micrometers to 5 micrometers.
  • the line widths of the first output transistor T10 and the output transistor T9 corresponding to the via hole are 1 micrometer above and below the via hole, for example, 4.0 micrometers to 4.5 micrometers.
  • the width of the trace connecting other transistors located in the third conductive layer LY3 only needs to meet the requirement of covering the via hole exceeding 1 micron at the via position, that is, Yes, for example, the trace width between vias can be thinner.
  • the spacing between the lines is more than 3 microns, and the line widths of the first clock signal line ECB, the second clock signal line ECB2, the third clock signal line ECK, and the fourth clock signal line ECK2 are set at 4 microns in order to meet the driving capability requirements. above.
  • the line width of each clock signal line is 4-10 microns.
  • the line width of each clock signal line is 8 micrometers or 10 micrometers.
  • the line width of the first power line VGL can be 6, 9 or 10 microns
  • the line width of the second power line VGH is for example 10 microns
  • the first power supply voltage provided by the first power line VGL is generally -7V, for example.
  • the thickness of the first conductive layer LY1 and the second conductive layer LY2 is 2000-3000 angstroms
  • the thickness of the third conductive layer LY3 and the fourth conductive layer LY4 is 5000-8000 angstroms
  • the embodiments of the present disclosure There is no restriction on this.
  • each of the above-mentioned transfer electrodes, wires and connection traces may function as connections or jumper connections.
  • the display substrate provided by the above embodiments of the present disclosure optimizes the line connection and structural layout of the shift register unit, compresses the length of the shift register unit in the first direction or the second direction to a certain extent, and further reduces the shift register unit.
  • the size of the bit register unit is favorable for realizing a narrow frame design by using the display substrate, and at the same time ensuring the display quality achieved by using the display substrate.
  • any capacitor in the display substrate shown in FIG. 22 may also adopt the parallel design method adopted by any capacitor in the display substrate shown in FIG. 3 .
  • the capacitances of the second capacitor C2 and the third capacitor C3 can be increased, for example, the second capacitor C2 in the display substrate shown in FIG. 22 and at least one of the third capacitor C3 is designed as a parallel capacitor.
  • FIG. 21 is a schematic diagram showing the arrangement position of each transfer electrode, each connection wire, and each wire in the display substrate shown in FIG. 3 .
  • FIG. 41 is a schematic diagram showing the arrangement position of each transfer electrode, each connection wire, and each wire in the display substrate shown in FIG. 22 .
  • the display substrate shown in FIG. 22 is not provided with connecting lines L4 , and neither the conducting wires M2 nor the conducting wires M3 are provided.
  • the display substrate shown in FIG. 22 is the same as the display substrate shown in FIG. 3 in that: connecting wires L1-L3 and connecting wires L5 are provided; and a conducting wire M1 is provided.
  • the transfer electrode ET12 in the display substrate shown in FIG. 3 is combined by the transfer electrode ET121, the transfer electrode ET122, and the transfer electrode ET0 in the display substrate shown in FIG. 22.
  • the function of the structure is replaced; the transfer electrode ET5, the transfer electrode ET11 and the second electrode plate C2b of the second electrode of the integrated structure in the display substrate shown in FIG. 3 are respectively set in the display substrate shown in FIG.
  • the function of the combined structure of the transfer electrode ET5, the transfer electrode ET11 and the second plate C2b of the second electrode is replaced; the transfer electrode ETb in the display substrate shown in FIG. 3 is replaced by the display shown in FIG. 22.
  • the transit electrode ETbm in the substrate is replaced.
  • the components in the display substrate shown in FIG. 3 are in the light dashed box (where the arrow starts), which is replaced by the component in the dark dashed box (where the arrow ends) to form The display substrate shown in FIG. 22 .
  • the elements in the solid-line frame are elements that are not provided in the display substrate shown in FIG. 22 but are provided in the display substrate shown in FIG. 3 .
  • connection trace L5 may be referred to as the first connection trace
  • the connection trace L1 may be referred to as the second connection trace
  • the connection trace L2 may be referred to as the second connection trace
  • the connection trace L3 may be referred to as the fourth connection trace
  • the connection trace L4 may be referred to as the fifth connection trace.
  • the connection wires may be directly connected to the components located at both ends thereof, or it can be said that the connection wires may be integrally formed with the components at both ends thereof.
  • the wire M1 may be referred to as the first wire
  • the wire M2 may be referred to as the second wire
  • the wire M3 may be referred to as the third wire.
  • each component is not marked in FIG. 3 and FIG. 22 , and the reference numerals of each element may refer to the reference numerals in the single-layer or multi-layer structure of the display substrate shown in FIG. 22 .
  • the transfer electrode ET5a may be referred to as the first transfer electrode TR1, and the transfer electrode ET5 may be referred to as the second transfer electrode TR2, the transfer electrode ET4 may be referred to as the third transfer electrode TR3, the transfer electrode ET13 may be referred to as the fourth transfer electrode TR4, and the transfer electrode ET6 may be referred to as the fifth transfer electrode TR5, and the transfer electrode ET11 may be referred to as the sixth transfer electrode TR6, the transfer electrode ETc may be referred to as the seventh transfer electrode TR7, the transfer electrode ET10 may be referred to as the eighth transfer electrode TR8, and the transfer electrode ET7 may be referred to as the eighth transfer electrode TR8.
  • the ninth transfer electrode TR9, the transfer electrode ET9 may be referred to as the tenth transfer electrode TR10, the transfer electrode ET8 may be referred to as the eleventh transfer electrode TR11, and the transfer electrode ETI may be referred to as the twelfth transfer electrode
  • the transfer electrode ET1 may be referred to as As the fourteenth transfer electrode TR14
  • the transfer electrode ET3 may be referred to as the fifteenth transfer electrode TR15
  • the transfer electrode ET14 may be referred to as the sixteenth transfer electrode TR16
  • the transfer electrode ET2 may be referred to as the sixteenth transfer electrode TR16.
  • the seventeenth transit electrode TR17, the transit electrode ETa may be referred to as the eighteenth transit electrode TR18, and the transit electrode ETd may be referred to as the nineteenth transit electrode TR19.
  • FIG. 42 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • the display device 2 includes a display substrate 1 , and the display substrate 1 may be a display substrate provided in any embodiment of the present disclosure, for example, the display substrate shown in FIG. 3 or FIG. 22 .
  • the display device 2 can be any product or component with a display function, such as an OLED panel, an OLED TV, a QLED panel, a QLED TV, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, and a navigator.
  • the display device 2 may further include other components, such as a data driving circuit, a timing controller, etc., which are not limited in the embodiments of the present disclosure.
  • the display device 2 can be used as a display device of low frequency GOA, but is not limited thereto.
  • the embodiments of the present disclosure do not provide all the constituent units of the display device 2 .
  • those skilled in the art can provide or set other structures not shown according to specific needs, which are not limited by the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure further provides a method for fabricating a display substrate, such as the method for fabricating a display substrate provided by any embodiment of the present disclosure.
  • the method can be used to manufacture the display substrate provided by any embodiment of the present disclosure, for example, can be used to manufacture the display substrate shown in FIG. 2 above.
  • the manufacturing method of the display substrate includes steps S110 to S120.
  • Step S110 Provide a base substrate.
  • Step S120 forming a shift register unit, a first power supply line for supplying a first power supply voltage, a second power supply line for supplying a second power supply voltage, a first clock signal line, a second clock signal line, a third power supply line on the base substrate a clock signal line and a fourth clock signal line.
  • a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fifth insulating layer, and a fourth conductive layer are formed respectively include forming corresponding material layers (eg, semiconductor material layers, insulating material layers or conductive material layers), and then using a patterning process to respectively form corresponding pattern structures (eg, active layers, electrode patterns, traces, vias, etc.) .
  • corresponding material layers eg, semiconductor material layers, insulating material layers or conductive material layers
  • the patterning process is, for example, a photolithography process, for example, including: coating a photoresist layer on the material layer to be patterned, exposing the photoresist layer using a mask, and developing the exposed photoresist layer to obtain A photoresist pattern, using the photoresist pattern to etch the structural layer, and then optionally removing the photoresist pattern.
  • a photolithography process for example, including: coating a photoresist layer on the material layer to be patterned, exposing the photoresist layer using a mask, and developing the exposed photoresist layer to obtain A photoresist pattern, using the photoresist pattern to etch the structural layer, and then optionally removing the photoresist pattern.
  • the base substrate 10 may be made of glass, plastic, quartz, or other suitable materials, which are not limited in the embodiments of the present disclosure.
  • the signal line ECK2 is formed on the base substrate 10 .
  • forming the shift register unit 100aa includes: sequentially forming the semiconductor layer LY0, the first insulating layer IL1, the first conductive layer LY1, the second insulating layer IL2, the second The conductive layer LY2, the third insulating layer IL3, the third conductive layer LY3, the fourth insulating layer IL4, the fifth insulating layer IL5, and the fourth conductive layer LY4.
  • each transistor is located in the semiconductor layer LY0, the gate of each transistor and the first part of the second plate of each capacitor are located in the first conductive layer LY1, and the first part of the first plate of each capacitor is located in the second conductive layer LY2 , the second part of the second plate of each capacitor is located in the third conductive layer LY3, the second part of the first plate of each capacitor is located in the fourth conductive layer LY4, the first part of the first power line VGL, the second power line
  • the pole and the second pole are located in the third conductive layer LY3.
  • the second portion of the fourth clock signal line ECK2 is located on the fourth conductive layer LY4.
  • the respective transistors and the respective capacitors are connected to each other and to the first power supply line VGL, the second power supply line VGH, and the first power supply line VGL through vias penetrating the first insulating layer IL1, the second insulating layer IL2, or the third insulating layer IL3.
  • the first clock signal line ECB, the second clock signal line ECB2, the third clock signal line ECK, and the fourth clock signal line ECK2 are connected.
  • the second power supply line VGH For the arrangement of the respective transistors and capacitors of the shift register unit 100aa, the second power supply line VGH, the first power supply line VGL, a plurality of clock signal lines, and the connection structure of the connecting lines, wires and transfer electrodes, please refer to the corresponding drawings. The corresponding description of , will not be repeated here.
  • forming the shift register unit 100ab includes: sequentially forming the semiconductor layer LY0, the first insulating layer IL1, the first conductive layer LY1, the second insulating layer IL2, the second The conductive layer LY2, the third insulating layer IL3, the third conductive layer LY3, the fourth insulating layer IL4, the fifth insulating layer IL5, and the fourth conductive layer LY4.
  • the active layer of each transistor is located in the semiconductor layer LY0, the gate of each transistor, the second plate of the first capacitor C1, the second plate of the second capacitor C2, the second plate of the fourth capacitor C4, and the third plate.
  • the first plate of the capacitor C3 is located in the first conductive layer LY1, the first plate of the first capacitor C1, the first plate of the second capacitor C2, the first plate of the fourth capacitor C4, and the third capacitor C3
  • the second plate is located in the second conductive layer LY2, the first power line VGL, the second power line VGH, the first clock signal line ECB, the second clock signal line ECB2, the third clock signal line ECK and the fourth clock signal line
  • the ECK2 and the first and second electrodes of the respective transistors are located on the third conductive layer LY3.
  • the transfer electrode ET122 and the transfer electrode ETbm are located on the fourth conductive layer LY4.
  • forming the semiconductor layer LY0 includes using the first conductive layer LY1 as a mask for doping, so as to conduct a portion of the active layer that is not covered by the pattern of the first conductive layer LY1 to form a source
  • the electrode region or the drain region is formed, and the part of the active layer covered by the pattern of the first conductive layer LY1 maintains semiconductor properties, forming a channel of the transistor.
  • forming the first conductive layer LY1 includes forming a first conductive film, and patterning the first conductive film to form the first conductive layer LY1.
  • forming the second conductive layer LY2 includes forming a second conductive film, and patterning the second conductive film to form the second conductive layer LY2.
  • a third insulating film is formed on the second conductive layer LY2, the third insulating film is patterned, and via holes are formed in the third insulating film , to form a third insulating layer IL3, the via hole in the third insulating layer IL3 is shown in FIG. 8, a third conductive film is formed on the third insulating layer IL3, and the third conductive film is patterned to form a third conductive layer , the pattern of the third conductive layer is shown in FIG. 9 .
  • some elements in the pattern of the third conductive layer may be connected to elements at corresponding positions in the semiconductor layer LY0 through vias penetrating through the third insulating layer IL3, the second insulating layer IL2, and the first insulating layer IL1, Some elements in the pattern of the third conductive layer may be connected to elements at corresponding positions in the first conductive layer LY1 through vias penetrating through the third insulating layer IL3 and the second insulating layer IL2, and in the pattern of the third conductive layer Some of the elements may be connected to elements at corresponding positions in the second conductive layer LY2 through vias penetrating through the third insulating layer IL3.
  • a fourth conductive film is formed on the third conductive layer LY3, and the fourth conductive film is patterned to form a fourth conductive layer LY4.
  • the pattern of the fourth conductive layer LY4 is shown in FIG. 12 .
  • elements in the fourth conductive layer LY4 may be connected to elements at corresponding positions in the third conductive layer LY3 through via holes penetrating through the fourth insulating layer LY4.
  • the elements in the semiconductor layer LY0 may be connected with the elements in the third conductive layer LY3 through via holes
  • the elements in the first conductive layer LY1 may be connected with the elements in the third conductive layer LY3 through the via holes
  • the elements in the second conductive layer LY2 can be connected to the elements in the third conductive layer LY3 through via holes.
  • Elements in the third conductive layer LY3 may be connected to elements in the fourth conductive layer LY4 through vias.
  • the elements in the semiconductor layer LY0 may be connected to the elements in the second conductive layer LY2 through the elements in the third conductive layer LY3, and the elements in the first conductive layer LY1 may be connected with the elements in the third conductive layer LY1
  • the elements in the conductive layer LY3 are connected to the elements in the second conductive layer LY2.
  • the elements in the semiconductor layer LY0 are not directly connected with the elements in the second conductive layer LY2, and the elements in the first conductive layer LY1 are not directly connected with the elements in the second conductive layer LY2.
  • the elements in the semiconductor layer LY0 are not in direct contact with the elements in the second conductive layer LY2, and the elements in the first conductive layer LY1 are not in direct contact with the elements in the second conductive layer LY2.
  • the process of the manufacturing method of the display substrate may include more or less operations, and these operations may be performed sequentially or in parallel.
  • the flow of the fabrication method described above includes various operations occurring in a particular order, it should be clearly understood that the order of the various operations is not limited.
  • the manufacturing method described above may be performed once, or may be performed multiple times according to predetermined conditions.
  • the transistor T1 may be referred to as the second control transistor T1
  • the transistor T2 may be referred to as the fourth control transistor T2
  • the transistor T3 may be referred to as The third control transistor T3, the transistor T4 may be referred to as the second transistor T4
  • the transistor T5 may be referred to as the first transistor T5
  • the transistor T6 may be referred to as the fifth control transistor T6
  • the transistor T7 may be referred to as the sixth control transistor T7
  • transistor T8 may be referred to as a seventh control transistor T8
  • transistor T9 may be referred to as a second output transistor T9
  • transistor T10 may be referred to as a first output transistor T10
  • transistor T11 may be referred to as a first node control transistor T11
  • the transistor T12 may be referred to as a first control transistor T12
  • the transistor T13 may be referred to as a first isolation transistor T13
  • the transistor T14 may be referred to as referred to as a third control transistor T

Abstract

提供一种显示基板和显示装置。显示基板包括：移位寄存器单元、第一时钟信号线和第一电源线，移位寄存器单元包括电荷泵电路，电荷泵电路包括第一电容、第一晶体管和第二电容，电荷泵电路分别与第一输入节点和第一节点电连接，第一电容的第一极板与第一时钟信号线相连，第一电容的第二极板与第一输入节点相连，第二电容的第一极板与第一电源线相连，第二电容的第二极板与第一节点相连，第一晶体管的栅极与第一晶体管的第一极或第二极相连，第一电容在衬底基板上的正投影和第一晶体管在衬底基板上的正投影相邻，并且第二电容在衬底基板上的正投影与第一晶体管在衬底基板上的正投影相邻。

Description

显示基板和显示装置 技术领域
本公开至少一实施例涉及一种显示基板和显示装置。
背景技术
在显示技术领域，例如液晶显示面板或有机发光二极管(Organic Light Emitting Diode,OLED)显示面板的像素阵列通常包括多行栅线和与栅线交叉设置的多列数据线。对栅线的驱动可以通过绑定的集成驱动电路实现。近几年随着非晶硅薄膜晶体管或氧化物薄膜晶体管制备工艺的不断提高，也可以将栅线驱动电路直接集成在薄膜晶体管阵列基板上形成GOA(Gate driver On Array)来对栅线进行驱动。例如，可以采用包括多个级联的移位寄存器单元的GOA为像素阵列的多行栅线提供开关态电压信号(扫描信号)，从而例如控制多行栅线依序打开，并且同时由数据线向像素阵列中对应行的像素单元提供数据信号，以在各像素单元形成显示图像的各灰阶所需要的灰度电压，进而显示一帧图像。
发明内容
本公开的至少一实施例涉及一种显示基板和显示装置。
本公开至少一实施例提供一种显示基板，包括：衬底基板；设置在所述衬底基板的周边区的移位寄存器单元、第一时钟信号线和第一电源线，所述移位寄存器单元包括电荷泵电路，所述第一时钟信号线被配置为向所述移位寄存器单元提供第一时钟信号，所述第一电源线被配置为向所述移位寄存器单元提供第一电源电压，所述电荷泵电路包括第一电容、第一晶体管和第二电容，所述电荷泵电路分别与第一输入节点和第一节点电连接，所述第一电容的第一极板与所述第一时钟信号线相连，所述第一电容的第二极板与所述第一输入节点相连，所述第二电容的第一极板与所述第一电源线相连，所述第二电容的第二极板与所述第一节点相连，所述第一晶体管的栅极与所述第一晶体管的第一极或第二极相连，所述第一电容在所述衬底基板上的正投影和所述第一晶体管在所述衬底基板上的正投影相邻，并且所述第二电容在所述衬底基板上的正投影与所述第一晶体管在衬底基板上的正投影相邻。
例如，在本公开一些实施例中，所述电荷泵电路被配置为在第一时间段，在所述第一时钟信号线提供的所述第一时钟信号的控制下，将所述第一输入节点的电位由第一电压信号转换为第二电压信号，并将所述第二电压信号传输至所述第一节点，并被配置为在第二时间段维持所述第一节点的电位。
例如，在本公开一些实施例中，所述第一电压信号的极性与所述第二电压信号的极性相同，所述第二电压信号的电压值的绝对值大于所述第一电压信号的电压值的绝对值。
例如，在本公开一些实施例中，显示基板还包括第一转接电极和第二转接电极；所述第一晶体管的栅极与所述第一晶体管的第一极通过所述第一转接电极相连以形成二极管结构，所述第一转接电极的第一端与所述第一晶体管的第一极相连，所述第一转接电极的第二端与所述第一晶体管的栅极相连，所述第二转接电极的第一端与所述第一晶体管的第二极相连，所述第二转接电极的第二端与所述第二电容的第二极板相连，所述第一晶体管的第一极通过第一过孔与所述第一晶体管的有源层相连，所述第一晶体管的沟道在所述衬底基板上的正投影与所述第一过孔在所述衬底基板上的正投影不交叠。
例如，在本公开一些实施例中，所述第一转接电极通过第二过孔与所述第一晶体管的栅极相连，所述第一晶体管的所述沟道在所述衬底基板上的正投影与所述第二过孔在所述衬底基板上的正投影不交叠。
例如，在本公开一些实施例中，所述第二过孔在垂直于所述衬底基板的方向上的高度小于所述第一过孔在垂直于所述衬底基板的方向上的高度。
例如，在本公开一些实施例中，所述第一过孔贯穿第一绝缘层、第二绝缘层和第三绝缘层，所述第二过孔贯穿所述第二绝缘层和所述第三绝缘层。
例如，在本公开一些实施例中，所述第一晶体管的所述沟道在所述衬底基板上的正投影与所述第一晶体管的栅极在所述衬底基板上的正投影部分交叠。
例如，在本公开一些实施例中，所述第一电容的电容值大于或等于所述第二电容的电容值。
例如，在本公开一些实施例中，所述第一电容的电容值小于或等于所述第二电容的电容值的十倍。
例如，在本公开一些实施例中，所述第二电容的电容值的范围为0.01pF-2pF。
例如，在本公开一些实施例中，所述第一电容和所述第二电容至少之一为三个电容并联的结构，所述三个电容并联的结构包括第二极板的第一部分、第二极板的第二部分、第一极板的第一部分、以及第一极板的第二部分。
例如，在本公开一些实施例中，所述第二极板的第一部分和所述第二极板的第二部分通过第三过孔相连，所述第一极板的第一部分和所述第一极板的第二部分通过转接部相连，所述第三过孔和所述转接部分别位于所述三个电容并联的结构的相对的两侧，所述第二极板的第一部分、所述第一极板的第一部分、所述第二极板的第二部分、以及所述第一极板的第二部分依次设置以形成所述三个电容并联的结构，所述转接部与所述第二极板的第二部分位于同一层并彼此绝缘。
例如，在本公开一些实施例中，所述第一电容的第二极板在所述衬底基板上的正投影和所述第一晶体管的第一极在所述衬底基板上的正投影部分交叠，并且所述第二电容的第二极板在所述衬底基板上的正投影与所述第一晶体管的第二极在所述衬底基板上的正投影部分交叠。
例如，在本公开一些实施例中，显示基板还包括第一导线和第三转接电极；所述第一导线的第一端与所述第一时钟信号线相连，所述第一导线的第二端与所述第三转接电极的第一端相连，所述第三转接电极的第二端与所述第一电容的第一极板相连。
例如，在本公开一些实施例中，显示基板还包括第四转接电极和第五转接电极，其中，所述电荷泵电路还包括第二晶体管，所述第四转接电极的第一端与所述第二晶体管的栅极相连，所述第四转接电极的所述第一端与所述第一电容的第二极板相连，所述第五转接电极的第一端与所述第二晶体管的第一极相连，所述第五转接电极的第二端与所述第一导线相连，所述第一导线与所述第一时钟信号线相连，所述第二晶体管的第二极与所述第三转接电极相连。
例如，在本公开一些实施例中，所述第一时钟信号线在所述衬底基板上沿第一方向延伸，并且所述第一电容、所述第一晶体管和所述第二电容在所述第二方向上依次排布，所述第一方向与所述第二方向相交。
例如，在本公开一些实施例中，显示基板还包括第六转接电极、第七转接电极、第八转接电极、第九转接电极、第十转接电极、第十一转接电极、第二时钟信号线和第二电源线；所述第二时钟信号 线被配置为向所述移位寄存器单元提供第二时钟信号，所述第二电源线被配置为向所述移位寄存器单元提供第二电源电压，所述移位寄存器单元还包括第一节点控制晶体管、第一输出晶体管、第二输出晶体管和第三电容；所述第一输出晶体管的栅极与所述第二电容的第二极板通过所述第六转接电极电连接，所述第一输出晶体管的第一极与所述第一电源线通过所述第七转接电极电连接，所述第一输出晶体管的第二极通过所述第八转接电极与驱动信号输出端电连接；所述第二输出晶体管的栅极与所述第三电容的第一极板通过所述第九转接电极电连接，所述第二输出晶体管的第一极与所述驱动信号输出端通过所述第八转接电极电连接，所述第二输出晶体管的第二极与所述第二时钟信号线通过所述第十转接电极电连接；所述第三电容的第二极板与所述第二时钟信号线电连接；所述第一节点控制晶体管的第一极与所述第二电源线通过所述第六转接电极电连接，所述第一节点控制晶体管的第二极与所述第一节点通过所述第十一转接电极电连接。
例如，在本公开一些实施例中，所述第三电容在所述衬底基板上的正投影与所述第二输出晶体管在所述衬底基板上的正投影相邻。
例如，在本公开一些实施例中，所述第二电源线和所述第一电源线分设在所述移位寄存器单元的两侧。
例如，在本公开一些实施例中，所述第二时钟信号线与所述第二电源线位于所述移位寄存器单元的同一侧，或者，所述第二时钟信号线与所述第一电源线位于所述移位寄存器单元的同一侧。
例如，在本公开一些实施例中，显示基板还包括第十二转接电极、第十三转接电极、第十四转接电极、以及第三时钟信号线；所述第三时钟信号线被配置为向所述移位寄存器单元提供第三时钟信号，所述移位寄存器单元还包括第一控制晶体管、第二控制晶体管和第一隔离晶体管；所述第一控制晶体管的栅极与所述第二时钟信号线电连接，所述第一控制晶体管的第一极与输入端通过所述第十二转接电极电连接；所述第二控制晶体管的栅极与所述第三时钟信号线电连接，所述第二控制晶体管的第一极与所述第一控制晶体管的第二极通过所述第十三转接电极电连接，所述第二控制晶体管的第二极与所述第一隔离晶体管的第二极通过所述第十四转接电极电连接，所述第一隔离晶体管的第一极与所述第一电容的第二极板通过所述第四转接电极电连接，所述第一隔离晶体管的栅极与所述第一电源线电连接。
例如，在本公开一些实施例中，所述第一控制晶体管和所述第二时钟信号线位于所述第二输出晶体管的同一侧，或者，所述第一控制晶体管和所述第二时钟信号线位于所述第二输出晶体管的相对的两侧。
例如，在本公开一些实施例中，所述第一控制晶体管、所述第二控制晶体管和所述第一隔离晶体管的中心连线构成锐角三角形。
例如，在本公开一些实施例中，所述第二控制晶体管、所述第一控制晶体管、所述第二输出晶体管以及所述第二时钟信号线沿所述第二方向依次排列。
例如，在本公开一些实施例中，所述第二控制晶体管、所述第二电容、所述第一控制晶体管、所述第二输出晶体管和所述第二时钟信号线沿所述第二方向依次排列。
例如，在本公开一些实施例中，显示基板还包括第十五转接电极、第十六转接电极、第十七转接电极以及第十八转接电极；所述移位寄存器单元还包括第三控制晶体管、第四控制晶体管和第二隔离 晶体管；所述第三控制晶体管的栅极与所述第三时钟信号线电连接，所述第三控制晶体管的第一极与所述第一电源线通过所述第十五转接电极电连接；所述第四控制晶体管的栅极与所述第二控制晶体管的第二极电连接，所述第四控制晶体管的第一极与所述第三时钟信号线通过所述第十七转接电极电连接，所述第四控制晶体管的第二极与所述第三控制晶体管的第二极通过所述第十六转接电极电连接；所述第二隔离晶体管的栅极与所述第一电源线电连接，所述第二隔离晶体管的第一极与所述第四控制晶体管的第二极通过所述第十六转接电极电连接，所述第二隔离晶体管的第二极与所述第十八转接电极相连。
例如，在本公开一些实施例中，所述第三控制晶体管、所述第四控制晶体管和所述第二隔离晶体管沿所述第二方向依次排列，所述第三控制晶体管在所述衬底基板上的正投影与所述第四控制晶体管在所述衬底基板上的正投影相邻，所述第二隔离晶体管在所述衬底基板上的正投影与所述第四控制晶体管在所述衬底基板上的正投影相邻。
例如，在本公开一些实施例中，显示基板还包括连接走线和第十九转接电极，所述移位寄存器单元还包括第五控制晶体管、第六控制晶体管、第七控制晶体管和第四电容；所述第四电容的第一极与所述第十八转接电极电连接，所述第五控制晶体管的栅极与所述第四电容的第一极板通过所述第十八转接电极电连接，所述第五控制晶体管的第一极与所述第四电容的第二极板通过所述第十九转接电极电连接，所述第五控制晶体管的第二极与所述第一时钟信号线通过所述第五转接电极电连接；所述第六控制晶体管的栅极与所述第一时钟信号线通过所述第五转接电极电连接，所述第六控制晶体管的第一极与所述第四电容的第二极板通过所述第十九转接电极电连接，所述第六控制晶体管的第二极与所述第三电容的第一极板通过所述第九转接电极电连接；所述第七控制晶体管的栅极与所述第二控制晶体管的第二极通过所述连接走线以及所述第十四转接电极电连接，所述第七控制晶体管的第一极与所述第二电源线通过所述第十一转接电极电连接，所述第七控制晶体管的第二极与所述第二输出晶体管的栅极通过所述第九转接电极电连接；所述第一节点控制晶体管的栅极与所述第四电容的第二极板相连。
例如，在本公开一些实施例中，所述第五控制晶体管在所述衬底基板上的正投影与所述第四电容在所述衬底基板上的正投影相邻，所述第六控制晶体管在所述衬底基板上的正投影与所述第四电容在所述衬底基板上的正投影相邻。
例如，在本公开一些实施例中，所述第四电容的中心、所述第五控制晶体管的中心、所述第六控制晶体管的中心构成钝角三角形或锐角三角形。
例如，在本公开一些实施例中，所述第五控制晶体管和所述第六控制晶体管沿所述第二方向排列，所述第五控制晶体管和所述第六控制晶体管位于所述第四电容的同一侧。
例如，在本公开一些实施例中，所述第一电容和所述第三电容在所述第一方向上排列，所述第二电容和所述第四电容在所述第二方向上排列，所述第二电容位于所述第一电容和所述第三电容之间，所述第四电容位于所述第一电容和所述第三电容之间。
例如，在本公开一些实施例中，所述第三电容到所述第二电容之间的在所述第二方向上的距离大于所述第一电容到所述第二电容之间的在所述第二方向上的距离。
本公开至少一实施例还提供一种显示装置，包括上述任一显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种显示面板的整体电路架构的示意图。
图1B是一种移位寄存器单元的示意图。
图1C为图1B所示的移位寄存器单元工作时的信号时序图。
图2A是一种移位寄存器单元的示意图。
图2B为一种移位寄存器单元的电路图。
图2C为图2B所示的移位寄存器单元工作时的信号时序图。
图3为图2B中所示的移位寄存器单元在显示基板中的一种布局示意图。
图4至图12为图3所示的显示基板的各层布线或者过孔的平面图。
图13至图19为图3所示的显示基板中的多个膜层的平面图。
图20A为图3的沿线A-B的剖视图。
图20B为图3的沿线E1-F1、E2-F2、E3-F3、或E4-F4的剖视图。
图21为图3所示的显示基板中各个连接走线、转接电极、导线的设置位置的示意图。
图22为图2B中所示的移位寄存器单元在显示基板中的一种布局示意图。
图23至图29为图22所示的显示基板的各层布线或者过孔的平面图。
图30至图37为图22所示的显示基板中的多个膜层的平面图。
图38为图22的沿线A-B的剖视图。
图39为图22的沿线E1-F1、E2-F2、或E4-F4的剖视图。
图40为图22的沿线E3-F3的剖视图。
图41为图22所示的显示基板中各个连接走线、转接电极、导线的设置位置的示意图。
图42为本公开至少一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变 后，则该相对位置关系也可能相应地改变。
图1A为一种显示面板的整体电路架构的示意图。例如，如图1A所示，附图标记101指向的矩形框表示显示面板的整体外框线；显示面板101包括显示区(即像素阵列区)102以及位于显示区102周边的周边区106，该显示区102包括阵列排布的像素单元103；该周边区106包括扫描驱动移位寄存器单元104，多个级联的扫描驱动移位寄存器单元104组成栅极驱动电路(Gate GOA)，用于向显示面板101的显示区102中的阵列排布的像素单元103提供例如逐行移位的栅极扫描信号；该周边区106还包括发光控制移位寄存器单元105，多个级联的发光控制移位寄存器单元105组成发光控制驱动电路阵列(EM GOA)，用于向显示面板101的显示区102中的阵列排布的像素单元103提供例如逐行移位的发光控制信号，即是用于输出发光控制信号的栅极驱动电路。
在一些实施例中，一个移位寄存器单元104的输出电路输出的输出信号对应输出至两行像素单元103，本公开的实施例包括但不限于此。
如图1A所示，与数据驱动芯片IC连接的数据线DL1-DLN(N为大于1的整数)纵向穿过显示区102，以为阵列排布的像素单元103提供数据信号；与扫描驱动移位寄存器单元104和发光控制移位寄存器单元105连接的栅线GL1-GLM(M为大于1的整数)横向穿过显示区102，以为阵列排布的像素单元103提供栅极扫描信号和发光控制信号。例如，各个像素单元103可以包括本领域内的具有7T1C、8T2C或4T1C等电路结构的像素电路和发光元件，像素电路在通过数据线传输的数据信号和通过栅线传输的栅极扫描信号和发光控制信号的控制下工作，以驱动发光元件发光从而实现显示等操作。该发光元件例如可以为有机发光二极管(OLED)或量子点发光二极管(QLED)。
为了使保持像素亮度波动在合理的范围内，静态画面时仍然需要刷新数据，因为控制亮度的电压会由于漏电而随时间变化。为了降低功耗，降低刷新频率是比较有效的方法，同时还需要保持显示质量，就需要减少像素漏电速度，而氧化物半导体具有超低漏电的特性，满足这种需求。为了使得像素单元具有较快的充电速度和较小的寄生电容，比较好的办法是结合低温多晶硅(Low Tempreture Poly-Silicon，LTPS)和氧化物(Oxide)半导体的优势，采用(Low Temperature Polycrystalline Oxide，LTPO)工艺制作显示基板。即，同一个像素单元中集成了低温多晶硅(LTPS)和氧化物(Oxide)两种TFT器件。
图1B是一种移位寄存器单元的示意图。图1C为图1B所示的移位寄存器单元工作时的信号时序图。如图1C所示，该移位寄存器单元的工作过程包括6个阶段，分别为第一阶段PS1、第二阶段PS2、第三阶段PS3、第四阶段PS4、第五阶段PS5以及第六阶段PS6。第一阶段PS1为输入阶段，第二阶段PS2为输出阶段，第三阶段PS3为复位阶段，第四阶段PS4为第一保持时间段，第五阶段PS5为第二保持时间段，第六阶段PS6为第三保持时间段。即，第四阶段PS4、第五阶段PS5和第六阶段PS6构成保持阶段。如图1B所示，移位寄存器单元采用十个晶体管(T1-T10)和三个电容的10T3C(电容C1-电容C3)结构。该结构在用于OLED发光控制开关EM时，复位延迟的影响可以忽略，但当用于LTPO工艺制作的显示基板中的氧化物薄膜晶体管的开关控制时，将严重影响像素单元的充电时间。例如，AMOLED的数据线共用，逐行给像素单元充电，GOA提供像素单元的开关信号，为了防止数据错充，只有当开关闭合后，即GOA输出复位后，数据信号才能改变为下一行的数据，而这段等待GOA复位的时间像素单元是不能有效充电的。分辨率、刷新率确定之后，每行像素单元可用的总时间 就定了，则GOA复位越快，像素充电时间越长，反之，则像素充电时间越短，因为复位台阶延迟可能达2行时间之久。
如图1B所示，当多个移位寄存器单元级联时，第一级移位寄存器单元中的晶体管T1的第一极和输入端EI连接，输入端EI被配置为与触发信号线连接以接收触发信号作为输入信号，而其它各级移位寄存器单元中的晶体管T1的第一极和上一级移位寄存器单元的输出端EOUT电连接，以接收上一级移位寄存器单元的输出端EOUT输出的输出信号作为输入信号，由此实现移位输出，以向显示面板101的显示区102中的阵列排布的像素单元103提供例如逐行移位的发光控制信号。
另外，如图1B所示，该移位寄存器单元还包括时钟信号端CK和时钟信号端CB。例如，时钟信号端CK和时钟信号端CB之一被配置为提供第一时钟信号，时钟信号端CK和时钟信号端CB之另一被配置为提供第二时钟信号。例如，第一时钟信号以及第二时钟信号可以采用占空比大于50％的脉冲信号，并且二者例如相差半个周期。例如，VGL表示第一电源线以及第一电源线提供的第一电源电压，VGH表示第二电源线以及第二电源线提供的第二电源电压，且第二电源电压大于第一电源电压。例如，第二电源电压为直流高电平，第一电源电压为直流低电平；N1、N2、N3以及N4分别表示电路示意图中的第一节点、第二节点、第三节点以及第四节点。例如，第一电源电压VGL可以为VSS，第二电源电压VGH可以为VDD。
图1B示出了半导体层LY0、第一导电层LY1和第二导电层LY2。半导体层LY0包括各个晶体管的有源层，第一导电层LY1包括各个晶体管的源极和漏极，第二导电层LY2包括各种连接线。
为了减少像素单元的漏电速度，将电荷泵电路引入去噪模块，以利于去噪模块在保持阶段持续开启，及时去除噪声干扰，从而确保GOA输出稳定，提升驱动电路和显示的稳定性。例如，去噪模块包括电荷泵电路和去噪晶体管。例如，去噪晶体管包括第一输出晶体管T10。
图2A是一种移位寄存器单元的示意图。图2B为一种移位寄存器单元的电路图。图2C为图2B所示的移位寄存器单元工作时的信号时序图。下面结合图2A至图2C对该移位寄存器单元的工作过程进行简要地介绍。
如图2A所示，移位寄存器单元100包括电荷泵电路11。电荷泵电路11分别与第一输入节点P11、第一时钟信号端CB和第一节点P1电连接，并被配置为在第一时间段，在第一时钟信号端CB提供的第一时钟信号的控制下，将第一输入节点P11的电位由第一电压信号转换为第二电压信号，并将第二电压信号传输至第一节点P1，并被配置为在第二时间段维持第一节点P1的电位。即，在第二时间段，第一节点P1的电位维持为第二电压信号。例如，第一电压信号的极性与第二电压信号的极性相同，第二电压信号的电压值的绝对值大于第一电压信号的电压值的绝对值。例如，在第二时间段，第一节点P1维持为第二电压信号时，第一输入节点P11的电压信号可被调整为第一电压信号。例如，第一时间段为第一保持时间段，第二时间段为第二保持时间段。例如，在第二时间段，第一节点P1维持为第二电压信号时，第一输入节点P11的电压信号可为第一电压信号。例如，第一时间段为第一保持时间段，第二时间段为第三保持时间段。图2C示出了第一电压信号V01和第二电压信号V02。
电荷泵是电路中一种类似水泵的结构，主要通过电容、时钟、以及二极管整流结构，实现对电荷的再分配，实现升压(或降压)的目的。例如，含有电荷泵电路11的移位寄存器单元能够通过电荷泵电路11在保持阶段充分拉低或升高第一节点P1的电位，使得在保持阶段，由第一节点P1控制的第一 输出晶体管保持开启，进而使得在保持阶段，能够使得移位寄存器单元输出的驱动信号的电位不受噪声干扰的影响。
例如，第一电压信号的极性与第二电压信号的极性相同指的是：当第一电压信号为正电压信号时，第二电压信号为正电压信号；当第一电压信号为负电压信号时，第二电压信号为负电压信号。
第二电压信号的电压值的绝对值大于第一电压信号的电压值的绝对值指的是：当第一电压信号为正电压信号时，第二电压信号的电压值大于第一电压信号的电压值；当第一电压信号为负电压信号时，第二电压信号的电压值小于第二电压信号的电压值。
移位寄存器单元100在工作时，电荷泵结构11能够在保持阶段进一步拉低或升高第一节点P1的电位。
例如，移位寄存器单元100在工作时，当第一电压信号的电位为-5V，第二电压信号的电位大于或等于-15V而小于或等于-10V，也即电荷泵电路可以将第一电压信号的电位泵低2-3倍，但不以此为限。
如图2B所示，该移位寄存器单元100a包括14个晶体管T1-T14以及4个电容(第一电容C1、第二电容C2、第三电容C3和第四电容C4)。图2B示出了各个晶体管的第一极a和第二极b，各个电容的第一极板a和第二极板b。在图2B以及后续附图所示的本公开的实施例中，为了描述方便，将图中所示的T1-T14简化为晶体管T1-T14，为了区分各晶体管，可对各晶体管进行名称上的限定，例如，晶体管T1被称作第二控制晶体管T1，晶体管T2被称作第四控制晶体管T2，晶体管T3被称作第三控制晶体管T3，晶体管T4被称作第二晶体管T4，晶体管T5被称作第一晶体管T5，晶体管T6被称作第五控制晶体管T6，晶体管T7被称作第六控制晶体管T7，晶体管T8被称作第七控制晶体管T8，晶体管T9被称作第二输出晶体管T9，晶体管T10被称作第一输出晶体管T10，晶体管T11被称作第一节点控制晶体管T11，晶体管T12被称作第一控制晶体管T12，晶体管T13被称作第一隔离晶体管T13，晶体管T14被称作第二隔离晶体管T14。例如，当多个移位寄存器单元100a级联时，第一级移位寄存器单元100a中的第一控制晶体管T12的第一极和输入端EI连接，输入端EI被配置为与触发信号线连接以接收触发信号作为输入信号，而其它各级移位寄存器单元100a中的第一控制晶体管T12的第一极和上一级移位寄存器单元100a的输出端EOUT电连接，以接收上一级移位寄存器单元100a的输出端EOUT输出的输出信号作为输入信号，由此实现移位输出，以向显示面板101的显示区102中的阵列排布的像素单元103提供例如逐行移位的发光控制信号。
另外，如图2B所示，该移位寄存器单元100a还包括第一时钟信号端CB和第二时钟信号端CB2。例如，第一时钟信号端CB与第一时钟信号线或第二时钟信号线连接以接收第一时钟信号。例如，当第一时钟信号端CB与第一时钟信号线连接时，第一时钟信号线提供第一时钟信号；当第一时钟信号端CB与第二时钟信号线连接时，第二时钟信号线提供第一时钟信号；具体视实际情况而定，本公开的实施例对此不作限制。类似地，第二时钟信号端CB2与第二时钟信号线或第一时钟信号线连接以接收第二时钟信号。下面以第一时钟信号端CB与第一时钟信号线连接以接收第一时钟信号，第二时钟信号端CB2与第二时钟信号线连接以接收第二时钟信号为例进行介绍，本公开的实施例对此不作限制。例如，第一时钟信号以及第二时钟信号可以采用占空比大于50％的脉冲信号，并且二者例如可以相差半个周期。
另外，如图2B所示，该移位寄存器单元还包括第三时钟信号端CK和第四时钟信号端CK2(图 2B未示出)。例如，在与图2B所示的移位寄存器单元的下一级移位寄存器单元中图2B所示的第三时钟信号端CK可替换为第四时钟信号端CK2。例如，第三时钟信号端CK与第三时钟信号线或第四时钟信号线连接以接收第三时钟信号。例如，当第三时钟信号端CK与第三时钟信号线连接时，第三时钟信号线提供第三时钟信号；当第三时钟信号端CK与第四时钟信号线连接时，第四时钟信号线提供第三时钟信号；具体视实际情况而定，本公开的实施例对此不作限制。类似地，第四时钟信号端CK2与第三时钟信号线或第四时钟信号线连接以接收第四时钟信号。下面以第三时钟信号端CK与第三时钟信号线连接以接收第三时钟信号，第四时钟信号端CK2与第四时钟信号线连接以接收第四时钟信号为例进行介绍，本公开的实施例对此不作限制。例如，第三时钟信号以及第四时钟信号可以采用占空比大于50％的脉冲信号，并且二者例如可以相差半个周期。
例如，VGL表示第一电源线以及第一电源线提供的第一电源电压，VGH表示第二电源线以及第二电源线提供的第二电源电压，且第一电源电压大于第二电源电压。例如，第一电源电压为直流高电平，第二电源电压为直流低电平。例如，P31、P11、P1、P2、P12、P13、以及P32分别表示电路示意图中的第一隔离节点、第一输入节点、第一节点、第二节点、第二输入节点、第三输入节点、以及第二隔离节点。即，图2B示出了第一隔离节点P31、第一输入节点P11、第一节点P1、第二节点P2、第二输入节点P12、第三输入节点P13、以及第二隔离节点P32。如图2B所示，移位寄存器单元100a包括电荷泵电路11、第一隔离节点控制子电路41、第一隔离子电路42、第一储能电路31、第一节点控制电路12、第二隔离节点控制子电路32、第二隔离子电路40、第二输入节点控制子电路33、第二节点控制子电路34、以及输出电路30。
如图2B所示，电荷泵电路11包括第一时钟信号端CB、第一电容C1、第一晶体管T5和第二电容C2。第一电容C1的第一极板与第一时钟信号端CB相连，第一电容C1的第二极板与第一输入节点P11相连。第一晶体管T5的第一极与第一输入节点P11相连，第一晶体管T5的第二极与第一节点P1相连。第一晶体管T5的栅极与第一晶体管T5的第一极或第二极相连，以形成二极管方式连接的三极管。第二电容C2的第一极板与第一电源线VGL相连，第二电容C2的第二极板与第一节点P1相连。
如图2B所示，电荷泵电路11还包括第二晶体管T4。第二晶体管T4的栅极与第一输入节点P11电连接，第二晶体管T4的第一极与第一时钟信号端CB电连接，第二晶体管T4的第二极与第一电容C1的第一极板电连接。
需要说明的是，电荷泵电路11也可以不包括第二晶体管T4，在电荷泵电路11不包括第二晶体管T4的情况下，第一时钟信号端CB与第一电容C1的第一极板相连。
如图2B所示，输出电路30分别与第一节点P1、第二节点P2、第一电源线VGL、第二时钟信号端CB2以及输出端EOUT相连，输出电路30被配置为在第一节点P1的电位的控制下，将第一电源电压输出至输出端EOUT，以进行复位，并在第二节点P2的电位的控制下，将第二时钟信号输出至输出端EOUT，以输出有效的驱动信号。
如图2B所示，输出电路30包括第一输出晶体管T10和第二输出晶体管T9。第一输出晶体管T10的栅极与第一节点P1电连接，第一输出晶体管T10的第一极与第一电源线VGL电连接，第一输出晶体管T10的第二极与驱动信号输出端EOUT电连接。第二输出晶体管T9的栅极与第二节点P2电连接，第二输出晶体管T9的第一极与驱动信号输出端EOUT电连接，第二输出晶体管T9的第二极与第二时 钟信号端CB2电连接。一方面，通过增加第二时钟信号端CB2，加快输出端EOUT的复位速度。另一方面，通过使得第二输出晶体管T9的第二极与第二时钟信号端CB2相连，利于加快输出端EOUT的充放电速度。
例如，第一输出晶体管T10为p型晶体管，第一电压信号为负电压信号；或者，第一输出晶体管T10为n型晶体管，第一电压信号为正电压信号。
例如，当第一输出晶体管为p型晶体管时，第一电压信号可以为负电压信号，电荷泵电路11可进一步拉低第一节点P1的电位；当第一输出晶体管为n型晶体管时，第一电压信号可以为正电压信号，电荷泵电路11可进一步升高第一节点P1的电位；但不以此为限。如图2C所示，该移位寄存器单元的工作过程包括6个阶段，分别为第一阶段PS1、第二阶段PS2、第三阶段PS3、第四阶段PS4、第五阶段PS5以及第六阶段PS6。第一阶段PS1为输入阶段，第二阶段PS2为输出阶段，第三阶段PS3为复位阶段，第四阶段PS4为第一保持时间段，第五阶段PS5为第二保持时间段，第六阶段PS6为第三保持时间段。即，第四阶段PS4、第五阶段PS5和第六阶段PS6构成保持阶段。在本公开的实施例中，移位寄存器单元的一工作周期可以包括依次设置的输入阶段、输出阶段、复位阶段和保持阶段，在输入阶段，输入端提供输入信号；在输出阶段，移位寄存器单元输出有效的驱动信号；在复位阶段，对驱动信号进行复位，使得移位寄存器单元输出无效的驱动信号；在保持阶段，移位寄存器单元需要保持输出无效的驱动信号。
例如，移位寄存器单元输出的驱动信号输出至像素电路的晶体管的栅极，当接收移位寄存器单元输出的驱动信号的晶体管为n型晶体管时，有效的驱动信号的电位为高电压，无效的驱动信号的电位为低电压。当接收移位寄存器单元输出的驱动信号的晶体管为p型晶体管时，有效的驱动信号的电位为低电压，无效的驱动信号的电位为高电压。
如图2B所示，第一储能电路31分别与第二节点P2和第二时钟信号端CB2相连，第一储能电路31被配置为控制第二节点P2的电位。例如，第一储能电路31被配置为在保持阶段维持第二节点P2的电位。例如，如图2B所示，第一储能电路31包括第三电容C3，第三电容C3的第一极板与第二节点P2电连接，第三电容C3的第二极板与第二时钟信号端CB2相连。
如图2B所示，第一隔离节点控制子电路41分别与第二时钟信号端CB2、第三时钟信号端CK、输入端EI以及第一隔离节点P31电连接，并被配置为在第二时钟信号和的第三时钟信号的控制下，将输入端EI的输入信号传输至第一隔离节点P31。
如图2B所示，第一隔离节点控制子电路41包括第一控制晶体管T12和第二控制晶体管T1。如图2B所示，第一控制晶体管T12的栅极与第二时钟信号端CB2电连接，第一控制晶体管T12的第一极与输入端EI电连接；第二控制晶体管T1的栅极与第三时钟信号端CK电连接，第二控制晶体管T1的第一极与第一控制晶体管T12的第二极电连接，第二控制晶体管T1的第二极与第一隔离节点P31电连接。例如，当该移位寄存器单元为第一级移位寄存器单元时，输入端EI与触发信号线连接以接收触发信号；当该移位寄存器单元为除第一级移位寄存器单元以外的其他各级移位寄存器单元时，输入端EI与其上一级移位寄存器单元的输出端EOUT连接。在其他的实施例中，第一隔离节点控制子电路41可以仅包括第一控制晶体管T12或者仅包括第二控制晶体管T1。例如，设置第一控制晶体管T12和第二控制晶体管T1，可利于减少漏电。
如图2B所示，第一隔离子电路42分别与第一电源线VGL、第一隔离节点P31和第一输入节点P11电连接，并被配置为控制第一隔离节点P31与第一输入节点P11之间是否连通。例如，设置第一隔离子电路42，能够减小第一输入节点P11向第一隔离节点P31的漏电，即，能够在第一输入节点P11的电位变化时维持第一隔离节点P31的电位，以提升驱动信号输出的响应速度。如图2B所示，第一隔离子电路42包括第一隔离晶体管T13。如图2B所示，第一隔离晶体管T13的栅极与第一电源线VGL电连接，第一隔离晶体管T13的第一极与第一输入节点P11电连接，第一隔离晶体管T13的第二极与第一隔离节点P31电连接。例如，设置第一隔离晶体管T13可以降低第一输入节点P11对第一隔离节点P31的漏电，使得驱动信号输出的响应速度更快。例如，在其他的实施例中，也可以不设置第一隔离子电路42，即，不设置第一隔离晶体管T13，此情况下，第一隔离节点P31和第一输入节点P11为同一节点。
如图2B所示，第二节点控制子电路34分别与第一时钟信号端CB、第二输入节点P12、第二节点P2、第一隔离节点P31、和第二电源线VGH电连接，第二节点控制子电路34被配置为在第一时钟信号的控制下，导通或断开第二输入节点P12与第二节点P2之间的连接，并用于在第一隔离节点P31的电位的控制下，将第二电源电压写入第二节点P2，以对第二节点P2的电位进行控制。
如图2B所示，第二节点控制子电路34包括第六控制晶体管T7和第七控制晶体管T8。如图2B所示，第六控制晶体管T7的栅极与第一时钟信号端CB电连接，第六控制晶体管T7的第一极与第二输入节点P12电连接，第六控制晶体管T7的第二极与第二节点P2电连接。第七控制晶体管T8的栅极与第一隔离节点P31电连接，第七控制晶体管T8的第一极与第二电源线VGH电连接，第七控制晶体管T8的第二极与第二节点P2电连接。例如，第六控制晶体管T7可以防止对第二输入节点P12的漏电，并隔离第四电容C4对第二节点P2的影响，增强第二时钟信号端CB2提供的第二时钟信号对第二节点P2的耦合作用，使得当第二时钟信号的电位降低时，第二节点P2的电位可以更低，从而加快第二输出晶体管T9对输出端EOUT的放电速度。
如图2B所示，第二输入节点控制子电路33分别与第三输入节点P13、第二输入节点P12和第一时钟信号端CB电连接，第二输入节点控制子电路33被配置为在第三输入节点P13的电位的控制下将第一时钟信号写入第二输入节点P12，并被配置为根据第三输入节点P13的电位控制第二输入节点P12的电位。如图2B所示，第二输入节点控制子电路33包括第五控制晶体管T6和第四电容C4。如图2B所示，第五控制晶体管T6的栅极与第三输入节点P13电连接，第五控制晶体管T6的第一极与第二输入节点P12电连接，第五控制晶体管T6的第二极与第一时钟信号端CB电连接。第四电容C4的第一极板与第三输入节点P13电连接，第四电容C4的第二极板与第二输入节点P12电连接。
如图2B所示，第二隔离节点控制子电路32分别与第一隔离节点P31、第二隔离节点P32、第三时钟信号端CK以及第一电源线VGL相连，并被配置为在第一隔离节点P31的电位和第三时钟信号的控制下，将第一电源电压或第三时钟信号输入至第二隔离节点P32，以对第二隔离节点P32的电位进行控制。
例如，如图2B所示，第二隔离节点控制子电路32包括第三控制晶体管T3和第四控制晶体管T2。如图2B所示，第三控制晶体管T3的栅极与第三时钟信号端CK电连接，第三控制晶体管T3的第一极与第一电源线VGL电连接，第三控制晶体管T3的第二极与第二隔离节点P32电连接。如图2B所 示，第四控制晶体管T2的栅极与第一隔离节点P31电连接，第四控制晶体管T2的第一极与第三时钟信号端CK电连接，第四控制晶体管T2的第二极与第二隔离节点P32电连接。
如图2B所示，第二隔离子电路40分别与第二隔离节点P32、第三输入节点P13、以及第一电源线VGL相连，并被配置为控制第二隔离节点P32和第三输入节点P13之间是否连通。设置第二隔离子电路40，可防止第三输入节点P13向第二隔离节点P32的漏电，并隔离第四电容C4对第二隔离节点P32的影响。
例如，如图2B所示，第二隔离子电路40包括第二隔离晶体管T14。如图2B所示，第二隔离晶体管T14的栅极与第一电源线VGL电连接，第二隔离晶体管T14的第一极与第二隔离节点P32电连接，第二隔离晶体管T14的第二极与第三输入节点P13电连接。设置第二隔离晶体管T14可以降低第三输入节点P13对第二隔离节点P32漏电，使得驱动信号输出的响应速度更快。在其他的实施例中，也可以不设置第二隔离子电路40，即，不设置第二隔离晶体管T14，此情况下，第二隔离节点P32和第三输入节点P13为同一节点。
如图2B所示，第一节点控制电路12分别与第二输入节点P12、第二电源线VGH、以及第一节点P1电连接，并被配置为在第二输入节点P12的电位的控制下，将第二电源电压写入第一节点P1，以对第一节点P1的电位进行控制。例如，如图2B所示，第一节点控制电路12包括第一节点控制晶体管T11。如图2B所示，第一节点控制晶体管T11的栅极与第二输入节点P12电连接，第一节点控制晶体管T11的第一极与第二电源线VGH电连接，第一节点控制晶体管T11的第二极与第一节点P1电连接。
图2B中所示的移位寄存器单元100a中的晶体管均是以P型晶体管为例进行说明的，即各个晶体管在栅极接入低电平(导通电平)时导通，而在接入高电平(截止电平)时截止。例如，晶体管的第一极可以是源极，晶体管的第二极可以是漏极。
该移位寄存器单元包括但不限于图2B的设置方式，例如，移位寄存器单元100a中的各个晶体管也可以采用N型晶体管或混合采用P型晶体管和N型晶体管，只需同时将选定类型的晶体管的端口极性按照本公开的实施例中的相应晶体管的端口极性进行连接即可。
需要说明的是，该移位寄存器单元中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，这里均以薄膜晶体管为例进行说明，例如该晶体管的有源层(沟道区)采用半导体材料，例如，多晶硅(例如低温多晶硅或高温多晶硅)、非晶硅、氧化铟镓锡(IGZO)等，而栅极、源极、漏极等则采用金属材料，例如金属铝或铝合金。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。此外，在本公开的实施例中，电容的极板可以采用金属电极或其中一个极板采用半导体材料(例如掺杂的多晶硅)。本公开的实施例中的电容的极板的材料以采用金属为例进行说明。
图2C为图2B所示的移位寄存器单元100a工作时的信号时序图以及各个节点的电位波形示意图。下面结合图2B和图2C对该移位寄存器单元的工作过程进行详细地介绍。例如，以第N+2级移位寄存器单元的工作原理进行说明，其余各级移位寄存器单元的工作原理与其类似，不再赘述。如图2C所示，该移位寄存器单元的工作过程包括6个阶段，分别为第一阶段PS1、第二阶段PS2、第三阶段PS3、第四阶段PS4、第五阶段PS5以及第六阶段PS6，图2C示出了每个阶段中各个信号的时序波形。第一阶 段PS1为输入阶段，第二阶段PS2为输出阶段，第三阶段PS3为复位阶段，第四阶段PS4为第一保持时间段，第五阶段PS5为第二保持时间段，第六阶段PS6为第三保持时间段。即，第四阶段PS4、第五阶段PS5和第六阶段PS6构成保持阶段。
在第一阶段PS1，如图2C所示，第三时钟信号端CK提供低电压，第一时钟信号端CB提供高电压，第二时钟信号端CB2提供低电压，输入端EI提供高电压，第一控制晶体管T12和第二控制晶体管T1打开，第一隔离晶体管T13打开，第一输入节点P11的电位为高电压，第一隔离节点P31的电位为高电压，第一晶体管T5和第二晶体管T4都关断；第四控制晶体管T2关断，第三控制晶体管T3打开，第二隔离晶体管T14打开，第二隔离节点P32的电位为低电压，第三输入节点P13的电位为低电压，第五控制晶体管T6打开，第二输入节点P12的电位为高电压，第六控制晶体管T7关闭，第七控制晶体管T8关闭，第一节点控制晶体管T11关闭，第一节点P1的电位维持为低电压，第二节点P2的电位维持为高电压，第一输出晶体管T10打开，第二输出晶体管T9关闭，输出端EOUT输出低电压。
在第二阶段PS2，如图2C所示，在输出阶段，第三时钟信号端CK提供高电压，第一时钟信号端CB提供低电压，第二时钟信号端CB2提供高电压，输入端EI提供低电压，第一控制晶体管T12和第二控制晶体管T1都关断，由于第一电容C1的存储作用，第一输入节点P11的电位维持为高电压，第一隔离晶体管T13打开，第一隔离节点P31的电位为高电压；第二晶体管T4关闭，第一晶体管T5关闭，第四控制晶体管T2关断，第三控制晶体管T3关断，第二隔离节点P32的电位维持为低电压，第二隔离晶体管T14关断，第三输入节点P13的电位被第四电容C4进一步拉低，第五控制晶体管T6打开，第二输入节点P12的电位为低电压，第六控制晶体管T7打开，第七控制晶体管T8关闭，第一节点控制晶体管T11打开，第一节点P1的电位为高电压，第二节点P2的电位为低电压，第二输出晶体管T9打开，第一输出晶体管T10关闭，输出端EOUT输出高电压。
在第三阶段PS3，如图2C所示，第三时钟信号端CK提供低电压，第一时钟信号端CB提供高电压，第二时钟信号端CB2提供低电压，输入端EI提供低电压，第一控制晶体管T12和第二控制晶体管T1都打开，第一输入节点P11的电位被拉低，第一隔离晶体管T13打开，第一隔离节点P31的电位被拉低，第四控制晶体管T2打开，第二晶体管T4打开，第一晶体管T5打开，第一节点P1的电位被拉低；第一输出晶体管T10打开；第三控制晶体管T3打开，第二隔离节点P32的电位为低电压，第二隔离晶体管T14打开，第五控制晶体管T6打开，第三输入节点P13的电位和第二输入节点P12的电位被拉高，第六控制晶体管T7关断，第一节点控制晶体管T11关断；第七控制晶体管T8打开，第二节点P2的电位为高电压，第二输出晶体管T9截止，输出端EOUT输出低电压。
在第四阶段PS4，如图2C所示，第三时钟信号端CK提供高电压，第一时钟信号端CB提供低电压，第二时钟信号端CB2提供高电压，输入端EI提供低电压，第一控制晶体管T12和第二控制晶体管T1都关闭，第二晶体管T4打开，第一时钟信号端CB通过第一电容C1拉低第一输入节点P11的电位，第一隔离晶体管T13关断，第一隔离节点P31的电位维持为低电压，第一晶体管T5打开，进而使得第一节点P1的电位被拉低并维持为低于VSS+Vth，Vth为第一输出晶体管T10的阈值电压，使得第一输出晶体管T10开启，进而使得输出端EOUT输出的驱动信号的电位维持为VSS，不受噪声干扰影响；第三控制晶体管T3关断，第四控制晶体管T2打开，第二隔离节点P32的电位为高电压，第 二隔离晶体管T14打开，第三输入节点P13的电位为高电压，第五控制晶体管T6关断，第二输入节点P12的电位为高电压，第六控制晶体管T7打开，第七控制晶体管T8打开，第二节点P2的电位为高电压，第二输出晶体管T9关断。
在第五阶段PS5，如图2C所示，第三时钟信号端CK提供低电压，第一时钟信号端CB提供高电压，第二时钟信号端CB2提供低电压，输入端EI提供低电压，第一控制晶体管T12和第二控制晶体管T1都打开，第一输入节点P11的电位为低电压，第一隔离晶体管T13打开，第二晶体管T4打开，第一时钟信号端CB提供的第一时钟信号的电位升高，从而通过第一电容C1拉升第一输入节点P11的电位，第一晶体管T5关闭，不影响第一节点P1的电位，在第二电容C2的作用下，使得第一节点P1的电位维持为低于VSS+Vth，Vth为第一输出晶体管T10的阈值电压，使得第一输出晶体管T10开启，进而使得输出端EOUT输出的驱动信号的电位维持为VSS，不受噪声干扰影响；第三控制晶体管T3打开，第四控制晶体管T2打开，第二隔离节点P32的电位为低电压，第二隔离晶体管T14打开，第三输入节点P13的电位为低电压，第五控制晶体管T6打开，第二输入节点P12的电位为高电压，第一节点控制晶体管T11关断，第六控制晶体管T7关断，第七控制晶体管T8打开，第二节点P2的电位为高电压，第二输出晶体管T9关断。
在第六阶段PS6，如图2C所示，第三时钟信号端CK提供高电压，第一时钟信号端CB提供低电压，第二时钟信号端CB2提供高电压，输入端EI提供低电压，第一控制晶体管T12和第二控制晶体管T1都关闭，第一输入节点P11的电位维持为低电压，第二晶体管T4打开，第一时钟信号端CB通过第一电容C1拉低第一输入节点P11的电位，第一晶体管T5打开，进而使得第一节点P1的电位维持为低于VSS+Vth，Vth为第一输出晶体管T10的阈值电压，使得第一输出晶体管T10开启，进而使得输出端EOUT输出的驱动信号的电位维持为VSS，不受噪声干扰影响；第一隔离晶体管T13关闭，第一隔离节点P31的电位维持为低电压，第三控制晶体管T3关断，第四控制晶体管T2打开，第二隔离节点P32的电位为高电压，第二隔离晶体管T14打开，第三输入节点P13的电位为高电压，第五控制晶体管T6关闭，第二输入节点P12的电位为高电压，第一节点控制晶体管T11关断，第六控制晶体管T7打开，第七控制晶体管T8打开，第二节点P2的电位为高电压，第二输出晶体管T9关断。
在保持阶段，第一节点P1的电位可以维持为低于VSS+Vth，Vth为第一输出晶体管T10的阈值电压，使得第一输出晶体管T10开启，进而使得输出端EOUT输出的驱动信号的电位维持为VSS，不受噪声干扰影响。
例如，在GOA驱动信号输出的保持阶段，第一输入节点P11为低电平VSS，晶体管T1和晶体管T12用来初始化第一输入节点P11，使其为VSS，第一电容C1和第二晶体管T4用来在第一时钟信号下降沿进一步拉低第一输入节点P11电位，通过二极管结构的第一晶体管T5将低电平保存到第一节点P1，同时通过第二电容C2存储电荷，保持电位。第一时钟信号升高时，第一输入节点P11被推高，第一晶体管T5截止，不影响第一节点P1的电位；当第三时钟信号端CK和第二时钟信号端CB2为低电平时，多余的电荷通过晶体管T1和晶体管T12释放到第一隔离节点P31。后续循环以上过程。
图2C示出了第一电压信号V01和第二电压信号V02。例如，第一电压信号V01和第二电压信号V02的极性相同，第二电压信号V02的电压值的绝对值大于第一电压信号V01的电压值的绝对值。
下面结合附图对本公开的实施例及其一些示例进行详细说明。
本公开至少一实施例提供一种显示基板。图3为图2B中所示的移位寄存器单元100a在显示基板中的一种布局示意图。
例如，如图3所示，该显示基板包括：衬底基板10和设置在衬底基板10上的移位寄存器单元100aa、第一电源线VGL、第二电源线VGH以及多条时钟信号线。例如，多条时钟信号线包括图中所示的第一时钟信号线ECB、第二时钟信号线ECB2、第三时钟信号线ECK、第四时钟信号线ECK2，还可以包括触发信号线(图中未示出)。例如，在本公开的实施例中，移位寄存器单元100aa为发光控制移位寄存器单元。
例如，第一电源线VGL、第二电源线VGH、和多条时钟信号线(例如，第一时钟信号线ECB、第二时钟信号线ECB2、第三时钟信号线ECK、第四时钟信号线ECK2)在衬底基板10上均沿第一方向Y延伸，且被配置为向移位寄存器单元100aa分别提供第一电源电压、第二电源电压和多个时钟信号(例如，上面所述的第一时钟信号、第二时钟信号等)。例如，第一电源线VGL被配置为向移位寄存器单元100aa提供第一电源电压，第二电源线VGH被配置为向移位寄存器单元100aa提供第二电源电压；第一时钟信号线ECB和第二时钟信号线ECB2被配置为分别向移位寄存器单元100aa提供第一时钟信号或第二时钟信号。例如，第一电源电压小于第二电源电压，例如第一电源电压为直流低电平，第二电源电压为直流高电平。第一电源线VGL、第二电源线VGH和多条时钟信号线与移位寄存器单元100aa的具体的连接关系可参考下面的描述。
需要说明的是，在本公开实施例中，以第一时钟信号线ECB向移位寄存器单元100aa提供第一时钟信号，且第二时钟信号线ECB2向移位寄存器单元100aa提供第二时钟信号为例进行说明，本公开的实施例包括但并不限于此。在本公开的其他一些实施例中，也可以是第一时钟信号线ECB向移位寄存器单元100aa提供第二时钟信号，第二时钟信号线ECB2向移位寄存器单元100aa提供第一时钟信号，本公开的实施例对此不作限制。
需要说明的是，在本公开实施例中，以第三时钟信号线ECK向移位寄存器单元100aa提供第三时钟信号，且第四时钟信号线ECK2向移位寄存器单元100aa提供第四时钟信号为例进行说明，本公开的实施例包括但并不限于此；在本公开的其他一些实施例中，也可以是第三时钟信号线ECK向移位寄存器单元100aa提供第四时钟信号，且第四时钟信号线ECK2向移位寄存器单元100aa提供第三时钟信号，本公开的实施例对此不作限制。
需要说明的是，第一电源线VGL、第二电源线VGH以及多条时钟信号线可以沿第一方向Y延伸且彼此平行设置，也可以交叉一定的角度(例如，小于等于20°)，本公开的实施例对此不作限制。
例如，该衬底基板10可以采用例如玻璃、塑料、石英或其他适合的材料，本公开的实施例对此不作限制。
例如，参见图1A，显示基板1包括显示区102(例如，显示区102也可以称作像素阵列区)和位于像素阵列区至少一侧的周边区106。本公开的实施例提供的移位寄存器单元100aa可为图1A所示的发光控制移位寄存器单元105，例如，上述第一电源线VGL、第二电源线VGH、多条时钟信号线和移位寄存器单元100aa位于衬底基板10的周边区106上且位于衬底基板10的一侧(如图1A所示，位于显示区102与衬底基板10的侧边之间)，例如，如图1A所示，位于衬底基板10的左侧，当然也可以位于衬底基板10的右侧或左右双侧，本公开的实施例对此不作限制。
例如，如图3所示，第一电源线VGL在衬底基板10上的正投影以及多条时钟信号线在衬底基板10上的正投影位于移位寄存器单元100aa在衬底基板10上的正投影远离显示区102的一侧，例如，在第二方向X上，均位于图3所示的移位寄存器单元100aa的左侧。第二电源线VGH位于移位寄存器单元100aa在衬底基板10上的正投影靠近显示区102的一侧，例如，在第二方向X上，位于图3所示的移位寄存器单元100aa的右侧。
例如，如图3所示，第一电源线VGL在衬底基板10上的正投影位于时钟信号线(包括第一时钟信号线ECB、第二时钟信号线ECB2、第三时钟信号线ECK以及第四时钟信号线ECK2)在衬底基板10上的正投影与移位寄存器单元100aa在衬底基板10上的正投影之间。例如，第二时钟信号线ECB2、第四时钟信号线ECK2、第一时钟信号线ECB、以及第三时钟信号线ECK在衬底基板10上沿第二方向X从左至右依次设置。
需要说明的是，上述多条时钟信号线还可以包括提供触发信号的触发信号线。例如，触发信号线在衬底基板10上的正投影可以位于第二时钟信号线ECB2在衬底基板10上的正投影远离移位寄存器单元100aa在衬底基板10上的正投影的一侧，也即，触发信号线、第二时钟信号线ECB2、第四时钟信号线ECK2、第一时钟信号线ECB、以及第三时钟信号线ECK在衬底基板10上沿第二方向X从左至右依次设置。
需要注意的是，上述走线位置仅是示例性的，只要能满足走线的设置便于实现与移位寄存器单元的连接即可，本公开的实施例对此不作限制。
例如，第一方向Y与第二方向X的夹角在70°到90°之间，并包括70°和90°。例如，第一方向Y与第二方向X的夹角为70°、75°、85°、90°或80°等，夹角的具体数值可根据实际情况设定，本公开的实施例对此不作限制。
例如，参考图1A，显示区102包括阵列排布的多个像素单元103。例如，多个像素单元103的每个包括像素电路，例如还可以进一步包括发光元件(图中未示出)。例如，发光元件包括有机发光二极管，但不限于此。
例如，多个级联的移位寄存器单元100aa(也即，发光控制移位寄存器单元100aa)组成发光控制驱动电路阵列(EM GOA)。例如，该多个移位寄存器单元100aa的输出端EOUT分别与位于像素阵列区的各行像素电路的发光控制信号端连接以向该各行像素电路提供输出信号(例如，发光控制信号)，从而实现驱动发光元件发光。例如，该像素电路可以是本领域内的例如包括7T1C、2T1C、4T2C、8T2C等电路结构的像素电路，在此不再赘述。
需要说明的是，图3中仅示出了栅极驱动电路中的第K(K为大于等于2的偶数)级移位寄存器单元100aa。例如，第一级移位寄存器单元(图中未示出)的第一时钟信号端CB(如图2B所示)和第三时钟信号线ECK连接以接收第一时钟信号，第一级移位寄存器单元的第二时钟信号端CB2和第四时钟信号线ECK2连接以接收第二时钟信号，第一级移位寄存器单元的第三时钟信号端CK(如图2B所示)和第一时钟信号线ECB连接以接收第三时钟信号，第一级移位寄存器单元的第四时钟信号端CK2和第四时钟信号线ECB2连接以接收第四时钟信号，第一级移位寄存器单元的输入端和触发信号线(图中未示出)连接以接收触发信号，第二级移位寄存器单元(图中未示出)的第一时钟信号端CB和第一时钟信号线ECB连接以接收第一时钟信号，第二级移位寄存器单元的第二时钟信号端CB2 和第二时钟信号线ECB2连接以接收第二时钟信号；第二级移位寄存器单元(图中未示出)的第三时钟信号端CK和第三时钟信号线ECK连接以接收第三时钟信号，第二级移位寄存器单元的第四时钟信号端CK2和第四时钟信号线ECK2连接以接收第四时钟信号；以此类推，如图2和图3所示，第K(K为大于等于2的偶数)级移位寄存器单元100aa的第一时钟信号端CB和第一时钟信号线ECB连接以接收第一时钟信号，第K级移位寄存器单元的第二时钟信号端CB2和第二时钟信号线ECB2连接以接收第二时钟信号；第K级移位寄存器单元(图中未示出)的第三时钟信号端CK和第三时钟信号线ECK连接以接收第三时钟信号，第K级移位寄存器单元的第四时钟信号端CK2和第四时钟信号线ECK2连接以接收第四时钟信号，第K+1级移位寄存器单元的第一时钟信号端CB和第三时钟信号线ECK连接以接收第一时钟信号，第K+1级移位寄存器单元的第二时钟信号端CB2和第四时钟信号线ECK2连接以接收第二时钟信号，第K+1级移位寄存器单元的第三时钟信号端CK(如图2B所示)和第一时钟信号线ECB连接以接收第三时钟信号，第K+1级移位寄存器单元的第四时钟信号端CK2和第二时钟信号线ECB2连接以接收第四时钟信号。需要注意的是，各级移位寄存器单元和时钟信号线的连接方式还可以采用本领域内的其他的连接方式，本公开的实施例对此不作限制。例如，第一级移位寄存器单元的输入端EI和触发信号线连接以接收触发信号作为输入信号，第二级移位寄存器单元的输入端和上一级移位寄存器单元(即，第一级移位寄存器单元)的输出端EOUT连接，其余各级移位寄存器单元的输入端的连接方式与此类似。下面以第K(K为大于等于2的偶数)级移位寄存器单元100aa的结构为例进行说明，本公开的实施例对此不作限制。
需要注意的是，本公开的实施例仅示意性地示出了四条时钟信号线(第一时钟信号线ECB、第二时钟信号线ECB2、第三时钟信号线ECK、第四时钟信号线ECK2)，本公开的实施例提供的显示基板还可以包括6条或8条等更多的时钟信号线，本公开的实施例对此不作限制。对应地，当时钟信号线的数量发生变化时，显示基板中移位寄存器单元100aa与时钟信号线的连接关系也相应地发生变化，具体内容可在本公开的实施例的基础上参考本领域的常规设计，在此不再赘述。
图4至图12为图3所示的显示基板的各层布线或者过孔的平面图。图13至图19为图3所示的显示基板中的多个膜层的平面图。图20A为图3的沿线A-B的剖视图。图20B为图3的沿线E1-F1、E2-F2、E3-F3、或E4-F4的剖视图。图21为图3所示的显示基板中各个连接走线、转接电极、导线的设置位置的示意图。具体地，图4为本公开至少一实施例提供的显示基板的有源层的平面图，图5为本公开至少一实施例提供的显示基板的第一导电层的平面图，图6为本公开至少一实施例提供的显示基板的第二导电层的平面图，图7为本公开至少一实施例提供的显示基板的贯穿第三绝缘层(第二层间绝缘层)的过孔的分布图，图8为本公开至少一实施例提供的显示基板的贯穿第一绝缘层的过孔的分布图，图9为本公开至少一实施例提供的显示基板的第三导电层的平面图，图10为本公开至少一实施例提供的显示基板的贯穿第四绝缘层(钝化层)的过孔的分布图，图11为本公开至少一实施例提供的显示基板的贯穿第五绝缘层(第一平坦化层)的过孔的分布图，图12为本公开至少一实施例提供的显示基板的第四导电层的平面图。图13为本公开至少一实施例提供的显示基板的半导体层LY0和贯穿层间绝缘层ILD(第一绝缘层IL1、第二绝缘层IL2和第三绝缘层IL3)的过孔的叠层示意图。图14为本公开至少一实施例提供的显示基板的贯穿层间绝缘层ILD的过孔和第一导电层LY1的叠层示意图。图15为本公开至少一实施例提供的显示基板的半导体层LY0、贯穿层间绝缘层ILD的过孔、以及第三导电 层LY3的叠层示意图。图16为本公开至少一实施例提供的显示基板的第一导电层LY1、贯穿层间绝缘层ILD的过孔、以及第三导电层LY3的叠层示意图。图17为本公开至少一实施例提供的显示基板的第二导电层LY2以及贯穿层第二间绝缘层ILD2的过孔的叠层示意图。图18为本公开至少一实施例提供的显示基板的第二导电层LY2、贯穿第二层间绝缘层ILD2的过孔、以及第三导电层LY3的叠层示意图。图19为本公开至少一实施例提供的显示基板的第三导电层LY3、第四绝缘层中的过孔、以及第五绝缘层中的过孔的叠层示意图。下面结合图3至图21对本公开至少一实施例提供的显示基板的单层结构以及层叠结构进行详细地介绍。
例如，参考图20A和图20B，该显示基板的绝缘层包括第一绝缘层IL1、第二绝缘层IL2、第三绝缘层IL3、第四绝缘层IL4、第五绝缘层IL5等。例如，第一绝缘层IL1(如图20A所示)位于图4所示的半导体层LY0和图5所示的第一导电层LY1之间，第二绝缘层IL2(如图20A所示)位于图5所示的第一导电层LY1和图6所示的第二导电层LY2之间(参见图20B)，第三绝缘层IL3(如图20A所示)位于图6所示的第二导电层LY2和图9所示的第三导电层LY3之间。第四绝缘层IL4(如图20B所示)位于图9所示的第三导电层LY3和图12所示的第四导电层LY4之间。图20B示出了第五绝缘层IL5。图7所示的过孔为贯穿第三绝缘层IL3的过孔。图8所示的过孔为贯穿第一绝缘层IL1、第二绝缘层IL2和第三绝缘层IL3中的一层或几层的过孔。图20B示出了第六绝缘层IL6。第六绝缘层IL6位于第四导电层LY4上，用于保护第四导电层LY4。
例如，第一绝缘层IL1包括第一栅绝缘层GI1，第二绝缘层IL2包括第一层间绝缘层ILD1，第三绝缘层IL3包括第二层间绝缘层ILD2，第四绝缘层IL4包括钝化层PVX，第五绝缘层IL5包括第一平坦化层PLN1，第六绝缘层IL6包括第二平坦化层PLN2。
例如，第一绝缘层IL1、第二绝缘层IL2、第三绝缘层IL3、第四绝缘层IL4、第五绝缘层IL5和第六绝缘层IL6均采用绝缘材料制成。例如，第一绝缘层IL1、第二绝缘层IL2、第三绝缘层IL3和第四绝缘层IL4的材料可以包括例如SiNx、SiOx、SiNxOy等无机绝缘材料，或其它适合的材料；例如第五绝缘层IL5和第六绝缘层IL6的材料包括有机树脂等有机绝缘材料，或其它适合的材料，本公开的实施例对此不作限定。例如，第五绝缘层IL5和第六绝缘层IL6的厚度较大，第五绝缘层IL5和第六绝缘层IL6中每个的厚度大于第一绝缘层IL1、第二绝缘层IL2、第三绝缘层IL3和第四绝缘层IL4中每个的厚度。
需要注意的是，图3所示的显示基板以发光控制驱动电路阵列中的第K级移位寄存器单元和与其连接的第一电源线、第二电源线以及时钟信号线的布局设计为例进行说明，其余各级移位寄存器单元的布局实施方式可以参考图3中所示的布局方式，在此不再赘述，当然也可以采用其他适合的布局方式，本公开的实施例对此不作限制。当然，其余各个发光控制驱动电路阵列的各级移位寄存器单元也可以参考图3中所示的布局方式，或者也可以采用其他适合的布局方式，本公开的实施例对此不作限制。
下面结合图3至图21对本公开至少一实施例提供的显示基板进行详细地介绍。在描述显示基板的布局图时，各个晶体管可能会用其简称以简化描述。
例如，图3中所示的移位寄存器单元100aa的晶体管T1至晶体管T14的有源层A1-A14可以参考图4所示的半导体层LY0的图形。半导体层LY0可采用半导体材料图案化形成。例如，如图4所示， 根据实际不同需要，该半导体层LY0可以包括短棒状的部分或包括具有弯曲或弯折的形状的部分，以用于制作上述晶体管T1至晶体管T14的有源层A1-A14。各晶体管的有源层可包括源极区域、漏极区域以及位于源极区域和漏极区域之间的沟道区。例如，沟道区具有半导体特性；源极区域和漏极区域在沟道区的两侧，并且可掺杂有杂质，并因此具有导电性。例如，该源极区域为有源层的一部分，与该源极区域接触的金属电极(例如，位于第三导电层LY3)对应于晶体管的源极(或叫做第一极)；漏极区域为有源层的一部分，与该漏极区域接触的金属电极(例如，位于第三导电层LY3)对应于晶体管的漏极(或叫做第二极)。例如，源极区域通过贯穿第一绝缘层IL1、第二绝缘层IL2以及第三绝缘层IL3的过孔与其对应的金属电极(源极)连接，漏极区域通过贯穿第一绝缘层IL1、第二绝缘层IL2以及第三绝缘层IL3的过孔与其对应的金属电极(漏极)连接。例如，在本公开的实施例中，位于第三导电层的转接电极即为金属电极。转接电极的至少一部分用来充当晶体管的源极或漏极。
例如，半导体层LY0的材料可以包括氧化物半导体、有机半导体或非晶硅、多晶硅等，例如，氧化物半导体包括金属氧化物半导体(例如氧化铟镓锌(IGZO))，多晶硅包括低温多晶硅或者高温多晶硅等，本公开的实施例对此不作限定。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域，本公开的实施例对此不作限制。
需要注意的是，在另一些示例中，各个晶体管的第一极和第二极也可以位于其他导电层，通过位于其和半导体层之间的绝缘层中的过孔与其对应的有源层连接，本公开的实施例对此不作限制。
图5示出了该显示基板的第一导电层LY1，第一导电层LY1设置在第一绝缘层IL1上，从而与半导体层LY0绝缘。例如，第一导电层LY1可包括第一电容C1至第四电容C4的第二极板C1b、C2b、C3b、C4b以及晶体管T1至晶体管T14的栅极G1-G14、各条连接走线(例如，连接走线L1-L5)以及用于与第三导电层LY3中的信号线或转接电极等连接的导线(例如，导线M1、导线M2和导线M3)。导线M1、导线M2和导线M3均为独立的图形。如图5所示，晶体管T1至晶体管T14的栅极G1-G14为用圆形或椭圆形虚线圈起来的部分，即为各个晶体管的半导体层结构与第一导电层LY1中的电极或走线交叠的部分。
如图5所示，第一电容C1至第四电容C4的第二极板C1b、C2b、C3b、C4b分别包括第一电容C1至第四电容C4的第二极板C1b的第一部分C1b1、C2b1、C3b1、C4b1。
例如，如图5所示，晶体管T5的栅极G5、连接走线L1、第一电容C1的第二极板C1b的第一部分C1b1、连接走线L2、以及晶体管T4的栅极G4相连并一体形成。例如，如图5所示，第四电容C4的第二极板C4b的第一部分C4b1、连接走线L3、以及晶体管T11的栅极G11相连并一体形成。例如，如图5所示，连接走线L4、晶体管T12的栅极G12、以及第三电容C3的第二极板C3b的第一部分C3b1相连并一体形成。例如，如图5所示，连接走线L5、晶体管T2的栅极G2、以及晶体管T8的栅极G8一体形成。
图6示出了该显示基板的第二导电层LY2，第二导电层LY2包括第一电容C1至第四电容C4的第一极板C1a、C2a、C3a、C4a以及输出端EOUT1。第一电容C1至第四电容C4的第一极板C1a、C2a、C3a、C4a包括第一极板C1a的第一部分C1a1、第一极板C2a的第一部分C2a1、第一极板C3a的第一部分C3a1、第一极板C4a的第一部分C4a1。
需要说明的是，在本公开的实施例中，位于第二导电层LY2的输出端EOUT1可用于向显示区的 像素单元提供输出信号；而在本公开的其他一些实施例中，移位寄存器单元100aa的输出端EOUT1的输出信号也可由位于其他层中的电极提供，也即，输出端EOUT1也可设置在不同于第二导电层LY2的其他层中，例如可以设置在第一导电层LY1中，本公开的实施例对此不作限制。
图7示出了该显示基板的第三绝缘层IL3中的过孔分布。图7所示的过孔为贯穿第三绝缘层IL3的过孔。
图8示出了该显示基板的第二绝缘层IL2中的过孔分布。图8所示的过孔为贯穿第三绝缘层IL3、第二绝缘层IL2、第一绝缘层IL1的过孔以及贯穿第三绝缘层IL3和第二绝缘层IL2的过孔。
图9示出了该显示基板的第三导电层LY3，第三导电层LY3包括多条信号线(例如，第一时钟信号线ECB、第二时钟信号线ECB2、第三时钟信号线ECK、第四时钟信号线ECK2)、第一电源线VGL、第二电源线VGH等。图9示出了第一时钟信号线ECB的第一部分ECBa、第二时钟信号线ECB2的第一部分ECB2a、第三时钟信号线ECK的第一部分ECKa、第四时钟信号线ECK2的第一部分ECK2a、第一电源线VGL的第一部分VGLa、第二电源线VGH的第一部分VGHa、第一电容C1的第二极板C1b的第二部分C1b2、第二电容C2的第二极板C2b的第二部分C2b2、第三电容C3的第二极板C3b的第二部分C3b2、以及第四电容C4的第二极板C4b的第二部分C4b2。需要注意的是，该第三导电层LY3还包括连接各个晶体管、电容以及信号线之间的转接电极ET1-ET14、转接电极ET5a、转接电极ETI、转接电极ETa、转接电极ETb、转接电极ETc以及转接电极ETd等。例如，参考图3、图9、以及图12，转接电极ETI可以通过过孔结构与位于第四导电层LY4的输入端EI连接。输入端EI也可称作输入线。
需要说明的是，在本公开的其他一些实施例中，移位寄存器单元100aa的输入端EI也可以位于其他层中，例如可以位于第三导电层LY3中以与转接电极ETI直接连接。例如，转接电极ETI可以与输入端EI一体化形成，例如转接电极ETI包括输入端EI，本公开的实施例对此不作限制。
图10示出了该显示基板的第四绝缘层IL4(钝化层PVX)中的过孔分布。
图11示出了该显示基板的第五绝缘层IL5(第一平坦化层PLN1)中的过孔分布。如图10和图11所示，第五绝缘层IL5(第一平坦化层PLN1)中的过孔的面积大于对应位置处的第四绝缘层IL4(钝化层PVX)中的过孔的面积，以利于实现第三导电层LY3中的元件和第四导电层LY4中的元件的连接，并减小电容的相对的两个极板之间的距离，以利于增大电容量。参照图20B，贯穿第五绝缘层IL5的过孔H0的面积大于贯穿第四绝缘层IL4的过孔H22的面积，以利于减小第一极板Ca与第二极板Cb之间的距离，增大电容量。进一步的，在电容采用并联方式的情况下，可利于减小第一极板Ca的第二部分Ca2与第二极板Cb的第二部分Cb2之间的距离，以增大电容量。
图12示出了该显示基板的第四导电层LY4。第四导电层LY4包括第一电容C1至第四电容C4的第一极板的第二部分C1a2、C2a2、C3a2和C4a2、第一时钟信号线ECB的第二部分ECBb、第二时钟信号线ECB2的第二部分ECB2b、第三时钟信号线ECK的第二部分ECKb、第四时钟信号线ECK2的第二部分ECK2b、第一电源线VGL的第二部分VGLb以及第二电源线VGH的第二部分VGHb、输入端EI、以及输出端EOUT2。例如，输出端EOUT2可用于与下一级的移位寄存器单元的输入端EI相连，以为下一级的移位寄存器单元的输入端EI提供输入信号。需要说明的是，输出端EOUT2也可以位于其他导电层。输入端EI用以接收上一级移位寄存器单元的输出端的输出信号作为本级移位寄存器单元 的输入端的输入信号。
参考图3、图9、图12、图15和图19，转接电极ET5与晶体管T5的第二极相连并一体形成，晶体管T5的第二极通过过孔与晶体管T5的有源层A5相连。换句话说，转接电极ET5的至少一部分充当晶体管T5的第二极。转接电极ET5通过过孔与晶体管T5的有源层A5相连。第一电容C1的第二极C1b的第二部分C1b2通过第一过孔H1与晶体管T5的有源层A5相连，第一电容C1的第二极C1b的第二部分C1b2通过第二过孔H2与晶体管T5的栅极G5相连。第一电容C1的第二极C1b的第二部分C1b2也可称作导电部CP。第一晶体管的第一极通过第一过孔H1与第一晶体管T5的有源层相连。
参考图3、图9、图12、图15和图19，晶体管T11的第二极与转接电极ET11相连并一体形成，晶体管T11的第二极通过过孔与晶体管T11的有源层A11相连。转接电极ET11通过过孔与晶体管T11的有源层A11相连。换句话说，转接电极ET11的至少一部分充当晶体管T11的第二极。转接电极ET11、转接电极ET5、以及第一电容C1的第二极C1b的第二部分C1b2相连并一体形成。
参考图3、图9、图12、图15和图19，输入端EI通过过孔与转接电极ETI相连，转接电极ETI与晶体管T12的第一极相连并一体形成，换句话说，转接电极ETI的至少一部分充当晶体管T12的第一极。晶体管T12的第一极通过过孔与有源层A12相连。转接电极ET12与晶体管T12的第二极相连并一体形成并与晶体管T1的第一极相连并一体形成，换句话说，转接电极ET12的至少一部分充当晶体管T12的第二极并且转接电极ET12的至少一部分充当晶体管T1的第一极。晶体管T1的第一极通过过孔与晶体管T1的有源层A1相连，转接电极ET1与晶体管T1的第二极相连并一体形成并与晶体管T13的第二极相连并一体形成，换句话说，转接电极ET1的至少一部分充当晶体管T1的第二极并且转接电极ET1的至少一部分充当晶体管T13的第二极。
参考图3、图5、图14和图16，转接电极ET1通过过孔与连接走线L5相连。
参考图3、图5、图14和图16，导线M1的一端通过过孔与第一时钟信号线ECB的第一部分ECBa相连，导线M1的另一端通过过孔与转接电极ET6相连，转接电极ET6的另一端通过过孔与晶体管T4的有源层A4相连。转接电极ET6与晶体管T6的第一极相连并一体形成并与晶体管T4的第一极相连并一体形成。换句话说，转接电极ET6的至少一部分充当晶体管T6的第一极并且转接电极ET6的至少一部分充当晶体管T4的第一极。转接电极ET4通过过孔与晶体管T4的有源层A4相连，转接电极ET4与晶体管T4的第二极相连并一体形成。换句话说，转接电极ET4的至少一部分充当晶体管T4的第二极。转接电极ETd通过过孔与晶体管T6的有源层A6和晶体管T7的有源层A7相连，转接电极ETd与第四电容C4的第二极板C4b的第二部分C4b2相连并一体形成，第四电容C4的第二极板C4b的第二部分C4b2与晶体管T6的第一极相连并一体形成并与晶体管T7的第一极相连并一体形成。换句话说，第四电容C4的第二极板C4b的第二部分C4b2的至少一部分充当晶体管T6的第一极并且第四电容C4的第二极板C4b的第二部分C4b2的至少一部分充当晶体管T7的第一极。参考图18，第一电极C1的第二极板C1b的第二部分C1b2通过过孔与转接电极ET4相连。
参考图3、图5、图9、图14、图15和图16，转接电极ETb与第二电源线VGH相连并一体形成。导线M2的一端通过过孔与转接电极ETb相连，导线M2的另一端通过过孔与转接电极ET8相连。转接电极ET8与晶体管T8的第一极相连并一体形成并与晶体管T11的第一极相连并一体形成。换句话说，转接电极ET8的至少一部分充当晶体管T8的第一极并且转接电极ET8的至少一部分充当晶体管 T11的第一极。
参考图3、图5、图9、图14、图15和图16，导线M3的一端与第一电源线VGL相连；导线M3的另一端与转接电极ET3相连，进而与晶体管T14的栅极G14相连，从而使得晶体管T14的栅极G14连接至第一电源线VGL。转接电极ET3与晶体管T3的第二极相连并一体形成。换句话说，转接电极ET3的至少一部分充当晶体管T3的第二极。
参考图3、图5、图9、图14、图15和图16，转接电极ET7的一端通过过孔与晶体管T9的栅极G9相连，参考图13和图15，转接电极ET7的另一端与晶体管T7的有源层A7相连，转接电极ET7的再一端通过过孔与晶体管T8的有源层A8相连，转接电极ET7与晶体管T7的第二极相连并一体形成并与晶体管T8的第二极相连并一体形成。换句话说，转接电极ET7的至少一部分充当晶体管T7的第二极并且转接电极ET7的至少一部分充当晶体管T8的第二极。
参考图3、图5、图9、图14、图15和图16，转接电极ET13通过过孔与晶体管T4的栅极G4相连，转接电极ET13与晶体管T13的第一极相连并一体形成。换句话说，转接电极ET13的至少一部分充当晶体管T13的第一极。例如，转接电极ET13的第一端通过过孔与晶体管T4的栅极G4相连。
参考图3、图5、图9、图14、图15和图16，晶体管T12的栅极G12通过过孔与第二时钟信号线ECB2的第一部分ECB2a相连，晶体管T1的栅极G1通过过孔与第三时钟信号线ECK的第一部分ECKa相连，连接走线M1通过过孔与第一时钟信号线ECB的第一部分ECBa相连，晶体管T13的栅极G13通过过孔与第一电源线VGL的第一部分VGLa相连。转接电极ETc与第一电源线VGL的第一部分VGLa相连并一体形成。转接电极ETc与晶体管T10的第一极相连并一体形成。换句话说，转接电极ETc的至少一部分充当晶体管T10的第一极。转接电极ET10与晶体管T10的第二极相连并一体形成并与晶体管T9的第一极相连并一体形成。换句话说，转接电极ET10的至少一部分充当晶体管T10的第二极并且转接电极ET10的至少一部分充当晶体管T9的第一极。转接电极ET9与第三电容C3的第二极C3b的第二部分C3b2相连并一体形成。转接电极ET9与晶体管T9的第二极相连并一体形成。换句话说，转接电极ET9的至少一部分充当晶体管T9的第二极。第二部分C3b2(转接电极ET9)通过过孔与第三电容C3的第二极C3b的第一部分C3b1相连，进而连接至第二时钟信号线ECB2。
参考图3、图5、图9、图14、图15和图16，转接电极ET14的一端通过过孔与晶体管T3的有源层A3相连，转接电极ET14的另一端通过过孔与晶体管T2的有源层A2以及晶体管T14的有源层A14相连。转接电极ET14与晶体管T2的第二极相连并一体形成并与晶体管T14的第一极相连并一体形成。换句话说，转接电极ET14的至少一部分充当晶体管T2的第二极并且转接电极ET14的至少一部分充当晶体管T14的第一极。
参考图3、图5、图9、图14、图15和图16，转接电极ET2的一端通过过孔与晶体管T2的有源层A2相连，转接电极ET2的另一端通过过孔与晶体管T3的栅极G3相连，再通过栅极G3与第三时钟信号线ECK的第一部分ECKa相连。转接电极ET2与晶体管T2的第一极相连并一体形成。换句话说，转接电极ET2的至少一部分充当晶体管T2的第一极。
参考图3、图5、图9、图14、图15和图16，转接电极ET3的一端与晶体管T14的栅极G14相连，转接电极ET3的另一端与晶体管T1的栅极G1相连，并进而连接至第一电源线VGL的第一部分VGLa。
参考图3、图5、图9、图14、图15和图16，转接电极ETa通过过孔与晶体管T6的栅极G6相连，转接电极ETa通过过孔与晶体管T14的有源层A14相连，转接电极ETa与晶体管T14的第二极相连并一体形成。换句话说，转接电极ETa的至少一部分充当晶体管T14的第二极。
参考图3、图5、图9、图14、图15和图16，第二电容C2的第二极板C2b的第二部分C2b2通过过孔与晶体管T10的栅极G10相连。
参考图3、图17和图18，第一电容C1的第一极板C1a的第一部分C1a1通过过孔与转接电极ET4相连。
参考图3、图17和图18，第二电容C2的第一极板C2a的第一部分C2a1通过过孔与转接电极ETc相连。
参考图3、图17和图18，第三电容C3的第一极板C3a的第一部分C3a1通过过孔与转接电极ET7相连。
参考图3、图17和图18，第四电容C4的第一极板C4a的第一部分C4a1通过过孔与转接电极ETa相连。
例如，参照图3至图19、以及图21、以及后续提及的表一，转接电极ET1或者连接走线L5可作为第一隔离节点P31，转接电极ET13或晶体管T4的栅极G4或第一电容C1的第二极板可作为第一输入节点P11，转接电极ET14可作为第二隔离节点P32，转接电极ETa可作为第三输入节点P13，转接电极ET7可作为第二节点P2，转接电极ET5(转接电极ET11)、第二电容C2的第二极板C2b或晶体管T10的栅极G10可作为第一节点P1，转接电极ETd可作为第二输入节点P12。
例如，输出端EOUT1可以具有分别向显示区102的相邻两行的像素单元103提供输出信号的两个端部，例如该两个端部在第一方向Y上并排设置。输出端EOUT2用于向下一级移位寄存器单元提供输出信号以作为下一级移位寄存器单元的输入信号，例如该输出端EOUT2可以与下一级移位寄存器单元的输入端EI连接。
如图2B和图3所示，电荷泵电路11包括第一电容C1、第一晶体管T5和第二电容C2。第一电容C1的第一极板与第一时钟信号线ECB相连，第一电容C1的第二极板与第一晶体管T5的第一极相连。第二电容C2的第一极板与第一电源线VGL相连，第二电容C2的第二极板与第一晶体管T5的第二极相连，第一晶体管T5的栅极与第一晶体管T5的第一极或第二极相连。对于电荷泵电路11，可参照之前描述。
如图3所示，第一电容C1在衬底基板10上的正投影和第一晶体管T5在衬底基板10上的正投影相邻，并且第二电容C2在衬底基板10上的正投影与第一晶体管T5在衬底基板10上的正投影相邻。在本公开的实施例中，第一电容C1和第一晶体管T5相邻，并且第二电容C2和第一晶体管T5相邻设置，利于移位寄存器单元的布局，利于减小显示基板的边框。
如图3所示，第一电容C1在衬底基板10上的正投影和第一晶体管T5在衬底基板10上的正投影部分交叠，并且第二电容C2在衬底基板10上的正投影与第一晶体管T5在衬底基板10上的正投影部分交叠。
在本公开的实施例中，元件相邻设置是指元件之间不再设置其他元件。换句话说，元件相邻设置是指元件直接相连，而不是通过其他元件间接相连。本公开的实施例的元件包括电容和晶体管。在本 公开的实施例中，元件A和元件B相邻是指该两个元件之间不具有其他的元件A和其他的元件B。例如电容和晶体管相邻是指该电容和晶体管之间不具有其他的电容并且不具有其他的晶体管。例如，元件A和元件B相邻是指该两个元件之间不具有其他的电容也不具有其他的晶体管。例如，元件A包括电容或晶体管，元件B包括电容或晶体管。
例如，在本公开的实施例中，将第一电容C1和第二电容C2排布于第一晶体管T5的周围。该排布方式可提高排版的密度，利于窄边框。例如，在一些实施例中，第一电容C1和第二电容C2均位于第一晶体管T5的左边。例如，在一些实施例中，第一电容C1和第二电容C2均位于第一晶体管T5的右边。例如，在一些实施例中，第一电容C1和第二电容C2之一位于第一晶体管T5的左边，第一电容C1和第二电容C2之另一位于第一晶体管T5的右边。例如，在一些实施例中，第一电容C1和第二电容C2之一位于第一晶体管T5的上边，第一电容C1和第二电容C2之另一位于第一晶体管T5的下边。
例如，如图15所示，为了使得电荷泵电路的排布更紧凑，减小显示基板的边框，第一电容C1的第二极板C1b在衬底基板10上的正投影和第一晶体管T5的第一极在衬底基板10上的正投影部分交叠，并且第二电容C2的第二极板C2b在衬底基板10上的正投影与第一晶体管T5的第二极在衬底基板10上的正投影部分交叠。
例如，如图3和图15所示，第一电容C1的第二极板C1b的第二部分C1b2与第一晶体管T5的有源层A5相连，第二电容C2的第二极板C2b的第二部分C2b2与第一晶体管T5的有源层A5相连。第一电容C1的第二极板C1b的第二部分C1b2也作为第一晶体管T5的第一极，第二电容C2的第二极板C2b的第二部分C2b2也作为第一晶体管T5的第二极。换句话说，第一电容C1的第二极板C1b的第二部分C1b2与第一晶体管T5的第一极相连并一体形成，第二电容C2的第二极板C2b的第二部分C2b2与第一晶体管T5的第二极相连并一体形成。
例如，为了更有效地给第一节点P1复位，使得去噪模块在保持阶段持续开启，第一电容C1的电容值大于或等于第二电容C2的电容值。进一步例如，第一电容C1的电容值小于或等于第二电容C2的电容值的十倍。在一些实施例中，为了兼顾窄边框和给第一节点P1的复位效果，第一电容C1的电容值为第二电容C2的电容值的四至六倍。
例如，第二电容C2的电容值的范围为0.01pF-2pF，该数值范围内的第二电容C2利于第一电容C1和第二电容C2的电容值的设置，利于实现第一电容C1和第二电容C2的功能，并利于实现窄边框。
例如，如图3所示，第一时钟信号线ECB在衬底基板10上沿第一方向Y延伸，并且第一电容C1、第一晶体管T5和第二电容C2在第二方向X上依次排布。例如，第一方向Y与第二方向X相交。例如，第一方向Y和第二方向X为平行于衬底基板10的主表面的方向，衬底基板10的主表面为制作各种膜层的表面。
例如，如图3所示，第一晶体管T5的栅极与第一晶体管T5的第一极通过导电部CP相连以形成二极管结构。如图15所示，导电部CP通过第一过孔H1与第一晶体管T5的有源层A5相连。如图3所示，第一晶体管T5的沟道CNL在衬底基板10上的正投影与第一过孔H1在衬底基板10上的正投影不交叠，以避免形成过孔的过程中对第一晶体管T5的沟道产生破坏作用，可有效实现二极管连接的第一晶体管T5的电流单向流通功能，有效去除保持阶段的噪声干扰。例如，如图16所示，导电部CP 为第一电容C1的第二极板C1b的第二部分C1b2。
例如，如图3和图16所示，导电部CP通过第二过孔H2与第一晶体管T5的栅极G5相连。如图3所示，为避免形成第二过孔H2的过程中对第一晶体管T5的沟道CNL产生影响，第一晶体管T5的沟道CNL在衬底基板10上的正投影与第二过孔H2在衬底基板10上的正投影不交叠。
例如，如图20A所示，第二过孔H2在垂直于衬底基板10的方向上的高度h2小于第一过孔H1在垂直于衬底基板10的方向上的高度h1。
例如，如图20A所示，第一过孔H1贯穿第三绝缘层IL3、第二绝缘层IL2、和第一绝缘层IL1，第二过孔H2贯穿第三绝缘层IL3和第二绝缘层IL2。
例如，如图3和图20A所示，第一晶体管T5的沟道CNL在衬底基板10上的正投影与第一晶体管T5的栅极G5在衬底基板10上的正投影部分交叠。有源层A5的被栅极G5覆盖的部分即为沟道CNL。第一晶体管T5的沟道CNL包括第一沟道CNL1和第二沟道CNL2，图20A示出了与第一晶体管T5的第一沟道CNL1交叠的第一栅极G51和与第一晶体管T5的第二沟道CNL2交叠的第二栅极G52。如图5所示，第一栅极G51和第二栅极G52均与连接走线L1相连并一体形成。
例如，如图3和图15所示，第二晶体管T4在衬底基板10上的正投影与第一电容C1在衬底基板10上的正投影部分交叠。第二晶体管T4在衬底基板10上的正投影与第一电容C1在衬底基板10上的正投影相邻。第二晶体管T4与第一电容C1相邻设置，以利于减小电荷泵电路的占用面积，利于减小显示基板的边框。
例如，如图3和图15所示，第二晶体管T4、第一电容C1、第一晶体管T5、以及第二电容C2在第二方向X上依次设置，以利于电荷泵电路与其他结构的连接和其他结构的设置，利于提高排版密度，利于减小显示基板的边框。
例如，如图3所示，第二时钟信号线ECB2在衬底基板10上沿第一方向Y延伸，第三时钟信号线ECK在衬底基板10上沿第一方向Y延伸，第四时钟信号线ECK2在衬底基板10上沿第一方向Y延伸，第一电源线VGL在衬底基板10上沿第一方向Y延伸，并且，第二电源线VGH在衬底基板10上沿第一方向Y延伸。
如图11至图12所示，第五绝缘层IL5(第一平坦化层PLN1)中的过孔H01、H02、H03和H04分别与第一电容C1至第四电容C4的第一极板的第二部分C1a2、C2a2、C3a2和C4a2的形状大致相同且面积大致相等，可以使得第一电容C1至第四电容C4的第一极板的第二部分在衬底基板上的正投影完全落入第五绝缘层IL5中的过孔在衬底基板上的正投影内，以利于减小电容的极板之间的距离，增大电容，并利于第一电容C1至第四电容C4的第一极板的第二部分与转接电极ET(参考图20B)的连接。例如，第一电容C1至第四电容C4的第一极板的第二部分和第一电容C1至第四电容C4的第二极板的第二部分之间的介电层不包括第五绝缘层IL5(参考图20B)。
在本公开的实施例中，参考图3、图9至图12，信号线可以采用位于不同层的两个部分并联的方式形式，以减小信号线的电阻，第一部分ECBa和第二部分ECBb并联以构成第一时钟信号线ECB，第一部分ECB2a和第二部分ECB2b并联以构成第二时钟信号线ECB2，第一部分ECKa和第二部分ECKb并联以构成第三时钟信号线ECK，第一部分ECK2a和第二部分ECK2b并联以构成第四时钟信号线ECK2。第一部分VGLa和第二部分VGLb并联以构成第一电源线VGL，第一部分VGHa和第二 部分VGHb并联以构成第二电源线VGH。信号线的两个部分可通过在对应位置设置贯穿位于该两个部分之间的绝缘层的过孔来实现连接。
如图3至图19所示，多条信号线、第一电源线VGL、第二电源线VGH、通过图8所示的至少一个过孔与其余各层中需要与其连接的晶体管以及电容等连接，各个晶体管、电容之间也可通过至少一个过孔连接，或通过转接电极桥接，在此不再赘述。
例如，第一导电层LY1、第二导电层LY2、第三导电层LY3和第四导电层LY4的材料包括金属。例如，第三导电层LY3的材料可以包括钛、钛合金、铝、铝合金、铜、铜合金或其他任意适合的复合材料，本公开的实施例对此不作限定。例如，第四导电层LY4的材料可以与第三导电层LY3的材料的选择范围相同，但不限于此。例如，第一导电层LY1的材料包括钼、镍、钼合金、镍合金等。例如，第二导电层LY2的材料与第一导电层LY1的材料的选择范围相同，但不限于此。
例如，如图3和图4所示，为了便于移位寄存器单元的布置，减小移位寄存器单元的尺寸，减小显示基板的边框，在至少一个示例中，晶体管T9的有源层A9与晶体管T10的有源层A10为一体结构，晶体管T2的有源层A2与晶体管T14的有源层A14为一体结构，晶体管T6的有源层A6与晶体管T7的有源层A7为一体结构。当然，在其他的实施例中，晶体管的有源层也可以分离设置。
例如，如图3和图5所示，在至少一个示例中，晶体管T12的栅极G12与第三电容C3的第二极板C3b的第一部分C3b1通过连接走线L4相连。晶体管T12的栅极G12、第三电容C3的第二极板C3b的第一部分C3b1、以及连接走线L4为一体结构。晶体管T11的栅极G11和第四电容C4的第二极板C4b的第一部分C4b1通过连接走线L3相连，例如，晶体管T11的栅极G11、连接走线L3和第四电容C4的第二极板C4b的第一部分C4b1为一体结构。
例如，如图3和图5所示，在至少一个示例中，第四控制晶体管T2包括第一栅极G21和第二栅极G22，第一栅极G21和第二栅极G22均连接至连接走线L5，连接走线L5位于第四控制晶体管T2的栅极G2的一侧，并沿第二方向X延伸，连接走线L5与第七控制晶体管T8的栅极G8相连。第四控制晶体管T2的栅极G2形成“U”字形结构，进而提升第四控制晶体管T2的稳定性，改善第四控制晶体管T2的性能。例如，如图4所示，晶体管T8的有源层A8为“U”字形结构，从而，晶体管T8为双栅结构。例如，如图4所示，晶体管T11的有源层A11为“U”字形结构，从而，晶体管T11为双栅结构。
当然，也可以是该第四控制晶体管T2的有源层为“U”字形结构，第四控制晶体管T2的栅极为与该“U”字形的有源层交叠的“一”字形结构，从而形成双栅结构，只要不影响其他结构的排布以及过多增加移位寄存器单元的宽度即可，本公开的实施例对此不作限制。需要注意的是，也可以是单个栅极与第四控制晶体管T2的有源层重叠，本公开的实施例对此不作限制。
例如，如图3和图5所示，在至少一个示例中，导线M1沿第二方向X延伸，导线M2沿第一方向Y延伸，导线M3沿第二方向X延伸。
例如，如图3和图5所示，在至少一个示例中，晶体管T11的栅极G11通过连接走线L3与第四电容C4的第二极板C4b的第一部分C4b1相连，晶体管T11的栅极G11、连接走线L3和第四电容C4的第二极板C4b的第一部分C4b1为一体结构。
例如，如图3和图5所示，在至少一个示例中，晶体管T4的栅极G4通过连接走线L2与第一电 容的第一极板C1b的第一部分C1b1相连，晶体管T4的栅极G4、连接走线L2与第一电容的第一极板C1b的第一部分C1b1为一体结构。进一步例如，晶体管T4的栅极G4、晶体管T5的栅极、连接走线L2、连接走线L1和第一电容的第一极板C1b的第一部分C1b1为一体结构。
例如，如图3和图5所示，在至少一个示例中，第二输出晶体管T9的栅极为梳状结构，以提升第二输出晶体管T9的稳定性。
例如，如图3和图4所示，第二晶体管T4的有源层A4的延伸方向与第一晶体管T5的有源层A5的延伸方向相交，以利于第一晶体管T5和第二晶体管T4的放置，利于减小电荷泵电路的占用面积，利于提高排版密度，减小移位寄存器单元的尺寸以减小边框。例如，如图4所示，第二晶体管T4的有源层A4沿第一方向Y延伸，第一晶体管T5的有源层A5沿第二方向X延伸。
例如，如图3和图4所示，为了减小移位寄存器单元的尺寸，第二控制晶体管T1的有源层A1沿第一方向Y延伸，第一控制晶体管T12的有源层A12沿第一方向Y延伸，第一隔离晶体管T13的有源层A13沿第一方向Y延伸，有源层A1位于有源层A12和有源层A13之间。例如，有源层A12、有源层A1和有源层A13沿第一方向Y依次排布。例如，有源层A12、有源层A1和有源层A13位于同一直线上。
例如，如图3和图4所示，为了提高排版密度，有源层A2、有源层A14、有源层A6和有源层A7均沿第二方向X延伸，有源层A3和有源层A4均沿第一方向Y延伸。
例如，参考图3、图10、图11和图19，过孔H041、过孔H031、过孔H021和过孔H011分别为贯穿第四绝缘层IL4(钝化层PVX)的过孔，过孔H04、过孔H03、过孔H02和过孔H01分别为贯穿第五绝缘层IL5(第一平坦化层PLN1)的过孔，如图19所示，过孔H041和过孔H04交叠且贯通，过孔H031和过孔H03交叠且贯通，过孔H021和过孔H02交叠且贯通，过孔H011和过孔H01交叠且贯通，以利于减小电容的极板之间的距离，增大电容量，并利于电容的极板的设置。
例如，在本公开的一些实施例中，第一电容C1、第二电容C2、第三电容C3和第四电容C4采用相同结构，均采用三个电容并联的结构。如图20B所示，电容C包括第一极板Ca和第二极板Cb，第一极板Ca包括第一部分Ca1和第二部分Ca2，第二极板Cb包括第一部分Cb1和第二部分Cb2，第一部分Ca1和第二部分Ca2通过转接电极ET相连，第一部分Cb1和第二部分Cb2相连。如图20B所示，在第三方向Z上，第一部分Cb1、第一部分Ca1、第二部分Cb2和第二部分Ca2依次排列。第三方向Z为垂直于衬底基板10的方向。第三方向Z垂直于第一方向Y，并且垂直于第二方向X。例如，第一方向Y和第二方向X为平行于衬底基板的主表面的方向，第三方向Z为垂直于衬底基板的主表面的方向，衬底基板的主表面可为制作各种元件的表面。第一部分Cb1和第一部分Ca1彼此正对形成一个电容，第一部分Ca1和第二部分Cb2彼此正对形成一个电容，第二部分Cb2和第二部分Ca2彼此正对形成一个电容。这种设置方式，利于增大电容量，减小电容的占用面积，利于实现显示基板的窄边框。需要说明的是，图20B只是示意性的示出三个并联的电容的结构，电容的极板之间设置的绝缘层可以包括至少一个绝缘层。
如图20B所示，第二部分Ca2通过贯穿第四绝缘层IL4的过孔H22与转接电极ET相连，转接电极ET通过贯穿第三绝缘层IL3的过孔H21与第一部分Ca1相连，第二部分Cb2通过贯穿第三绝缘层IL3和第二绝缘层IL2的过孔H23与第一部分Cb1相连。
参考图17、图18和图20B，对于第一电容C1，图20B所示的第一极板Ca即为第一极板C1a，图20B所示的第一部分Ca1即为第一部分C1a1。参考图12和图20B，图20B所示的第二部分Ca2即为第二部分C1a2，图20B所示的第二极板Cb即为第二极板C1b，图20B所示的第一部分Cb1即为第一部分C1b1，图20B所示的第二部分Cb2即为第二部分C1b2，图20B所示的转接电极ET即为转接电极ET4，也可被称作转接部或第一转接部。
参考图17、图18和图20B，对于第二电容C2，图20B所示的第一极板Ca即为第一极板C2a，图20B所示的第一部分Ca1即为第一部分C2a1，图20B所示的第二部分Ca2即为第二部分C2a2。参考图12和图20B，图20B所示的第二极板Cb即为第二极板C2b，图20B所示的第一部分Cb1即为第一部分C2b1，图20B所示的第二部分Cb2即为第二部分C2b2，图20B所示的转接电极ET即为转接电极ETc，也可被称作转接部或第二转接部。
参考图17、图18和图20B，对于第三电容C3，图20B所示的第一极板Ca即为第一极板C3a，图20B所示的第一部分Ca1即为第一部分C3a1，图20B所示的第二部分Ca2即为第二部分C3a2。参考图12和图20B，图20B所示的第二极板Cb即为第二极板C3b，图20B所示的第一部分Cb1即为第一部分C3b1，图20B所示的第二部分Cb2即为第二部分C3b2，图20B所示的转接电极ET即为转接电极ET7，也可被称作转接部或第三转接部。
参考图17、图18和图20B，对于第四电容C4，图20B所示的第一极板Ca即为第一极板C4a，图20B所示的第一部分Ca1即为第一部分C4a1，图20B所示的第二部分Ca2即为第二部分C4a2。参考图12和图20B，图20B所示的第二极板Cb即为第二极板C4b，图20B所示的第一部分Cb1即为第一部分C4b1，图20B所示的第二部分Cb2即为第二部分C4b2，图20B所示的转接电极ET即为转接电极ETa，也可被称作转接部或第四转接部。
例如，如图20B所示，第一电容C1、第二电容C2、第三电容C3、第四电容C4至少之一为三个电容并联的结构，三个电容并联的结构包括第二极板的第一部分、第二极板的第二部分、第一极板的第一部分、以及第一极板的第二部分，第二极板的第一部分和第二极板的第二部分通过第三过孔(过孔H23)相连，第一极板的第一部分和第一极板的第二部分通过转接电极ET相连，第三过孔(过孔H23)和转接电极ET分别位于三个电容并联的结构的相对的两侧，第二极板的第一部分、第一极板的第一部分、第二极板的第二部分、以及第一极板的第二部分依次设置以形成三个电容并联的结构，转接电极ET与第二极板的第二部分位于同一层并彼此绝缘。例如，如图20B所示，第二极板的第一部分、第一极板的第一部分、第二极板的第二部分、以及第一极板的第二部分依次形成。例如，如图20B所示，转接电极ET与第二极板Cb的第二部分Cb2位于同一层并彼此间隔以彼此绝缘。
例如，如图3和图16所示，第一输出晶体管T10的栅极与第二电容C2的第二极C2b的第二部分C2b2电连接，第一输出晶体管T10的第一极与第一电源线VGL的第一部分VGLa电连接，第一输出晶体管T10的第二极与驱动信号输出端电连接。例如，如图3、图16和图18所示，第二输出晶体管T9的栅极与第三电容C3的第一极板C3a的第一部分C3a1通过转接电极ET7电连接。
如图3、图15和图18所示，第二输出晶体管T9的第一极通过过孔与驱动信号输出端EOUT1电连接，第二输出晶体管T9的第二极与第三电容C3的第二极板C3b的第一部分C3b1通过转接电极ET9相连，进而与连接走线L4相连，进而与第二时钟信号线ECB2电连接。第三电容C3的第二极板C3b 的第一部分C3b1与第二时钟信号线ECB2的第一部分ECB2a电连接。第三电容C3在衬底基板上的正投影与第二输出晶体管T9在衬底基板上的正投影相邻。例如，第三电容C3与第二输出晶体管T9相邻设置，以便于信号传递。
例如，如图20B所示，第一极板Ca的第二部分Ca2的面积小于或等于贯穿第五绝缘层IL5的过孔H0的面积，以最大限度的减小电容的极板之间的距离，增大电容量。例如，第一极板Ca的第二部分Ca2在衬底基板10上的正投影完全落入贯穿第五绝缘层IL5的过孔H0在衬底基板10上的正投影内。
例如，如图3和图15所示，移位寄存器单元100aa还包括第一控制晶体管T12、第二控制晶体管T1和第一隔离晶体管T13；第一控制晶体管T12的栅极与第二时钟信号线ECB2通过过孔电连接，第一控制晶体管T12的第一极通过转接电极ETI与输入端EI电连接；第二控制晶体管T1的栅极与第三时钟信号线ECK通过过孔电连接，第二控制晶体管T1的第一极与第一控制晶体管T12的第二极通过转接电极ET12电连接，第二控制晶体管T1的第二极与第一隔离晶体管T13的第二极通过转接电极ET1电连接，第一隔离晶体管T13的第一极与第一电容C1的第二极板通过转接电极ET13电连接，第一隔离晶体管T13的栅极与第一电源线VGL的第一部分VGLa通过过孔电连接。例如，转接电极ET13的第二端与第一隔离晶体管T13的第一极相连。
例如，为了便于缩小GOA宽度和便于信号传输，第一控制晶体管T12靠近第二时钟信号线ECB2设置，第一控制晶体管T12在衬底基板上的正投影和第二时钟信号线ECB2在衬底基板上的正投影位于第二输出晶体管T9在衬底基板上的正投影的同一侧。例如，如图3所示，第一控制晶体管T12和第二时钟信号线ECB2位于第二输出晶体管T9的同一侧。在图3中，第一控制晶体管T12和第二时钟信号线ECB2均位于第二输出晶体管T9的左侧。
例如，第二时钟信号线ECB2在衬底基板上的正投影、第一控制晶体管T12在衬底基板上的正投影、以及第二输出晶体管T9在衬底基板上的正投影沿第二方向X依次排列。例如，如图3所示，第二时钟信号线ECB2、第一控制晶体管T12、以及第二输出晶体管T9沿第二方向X依次排列。
例如，如图3所示，第二时钟信号线ECB2、第一控制晶体管T12、第一电容C1、第二电容C2、以及第二输出晶体管T9沿第二方向X依次排列。
例如，如图3所示，第二时钟信号线ECB2、第一控制晶体管T12、第四电容C4、第三电容C3、以及第二输出晶体管T9沿第二方向X依次排列。
例如，如图3和图21所示，移位寄存器单元100aa还包括第三控制晶体管T3、第四控制晶体管T2和第二隔离晶体管T14。第三控制晶体管T3的栅极与第三时钟信号线ECK通过过孔电连接，第三控制晶体管T3的第一极与第一电源线VGL通过转接电极ET3(如图16所示)以及导线M3电连接，第三控制晶体管T3的第二极通过转接电极ET14(如图16所示)与第四控制晶体管T2的第二极电连接；第四控制晶体管T2的栅极与连接走线L5电连接，进而与转接电极ET1电连接，连接走线L5和/或转接电极ET1可作为第一隔离节点P31，第四控制晶体管T2的第一极与第三时钟信号线ECK通过转接电极ET2以及第三控制晶体管T3的栅极电连接，第四控制晶体管T2的第二极与第三控制晶体管T3的第二极通过转接电极ET14电连接；第二隔离晶体管T14的栅极与第一电源线VGL通过转接电极ET3以及导线M3电连接，第二隔离晶体管T14的第一极与第四控制晶体管T2的第二极通过转接 电极ET14电连接，第二隔离晶体管T14的第二极与转接电极ETa相连。
例如，参考图3、图16和图21，移位寄存器单元100aa还包括第五控制晶体管T6、第六控制晶体管T7、第七控制晶体管T8和第四电容C4。第四电容C4的第一极板与转接电极ETa电连接，进而与第二隔离晶体管T14的第二极相连。第五控制晶体管T6的栅极G6通过转接电极ETa与第四电容C4的第一极板C4a(第一极板C4a的第一部分C4a1以及第二部分C4a2)电连接，第五控制晶体管T6的第一极与第四电容C4的第二极板C4b通过转接电极ETd电连接，第五控制晶体管T6的第二极通过转接电极ET6和导线M1与第一时钟信号线ECB电连接；第六控制晶体管T7的栅极G7通过转接电极ET6和导线M1与第一时钟信号线ECB电连接，第六控制晶体管T7的第一极与第四电容C4的第二极板通过转接电极ETd电连接，第六控制晶体管T7的第二极通过转接电极ET7与第三电容C3的第一极板C3a电连接；第七控制晶体管T8的栅极G8通过连接走线L5和转接电极ET1与第二控制晶体管T1的第二极电连接，第七控制晶体管T8的第一极与第二电源线VGH通过转接电极ET8、导线M2和转接电极ETb电连接，第七控制晶体管T8的第二极通过转接电极ET7与第三电容C3的第一极板C3a电连接。
例如，如图3所示，为了减小显示基板的边框，第四电容C4与第五控制晶体管T6、第六控制晶体管T7相邻设置。第四电容C4在衬底基板上的正投影与第五控制晶体管T6在衬底基板上的正投影相邻，第四电容C4在衬底基板上的正投影与第六控制晶体管T7在衬底基板上的正投影相邻。第四电容C4靠近第五控制晶体管T6和第六控制晶体管T7设置，便于信号的传递。
例如，如图3所示，第四电容C4与第五控制晶体管T6、第六控制晶体管T7的中心连线构成钝角三角形。例如，第四电容C4的中心包括第四电容C4的第一极板C4a的中心或者第二极板C4b的中心。例如，第五控制晶体管T6的中心包括有源层A6的中心，第六控制晶体管T7的中心包括有源层A7的中心。在本公开的实施例中，晶体管的中心可指该晶体管的有源层的中心，电容的中心可指其任一极板的中心。例如，元件的中心可以指该元件的几何中心。
例如，如图3所示，第五控制晶体管T6和第六控制晶体管T7沿第二方向X排列，第五控制晶体管T6和第六控制晶体管T7位于第四电容C4的同一侧。如图3所示，第五控制晶体管T6和第六控制晶体管T7位于第四电容C4的下侧。如图3所示，连接走线L4位于第四电容C4的上侧，则，第五控制晶体管T6和第六控制晶体管T7、以及连接走线L4分设在第四电容C4的相对的两侧。
例如，如图3所示，第五控制晶体管T6和第六控制晶体管T7均位于第七控制晶体管T8和第四电容C4之间。
例如，如图3所示，为了提高排版密度，第五控制晶体管T6、第六控制晶体管T7和第七控制晶体管T8位于第一电容C1、第二电容C2和第四电容C4围绕的区域内。
例如，如图3所示，为了提高排版密度，第五控制晶体管T6、第六控制晶体管T7和第七控制晶体管T8位于第一电容C1、第二电容C2、第三电容C3和第四电容C4围绕的区域内。
例如，如图3所示，第一电容C1和第三电容C3在第二方向X上排列，第二电容C2和第四电容C4在第一方向Y上排列，第二电容C2位于第一电容C1和第三电容C3之间，第四电容C4位于第一电容C1和第三电容C3之间。
例如，如图3所示，为了利于第一晶体管T5的设置，即，将第一晶体管T5设置在第一电容C1 和第二电容C2之间，第三电容C3到第二电容C2之间的在第二方向X上的距离小于第一电容C1到第二电容C2之间的在第二方向X上的距离。
例如，如图3所示，为了利于布线，第三电容C3到第四电容C4之间的在第二方向X上的距离大于第一电容C1到第四电容C4之间的在第二方向X上的距离。
图22为图2B中所示的移位寄存器单元100a在显示基板中的一种布局示意图。图23至图29为图22所示的显示基板的各层布线或者过孔的平面图。图30至图37为图22所示的显示基板中的多个膜层的平面图。图38为图22的沿线A-B的剖视图。图39为图22的沿线E1-F1、E2-F2、或E4-F4的剖视图。图40为图22的沿线E3-F3的剖视图。图41为图22所示的显示基板中各个连接走线、转接电极、导线的设置位置的示意图。图23为本公开至少一实施例提供的显示基板的有源层的平面图，图24为本公开至少一实施例提供的显示基板的第一导电层的平面图，图25为本公开至少一实施例提供的显示基板的第二导电层的平面图，图26为本公开至少一实施例提供的显示基板的贯穿第一绝缘层、第二绝缘层和第三绝缘层至少之一的过孔的分布图，图27为本公开至少一实施例提供的显示基板的第三导电层的平面图，图28为本公开至少一实施例提供的显示基板的贯穿第四绝缘层和第五绝缘层的过孔的分布图，图29为本公开至少一实施例提供的显示基板的贯穿第四绝缘层(第一平坦化层)的过孔的分布图。图30为本公开至少一实施例提供的显示基板的半导体层LY0和贯穿层间绝缘层ILD(第一绝缘层IL1、第二绝缘层IL2和第三绝缘层IL3)的过孔的叠层示意图。图31为本公开至少一实施例提供的显示基板的第一导电层LY1、贯穿层间绝缘层ILD的过孔的叠层示意图。图32为本公开至少一实施例提供的显示基板的第二导电层LY2、贯穿层间绝缘层ILD的过孔的叠层示意图。图33为本公开至少一实施例提供的显示基板的半导体层LY0、贯穿层间绝缘层ILD的过孔、以及第三导电层LY3的叠层示意图。图34为本公开至少一实施例提供的显示基板的第一导电层LY1、贯穿层间绝缘层ILD的过孔、以及第三导电层LY3的叠层示意图。图35为本公开至少一实施例提供的显示基板的第二导电层LY2、贯穿层间绝缘层ILD的过孔、以及第三导电层LY3的叠层示意图。图36为本公开至少一实施例提供的显示基板的第四导电层LY4、贯穿第四绝缘层和第五绝缘层的过孔的叠层示意图。图37为本公开至少一实施例提供的显示基板的第三导电层LY3、贯穿第四绝缘层和第五绝缘层的过孔、以及第四导电层LY4的叠层示意图。
例如，如图22所示，一部分时钟信号线和第一电源线VGL位于移位寄存器单元100ab的一侧，另一部分时钟信号线和第二电源线VGH位于移位寄存器单元100aa的另一侧。
例如，为了减小第一控制晶体管T12的栅极和第二输出晶体管T9的第二极之间的连线长度，且减小第一控制晶体管T12与第二时钟信号线ECB2/第四时钟信号线ECK2的连线的长度，以有利于第二时钟信号线ECB2/第四时钟信号线ECK2上负载的降低，进而降低GOA的功耗，如图22所示，第一控制晶体管T12靠近或相邻第二输出晶体管T9设置，第一控制晶体管T12和第二时钟信号线ECB2位于第二输出晶体管T9的相对的两侧。例如，第一控制晶体管T12在衬底基板上的正投影和第二时钟信号线ECB2在衬底基板上的正投影位于第二输出晶体管T9在衬底基板上的正投影的相对的两侧。
例如，如图22所示，第一控制晶体管T12、第二输出晶体管T9以及第二时钟信号线ECB2沿第二方向X依次排列。例如，如图22所示，第一控制晶体管T12在衬底基板上的正投影、第二输出晶体管T9在衬底基板上的正投影、以及第二时钟信号线ECB2在衬底基板上的正投影沿第二方向X依 次排列。例如，如图22所示，第二控制晶体管T1在衬底基板上的正投影、第一控制晶体管T12在衬底基板上的正投影、第二输出晶体管T9在衬底基板上的正投影、以及第二时钟信号线ECB2在衬底基板上的正投影沿第二方向X依次排列。例如，如图22所示，第二控制晶体管T1在衬底基板上的正投影、第二电容C2在衬底基板上的正投影、第一控制晶体管T12在衬底基板上的正投影、第二输出晶体管T9在衬底基板上的正投影、以及第二时钟信号线ECB2在衬底基板上的正投影沿第二方向X依次排列。
例如，如图22所示，第一控制晶体管T12、第二控制晶体管T1和第一隔离晶体管T13的中心连线构成锐角三角形。
例如，如图22所示，第一控制晶体管T12的中心、第一节点控制晶体管T11的中心、以及第七控制晶体管T8的中心的连线构成锐角三角形。例如，如图22所示，第一控制晶体管T12在衬底基板上的正投影的中心、第一节点控制晶体管T11在衬底基板上的正投影的中心、以及第七控制晶体管T8在衬底基板上的正投影的中心构成锐角三角形。例如，如图22所示，第一控制晶体管T12、第一节点控制晶体管T11、以及第七控制晶体管T8彼此相邻设置。第一控制晶体管T12在衬底基板上的正投影、第一节点控制晶体管T11在衬底基板上的正投影、以及第七控制晶体管T8在衬底基板上的正投影彼此相邻设置。
例如，如图22所示，第一控制晶体管T12在衬底基板上的正投影位于第二输出晶体管T9在衬底基板上的正投影和第一节点控制晶体管T11在衬底基板上的正投影之间。
例如，如图22所示，第一节点控制晶体管T11在衬底基板上的正投影以及第七控制晶体管T8在衬底基板上的正投影沿第一方向Y排列，第一节点控制晶体管T11在衬底基板上的正投影以及第二输出晶体管T9在衬底基板上的正投影沿第二方向X排列。
例如，如图22所示，第三电容C3在衬底基板上的正投影位于第二输出晶体管T9在衬底基板上的正投影以及第二电源线VGH在衬底基板上的正投影之间。
图22所示的显示基板与图3所示的显示基板相比，各个时钟信号线、第一电源线VGL、第二电源线VGL均没有采用两层金属结构并联的方式，且第一电容C1、第二电容C2、第三电容C3、第四电容C4均没有采用三个电容并联的方式。如图24所示，第一导电层LY1设置导线M1和导线M2，与图3所示的显示基板相比，第一导电层LY1没有设置导线M3。如图27所示，第三导电层LY3设置有转接电极ET3m、转接电极ET0、以及转接电极ET121，当然，图27还示出了转接电极ET1、转接电极ET3-ET14、转接电极ET5a、转接电极ETI、转接电极ETa、转接电极ETc以及转接电极ETd等。如图29所示，第四导电层LY4设置有转接电极ET122和转接电极ETbm。例如，转接电极ET5a与第一晶体管T5的第一极相连并一体形成。换句话说，转接电极ET5a的至少一部分充当第一晶体管T5的第一极。转接电极ET3m相当于整合了图3所示的显示基板中的转接电极ET3和导线M3的功能。转接电极ETbm相当于整合了图3所示的显示基板中的转接电极ETb和导线M2的功能。
参考图37，转接电极ET0与转接电极ET121通过转接电极ET122相连。换句话说，转接电极ET122的第一端与转接电极ET121相连，转接电极ET122的第二端与转接电极ET0相连。例如，参考图37，转接电极ET121与第一控制晶体管T12的第二极相连并一体形成，换句话说，转接电极ET121的至少一部分充当第一控制晶体管T12的第二极。例如，参考图37，转接电极ET0与晶体管T1的第一极相 连并一体形成，换句话说，转接电极ET0的至少一部分充当晶体管T1的第一极。即，图22所示的显示基板中的转接电极ET0、转接电极ET121以及转接电极ET122可与图3所示的显示基板中的转接电极ET12所起的作用相同。参考图37，第二电源线VGH通过转接电极ETbm与转接电极ET8相连。
例如，图22所示的电容(包括第一电容C1、第二电容C2、第三电容C3、第四电容C4)均采用第一极板和第二极板相对设置其间夹设绝缘层的方式形成。图32和图35示出了第一电容C1的第一极板C1a、第二电容C2的第一极板C2a、第三电容C3的第二极板C3b、以及第四电容C4的第一极板C4a。图31示出了第一电容C1的第二极板C1b、第二电容C2的第二极板C2b、第三电容C3的第一极板C31、以及第四电容C4的第二极板C4b。因图22所示的显示基板中的第一电容C1、第二电容C2、第三电容C3、第四电容C4没有采用多个电容并联的方式，所以在描述其连接结构时，将图3所示的显示基板中的电容的第一极板Ca的第一部分Ca1和第二部分Ca2均替换为第一极板Ca，第二极板Cb的第一部分Cb1和第二部分Cb2均替换为第二极板Cb即可。
参考图35和图41，第一电容C1的第一极板C1a与转接电极ET4通过过孔相连，第二电容C2的第一极板C2a与转接电极ETc通过过孔相连，第三电容C3的第二极板C3b与第二时钟信号线ECB2通过过孔相连，第四电容C4的第一极板C4a与转接电极ETa通过过孔相连。参考图35，第三电容C3的第二极板C3b与转接电极ET9通过过孔相连。输出端EOUT1与转接电极ET10通过过孔相连。
图34所示的其余转接电极的连接方式和作用可参照图3所示的各个转接电极的连接方式和作用。
图22所示的显示基板与图3所示的显示基板相比，调整了晶体管T12的位置，进而调整了部分布线设计，参考图34，晶体管T12的栅极G12与转接电极ET9通过过孔相连，进而与第三电容C3的第二极板C3b相连，进而连接至第二时钟信号线ECB2。
参考图5、图22和图38，转接电极ET5a也可称作导电部CP，图38示出了第一晶体管T5的栅极G5以及第一晶体管T5的沟道CNL，第一晶体管T5的栅极G5和第一晶体管T5的沟道CNL在第三方向Z上部分交叠。第三方向Z为垂直于衬底基板10的方向。
例如，如图3和图22所示，第一晶体管T5的栅极与第一晶体管T5的第一极通过导电部CP(转接电极ET5a)相连以形成二极管结构。如图22和图38所示，导电部CP通过第一过孔H1与第一晶体管T5的有源层A5相连。如图5和图22所示，第一晶体管T5的沟道CNL在衬底基板10上的正投影与第一过孔H1在衬底基板10上的正投影不交叠，以避免形成过孔的过程中对第一晶体管T5的沟道产生破坏作用，可有效实现二极管连接的第一晶体管T5的电流单向流通功能，有效去除保持阶段的噪声干扰。
如图22和图38所示，导电部CP通过第二过孔H2与第一晶体管T5的栅极G5相连，第一晶体管T5的沟道CNL在衬底基板10上的正投影与第二过孔H2在衬底基板10上的正投影不交叠，以避免形成过孔的过程中对第一晶体管T5的沟道产生破坏作用。
参考图22和图39，电容C包括第一极板Ca和第二极板Cb，转接电极ET01与第一极板Ca相连，转接电极ET02与第二极板Cb相连，第二极板Cb位于第二导电层LY2，第一极板Ca位于第一导电层LY1，转接电极ET01和转接电极ET02位于第二导电层LY3。第一极板Ca和第二极板Cb相对设置，其间夹设有介电层，从而形成电容，电容C可为第一电容C1、第二电容C2和第四电容C4至少之一。
参考图22和图39，对于第一电容C1，第一极板Ca为第一极板C1a，第二极板Cb为第二极板C1b，转接电极ET01为转接电极ET4，转接电极ET02为转接电极ET5a。
参考图22和图39，对于第二电容C2，第一极板Ca为第一极板C2a，第二极板Cb为第二极板C2b，转接电极ET01为转接电极ETc，转接电极ET02为转接电极ET5。
参考图22和图39，对于第四电容C4，第一极板Ca为第一极板C4a，第二极板Cb为第二极板C4b，转接电极ET01为转接电极ETa，转接电极ET02为转接电极ETd。
参考图22和图39，对于第一电容C1、第二电容C2和第四电容C4，第一极板C1a、第一极板C2a和第一极板C4a位于第二导电层LY2，第二极板C1b、第二极板C2b和第二极板C4b位于第一导电层LY1。
参考图22和图40，对于第三电容C3，第一极板C3a位于第一导电层LY1，第二极板C3b位于第二导电层LY2。第一极板C3a和第二极板C3b彼此正对且其间夹设介电层，从而形成电容。
参考图22、图39和图40，第二极板C1b、第二极板C2b、第一极板C3a和第二极板C4b位于第一导电层LY1；第一极板C1a、第一极板C2a、第二极板C3b和第一极板C4a位于第二导电层LY2。
如图22和图34示，第一电容C1在衬底基板10上的正投影和第一晶体管T5在衬底基板10上的正投影部分交叠，并且第二电容C2在衬底基板10上的正投影与第一晶体管T5在衬底基板10上的正投影部分交叠。
例如，如图22所示，第四电容C4与第五控制晶体管T6、第六控制晶体管T7的中心构成锐角三角形。
例如，如图3和图22所示，为了减小边框，第三控制晶体管T3、第四控制晶体管T2和第二隔离晶体管T14沿第二方向X依次排列，第三控制晶体管T3在衬底基板上的正投影与第四控制晶体管T2在衬底基板上的正投影相邻，第二隔离晶体管T14在衬底基板上的正投影与第四控制晶体管T2在衬底基板上的正投影相邻。
例如，该显示基板还包括栅极驱动电路(图中未示出)和触发信号线。例如，触发信号线被配置为向栅极驱动电路提供触发信号，触发信号线在衬底基板10上的正投影位于第二时钟信号线ECB2在衬底基板10上的正投影远离显示区102的一侧。例如，该栅极驱动电路为前面所述的发光控制驱动电路阵列(EM GOA)，其包括多个级联的移位寄存器单元100aa或者包括多个级联的移位寄存器单元100ab，从而可以逐行输出发光控制信号。
例如，触发信号线与栅极驱动电路的第一级移位寄存器单元的晶体管T12的第一极连接以提供触发信号。具体介绍可参考前面的描述，在此不再赘述。
例如，在本公开一些实施例中，各层走线的线宽例如一般为3微米，位于同层的走线之间的间距例如大于3微米。例如，该走线间距例如与曝光机的精度有关，曝光机的精度越高，间距可以越小，具体可根据实际情况确定，本公开的实施例对此不作限制。在本公开的实施例中，同层的走线之间须留有必要的间距，以避免在实际工艺中导致走线粘连、信号短路等。
第一导电层LY1的各条走线在衬底基板10上的正投影和第二导电层LY2的各条走线在衬底基板10上的正投影之间的间距例如一般为1.5微米，例如，第一导电层LY1中的晶体管的栅极要超出其在半导体层LY0上的有源层例如2微米以上。例如，如图3所示，晶体管T2的“U”型双栅极在第一方 向Y上在晶体管T2的有源层的两侧均超出晶体管T2的有源层例如2微米以上，例如，不与晶体管T2的有源层重叠的部分在第一方向Y上的长度为2微米以上，本公开的实施例对此不作限制。
例如，半导体层LY0上各个晶体管的有源层在衬底基板10上的正投影与第一导电层LY1上的各条栅极走线在衬底基板10上的正投影之间的间距为1.5微米以上，从而可以避免栅极走线与半导体层LY0上各个晶体管的有源层之间产生沟道效应。例如，半导体层LY0在衬底基板10上的正投影与第二导电层LY2在衬底基板10上的正投影之间的间距可以无限制，例如可以重叠设置。例如，在本公开的一些实施例中，不同层走线之间尽可能保留一定间距(此间距小于同层走线间距)，由此可减少不必要的交叠，以减弱或避免寄生电容过大产生窜扰。
例如，第三导电层LY3的各条走线的宽度要包住(例如完全覆盖住)其对应的过孔，例如，可以超过过孔的尺寸(例如，过孔的直径)1微米以上，例如，过孔的尺寸为2.0微米～2.5微米，第三导电层LY3的包住过孔的各条走线的宽度为4微米～5微米。例如，第一输出晶体管T10和输出晶体管T9的与过孔对应的走线线宽为上下超过过孔1微米，例如为4.0微米～4.5微米。因为第一输出晶体管T10和输出晶体管T9对应的过孔较多，而连接其他晶体管的位于第三导电层LY3的走线的宽度只需要在过孔位置满足包住过孔超过1微米的要求即可，例如，过孔之间的走线宽度可以细一点。
例如，位于第三导电层LY3的第一时钟信号线ECB、第二时钟信号线ECB2、第三时钟信号线ECK、第四时钟信号线ECK2、第一电源线VGL、第二电源线VGH等走线之间的间距为3微米以上，第一时钟信号线ECB和第二时钟信号线ECB2、第三时钟信号线ECK、以及第四时钟信号线ECK2为了满足驱动能力要求其线宽设置在4微米以上。例如，各时钟信号线的线宽为4-10微米。进一步例如，各时钟信号线的线宽为8微米或10微米。第一电源线VGL的线宽为6、9或10微米都可以，第二电源线VGH的线宽例如为10微米，第一电源线VGL提供的第一电源电压例如一般为-7V。
例如，在一些示例中，第一导电层LY1和第二导电层LY2的厚度为2000～3000埃，第三导电层LY3和第四导电层LY4的厚度为5000～8000埃，本公开的实施例对此不作限制。
例如，通过设置上述转接电极、导线和连接走线，可以减弱或避免同一层的走线密集而导致的走线粘连、信号短路等问题。例如，上述各个转接电极、导线和连接走线可以起连接或跳线连接的作用。
本公开上述实施例提供的显示基板优化了移位寄存器单元的线路连接和结构布局，在一定程度上压缩了移位寄存器单元在第一方向上或第二方向上的长度，进而减小了移位寄存器单元的尺寸，有利于利用该显示基板实现窄边框设计，同时保证了利用该显示基板所达到的显示质量。
需要说明的是，图22所示的显示基板中的任一电容也可以采用图3所示的显示基板中的任一电容采用的并联的设计方式。例如，对于输出晶体管T9,T10，为了增强这两个TFT的输出能力，可以增大第二电容C2、第三电容C3的电容量，例如，图22所示的显示基板中的第二电容C2和第三电容C3至少之一设计为并联电容。
图21示出了图3所示的显示基板中的各个转接电极、各个连接走线，各条导线的设置位置示意图。图41示出了图22所示的显示基板中的各个转接电极、各个连接走线，各条导线的设置位置示意图。如图3、图22、图21和图41所示，图22所示的显示基板与图3所示的显示基板相比，没有设置连接走线L4，没有设置导线M2也没有设置导线M3。图22所示的显示基板与图3所示的显示基板相同之处在于：设置了连接走线L1-L3以及连接走线L5；并设置了导线M1。对于转接电极所在的层，图3 所示的显示基板中的转接电极ET12被图22所示的显示基板中的转接电极ET121、转接电极ET122、以及转接电极ET0合在一起的结构的功能所替代；图3所示的显示基板中的一体结构的转接电极ET5、转接电极ET11和第二电极的第二极板C2b被图22所示的显示基板中的分别设置的转接电极ET5、转接电极ET11和第二电极的第二极板C2b的合在一起的结构的功能所替代；图3所示的显示基板中的转接电极ETb被图22所示的显示基板中的转接电极ETbm替代。
在图41中，浅色虚线框(箭头起始位置处)内的是图3所示的显示基板中的元件，该元件被深色虚线框(箭头终止位置处)内的元件替换，以形成图22所示的显示基板。实线框内的元件为图22所示的显示基板中没有设置而在图3所示的显示基板中设置的元件。
例如，在如图3和图22所示的显示基板中，连接走线L5可被称作第一连接走线，连接走线L1可被称作第二连接走线，连接走线L2可被称作第三连接走线，连接走线L3可被称作第四连接走线，连接走线L4可被称作第五连接走线。如图14和图31所示，在本公开的实施例中，连接走线可以与位于其两端的元件直接相连，也可以说连接走线可以与位于其两端的元件一体形成。
例如，在如图3和图22所示的显示基板中，导线M1可被称作第一导线、导线M2可被称作第二导线，导线M3可被称作第三导线。
为了图示清晰，图3和图22中并未对各个部件均进行标记，各个元件的附图标记可参照图22所示的显示基板中的单层或多层结构中的附图标记。
参照图21和图41以及后续提及的表二，为了便于区分各个转接电极，转接电极ET5a可被称作第一转接电极TR1，转接电极ET5可被称作第二转接电极TR2，转接电极ET4可被称作第三转接电极TR3，转接电极ET13可被称作第四转接电极TR4，转接电极ET6可被称作第五转接电极TR5，转接电极ET11可被称作第六转接电极TR6，转接电极ETc可被称作第七转接电极TR7，转接电极ET10可被称作第八转接电极TR8，转接电极ET7可被称作第九转接电极TR9，转接电极ET9可被称作第十转接电极TR10，转接电极ET8可被称作第十一转接电极TR11，转接电极ETI可被称作第十二转接电极TR12，图3所示的显示基板中的转接电极ET12或者图22所示的显示基板中的转接电极ET121可被称作第十三转接电极TR13，转接电极ET1可被称作第十四转接电极TR14，转接电极ET3可被称作第十五转接电极TR15，转接电极ET14可被称作第十六转接电极TR16，转接电极ET2可被称作第十七转接电极TR17，转接电极ETa可被称作第十八转接电极TR18，转接电极ETd可被称作第十九转接电极TR19。
本公开至少一实施例还提供一种显示装置。图42为本公开至少一实施例提供的一种显示装置的示意图。如图42所示，该显示装置2包括显示基板1，该显示基板1可以为本公开任一实施例提供的显示基板，例如为上述图3或图22中所示的显示基板。
需要说明的是，该显示装置2可以为OLED面板、OLED电视、QLED面板、QLED电视、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置2还可以包括其他部件，例如数据驱动电路、时序控制器等，本公开的实施例对此不作限定。该显示装置2可用于低频GOA的显示装置，但不限于此。
需要说明的是，为表示清楚、简洁，本公开的实施例并没有给出该显示装置2的全部组成单元。为实现该显示装置2的基本功能，本领域技术人员可以根据具体需要提供、设置其他未示出的结构， 本公开的实施例对此不作限制。
关于上述实施例提供的显示装置2的技术效果可以参考本公开的实施例中提供的显示基板(例如上述图2中所示的显示基板)的技术效果，这里不再赘述。
本公开至少一实施例还提供了一种显示基板的制作方法，例如本公开任一实施例提供的显示基板的制作方法。例如，该方法可以用于制作本公开任一实施例提供的显示基板，例如可以用于制作上述图2中所示的显示基板。
例如，该显示基板的制作方法包括步骤S110至步骤S120。
步骤S110：提供衬底基板。
步骤S120：在衬底基板上形成移位寄存器单元、提供第一电源电压的第一电源线、提供第二电源电压的第二电源线、第一时钟信号线、第二时钟信号线、第三时钟信号线和第四时钟信号线。
例如，形成半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、第五绝缘层以及第四导电层分别包括形成对应的材料层(例如，半导体材料层、绝缘材料层或导电材料层)，然后使用构图工艺分别形成对应的图案结构(例如，有源层、电极图案、走线、过孔等)。该构图工艺例如为光刻工艺，例如包括：在需要被构图的材料层上涂覆光刻胶层，使用掩膜板对光刻胶层进行曝光，对曝光的光刻胶层进行显影以得到光刻胶图案，使用光刻胶图案对结构层进行蚀刻，然后可选地去除光刻胶图案。
对于步骤S110，例如，该衬底基板10可以采用例如玻璃、塑料、石英，或其他适合的材料，本公开的实施例对此不作限制。
例如，移位寄存器单元100aa、第一电源线VGL、第二电源线VGH、第一电源线VGL、第一时钟信号线ECB、第二时钟信号线ECB2、第三时钟信号线ECK和第四时钟信号线ECK2形成在衬底基板10上。
对于步骤S120，例如，形成移位寄存器单元100aa包括：在垂直于衬底基板10的方向上依次形成半导体层LY0、第一绝缘层IL1、第一导电层LY1、第二绝缘层IL2、第二导电层LY2、第三绝缘层IL3、第三导电层LY3、第四绝缘层IL4、第五绝缘层IL5以及第四导电层LY4。各个晶体管的有源层位于半导体层LY0，各个晶体管的栅极和各个电容的第二极板的第一部分位于第一导电层LY1，各个电容的第一极板的第一部分位于第二导电层LY2，各个电容的第二极板的第二部分位于第三导电层LY3，各个电容的第一极板的第二部分位于第四导电层LY4，第一电源线VGL的第一部分、第二电源线VGH的第一部分、第一时钟信号线ECB的第一部分、第二时钟信号线ECB2的第一部分、第三时钟信号线ECK的第一部分、第四时钟信号线ECK2的第一部分和各个晶体管的第一极和第二极位于第三导电层LY3。第一电源线VGL的第一部分、第二电源线VGH的第一部分、第一时钟信号线ECB的第二部分、第二时钟信号线ECB2的第二部分、第三时钟信号线ECK的第二部分、第四时钟信号线ECK2的第二部分位于第四导电层LY4。
例如，各个晶体管和各个电容通过贯穿第一绝缘层IL1、第二绝缘层IL2或第三绝缘层IL3的过孔互相连接以及与第一电源线VGL、第二电源线VGH、第一电源线VGL、第一时钟信号线ECB、第二时钟信号线ECB2、第三时钟信号线ECK、和第四时钟信号线ECK2连接。
关于移位寄存器单元100aa的各个晶体管和电容与第二电源线VGH、第一电源线VGL、多条时钟 信号线以及连接走线、导线和转接电极的连接结构等的设置可参考对应附图的相应描述，在此不再赘述。
对于步骤S120，例如，形成移位寄存器单元100ab包括：在垂直于衬底基板10的方向上依次形成半导体层LY0、第一绝缘层IL1、第一导电层LY1、第二绝缘层IL2、第二导电层LY2、第三绝缘层IL3、第三导电层LY3、第四绝缘层IL4、第五绝缘层IL5以及第四导电层LY4。各个晶体管的有源层位于半导体层LY0，各个晶体管的栅极、第一电容C1的第二极板、第二电容C2的第二极板、第四电容C4的第二极板、以及第三电容C3的第一极板位于第一导电层LY1，第一电容C1的第一极板、第二电容C2的第一极板、以及第四电容C4的第一极板、以及第三电容C3的第二极板位于第二导电层LY2，第一电源线VGL、第二电源线VGH、第一时钟信号线ECB、第二时钟信号线ECB2、第三时钟信号线ECK和第四时钟信号线ECK2和各个晶体管的第一极和第二极位于第三导电层LY3。转接电极ET122和转接电极ETbm位于第四导电层LY4。
例如，在本公开的实施例中，形成半导体层LY0包括以第一导电层LY1为掩膜进行掺杂，以使得未被第一导电层LY1的图形覆盖的有源层的部分导体化形成源极区或漏极区，并使得被第一导电层LY1的图形覆盖的有源层的部分保持半导体特性，形成晶体管的沟道。
例如，在本公开的实施例中，形成第一导电层LY1包括形成第一导电薄膜，对第一导电薄膜进行构图以形成第一导电层LY1。
例如，在本公开的实施例中，形成第二导电层LY2包括形成第二导电薄膜，对第二导电薄膜进行构图以形成第二导电层LY2。
在本公开的实施例中，以图3所示的显示基板为例，在第二导电层LY2上形成第三绝缘薄膜，并对第三绝缘薄膜进行构图，在第三绝缘薄膜中形成过孔，以形成第三绝缘层IL3，第三绝缘层IL3中的过孔如图8所示，在第三绝缘层IL3上形成第三导电薄膜，对第三导电薄膜进行构图以形成第三导电层，第三导电层的图形如图9所示。例如，第三导电层的图形中的一些元件可以通过贯穿第三绝缘层IL3、第二绝缘层IL2、以及第一绝缘层IL1中的过孔与半导体层LY0中的对应位置处的元件相连，第三导电层的图形中的一些元件可以通过贯穿第三绝缘层IL3、第二绝缘层IL2中的过孔与第一导电层LY1中的对应位置处的元件相连，第三导电层的图形中的一些元件可以通过贯穿第三绝缘层IL3中的过孔与第二导电层LY2中的对应位置处的元件相连。在第三导电层LY3上形成第四导电薄膜，对第四导电薄膜进行构图以形成第四导电层LY4，第四导电层LY4的图形如图12所示。例如，第四导电层LY4中的元件可以通过贯穿第四绝缘层LY4中的过孔与第三导电层LY3中对应位置处的元件相连。
在本公开的实施例中，半导体层LY0中的元件可以通过过孔与位于第三导电层LY3中的元件相连，第一导电层LY1中的元件可以通过过孔与位于第三导电层LY3中的元件相连，第二导电层LY2中的元件可以通过过孔与位于第三导电层LY3中的元件相连。第三导电层LY3中的元件可以通过过孔与位于第四导电层LY4中的元件相连。
在本公开的实施例中，半导体层LY0中的元件可以通过位于第三导电层LY3中的元件与位于第二导电层LY2中的元件相连，第一导电层LY1中的元件可以通过位于第三导电层LY3中的元件与位于第二导电层LY2中的元件相连。换句话说，半导体层LY0中的元件不直接与位于第二导电层LY2中的元件相连，第一导电层LY1中的元件不直接与位于第二导电层LY2中的元件相连。再换句话说，半 导体层LY0中的元件不直接与位于第二导电层LY2中的元件接触，第一导电层LY1中的元件不直接与位于第二导电层LY2中的元件接触。
需要说明的是，本公开的多个实施例中，该显示基板的制作方法的流程可以包括更多或更少的操作，这些操作可以顺序执行或并行执行。虽然上文描述的制作方法的流程包括特定顺序出现的多个操作，但是应该清楚地了解，多个操作的顺序并不受限制。上文描述的制作方法可以执行一次，也可以按照预定条件执行多次。
关于上述实施例提供的显示基板的制作方法的技术效果可以参考本公开的实施例中提供的显示基板(例如上述图2中所示的显示基板)的技术效果，这里不再赘述。
例如，如后续提及的表三所示，在本公开的实施例中，晶体管T1可被称作第二控制晶体管T1，晶体管T2可被称作第四控制晶体管T2，晶体管T3可被称作第三控制晶体管T3，晶体管T4可被称作第二晶体管T4，晶体管T5可被称作第一晶体管T5，晶体管T6可被称作第五控制晶体管T6，晶体管T7可被称作第六控制晶体管T7，晶体管T8可被称作第七控制晶体管T8，晶体管T9可被称作第二输出晶体管T9，晶体管T10可被称作第一输出晶体管T10，晶体管T11可被称作第一节点控制晶体管T11，晶体管T12可被称作第一控制晶体管T12，晶体管T13可被称作第一隔离晶体管T13，晶体管T14可被称作第二隔离晶体管T14。在对显示基板的移位寄存器单元的布局进行描述时，可能使用各个晶体管的简称。
对于图3和图22所示的显示基板，为了便于对应，以下给出三个表格，以便于对本公开的实施例的理解。
表一 各个节点以及其对应的转接电极
Figure PCTCN2021082769-appb-000001
表二 转接电极ET与转接电极TR的对应关系
Figure PCTCN2021082769-appb-000002
表三 各个晶体管以及其名称
  名称 名称
晶体管T1 第二控制晶体管 第七晶体管
晶体管T2 第四控制晶体管 第十晶体管
晶体管T3 第三控制晶体管 第九晶体管
晶体管T4 第二晶体管 第二晶体管
晶体管T5 第一晶体管 第一晶体管
晶体管T6 第五控制晶体管 第十二晶体管
晶体管T7 第六控制晶体管 第十三晶体管
晶体管T8 第七控制晶体管 第十四晶体管
晶体管T9 第二输出晶体管 第五晶体管
晶体管T10 第一输出晶体管 第四晶体管
晶体管T11 第一节点控制晶体管 第三晶体管
晶体管T12 第一控制晶体管 第六晶体管
晶体管T13 第一隔离晶体管 第八晶体管
晶体管T14 第二隔离晶体管 第十一晶体管
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (35)

  1. 一种显示基板，包括：
    衬底基板；
    设置在所述衬底基板的周边区的移位寄存器单元、第一时钟信号线和第一电源线，所述移位寄存器单元包括电荷泵电路，其中，
    所述第一时钟信号线被配置为向所述移位寄存器单元提供第一时钟信号，
    所述第一电源线被配置为向所述移位寄存器单元提供第一电源电压，
    所述电荷泵电路包括第一电容、第一晶体管和第二电容，所述电荷泵电路分别与第一输入节点和第一节点电连接，
    所述第一电容的第一极板与所述第一时钟信号线相连，所述第一电容的第二极板与所述第一输入节点相连，
    所述第二电容的第一极板与所述第一电源线相连，所述第二电容的第二极板与所述第一节点相连，
    所述第一晶体管的栅极与所述第一晶体管的第一极或第二极相连，
    所述第一电容在所述衬底基板上的正投影和所述第一晶体管在所述衬底基板上的正投影相邻，并且所述第二电容在所述衬底基板上的正投影与所述第一晶体管在衬底基板上的正投影相邻。
  2. 根据权利要求1所述的显示基板，其中，所述电荷泵电路被配置为在第一时间段，在所述第一时钟信号线提供的所述第一时钟信号的控制下，将所述第一输入节点的电位由第一电压信号转换为第二电压信号，并将所述第二电压信号传输至所述第一节点，并被配置为在第二时间段维持所述第一节点的电位。
  3. 根据权利要求2所述的显示基板，其中，所述第一电压信号的电位大于所述第二电压信号的电位。
  4. 根据权利要求1-3任一项所述的显示基板，还包括第一转接电极和第二转接电极，其中，所述第一晶体管的栅极与所述第一晶体管的第一极通过所述第一转接电极相连以形成二极管结构，所述第一转接电极的第一端与所述第一晶体管的第一极相连，所述第一转接电极的第二端与所述第一晶体管的栅极相连，所述第二转接电极的第一端与所述第一晶体管的第二极相连，所述第二转接电极的第二端与所述第二电容的第二极板相连，所述第一晶体管的第一极通过第一过孔与所述第一晶体管的有源层相连，所述第一晶体管的沟道在所述衬底基板上的正投影与所述第一过孔在所述衬底基板上的正投影不交叠。
  5. 根据权利要求4所述的显示基板，其中，所述第一转接电极通过第二过孔与所述第一晶体管的栅极相连，所述第一晶体管的所述沟道在所述衬底基板上的正投影与所述第二过孔在所述衬底基板上的正投影不交叠。
  6. 根据权利要求5所述的显示基板，其中，所述第二过孔在垂直于所述衬底基板的方向上的高度小于所述第一过孔在垂直于所述衬底基板的方向上的高度。
  7. 根据权利要求6所述的显示基板，其中，所述第一过孔贯穿第一绝缘层、第二绝缘层和第三绝缘层，所述第二过孔贯穿所述第二绝缘层和所述第三绝缘层。
  8. 根据权利要求4-7任一项所述的显示基板，其中，所述第一晶体管的所述沟道在所述衬底基板上的正投影与所述第一晶体管的栅极在所述衬底基板上的正投影部分交叠。
  9. 根据权利要求1-8任一项所述的显示基板，其中，所述第一电容的电容值大于或等于所述第二电容的电容值。
  10. 根据权利要求9所述的显示基板，其中，所述第一电容的电容值小于或等于所述第二电容的电容值的十倍。
  11. 根据权利要求9或10所述的显示基板，其中，所述第二电容的电容值的范围为0.01pF-2pF。
  12. 根据权利要求1-11任一项所述的显示基板，其中，所述第一电容和所述第二电容至少之一为三个电容并联的结构，所述三个电容并联的结构包括第二极板的第一部分、第二极板的第二部分、第一极板的第一部分、以及第一极板的第二部分。
  13. 根据权利要求12所述的显示基板，其中，所述第二极板的第一部分和所述第二极板的第二部分通过第三过孔相连，所述第一极板的第一部分和所述第一极板的第二部分通过转接部相连，所述第三过孔和所述转接部分别位于所述三个电容并联的结构的相对的两侧，
    所述第二极板的第一部分、所述第一极板的第一部分、所述第二极板的第二部分、以及所述第一极板的第二部分依次设置以形成所述三个电容并联的结构，
    所述转接部与所述第二极板的第二部分位于同一层并彼此绝缘。
  14. 根据权利要求1-13任一项所述的显示基板，其中，所述第一电容的第二极板在所述衬底基板上的正投影和所述第一晶体管的第一极在所述衬底基板上的正投影部分交叠，并且所述第二电容的第二极板在所述衬底基板上的正投影与所述第一晶体管的第二极在所述衬底基板上的正投影部分交叠。
  15. 根据权利要求1-14任一项所述的显示基板，还包括第一导线和第三转接电极，其中，所述第一导线的第一端与所述第一时钟信号线相连，所述第一导线的第二端与所述第三转接电极的第一端相连，所述第三转接电极的第二端与所述第一电容的第一极板相连。
  16. 根据权利要求15所述的显示基板，还包括第四转接电极和第五转接电极，其中，所述电荷泵电路还包括第二晶体管，所述第四转接电极的第一端与所述第二晶体管的栅极相连，所述第四转接电极的所述第一端与所述第一电容的第二极板相连，所述第五转接电极的第一端与所述第二晶体管的第一极相连，所述第五转接电极的第二端与所述第一导线相连，所述第一导线与所述第一时钟信号线相连，所述第二晶体管的第二极与所述第三转接电极相连。
  17. 根据权利要求1-16任一项所述的显示基板，其中，所述第一时钟信号线在所述衬底基板上沿第一方向延伸，并且所述第一电容、所述第一晶体管和所述第二电容在所述第二方向上依次排布，所述第一方向与所述第二方向相交。
  18. 根据权利要求17所述的显示基板，还包括第六转接电极、第七转接电极、第八转接电极、第九转接电极、第十转接电极、第十一转接电极、第二时钟信号线和第二电源线，其中，所述第二时钟信号线被配置为向所述移位寄存器单元提供第二时钟信号，所述第二电源线被配置为向所述移位寄存器单元提供第二电源电压，所述移位寄存器单元还包括第一节点控制晶体管、第一输出晶体管、第二输出晶体管和第三电容；
    所述第一输出晶体管的栅极与所述第二电容的第二极板通过所述第六转接电极电连接，所述第一 输出晶体管的第一极与所述第一电源线通过所述第七转接电极电连接，所述第一输出晶体管的第二极通过所述第八转接电极与驱动信号输出端电连接；
    所述第二输出晶体管的栅极与所述第三电容的第一极板通过所述第九转接电极电连接，所述第二输出晶体管的第一极与所述驱动信号输出端通过所述第八转接电极电连接，所述第二输出晶体管的第二极与所述第二时钟信号线通过所述第十转接电极电连接；
    所述第三电容的第二极板与所述第二时钟信号线电连接；
    所述第一节点控制晶体管的第一极与所述第二电源线通过所述第六转接电极电连接，所述第一节点控制晶体管的第二极与所述第一节点通过所述第十一转接电极电连接。
  19. 根据权利要求18所述的显示基板，其中，所述第三电容在所述衬底基板上的正投影与所述第二输出晶体管在所述衬底基板上的正投影相邻。
  20. 根据权利要求18或19所述的显示基板，其中，所述第二电源线和所述第一电源线分设在所述移位寄存器单元的两侧。
  21. 根据权利要求20所述的显示基板，其中，所述第二时钟信号线与所述第二电源线位于所述移位寄存器单元的同一侧，或者，所述第二时钟信号线与所述第一电源线位于所述移位寄存器单元的同一侧。
  22. 根据权利要求18-21任一项所述的显示基板，还包括第十二转接电极、第十三转接电极、第十四转接电极、以及第三时钟信号线，其中，所述第三时钟信号线被配置为向所述移位寄存器单元提供第三时钟信号，所述移位寄存器单元还包括第一控制晶体管、第二控制晶体管和第一隔离晶体管；
    所述第一控制晶体管的栅极与所述第二时钟信号线电连接，所述第一控制晶体管的第一极与输入端通过所述第十二转接电极电连接；
    所述第二控制晶体管的栅极与所述第三时钟信号线电连接，所述第二控制晶体管的第一极与所述第一控制晶体管的第二极通过所述第十三转接电极电连接，所述第二控制晶体管的第二极与所述第一隔离晶体管的第二极通过所述第十四转接电极电连接，所述第一隔离晶体管的第一极与所述第一电容的第二极板通过所述第四转接电极电连接，所述第一隔离晶体管的栅极与所述第一电源线电连接。
  23. 根据权利要求22所述的显示基板，其中，所述第一控制晶体管和所述第二时钟信号线位于所述第二输出晶体管的同一侧，或者，所述第一控制晶体管和所述第二时钟信号线位于所述第二输出晶体管的相对的两侧。
  24. 根据权利要求22所述的显示基板，其中，所述第一控制晶体管、所述第二控制晶体管和所述第一隔离晶体管的中心连线构成锐角三角形。
  25. 根据权利要求22-24任一项所述的显示基板，其中，所述第二控制晶体管、所述第一控制晶体管、所述第二输出晶体管以及所述第二时钟信号线沿所述第二方向依次排列。
  26. 根据权利要求22-24任一项所述的显示基板，其中，所述第二控制晶体管、所述第二电容、所述第一控制晶体管、所述第二输出晶体管和所述第二时钟信号线沿所述第二方向依次排列。
  27. 根据权利要求22-26任一项所述的显示基板，还包括第十五转接电极、第十六转接电极、第十七转接电极以及第十八转接电极，其中，所述移位寄存器单元还包括第三控制晶体管、第四控制晶体管和第二隔离晶体管；
    所述第三控制晶体管的栅极与所述第三时钟信号线电连接，所述第三控制晶体管的第一极与所述第一电源线通过所述第十五转接电极电连接；
    所述第四控制晶体管的栅极与所述第二控制晶体管的第二极电连接，所述第四控制晶体管的第一极与所述第三时钟信号线通过所述第十七转接电极电连接，所述第四控制晶体管的第二极与所述第三控制晶体管的第二极通过所述第十六转接电极电连接；
    所述第二隔离晶体管的栅极与所述第一电源线电连接，所述第二隔离晶体管的第一极与所述第四控制晶体管的第二极通过所述第十六转接电极电连接，所述第二隔离晶体管的第二极与所述第十八转接电极相连。
  28. 根据权利要求27所述的显示基板，其中，所述第三控制晶体管、所述第四控制晶体管和所述第二隔离晶体管沿所述第二方向依次排列，所述第三控制晶体管在所述衬底基板上的正投影与所述第四控制晶体管在所述衬底基板上的正投影相邻，所述第二隔离晶体管在所述衬底基板上的正投影与所述第四控制晶体管在所述衬底基板上的正投影相邻。
  29. 根据权利要求27或28所述的显示基板，还包括连接走线和第十九转接电极，其中，所述移位寄存器单元还包括第五控制晶体管、第六控制晶体管、第七控制晶体管和第四电容；
    所述第四电容的第一极与所述第十八转接电极电连接，所述第五控制晶体管的栅极与所述第四电容的第一极板通过所述第十八转接电极电连接，所述第五控制晶体管的第一极与所述第四电容的第二极板通过所述第十九转接电极电连接，所述第五控制晶体管的第二极与所述第一时钟信号线通过所述第五转接电极电连接；
    所述第六控制晶体管的栅极与所述第一时钟信号线通过所述第五转接电极电连接，所述第六控制晶体管的第一极与所述第四电容的第二极板通过所述第十九转接电极电连接，所述第六控制晶体管的第二极与所述第三电容的第一极板通过所述第九转接电极电连接；
    所述第七控制晶体管的栅极与所述第二控制晶体管的第二极通过所述连接走线以及所述第十四转接电极电连接，所述第七控制晶体管的第一极与所述第二电源线通过所述第十一转接电极电连接，所述第七控制晶体管的第二极与所述第二输出晶体管的栅极通过所述第九转接电极电连接；
    所述第一节点控制晶体管的栅极与所述第四电容的第二极板相连。
  30. 根据权利要求29所述的显示基板，其中，所述第五控制晶体管在所述衬底基板上的正投影与所述第四电容在所述衬底基板上的正投影相邻，所述第六控制晶体管在所述衬底基板上的正投影与所述第四电容在所述衬底基板上的正投影相邻。
  31. 根据权利要求29或30所述的显示基板，其中，所述第四电容的中心、所述第五控制晶体管的中心、所述第六控制晶体管的中心构成钝角三角形或锐角三角形。
  32. 根据权利要求29-31任一项所述的显示基板，其中，所述第五控制晶体管和所述第六控制晶体管沿所述第二方向排列，所述第五控制晶体管和所述第六控制晶体管位于所述第四电容的同一侧。
  33. 根据权利要求29-32任一项所述的显示基板，其中，所述第一电容和所述第三电容在所述第一方向上排列，所述第二电容和所述第四电容在所述第二方向上排列，所述第二电容位于所述第一电容和所述第三电容之间，所述第四电容位于所述第一电容和所述第三电容之间。
  34. 根据权利要求33所述的显示基板，其中，所述第三电容到所述第二电容之间的在所述第二方 向上的距离大于所述第一电容到所述第二电容之间的在所述第二方向上的距离。
  35. 一种显示装置，包括根据权利要求1-34任一项所述的显示基板。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080279327A1 (en) * 2007-05-09 2008-11-13 Chunghwa Picture Tubes, Ltd. Shift register and shift register apparatus thereof
CN107784977A (zh) * 2017-12-11 2018-03-09 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN210837103U (zh) * 2019-12-18 2020-06-23 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路以及显示装置
CN111415624A (zh) * 2020-04-29 2020-07-14 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置
WO2020191597A1 (zh) * 2019-03-25 2020-10-01 京东方科技集团股份有限公司 移位寄存器、其驱动方法、栅极驱动电路及显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5291874B2 (ja) * 2005-10-18 2013-09-18 株式会社半導体エネルギー研究所 半導体装置、シフトレジスタ、表示装置
CN208141792U (zh) * 2018-05-28 2018-11-23 北京京东方技术开发有限公司 移位寄存器单元、电路结构、驱动电路及显示装置
CN110010078B (zh) * 2019-03-14 2022-02-08 合肥京东方卓印科技有限公司 移位寄存器单元、栅极驱动电路和显示装置
CN110518022A (zh) * 2019-09-10 2019-11-29 合肥京东方卓印科技有限公司 栅极驱动结构、阵列基板及显示装置
CN110767665B (zh) * 2019-11-29 2022-05-31 京东方科技集团股份有限公司 一种显示面板、其制备方法及显示装置
CN111326558B (zh) * 2020-02-27 2023-11-28 合肥京东方卓印科技有限公司 显示面板和电子装置
CN111508974B (zh) * 2020-04-26 2023-10-17 京东方科技集团股份有限公司 阵列基板及其制作方法、移位寄存器单元、显示面板
CN113823640A (zh) * 2020-05-11 2021-12-21 京东方科技集团股份有限公司 显示基板和显示装置
CN111508433B (zh) * 2020-05-28 2021-08-31 京东方科技集团股份有限公司 信号生成电路、信号生成方法、信号生成模组和显示装置
CN112838109A (zh) * 2020-08-28 2021-05-25 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080279327A1 (en) * 2007-05-09 2008-11-13 Chunghwa Picture Tubes, Ltd. Shift register and shift register apparatus thereof
CN107784977A (zh) * 2017-12-11 2018-03-09 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
WO2020191597A1 (zh) * 2019-03-25 2020-10-01 京东方科技集团股份有限公司 移位寄存器、其驱动方法、栅极驱动电路及显示装置
CN210837103U (zh) * 2019-12-18 2020-06-23 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路以及显示装置
CN111415624A (zh) * 2020-04-29 2020-07-14 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置

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